diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c new file mode 100644 index 0000000..91d248e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.c @@ -0,0 +1,270 @@ +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.50 +* +* \brief +* Provides an API for the Bootloadable application. +* +******************************************************************************** +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "Bootloadable_1.h" + +/** + \defgroup functions_group Functions + @{ +*/ + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + ; +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* Function Name: Bootloadable_1_Load +****************************************************************************//** +* +* \brief +* Schedules the Bootloader/Launcher to be launched and then performs +* a software reset to launch it +* +* \return +* This method will never return. It will load a new application and reset +* the device. +* +*******************************************************************************/ +void Bootloadable_1_Load(void) +{ + /* Schedule Bootloader to start after reset */ + Bootloadable_1_SET_RUN_TYPE(Bootloadable_1_SCHEDULE_BTLDR); + + CySoftwareReset(); +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) +/******************************************************************************* +* Function Name: Bootloadable_1_GetActiveApplication +****************************************************************************//** +* +* \brief +* Gets the application which will be loaded after a next reset event. +* NOTE Intended for the combination project type ONLY! +* +* \return +* A number of the current active application set in the metadata section. +* \n 0 - app#0 is set as active. +* \n 1 - app#1 is set as active. +* +* \note If neither of the applications is set active, then the API returns 0x02. +* +*******************************************************************************/ +uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + +{ + uint8 result = Bootloadable_1_MD_BTLDB_ACTIVE_NONE; + + if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_0))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_0; + } + else if (0u != Bootloadable_1_GET_CODE_DATA( \ + Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(Bootloadable_1_MD_BTLDB_ACTIVE_1))) + { + result = Bootloadable_1_MD_BTLDB_ACTIVE_1; + } + else + { + /*Do nothing, result is none*/ + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_SetActiveApplication +****************************************************************************//** +* +* \brief +* Sets the application which will be loaded after a next reset event. +* +* \details +* Theory: +* This API sets in the Flash (metadata section) the given active application +* number. +* +* NOTE The active application number is not set directly, but the boolean +* mark instead means that the application is active or not for the relative +* metadata. Both metadata sections are updated. For example, if the second +* application is to be set active, then in the metadata section for the first +* application there will be a "0" written, which means that it is not active, and +* for the second metadata section there will be a "1" written, which means that it is +* active. +* +* NOTE Intended for the combination project type ONLY! +* +* \param appId +* The active application number to be written to flash (metadata section) +* NOTE Possible values are: +* 0 - for the first application +* 1 - for the second application. +* Any other number is considered invalid. +* +* \return +* A status of writing to flash operation. +* \n CYRET_SUCCESS - Returned if appId was successfully changed. +* \n CYRET_BAD_PARAM - Returned if the parameter appID passed to the function has the +* same value as the active application ID. +* \note - The other non-zero value is considered as a failure during writing to flash. +* +* \note - This API does not update Bootloader_activeApp variable. +* +*******************************************************************************/ +cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + +{ + cystatus result = CYRET_SUCCESS; + + uint8 CYDATA idx; + + /* If invalid application number */ + if (appId > Bootloadable_1_MD_BTLDB_ACTIVE_1) + { + result = CYRET_BAD_PARAM; + } + else + { + /* If appID has same value as active application ID */ + if (1u == Bootloadable_1_GET_CODE_DATA(Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId))) + { + result = CYRET_BAD_PARAM; + } + else + { + /* Updating metadata section */ + for(idx = 0u; idx < Bootloadable_1_MAX_NUM_OF_BTLDB; idx++) + { + result |= Bootloadable_1_WriteFlashByte((uint32) Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(idx), \ + (uint8)(idx == appId)); + } + } + } + + return (result); +} + +/******************************************************************************* +* Function Name: Bootloadable_1_WriteFlashByte +****************************************************************************//** +* +* \brief +* This API writes to flash the specified data. +* +* \param address +* The address in flash. +* +* \param inputValue +* One-byte data. +* +* \return +* A status of the writing to flash procedure. +* +*******************************************************************************/ +static cystatus Bootloadable_1_WriteFlashByte(const uint32 address, const uint8 inputValue) CYLARGE \ + +{ + cystatus result = CYRET_SUCCESS; + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = (uint8)Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = inputValue; + + #if(CY_PSOC4) + result = CySysFlashWriteRow((uint32) rowNum, rowData); + #else + result = CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ + return (result); +} +#endif /*(CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ +/** @} functions_group */ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +*******************************************************************************/ +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + + for (idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = Bootloadable_1_GET_CODE_DATA(baseAddr + idx); + } + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32) rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing to flash, data in the instruction cache can become obsolete. + * Therefore, the cache data does not correlate to the data just written to + * flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h new file mode 100644 index 0000000..40e7f27 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Bootloadable_1.h @@ -0,0 +1,200 @@ +/****************************************************************************//** +* \file Bootloadable_1.c +* \version 1.50 +* +* \brief +* Provides an API for the Bootloadable application. The API includes a +* single function for starting the Bootloader. +* +******************************************************************************** +* \copyright +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#ifndef CY_BOOTLOADABLE_Bootloadable_1_H +#define CY_BOOTLOADABLE_Bootloadable_1_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Bootloadable_v1_50 requires cy_boot v3.0 or later +#endif /* !defined (CY_PSOC5LP) */ + + +#ifndef CYDEV_FLASH_BASE + #define CYDEV_FLASH_BASE CYDEV_FLS_BASE + #define CYDEV_FLASH_SIZE CYDEV_FLS_SIZE +#endif /* CYDEV_FLASH_BASE */ + +#if(CY_PSOC3) + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) +#else + #define Bootloadable_1_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This variable is used by the Bootloader/Bootloadable components to schedule which +* application will be started after a software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Gets the reason for a device reset +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_RES_CAUSE_RESET_SOFT (0x10u) + #define Bootloadable_1_GET_RUN_TYPE \ + (((CY_GET_REG32(CYREG_RES_CAUSE) & Bootloadable_1_RES_CAUSE_RESET_SOFT) > 0u) \ + ? (cyBtldrRunType) \ + : 0u) +#else + #define Bootloadable_1_GET_RUN_TYPE (CY_GET_REG8(CYREG_RESET_SR0) & \ + (Bootloadable_1_START_BTLDR | Bootloadable_1_START_APP)) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule the Bootloader/Bootloadable to be run after a software reset. +*******************************************************************************/ +#if(CY_PSOC4) + #define Bootloadable_1_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define Bootloadable_1_SET_RUN_TYPE(x) CY_SET_REG8(CYREG_RESET_SR0, (x)) +#endif /* (CY_PSOC4) */ + + + +/*************************************** +* Function Prototypes +***************************************/ +extern void Bootloadable_1_Load(void) ; + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.10. +*******************************************************************************/ +#define CYBTDLR_SET_RUN_TYPE(x) Bootloadable_1_SET_RUN_TYPE(x) + +/******************************************************************************* +* Bootloadable's declarations for in-app bootloading. +*******************************************************************************/ +#define Bootloadable_1_MD_BTLDB_ACTIVE_0 (0x00u) + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x02u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_1 (0x01u) + #define Bootloadable_1_MD_BTLDB_ACTIVE_NONE (0x02u) + #define Bootloadable_1_MD_SIZEOF (64u) + #define Bootloadable_1_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + Bootloadable_1_MD_SIZEOF)) + #define Bootloadable_1_MD_BTLDB_ACTIVE_OFFSET(appId) (Bootloadable_1_MD_BASE_ADDR(appId) + 16u) + +#else + #define Bootloadable_1_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/* Mask used to indicate starting application */ +#define Bootloadable_1_SCHEDULE_BTLDB (0x80u) +#define Bootloadable_1_SCHEDULE_BTLDR (0x40u) +#define Bootloadable_1_SCHEDULE_MASK (0xC0u) +/******************************************************************************* +* API prototypes +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + uint8 Bootloadable_1_GetActiveApplication(void) CYSMALL \ + ; + cystatus Bootloadable_1_SetActiveApplication(uint8 appId) CYSMALL \ + ; +#endif /* (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)*/ + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from version 1.20 +*******************************************************************************/ +#define Bootloadable_1_START_APP (0x80u) +#define Bootloadable_1_START_BTLDR (0x40u) +#define Bootloadable_1_META_DATA_SIZE (64u) +#define Bootloadable_1_META_APP_CHECKSUM_OFFSET (0u) + +#if(CY_PSOC3) + + #define Bootloadable_1_APP_ADDRESS uint16 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + + /* Offset by 2 from 32 bit start because only 16 bits are needed */ + #define Bootloadable_1_META_APP_ADDR_OFFSET (3u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (7u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (11u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (15u) + +#else + + #define Bootloadable_1_APP_ADDRESS uint32 + #define Bootloadable_1_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + + #define Bootloadable_1_META_APP_ADDR_OFFSET (1u) + #define Bootloadable_1_META_APP_BL_LAST_ROW_OFFSET (5u) + #define Bootloadable_1_META_APP_BYTE_LEN_OFFSET (9u) + #define Bootloadable_1_META_APP_RUN_TYPE_OFFSET (13u) + +#endif /* (CY_PSOC3) */ + +#define Bootloadable_1_META_APP_ACTIVE_OFFSET (16u) +#define Bootloadable_1_META_APP_VERIFIED_OFFSET (17u) + +#define Bootloadable_1_META_APP_BL_BUILD_VER_OFFSET (18u) +#define Bootloadable_1_META_APP_ID_OFFSET (20u) +#define Bootloadable_1_META_APP_VER_OFFSET (22u) +#define Bootloadable_1_META_APP_CUST_ID_OFFSET (24u) + +#define Bootloadable_1_SetFlashRunType(runType) \ + Bootloadable_1_SetFlashByte(Bootloadable_1_MD_APP_RUN_ADDR(0), (runType)) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions are intended for the application, use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* NOTE Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +void Bootloadable_1_SetFlashByte(uint32 address, uint8 runType) ; +#if(CY_PSOC4) + #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset() +#else + #define Bootloadable_1_SOFTWARE_RESET CySoftwareReset() +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + + +#endif /* CY_BOOTLOADABLE_Bootloadable_1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c new file mode 100644 index 0000000..747cacc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.c @@ -0,0 +1,730 @@ +/******************************************************************************* +* File Name: CFG_EEPROM.c +* Version 3.0 +* +* Description: +* Provides the source code to the API for the EEPROM component. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CFG_EEPROM.h" + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Enable +******************************************************************************** +* +* Summary: +* Enable the EEPROM block. Also reads the temperature and stores it for +* future writes. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Enable(void) +{ + /* Read temperature value */ + (void)CySetTemp(); + + /* Start EEPROM block */ + CyEEPROM_Start(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Start +******************************************************************************** +* +* Summary: +* Starts EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Start(void) +{ + CFG_EEPROM_Enable(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Stop +******************************************************************************** +* +* Summary: +* Stops and powers down EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CFG_EEPROM_Stop (void) +{ + /* Stop and power down EEPROM block */ + CyEEPROM_Stop(); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_WriteByte +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This function blocks until +* the function is complete. For a reliable write procedure to occur you should +* call CFG_EEPROM_UpdateTemperature() function if the temperature of the +* silicon has been changed for more than 10C since the component was started. +* +* Parameters: +* dataByte: The byte of data to write to the EEPROM +* address: The address of data to be written. The maximum address is dependent +* on the EEPROM size. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) +{ + cystatus status; + uint16 rowNumber; + uint16 byteNumber; + + CySpcStart(); + + if (address < CY_EEPROM_SIZE) + { + rowNumber = address/(uint16)CY_EEPROM_SIZEOF_ROW; + byteNumber = address - (rowNumber * ((uint16)CY_EEPROM_SIZEOF_ROW)); + if(CYRET_SUCCESS == CySpcLock()) + { + status = CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, byteNumber, &dataByte, \ + CFG_EEPROM_SPC_BYTE_WRITE_SIZE); + if (CYRET_STARTED == status) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + /* Command to erase and program the row. */ + if(CYRET_SUCCESS == status) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + if (CYRET_BAD_PARAM != status) + { + status = CYRET_UNKNOWN; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + + return (status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_ReadByte +******************************************************************************** +* +* Summary: +* Reads and returns a byte of data from the on-chip EEPROM memory. Although +* the data is present in the CPU memory space, this function provides an +* intuitive user interface, addressing the EEPROM memory as a separate block with +* the first EERPOM byte address equal to 0x0000. +* +* Parameters: +* address: The address of data to be read. The maximum address is limited by the +* size of the EEPROM array on a specific device. +* +* Return: +* Data located at an address. +* +*******************************************************************************/ +uint8 CFG_EEPROM_ReadByte(uint16 address) +{ + uint8 retByte; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Request access to EEPROM for reading. + This is needed to reserve PHUB for read operation from EEPROM */ + CyEEPROM_ReadReserve(); + + retByte = *((reg8 *) (CYDEV_EE_BASE + address)); + + /* Release EEPROM array */ + CyEEPROM_ReadRelease(); + + CyExitCriticalSection(interruptState); + + return (retByte); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_UpdateTemperature +******************************************************************************** +* +* Summary: +* Updates and stores the temperature value. This function should be called +* before EEPROM writes if the temperature may have been changed by more than +* 10 degrees Celsius. +* +* Parameters: +* None +* +* Return: +* Status of operation, 0 if operation complete, non-zero value if error +* was detected. +* +*******************************************************************************/ +uint8 CFG_EEPROM_UpdateTemperature(void) +{ + return ((uint8)CySetTemp()); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_EraseSector +******************************************************************************** +* +* Summary: +* Erase an EEPROM sector (64 rows). This function blocks until the erase +* operation is complete. Using this API helps to erase the EEPROM sector at +* a time. This is faster than using individual writes but affects a cycle +* recourse of the whole EEPROM row. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) CFG_EEPROM_SECTORS_NUMBER) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Write +******************************************************************************** +* +* Summary: +* Writes a row (16 bytes) of data to the EEPROM. This function blocks until +* the write operation is complete. Compared to functions that write one byte, +* this function allows writing a whole row (16 bytes) at a time. For +* a reliable write procedure to occur you should call the +* CFG_EEPROM_UpdateTemperature() function if the temperature of the +* silicon has changed for more than 10C since component was started. +* +* Parameters: +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) +{ + cystatus status; + + CySpcStart(); + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_StartWrite +******************************************************************************** +* +* Summary: +* Starts a write of a row (16 bytes) of data to the EEPROM. +* This function does not block. The function returns once the SPC has begun +* writing the data. This function must be used in combination with +* CFG_EEPROM_Query(). CFG_EEPROM_Query() must be called +* until it returns a status other than CYRET_STARTED. That indicates that the +* write has completed. Until CFG_EEPROM_Query() detects that +* the write is complete, the SPC is marked as locked to prevent another +* SPC operation from being performed. For a reliable write procedure to occur +* you should call CFG_EEPROM_UpdateTemperature() API if the temperature +* of the silicon has changed for more than 10C since component was started. +* +* Parameters: +* rowData: The address of the data to write to the EEPROM. +* rowNumber: The row number to write. +* +* Return: +* CYRET_STARTED, if the SPC command to write was successfully started. +* CYRET_BAD_PARAM, if the parameter rowNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* +*******************************************************************************/ +cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + +{ + cystatus status; + + CySpcStart(); + + if(rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcLoadRow(CY_SPC_FIRST_EE_ARRAYID, rowData, CYDEV_EEPROM_ROW_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + status = CYRET_STARTED; + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_StartErase +******************************************************************************** +* +* Summary: +* Starts the EEPROM sector erase. This function does not block. +* The function returns once the SPC has begun writing the data. This function +* must be used in combination with CFG_EEPROM_Query(). +* CFG_EEPROM_Query() must be called until it returns a status +* other than CYRET_STARTED. That indicates the erase has been completed. +* Until CFG_EEPROM_Query() detects that the erase is +* complete, the SPC is marked as locked to prevent another SPC operation +* from being performed. +* +* Parameters: +* sectorNumber: The sector number to erase. +* +* Return: +* CYRET_STARTED, if the SPC command to erase was successfully started. +* CYRET_BAD_PARAM, if the parameter sectorNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +* Side effects: +* After calling this API, the device should not be powered down, reset or switched +* to low power modes until EEPROM operation is complete. +* Ignoring this recommendation may lead to data corruption or silicon +* unexpected behavior. +* +*******************************************************************************/ +cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) +{ + cystatus status; + + CySpcStart(); + + if(sectorNumber < (uint8) CY_EEPROM_NUMBER_ARRAYS) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load a row of data */ + if(CySpcEraseSector(CY_SPC_FIRST_EE_ARRAYID, sectorNumber) == CYRET_STARTED) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_Query +******************************************************************************** +* +* Summary: +* Checks the status of an earlier call to CFG_EEPROM_StartWrite() or +* CFG_EEPROM_StartErase(). +* This function must be called until it returns a value other than +* CYRET_STARTED. Once that occurs, the write or erase has been completed and +* the SPC is unlocked. +* +* Parameters: +* None +* +* Return: +* CYRET_STARTED, if the SPC command is still processing. +* CYRET_SUCCESS, if the operation was completed successfully. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_Query(void) +{ + cystatus status; + + CySpcStart(); + + /* Check if SPC is idle */ + if(CY_SPC_IDLE) + { + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_STARTED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CFG_EEPROM_ByteWritePos +******************************************************************************** +* +* Summary: +* Writes a byte of data to the EEPROM. This is a blocking call. It will not +* return until the write operation succeeds or fails. +* +* Parameters: +* dataByte: The byte of data to write to the EEPROM. +* rowNumber: The EEPROM row number to program. +* byteNumber: The byte number within the row to program. +* +* Return: +* CYRET_SUCCESS, if the operation was successful. +* CYRET_BAD_PARAM, if the parameter rowNumber or byteNumber is out of range. +* CYRET_LOCKED, if the SPC is being used. +* CYRET_UNKNOWN, if there was an SPC error. +* +*******************************************************************************/ +cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + +{ + cystatus status; + + /* Start SPC */ + CySpcStart(); + + if((rowNumber < (uint8) CY_EEPROM_NUMBER_ROWS) && (byteNumber < (uint8) SIZEOF_EEPROM_ROW)) + { + /* See if we can get SPC. */ + if(CySpcLock() == CYRET_SUCCESS) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + /* Command to load byte of data */ + if(CySpcLoadMultiByte(CY_SPC_FIRST_EE_ARRAYID, (uint16)byteNumber, &dataByte,\ + CFG_EEPROM_SPC_BYTE_WRITE_SIZE) == CYRET_STARTED) + { + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + + /* Command to erase and program the row. */ + if(status == CYRET_SUCCESS) + { + if(CySpcWriteRow(CY_SPC_FIRST_EE_ARRAYID, (uint16)rowNumber, dieTemperature[0u], + dieTemperature[1u]) == CYRET_STARTED) + { + /* Plan for failure */ + status = CYRET_UNKNOWN; + + while(CY_SPC_BUSY) + { + /* Wait until SPC becomes idle */ + } + + /* SPC is idle now */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + else + { + status = CYRET_UNKNOWN; + } + } + + /* Unlock SPC so that someone else can use it. */ + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h new file mode 100644 index 0000000..6323d86 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CFG_EEPROM.h @@ -0,0 +1,79 @@ +/******************************************************************************* +* File Name: CFG_EEPROM.h +* Version 3.0 +* +* Description: +* Provides the function definitions for the EEPROM APIs. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_EEPROM_CFG_EEPROM_H) +#define CY_EEPROM_CFG_EEPROM_H + +#include "cydevice_trm.h" +#include "CyFlash.h" + +#if !defined(CY_PSOC5LP) + #error Component EEPROM_v3_0 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void CFG_EEPROM_Enable(void) ; +void CFG_EEPROM_Start(void) ; +void CFG_EEPROM_Stop (void) ; +cystatus CFG_EEPROM_WriteByte(uint8 dataByte, uint16 address) \ + ; +uint8 CFG_EEPROM_ReadByte(uint16 address) ; +uint8 CFG_EEPROM_UpdateTemperature(void) ; +cystatus CFG_EEPROM_EraseSector(uint8 sectorNumber) ; +cystatus CFG_EEPROM_Write(const uint8 * rowData, uint8 rowNumber) ; +cystatus CFG_EEPROM_StartWrite(const uint8 * rowData, uint8 rowNumber) \ + ; +cystatus CFG_EEPROM_StartErase(uint8 sectorNumber) ; +cystatus CFG_EEPROM_Query(void) ; +cystatus CFG_EEPROM_ByteWritePos(uint8 dataByte, uint8 rowNumber, uint8 byteNumber) \ + ; + + +/**************************************** +* API Constants +****************************************/ + +#define CFG_EEPROM_EEPROM_SIZE CYDEV_EE_SIZE +#define CFG_EEPROM_SPC_BYTE_WRITE_SIZE (0x01u) + +#define CFG_EEPROM_SECTORS_NUMBER (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) + +#define CFG_EEPROM_AHB_REQ_SHIFT (0x00u) +#define CFG_EEPROM_AHB_REQ ((uint8)(0x01u << CFG_EEPROM_AHB_REQ_SHIFT)) +#define CFG_EEPROM_AHB_ACK_SHIFT (0x01u) +#define CFG_EEPROM_AHB_ACK_MASK ((uint8)(0x01u << CFG_EEPROM_AHB_ACK_SHIFT)) + + +/*************************************** +* Registers +***************************************/ +#define CFG_EEPROM_SPC_EE_SCR_REG (*(reg8 *) CYREG_SPC_EE_SCR) +#define CFG_EEPROM_SPC_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ +#define CFG_EEPROM_ByteWrite CFG_EEPROM_ByteWritePos +#define CFG_EEPROM_QueryWrite CFG_EEPROM_Query + +#endif /* CY_EEPROM_CFG_EEPROM_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf new file mode 100644 index 0000000..d881592 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf @@ -0,0 +1,160 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2); +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x1000; +define symbol __ICFEDIT_size_heap__ = 0x0400; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_APPL_LOADABLE = 1; +define symbol CY_APPL_LOADER = 0; +define symbol CY_APPL_NUM = 1; +define symbol CY_APPL_MAX = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_CHECKSUM_EXCLUDE_SIZE = 0; +define symbol CY_EE_IN_BTLDR = 0x00; +define symbol CY_EE_SIZE = 2048; +include "cybootloader.icf"; +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; +} + +define symbol CY_FLASH_SIZE = 131072; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_ECC_ROW_SIZE = 32; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +if (CY_APPL_LOADABLE) +{ +define block LOADER { readonly section .cybootloader }; +} +define block APPL with fixed order {readonly section .romvectors, readonly}; + +/* The address of the Flash row next after the Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* The ECC data placement address */ +define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + +/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */ +define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; +define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + +/* Define EEPROM region */ +define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE]; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors }; + +/******** Placements *********/ +if (CY_APPL_LOADABLE) +{ +".cybootloader" : place at start of ROM_region {block LOADER}; +} + +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cyconfigecc, + section .cy_checksum_exclude, + section .cycustnvl, + section .cywolatch, + section .cyeeprom, + section .cyflashprotect, + section .cymeta }; + +".cyloadermeta" : place at address mem : ((CY_APPL_LOADER && !CY_APPL_LOADABLE) ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; +if (CY_APPL_LOADABLE) +{ +".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; +} + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +if (CY_APPL_LOADABLE) +{ + /* Align size to the flash row size */ + define symbol CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED = CY_CHECKSUM_EXCLUDE_SIZE + ((CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_SIZE % CY_FLASH_ROW_SIZE)) : 0); + + if (CY_CHECKSUM_EXCLUDE_SIZE != 0) + { + + /* General case */ + if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + { + define symbol CY_CHECKSUM_EXCLUDE_START = CY_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + else + { + define symbol CY_CHECKSUM_EXCLUDE_START = (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED; + } + + define symbol CY_CHECKSUM_EXCLUDE_START_ALIGNED = CY_CHECKSUM_EXCLUDE_START + ((CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE) ? (CY_FLASH_ROW_SIZE - (CY_CHECKSUM_EXCLUDE_START % CY_FLASH_ROW_SIZE)) : 0); + + ".cy_checksum_exclude" : place at address mem : (CY_CHECKSUM_EXCLUDE_START_ALIGNED) { readonly section .cy_checksum_exclude }; + + } /* (CY_CHECKSUM_EXCLUDE_SIZE_ALIGNED != 0) */ +} +else +{ + ".cy_checksum_exclude" : place in ROM_region { readonly section .cy_checksum_exclude }; +} + + +".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; +".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; +".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; +".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom }; +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +/* EOF */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat new file mode 100644 index 0000000..16a1b52 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -0,0 +1,228 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* \file Cm3RealView.scat +;* \version 5.50 +;* +;* \brief +;* This Linker Descriptor file describes the memory layout of the PSoC5 +;* device. The memory layout of the final binary and hex images as well as +;* the placement in PSoC5 memory is described. +;* +;* romvectors: Cypress default Interrupt service routine vector table. +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* This is the ISR vector table used by the application. +;* +;******************************************************************************** +;* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" + +#define CY_FLASH_SIZE 131072 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 256 +#define CY_ECC_ROW_SIZE 32 +#define CY_EE_SIZE 2048 +#define CY_METADATA_SIZE 64 + +#define CY_CHECKSUM_EXCLUDE_SIZE AlignExpr(0, CY_FLASH_ROW_SIZE) +#define CY_APPL_NUM 1 +#define CY_APPL_MAX 1 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + #define CY_EE_IN_BTLDR 0 + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) + #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) + #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX)) + +#else + + #define APPL_START 0 + #define ECC_OFFSET 0 + #define EE_OFFSET 0 + #define EE_SIZE CY_EE_SIZE + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START >= LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + CODE +0 + { + * (+RO) + } + + ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT + { + * (.ramvectors) + } + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0400 - 0x1000) EMPTY 0x0400 + { + } + + ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x1000 + { + } +} + + +/******************************************************************************* +* Bootloader Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LAUNCHER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif + + +/******************************************************************************* +* Bootloadable Metadata Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE || \ + CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } + +#endif + + +/******************************************************************************* +* Checksum Exclude Section. See cm0gcc.ld on placement details. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + #if (0 != 0) + + #if ((CY_APPL_NUM == 1) && (CY_APPL_MAX == 2)) + #define CY_CHECKSUM_APPL2_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ), CY_FLASH_ROW_SIZE)) + #define CY_CHECKSUM_EXCLUDE_START AlignExpr(CY_CHECKSUM_APPL2_START - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #else + #define CY_CHECKSUM_EXCLUDE_START AlignExpr((CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE, CY_FLASH_ROW_SIZE) + #endif + + CY_CHECKSUM_EXCLUDE (CY_CHECKSUM_EXCLUDE_START) + { + .cy_checksum_exclude +0 + { + * (.cy_checksum_exclude) + } + } + + #endif /* (0 != 0) */ + +#endif + + +#if (CYDEV_ECC_ENABLE == 0) + + CYCONFIGECC (0x80000000 + ECC_OFFSET) + { + .cyconfigecc +0 { * (.cyconfigecc) } + } + +#endif + +CYCUSTNVL 0x90000000 +{ + .cycustnvl +0 { * (.cycustnvl) } +} + +CYWOLATCH 0x90100000 +{ + .cywolatch +0 { * (.cywolatch) } +} + +#if defined(CYDEV_ALLOCATE_EEPROM) + + CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE) + { + .cyeeprom +0 { * (.cyeeprom) } + } + +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + + +/******************************************************************************* +* Bootloader Metadata Section. Must be part of the image, but beyond rom memory. +*******************************************************************************/ +#if ((CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) || (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c new file mode 100644 index 0000000..f5a1fa8 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -0,0 +1,503 @@ +/***************************************************************************//** +* \file Cm3Start.c +* \version 5.50 +* +* \brief +* Startup code for the ARM CM3. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "CyDmac.h" +#include "cyfitter.h" + + +#define CY_NUM_INTERRUPTS (32u) +#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) +#define CY_NUM_ROM_VECTORS (4u) +#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) +#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) +#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ +#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ +#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ + +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER (&__cy_stack) +#elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); +#endif /* (__ARMCC_VERSION) */ + +#if defined(__GNUC__) + #include + extern int errno; + extern int end; +#endif /* defined(__GNUC__) */ + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +/******************************************************************************* +* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ +#if defined (__ICCARM__) + #pragma location=".ramvectors" + #pragma data_alignment=256 +#else + CY_SECTION(".ramvectors") + CY_ALIGN(256) +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Function Name: IntDefaultHandler +****************************************************************************//** +* +* This function is called for all interrupts, other than a reset that gets +* called before the system is setup. +* +* Theory: +* Any value other than zero is acceptable. +* +*******************************************************************************/ +CY_ISR(IntDefaultHandler) +{ + /*************************************************************************** + * We must not get here. If we do, a serious problem occurs, so go into + * an infinite loop. + ***************************************************************************/ + + #if defined(__GNUC__) + if (errno == ENOMEM) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK + CyBoot_IntDefaultHandler_Enomem_Exception_Callback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_ENOMEM_EXCEPTION_CALLBACK */ + + while(1) + { + /* Out Of Heap Space + * This can be increased in the System tab of the Design Wide Resources. + */ + } + } + else + #endif + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + + } + } +} + + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the RVDS/MDK toolchains. +* This is the first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + __main(); +} + + +/******************************************************************************* +* Function Name: $Sub$$main +****************************************************************************//** +* +* This function is called immediately before the users main +* +*******************************************************************************/ +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns, it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +void Start_c(void); + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* Static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +****************************************************************************//** +* +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* \param status: Status caused program exit. +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + CyHalt((uint8) status); + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +****************************************************************************//** +* +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* \param nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static void *heapPointer = (void *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Reset +****************************************************************************//** +* +* This function handles the reset interrupt for the GCC toolchain. This is the +* first bit of code that is executed at startup. +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + Start_c(); +} + + +/******************************************************************************* +* Function Name: Start_c +****************************************************************************//** +* +* This function handles initializing the .data and .bss sections in +* preparation for running the standard C code. Once initialization is complete +* it will call main(). This function will never return. +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn)); +void Start_c(void) +{ + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } +} + + +#elif defined (__ICCARM__) + +/******************************************************************************* +* Function Name: __low_level_init +****************************************************************************//** +* +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of a reset interrupt handler +* before the data sections are initialized. +* +* \return +* The value that determines whether or not data sections should be initialized +* by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +int __low_level_init(void) +{ + #if (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE && CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER) */ + + #if ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) + CyBtldr_CheckLaunch(); + #endif /* ((CYDEV_BOOTLOADER_ENABLE) && (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER)) */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + CY_SECTION(".romvectors") + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + INITIAL_STACK_POINTER, /* Initial stack pointer 0 */ + #if defined (__ICCARM__) /* Reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* NMI handler 2 */ + &IntDefaultHandler, /* Hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +****************************************************************************//** +* +* This function used to initialize the PSoC chip before calling main. +* +*******************************************************************************/ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif +void initialize_psoc(void) +{ + uint32 i; + + /* Set Priority group 5. */ + + /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ + *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; + *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; + + /* Set Ram interrupt vectors to default functions. */ + for (i = 0u; i < CY_NUM_VECTORS; i++) + { + #if defined (__ICCARM__) + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; + #else + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ + CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); + + /* Point NVIC at RAM vector table. */ + *CYINT_VECT_TABLE = CyRamVectors; + + /* Initialize the configuration registers. */ + cyfitter_cfg(); + + #if(0u != DMA_CHANNELS_USED__MASK0) + + /* Setup DMA - only necessary if design contains DMA component. */ + CyDmacConfigure(); + + #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s new file mode 100644 index 0000000..eefb063 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -0,0 +1,161 @@ +/***************************************************************************//** +* \file CyBootAsmGnu.s +* \version 5.50 +* +* \brief +* Assembly routines for GNU as. +* +******************************************************************************** +* \copyright +* Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.include "cyfittergnu.inc" + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: CyDelayCycles +****************************************************************************//** +* +* Delays for the specified number of cycles. +* +* \param uint32 cycles: number of cycles to delay. +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ +/* If ICache is enabled */ +.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 + + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ + NOP /* 1 2 Loop alignment padding */ + +CyDelayCycles_loop: + SUBS r0, r0, #1 /* 1 2 */ + MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ + BNE CyDelayCycles_loop /* 2 2 */ + +CyDelayCycles_done: + BX lr /* 3 2 */ + +.else + + CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ + BLS CyDelayCycles_short /* 1 2 */ + PUSH {r1} /* 2 2 PUSH r1 to stack */ + MOVS r1, #1 /* 1 2 */ + + SUBS r0, r0, #20 /* 1 2 Subtract overhead */ + LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ + LDRB r1, [r1, #0] /* 2 2 */ + ANDS r1, #0xC0 /* 1 2 */ + + LSRS r1, r1, #6 /* 1 2 */ + PUSH {r2} /* 1 2 PUSH r2 to stack */ + LDR r2, =cy_flash_cycles /* 2 2 */ + LDRB r1, [r2, r1] /* 2 2 */ + + POP {r2} /* 2 2 POP r2 from stack */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_loop: + SBCS r0, r0, r1 /* 1 2 */ + BPL CyDelayCycles_loop /* 3 2 */ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ + + POP {r1} /* 2 2 POP r1 from stack */ +CyDelayCycles_done: + BX lr /* 3 2 */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_short: + SBCS r0, r0, #4 /* 1 2 */ + BPL CyDelayCycles_short /* 3 2 */ + BX lr /* 3 2 */ + +cy_flash_cycles: +.byte 0x0B +.byte 0x05 +.byte 0x07 +.byte 0x09 +.endif + +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +****************************************************************************//** +* +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* \return +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +****************************************************************************//** +* +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* \param uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s new file mode 100644 index 0000000..b300e04 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -0,0 +1,156 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmIar.s +; Version 5.50 +; +; DESCRIPTION: +; Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013-2015, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + INCLUDE cyfitteriar.inc + THUMB + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid a corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop: + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 +CyDelayCycles_done: + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop: + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done: + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding +CyDelayCycles_short: + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + NOP ; 1 2 Loop alignment padding + + DATA +cy_flash_cycles: +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + + END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s new file mode 100644 index 0000000..b42dbbb --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -0,0 +1,161 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmRv.s +; Version 5.50 +; +; DESCRIPTION: +; Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2015, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + + GET cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_done + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_short + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + +cy_flash_cycles +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c new file mode 100644 index 0000000..78150bf --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -0,0 +1,1039 @@ +/***************************************************************************//** +* \file CyDmac.c +* \version 5.50 +* +* \brief +* Provides an API for the DMAC component. The API includes functions for the +* DMA controller, DMA channels and Transfer Descriptors. This API is the library +* version not the auto generated code that gets generated when the user places a +* DMA component on the schematic. +* +* The auto generated code would use the APi's in this module. +* +* \note This code is endian agnostic. +* +* \note The Transfer Descriptor memory can be used as regular memory if the +* TD's are not being used. +* +* \note This code uses the first byte of each TD to manage the free list of +* TD's. The user can overwrite this once the TD is allocated. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyDmac.h" + + +/******************************************************************************* +* The following variables are initialized from CyDmacConfigure() function that +* is executed from initialize_psoc() at the early initialization stage. +* In case of IAR EW IDE, initialize_psoc() is executed before the data sections +* are initialized. To avoid zeroing, these variables should be initialized +* properly during segments initialization as well. +*******************************************************************************/ +static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */ +static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */ +static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */ + + +/******************************************************************************* +* Function Name: CyDmacConfigure +****************************************************************************//** +* +* Creates a linked list of all the TDs to be allocated. This function is called +* by the startup code; you do not normally need to call it. You can call this +* function if all of the DMA channels are inactive. +* +*******************************************************************************/ +void CyDmacConfigure(void) +{ + uint8 dmaIndex; + + /* Set TD list variables. */ + CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); + CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; + + /* Make TD free list. */ + for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) + { + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); + } + + /* Make last one point to zero. */ + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; +} + + +/******************************************************************************* +* Function Name: CyDmacError +****************************************************************************//** +* +* Returns errors of the last failed DMA transaction. +* +* \return Errors of the last failed DMA transaction. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by +* writing 1 to the error register. +* +*******************************************************************************/ +uint8 CyDmacError(void) +{ + return((uint8)(((uint32) 0x0Eu) & *CY_DMA_ERR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmacClearError +****************************************************************************//** +* +* Clears the error bits in the error register of the DMAC. +* +* \param error: +* Clears the error bits in the DMAC error register. +* +* \param DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* \param DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* \param DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by +* writing 1 to the error register. +* +*******************************************************************************/ +void CyDmacClearError(uint8 error) +{ + *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); +} + + +/******************************************************************************* +* Function Name: CyDmacErrorAddress +****************************************************************************//** +* +* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the +* address of the error is written to the error address register and can be read +* with this function. +* +* If there are multiple errors, only the address of the first is saved. +* +* \return The address that caused the error. +* +*******************************************************************************/ +uint32 CyDmacErrorAddress(void) +{ + return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmaChAlloc +****************************************************************************//** +* +* Allocates a channel from the DMAC to be used in all functions that require a +* channel handle. +* +* \return The allocated channel number. Zero is a valid channel number. +* DMA_INVALID_CHANNEL is returned if there are no channels available. +* +*******************************************************************************/ +uint8 CyDmaChAlloc(void) +{ + uint8 interruptState; + uint8 dmaIndex; + uint32 channel = 1u; + + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + /* Look for free channel. */ + for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) + { + if(0uL == (CyDmaChannels & channel)) + { + /* Mark channel as used. */ + CyDmaChannels |= channel; + break; + } + + channel <<= 1u; + } + + if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) + { + dmaIndex = CY_DMA_INVALID_CHANNEL; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(dmaIndex); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +****************************************************************************//** +* +* Frees a channel allocated by \ref DmaChAlloc(). +* +* \param chHandle The handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + uint8 interruptState; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Clear bit mask that keeps track of ownership. */ + CyDmaChannels &= ~(((uint32) 1u) << chHandle); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +****************************************************************************//** +* +* Enables the DMA channel. A software or hardware request still must happen +* before the channel is executed. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \param preserveTds Preserves the original TD state when the TD has completed. +* This parameter applies to all TDs in the channel. +* +* 0 - When TD is completed, the DMAC leaves the TD configuration values in +* their current state, and does not restore them to their original state. +* +* 1 - When TD is completed, the DMAC restores the original configuration +* values of the TD. +* +* When preserveTds is set, the TD slot that equals the channel number becomes +* RESERVED and that becomes where the working registers exist. So, for example, +* if you are using CH06 and preserveTds is set, you are not allowed to use TD +* slot 6. That is reclaimed by the DMA engine for its private use. +* +* \note Do not chain back to a completed TD if the preserveTds for the channel +* is set to 0. When a TD has completed preserveTds for the channel set to 0, +* the transfer count will be at 0. If a TD with a transfer count of 0 is +* started, the TD will transfer an indefinite amount of data. +* +* Take extra precautions when using the hardware request (DRQ) option when the +* preserveTds is set to 0, as you might be requesting the wrong data. +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != preserveTds) + { + /* Store intermediate TD states separately in CHn_SEP_TD0/1 to + * preserve original TD chain + */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; + } + else + { + /* Store intermediate and final TD states on top of original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); + } + + /* Enable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +****************************************************************************//** +* +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. +* +* If it is currently executing it will allow the current burst to finish +* naturally. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChDisable(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /*********************************************************************** + * Should not change configuration information of a DMA channel when it + * is active (or vulnerable to becoming active). + ***********************************************************************/ + + /* Disable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); + + /* Store intermediate and final TD states on top of original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaClearPendingDrq +****************************************************************************//** +* +* Clears pending the DMA data request. +* +* \param chHandle Handle to the dma channel. +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaClearPendingDrq(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChPriority +****************************************************************************//** +* +* Sets the priority of a DMA channel. You can use this function when you want +* to change the priority at run time. If the priority remains the same for a +* DMA channel, then you can configure the priority in the .cydwr file. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \param priority Priority to set the channel to, 0 - 7. +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) +{ + uint8 value; + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); + + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetExtendedAddress +****************************************************************************//** +* +* Sets the high 16 bits of the source and destination addresses for the DMA +* channel (valid for all TDs in the chain). +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \param source Upper 16 bit address of the DMA transfer source. +* +* \param destination Upper 16 bit address of the DMA transfer destination. +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ + +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + #if(CY_PSOC5) + + /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ + if(source == 0x1FFFu) + { + source = 0x2000u; + } + + if(destination == 0x1FFFu) + { + destination = 0x2000u; + } + + #endif /* (CY_PSOC5) */ + + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; + CY_SET_REG16(convert, destination); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetInitialTd +****************************************************************************//** +* +* Sets the initial TD to be executed for the channel when the \ref CyDmaChEnable() +* function is called. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or +* \ref DMA_DmaInitialize(). +* +* \param startTd Set the TD index as the first TD associated with the +* channel. Zero is a valid TD index. +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetRequest +****************************************************************************//** +* +* Allows the caller to terminate a chain of TDs, terminate one TD, or create a +* direct request to start the DMA channel. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \param request One of the following constants. Each of the constants is a +* three-bit value. +* CPU_REQ - Create a direct request to start the DMA channel +* CPU_TERM_TD - Terminate one TD +* CPU_TERM_CHAIN - Terminate a chain of TDs +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChGetRequest +****************************************************************************//** +* +* This function allows the caller of \ref CyDmaChSetRequest() to determine if the +* request was completed. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \return Returns a three-bit field, corresponding to the three bits of the +* request, which describes the state of the previously posted request. If the +* value is zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle +* is invalid. +* +*******************************************************************************/ +cystatus CyDmaChGetRequest(uint8 chHandle) +{ + cystatus status = CY_DMA_INVALID_CHANNEL; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChStatus +****************************************************************************//** +* +* Determines the status of the DMA channel. +* +* \param chHandle A handle previously returned by \ref CyDmaChAlloc() or \ref +* DMA_DmaInitalize(). +* +* \param currentTd The address to store the index of the current TD. Can be NULL +* if the value is not needed. +* +* \param state The address to store the state of the channel. Can be NULL if the +* value is not needed. +* +* STATUS_TD_ACTIVE +* \param 0: Channel is not currently being serviced by DMAC +* \param 1: Channel is currently being serviced by DMAC +* +* STATUS_CHAIN_ACTIVE +* \param 0: TD chain is inactive; either no DMA requests have triggered a new chain +* or the previous chain has completed. +* \param 1: TD chain has been triggered by a DMA request +* +* \return CYRET_SUCCESS if successful. +* \return CYRET_BAD_PARAM if chHandle is invalid. +* +* Theory: +* The caller can check on the activity of the Current TD and the Chain. +* +*******************************************************************************/ +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if(NULL != currentTd) + { + *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; + } + + if(NULL != state) + { + *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; + } + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetConfiguration +****************************************************************************//** +* +* Sets configuration information of the channel. +* +* \param uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* \param uint8 burstCount: +* Specifies the size of bursts (1 to 127) the data transfer should be divided +* into. If this value is zero then the whole transfer is done in one burst. +* +* \param uint8 requestPerBurst: +* The whole of the data can be split into multiple bursts, if this is +* \param required to complete the transaction: +* \param 0: All subsequent bursts after the first burst will be automatically +* requested and carried out +* \param 1: All subsequent bursts after the first burst must also be individually +* requested. +* +* \param uint8 tdDone0: +* Selects one of the TERMOUT0 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT0_SEL definition and +* should be used as supplied by cyfitter.h +* +* \param uint8 tdDone1: +* Selects one of the TERMOUT1 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT1_SEL definition and +* should be used as supplied by cyfitter.h +* +* \param uint8 tdStop: +* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD +* should terminate. The signal connected to the trq terminal will determine +* which TERMIN (termination request) is used. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, + uint8 tdDone0, uint8 tdDone1, uint8 tdStop) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdAllocate +****************************************************************************//** +* +* Allocates a TD for use with an allocated DMA channel. +* +* \return +* Zero-based index of the TD to be used by the caller. Since there are 128 TDs +* minus the reserved TDs (0 to 23), the value returned would range from 24 to +* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs +* available. +* +*******************************************************************************/ +uint8 CyDmaTdAllocate(void) +{ + uint8 interruptState; + uint8 element = CY_DMA_INVALID_TD; + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) + { + /* Get pointer to Next available. */ + element = CyDmaTdFreeIndex; + + /* Decrement the count. */ + CyDmaTdCurrentNumber--; + + /* Update next available pointer. */ + CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(element); +} + + +/******************************************************************************* +* Function Name: CyDmaTdFree +****************************************************************************//** +* +* Returns a TD to the free list. +* +* \param uint8 tdHandle: +* The TD handle returned by the CyDmaTdAllocate(). +* +*******************************************************************************/ +void CyDmaTdFree(uint8 tdHandle) +{ + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Enter critical section! */ + uint8 interruptState = CyEnterCriticalSection(); + + /* Get pointer to Next available. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; + + /* Set new Next Available. */ + CyDmaTdFreeIndex = tdHandle; + + /* Keep track of how many left. */ + CyDmaTdCurrentNumber++; + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + } +} + + +/******************************************************************************* +* Function Name: CyDmaTdFreeCount +****************************************************************************//** +* +* Returns the number of free TDs available to be allocated. +* +* \return +* The number of free TDs. +* +*******************************************************************************/ +uint8 CyDmaTdFreeCount(void) +{ + return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetConfiguration +****************************************************************************//** +* +* Configures the TD. +* +* \param uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* \param uint16 transferCount: +* The size of the data transfer (in bytes) for this TD. A size of zero will +* cause the transfer to continue indefinitely. This parameter is limited to +* 4095 bytes; the TD is not initialized at all when a higher value is passed. +* +* \param uint8 nextTd: +* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a +* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. +* +* \param uint8 configuration: +* Stores the Bit field of configuration bits. +* +* CY_DMA_TD_SWAP_EN - Perform endian swap +* +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes +* +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. +* +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. +* +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. +* +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. +* +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) + { + /* Set 12 bits transfer count. */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; + CY_SET_REG16(convert, transferCount); + + /* Set Next TD pointer. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; + + /* Configure the TD */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetConfiguration +****************************************************************************//** +* +* Retrieves the configuration of the TD. If a NULL pointer is passed as a +* parameter, that parameter is skipped. You may request only the values you are +* interested in. +* +* \param uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* \param uint16 * transferCount: +* The address to store the size of the data transfer (in bytes) for this TD. +* A size of zero could indicate that the TD has completed its transfer, or +* that the TD is doing an indefinite transfer. +* +* \param uint8 * nextTd: +* The address to store the index of the next TD in the TD chain. +* +* \param uint8 * configuration: +* The address to store the Bit field of configuration bits. +* See CyDmaTdSetConfiguration() function description. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +* \sideeffect +* If TD has a transfer count of N and is executed, the transfer count becomes +* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a +* request for indefinite transfer. Be careful when requesting TD with a +* transfer count of zero. +* +*******************************************************************************/ +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have pointer */ + if(NULL != transferCount) + { + /* Get 12 bits of transfer count */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; + *transferCount = 0x0FFFu & CY_GET_REG16(convert); + } + + /* If we have pointer */ + if(NULL != nextTd) + { + /* Get Next TD pointer */ + *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; + } + + /* If we have pointer */ + if(NULL != configuration) + { + /* Get configuration TD */ + *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetAddress +****************************************************************************//** +* +* Sets the lower 16 bits of the source and destination addresses for this TD +* only. +* +* \param uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* \param uint16 source: +* The lower 16 address bits of the source of the data transfer. +* +* \param uint16 destination: +* The lower 16 address bits of the destination of the data transfer. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + CY_SET_REG16(convert, destination); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetAddress +****************************************************************************//** +* +* Retrieves the lower 16 bits of the source and/or destination addresses for +* this TD only. If NULL is passed for a pointer parameter, that value is +* skipped. You may request only the values of interest. +* +* \param uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* \param uint16 * source: +* The address to store the lower 16 address bits of the source of the data +* transfer. +* +* \param uint16 * destination: +* The address to store the lower 16 address bits of the destination of the +* data transfer. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer. */ + if(NULL != source) + { + /* Get source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + *source = CY_GET_REG16(convert); + } + + /* If we have a pointer. */ + if(NULL != destination) + { + /* Get Destination address. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + *destination = CY_GET_REG16(convert); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChRoundRobin +****************************************************************************//** +* +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. +* +* \param uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* +* \param uint8 enableRR: +* \param 0: Disable Round-Robin fairness algorithm +* \param 1: Enable Round-Robin fairness algorithm +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != enableRR) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; + } + else + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h new file mode 100644 index 0000000..63b73ae --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -0,0 +1,228 @@ +/***************************************************************************//** +* \file CyDmac.h +* \version 5.50 +* +* \brief Provides the function definitions for the DMA Controller. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ +; +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, + uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ +; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ +; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ +#define CY_DMA_DISABLE_TD 0xFEu + +#define CY_DMA_TD_SIZE 0x08u + +/* "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/******************************************************************************* +* CyDmaChEnable() / CyDmaChDisable() API constants +*******************************************************************************/ +#define CY_DMA_CH_BASIC_CFG_EN (0x01u) +#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c new file mode 100644 index 0000000..79a6678 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -0,0 +1,684 @@ +/***************************************************************************//** +* \file CyFlash.c +* \version 5.50 +* +* \brief Provides an API for the FLASH/EEPROM. +* +* \note This code is endian agnostic. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + +/* The number of EEPROM arrays */ +#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u) + + +/******************************************************************************* +* Holds the die temperature, updated by CySetTemp(). Used for flash writing. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); +static cystatus CyFlashGetSpcAlgorithm(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +****************************************************************************//** +* +* Enable the Flash. +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or eeprom to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable flash. Active flash macros consume current, but re-enabling a + * disabled flash macro takes 5us. If the CPU attempts to fetch out of the + * macro during that time, it will be stalled. This bit allows the flash to + * be enabled even if the CPU is disabled, which allows a quicker return to + * code execution. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +****************************************************************************//** +* +* Disable the Flash. +* +* \sideeffect +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySetTempInt +****************************************************************************//** +* +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write function. This function must be called once before +* executing a series of Flash writing functions. +* +* \return +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyFlashGetSpcAlgorithm +****************************************************************************//** +* +* Sends a command to the SPC to download code into RAM. +* +* \return +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CyFlashGetSpcAlgorithm(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + if(CySpcLock() == CYRET_SUCCESS) + { + status = CySpcGetAlgorithm(); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +****************************************************************************//** +* +* This is a wraparound for CySetTempInt(). It is used to return the second +* successful read of the temperature value. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds the die temperature for the flash writing algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CyFlashGetSpcAlgorithm(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +****************************************************************************//** +* +* Sets the user supplied temporary buffer to store SPC data while performing +* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC +* is disabled. +* +* \param buffer: +* The address of a block of memory to store temporary memory. The size of the +* block of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + rowBuffer = rowBuffer; + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + rowBuffer = rowBuffer; + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To suppress warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +/******************************************************************************* +* Function Name: CyWriteRowData +****************************************************************************//** +* +* Sends a command to the SPC to load and program a row of data in +* Flash or EEPROM. +* +* \param arrayID: ID of the array to write. +* The type of write, Flash or EEPROM, is determined from the array ID. +* The arrays in the part are sequential starting at the first ID for the +* specific memory type. The array ID for the Flash memory lasts from 0x00 to +* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. +* \param rowAddress: rowAddress of flash row to program. +* \param rowData: Array of bytes to write. +* +* \return +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) +{ + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); +} + + +/******************************************************************* +* If "Enable Error Correcting Code (ECC)" and "Store Configuration +* Data in ECC" DWR options are disabled, ECC section is available +* for user data. +*******************************************************************/ +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ****************************************************************************//** + * + * Sends a command to the SPC to load and program a row of config data in the + * Flash. This function is only valid for Flash array IDs (not for EEPROM). + * + * \param arrayId: ID of the array to write + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts + * from 0x00 to 0x3F. + * \param rowAddress: The address of the sector to erase. + * \param rowECC: The array of bytes to write. + * + * \return + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ + + { + cystatus status; + + status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE); + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +****************************************************************************//** +* Sends a command to the SPC to load and program a row of data in the Flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* \param arrayId: FLASH or EEPROM array id. +* \param rowData: Pointer to a row of data to write. +* \param rowNumber: Zero based number of the row. +* \param rowSize: Size of the row. +* +* \return +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status = CYRET_SUCCESS; + + if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId > CY_SPC_LAST_EE_ARRAYID) + { + status = CYRET_BAD_PARAM; + } + + if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID) + { + /* Flash */ + if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + } + else + { + /* EEPROM */ + if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + + if(CY_EEPROM_SIZEOF_ROW != rowSize) + { + status = CYRET_BAD_PARAM; + } + } + + if(rowData == NULL) + { + status = CYRET_BAD_PARAM; + } + + + if(status == CYRET_SUCCESS) + { + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + } + CySpcUnlock(); + } /* if(CySpcLock() == CYRET_SUCCESS) */ + else + { + status = CYRET_LOCKED; + } + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +****************************************************************************//** +* +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from the Flash. This function must be called before increasing +* the CPU clock frequency. It can optionally be called after lowering the CPU +* clock frequency in order to improve the CPU performance. +* +* \param uint8 freq: +* Frequency of operation in Megahertz. +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_1_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_2_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_3_VALUE_MASK; + } +#if (CY_PSOC5) + else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_4_VALUE_MASK; + } + else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_5_VALUE_MASK; + } +#endif /* (CY_PSOC5) */ + else + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Start +****************************************************************************//** +* +* Enable the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or EEPROM to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time, + * the EE will not acknowledge a PHUB request. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Stop +****************************************************************************//** +* +* Disable the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_Stop (void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +****************************************************************************//** +* +* Request access to the EEPROM for reading and wait until access is available. +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make request for PHUB to have access */ + CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgment from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +****************************************************************************//** +* +* Release the read reservation of the EEPROM. +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h new file mode 100644 index 0000000..5307f99 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -0,0 +1,322 @@ +/***************************************************************************//** +* \file CyFlash.h +* \version 5.50 +* +* \brief Provides the function definitions for the FLASH/EEPROM. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#if(CYDEV_ECC_ENABLE == 0) + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW) +#else + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW) +#endif /* (CYDEV_ECC_ENABLE == 0) */ +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EE_SIZE) /* EEPROM has one array */ +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) +#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +void CyEEPROM_Start(void) ; +void CyEEPROM_Stop(void) ; + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ +/* Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0) +#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Alternate Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0) +#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + +/* Alternate Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + +/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) + +/* Flash macro control register */ +#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR) +#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR) + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ + +/* Enable EEPROM */ +#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u) +#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u) + +/* Enable Flash */ +#if (CY_PSOC3) + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u) +#else + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu) +#endif /* (CY_PSOC3) */ + + + +/* Frequency Constants */ +#if (CY_PSOC3) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u) +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u) + #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u) + #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u) + #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u) +#endif /* (CY_PSOC5) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + +#define CY_FLASH_EE_EE_AWAKE (0x20u) + +/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u) + +/* Enable clk_spc. This also internally enables the 36MHz IMO. */ +#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u) +#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u) + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if (CY_PSOC5) + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) +#endif /* (CY_PSOC5) */ + +#if (CY_PSOC3) + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) +#endif /* (CY_PSOC3) */ + +#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_EE_MASK (0x10u) +#define CY_FLASH_PM_FLASH_MASK (0x01u) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_SECTORS) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) +#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + +#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) +#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) +#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c new file mode 100644 index 0000000..995972f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c @@ -0,0 +1,2928 @@ +/***************************************************************************//** +* \file CyLib.c +* \version 5.50 +* +* \brief Provides a system API for the clocking, interrupts and watchdog timer. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. It is set from initialize_psoc() at the early initialization +* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data +* sections are initialized. To avoid zeroing, CyResetStatus should be placed +* to the .noinit section. +*******************************************************************************/ +CY_NOINIT uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + +#if(CY_PSOC5) + static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; + static void CySysTickServiceCallbacks(void); + uint32 CySysTickInitVar = 0u; +#endif /* (CY_PSOC5) */ + + +#if(CY_PSOC3) + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +****************************************************************************//** +* +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* \param wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for PLL lock or timeout. +* +* \return +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* \sideeffect +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == iloEnableState) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +****************************************************************************//** +* +* Disables the PLL. +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +****************************************************************************//** +* +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* \param uint8 pDiv: +* Valid range [8 - 255]. +* +* \param uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* \param uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +****************************************************************************//** +* +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* \param source: One of the three available PLL clock sources +* \param CY_PLL_SOURCE_IMO : IMO +* \param CY_PLL_SOURCE_XTAL : MHz Crystal +* \param CY_PLL_SOURCE_DSI : DSI +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the3 Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +****************************************************************************//** +* +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* \param uint8 wait: +* \param 0: Return immediately after configuration +* \param 1: Wait for at least 6 us for the IMO to settle. +* +* \sideeffect +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 ilo100KhzEnable; + + + CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; + CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; + + if(0u != wait) + { + /* Need to turn on 100KHz ILO if it happens to not already be running.*/ + ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; + pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); + + while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + } + + if(0u == ilo100KhzEnable) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; + CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +****************************************************************************//** +* +* Disables the IMO. +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); + CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +****************************************************************************//** +* +* Returns the USB power status value. A private function to cy_boot. +* +* \return +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActive and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +****************************************************************************//** +* +* Sets the IMO factory trim values. +* +* uint8 freq - frequency for which trims must be set +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usbPowerOn = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Unlock USB write */ + CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Lock USB Oscillator */ + CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +****************************************************************************//** +* +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* \param freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62.6 MHz +* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* \sideeffect +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * If the IMO frequency is changed,the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set a new trim and then change the frequency, + * otherwise change the frequency and then set new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + +#if(CY_PSOC5) + case 6u: + currentFreq = CY_IMO_FREQ_74MHZ; + break; +#endif /* (CY_PSOC5) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the trim after setting frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +****************************************************************************//** +* +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or DSI input can be the source of the IMO output instead. +* +* \param source: CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +****************************************************************************//** +* +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +****************************************************************************//** +* +* Disables the IMO doubler. +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +****************************************************************************//** +* +* Sets the source of the master clock. +* +* \param source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* \sideeffect +* The current source and the new source must both be running and stable before +* calling this function. +* +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +****************************************************************************//** +* +* Sets the divider value used to generate Master Clock. +* +* \param uint8 divider: +* The valid range is [0-255]. The clock will be divided by this value + 1. +* For example to divide this parameter by two should be set to 1. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +****************************************************************************//** +* +* The function used by CyBusClk_SetDivider(). For internal use only. +* +* \param divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +****************************************************************************//** +* +* Sets the divider value used to generate the Bus Clock. +* +* \param divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +* \sideeffect +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling +* CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally +* called if the CPU clock frequency is lowered in order to improve the CPU +* performance. See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set bus clock divider value */ + busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); + busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set SSS bit and divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ****************************************************************************//** + * + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * \param divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example, to divide this parameter by two should be set to 1. + * + * \sideeffect + * If this function execution resulted in the CPU clock frequency increasing, + * then the number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be adjusted by calling + * CyFlash_SetWaitCycles() with an appropriate parameter. It can be optionally + * called if the CPU clock frequency is lowered in order to improve the CPU + * performance. See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | + ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +****************************************************************************//** +* +* Sets the source of the USB clock. +* +* \param source: One of the four available USB clock sources +* CY_LIB_USB_CLK_IMO2X - IMO 2x +* CY_LIB_USB_CLK_IMO - IMO +* CY_LIB_USB_CLK_PLL - PLL +* CY_LIB_USB_CLK_DSI - DSI +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | + (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +****************************************************************************//** +* +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +****************************************************************************//** +* +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low +* power mode APIs are expected to be used. For more information, refer to the +* Power Management section of this document. +* +* \sideeffect +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +****************************************************************************//** +* +* Enables the ILO 100 KHz oscillator. +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +****************************************************************************//** +* +* Disables the ILO 100 KHz oscillator. +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +****************************************************************************//** +* +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set bit 5 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +****************************************************************************//** +* +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +****************************************************************************//** +* +* Sets the source of the clock output from the ILO block. +* +* \param source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +****************************************************************************//** +* +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* \param mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* \return Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = CY_LIB_SLOWCLK_ILO_CR0_REG; + + /* Set the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); + } + else + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); + } + + /* Return old mode. */ + return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +****************************************************************************//** +* +* Enables the 32 KHz Crystal Oscillator. +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to high power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +****************************************************************************//** +* +* Disables the 32KHz Crystal Oscillator. +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +****************************************************************************//** +* +* Returns status of the 32 KHz oscillator. +* +* \return +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +****************************************************************************//** +* +* Sets the power mode for the 32 KHz oscillator used during the sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During the active mode the oscillator is always run in the high power mode. +* +* uint8 mode +* \param 0: High power mode +* \param 1: Low power mode during sleep +* +* \return +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +****************************************************************************//** +* +* Enables the megahertz crystal. +* +* PSoC 3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* \param wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* \return +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + volatile uint8 timeout = wait; + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; + pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + /* Wait for 1 millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for FTW interrupt event */ + } + } + + + /******************************************************************* + * High output indicates an oscillator failure. + * Only can be used after a start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) + { + CyILO_Stop100K(); + } + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +****************************************************************************//** +* +* Disables the megahertz crystal oscillator. +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableErrStatus +****************************************************************************//** +* +* Enables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_EnableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableErrStatus +****************************************************************************//** +* +* Disables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_DisableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; +} + + +/******************************************************************************* +* Function Name: CyXTAL_ReadStatus +****************************************************************************//** +* +* Reads the XERR status bit for the megahertz crystal. This status bit is a +* sticky, clear on read. This function is not available for PSoC5. +* +* \return +* Status +* 0: No error +* 1: Error +* +*******************************************************************************/ +uint8 CyXTAL_ReadStatus(void) +{ + /*************************************************************************** + * High output indicates an oscillator failure. Only use this after a start-up + * interval is completed. This can be used for the status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableFaultRecovery +****************************************************************************//** +* +* Enables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. The crystal must be up and +* running with the XERR bit at 0, before calling this function to prevent +* an immediate fault switchover. This function is not available for PSoC5. +* +*******************************************************************************/ +void CyXTAL_EnableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableFaultRecovery +****************************************************************************//** +* +* Disables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. This function is not available +* for PSoC5. +* +*******************************************************************************/ +void CyXTAL_DisableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +****************************************************************************//** +* +* Sets the startup settings for the crystal. The logic model outputs a +* frequency (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* \param setting: Valid range [0-31]. +* The value is dependent on the frequency and quality of the crystal being +* used. Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + + +/******************************************************************************* +* Function Name: CyXTAL_SetFbVoltage +****************************************************************************//** +* +* Sets the feedback reference voltage to use for the crystal circuit. +* This function is only available for PSoC3 and PSoC 5LP. +* +* \param setting: Valid range [0-15]. +* Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetFbVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetWdVoltage +****************************************************************************//** +* +* Sets the reference voltage used by the watchdog to detect a failure in the +* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. +* +* \param setting: Valid range [0-7]. +* Refer to the device TRM and datasheet for more information. +* +*******************************************************************************/ +void CyXTAL_SetWdVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); +} + + +/******************************************************************************* +* Function Name: CyHalt +****************************************************************************//** +* +* Halts the CPU. +* +* \param uint8 reason: Value to be used during debugging. +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +****************************************************************************//** +* +* Forces a device software reset. +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; +} + + +/******************************************************************************* +* Function Name: CyDelay +****************************************************************************//** +* +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* the instruction cache is disabled on PSoC5, CyDelay will be two times larger. +* For example, with instruction cache disabled CyDelay(100) would result in +* about 200 ms delay instead of 100 ms. +* +* \param milliseconds: number of milliseconds to delay. +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ****************************************************************************//** + * + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * \param uint16 microseconds: number of microseconds to delay. + * + * \sideeffect + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with the instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +****************************************************************************//** +* +* Sets the clock frequency for CyDelay. +* +* \param freq: The frequency of the bus clock in Hertz. +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +****************************************************************************//** +* +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for the low power mode is configured and +* the watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* \param ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* \param lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* \sideeffect +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + /* Setting low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + + /* Enables watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +****************************************************************************//** +* +* Clears (feeds) the watchdog timer. +* +*******************************************************************************/ +void CyWdtClear(void) +{ + CY_WDT_CR_REG = CY_WDT_CR_FEED; +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +****************************************************************************//** +* +* Sets the voltage trip level, enables the output of the digital low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +* \param reset: Enables device reset on digital low-voltage event: +* Zero - Interrupt on digital low-voltage event +* Non-zero - Reset on digital low-voltage event +* +* \param threshold: Sets the trip point of the digital low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when the threshold +* parameter value is 0x04. Refer to the device TRM for the exact trip voltage +* values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as the +* supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_LVID); + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +****************************************************************************//** +* +* Sets the voltage trip level, enables the output of the analog low-voltage +* monitor, and optionally configures voltage monitor to reset device upon the +* low-voltage event instead of generating an interrupt. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +* \param reset: Enables device reset on analog low-voltage event: +* Zero - Interrupt on analog low-voltage event +* Non-zero - Reset on analog low-voltage event +* +* \param threshold: Sets the trip point of the analog low-voltage monitoring circuit +* in steps of approximately 250 mV in range from 1.70 V (0x00) to 5.45 V +* (0x0F). For example, the trip point is set to 1.80 V when value of the +* threshold parameter is 0x04. Please refer to the device TRM for the exact +* trip voltage values. +* +* Side Effects and Restrictions: +* The voltage resets are momentary. When a voltage reset (analog/digital +* low-voltage and analog high-voltage) occurs, the RESET_CR1 and RESET_CR3 +* registers are restored to their default values. This means that the voltage +* monitor circuit is no longer enabled and the device exits reset. If the +* supply is below the trip level and firmware enables the voltage reset +* functionality, the device will reset again. This will continue as long as +* the supply is below the trip level or as long as the user enables the reset +* functionality of the voltage monitor functionality. +* +* When any voltage reset occurs, the RESET_SR0 and RESET_SR2 status registers +* are cleared. This means that analog low-voltage, digital low-voltage and +* analog high-voltage status bits are not persistent across any voltage reset. +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_LVIA); + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +****************************************************************************//** +* +* Disables the digital low-voltage monitor, turns off device reset upon the +* digital low-voltage event, and clears the associated persistent status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + (void) CyVdStickyStatus(CY_VD_LVID); + + while(0u != (CyVdStickyStatus(CY_VD_LVID) & CY_VD_LVID)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +****************************************************************************//** +* +* Disables the analog low-voltage monitor, turns off device reset upon the +* analog low-voltage event, and clears the associated persistent status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + while(0u != (CyVdStickyStatus(CY_VD_LVIA) & CY_VD_LVIA)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +****************************************************************************//** +* +* Enables the output of the analog high-voltage monitor and sets 5.75 V +* threshold detection for Vdda. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The Interrupt component API should be used to register the +* interrupt service routine and to enable/disable associated interrupt. +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + uint32 intRegTmp; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Store interrupt enable state */ + intRegTmp = CY_INT_ENABLE_REG & CY_VD_INT_MASK; + + /* Disable VD interrupt (write 1) to protect against glitches */ + CY_INT_CLEAR_REG = CY_VD_INT_MASK; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling (ID # 127412) */ + CyDelayUs(1u); + + (void) CyVdStickyStatus(CY_VD_HVIA); + + /* Clear pending interrupt */ + CY_INT_CLR_PEND_REG = CY_VD_INT_MASK; + + /* Restore interrupt enable state */ + CY_INT_ENABLE_REG = intRegTmp; + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +****************************************************************************//** +* +* Disables the analog high-voltage monitor and clears the associated persistent +* status bit. +* +* Note The associated interrupt enable/disable state is not changed by the +* function. The pending interrupt status is not cleared. The Interrupt +* component API should be used to manipulate with the associated interrupts. +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); + while(0u != (CyVdStickyStatus(CY_VD_HVIA) & CY_VD_HVIA)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +****************************************************************************//** +* +* Reads and clears the voltage detection status bits in the RESET_SR0 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector trip point. They stay set to 1 until they are read or +* a POR / LVI / PRES reset occurs. This function uses a shadow register, so +* only the bits passed in the parameter will be cleared in the shadow register. +* +* \param mask: Bits in the RESET_SR0 shadow register to clear and return. +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +* \return +* Status. Same enumerated bit values as used for the mask parameter. A zero is +* returned for bits not used in the mask parameter. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR0 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + interruptState = CyEnterCriticalSection(); + + interruptStatus |= CY_VD_PERSISTENT_STATUS_REG; + tmpStatus = interruptStatus & (uint8)(CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); + interruptStatus &= ((uint8)(~mask)); + + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +****************************************************************************//** +* +* Reads the real-time voltage detection status bits in the RESET_SR2 register. +* The bits are set to 1 by the voltage monitor circuit when the supply is +* outside the detector’s trip point, and set to 0 when the supply is inside the +* trip point. +* +* \return +* Status of the LVID, LVIA, and HVIA bits in the RESET_SR2 register. +* Define Definition +* CY_VD_LVID Real-time status of digital LVI. +* CY_VD_LVIA Real-time status of analog LVI. +* CY_VD_HVIA Real-time status of analog HVI. +* +* Side Effects and Restrictions: +* When an LVI reset occurs, the RESET_SR2 status registers are cleared. This +* means that the voltage detection status bits are not persistent across an LVI +* reset and cannot be used to determine a reset source. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG & (CY_VD_LVID | CY_VD_LVIA | CY_VD_HVIA); + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +****************************************************************************//** +* +* Disables the interrupt enable for each interrupt. +* +* \return +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +****************************************************************************//** +* +* Enables interrupts to a given state. +* +* \param uint32 mask: 32 bit mask of interrupts to enable. +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ****************************************************************************//** + * Call this API after a flash row erase/write operation to invalidate or flush + * any of that particular flash region content already present in the cache. + * After a cache flush operation, any access to that flash region after the + * erase/write operation would reload the cache with the modified data from the + * flash region. If the flash region update involves multiple flash row write + * operations, then the flushing of the cache can be done once at the end of + * the operation as long as the flash data would not be accessed in the middle + * of the multiple row update process. Else, flush the cache after every flash + * row write. + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in cache are invalidated on next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + /* Once this is executed it's guaranteed the cache has been flushed */ + (void) CY_CACHE_CONTROL_REG; + + /* Flush the pipeline */ + CY_SYS_ISB; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ****************************************************************************//** + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * \param number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * \param address: Pointer to an interrupt service routine. + * + * \return + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * \param number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * \return + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ****************************************************************************//** + * + * Sets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine + * + * \return + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + * \return + * The address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ****************************************************************************//** + * + * Sets the Priority of the Interrupt. + * + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ****************************************************************************//** + * + * Gets the Priority of the Interrupt. + * + * \param number: The number of the interrupt, 0 - 31. + * + * \return + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ****************************************************************************//** + * + * Gets the enable state of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + * \return + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get state of interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called for all interrupts, other than a reset that gets + * called before the system is setup. + * + * Theory: + * Any value other than zero is acceptable. + * + *******************************************************************************/ + CY_ISR(IntDefaultHandler) + { + #ifdef CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK + CyBoot_IntDefaultHandler_Exception_EntryCallback(); + #endif /* CY_BOOT_INT_DEFAULT_HANDLER_EXCEPTION_ENTRY_CALLBACK */ + + while(1) + { + /*********************************************************************** + * We must not get here. If we do, a serious problem occurs, so go + * into an infinite loop. + ***********************************************************************/ + } + } + + + /******************************************************************************* + * Function Name: IntDefaultHandler + ****************************************************************************//** + * + * This function is called during startup to initialize interrupt address vector + * registers with the address of the IntDefaultHandler(). + * + *******************************************************************************/ + void CyIntInitVectors(void) + { + uint8 i; + + for (i = 0; i <= CY_INT_NUMBER_MAX; i++) + { + CY_SET_REG16(&CY_INT_VECT_TABLE[i], (uint16) &IntDefaultHandler); + } + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ****************************************************************************//** + * + * Sets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * \param address: Pointer to an interrupt service routine + * + * \return + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ****************************************************************************//** + * + * Gets the interrupt vector of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + * \return + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ****************************************************************************//** + * + * Sets the Priority of the Interrupt. + * + * \param priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * \param number: The number of the interrupt, 0 - 31. + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ****************************************************************************//** + * + * Gets the Priority of the Interrupt. + * + * \param number: The number of the interrupt, 0 - 31. + * + * \return + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ****************************************************************************//** + * + * Gets the enable state of the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + * \return + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get state of interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + +#endif /* (CY_PSOC5) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + /******************************************************************************* + * Function Name: CySetScPumps + ****************************************************************************//** + * + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For each enabled SC block set a boost clock index and enable the boost + * clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop the boost clock. + * - For each enabled SC block clear the boost clock index and disable the + * boost clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed the + * parameter. + * + * \param uint8 enable: Enable/disable SC pumps and the boost clock for the enabled + * \param SC block: + * 1 - Enable + * 0 - Disable + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + CyScBoostClk_Start(); + } + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +#if(CY_PSOC5) + /******************************************************************************* + * Function Name: CySysTickStart + ****************************************************************************//** + * + * Configures the SysTick timer to generate interrupt every 1 ms by call to the + * CySysTickInit() function and starts it by calling CySysTickEnable() function. + * Refer to the corresponding function description for the details. + + * \sideeffect + * Clears SysTick count flag if it was set + * + *******************************************************************************/ + void CySysTickStart(void) + { + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); + } + + + /******************************************************************************* + * Function Name: CySysTickInit + ****************************************************************************//** + * + * Initializes the callback addresses with pointers to NULL, associates the + * SysTick system vector with the function that is responsible for calling + * registered callback functions, configures SysTick timer to generate interrupt + * every 1 ms. + * + * \sideeffect + * Clears SysTick count flag if it was set. + * + * The 1 ms interrupt interval is configured based on the frequency determined + * by PSoC Creator at build time. If System clock frequency is changed in + * runtime, the CyDelayFreq() with the appropriate parameter should be called. + * + *******************************************************************************/ + void CySysTickInit(void) + { + uint32 i; + + for (i = 0u; i> CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT) & CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ); + } + + + /******************************************************************************* + * Function Name: CySysTickGetCountFlag + ****************************************************************************//** + * + * The count flag is set once SysTick counter reaches zero. + * The flag cleared on read. + * + * \return + * Returns non-zero value if flag is set, otherwise zero is returned. + * + * + * \sideeffect + * Clears SysTick count flag if it was set. + * + *******************************************************************************/ + uint32 CySysTickGetCountFlag(void) + { + return ((CY_SYS_SYST_CSR_REG >> CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTickClear + ****************************************************************************//** + * + * Clears the SysTick counter for well-defined startup. + * + *******************************************************************************/ + void CySysTickClear(void) + { + CY_SYS_SYST_CVR_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysTickSetCallback + ****************************************************************************//** + * + * This function allows up to five user-defined interrupt service routine + * functions to be associated with the SysTick interrupt. These are specified + * through the use of pointers to the function. + * + * To set a custom callback function without the overhead of the system provided + * one, use CyIntSetSysVector(CY_INT_SYSTICK_IRQN, cyisraddress
), + * where
is address of the custom defined interrupt service routine. + * Note: a custom callback function overrides the system defined callback + * functions. + * + * \param number: The number of the callback function addresses to be set. The valid + * range is from 0 to 4. + * + * void(*CallbackFunction(void): A pointer to the function that will be + * associated with the SysTick ISR for the + * specified number. + * + * \return + * Returns the address of the previous callback function. + * The NULL is returned if the specified address in not set. + * + * \sideeffect + * The registered callback functions will be executed in the interrupt. + * + *******************************************************************************/ + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) + { + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); + } + + + /******************************************************************************* + * Function Name: CySysTickGetCallback + ****************************************************************************//** + * + * The function get the specified callback pointer. + * + * \param number: The number of callback function address to get. The valid + * range is from 0 to 4. + * + * \return + * Returns the address of the specified callback function. + * The NULL is returned if the specified address in not initialized. + * + *******************************************************************************/ + cySysTickCallback CySysTickGetCallback(uint32 number) + { + return ((cySysTickCallback) CySysTickCallbacks[number]); + } + + + /******************************************************************************* + * Function Name: CySysTickServiceCallbacks + ****************************************************************************//** + * + * System Tick timer interrupt routine + * + *******************************************************************************/ + static void CySysTickServiceCallbacks(void) + { + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } + } +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CyGetUniqueId +****************************************************************************//** +* +* Returns the 64-bit unique ID of the device. The uniqueness of the number is +* guaranteed for 10 years due to the die lot number having a cycle life of 10 +* years and even after 10 years, the probability of getting two identical +* numbers is very small. +* +* \param uniqueId: The pointer to a two element 32-bit unsigned integer array. Returns +* the 64-bit unique ID of the device by loading them into the integer array +* pointed to by uniqueId. +* +*******************************************************************************/ +void CyGetUniqueId(uint32* uniqueId) +{ +#if(CY_PSOC4) + uniqueId[0u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT0 ); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT1 ) << 8u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_LOT2 ) << 16u); + uniqueId[0u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_WAFER ) << 24u); + + uniqueId[1u] = (uint32)(* (reg8 *) CYREG_SFLASH_DIE_X ); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_Y ) << 8u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_SORT ) << 16u); + uniqueId[1u] |= ((uint32)(* (reg8 *) CYREG_SFLASH_DIE_MINOR ) << 24u); +#else + uniqueId[0u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_LSB )); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_LOT_MSB )) << 8u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_MLOGIC_REV_ID )) << 16u); + uniqueId[0u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WAFER_NUM )) << 24u); + + uniqueId[1u] = (uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_X_LOC )); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_Y_LOC )) << 8u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_WRK_WK )) << 16u); + uniqueId[1u] |= ((uint32) CY_GET_XTND_REG8((void CYFAR *) (CYREG_FLSHID_CUST_TABLES_FAB_YR )) << 24u); +#endif /* (CY_PSOC4) */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h new file mode 100644 index 0000000..a9042b4 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h @@ -0,0 +1,1320 @@ +/***************************************************************************//** +* \file CyLib.h +* \version 5.50 +* +* \brief Provides the function definitions for the system, clocking, interrupts +* and watchdog timer API. +* +* \note Documentation of the API's in this file is located in the System +* Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; + +void CyXTAL_EnableErrStatus(void) ; +void CyXTAL_DisableErrStatus(void) ; +uint8 CyXTAL_ReadStatus(void) ; +void CyXTAL_EnableFaultRecovery(void) ; +void CyXTAL_DisableFaultRecovery(void) ; + +void CyXTAL_SetFbVoltage(uint8 setting) ; +void CyXTAL_SetWdVoltage(uint8 setting) ; + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +void CySetScPumps(uint8 enable) ; + +#if(CY_PSOC5) + /* Default interrupt handler */ + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC5) + /** System tick timer APIs */ + typedef void (*cySysTickCallback)(void); + + void CySysTickStart(void); + void CySysTickInit(void); + void CySysTickEnable(void); + void CySysTickStop(void); + void CySysTickEnableInterrupt(void); + void CySysTickDisableInterrupt(void); + void CySysTickSetReload(uint32 value); + uint32 CySysTickGetReload(void); + uint32 CySysTickGetValue(void); + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); + cySysTickCallback CySysTickGetCallback(uint32 number); + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetCountFlag(void); + void CySysTickClear(void); +#endif /* (CY_PSOC5) */ + +void CyGetUniqueId(uint32* uniqueId); + + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) +#define CY_VD_INT_MASK ((uint32) (0x01u)) + + +/******************************************************************************* +* Variable VDDA API Constants +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution API Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + + +/* CyILO_SetPowerMode() */ +#define CY_ILO_CONTROL_PD_MODE (0x10u) +#define CY_ILO_CONTROL_PD_POSITION (4u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) + + +/* CyIMO_Start() */ +#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) +#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) +#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) + +#define CY_LIB_IMO_3MHZ_VALUE (0x03u) +#define CY_LIB_IMO_6MHZ_VALUE (0x01u) +#define CY_LIB_IMO_12MHZ_VALUE (0x00u) +#define CY_LIB_IMO_24MHZ_VALUE (0x02u) +#define CY_LIB_IMO_48MHZ_VALUE (0x04u) +#define CY_LIB_IMO_62MHZ_VALUE (0x05u) +#define CY_LIB_IMO_74MHZ_VALUE (0x06u) + + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#define CY_IMO_FREQ_62MHZ (5u) +#if(CY_PSOC5) + #define CY_IMO_FREQ_74MHZ (6u) +#endif /* (CY_PSOC5) */ +#define CY_IMO_FREQ_USB (8u) + +#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) + + +/* CyCpuClk_SetDivider() */ +#define CY_LIB_CLKDIST_DIV_POSITION (4u) +#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) + + +/* CyIMO_SetTrimValue() */ +#define CY_LIB_USB_CLK_EN (0x02u) + + +/* CyPLL_OUT_SetSource() - parameters */ +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + + +/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ +#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) + + +/* CyUsbClk_SetSource() */ +#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) + + +/* CyUsbClk_SetSource() - parameters */ +#define CY_LIB_USB_CLK_IMO2X (0x00u) +#define CY_LIB_USB_CLK_IMO (0x01u) +#define CY_LIB_USB_CLK_PLL (0x02u) +#define CY_LIB_USB_CLK_DSI (0x03u) + + +/* CyUSB_PowerOnCheck() */ +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +#if(CY_PSOC5) + + /*************************************************************************** + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed. + ***************************************************************************/ + + #if defined(__ARMCC_VERSION) + #define CY_SYS_ISB __isb(0x0f) + #else /* ASM for GCC & IAR */ + #define CY_SYS_ISB __asm volatile ("isb \n") + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* System Registers +*******************************************************************************/ + +/* Software Reset Control Register */ +#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) +#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) + +/* Timewheel Configuration Register 0 */ +#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) +#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) + +/* Timewheel Configuration Register 2 */ +#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) +#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) + +/* USB Configuration Register */ +#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) + +/* Internal Main Oscillator Trim Register 1 */ +#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) +#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) + +/* USB control 1 Register */ +#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) +#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) +#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) +#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 5 */ +#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + +/* CyIMO_SetTrimValue() */ +#if(CY_PSOC3) + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + + /* System tick registers */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +****************************************************************************//** +* The macro that evaluates the expression and if it is false (evaluates to 0) +* then the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* \param expr: Logical expression. Asserts if false. +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) || defined (__ICCARM__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) +#define CY_LIB_RESET_CR2_RESET (0x01u) + +#if(CY_PSOC5) + /* System tick API constants */ + #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) + #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u)) + #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) + #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u)) + #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_CVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u)) +#endif /* (CY_PSOC5) */ + + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + +#if(CY_PSOC5) + + /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ + #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ + #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ + #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */ + #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */ + #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */ + #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ + #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */ + #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ + #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + +#endif /* (CY_PSOC5) */ + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ****************************************************************************//** + * + * Enables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ****************************************************************************//** + * + * Disables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ****************************************************************************//** + * + * Forces the specified interrupt number to be pending. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ****************************************************************************//** + * + * Clears any pending interrupt for the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ****************************************************************************//** + * + * Enables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ****************************************************************************//** + * + * Disables the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ****************************************************************************//** + * + * Forces the specified interrupt number to be pending. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ****************************************************************************//** + * Clears any pending interrupt for the specified interrupt number. + * + * \param number: Valid range [0-31]. Interrupt number. + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ + +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + + +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + + +#define IMO_PM_ENABLE (0x10u) +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define ILO_CONTROL_PD_MODE (0x10u) +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) +#define FTW_CLEAR_ALL_BITS (0x00u) +#define FTW_CLEAR_FTW_BITS (0xFCu) +#define FTW_ENABLE (0x01u) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c new file mode 100644 index 0000000..bc868a7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c @@ -0,0 +1,693 @@ +/***************************************************************************//** +* \file CySpc.c +* \version 5.50 +* +* \brief Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint32 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CySpcStart +****************************************************************************//** +* Starts the SPC. +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +****************************************************************************//** +* Stops the SPC. +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +****************************************************************************//** +* Reads data from the SPC. +* +* \param uint8 buffer: +* Address to store data read. +* +* \param uint8 size: +* Number of bytes to read from the SPC. +* +* \return +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +****************************************************************************//** +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 address: +* Flash/eeprom addrress +* +* \param uint8* buffer: +* Data to load to the row latch +* +* \param uint16 number: +* Number bytes to load. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ + +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +****************************************************************************//** +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The buffer pointer should point to the data that should be written to the +* flash row directly (no data in ECC/flash will be preserved). It is Flash API +* responsibility to prepare data: the preserved data are copied from flash into +* array with the modified data. +* +* \param uint8 array: +* Id of the array. +* +* \param uint8* buffer: +* Data to be loaded to the row latch +* +* \param uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRowFull +****************************************************************************//** +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The only data that are going to be changed should be passed. The function +* will handle unmodified data preservation based on DWR settings and input +* parameters. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 row: +* Flash row number to be loaded. +* +* \param uint8* buffer: +* Data to be loaded to the row latch +* +* \param uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ + +{ + cystatus status = CYRET_STARTED; + uint16 i; + + #if (CYDEV_ECC_ENABLE == 0) + uint32 offset; + #endif /* (CYDEV_ECC_ENABLE == 0) */ + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" and "Store Configuration + * Data in ECC" DWR options are disabled, ECC section is available + * for user data. + *******************************************************************/ + #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************* + * If size parameter equals size of the ECC row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the ECC section. + * In this case flash data must be preserved. The flash data copied + * from flash data section to the SPC data register. + *******************************************************************/ + if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_FLS_BASE + + ((uint32) array * CYDEV_FLS_SECTOR_SIZE) + + ((uint32) row * CYDEV_FLS_ROW_SIZE ); + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" DWR option is disabled, + * ECC section can be used for storing device configuration data + * ("Store Configuration Data in ECC" DWR option is enabled) or for + * storing user data in the ECC section ("Store Configuration Data in + * ECC" DWR option is enabled). In both cases, the data in the ECC + * section must be preserved if flash data is written. + *******************************************************************/ + #if (CYDEV_ECC_ENABLE == 0) + + + /******************************************************************* + * If size parameter equals size of the flash row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the flash data + * section. In this case, ECC section data must be preserved. + * The ECC section data copied from ECC section to the SPC data + * register. + *******************************************************************/ + if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_ECC_BASE + + ((uint32) array * CYDEV_ECC_SECTOR_SIZE) + + ((uint32) row * CYDEV_ECC_ROW_SIZE ); + + for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #else + + if(0u != row) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CYDEV_ECC_ENABLE == 0) */ + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +****************************************************************************//** +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* \param uint8 array: +* Id of the array. +* +* \param uint16 address: +* flash/eeprom addrress +* +* \param uint8 tempPolarity: +* temperature polarity. +* \param 1: the Temp Magnitude is interpreted as a positive value +* \param 0: the Temp Magnitude is interpreted as a negative value +* +* \param uint8 tempMagnitude: +* temperature magnitude. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +****************************************************************************//** +* Erases all data in the addressed sector (block of 64 rows). +* +* \param uint8 array: +* Id of the array. +* +* \param uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +****************************************************************************//** +* Returns the internal die temperature +* +* \param uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* \param uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* \param uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* \return +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetTemp(uint8 numSamples) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +****************************************************************************//** +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* \return +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +****************************************************************************//** +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcGetAlgorithm +****************************************************************************//** +* Downloads SPC algorithm from SPC SROM into SRAM. +* +* \return +* CYRET_STARTED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetAlgorithm(void) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM; + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + +/* [] END OF FILE */ + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h new file mode 100644 index 0000000..ad431cf --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h @@ -0,0 +1,168 @@ +/***************************************************************************//** +* \file CySpc.c +* \version 5.50 +* +* \brief Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ +; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ +; +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); +cystatus CySpcGetTemp(uint8 numSamples); +cystatus CySpcGetAlgorithm(void); +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c new file mode 100644 index 0000000..ba36af7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.c @@ -0,0 +1,774 @@ +/******************************************************************************* +* File Name: Debug_Timer.c +* Version 2.70 +* +* Description: +* The Timer component consists of a 8, 16, 24 or 32-bit timer with +* a selectable period between 2 and 2^Width - 1. The timer may free run +* or be used as a capture timer as well. The capture can be initiated +* by a positive or negative edge signal as well as via software. +* A trigger input can be programmed to enable the timer on rising edge +* falling edge, either edge or continous run. +* Interrupts may be generated due to a terminal count condition +* or a capture event. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Debug_Timer.h" + +uint8 Debug_Timer_initVar = 0u; + + +/******************************************************************************* +* Function Name: Debug_Timer_Init +******************************************************************************** +* +* Summary: +* Initialize to the schematic state +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_Init(void) +{ + #if(!Debug_Timer_UsingFixedFunction) + /* Interrupt State Backup for Critical Region*/ + uint8 Debug_Timer_interruptState; + #endif /* Interrupt state back up for Fixed Function only */ + + #if (Debug_Timer_UsingFixedFunction) + /* Clear all bits but the enable bit (if it's already set) for Timer operation */ + Debug_Timer_CONTROL &= Debug_Timer_CTRL_ENABLE; + + /* Clear the mode bits for continuous run mode */ + #if (CY_PSOC5A) + Debug_Timer_CONTROL2 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK)); + #endif /* Clear bits in CONTROL2 only in PSOC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_MODE_MASK)); + #endif /* CONTROL3 register exists only in PSoC3 OR PSoC5LP */ + + /* Check if One Shot mode is enabled i.e. RunMode !=0*/ + #if (Debug_Timer_RunModeUsed != 0x0u) + /* Set 3rd bit of Control register to enable one shot mode */ + Debug_Timer_CONTROL |= 0x04u; + #endif /* One Shot enabled only when RunModeUsed is not Continuous*/ + + #if (Debug_Timer_RunModeUsed == 2) + #if (CY_PSOC5A) + /* Set last 2 bits of control2 register if one shot(halt on + interrupt) is enabled*/ + Debug_Timer_CONTROL2 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Set last 2 bits of control3 register if one shot(halt on + interrupt) is enabled*/ + Debug_Timer_CONTROL3 |= 0x03u; + #endif /* Set One-Shot Halt on Interrupt bit in CONTROL3 for PSoC3 or PSoC5LP */ + + #endif /* Remove section if One Shot Halt on Interrupt is not enabled */ + + #if (Debug_Timer_UsingHWEnable != 0) + #if (CY_PSOC5A) + /* Set the default Run Mode of the Timer to Continuous */ + Debug_Timer_CONTROL2 |= Debug_Timer_CTRL_MODE_PULSEWIDTH; + #endif /* Set Continuous Run Mode in CONTROL2 for PSoC5A */ + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Clear and Set ROD and COD bits of CFG2 register */ + Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_RCOD_MASK)); + Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_RCOD; + + /* Clear and Enable the HW enable bit in CFG2 register */ + Debug_Timer_CONTROL3 &= ((uint8)(~Debug_Timer_CTRL_ENBL_MASK)); + Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_ENBL; + + /* Set the default Run Mode of the Timer to Continuous */ + Debug_Timer_CONTROL3 |= Debug_Timer_CTRL_MODE_CONTINUOUS; + #endif /* Set Continuous Run Mode in CONTROL3 for PSoC3ES3 or PSoC5A */ + + #endif /* Configure Run Mode with hardware enable */ + + /* Clear and Set SYNCTC and SYNCCMP bits of RT1 register */ + Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_RT1_MASK)); + Debug_Timer_RT1 |= Debug_Timer_SYNC; + + /*Enable DSI Sync all all inputs of the Timer*/ + Debug_Timer_RT1 &= ((uint8)(~Debug_Timer_SYNCDSI_MASK)); + Debug_Timer_RT1 |= Debug_Timer_SYNCDSI_EN; + + /* Set the IRQ to use the status register interrupts */ + Debug_Timer_CONTROL2 |= Debug_Timer_CTRL2_IRQ_SEL; + #endif /* Configuring registers of fixed function implementation */ + + /* Set Initial values from Configuration */ + Debug_Timer_WritePeriod(Debug_Timer_INIT_PERIOD); + Debug_Timer_WriteCounter(Debug_Timer_INIT_PERIOD); + + #if (Debug_Timer_UsingHWCaptureCounter)/* Capture counter is enabled */ + Debug_Timer_CAPTURE_COUNT_CTRL |= Debug_Timer_CNTR_ENABLE; + Debug_Timer_SetCaptureCount(Debug_Timer_INIT_CAPTURE_COUNT); + #endif /* Configure capture counter value */ + + #if (!Debug_Timer_UsingFixedFunction) + #if (Debug_Timer_SoftwareCaptureMode) + Debug_Timer_SetCaptureMode(Debug_Timer_INIT_CAPTURE_MODE); + #endif /* Set Capture Mode for UDB implementation if capture mode is software controlled */ + + #if (Debug_Timer_SoftwareTriggerMode) + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + if (0u == (Debug_Timer_CONTROL & Debug_Timer__B_TIMER__TM_SOFTWARE)) + { + Debug_Timer_SetTriggerMode(Debug_Timer_INIT_TRIGGER_MODE); + } + #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ + #endif /* Set trigger mode for UDB Implementation if trigger mode is software controlled */ + + /* CyEnterCriticalRegion and CyExitCriticalRegion are used to mark following region critical*/ + /* Enter Critical Region*/ + Debug_Timer_interruptState = CyEnterCriticalSection(); + + /* Use the interrupt output of the status register for IRQ output */ + Debug_Timer_STATUS_AUX_CTRL |= Debug_Timer_STATUS_ACTL_INT_EN_MASK; + + /* Exit Critical Region*/ + CyExitCriticalSection(Debug_Timer_interruptState); + + #if (Debug_Timer_EnableTriggerMode) + Debug_Timer_EnableTrigger(); + #endif /* Set Trigger enable bit for UDB implementation in the control register*/ + + + #if (Debug_Timer_InterruptOnCaptureCount && !Debug_Timer_UDB_CONTROL_REG_REMOVED) + Debug_Timer_SetInterruptCount(Debug_Timer_INIT_INT_CAPTURE_COUNT); + #endif /* Set interrupt count in UDB implementation if interrupt count feature is checked.*/ + + Debug_Timer_ClearFIFO(); + #endif /* Configure additional features of UDB implementation */ + + Debug_Timer_SetInterruptMode(Debug_Timer_INIT_INTERRUPT_MODE); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Enable +******************************************************************************** +* +* Summary: +* Enable the Timer +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_Enable(void) +{ + /* Globally Enable the Fixed Function Block chosen */ + #if (Debug_Timer_UsingFixedFunction) + Debug_Timer_GLOBAL_ENABLE |= Debug_Timer_BLOCK_EN_MASK; + Debug_Timer_GLOBAL_STBY_ENABLE |= Debug_Timer_BLOCK_STBY_EN_MASK; + #endif /* Set Enable bit for enabling Fixed function timer*/ + + /* Remove assignment if control register is removed */ + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction) + Debug_Timer_CONTROL |= Debug_Timer_CTRL_ENABLE; + #endif /* Remove assignment if control register is removed */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Start +******************************************************************************** +* +* Summary: +* The start function initializes the timer with the default values, the +* enables the timerto begin counting. It does not enable interrupts, +* the EnableInt command should be called if interrupt generation is required. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Debug_Timer_initVar: Is modified when this function is called for the +* first time. Is used to ensure that initialization happens only once. +* +*******************************************************************************/ +void Debug_Timer_Start(void) +{ + if(Debug_Timer_initVar == 0u) + { + Debug_Timer_Init(); + + Debug_Timer_initVar = 1u; /* Clear this bit for Initialization */ + } + + /* Enable the Timer */ + Debug_Timer_Enable(); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Stop +******************************************************************************** +* +* Summary: +* The stop function halts the timer, but does not change any modes or disable +* interrupts. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: If the Enable mode is set to Hardware only then this function +* has no effect on the operation of the timer. +* +*******************************************************************************/ +void Debug_Timer_Stop(void) +{ + /* Disable Timer */ + #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED || Debug_Timer_UsingFixedFunction) + Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_ENABLE)); + #endif /* Remove assignment if control register is removed */ + + /* Globally disable the Fixed Function Block chosen */ + #if (Debug_Timer_UsingFixedFunction) + Debug_Timer_GLOBAL_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_EN_MASK)); + Debug_Timer_GLOBAL_STBY_ENABLE &= ((uint8)(~Debug_Timer_BLOCK_STBY_EN_MASK)); + #endif /* Disable global enable for the Timer Fixed function block to stop the Timer*/ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_SetInterruptMode +******************************************************************************** +* +* Summary: +* This function selects which of the interrupt inputs may cause an interrupt. +* The twosources are caputure and terminal. One, both or neither may +* be selected. +* +* Parameters: +* interruptMode: This parameter is used to enable interrups on either/or +* terminal count or capture. +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_SetInterruptMode(uint8 interruptMode) +{ + Debug_Timer_STATUS_MASK = interruptMode; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_SoftwareCapture +******************************************************************************** +* +* Summary: +* This function forces a capture independent of the capture signal. +* +* Parameters: +* void +* +* Return: +* void +* +* Side Effects: +* An existing hardware capture could be overwritten. +* +*******************************************************************************/ +void Debug_Timer_SoftwareCapture(void) +{ + /* Generate a software capture by reading the counter register */ + #if(Debug_Timer_UsingFixedFunction) + (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR); + #else + (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT); + #endif/* (Debug_Timer_UsingFixedFunction) */ + /* Capture Data is now in the FIFO */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadStatusRegister +******************************************************************************** +* +* Summary: +* Reads the status register and returns it's state. This function should use +* defined types for the bit-field information as the bits in this register may +* be permuteable. +* +* Parameters: +* void +* +* Return: +* The contents of the status register +* +* Side Effects: +* Status register bits may be clear on read. +* +*******************************************************************************/ +uint8 Debug_Timer_ReadStatusRegister(void) +{ + return (Debug_Timer_STATUS); +} + + +#if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove API if control register is unused */ + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadControlRegister +******************************************************************************** +* +* Summary: +* Reads the control register and returns it's value. +* +* Parameters: +* void +* +* Return: +* The contents of the control register +* +*******************************************************************************/ +uint8 Debug_Timer_ReadControlRegister(void) +{ + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + return ((uint8)Debug_Timer_CONTROL); + #else + return (0); + #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_WriteControlRegister +******************************************************************************** +* +* Summary: +* Sets the bit-field of the control register. +* +* Parameters: +* control: The contents of the control register +* +* Return: +* +*******************************************************************************/ +void Debug_Timer_WriteControlRegister(uint8 control) +{ + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + Debug_Timer_CONTROL = control; + #else + control = 0u; + #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ +} + +#endif /* Remove API if control register is unused */ + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadPeriod +******************************************************************************** +* +* Summary: +* This function returns the current value of the Period. +* +* Parameters: +* void +* +* Return: +* The present value of the counter. +* +*******************************************************************************/ +uint16 Debug_Timer_ReadPeriod(void) +{ + #if(Debug_Timer_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR)); + #else + return (CY_GET_REG16(Debug_Timer_PERIOD_LSB_PTR)); + #endif /* (Debug_Timer_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_WritePeriod +******************************************************************************** +* +* Summary: +* This function is used to change the period of the counter. The new period +* will be loaded the next time terminal count is detected. +* +* Parameters: +* period: This value may be between 1 and (2^Resolution)-1. A value of 0 will +* result in the counter remaining at zero. +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_WritePeriod(uint16 period) +{ + #if(Debug_Timer_UsingFixedFunction) + uint16 period_temp = (uint16)period; + CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period_temp); + #else + CY_SET_REG16(Debug_Timer_PERIOD_LSB_PTR, period); + #endif /*Write Period value with appropriate resolution suffix depending on UDB or fixed function implementation */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadCapture +******************************************************************************** +* +* Summary: +* This function returns the last value captured. +* +* Parameters: +* void +* +* Return: +* Present Capture value. +* +*******************************************************************************/ +uint16 Debug_Timer_ReadCapture(void) +{ + #if(Debug_Timer_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR)); + #endif /* (Debug_Timer_UsingFixedFunction) */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_WriteCounter +******************************************************************************** +* +* Summary: +* This funtion is used to set the counter to a specific value +* +* Parameters: +* counter: New counter value. +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_WriteCounter(uint16 counter) +{ + #if(Debug_Timer_UsingFixedFunction) + /* This functionality is removed until a FixedFunction HW update to + * allow this register to be written + */ + CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, (uint16)counter); + + #else + CY_SET_REG16(Debug_Timer_COUNTER_LSB_PTR, counter); + #endif /* Set Write Counter only for the UDB implementation (Write Counter not available in fixed function Timer */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadCounter +******************************************************************************** +* +* Summary: +* This function returns the current counter value. +* +* Parameters: +* void +* +* Return: +* Present compare value. +* +*******************************************************************************/ +uint16 Debug_Timer_ReadCounter(void) +{ + /* Force capture by reading Accumulator */ + /* Must first do a software capture to be able to read the counter */ + /* It is up to the user code to make sure there isn't already captured data in the FIFO */ + #if(Debug_Timer_UsingFixedFunction) + (void)CY_GET_REG16(Debug_Timer_COUNTER_LSB_PTR); + #else + (void)CY_GET_REG8(Debug_Timer_COUNTER_LSB_PTR_8BIT); + #endif/* (Debug_Timer_UsingFixedFunction) */ + + /* Read the data from the FIFO (or capture register for Fixed Function)*/ + #if(Debug_Timer_UsingFixedFunction) + return ((uint16)CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR)); + #else + return (CY_GET_REG16(Debug_Timer_CAPTURE_LSB_PTR)); + #endif /* (Debug_Timer_UsingFixedFunction) */ +} + + +#if(!Debug_Timer_UsingFixedFunction) /* UDB Specific Functions */ + + +/******************************************************************************* + * The functions below this point are only available using the UDB + * implementation. If a feature is selected, then the API is enabled. + ******************************************************************************/ + + +#if (Debug_Timer_SoftwareCaptureMode) + + +/******************************************************************************* +* Function Name: Debug_Timer_SetCaptureMode +******************************************************************************** +* +* Summary: +* This function sets the capture mode to either rising or falling edge. +* +* Parameters: +* captureMode: This parameter sets the capture mode of the UDB capture feature +* The parameter values are defined using the +* #define Debug_Timer__B_TIMER__CM_NONE 0 +#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1 +#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2 +#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3 +#define Debug_Timer__B_TIMER__CM_SOFTWARE 4 + identifiers +* The following are the possible values of the parameter +* Debug_Timer__B_TIMER__CM_NONE - Set Capture mode to None +* Debug_Timer__B_TIMER__CM_RISINGEDGE - Rising edge of Capture input +* Debug_Timer__B_TIMER__CM_FALLINGEDGE - Falling edge of Capture input +* Debug_Timer__B_TIMER__CM_EITHEREDGE - Either edge of Capture input +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_SetCaptureMode(uint8 captureMode) +{ + /* This must only set to two bits of the control register associated */ + captureMode = ((uint8)((uint8)captureMode << Debug_Timer_CTRL_CAP_MODE_SHIFT)); + captureMode &= (Debug_Timer_CTRL_CAP_MODE_MASK); + + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + /* Clear the Current Setting */ + Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_CAP_MODE_MASK)); + + /* Write The New Setting */ + Debug_Timer_CONTROL |= captureMode; + #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ +} +#endif /* Remove API if Capture Mode is not Software Controlled */ + + +#if (Debug_Timer_SoftwareTriggerMode) + + +/******************************************************************************* +* Function Name: Debug_Timer_SetTriggerMode +******************************************************************************** +* +* Summary: +* This function sets the trigger input mode +* +* Parameters: +* triggerMode: Pass one of the pre-defined Trigger Modes (except Software) + #define Debug_Timer__B_TIMER__TM_NONE 0x00u + #define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u + #define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u + #define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu + #define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_SetTriggerMode(uint8 triggerMode) +{ + /* This must only set to two bits of the control register associated */ + triggerMode &= Debug_Timer_CTRL_TRIG_MODE_MASK; + + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */ + + /* Clear the Current Setting */ + Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_MODE_MASK)); + + /* Write The New Setting */ + Debug_Timer_CONTROL |= (triggerMode | Debug_Timer__B_TIMER__TM_SOFTWARE); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API if Trigger Mode is not Software Controlled */ + +#if (Debug_Timer_EnableTriggerMode) + + +/******************************************************************************* +* Function Name: Debug_Timer_EnableTrigger +******************************************************************************** +* +* Summary: +* Sets the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_EnableTrigger(void) +{ + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) /* Remove assignment if control register is removed */ + Debug_Timer_CONTROL |= Debug_Timer_CTRL_TRIG_EN; + #endif /* Remove code section if control register is not used */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_DisableTrigger +******************************************************************************** +* +* Summary: +* Clears the control bit enabling Hardware Trigger mode +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_DisableTrigger(void) +{ + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED ) /* Remove assignment if control register is removed */ + Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_TRIG_EN)); + #endif /* Remove code section if control register is not used */ +} +#endif /* Remove API is Trigger Mode is set to None */ + +#if(Debug_Timer_InterruptOnCaptureCount) + + +/******************************************************************************* +* Function Name: Debug_Timer_SetInterruptCount +******************************************************************************** +* +* Summary: +* This function sets the capture count before an interrupt is triggered. +* +* Parameters: +* interruptCount: A value between 0 and 3 is valid. If the value is 0, then +* an interrupt will occur each time a capture occurs. +* A value of 1 to 3 will cause the interrupt +* to delay by the same number of captures. +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_SetInterruptCount(uint8 interruptCount) +{ + /* This must only set to two bits of the control register associated */ + interruptCount &= Debug_Timer_CTRL_INTCNT_MASK; + + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + /* Clear the Current Setting */ + Debug_Timer_CONTROL &= ((uint8)(~Debug_Timer_CTRL_INTCNT_MASK)); + /* Write The New Setting */ + Debug_Timer_CONTROL |= interruptCount; + #endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ +} +#endif /* Debug_Timer_InterruptOnCaptureCount */ + + +#if (Debug_Timer_UsingHWCaptureCounter) + + +/******************************************************************************* +* Function Name: Debug_Timer_SetCaptureCount +******************************************************************************** +* +* Summary: +* This function sets the capture count +* +* Parameters: +* captureCount: A value between 2 and 127 inclusive is valid. A value of 1 +* to 127 will cause the interrupt to delay by the same number of +* captures. +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_SetCaptureCount(uint8 captureCount) +{ + Debug_Timer_CAP_COUNT = captureCount; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_ReadCaptureCount +******************************************************************************** +* +* Summary: +* This function reads the capture count setting +* +* Parameters: +* void +* +* Return: +* Returns the Capture Count Setting +* +*******************************************************************************/ +uint8 Debug_Timer_ReadCaptureCount(void) +{ + return ((uint8)Debug_Timer_CAP_COUNT); +} +#endif /* Debug_Timer_UsingHWCaptureCounter */ + + +/******************************************************************************* +* Function Name: Debug_Timer_ClearFIFO +******************************************************************************** +* +* Summary: +* This function clears all capture data from the capture FIFO +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +void Debug_Timer_ClearFIFO(void) +{ + while(0u != (Debug_Timer_ReadStatusRegister() & Debug_Timer_STATUS_FIFONEMP)) + { + (void)Debug_Timer_ReadCapture(); + } +} + +#endif /* UDB Specific Functions */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h new file mode 100644 index 0000000..2a8742c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer.h @@ -0,0 +1,434 @@ +/******************************************************************************* +* File Name: Debug_Timer.h +* Version 2.70 +* +* Description: +* Contains the function prototypes and constants available to the timer +* user module. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CY_Timer_v2_60_Debug_Timer_H) +#define CY_Timer_v2_60_Debug_Timer_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + +extern uint8 Debug_Timer_initVar; + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component Timer_v2_70 requires cy_boot v3.0 or later +#endif /* (CY_ PSOC5LP) */ + + +/************************************** +* Parameter Defaults +**************************************/ + +#define Debug_Timer_Resolution 16u +#define Debug_Timer_UsingFixedFunction 1u +#define Debug_Timer_UsingHWCaptureCounter 0u +#define Debug_Timer_SoftwareCaptureMode 0u +#define Debug_Timer_SoftwareTriggerMode 0u +#define Debug_Timer_UsingHWEnable 0u +#define Debug_Timer_EnableTriggerMode 0u +#define Debug_Timer_InterruptOnCaptureCount 0u +#define Debug_Timer_RunModeUsed 0u +#define Debug_Timer_ControlRegRemoved 0u + +#if defined(Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG) + #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u) +#elif (Debug_Timer_UsingFixedFunction) + #define Debug_Timer_UDB_CONTROL_REG_REMOVED (0u) +#else + #define Debug_Timer_UDB_CONTROL_REG_REMOVED (1u) +#endif /* End Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG */ + + +/*************************************** +* Type defines +***************************************/ + + +/************************************************************************** + * Sleep Wakeup Backup structure for Timer Component + *************************************************************************/ +typedef struct +{ + uint8 TimerEnableState; + #if(!Debug_Timer_UsingFixedFunction) + + uint16 TimerUdb; + uint8 InterruptMaskValue; + #if (Debug_Timer_UsingHWCaptureCounter) + uint8 TimerCaptureCounter; + #endif /* variable declarations for backing up non retention registers in CY_UDB_V1 */ + + #if (!Debug_Timer_UDB_CONTROL_REG_REMOVED) + uint8 TimerControlRegister; + #endif /* variable declaration for backing up enable state of the Timer */ + #endif /* define backup variables only for UDB implementation. Fixed function registers are all retention */ + +}Debug_Timer_backupStruct; + + +/*************************************** +* Function Prototypes +***************************************/ + +void Debug_Timer_Start(void) ; +void Debug_Timer_Stop(void) ; + +void Debug_Timer_SetInterruptMode(uint8 interruptMode) ; +uint8 Debug_Timer_ReadStatusRegister(void) ; +/* Deprecated function. Do not use this in future. Retained for backward compatibility */ +#define Debug_Timer_GetInterruptSource() Debug_Timer_ReadStatusRegister() + +#if(!Debug_Timer_UDB_CONTROL_REG_REMOVED) + uint8 Debug_Timer_ReadControlRegister(void) ; + void Debug_Timer_WriteControlRegister(uint8 control) ; +#endif /* (!Debug_Timer_UDB_CONTROL_REG_REMOVED) */ + +uint16 Debug_Timer_ReadPeriod(void) ; +void Debug_Timer_WritePeriod(uint16 period) ; +uint16 Debug_Timer_ReadCounter(void) ; +void Debug_Timer_WriteCounter(uint16 counter) ; +uint16 Debug_Timer_ReadCapture(void) ; +void Debug_Timer_SoftwareCapture(void) ; + +#if(!Debug_Timer_UsingFixedFunction) /* UDB Prototypes */ + #if (Debug_Timer_SoftwareCaptureMode) + void Debug_Timer_SetCaptureMode(uint8 captureMode) ; + #endif /* (!Debug_Timer_UsingFixedFunction) */ + + #if (Debug_Timer_SoftwareTriggerMode) + void Debug_Timer_SetTriggerMode(uint8 triggerMode) ; + #endif /* (Debug_Timer_SoftwareTriggerMode) */ + + #if (Debug_Timer_EnableTriggerMode) + void Debug_Timer_EnableTrigger(void) ; + void Debug_Timer_DisableTrigger(void) ; + #endif /* (Debug_Timer_EnableTriggerMode) */ + + + #if(Debug_Timer_InterruptOnCaptureCount) + void Debug_Timer_SetInterruptCount(uint8 interruptCount) ; + #endif /* (Debug_Timer_InterruptOnCaptureCount) */ + + #if (Debug_Timer_UsingHWCaptureCounter) + void Debug_Timer_SetCaptureCount(uint8 captureCount) ; + uint8 Debug_Timer_ReadCaptureCount(void) ; + #endif /* (Debug_Timer_UsingHWCaptureCounter) */ + + void Debug_Timer_ClearFIFO(void) ; +#endif /* UDB Prototypes */ + +/* Sleep Retention APIs */ +void Debug_Timer_Init(void) ; +void Debug_Timer_Enable(void) ; +void Debug_Timer_SaveConfig(void) ; +void Debug_Timer_RestoreConfig(void) ; +void Debug_Timer_Sleep(void) ; +void Debug_Timer_Wakeup(void) ; + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* Enumerated Type B_Timer__CaptureModes, Used in Capture Mode */ +#define Debug_Timer__B_TIMER__CM_NONE 0 +#define Debug_Timer__B_TIMER__CM_RISINGEDGE 1 +#define Debug_Timer__B_TIMER__CM_FALLINGEDGE 2 +#define Debug_Timer__B_TIMER__CM_EITHEREDGE 3 +#define Debug_Timer__B_TIMER__CM_SOFTWARE 4 + + + +/* Enumerated Type B_Timer__TriggerModes, Used in Trigger Mode */ +#define Debug_Timer__B_TIMER__TM_NONE 0x00u +#define Debug_Timer__B_TIMER__TM_RISINGEDGE 0x04u +#define Debug_Timer__B_TIMER__TM_FALLINGEDGE 0x08u +#define Debug_Timer__B_TIMER__TM_EITHEREDGE 0x0Cu +#define Debug_Timer__B_TIMER__TM_SOFTWARE 0x10u + + +/*************************************** +* Initialial Parameter Constants +***************************************/ + +#define Debug_Timer_INIT_PERIOD 31999u +#define Debug_Timer_INIT_CAPTURE_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_CAP_MODE_SHIFT)) +#define Debug_Timer_INIT_TRIGGER_MODE ((uint8)((uint8)0u << Debug_Timer_CTRL_TRIG_MODE_SHIFT)) +#if (Debug_Timer_UsingFixedFunction) + #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT))) +#else + #define Debug_Timer_INIT_INTERRUPT_MODE (((uint8)((uint8)0u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) | \ + ((uint8)((uint8)0 << Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT))) +#endif /* (Debug_Timer_UsingFixedFunction) */ +#define Debug_Timer_INIT_CAPTURE_COUNT (2u) +#define Debug_Timer_INIT_INT_CAPTURE_COUNT ((uint8)((uint8)(1u - 1u) << Debug_Timer_CTRL_INTCNT_SHIFT)) + + +/*************************************** +* Registers +***************************************/ + +#if (Debug_Timer_UsingFixedFunction) /* Implementation Specific Registers and Register Constants */ + + + /*************************************** + * Fixed Function Registers + ***************************************/ + + #define Debug_Timer_STATUS (*(reg8 *) Debug_Timer_TimerHW__SR0 ) + /* In Fixed Function Block Status and Mask are the same register */ + #define Debug_Timer_STATUS_MASK (*(reg8 *) Debug_Timer_TimerHW__SR0 ) + #define Debug_Timer_CONTROL (*(reg8 *) Debug_Timer_TimerHW__CFG0) + #define Debug_Timer_CONTROL2 (*(reg8 *) Debug_Timer_TimerHW__CFG1) + #define Debug_Timer_CONTROL2_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG1) + #define Debug_Timer_RT1 (*(reg8 *) Debug_Timer_TimerHW__RT1) + #define Debug_Timer_RT1_PTR ( (reg8 *) Debug_Timer_TimerHW__RT1) + + #if (CY_PSOC3 || CY_PSOC5LP) + #define Debug_Timer_CONTROL3 (*(reg8 *) Debug_Timer_TimerHW__CFG2) + #define Debug_Timer_CONTROL3_PTR ( (reg8 *) Debug_Timer_TimerHW__CFG2) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + #define Debug_Timer_GLOBAL_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_ACT_CFG) + #define Debug_Timer_GLOBAL_STBY_ENABLE (*(reg8 *) Debug_Timer_TimerHW__PM_STBY_CFG) + + #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerHW__CAP0 ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CAP0 ) + #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerHW__PER0 ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__PER0 ) + #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerHW__CNT_CMP0 ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerHW__CNT_CMP0 ) + + + /*************************************** + * Register Constants + ***************************************/ + + /* Fixed Function Block Chosen */ + #define Debug_Timer_BLOCK_EN_MASK Debug_Timer_TimerHW__PM_ACT_MSK + #define Debug_Timer_BLOCK_STBY_EN_MASK Debug_Timer_TimerHW__PM_STBY_MSK + + /* Control Register Bit Locations */ + /* Interrupt Count - Not valid for Fixed Function Block */ + #define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u + /* Trigger Polarity - Not valid for Fixed Function Block */ + #define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x00u + /* Trigger Enable - Not valid for Fixed Function Block */ + #define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x00u + /* Capture Polarity - Not valid for Fixed Function Block */ + #define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x00u + /* Timer Enable - As defined in Register Map, part of TMRX_CFG0 register */ + #define Debug_Timer_CTRL_ENABLE_SHIFT 0x00u + + /* Control Register Bit Masks */ + #define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT)) + + /* Control2 Register Bit Masks */ + /* As defined in Register Map, Part of the TMRX_CFG1 register */ + #define Debug_Timer_CTRL2_IRQ_SEL_SHIFT 0x00u + #define Debug_Timer_CTRL2_IRQ_SEL ((uint8)((uint8)0x01u << Debug_Timer_CTRL2_IRQ_SEL_SHIFT)) + + #if (CY_PSOC5A) + /* Use CFG1 Mode bits to set run mode */ + /* As defined by Verilog Implementation */ + #define Debug_Timer_CTRL_MODE_SHIFT 0x01u + #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x07u << Debug_Timer_CTRL_MODE_SHIFT)) + #endif /* (CY_PSOC5A) */ + #if (CY_PSOC3 || CY_PSOC5LP) + /* Control3 Register Bit Locations */ + #define Debug_Timer_CTRL_RCOD_SHIFT 0x02u + #define Debug_Timer_CTRL_ENBL_SHIFT 0x00u + #define Debug_Timer_CTRL_MODE_SHIFT 0x00u + + /* Control3 Register Bit Masks */ + #define Debug_Timer_CTRL_RCOD_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) /* ROD and COD bit masks */ + #define Debug_Timer_CTRL_ENBL_MASK ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) /* HW_EN bit mask */ + #define Debug_Timer_CTRL_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_MODE_SHIFT)) /* Run mode bit mask */ + + #define Debug_Timer_CTRL_RCOD ((uint8)((uint8)0x03u << Debug_Timer_CTRL_RCOD_SHIFT)) + #define Debug_Timer_CTRL_ENBL ((uint8)((uint8)0x80u << Debug_Timer_CTRL_ENBL_SHIFT)) + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /*RT1 Synch Constants: Applicable for PSoC3 and PSoC5LP */ + #define Debug_Timer_RT1_SHIFT 0x04u + /* Sync TC and CMP bit masks */ + #define Debug_Timer_RT1_MASK ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT)) + #define Debug_Timer_SYNC ((uint8)((uint8)0x03u << Debug_Timer_RT1_SHIFT)) + #define Debug_Timer_SYNCDSI_SHIFT 0x00u + /* Sync all DSI inputs with Mask */ + #define Debug_Timer_SYNCDSI_MASK ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT)) + /* Sync all DSI inputs */ + #define Debug_Timer_SYNCDSI_EN ((uint8)((uint8)0x0Fu << Debug_Timer_SYNCDSI_SHIFT)) + + #define Debug_Timer_CTRL_MODE_PULSEWIDTH ((uint8)((uint8)0x01u << Debug_Timer_CTRL_MODE_SHIFT)) + #define Debug_Timer_CTRL_MODE_PERIOD ((uint8)((uint8)0x02u << Debug_Timer_CTRL_MODE_SHIFT)) + #define Debug_Timer_CTRL_MODE_CONTINUOUS ((uint8)((uint8)0x00u << Debug_Timer_CTRL_MODE_SHIFT)) + + /* Status Register Bit Locations */ + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Debug_Timer_STATUS_TC_SHIFT 0x07u + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Debug_Timer_STATUS_CAPTURE_SHIFT 0x06u + /* As defined in Register Map, part of TMRX_SR0 register */ + #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT (Debug_Timer_STATUS_TC_SHIFT - 0x04u) + /* As defined in Register Map, part of TMRX_SR0 register, Shared with Compare Status */ + #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT (Debug_Timer_STATUS_CAPTURE_SHIFT - 0x04u) + + /* Status Register Bit Masks */ + #define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT)) + #define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on TC */ + #define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_INT_MASK_SHIFT)) + /* Interrupt Enable Bit-Mask for interrupt on Capture */ + #define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT)) + +#else /* UDB Registers and Register Constants */ + + + /*************************************** + * UDB Registers + ***************************************/ + + #define Debug_Timer_STATUS (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_REG ) + #define Debug_Timer_STATUS_MASK (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__MASK_REG) + #define Debug_Timer_STATUS_AUX_CTRL (* (reg8 *) Debug_Timer_TimerUDB_rstSts_stsreg__STATUS_AUX_CTL_REG) + #define Debug_Timer_CONTROL (* (reg8 *) Debug_Timer_TimerUDB_sCTRLReg_SyncCtl_ctrlreg__CONTROL_REG ) + + #if(Debug_Timer_Resolution <= 8u) /* 8-bit Timer */ + #define Debug_Timer_CAPTURE_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #elif(Debug_Timer_Resolution <= 16u) /* 8-bit Timer */ + #if(CY_PSOC3) /* 8-bit addres space */ + #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 16-bit address space */ + #define Debug_Timer_CAPTURE_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg16 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__16BIT_A0_REG ) + #endif /* CY_PSOC3 */ + #elif(Debug_Timer_Resolution <= 24u)/* 24-bit Timer */ + #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit Timer */ + #if(CY_PSOC3 || CY_PSOC5) /* 8-bit address space */ + #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + #else /* 32-bit address space */ + #define Debug_Timer_CAPTURE_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Debug_Timer_CAPTURE_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_F0_REG ) + #define Debug_Timer_PERIOD_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Debug_Timer_PERIOD_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_D0_REG ) + #define Debug_Timer_COUNTER_LSB (* (reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #define Debug_Timer_COUNTER_LSB_PTR ((reg32 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__32BIT_A0_REG ) + #endif /* CY_PSOC3 || CY_PSOC5 */ + #endif + + #define Debug_Timer_COUNTER_LSB_PTR_8BIT ((reg8 *) Debug_Timer_TimerUDB_sT16_timerdp_u0__A0_REG ) + + #if (Debug_Timer_UsingHWCaptureCounter) + #define Debug_Timer_CAP_COUNT (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Debug_Timer_CAP_COUNT_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__PERIOD_REG ) + #define Debug_Timer_CAPTURE_COUNT_CTRL (*(reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #define Debug_Timer_CAPTURE_COUNT_CTRL_PTR ( (reg8 *) Debug_Timer_TimerUDB_sCapCount_counter__CONTROL_AUX_CTL_REG ) + #endif /* (Debug_Timer_UsingHWCaptureCounter) */ + + + /*************************************** + * Register Constants + ***************************************/ + + /* Control Register Bit Locations */ + #define Debug_Timer_CTRL_INTCNT_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Debug_Timer_CTRL_TRIG_MODE_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Debug_Timer_CTRL_TRIG_EN_SHIFT 0x04u /* As defined by Verilog Implementation */ + #define Debug_Timer_CTRL_CAP_MODE_SHIFT 0x05u /* As defined by Verilog Implementation */ + #define Debug_Timer_CTRL_ENABLE_SHIFT 0x07u /* As defined by Verilog Implementation */ + + /* Control Register Bit Masks */ + #define Debug_Timer_CTRL_INTCNT_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_INTCNT_SHIFT)) + #define Debug_Timer_CTRL_TRIG_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_TRIG_MODE_SHIFT)) + #define Debug_Timer_CTRL_TRIG_EN ((uint8)((uint8)0x01u << Debug_Timer_CTRL_TRIG_EN_SHIFT)) + #define Debug_Timer_CTRL_CAP_MODE_MASK ((uint8)((uint8)0x03u << Debug_Timer_CTRL_CAP_MODE_SHIFT)) + #define Debug_Timer_CTRL_ENABLE ((uint8)((uint8)0x01u << Debug_Timer_CTRL_ENABLE_SHIFT)) + + /* Bit Counter (7-bit) Control Register Bit Definitions */ + /* As defined by the Register map for the AUX Control Register */ + #define Debug_Timer_CNTR_ENABLE 0x20u + + /* Status Register Bit Locations */ + #define Debug_Timer_STATUS_TC_SHIFT 0x00u /* As defined by Verilog Implementation */ + #define Debug_Timer_STATUS_CAPTURE_SHIFT 0x01u /* As defined by Verilog Implementation */ + #define Debug_Timer_STATUS_TC_INT_MASK_SHIFT Debug_Timer_STATUS_TC_SHIFT + #define Debug_Timer_STATUS_CAPTURE_INT_MASK_SHIFT Debug_Timer_STATUS_CAPTURE_SHIFT + #define Debug_Timer_STATUS_FIFOFULL_SHIFT 0x02u /* As defined by Verilog Implementation */ + #define Debug_Timer_STATUS_FIFONEMP_SHIFT 0x03u /* As defined by Verilog Implementation */ + #define Debug_Timer_STATUS_FIFOFULL_INT_MASK_SHIFT Debug_Timer_STATUS_FIFOFULL_SHIFT + + /* Status Register Bit Masks */ + /* Sticky TC Event Bit-Mask */ + #define Debug_Timer_STATUS_TC ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT)) + /* Sticky Capture Event Bit-Mask */ + #define Debug_Timer_STATUS_CAPTURE ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Debug_Timer_STATUS_TC_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_TC_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Debug_Timer_STATUS_CAPTURE_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_CAPTURE_SHIFT)) + /* NOT-Sticky FIFO Full Bit-Mask */ + #define Debug_Timer_STATUS_FIFOFULL ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT)) + /* NOT-Sticky FIFO Not Empty Bit-Mask */ + #define Debug_Timer_STATUS_FIFONEMP ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFONEMP_SHIFT)) + /* Interrupt Enable Bit-Mask */ + #define Debug_Timer_STATUS_FIFOFULL_INT_MASK ((uint8)((uint8)0x01u << Debug_Timer_STATUS_FIFOFULL_SHIFT)) + + #define Debug_Timer_STATUS_ACTL_INT_EN 0x10u /* As defined for the ACTL Register */ + + /* Datapath Auxillary Control Register definitions */ + #define Debug_Timer_AUX_CTRL_FIFO0_CLR 0x01u /* As defined by Register map */ + #define Debug_Timer_AUX_CTRL_FIFO1_CLR 0x02u /* As defined by Register map */ + #define Debug_Timer_AUX_CTRL_FIFO0_LVL 0x04u /* As defined by Register map */ + #define Debug_Timer_AUX_CTRL_FIFO1_LVL 0x08u /* As defined by Register map */ + #define Debug_Timer_STATUS_ACTL_INT_EN_MASK 0x10u /* As defined for the ACTL Register */ + +#endif /* Implementation Specific Registers and Register Constants */ + +#endif /* CY_Timer_v2_30_Debug_Timer_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c new file mode 100644 index 0000000..8e9bbe0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: Debug_Timer_Interrupt.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(Debug_Timer_Interrupt__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START Debug_Timer_Interrupt_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_Start(void) +{ + /* For all we know the interrupt is active. */ + Debug_Timer_Interrupt_Disable(); + + /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */ + Debug_Timer_Interrupt_SetVector(&Debug_Timer_Interrupt_Interrupt); + + /* Set the priority. */ + Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER); + + /* Enable it. */ + Debug_Timer_Interrupt_Enable(); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + Debug_Timer_Interrupt_Disable(); + + /* Set the ISR to point to the Debug_Timer_Interrupt Interrupt. */ + Debug_Timer_Interrupt_SetVector(address); + + /* Set the priority. */ + Debug_Timer_Interrupt_SetPriority((uint8)Debug_Timer_Interrupt_INTC_PRIOR_NUMBER); + + /* Enable it. */ + Debug_Timer_Interrupt_Enable(); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_Stop(void) +{ + /* Disable this interrupt. */ + Debug_Timer_Interrupt_Disable(); + + /* Set the ISR to point to the passive one. */ + Debug_Timer_Interrupt_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for Debug_Timer_Interrupt. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(Debug_Timer_Interrupt_Interrupt) +{ + #ifdef Debug_Timer_Interrupt_INTERRUPT_INTERRUPT_CALLBACK + Debug_Timer_Interrupt_Interrupt_InterruptCallback(); + #endif /* Debug_Timer_Interrupt_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START Debug_Timer_Interrupt_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling Debug_Timer_Interrupt_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use Debug_Timer_Interrupt_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress Debug_Timer_Interrupt_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)Debug_Timer_Interrupt__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx will +* override any effect this API would have had. This API should only be called +* after Debug_Timer_Interrupt_Start or Debug_Timer_Interrupt_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_SetPriority(uint8 priority) +{ + *Debug_Timer_Interrupt_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 Debug_Timer_Interrupt_GetPriority(void) +{ + uint8 priority; + + + priority = *Debug_Timer_Interrupt_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_Enable(void) +{ + /* Enable the general interrupt. */ + *Debug_Timer_Interrupt_INTC_SET_EN = Debug_Timer_Interrupt__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 Debug_Timer_Interrupt_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*Debug_Timer_Interrupt_INTC_SET_EN & (uint32)Debug_Timer_Interrupt__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_Disable(void) +{ + /* Disable the general interrupt. */ + *Debug_Timer_Interrupt_INTC_CLR_EN = Debug_Timer_Interrupt__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void Debug_Timer_Interrupt_SetPending(void) +{ + *Debug_Timer_Interrupt_INTC_SET_PD = Debug_Timer_Interrupt__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Interrupt_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Debug_Timer_Interrupt_ClearPending(void) +{ + *Debug_Timer_Interrupt_INTC_CLR_PD = Debug_Timer_Interrupt__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h new file mode 100644 index 0000000..94ef1af --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_Interrupt.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: Debug_Timer_Interrupt.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_Debug_Timer_Interrupt_H) +#define CY_ISR_Debug_Timer_Interrupt_H + + +#include +#include + +/* Interrupt Controller API. */ +void Debug_Timer_Interrupt_Start(void); +void Debug_Timer_Interrupt_StartEx(cyisraddress address); +void Debug_Timer_Interrupt_Stop(void); + +CY_ISR_PROTO(Debug_Timer_Interrupt_Interrupt); + +void Debug_Timer_Interrupt_SetVector(cyisraddress address); +cyisraddress Debug_Timer_Interrupt_GetVector(void); + +void Debug_Timer_Interrupt_SetPriority(uint8 priority); +uint8 Debug_Timer_Interrupt_GetPriority(void); + +void Debug_Timer_Interrupt_Enable(void); +uint8 Debug_Timer_Interrupt_GetState(void); +void Debug_Timer_Interrupt_Disable(void); + +void Debug_Timer_Interrupt_SetPending(void); +void Debug_Timer_Interrupt_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the Debug_Timer_Interrupt ISR. */ +#define Debug_Timer_Interrupt_INTC_VECTOR ((reg32 *) Debug_Timer_Interrupt__INTC_VECT) + +/* Address of the Debug_Timer_Interrupt ISR priority. */ +#define Debug_Timer_Interrupt_INTC_PRIOR ((reg8 *) Debug_Timer_Interrupt__INTC_PRIOR_REG) + +/* Priority of the Debug_Timer_Interrupt interrupt. */ +#define Debug_Timer_Interrupt_INTC_PRIOR_NUMBER Debug_Timer_Interrupt__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable Debug_Timer_Interrupt interrupt. */ +#define Debug_Timer_Interrupt_INTC_SET_EN ((reg32 *) Debug_Timer_Interrupt__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the Debug_Timer_Interrupt interrupt. */ +#define Debug_Timer_Interrupt_INTC_CLR_EN ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the Debug_Timer_Interrupt interrupt state to pending. */ +#define Debug_Timer_Interrupt_INTC_SET_PD ((reg32 *) Debug_Timer_Interrupt__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the Debug_Timer_Interrupt interrupt. */ +#define Debug_Timer_Interrupt_INTC_CLR_PD ((reg32 *) Debug_Timer_Interrupt__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_Debug_Timer_Interrupt_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c new file mode 100644 index 0000000..c9c443b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/Debug_Timer_PM.c @@ -0,0 +1,162 @@ +/******************************************************************************* +* File Name: Debug_Timer_PM.c +* Version 2.70 +* +* Description: +* This file provides the power management source code to API for the +* Timer. +* +* Note: +* None +* +******************************************************************************* +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "Debug_Timer.h" + +static Debug_Timer_backupStruct Debug_Timer_backup; + + +/******************************************************************************* +* Function Name: Debug_Timer_SaveConfig +******************************************************************************** +* +* Summary: +* Save the current user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Debug_Timer_backup: Variables of this global structure are modified to +* store the values of non retention configuration registers when Sleep() API is +* called. +* +*******************************************************************************/ +void Debug_Timer_SaveConfig(void) +{ + #if (!Debug_Timer_UsingFixedFunction) + Debug_Timer_backup.TimerUdb = Debug_Timer_ReadCounter(); + Debug_Timer_backup.InterruptMaskValue = Debug_Timer_STATUS_MASK; + #if (Debug_Timer_UsingHWCaptureCounter) + Debug_Timer_backup.TimerCaptureCounter = Debug_Timer_ReadCaptureCount(); + #endif /* Back Up capture counter register */ + + #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED) + Debug_Timer_backup.TimerControlRegister = Debug_Timer_ReadControlRegister(); + #endif /* Backup the enable state of the Timer component */ + #endif /* Backup non retention registers in UDB implementation. All fixed function registers are retention */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Debug_Timer_backup: Variables of this global structure are used to +* restore the values of non retention registers on wakeup from sleep mode. +* +*******************************************************************************/ +void Debug_Timer_RestoreConfig(void) +{ + #if (!Debug_Timer_UsingFixedFunction) + + Debug_Timer_WriteCounter(Debug_Timer_backup.TimerUdb); + Debug_Timer_STATUS_MASK =Debug_Timer_backup.InterruptMaskValue; + #if (Debug_Timer_UsingHWCaptureCounter) + Debug_Timer_SetCaptureCount(Debug_Timer_backup.TimerCaptureCounter); + #endif /* Restore Capture counter register*/ + + #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED) + Debug_Timer_WriteControlRegister(Debug_Timer_backup.TimerControlRegister); + #endif /* Restore the enable state of the Timer component */ + #endif /* Restore non retention registers in the UDB implementation only */ +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Sleep +******************************************************************************** +* +* Summary: +* Stop and Save the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Debug_Timer_backup.TimerEnableState: Is modified depending on the +* enable state of the block before entering sleep mode. +* +*******************************************************************************/ +void Debug_Timer_Sleep(void) +{ + #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED) + /* Save Counter's enable state */ + if(Debug_Timer_CTRL_ENABLE == (Debug_Timer_CONTROL & Debug_Timer_CTRL_ENABLE)) + { + /* Timer is enabled */ + Debug_Timer_backup.TimerEnableState = 1u; + } + else + { + /* Timer is disabled */ + Debug_Timer_backup.TimerEnableState = 0u; + } + #endif /* Back up enable state from the Timer control register */ + Debug_Timer_Stop(); + Debug_Timer_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: Debug_Timer_Wakeup +******************************************************************************** +* +* Summary: +* Restores and enables the user configuration +* +* Parameters: +* void +* +* Return: +* void +* +* Global variables: +* Debug_Timer_backup.enableState: Is used to restore the enable state of +* block on wakeup from sleep mode. +* +*******************************************************************************/ +void Debug_Timer_Wakeup(void) +{ + Debug_Timer_RestoreConfig(); + #if(!Debug_Timer_UDB_CONTROL_REG_REMOVED) + if(Debug_Timer_backup.TimerEnableState == 1u) + { /* Enable Timer's operation */ + Debug_Timer_Enable(); + } /* Do nothing if Timer was disabled before */ + #endif /* Remove this code section if Control register is removed */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c new file mode 100644 index 0000000..2ea06ad --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: EXTLED.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "EXTLED.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: EXTLED_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet EXTLED_SUT.c usage_EXTLED_Write +*******************************************************************************/ +void EXTLED_Write(uint8 value) +{ + uint8 staticBits = (EXTLED_DR & (uint8)(~EXTLED_MASK)); + EXTLED_DR = staticBits | ((uint8)(value << EXTLED_SHIFT) & EXTLED_MASK); +} + + +/******************************************************************************* +* Function Name: EXTLED_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet EXTLED_SUT.c usage_EXTLED_SetDriveMode +*******************************************************************************/ +void EXTLED_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(EXTLED_0, mode); +} + + +/******************************************************************************* +* Function Name: EXTLED_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet EXTLED_SUT.c usage_EXTLED_Read +*******************************************************************************/ +uint8 EXTLED_Read(void) +{ + return (EXTLED_PS & EXTLED_MASK) >> EXTLED_SHIFT; +} + + +/******************************************************************************* +* Function Name: EXTLED_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred EXTLED_Read() API because the +* EXTLED_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet EXTLED_SUT.c usage_EXTLED_ReadDataReg +*******************************************************************************/ +uint8 EXTLED_ReadDataReg(void) +{ + return (EXTLED_DR & EXTLED_MASK) >> EXTLED_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(EXTLED_INTSTAT) + + /******************************************************************************* + * Function Name: EXTLED_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use EXTLED_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - EXTLED_0_INTR (First pin in the list) + * - EXTLED_1_INTR (Second pin in the list) + * - ... + * - EXTLED_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet EXTLED_SUT.c usage_EXTLED_SetInterruptMode + *******************************************************************************/ + void EXTLED_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & EXTLED_0_INTR) != 0u) + { + EXTLED_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: EXTLED_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet EXTLED_SUT.c usage_EXTLED_ClearInterrupt + *******************************************************************************/ + uint8 EXTLED_ClearInterrupt(void) + { + return (EXTLED_INTSTAT & EXTLED_MASK) >> EXTLED_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h new file mode 100644 index 0000000..b518b6a --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: EXTLED.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_EXTLED_H) /* Pins EXTLED_H */ +#define CY_PINS_EXTLED_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "EXTLED_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + EXTLED__PORT == 15 && ((EXTLED__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void EXTLED_Write(uint8 value); +void EXTLED_SetDriveMode(uint8 mode); +uint8 EXTLED_ReadDataReg(void); +uint8 EXTLED_Read(void); +void EXTLED_SetInterruptMode(uint16 position, uint16 mode); +uint8 EXTLED_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the EXTLED_SetDriveMode() function. + * @{ + */ + #define EXTLED_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define EXTLED_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define EXTLED_DM_RES_UP PIN_DM_RES_UP + #define EXTLED_DM_RES_DWN PIN_DM_RES_DWN + #define EXTLED_DM_OD_LO PIN_DM_OD_LO + #define EXTLED_DM_OD_HI PIN_DM_OD_HI + #define EXTLED_DM_STRONG PIN_DM_STRONG + #define EXTLED_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define EXTLED_MASK EXTLED__MASK +#define EXTLED_SHIFT EXTLED__SHIFT +#define EXTLED_WIDTH 1u + +/* Interrupt constants */ +#if defined(EXTLED__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in EXTLED_SetInterruptMode() function. + * @{ + */ + #define EXTLED_INTR_NONE (uint16)(0x0000u) + #define EXTLED_INTR_RISING (uint16)(0x0001u) + #define EXTLED_INTR_FALLING (uint16)(0x0002u) + #define EXTLED_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define EXTLED_INTR_MASK (0x01u) +#endif /* (EXTLED__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define EXTLED_PS (* (reg8 *) EXTLED__PS) +/* Data Register */ +#define EXTLED_DR (* (reg8 *) EXTLED__DR) +/* Port Number */ +#define EXTLED_PRT_NUM (* (reg8 *) EXTLED__PRT) +/* Connect to Analog Globals */ +#define EXTLED_AG (* (reg8 *) EXTLED__AG) +/* Analog MUX bux enable */ +#define EXTLED_AMUX (* (reg8 *) EXTLED__AMUX) +/* Bidirectional Enable */ +#define EXTLED_BIE (* (reg8 *) EXTLED__BIE) +/* Bit-mask for Aliased Register Access */ +#define EXTLED_BIT_MASK (* (reg8 *) EXTLED__BIT_MASK) +/* Bypass Enable */ +#define EXTLED_BYP (* (reg8 *) EXTLED__BYP) +/* Port wide control signals */ +#define EXTLED_CTL (* (reg8 *) EXTLED__CTL) +/* Drive Modes */ +#define EXTLED_DM0 (* (reg8 *) EXTLED__DM0) +#define EXTLED_DM1 (* (reg8 *) EXTLED__DM1) +#define EXTLED_DM2 (* (reg8 *) EXTLED__DM2) +/* Input Buffer Disable Override */ +#define EXTLED_INP_DIS (* (reg8 *) EXTLED__INP_DIS) +/* LCD Common or Segment Drive */ +#define EXTLED_LCD_COM_SEG (* (reg8 *) EXTLED__LCD_COM_SEG) +/* Enable Segment LCD */ +#define EXTLED_LCD_EN (* (reg8 *) EXTLED__LCD_EN) +/* Slew Rate Control */ +#define EXTLED_SLW (* (reg8 *) EXTLED__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define EXTLED_PRTDSI__CAPS_SEL (* (reg8 *) EXTLED__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define EXTLED_PRTDSI__DBL_SYNC_IN (* (reg8 *) EXTLED__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define EXTLED_PRTDSI__OE_SEL0 (* (reg8 *) EXTLED__PRTDSI__OE_SEL0) +#define EXTLED_PRTDSI__OE_SEL1 (* (reg8 *) EXTLED__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define EXTLED_PRTDSI__OUT_SEL0 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL0) +#define EXTLED_PRTDSI__OUT_SEL1 (* (reg8 *) EXTLED__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define EXTLED_PRTDSI__SYNC_OUT (* (reg8 *) EXTLED__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(EXTLED__SIO_CFG) + #define EXTLED_SIO_HYST_EN (* (reg8 *) EXTLED__SIO_HYST_EN) + #define EXTLED_SIO_REG_HIFREQ (* (reg8 *) EXTLED__SIO_REG_HIFREQ) + #define EXTLED_SIO_CFG (* (reg8 *) EXTLED__SIO_CFG) + #define EXTLED_SIO_DIFF (* (reg8 *) EXTLED__SIO_DIFF) +#endif /* (EXTLED__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(EXTLED__INTSTAT) + #define EXTLED_INTSTAT (* (reg8 *) EXTLED__INTSTAT) + #define EXTLED_SNAP (* (reg8 *) EXTLED__SNAP) + + #define EXTLED_0_INTTYPE_REG (* (reg8 *) EXTLED__0__INTTYPE) +#endif /* (EXTLED__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_EXTLED_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h new file mode 100644 index 0000000..b41f1e8 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/EXTLED_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: EXTLED.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_EXTLED_ALIASES_H) /* Pins EXTLED_ALIASES_H */ +#define CY_PINS_EXTLED_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define EXTLED_0 (EXTLED__0__PC) +#define EXTLED_0_INTR ((uint16)((uint16)0x0001u << EXTLED__0__SHIFT)) + +#define EXTLED_INTR_ALL ((uint16)(EXTLED_0_INTR)) + +#endif /* End Pins EXTLED_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c new file mode 100644 index 0000000..9127d57 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.c @@ -0,0 +1,231 @@ +/******************************************************************************* +* File Name: LED1.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED1_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_Write +*******************************************************************************/ +void LED1_Write(uint8 value) +{ + uint8 staticBits = (LED1_DR & (uint8)(~LED1_MASK)); + LED1_DR = staticBits | ((uint8)(value << LED1_SHIFT) & LED1_MASK); +} + + +/******************************************************************************* +* Function Name: LED1_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_SetDriveMode +*******************************************************************************/ +void LED1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED1_0, mode); + CyPins_SetPinDriveMode(LED1_1, mode); +} + + +/******************************************************************************* +* Function Name: LED1_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_Read +*******************************************************************************/ +uint8 LED1_Read(void) +{ + return (LED1_PS & LED1_MASK) >> LED1_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED1_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred LED1_Read() API because the +* LED1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet LED1_SUT.c usage_LED1_ReadDataReg +*******************************************************************************/ +uint8 LED1_ReadDataReg(void) +{ + return (LED1_DR & LED1_MASK) >> LED1_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(LED1_INTSTAT) + + /******************************************************************************* + * Function Name: LED1_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use LED1_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - LED1_0_INTR (First pin in the list) + * - LED1_1_INTR (Second pin in the list) + * - ... + * - LED1_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet LED1_SUT.c usage_LED1_SetInterruptMode + *******************************************************************************/ + void LED1_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & LED1_0_INTR) != 0u) + { + LED1_0_INTTYPE_REG = (uint8)mode; + } + if((position & LED1_1_INTR) != 0u) + { + LED1_1_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: LED1_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet LED1_SUT.c usage_LED1_ClearInterrupt + *******************************************************************************/ + uint8 LED1_ClearInterrupt(void) + { + return (LED1_INTSTAT & LED1_MASK) >> LED1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h new file mode 100644 index 0000000..b43ada7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1.h @@ -0,0 +1,166 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_H) /* Pins LED1_H */ +#define CY_PINS_LED1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED1_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED1__PORT == 15 && ((LED1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void LED1_Write(uint8 value); +void LED1_SetDriveMode(uint8 mode); +uint8 LED1_ReadDataReg(void); +uint8 LED1_Read(void); +void LED1_SetInterruptMode(uint16 position, uint16 mode); +uint8 LED1_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the LED1_SetDriveMode() function. + * @{ + */ + #define LED1_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define LED1_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define LED1_DM_RES_UP PIN_DM_RES_UP + #define LED1_DM_RES_DWN PIN_DM_RES_DWN + #define LED1_DM_OD_LO PIN_DM_OD_LO + #define LED1_DM_OD_HI PIN_DM_OD_HI + #define LED1_DM_STRONG PIN_DM_STRONG + #define LED1_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define LED1_MASK LED1__MASK +#define LED1_SHIFT LED1__SHIFT +#define LED1_WIDTH 2u + +/* Interrupt constants */ +#if defined(LED1__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in LED1_SetInterruptMode() function. + * @{ + */ + #define LED1_INTR_NONE (uint16)(0x0000u) + #define LED1_INTR_RISING (uint16)(0x0001u) + #define LED1_INTR_FALLING (uint16)(0x0002u) + #define LED1_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define LED1_INTR_MASK (0x01u) +#endif /* (LED1__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED1_PS (* (reg8 *) LED1__PS) +/* Data Register */ +#define LED1_DR (* (reg8 *) LED1__DR) +/* Port Number */ +#define LED1_PRT_NUM (* (reg8 *) LED1__PRT) +/* Connect to Analog Globals */ +#define LED1_AG (* (reg8 *) LED1__AG) +/* Analog MUX bux enable */ +#define LED1_AMUX (* (reg8 *) LED1__AMUX) +/* Bidirectional Enable */ +#define LED1_BIE (* (reg8 *) LED1__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED1_BIT_MASK (* (reg8 *) LED1__BIT_MASK) +/* Bypass Enable */ +#define LED1_BYP (* (reg8 *) LED1__BYP) +/* Port wide control signals */ +#define LED1_CTL (* (reg8 *) LED1__CTL) +/* Drive Modes */ +#define LED1_DM0 (* (reg8 *) LED1__DM0) +#define LED1_DM1 (* (reg8 *) LED1__DM1) +#define LED1_DM2 (* (reg8 *) LED1__DM2) +/* Input Buffer Disable Override */ +#define LED1_INP_DIS (* (reg8 *) LED1__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED1_LCD_COM_SEG (* (reg8 *) LED1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED1_LCD_EN (* (reg8 *) LED1__LCD_EN) +/* Slew Rate Control */ +#define LED1_SLW (* (reg8 *) LED1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED1_PRTDSI__CAPS_SEL (* (reg8 *) LED1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED1_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED1_PRTDSI__OE_SEL0 (* (reg8 *) LED1__PRTDSI__OE_SEL0) +#define LED1_PRTDSI__OE_SEL1 (* (reg8 *) LED1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED1_PRTDSI__OUT_SEL0 (* (reg8 *) LED1__PRTDSI__OUT_SEL0) +#define LED1_PRTDSI__OUT_SEL1 (* (reg8 *) LED1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED1_PRTDSI__SYNC_OUT (* (reg8 *) LED1__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(LED1__SIO_CFG) + #define LED1_SIO_HYST_EN (* (reg8 *) LED1__SIO_HYST_EN) + #define LED1_SIO_REG_HIFREQ (* (reg8 *) LED1__SIO_REG_HIFREQ) + #define LED1_SIO_CFG (* (reg8 *) LED1__SIO_CFG) + #define LED1_SIO_DIFF (* (reg8 *) LED1__SIO_DIFF) +#endif /* (LED1__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(LED1__INTSTAT) + #define LED1_INTSTAT (* (reg8 *) LED1__INTSTAT) + #define LED1_SNAP (* (reg8 *) LED1__SNAP) + + #define LED1_0_INTTYPE_REG (* (reg8 *) LED1__0__INTTYPE) + #define LED1_1_INTTYPE_REG (* (reg8 *) LED1__1__INTTYPE) +#endif /* (LED1__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h new file mode 100644 index 0000000..51b89fb --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/LED1_aliases.h @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: LED1.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED1_ALIASES_H) /* Pins LED1_ALIASES_H */ +#define CY_PINS_LED1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define LED1_0 (LED1__0__PC) +#define LED1_0_INTR ((uint16)((uint16)0x0001u << LED1__0__SHIFT)) + +#define LED1_1 (LED1__1__PC) +#define LED1_1_INTR ((uint16)((uint16)0x0001u << LED1__1__SHIFT)) + +#define LED1_INTR_ALL ((uint16)(LED1_0_INTR| LED1_1_INTR)) + +#endif /* End Pins LED1_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c new file mode 100644 index 0000000..327ddb7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SCSI_ATN.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_ATN.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_ATN_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_ATN_Write(uint8 value) +{ + uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK)); + SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_ATN_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_ATN_0, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_ATN_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_ATN_Read(void) +{ + return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_ATN_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_ATN_ReadDataReg(void) +{ + return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_ATN_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_ATN_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_ATN_ClearInterrupt(void) + { + return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h new file mode 100644 index 0000000..2c89fad --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_ATN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */ +#define CY_PINS_SCSI_ATN_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_ATN_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_ATN_Write(uint8 value) ; +void SCSI_ATN_SetDriveMode(uint8 mode) ; +uint8 SCSI_ATN_ReadDataReg(void) ; +uint8 SCSI_ATN_Read(void) ; +uint8 SCSI_ATN_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_ATN_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_ATN_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_ATN_DM_RES_UP PIN_DM_RES_UP +#define SCSI_ATN_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_ATN_DM_OD_LO PIN_DM_OD_LO +#define SCSI_ATN_DM_OD_HI PIN_DM_OD_HI +#define SCSI_ATN_DM_STRONG PIN_DM_STRONG +#define SCSI_ATN_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_ATN_MASK SCSI_ATN__MASK +#define SCSI_ATN_SHIFT SCSI_ATN__SHIFT +#define SCSI_ATN_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_ATN_PS (* (reg8 *) SCSI_ATN__PS) +/* Data Register */ +#define SCSI_ATN_DR (* (reg8 *) SCSI_ATN__DR) +/* Port Number */ +#define SCSI_ATN_PRT_NUM (* (reg8 *) SCSI_ATN__PRT) +/* Connect to Analog Globals */ +#define SCSI_ATN_AG (* (reg8 *) SCSI_ATN__AG) +/* Analog MUX bux enable */ +#define SCSI_ATN_AMUX (* (reg8 *) SCSI_ATN__AMUX) +/* Bidirectional Enable */ +#define SCSI_ATN_BIE (* (reg8 *) SCSI_ATN__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_ATN_BIT_MASK (* (reg8 *) SCSI_ATN__BIT_MASK) +/* Bypass Enable */ +#define SCSI_ATN_BYP (* (reg8 *) SCSI_ATN__BYP) +/* Port wide control signals */ +#define SCSI_ATN_CTL (* (reg8 *) SCSI_ATN__CTL) +/* Drive Modes */ +#define SCSI_ATN_DM0 (* (reg8 *) SCSI_ATN__DM0) +#define SCSI_ATN_DM1 (* (reg8 *) SCSI_ATN__DM1) +#define SCSI_ATN_DM2 (* (reg8 *) SCSI_ATN__DM2) +/* Input Buffer Disable Override */ +#define SCSI_ATN_INP_DIS (* (reg8 *) SCSI_ATN__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_ATN_LCD_COM_SEG (* (reg8 *) SCSI_ATN__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_ATN_LCD_EN (* (reg8 *) SCSI_ATN__LCD_EN) +/* Slew Rate Control */ +#define SCSI_ATN_SLW (* (reg8 *) SCSI_ATN__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_ATN_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_ATN_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_ATN_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0) +#define SCSI_ATN_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_ATN_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0) +#define SCSI_ATN_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_ATN_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_ATN__INTSTAT) /* Interrupt Registers */ + + #define SCSI_ATN_INTSTAT (* (reg8 *) SCSI_ATN__INTSTAT) + #define SCSI_ATN_SNAP (* (reg8 *) SCSI_ATN__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_ATN_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h new file mode 100644 index 0000000..46aff1f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: SCSI_ATN.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */ +#define CY_PINS_SCSI_ATN_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_ATN_0 SCSI_ATN__0__PC + +#define SCSI_ATN_INT SCSI_ATN__INT__PC + +#endif /* End Pins SCSI_ATN_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c new file mode 100644 index 0000000..6e8f808 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SCSI_CLK.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SCSI_CLK.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SCSI_CLK_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_Start(void) +{ + /* Set the bit to enable the clock. */ + SCSI_CLK_CLKEN |= SCSI_CLK_CLKEN_MASK; + SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SCSI_CLK_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_StopBlock(void) +{ + if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SCSI_CLK__CFG3) + CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SCSI_CLK__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SCSI_CLK_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SCSI_CLK_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SCSI_CLK_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SCSI_CLK_CLKSTBY &= (uint8)(~SCSI_CLK_CLKSTBY_MASK); + } + else + { + SCSI_CLK_CLKSTBY |= SCSI_CLK_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SCSI_CLK_GetSourceRegister(); + uint16 oldDivider = SCSI_CLK_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SCSI_CLK_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SCSI_CLK__CFG3) + CLK_DIST_AMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SCSI_CLK_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SCSI_CLK__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SCSI_CLK_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SCSI_CLK_CLKEN &= (uint8)(~SCSI_CLK_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SCSI_CLK_CLKEN & SCSI_CLK_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SCSI_CLK_DIV_PTR, clkDivider); + SCSI_CLK_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SCSI_CLK_GetDividerRegister(void) +{ + return CY_GET_REG16(SCSI_CLK_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetModeRegister(uint8 modeBitMask) +{ + SCSI_CLK_MOD_SRC |= modeBitMask & (uint8)SCSI_CLK_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) +{ + SCSI_CLK_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SCSI_CLK_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetModeRegister(void) +{ + return SCSI_CLK_MOD_SRC & (uint8)(SCSI_CLK_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SCSI_CLK_GetDividerRegister(); + uint8 oldSrc = SCSI_CLK_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SCSI_CLK_MOD_SRC |= CYCLK_SSS; + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + SCSI_CLK_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SCSI_CLK_MOD_SRC = + (SCSI_CLK_MOD_SRC & (uint8)(~SCSI_CLK_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetSourceRegister(void) +{ + return SCSI_CLK_MOD_SRC & SCSI_CLK_SRC_SEL_MSK; +} + + +#if defined(SCSI_CLK__CFG3) + + +/******************************************************************************* +* Function Name: SCSI_CLK_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) +{ + SCSI_CLK_PHASE = clkPhase & SCSI_CLK_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_CLK_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SCSI_CLK_GetPhaseRegister(void) +{ + return SCSI_CLK_PHASE & SCSI_CLK_PHASE_MASK; +} + +#endif /* SCSI_CLK__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h new file mode 100644 index 0000000..e4c3e10 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CLK.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SCSI_CLK.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SCSI_CLK_H) +#define CY_CLOCK_SCSI_CLK_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CLK_Start(void) ; +void SCSI_CLK_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SCSI_CLK_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SCSI_CLK_StandbyPower(uint8 state) ; +void SCSI_CLK_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SCSI_CLK_GetDividerRegister(void) ; +void SCSI_CLK_SetModeRegister(uint8 modeBitMask) ; +void SCSI_CLK_ClearModeRegister(uint8 modeBitMask) ; +uint8 SCSI_CLK_GetModeRegister(void) ; +void SCSI_CLK_SetSourceRegister(uint8 clkSource) ; +uint8 SCSI_CLK_GetSourceRegister(void) ; +#if defined(SCSI_CLK__CFG3) +void SCSI_CLK_SetPhaseRegister(uint8 clkPhase) ; +uint8 SCSI_CLK_GetPhaseRegister(void) ; +#endif /* defined(SCSI_CLK__CFG3) */ + +#define SCSI_CLK_Enable() SCSI_CLK_Start() +#define SCSI_CLK_Disable() SCSI_CLK_Stop() +#define SCSI_CLK_SetDivider(clkDivider) SCSI_CLK_SetDividerRegister(clkDivider, 1u) +#define SCSI_CLK_SetDividerValue(clkDivider) SCSI_CLK_SetDividerRegister((clkDivider) - 1u, 1u) +#define SCSI_CLK_SetMode(clkMode) SCSI_CLK_SetModeRegister(clkMode) +#define SCSI_CLK_SetSource(clkSource) SCSI_CLK_SetSourceRegister(clkSource) +#if defined(SCSI_CLK__CFG3) +#define SCSI_CLK_SetPhase(clkPhase) SCSI_CLK_SetPhaseRegister(clkPhase) +#define SCSI_CLK_SetPhaseValue(clkPhase) SCSI_CLK_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SCSI_CLK__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SCSI_CLK_CLKEN (* (reg8 *) SCSI_CLK__PM_ACT_CFG) +#define SCSI_CLK_CLKEN_PTR ((reg8 *) SCSI_CLK__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SCSI_CLK_CLKSTBY (* (reg8 *) SCSI_CLK__PM_STBY_CFG) +#define SCSI_CLK_CLKSTBY_PTR ((reg8 *) SCSI_CLK__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SCSI_CLK_DIV_LSB (* (reg8 *) SCSI_CLK__CFG0) +#define SCSI_CLK_DIV_LSB_PTR ((reg8 *) SCSI_CLK__CFG0) +#define SCSI_CLK_DIV_PTR ((reg16 *) SCSI_CLK__CFG0) + +/* Clock MSB divider configuration register. */ +#define SCSI_CLK_DIV_MSB (* (reg8 *) SCSI_CLK__CFG1) +#define SCSI_CLK_DIV_MSB_PTR ((reg8 *) SCSI_CLK__CFG1) + +/* Mode and source configuration register */ +#define SCSI_CLK_MOD_SRC (* (reg8 *) SCSI_CLK__CFG2) +#define SCSI_CLK_MOD_SRC_PTR ((reg8 *) SCSI_CLK__CFG2) + +#if defined(SCSI_CLK__CFG3) +/* Analog clock phase configuration register */ +#define SCSI_CLK_PHASE (* (reg8 *) SCSI_CLK__CFG3) +#define SCSI_CLK_PHASE_PTR ((reg8 *) SCSI_CLK__CFG3) +#endif /* defined(SCSI_CLK__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SCSI_CLK_CLKEN_MASK SCSI_CLK__PM_ACT_MSK +#define SCSI_CLK_CLKSTBY_MASK SCSI_CLK__PM_STBY_MSK + +/* CFG2 field masks */ +#define SCSI_CLK_SRC_SEL_MSK SCSI_CLK__CFG2_SRC_SEL_MASK +#define SCSI_CLK_MODE_MASK (~(SCSI_CLK_SRC_SEL_MSK)) + +#if defined(SCSI_CLK__CFG3) +/* CFG3 phase mask */ +#define SCSI_CLK_PHASE_MASK SCSI_CLK__CFG3_PHASE_DLY_MASK +#endif /* defined(SCSI_CLK__CFG3) */ + +#endif /* CY_CLOCK_SCSI_CLK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c new file mode 100644 index 0000000..87f8273 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SCSI_CTL_IO.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_CTL_IO.h" + +#if !defined(SCSI_CTL_IO_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SCSI_CTL_IO_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_CTL_IO_Write(uint8 control) +{ + SCSI_CTL_IO_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_IO_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_CTL_IO_Read(void) +{ + return SCSI_CTL_IO_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h new file mode 100644 index 0000000..d140e57 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_IO.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SCSI_CTL_IO.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_CTL_IO_H) /* CY_CONTROL_REG_SCSI_CTL_IO_H */ +#define CY_CONTROL_REG_SCSI_CTL_IO_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CTL_IO_Write(uint8 control) ; +uint8 SCSI_CTL_IO_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_CTL_IO_Control (* (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_CTL_IO_Control_PTR ( (reg8 *) SCSI_CTL_IO_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_CTL_IO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c new file mode 100644 index 0000000..c9d441e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: SCSI_CTL_PHASE.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_CTL_PHASE.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_CTL_PHASE_Write(uint8 control) +{ + SCSI_CTL_PHASE_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_CTL_PHASE_Read(void) +{ + return SCSI_CTL_PHASE_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h new file mode 100644 index 0000000..4db2bae --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: SCSI_CTL_PHASE.h +* Version 1.80 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_CTL_PHASE_H) /* CY_CONTROL_REG_SCSI_CTL_PHASE_H */ +#define CY_CONTROL_REG_SCSI_CTL_PHASE_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_CTL_PHASE_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_CTL_PHASE_Write(uint8 control) ; +uint8 SCSI_CTL_PHASE_Read(void) ; + +void SCSI_CTL_PHASE_SaveConfig(void) ; +void SCSI_CTL_PHASE_RestoreConfig(void) ; +void SCSI_CTL_PHASE_Sleep(void) ; +void SCSI_CTL_PHASE_Wakeup(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_CTL_PHASE_Control (* (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_CTL_PHASE_Control_PTR ( (reg8 *) SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_CTL_PHASE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c new file mode 100644 index 0000000..f20c66d --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_CTL_PHASE_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_CTL_PHASE_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_CTL_PHASE.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_CTL_PHASE_Sync_ctrl_reg__REMOVED) + +static SCSI_CTL_PHASE_BACKUP_STRUCT SCSI_CTL_PHASE_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_SaveConfig(void) +{ + SCSI_CTL_PHASE_backup.controlState = SCSI_CTL_PHASE_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_CTL_PHASE_RestoreConfig(void) +{ + SCSI_CTL_PHASE_Control = SCSI_CTL_PHASE_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_Sleep(void) +{ + SCSI_CTL_PHASE_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_CTL_PHASE_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_CTL_PHASE_Wakeup(void) +{ + SCSI_CTL_PHASE_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c new file mode 100644 index 0000000..593f8c3 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Filtered.h" + +#if !defined(SCSI_Filtered_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Filtered_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_Read(void) +{ + return SCSI_Filtered_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl |= SCSI_Filtered_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Filtered_Status_Aux_Ctrl &= (uint8)(~SCSI_Filtered_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Filtered_WriteMask(uint8 mask) +{ + #if(SCSI_Filtered_INPUTS < 8u) + mask &= ((uint8)(1u << SCSI_Filtered_INPUTS) - 1u); + #endif /* End SCSI_Filtered_INPUTS < 8u */ + SCSI_Filtered_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Filtered_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Filtered_ReadMask(void) +{ + return SCSI_Filtered_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h new file mode 100644 index 0000000..c64ec62 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Filtered.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* File Name: SCSI_Filtered.h +* Version 1.90 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Filtered_H) /* CY_STATUS_REG_SCSI_Filtered_H */ +#define CY_STATUS_REG_SCSI_Filtered_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 statusState; + +} SCSI_Filtered_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Filtered_Read(void) ; +void SCSI_Filtered_InterruptEnable(void) ; +void SCSI_Filtered_InterruptDisable(void) ; +void SCSI_Filtered_WriteMask(uint8 mask) ; +uint8 SCSI_Filtered_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Filtered_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Filtered_INPUTS 5 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Filtered_Status (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_PTR ( (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_REG ) +#define SCSI_Filtered_Status_Mask (* (reg8 *) SCSI_Filtered_sts_sts_reg__MASK_REG ) +#define SCSI_Filtered_Status_Aux_Ctrl (* (reg8 *) SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Filtered_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c new file mode 100644 index 0000000..b447184 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Glitch_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Write(uint8 control) +{ + SCSI_Glitch_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_Glitch_Ctl_Read(void) +{ + return SCSI_Glitch_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h new file mode 100644 index 0000000..88e1557 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl.h +* Version 1.80 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_Glitch_Ctl_H) /* CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ +#define CY_CONTROL_REG_SCSI_Glitch_Ctl_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Glitch_Ctl_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Glitch_Ctl_Write(uint8 control) ; +uint8 SCSI_Glitch_Ctl_Read(void) ; + +void SCSI_Glitch_Ctl_SaveConfig(void) ; +void SCSI_Glitch_Ctl_RestoreConfig(void) ; +void SCSI_Glitch_Ctl_Sleep(void) ; +void SCSI_Glitch_Ctl_Wakeup(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_Glitch_Ctl_Control (* (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_Glitch_Ctl_Control_PTR ( (reg8 *) SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_Glitch_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c new file mode 100644 index 0000000..47fc7c0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Glitch_Ctl_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Glitch_Ctl_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Glitch_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Glitch_Ctl_Sync_ctrl_reg__REMOVED) + +static SCSI_Glitch_Ctl_BACKUP_STRUCT SCSI_Glitch_Ctl_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_SaveConfig(void) +{ + SCSI_Glitch_Ctl_backup.controlState = SCSI_Glitch_Ctl_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_RestoreConfig(void) +{ + SCSI_Glitch_Ctl_Control = SCSI_Glitch_Ctl_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Sleep(void) +{ + SCSI_Glitch_Ctl_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Glitch_Ctl_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Glitch_Ctl_Wakeup(void) +{ + SCSI_Glitch_Ctl_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c new file mode 100644 index 0000000..b3a407b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SCSI_In.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_In.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_In__PORT == 15 && ((SCSI_In__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_In_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SCSI_In_SUT.c usage_SCSI_In_Write +*******************************************************************************/ +void SCSI_In_Write(uint8 value) +{ + uint8 staticBits = (SCSI_In_DR & (uint8)(~SCSI_In_MASK)); + SCSI_In_DR = staticBits | ((uint8)(value << SCSI_In_SHIFT) & SCSI_In_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_In_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SCSI_In_SUT.c usage_SCSI_In_SetDriveMode +*******************************************************************************/ +void SCSI_In_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_In_0, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_In_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SCSI_In_SUT.c usage_SCSI_In_Read +*******************************************************************************/ +uint8 SCSI_In_Read(void) +{ + return (SCSI_In_PS & SCSI_In_MASK) >> SCSI_In_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_In_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SCSI_In_Read() API because the +* SCSI_In_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SCSI_In_SUT.c usage_SCSI_In_ReadDataReg +*******************************************************************************/ +uint8 SCSI_In_ReadDataReg(void) +{ + return (SCSI_In_DR & SCSI_In_MASK) >> SCSI_In_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SCSI_In_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_In_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SCSI_In_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SCSI_In_0_INTR (First pin in the list) + * - SCSI_In_1_INTR (Second pin in the list) + * - ... + * - SCSI_In_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SCSI_In_SUT.c usage_SCSI_In_SetInterruptMode + *******************************************************************************/ + void SCSI_In_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SCSI_In_0_INTR) != 0u) + { + SCSI_In_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SCSI_In_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SCSI_In_SUT.c usage_SCSI_In_ClearInterrupt + *******************************************************************************/ + uint8 SCSI_In_ClearInterrupt(void) + { + return (SCSI_In_INTSTAT & SCSI_In_MASK) >> SCSI_In_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h new file mode 100644 index 0000000..bc739cb --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SCSI_In.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_H) /* Pins SCSI_In_H */ +#define CY_PINS_SCSI_In_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_In_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_In__PORT == 15 && ((SCSI_In__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SCSI_In_Write(uint8 value); +void SCSI_In_SetDriveMode(uint8 mode); +uint8 SCSI_In_ReadDataReg(void); +uint8 SCSI_In_Read(void); +void SCSI_In_SetInterruptMode(uint16 position, uint16 mode); +uint8 SCSI_In_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SCSI_In_SetDriveMode() function. + * @{ + */ + #define SCSI_In_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SCSI_In_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SCSI_In_DM_RES_UP PIN_DM_RES_UP + #define SCSI_In_DM_RES_DWN PIN_DM_RES_DWN + #define SCSI_In_DM_OD_LO PIN_DM_OD_LO + #define SCSI_In_DM_OD_HI PIN_DM_OD_HI + #define SCSI_In_DM_STRONG PIN_DM_STRONG + #define SCSI_In_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SCSI_In_MASK SCSI_In__MASK +#define SCSI_In_SHIFT SCSI_In__SHIFT +#define SCSI_In_WIDTH 1u + +/* Interrupt constants */ +#if defined(SCSI_In__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SCSI_In_SetInterruptMode() function. + * @{ + */ + #define SCSI_In_INTR_NONE (uint16)(0x0000u) + #define SCSI_In_INTR_RISING (uint16)(0x0001u) + #define SCSI_In_INTR_FALLING (uint16)(0x0002u) + #define SCSI_In_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SCSI_In_INTR_MASK (0x01u) +#endif /* (SCSI_In__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_In_PS (* (reg8 *) SCSI_In__PS) +/* Data Register */ +#define SCSI_In_DR (* (reg8 *) SCSI_In__DR) +/* Port Number */ +#define SCSI_In_PRT_NUM (* (reg8 *) SCSI_In__PRT) +/* Connect to Analog Globals */ +#define SCSI_In_AG (* (reg8 *) SCSI_In__AG) +/* Analog MUX bux enable */ +#define SCSI_In_AMUX (* (reg8 *) SCSI_In__AMUX) +/* Bidirectional Enable */ +#define SCSI_In_BIE (* (reg8 *) SCSI_In__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_In_BIT_MASK (* (reg8 *) SCSI_In__BIT_MASK) +/* Bypass Enable */ +#define SCSI_In_BYP (* (reg8 *) SCSI_In__BYP) +/* Port wide control signals */ +#define SCSI_In_CTL (* (reg8 *) SCSI_In__CTL) +/* Drive Modes */ +#define SCSI_In_DM0 (* (reg8 *) SCSI_In__DM0) +#define SCSI_In_DM1 (* (reg8 *) SCSI_In__DM1) +#define SCSI_In_DM2 (* (reg8 *) SCSI_In__DM2) +/* Input Buffer Disable Override */ +#define SCSI_In_INP_DIS (* (reg8 *) SCSI_In__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_In_LCD_COM_SEG (* (reg8 *) SCSI_In__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_In_LCD_EN (* (reg8 *) SCSI_In__LCD_EN) +/* Slew Rate Control */ +#define SCSI_In_SLW (* (reg8 *) SCSI_In__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_In_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_In__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_In_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_In__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_In_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_In__PRTDSI__OE_SEL0) +#define SCSI_In_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_In__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_In_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_In__PRTDSI__OUT_SEL0) +#define SCSI_In_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_In__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_In_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_In__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SCSI_In__SIO_CFG) + #define SCSI_In_SIO_HYST_EN (* (reg8 *) SCSI_In__SIO_HYST_EN) + #define SCSI_In_SIO_REG_HIFREQ (* (reg8 *) SCSI_In__SIO_REG_HIFREQ) + #define SCSI_In_SIO_CFG (* (reg8 *) SCSI_In__SIO_CFG) + #define SCSI_In_SIO_DIFF (* (reg8 *) SCSI_In__SIO_DIFF) +#endif /* (SCSI_In__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SCSI_In__INTSTAT) + #define SCSI_In_INTSTAT (* (reg8 *) SCSI_In__INTSTAT) + #define SCSI_In_SNAP (* (reg8 *) SCSI_In__SNAP) + + #define SCSI_In_0_INTTYPE_REG (* (reg8 *) SCSI_In__0__INTTYPE) +#endif /* (SCSI_In__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_In_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h new file mode 100644 index 0000000..447155b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* File Name: SCSI_In_DBx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_DBx_ALIASES_H) /* Pins SCSI_In_DBx_ALIASES_H */ +#define CY_PINS_SCSI_In_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_DBx_0 (SCSI_In_DBx__0__PC) +#define SCSI_In_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT)) + +#define SCSI_In_DBx_1 (SCSI_In_DBx__1__PC) +#define SCSI_In_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT)) + +#define SCSI_In_DBx_2 (SCSI_In_DBx__2__PC) +#define SCSI_In_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT)) + +#define SCSI_In_DBx_3 (SCSI_In_DBx__3__PC) +#define SCSI_In_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT)) + +#define SCSI_In_DBx_4 (SCSI_In_DBx__4__PC) +#define SCSI_In_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT)) + +#define SCSI_In_DBx_5 (SCSI_In_DBx__5__PC) +#define SCSI_In_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT)) + +#define SCSI_In_DBx_6 (SCSI_In_DBx__6__PC) +#define SCSI_In_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT)) + +#define SCSI_In_DBx_7 (SCSI_In_DBx__7__PC) +#define SCSI_In_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT)) + +#define SCSI_In_DBx_INTR_ALL ((uint16)(SCSI_In_DBx_0_INTR| SCSI_In_DBx_1_INTR| SCSI_In_DBx_2_INTR| SCSI_In_DBx_3_INTR| SCSI_In_DBx_4_INTR| SCSI_In_DBx_5_INTR| SCSI_In_DBx_6_INTR| SCSI_In_DBx_7_INTR)) +#define SCSI_In_DBx_DB0 (SCSI_In_DBx__DB0__PC) +#define SCSI_In_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__0__SHIFT)) + +#define SCSI_In_DBx_DB1 (SCSI_In_DBx__DB1__PC) +#define SCSI_In_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__1__SHIFT)) + +#define SCSI_In_DBx_DB2 (SCSI_In_DBx__DB2__PC) +#define SCSI_In_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__2__SHIFT)) + +#define SCSI_In_DBx_DB3 (SCSI_In_DBx__DB3__PC) +#define SCSI_In_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__3__SHIFT)) + +#define SCSI_In_DBx_DB4 (SCSI_In_DBx__DB4__PC) +#define SCSI_In_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__4__SHIFT)) + +#define SCSI_In_DBx_DB5 (SCSI_In_DBx__DB5__PC) +#define SCSI_In_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__5__SHIFT)) + +#define SCSI_In_DBx_DB6 (SCSI_In_DBx__DB6__PC) +#define SCSI_In_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__6__SHIFT)) + +#define SCSI_In_DBx_DB7 (SCSI_In_DBx__DB7__PC) +#define SCSI_In_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_In_DBx__7__SHIFT)) + +#endif /* End Pins SCSI_In_DBx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h new file mode 100644 index 0000000..81056ee --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h @@ -0,0 +1,38 @@ +/******************************************************************************* +* File Name: SCSI_In.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_In_ALIASES_H) /* Pins SCSI_In_ALIASES_H */ +#define CY_PINS_SCSI_In_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SCSI_In_0 (SCSI_In__0__PC) +#define SCSI_In_0_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT)) + +#define SCSI_In_INTR_ALL ((uint16)(SCSI_In_0_INTR)) +#define SCSI_In_DBP (SCSI_In__DBP__PC) +#define SCSI_In_DBP_INTR ((uint16)((uint16)0x0001u << SCSI_In__0__SHIFT)) + +#endif /* End Pins SCSI_In_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h new file mode 100644 index 0000000..a6c3ff1 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Noise_aliases.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* File Name: SCSI_Noise.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Noise_ALIASES_H) /* Pins SCSI_Noise_ALIASES_H */ +#define CY_PINS_SCSI_Noise_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Noise_0 (SCSI_Noise__0__PC) +#define SCSI_Noise_0_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT)) + +#define SCSI_Noise_1 (SCSI_Noise__1__PC) +#define SCSI_Noise_1_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT)) + +#define SCSI_Noise_2 (SCSI_Noise__2__PC) +#define SCSI_Noise_2_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT)) + +#define SCSI_Noise_3 (SCSI_Noise__3__PC) +#define SCSI_Noise_3_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT)) + +#define SCSI_Noise_4 (SCSI_Noise__4__PC) +#define SCSI_Noise_4_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT)) + +#define SCSI_Noise_INTR_ALL ((uint16)(SCSI_Noise_0_INTR| SCSI_Noise_1_INTR| SCSI_Noise_2_INTR| SCSI_Noise_3_INTR| SCSI_Noise_4_INTR)) +#define SCSI_Noise_ATN (SCSI_Noise__ATN__PC) +#define SCSI_Noise_ATN_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__0__SHIFT)) + +#define SCSI_Noise_BSY (SCSI_Noise__BSY__PC) +#define SCSI_Noise_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__1__SHIFT)) + +#define SCSI_Noise_SEL (SCSI_Noise__SEL__PC) +#define SCSI_Noise_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__2__SHIFT)) + +#define SCSI_Noise_RST (SCSI_Noise__RST__PC) +#define SCSI_Noise_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__3__SHIFT)) + +#define SCSI_Noise_ACK (SCSI_Noise__ACK__PC) +#define SCSI_Noise_ACK_INTR ((uint16)((uint16)0x0001u << SCSI_Noise__4__SHIFT)) + +#endif /* End Pins SCSI_Noise_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c new file mode 100644 index 0000000..85a089e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: SCSI_Out_Bits.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Bits.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Out_Bits_Write(uint8 control) +{ + SCSI_Out_Bits_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_Out_Bits_Read(void) +{ + return SCSI_Out_Bits_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h new file mode 100644 index 0000000..1ada4ee --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: SCSI_Out_Bits.h +* Version 1.80 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_Out_Bits_H) /* CY_CONTROL_REG_SCSI_Out_Bits_H */ +#define CY_CONTROL_REG_SCSI_Out_Bits_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Out_Bits_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Out_Bits_Write(uint8 control) ; +uint8 SCSI_Out_Bits_Read(void) ; + +void SCSI_Out_Bits_SaveConfig(void) ; +void SCSI_Out_Bits_RestoreConfig(void) ; +void SCSI_Out_Bits_Sleep(void) ; +void SCSI_Out_Bits_Wakeup(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_Out_Bits_Control (* (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_Out_Bits_Control_PTR ( (reg8 *) SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_Out_Bits_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c new file mode 100644 index 0000000..04f06a0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Bits_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Out_Bits_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Bits.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Bits_Sync_ctrl_reg__REMOVED) + +static SCSI_Out_Bits_BACKUP_STRUCT SCSI_Out_Bits_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_SaveConfig(void) +{ + SCSI_Out_Bits_backup.controlState = SCSI_Out_Bits_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Out_Bits_RestoreConfig(void) +{ + SCSI_Out_Bits_Control = SCSI_Out_Bits_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_Sleep(void) +{ + SCSI_Out_Bits_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Bits_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Bits_Wakeup(void) +{ + SCSI_Out_Bits_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c new file mode 100644 index 0000000..ecba124 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: SCSI_Out_Ctl.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Out_Ctl_Write(uint8 control) +{ + SCSI_Out_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SCSI_Out_Ctl_Read(void) +{ + return SCSI_Out_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h new file mode 100644 index 0000000..725873f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: SCSI_Out_Ctl.h +* Version 1.80 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SCSI_Out_Ctl_H) /* CY_CONTROL_REG_SCSI_Out_Ctl_H */ +#define CY_CONTROL_REG_SCSI_Out_Ctl_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} SCSI_Out_Ctl_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_Out_Ctl_Write(uint8 control) ; +uint8 SCSI_Out_Ctl_Read(void) ; + +void SCSI_Out_Ctl_SaveConfig(void) ; +void SCSI_Out_Ctl_RestoreConfig(void) ; +void SCSI_Out_Ctl_Sleep(void) ; +void SCSI_Out_Ctl_Wakeup(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SCSI_Out_Ctl_Control (* (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SCSI_Out_Ctl_Control_PTR ( (reg8 *) SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SCSI_Out_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c new file mode 100644 index 0000000..abc42cf --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_Ctl_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: SCSI_Out_Ctl_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Out_Ctl.h" + +/* Check for removal by optimization */ +#if !defined(SCSI_Out_Ctl_Sync_ctrl_reg__REMOVED) + +static SCSI_Out_Ctl_BACKUP_STRUCT SCSI_Out_Ctl_backup = {0u}; + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_SaveConfig(void) +{ + SCSI_Out_Ctl_backup.controlState = SCSI_Out_Ctl_Control; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void SCSI_Out_Ctl_RestoreConfig(void) +{ + SCSI_Out_Ctl_Control = SCSI_Out_Ctl_backup.controlState; +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_Sleep(void) +{ + SCSI_Out_Ctl_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: SCSI_Out_Ctl_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_Out_Ctl_Wakeup(void) +{ + SCSI_Out_Ctl_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h new file mode 100644 index 0000000..6006db5 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ +#define CY_PINS_SCSI_Out_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) +#define SCSI_Out_DBx_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) + +#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) +#define SCSI_Out_DBx_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) +#define SCSI_Out_DBx_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) +#define SCSI_Out_DBx_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) +#define SCSI_Out_DBx_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) +#define SCSI_Out_DBx_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) +#define SCSI_Out_DBx_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) +#define SCSI_Out_DBx_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) + +#define SCSI_Out_DBx_INTR_ALL ((uint16)(SCSI_Out_DBx_0_INTR| SCSI_Out_DBx_1_INTR| SCSI_Out_DBx_2_INTR| SCSI_Out_DBx_3_INTR| SCSI_Out_DBx_4_INTR| SCSI_Out_DBx_5_INTR| SCSI_Out_DBx_6_INTR| SCSI_Out_DBx_7_INTR)) +#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) +#define SCSI_Out_DBx_DB0_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__0__SHIFT)) + +#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) +#define SCSI_Out_DBx_DB1_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__1__SHIFT)) + +#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) +#define SCSI_Out_DBx_DB2_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__2__SHIFT)) + +#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) +#define SCSI_Out_DBx_DB3_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__3__SHIFT)) + +#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) +#define SCSI_Out_DBx_DB4_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__4__SHIFT)) + +#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) +#define SCSI_Out_DBx_DB5_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__5__SHIFT)) + +#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) +#define SCSI_Out_DBx_DB6_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__6__SHIFT)) + +#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) +#define SCSI_Out_DBx_DB7_INTR ((uint16)((uint16)0x0001u << SCSI_Out_DBx__7__SHIFT)) + +#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h new file mode 100644 index 0000000..4f3c79d --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -0,0 +1,80 @@ +/******************************************************************************* +* File Name: SCSI_Out.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ +#define CY_PINS_SCSI_Out_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_0 (SCSI_Out__0__PC) +#define SCSI_Out_0_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) + +#define SCSI_Out_1 (SCSI_Out__1__PC) +#define SCSI_Out_1_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_2 (SCSI_Out__2__PC) +#define SCSI_Out_2_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_3 (SCSI_Out__3__PC) +#define SCSI_Out_3_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_4 (SCSI_Out__4__PC) +#define SCSI_Out_4_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_5 (SCSI_Out__5__PC) +#define SCSI_Out_5_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_6 (SCSI_Out__6__PC) +#define SCSI_Out_6_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_7 (SCSI_Out__7__PC) +#define SCSI_Out_7_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) + +#define SCSI_Out_INTR_ALL ((uint16)(SCSI_Out_0_INTR| SCSI_Out_1_INTR| SCSI_Out_2_INTR| SCSI_Out_3_INTR| SCSI_Out_4_INTR| SCSI_Out_5_INTR| SCSI_Out_6_INTR| SCSI_Out_7_INTR)) +#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) +#define SCSI_Out_DBP_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__0__SHIFT)) + +#define SCSI_Out_BSY (SCSI_Out__BSY__PC) +#define SCSI_Out_BSY_INTR ((uint16)((uint16)0x0001u << SCSI_Out__1__SHIFT)) + +#define SCSI_Out_RST (SCSI_Out__RST__PC) +#define SCSI_Out_RST_INTR ((uint16)((uint16)0x0001u << SCSI_Out__2__SHIFT)) + +#define SCSI_Out_MSG_raw (SCSI_Out__MSG_raw__PC) +#define SCSI_Out_MSG_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__3__SHIFT)) + +#define SCSI_Out_SEL (SCSI_Out__SEL__PC) +#define SCSI_Out_SEL_INTR ((uint16)((uint16)0x0001u << SCSI_Out__4__SHIFT)) + +#define SCSI_Out_CD_raw (SCSI_Out__CD_raw__PC) +#define SCSI_Out_CD_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__5__SHIFT)) + +#define SCSI_Out_REQ (SCSI_Out__REQ__PC) +#define SCSI_Out_REQ_INTR ((uint16)((uint16)0x0001u << SCSI_Out__6__SHIFT)) + +#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) +#define SCSI_Out_IO_raw_INTR ((uint16)((uint16)0x0001u << SCSI_Out__7__SHIFT)) + +#endif /* End Pins SCSI_Out_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c new file mode 100644 index 0000000..de05e37 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.c @@ -0,0 +1,134 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware to read the value of a Status +* Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SCSI_Parity_Error.h" + +#if !defined(SCSI_Parity_Error_sts_sts_reg__REMOVED) /* Check for removal by optimization */ + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The current value in the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_Read(void) +{ + return SCSI_Parity_Error_Status; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptEnable +******************************************************************************** +* +* Summary: +* Enables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptEnable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl |= SCSI_Parity_Error_STATUS_INTR_ENBL; + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_InterruptDisable +******************************************************************************** +* +* Summary: +* Disables the Status Register interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_InterruptDisable(void) +{ + uint8 interruptState; + interruptState = CyEnterCriticalSection(); + SCSI_Parity_Error_Status_Aux_Ctrl &= (uint8)(~SCSI_Parity_Error_STATUS_INTR_ENBL); + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_WriteMask +******************************************************************************** +* +* Summary: +* Writes the current mask value assigned to the Status Register. +* +* Parameters: +* mask: Value to write into the mask register. +* +* Return: +* None. +* +*******************************************************************************/ +void SCSI_Parity_Error_WriteMask(uint8 mask) +{ + #if(SCSI_Parity_Error_INPUTS < 8u) + mask &= ((uint8)(1u << SCSI_Parity_Error_INPUTS) - 1u); + #endif /* End SCSI_Parity_Error_INPUTS < 8u */ + SCSI_Parity_Error_Status_Mask = mask; +} + + +/******************************************************************************* +* Function Name: SCSI_Parity_Error_ReadMask +******************************************************************************** +* +* Summary: +* Reads the current interrupt mask assigned to the Status Register. +* +* Parameters: +* None. +* +* Return: +* The value of the interrupt mask of the Status Register. +* +*******************************************************************************/ +uint8 SCSI_Parity_Error_ReadMask(void) +{ + return SCSI_Parity_Error_Status_Mask; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h new file mode 100644 index 0000000..de1ddc8 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Parity_Error.h @@ -0,0 +1,83 @@ +/******************************************************************************* +* File Name: SCSI_Parity_Error.h +* Version 1.90 +* +* Description: +* This file containts Status Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_STATUS_REG_SCSI_Parity_Error_H) /* CY_STATUS_REG_SCSI_Parity_Error_H */ +#define CY_STATUS_REG_SCSI_Parity_Error_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" + #include "CyLib.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 statusState; + +} SCSI_Parity_Error_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +uint8 SCSI_Parity_Error_Read(void) ; +void SCSI_Parity_Error_InterruptEnable(void) ; +void SCSI_Parity_Error_InterruptDisable(void) ; +void SCSI_Parity_Error_WriteMask(uint8 mask) ; +uint8 SCSI_Parity_Error_ReadMask(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define SCSI_Parity_Error_STATUS_INTR_ENBL 0x10u + + +/*************************************** +* Parameter Constants +***************************************/ + +/* Status Register Inputs */ +#define SCSI_Parity_Error_INPUTS 1 + + +/*************************************** +* Registers +***************************************/ + +/* Status Register */ +#define SCSI_Parity_Error_Status (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_PTR ( (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_REG ) +#define SCSI_Parity_Error_Status_Mask (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__MASK_REG ) +#define SCSI_Parity_Error_Status_Aux_Ctrl (* (reg8 *) SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG ) + +#endif /* End CY_STATUS_REG_SCSI_Parity_Error_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c new file mode 100644 index 0000000..0044ffd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.c @@ -0,0 +1,137 @@ +/******************************************************************************* +* File Name: SCSI_RST.c +* Version 1.90 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SCSI_RST.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SCSI_RST_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_Write(uint8 value) +{ + uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK)); + SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to this drive mode. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SCSI_RST_0, mode); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SCSI_RST_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SCSI_RST_Read(void) +{ + return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SCSI_RST_ReadDataReg(void) +{ + return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SCSI_RST_INTSTAT) + + /******************************************************************************* + * Function Name: SCSI_RST_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SCSI_RST_ClearInterrupt(void) + { + return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h new file mode 100644 index 0000000..c0f868a --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SCSI_RST.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */ +#define CY_PINS_SCSI_RST_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SCSI_RST_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v1_90 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SCSI_RST_Write(uint8 value) ; +void SCSI_RST_SetDriveMode(uint8 mode) ; +uint8 SCSI_RST_ReadDataReg(void) ; +uint8 SCSI_RST_Read(void) ; +uint8 SCSI_RST_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SCSI_RST_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SCSI_RST_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SCSI_RST_DM_RES_UP PIN_DM_RES_UP +#define SCSI_RST_DM_RES_DWN PIN_DM_RES_DWN +#define SCSI_RST_DM_OD_LO PIN_DM_OD_LO +#define SCSI_RST_DM_OD_HI PIN_DM_OD_HI +#define SCSI_RST_DM_STRONG PIN_DM_STRONG +#define SCSI_RST_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SCSI_RST_MASK SCSI_RST__MASK +#define SCSI_RST_SHIFT SCSI_RST__SHIFT +#define SCSI_RST_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SCSI_RST_PS (* (reg8 *) SCSI_RST__PS) +/* Data Register */ +#define SCSI_RST_DR (* (reg8 *) SCSI_RST__DR) +/* Port Number */ +#define SCSI_RST_PRT_NUM (* (reg8 *) SCSI_RST__PRT) +/* Connect to Analog Globals */ +#define SCSI_RST_AG (* (reg8 *) SCSI_RST__AG) +/* Analog MUX bux enable */ +#define SCSI_RST_AMUX (* (reg8 *) SCSI_RST__AMUX) +/* Bidirectional Enable */ +#define SCSI_RST_BIE (* (reg8 *) SCSI_RST__BIE) +/* Bit-mask for Aliased Register Access */ +#define SCSI_RST_BIT_MASK (* (reg8 *) SCSI_RST__BIT_MASK) +/* Bypass Enable */ +#define SCSI_RST_BYP (* (reg8 *) SCSI_RST__BYP) +/* Port wide control signals */ +#define SCSI_RST_CTL (* (reg8 *) SCSI_RST__CTL) +/* Drive Modes */ +#define SCSI_RST_DM0 (* (reg8 *) SCSI_RST__DM0) +#define SCSI_RST_DM1 (* (reg8 *) SCSI_RST__DM1) +#define SCSI_RST_DM2 (* (reg8 *) SCSI_RST__DM2) +/* Input Buffer Disable Override */ +#define SCSI_RST_INP_DIS (* (reg8 *) SCSI_RST__INP_DIS) +/* LCD Common or Segment Drive */ +#define SCSI_RST_LCD_COM_SEG (* (reg8 *) SCSI_RST__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SCSI_RST_LCD_EN (* (reg8 *) SCSI_RST__LCD_EN) +/* Slew Rate Control */ +#define SCSI_RST_SLW (* (reg8 *) SCSI_RST__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SCSI_RST_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SCSI_RST_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SCSI_RST_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0) +#define SCSI_RST_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SCSI_RST_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0) +#define SCSI_RST_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SCSI_RST_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT) + + +#if defined(SCSI_RST__INTSTAT) /* Interrupt Registers */ + + #define SCSI_RST_INTSTAT (* (reg8 *) SCSI_RST__INTSTAT) + #define SCSI_RST_SNAP (* (reg8 *) SCSI_RST__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SCSI_RST_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c new file mode 100644 index 0000000..924ed9f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SCSI_RST_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_RST_ISR_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */ + SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt); + + /* Set the priority. */ + SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RST_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the SCSI_RST_ISR Interrupt. */ + SCSI_RST_ISR_SetVector(address); + + /* Set the priority. */ + SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RST_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_RST_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_RST_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_RST_ISR. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_RST_ISR_Interrupt) +{ + #ifdef SCSI_RST_ISR_INTERRUPT_INTERRUPT_CALLBACK + SCSI_RST_ISR_Interrupt_InterruptCallback(); + #endif /* SCSI_RST_ISR_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SCSI_RST_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_RST_ISR_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_RST_ISR_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx will +* override any effect this API would have had. This API should only be called +* after SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_SetPriority(uint8 priority) +{ + *SCSI_RST_ISR_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SCSI_RST_ISR_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_RST_ISR_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_RST_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SCSI_RST_ISR_SetPending(void) +{ + *SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RST_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RST_ISR_ClearPending(void) +{ + *SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h new file mode 100644 index 0000000..ddefebc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_RST_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_RST_ISR_H) +#define CY_ISR_SCSI_RST_ISR_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_RST_ISR_Start(void); +void SCSI_RST_ISR_StartEx(cyisraddress address); +void SCSI_RST_ISR_Stop(void); + +CY_ISR_PROTO(SCSI_RST_ISR_Interrupt); + +void SCSI_RST_ISR_SetVector(cyisraddress address); +cyisraddress SCSI_RST_ISR_GetVector(void); + +void SCSI_RST_ISR_SetPriority(uint8 priority); +uint8 SCSI_RST_ISR_GetPriority(void); + +void SCSI_RST_ISR_Enable(void); +uint8 SCSI_RST_ISR_GetState(void); +void SCSI_RST_ISR_Disable(void); + +void SCSI_RST_ISR_SetPending(void); +void SCSI_RST_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */ +#define SCSI_RST_ISR_INTC_VECTOR ((reg32 *) SCSI_RST_ISR__INTC_VECT) + +/* Address of the SCSI_RST_ISR ISR priority. */ +#define SCSI_RST_ISR_INTC_PRIOR ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG) + +/* Priority of the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_PRIOR_NUMBER SCSI_RST_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_SET_EN ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_CLR_EN ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */ +#define SCSI_RST_ISR_INTC_SET_PD ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */ +#define SCSI_RST_ISR_INTC_CLR_PD ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_RST_ISR_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h new file mode 100644 index 0000000..d1a2496 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h @@ -0,0 +1,34 @@ +/******************************************************************************* +* File Name: SCSI_RST.h +* Version 1.90 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_RST_ALIASES_H) /* Pins SCSI_RST_ALIASES_H */ +#define CY_PINS_SCSI_RST_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_RST_0 SCSI_RST__0__PC + +#define SCSI_RST_INT SCSI_RST__INT__PC + +#endif /* End Pins SCSI_RST_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c new file mode 100644 index 0000000..b2633aa --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SCSI_RX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SCSI_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_RX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */ + SCSI_RX_DMA_COMPLETE_SetVector(&SCSI_RX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_RX_DMA_COMPLETE Interrupt. */ + SCSI_RX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SCSI_RX_DMA_COMPLETE_SetPriority((uint8)SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_RX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_RX_DMA_COMPLETE_Interrupt) +{ + #ifdef SCSI_RX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK + SCSI_RX_DMA_COMPLETE_Interrupt_InterruptCallback(); + #endif /* SCSI_RX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SCSI_RX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_RX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_RX_DMA_COMPLETE_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx will +* override any effect this API would have had. This API should only be called +* after SCSI_RX_DMA_COMPLETE_Start or SCSI_RX_DMA_COMPLETE_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SCSI_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_RX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_RX_DMA_COMPLETE_INTC_SET_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_RX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_RX_DMA_COMPLETE_INTC_CLR_EN = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_SetPending(void) +{ + *SCSI_RX_DMA_COMPLETE_INTC_SET_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_RX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_RX_DMA_COMPLETE_ClearPending(void) +{ + *SCSI_RX_DMA_COMPLETE_INTC_CLR_PD = SCSI_RX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h new file mode 100644 index 0000000..cdb95bd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_RX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_RX_DMA_COMPLETE_H) +#define CY_ISR_SCSI_RX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_RX_DMA_COMPLETE_Start(void); +void SCSI_RX_DMA_COMPLETE_StartEx(cyisraddress address); +void SCSI_RX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SCSI_RX_DMA_COMPLETE_Interrupt); + +void SCSI_RX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SCSI_RX_DMA_COMPLETE_GetVector(void); + +void SCSI_RX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SCSI_RX_DMA_COMPLETE_GetPriority(void); + +void SCSI_RX_DMA_COMPLETE_Enable(void); +uint8 SCSI_RX_DMA_COMPLETE_GetState(void); +void SCSI_RX_DMA_COMPLETE_Disable(void); + +void SCSI_RX_DMA_COMPLETE_SetPending(void); +void SCSI_RX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RX_DMA_COMPLETE ISR. */ +#define SCSI_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SCSI_RX_DMA_COMPLETE ISR priority. */ +#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_RX_DMA_COMPLETE interrupt state to pending. */ +#define SCSI_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RX_DMA_COMPLETE interrupt. */ +#define SCSI_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_RX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c new file mode 100644 index 0000000..6bdb2ea --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SCSI_RX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SCSI_RX_DMA__DRQ_CTL_REG +* +* +* SCSI_RX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SCSI_RX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SCSI_RX_DMA__PRIORITY +* +* True if SCSI_RX_DMA_TERMIN_SEL is used. +* SCSI_RX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SCSI_RX_DMA__TERMIN_SEL +* +* +* True if SCSI_RX_DMA_TERMOUT0_SEL is used. +* SCSI_RX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SCSI_RX_DMA__TERMOUT0_SEL +* +* +* True if SCSI_RX_DMA_TERMOUT1_SEL is used. +* SCSI_RX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SCSI_RX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SCSI_RX_DMA dma channel */ +uint8 SCSI_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SCSI_RX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SCSI_RX_DMA_DmaHandle = (uint8)SCSI_RX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SCSI_RX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SCSI_RX_DMA__TERMOUT0_SEL, + (uint8)SCSI_RX_DMA__TERMOUT1_SEL, + (uint8)SCSI_RX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SCSI_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SCSI_RX_DMA_DmaHandle, (uint8)SCSI_RX_DMA__PRIORITY); + + return SCSI_RX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SCSI_RX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SCSI_RX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SCSI_RX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SCSI_RX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h new file mode 100644 index 0000000..4030614 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SCSI_RX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SCSI_RX_DMA_DMA_H__) +#define CY_DMA_SCSI_RX_DMA_DMA_H__ + + + +#include +#include + +#define SCSI_RX_DMA__TD_TERMOUT_EN (((0 != SCSI_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SCSI_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SCSI_RX_DMA dma channel */ +extern uint8 SCSI_RX_DMA_DmaHandle; + + +uint8 SCSI_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SCSI_RX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SCSI_RX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c new file mode 100644 index 0000000..e274d74 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SCSI_SEL_ISR.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SCSI_SEL_ISR__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_SEL_ISR_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_SEL_ISR_Disable(); + + /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */ + SCSI_SEL_ISR_SetVector(&SCSI_SEL_ISR_Interrupt); + + /* Set the priority. */ + SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_SEL_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_SEL_ISR_Disable(); + + /* Set the ISR to point to the SCSI_SEL_ISR Interrupt. */ + SCSI_SEL_ISR_SetVector(address); + + /* Set the priority. */ + SCSI_SEL_ISR_SetPriority((uint8)SCSI_SEL_ISR_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_SEL_ISR_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_SEL_ISR_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_SEL_ISR_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_SEL_ISR. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_SEL_ISR_Interrupt) +{ + #ifdef SCSI_SEL_ISR_INTERRUPT_INTERRUPT_CALLBACK + SCSI_SEL_ISR_Interrupt_InterruptCallback(); + #endif /* SCSI_SEL_ISR_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SCSI_SEL_ISR_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_SEL_ISR_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_SEL_ISR_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_SEL_ISR_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_SEL_ISR__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx will +* override any effect this API would have had. This API should only be called +* after SCSI_SEL_ISR_Start or SCSI_SEL_ISR_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_SetPriority(uint8 priority) +{ + *SCSI_SEL_ISR_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SCSI_SEL_ISR_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_SEL_ISR_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_SEL_ISR_INTC_SET_EN = SCSI_SEL_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_SEL_ISR_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_SEL_ISR_INTC_SET_EN & (uint32)SCSI_SEL_ISR__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_SEL_ISR_INTC_CLR_EN = SCSI_SEL_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SCSI_SEL_ISR_SetPending(void) +{ + *SCSI_SEL_ISR_INTC_SET_PD = SCSI_SEL_ISR__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_SEL_ISR_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_SEL_ISR_ClearPending(void) +{ + *SCSI_SEL_ISR_INTC_CLR_PD = SCSI_SEL_ISR__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h new file mode 100644 index 0000000..0bc65ef --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_SEL_ISR.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_SEL_ISR.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_SEL_ISR_H) +#define CY_ISR_SCSI_SEL_ISR_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_SEL_ISR_Start(void); +void SCSI_SEL_ISR_StartEx(cyisraddress address); +void SCSI_SEL_ISR_Stop(void); + +CY_ISR_PROTO(SCSI_SEL_ISR_Interrupt); + +void SCSI_SEL_ISR_SetVector(cyisraddress address); +cyisraddress SCSI_SEL_ISR_GetVector(void); + +void SCSI_SEL_ISR_SetPriority(uint8 priority); +uint8 SCSI_SEL_ISR_GetPriority(void); + +void SCSI_SEL_ISR_Enable(void); +uint8 SCSI_SEL_ISR_GetState(void); +void SCSI_SEL_ISR_Disable(void); + +void SCSI_SEL_ISR_SetPending(void); +void SCSI_SEL_ISR_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_SEL_ISR ISR. */ +#define SCSI_SEL_ISR_INTC_VECTOR ((reg32 *) SCSI_SEL_ISR__INTC_VECT) + +/* Address of the SCSI_SEL_ISR ISR priority. */ +#define SCSI_SEL_ISR_INTC_PRIOR ((reg8 *) SCSI_SEL_ISR__INTC_PRIOR_REG) + +/* Priority of the SCSI_SEL_ISR interrupt. */ +#define SCSI_SEL_ISR_INTC_PRIOR_NUMBER SCSI_SEL_ISR__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_SEL_ISR interrupt. */ +#define SCSI_SEL_ISR_INTC_SET_EN ((reg32 *) SCSI_SEL_ISR__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_SEL_ISR interrupt. */ +#define SCSI_SEL_ISR_INTC_CLR_EN ((reg32 *) SCSI_SEL_ISR__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_SEL_ISR interrupt state to pending. */ +#define SCSI_SEL_ISR_INTC_SET_PD ((reg32 *) SCSI_SEL_ISR__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_SEL_ISR interrupt. */ +#define SCSI_SEL_ISR_INTC_CLR_PD ((reg32 *) SCSI_SEL_ISR__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_SEL_ISR_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c new file mode 100644 index 0000000..20517cc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SCSI_TX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SCSI_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SCSI_TX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */ + SCSI_TX_DMA_COMPLETE_SetVector(&SCSI_TX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SCSI_TX_DMA_COMPLETE Interrupt. */ + SCSI_TX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SCSI_TX_DMA_COMPLETE_SetPriority((uint8)SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SCSI_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SCSI_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SCSI_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SCSI_TX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SCSI_TX_DMA_COMPLETE_Interrupt) +{ + #ifdef SCSI_TX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK + SCSI_TX_DMA_COMPLETE_Interrupt_InterruptCallback(); + #endif /* SCSI_TX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SCSI_TX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SCSI_TX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SCSI_TX_DMA_COMPLETE_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_TX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx will +* override any effect this API would have had. This API should only be called +* after SCSI_TX_DMA_COMPLETE_Start or SCSI_TX_DMA_COMPLETE_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SCSI_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SCSI_TX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SCSI_TX_DMA_COMPLETE_INTC_SET_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SCSI_TX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SCSI_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SCSI_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SCSI_TX_DMA_COMPLETE_INTC_CLR_EN = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_SetPending(void) +{ + *SCSI_TX_DMA_COMPLETE_INTC_SET_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SCSI_TX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SCSI_TX_DMA_COMPLETE_ClearPending(void) +{ + *SCSI_TX_DMA_COMPLETE_INTC_CLR_PD = SCSI_TX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h new file mode 100644 index 0000000..e84f6ac --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SCSI_TX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SCSI_TX_DMA_COMPLETE_H) +#define CY_ISR_SCSI_TX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SCSI_TX_DMA_COMPLETE_Start(void); +void SCSI_TX_DMA_COMPLETE_StartEx(cyisraddress address); +void SCSI_TX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SCSI_TX_DMA_COMPLETE_Interrupt); + +void SCSI_TX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SCSI_TX_DMA_COMPLETE_GetVector(void); + +void SCSI_TX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SCSI_TX_DMA_COMPLETE_GetPriority(void); + +void SCSI_TX_DMA_COMPLETE_Enable(void); +uint8 SCSI_TX_DMA_COMPLETE_GetState(void); +void SCSI_TX_DMA_COMPLETE_Disable(void); + +void SCSI_TX_DMA_COMPLETE_SetPending(void); +void SCSI_TX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_TX_DMA_COMPLETE ISR. */ +#define SCSI_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SCSI_TX_DMA_COMPLETE ISR priority. */ +#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SCSI_TX_DMA_COMPLETE interrupt state to pending. */ +#define SCSI_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SCSI_TX_DMA_COMPLETE interrupt. */ +#define SCSI_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SCSI_TX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c new file mode 100644 index 0000000..83419f7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SCSI_TX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SCSI_TX_DMA__DRQ_CTL_REG +* +* +* SCSI_TX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SCSI_TX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SCSI_TX_DMA__PRIORITY +* +* True if SCSI_TX_DMA_TERMIN_SEL is used. +* SCSI_TX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SCSI_TX_DMA__TERMIN_SEL +* +* +* True if SCSI_TX_DMA_TERMOUT0_SEL is used. +* SCSI_TX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SCSI_TX_DMA__TERMOUT0_SEL +* +* +* True if SCSI_TX_DMA_TERMOUT1_SEL is used. +* SCSI_TX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SCSI_TX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SCSI_TX_DMA dma channel */ +uint8 SCSI_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SCSI_TX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SCSI_TX_DMA_DmaHandle = (uint8)SCSI_TX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SCSI_TX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SCSI_TX_DMA__TERMOUT0_SEL, + (uint8)SCSI_TX_DMA__TERMOUT1_SEL, + (uint8)SCSI_TX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SCSI_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SCSI_TX_DMA_DmaHandle, (uint8)SCSI_TX_DMA__PRIORITY); + + return SCSI_TX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SCSI_TX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SCSI_TX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SCSI_TX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SCSI_TX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h new file mode 100644 index 0000000..c0a1b00 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_TX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SCSI_TX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SCSI_TX_DMA_DMA_H__) +#define CY_DMA_SCSI_TX_DMA_DMA_H__ + + + +#include +#include + +#define SCSI_TX_DMA__TD_TERMOUT_EN (((0 != SCSI_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SCSI_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SCSI_TX_DMA dma channel */ +extern uint8 SCSI_TX_DMA_DmaHandle; + + +uint8 SCSI_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SCSI_TX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SCSI_TX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c new file mode 100644 index 0000000..446c6fe --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.c @@ -0,0 +1,1154 @@ +/******************************************************************************* +* File Name: SDCard.c +* Version 2.50 +* +* Description: +* This file provides all API functionality of the SPI Master component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE]; + volatile uint8 SDCard_txBufferFull; + volatile uint8 SDCard_txBufferRead; + volatile uint8 SDCard_txBufferWrite; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE]; + volatile uint8 SDCard_rxBufferFull; + volatile uint8 SDCard_rxBufferRead; + volatile uint8 SDCard_rxBufferWrite; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +uint8 SDCard_initVar = 0u; + +volatile uint8 SDCard_swStatusTx; +volatile uint8 SDCard_swStatusRx; + + +/******************************************************************************* +* Function Name: SDCard_Init +******************************************************************************** +* +* Summary: +* Inits/Restores default SPIM configuration provided with customizer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* When this function is called it initializes all of the necessary parameters +* for execution. i.e. setting the initial interrupt mask, configuring the +* interrupt service routine, configuring the bit-counter parameters and +* clearing the FIFO and Status Register. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Init(void) +{ + /* Initialize the Bit counter */ + SDCard_COUNTER_PERIOD_REG = SDCard_BITCTR_INIT; + + /* Init TX ISR */ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable (SDCard_TX_ISR_NUMBER); + CyIntSetPriority (SDCard_TX_ISR_NUMBER, SDCard_TX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_TX_ISR_NUMBER, &SDCard_TX_ISR); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ + + /* Init RX ISR */ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable (SDCard_RX_ISR_NUMBER); + CyIntSetPriority (SDCard_RX_ISR_NUMBER, SDCard_RX_ISR_PRIORITY); + (void) CyIntSetVector(SDCard_RX_ISR_NUMBER, &SDCard_RX_ISR); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ + + /* Clear any stray data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + (void) SDCard_ReadTxStatus(); /* Clear Tx status and swStatusTx */ + (void) SDCard_ReadRxStatus(); /* Clear Rx status and swStatusRx */ + + /* Configure TX and RX interrupt mask */ + SDCard_TX_STATUS_MASK_REG = SDCard_TX_INIT_INTERRUPTS_MASK; + SDCard_RX_STATUS_MASK_REG = SDCard_RX_INIT_INTERRUPTS_MASK; +} + + +/******************************************************************************* +* Function Name: SDCard_Enable +******************************************************************************** +* +* Summary: +* Enable SPIM component. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SDCard_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_COUNTER_CONTROL_REG |= SDCard_CNTR_ENABLE; + SDCard_TX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + SDCard_RX_STATUS_ACTL_REG |= SDCard_INT_ENABLE; + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Enable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_EnableTxInt(); + SDCard_EnableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_Start +******************************************************************************** +* +* Summary: +* Initialize and Enable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_initVar - used to check initial configuration, modified on +* first function call. +* +* Theory: +* Enable the clock input to enable operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Start(void) +{ + if(0u == SDCard_initVar) + { + SDCard_Init(); + SDCard_initVar = 1u; + } + + SDCard_Enable(); +} + + +/******************************************************************************* +* Function Name: SDCard_Stop +******************************************************************************** +* +* Summary: +* Disable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the clock input to enable operation. +* +*******************************************************************************/ +void SDCard_Stop(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + SDCard_TX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + SDCard_RX_STATUS_ACTL_REG &= ((uint8) ~SDCard_INT_ENABLE); + CyExitCriticalSection(enableInterrupts); + + #if(0u != SDCard_INTERNAL_CLOCK) + SDCard_IntClock_Disable(); + #endif /* (0u != SDCard_INTERNAL_CLOCK) */ + + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_EnableTxInt +******************************************************************************** +* +* Summary: +* Enable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntEnable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_EnableRxInt +******************************************************************************** +* +* Summary: +* Enable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntEnable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableTxInt +******************************************************************************** +* +* Summary: +* Disable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableTxInt(void) +{ + #if(0u != SDCard_INTERNAL_TX_INT_ENABLED) + CyIntDisable(SDCard_TX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_DisableRxInt +******************************************************************************** +* +* Summary: +* Disable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableRxInt(void) +{ + #if(0u != SDCard_INTERNAL_RX_INT_ENABLED) + CyIntDisable(SDCard_RX_ISR_NUMBER); + #endif /* (0u != SDCard_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_SetTxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetTxInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_SetRxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetRxInterruptMode(uint8 intSrc) +{ + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadTxStatus +******************************************************************************** +* +* Summary: +* Read the Tx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Tx status register. +* +* Global variables: +* SDCard_swStatusTx - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Tx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadTxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = 0u; + + SDCard_EnableTxInt(); + + #else + + tmpStatus = SDCard_TX_STATUS_REG; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxStatus +******************************************************************************** +* +* Summary: +* Read the Rx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Rx status register. +* +* Global variables: +* SDCard_swStatusRx - used to store in software Rx status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Rx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Rx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = 0u; + + SDCard_EnableRxInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: SDCard_WriteTxData +******************************************************************************** +* +* Summary: +* Write a byte of data to be sent across the SPI. +* +* Parameters: +* txDataByte: The data value to send across the SPI. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call if TX Software Buffer is used. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending, modified every function call if TX Software Buffer is used. +* +* Theory: +* Allows the user to transmit any byte of data in a single transfer. +* +* Side Effects: +* If this function is called again before the previous byte is finished then +* the next byte will be appended to the transfer with no time between +* the byte transfers. Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_WriteTxData(uint8 txData) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + + uint8 tempStatus; + uint8 tmpTxBufferRead; + + /* Block if TX buffer is FULL: don't overwrite */ + do + { + tmpTxBufferRead = SDCard_txBufferRead; + if(0u == tmpTxBufferRead) + { + tmpTxBufferRead = (SDCard_TX_BUFFER_SIZE - 1u); + } + else + { + tmpTxBufferRead--; + } + + }while(tmpTxBufferRead == SDCard_txBufferWrite); + + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + tempStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tempStatus; + + + if((SDCard_txBufferRead == SDCard_txBufferWrite) && + (0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL))) + { + /* Put data element into the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + } + else + { + /* Add to the TX software buffer */ + SDCard_txBufferWrite++; + if(SDCard_txBufferWrite >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferWrite = 0u; + } + + if(SDCard_txBufferWrite == SDCard_txBufferRead) + { + SDCard_txBufferRead++; + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + SDCard_txBufferFull = 1u; + } + + SDCard_txBuffer[SDCard_txBufferWrite] = txData; + + SDCard_TX_STATUS_MASK_REG |= SDCard_STS_TX_FIFO_NOT_FULL; + } + + SDCard_EnableTxInt(); + + #else + /* Wait until TX FIFO has a place */ + while(0u == (SDCard_TX_STATUS_REG & SDCard_STS_TX_FIFO_NOT_FULL)) + { + } + + /* Put data element into the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, txData); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ReadRxData +******************************************************************************** +* +* Summary: +* Read the next byte of data received across the SPI. +* +* Parameters: +* None. +* +* Return: +* The next byte of data read from the FIFO. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function +* call if RX Software Buffer is used. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data. +* +* Theory: +* Allows the user to read a byte of data received. +* +* Side Effects: +* Will return invalid data if the FIFO is empty. The user should Call +* GetRxBufferSize() and if it returns a non-zero value then it is safe to call +* ReadByte() function. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadRxData(void) +{ + uint8 rxData; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead != SDCard_rxBufferWrite) + { + if(0u == SDCard_rxBufferFull) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + } + else + { + SDCard_rxBufferFull = 0u; + } + } + + rxData = SDCard_rxBuffer[SDCard_rxBufferRead]; + + SDCard_EnableRxInt(); + + #else + + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(rxData); +} + + +/******************************************************************************* +* Function Name: SDCard_GetRxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the RX buffer. +* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if +* FIFO not empty. In another case function return size of RX Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the RX buffer. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetRxBufferSize(void) +{ + uint8 size; + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + if(SDCard_rxBufferRead == SDCard_rxBufferWrite) + { + size = 0u; + } + else if(SDCard_rxBufferRead < SDCard_rxBufferWrite) + { + size = (SDCard_rxBufferWrite - SDCard_rxBufferRead); + } + else + { + size = (SDCard_RX_BUFFER_SIZE - SDCard_rxBufferRead) + SDCard_rxBufferWrite; + } + + SDCard_EnableRxInt(); + + #else + + /* We can only know if there is data in the RX FIFO */ + size = (0u != (SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u; + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_GetTxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the TX buffer. +* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if +* FIFO not full, 4 - if FIFO full. In another case function return size of TX +* Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the TX buffer. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 SDCard_GetTxBufferSize(void) +{ + uint8 size; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + size = 0u; + } + else if(SDCard_txBufferRead < SDCard_txBufferWrite) + { + size = (SDCard_txBufferWrite - SDCard_txBufferRead); + } + else + { + size = (SDCard_TX_BUFFER_SIZE - SDCard_txBufferRead) + SDCard_txBufferWrite; + } + + SDCard_EnableTxInt(); + + #else + + size = SDCard_TX_STATUS_REG; + + if(0u != (size & SDCard_STS_TX_FIFO_EMPTY)) + { + size = 0u; + } + else if(0u != (size & SDCard_STS_TX_FIFO_NOT_FULL)) + { + size = 1u; + } + else + { + size = SDCard_FIFO_SIZE; + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: SDCard_ClearRxBuffer +******************************************************************************** +* +* Summary: +* Clear the RX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer, modified every function +* call - resets to zero. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any received data not read from the RAM buffer will be lost when overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearRxBuffer(void) +{ + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + SDCard_DisableRxInt(); + + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + + SDCard_EnableRxInt(); + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: SDCard_ClearTxBuffer +******************************************************************************** +* +* Summary: +* Clear the TX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call - resets to zero. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any data not yet transmitted from the RAM buffer will be lost when +* overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_ClearTxBuffer(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + SDCard_DisableTxInt(); + + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + + /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + + SDCard_EnableTxInt(); + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ +} + + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + /******************************************************************************* + * Function Name: SDCard_TxEnable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to transmit. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxEnable(void) + { + SDCard_CONTROL_REG |= SDCard_CTRL_TX_SIGNAL_EN; + } + + + /******************************************************************************* + * Function Name: SDCard_TxDisable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to receive. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void SDCard_TxDisable(void) + { + SDCard_CONTROL_REG &= ((uint8) ~SDCard_CTRL_TX_SIGNAL_EN); + } + +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + + +/******************************************************************************* +* Function Name: SDCard_PutArray +******************************************************************************** +* +* Summary: +* Write available data from ROM/RAM to the TX buffer while space is available +* in the TX buffer. Keep trying until all data is passed to the TX buffer. +* +* Parameters: +* *buffer: Pointer to the location in RAM containing the data to send +* byteCount: The number of bytes to move to the transmit buffer. +* +* Return: +* None. +* +* Side Effects: +* Will stay in this routine until all data has been sent. May get locked in +* this loop if data is not being initiated by the master if there is not +* enough room in the TX FIFO. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) + +{ + uint8 bufIndex; + + bufIndex = 0u; + + while(byteCount > 0u) + { + SDCard_WriteTxData(buffer[bufIndex]); + bufIndex++; + byteCount--; + } +} + + +/******************************************************************************* +* Function Name: SDCard_ClearFIFO +******************************************************************************** +* +* Summary: +* Clear the RX and TX FIFO's of all data for a fresh start. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +void SDCard_ClearFIFO(void) +{ + uint8 enableInterrupts; + + /* Clear Hardware RX FIFO */ + while(0u !=(SDCard_RX_STATUS_REG & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(SDCard_RXDATA_PTR); + } + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + SDCard_AUX_CONTROL_DP0_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP0_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + + #if(SDCard_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + SDCard_AUX_CONTROL_DP1_REG |= ((uint8) SDCard_TX_FIFO_CLR); + SDCard_AUX_CONTROL_DP1_REG &= ((uint8) ~SDCard_TX_FIFO_CLR); + #endif /* (SDCard_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); +} + + +/* Following functions are for version Compatibility, they are obsolete. +* Please do not use it in new projects. +*/ + + +/******************************************************************************* +* Function Name: SDCard_EnableInt +******************************************************************************** +* +* Summary: +* Enable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_EnableInt(void) +{ + SDCard_EnableRxInt(); + SDCard_EnableTxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_DisableInt +******************************************************************************** +* +* Summary: +* Disable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void SDCard_DisableInt(void) +{ + SDCard_DisableTxInt(); + SDCard_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: SDCard_SetInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void SDCard_SetInterruptMode(uint8 intSrc) +{ + SDCard_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~SDCard_STS_SPI_IDLE)); + SDCard_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: SDCard_ReadStatus +******************************************************************************** +* +* Summary: +* Read the status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the status register. +* +* Global variables: +* SDCard_swStatus - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the status register for error detection +* and flow control. +* +* Side Effects: +* Clear status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 SDCard_ReadStatus(void) +{ + uint8 tmpStatus; + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) + + SDCard_DisableInt(); + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + tmpStatus |= SDCard_GET_STATUS_TX(SDCard_swStatusTx); + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + SDCard_swStatusTx = 0u; + SDCard_swStatusRx = 0u; + + SDCard_EnableInt(); + + #else + + tmpStatus = SDCard_RX_STATUS_REG; + tmpStatus |= SDCard_TX_STATUS_REG; + tmpStatus &= ((uint8) ~SDCard_STS_SPI_IDLE); + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED || SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h new file mode 100644 index 0000000..45b000e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h @@ -0,0 +1,367 @@ +/******************************************************************************* +* File Name: SDCard.h +* Version 2.50 +* +* Description: +* Contains the function prototypes, constants and register definition +* of the SPI Master Component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_SDCard_H) +#define CY_SPIM_SDCard_H + +#include "cyfitter.h" +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define SDCard_INTERNAL_CLOCK (0u) + +#if(0u != SDCard_INTERNAL_CLOCK) + #include "SDCard_IntClock.h" +#endif /* (0u != SDCard_INTERNAL_CLOCK) */ + +#define SDCard_MODE (1u) +#define SDCard_DATA_WIDTH (8u) +#define SDCard_MODE_USE_ZERO (1u) +#define SDCard_BIDIRECTIONAL_MODE (0u) + +/* Internal interrupt handling */ +#define SDCard_TX_BUFFER_SIZE (4u) +#define SDCard_RX_BUFFER_SIZE (4u) +#define SDCard_INTERNAL_TX_INT_ENABLED (0u) +#define SDCard_INTERNAL_RX_INT_ENABLED (0u) + +#define SDCard_SINGLE_REG_SIZE (8u) +#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE) + +#define SDCard_FIFO_SIZE (4u) +#define SDCard_TX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_TX_INT_ENABLED) && \ + (SDCard_TX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + +#define SDCard_RX_SOFTWARE_BUF_ENABLED ((0u != SDCard_INTERNAL_RX_INT_ENABLED) && \ + (SDCard_RX_BUFFER_SIZE > SDCard_FIFO_SIZE)) + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint8 cntrPeriod; +} SDCard_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void SDCard_Init(void) ; +void SDCard_Enable(void) ; +void SDCard_Start(void) ; +void SDCard_Stop(void) ; + +void SDCard_EnableTxInt(void) ; +void SDCard_EnableRxInt(void) ; +void SDCard_DisableTxInt(void) ; +void SDCard_DisableRxInt(void) ; + +void SDCard_Sleep(void) ; +void SDCard_Wakeup(void) ; +void SDCard_SaveConfig(void) ; +void SDCard_RestoreConfig(void) ; + +void SDCard_SetTxInterruptMode(uint8 intSrc) ; +void SDCard_SetRxInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadTxStatus(void) ; +uint8 SDCard_ReadRxStatus(void) ; +void SDCard_WriteTxData(uint8 txData) \ + ; +uint8 SDCard_ReadRxData(void) \ + ; +uint8 SDCard_GetRxBufferSize(void) ; +uint8 SDCard_GetTxBufferSize(void) ; +void SDCard_ClearRxBuffer(void) ; +void SDCard_ClearTxBuffer(void) ; +void SDCard_ClearFIFO(void) ; +void SDCard_PutArray(const uint8 buffer[], uint8 byteCount) \ + ; + +#if(0u != SDCard_BIDIRECTIONAL_MODE) + void SDCard_TxEnable(void) ; + void SDCard_TxDisable(void) ; +#endif /* (0u != SDCard_BIDIRECTIONAL_MODE) */ + +CY_ISR_PROTO(SDCard_TX_ISR); +CY_ISR_PROTO(SDCard_RX_ISR); + + +/*************************************** +* Variable with external linkage +***************************************/ + +extern uint8 SDCard_initVar; + + +/*************************************** +* API Constants +***************************************/ + +#define SDCard_TX_ISR_NUMBER ((uint8) (SDCard_TxInternalInterrupt__INTC_NUMBER)) +#define SDCard_RX_ISR_NUMBER ((uint8) (SDCard_RxInternalInterrupt__INTC_NUMBER)) + +#define SDCard_TX_ISR_PRIORITY ((uint8) (SDCard_TxInternalInterrupt__INTC_PRIOR_NUM)) +#define SDCard_RX_ISR_PRIORITY ((uint8) (SDCard_RxInternalInterrupt__INTC_PRIOR_NUM)) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define SDCard_INT_ON_SPI_DONE ((uint8) (0u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_INT_ON_TX_EMPTY ((uint8) (1u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_INT_ON_TX_NOT_FULL ((uint8) (0u << \ + SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_INT_ON_BYTE_COMP ((uint8) (0u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_INT_ON_SPI_IDLE ((uint8) (0u << SDCard_STS_SPI_IDLE_SHIFT)) + +/* Disable TX_NOT_FULL if software buffer is used */ +#define SDCard_INT_ON_TX_NOT_FULL_DEF ((SDCard_TX_SOFTWARE_BUF_ENABLED) ? \ + (0u) : (SDCard_INT_ON_TX_NOT_FULL)) + +/* TX interrupt mask */ +#define SDCard_TX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_BYTE_COMP | \ + SDCard_INT_ON_SPI_IDLE) + +#define SDCard_INT_ON_RX_FULL ((uint8) (0u << \ + SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_INT_ON_RX_NOT_EMPTY ((uint8) (1u << \ + SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_INT_ON_RX_OVER ((uint8) (0u << \ + SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* RX interrupt mask */ +#define SDCard_RX_INIT_INTERRUPTS_MASK (SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER) +/* Nubmer of bits to receive/transmit */ +#define SDCard_BITCTR_INIT (((uint8) (SDCard_DATA_WIDTH << 1u)) - 1u) + + +/*************************************** +* Registers +***************************************/ +#if(CY_PSOC3 || CY_PSOC5) + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) +#else /* PSOC4 */ + #if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_TXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_TXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define SDCard_RXDATA_REG (* (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #define SDCard_RXDATA_PTR ( (reg16 *) \ + SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #else + #define SDCard_TXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_TXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F0_REG) + #define SDCard_RXDATA_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #define SDCard_RXDATA_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__F1_REG) + #endif /* (SDCard_USE_SECOND_DATAPATH) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + +#define SDCard_AUX_CONTROL_DP0_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) +#define SDCard_AUX_CONTROL_DP0_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROL_DP1_REG (* (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) + #define SDCard_AUX_CONTROL_DP1_PTR ( (reg8 *) \ + SDCard_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + +#define SDCard_COUNTER_PERIOD_REG (* (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_PERIOD_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__PERIOD_REG) +#define SDCard_COUNTER_CONTROL_REG (* (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) +#define SDCard_COUNTER_CONTROL_PTR ( (reg8 *) SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) + +#define SDCard_TX_STATUS_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_TX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) +#define SDCard_RX_STATUS_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_REG) + +#define SDCard_CONTROL_REG (* (reg8 *) \ + SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG) +#define SDCard_CONTROL_PTR ( (reg8 *) \ + SDCard_BSPIM_BidirMode_CtrlReg__CONTROL_REG) + +#define SDCard_TX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_TX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) +#define SDCard_RX_STATUS_MASK_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__MASK_REG) + +#define SDCard_TX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_TX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_REG (* (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) +#define SDCard_RX_STATUS_ACTL_PTR ( (reg8 *) SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) + +#if(SDCard_USE_SECOND_DATAPATH) + #define SDCard_AUX_CONTROLDP1 (SDCard_AUX_CONTROL_DP1_REG) +#endif /* (SDCard_USE_SECOND_DATAPATH) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Status Register Definitions */ +#define SDCard_STS_SPI_DONE_SHIFT (0x00u) +#define SDCard_STS_TX_FIFO_EMPTY_SHIFT (0x01u) +#define SDCard_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u) +#define SDCard_STS_BYTE_COMPLETE_SHIFT (0x03u) +#define SDCard_STS_SPI_IDLE_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_FULL_SHIFT (0x04u) +#define SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u) +#define SDCard_STS_RX_FIFO_OVERRUN_SHIFT (0x06u) + +#define SDCard_STS_SPI_DONE ((uint8) (0x01u << SDCard_STS_SPI_DONE_SHIFT)) +#define SDCard_STS_TX_FIFO_EMPTY ((uint8) (0x01u << SDCard_STS_TX_FIFO_EMPTY_SHIFT)) +#define SDCard_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << SDCard_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define SDCard_STS_BYTE_COMPLETE ((uint8) (0x01u << SDCard_STS_BYTE_COMPLETE_SHIFT)) +#define SDCard_STS_SPI_IDLE ((uint8) (0x01u << SDCard_STS_SPI_IDLE_SHIFT)) +#define SDCard_STS_RX_FIFO_FULL ((uint8) (0x01u << SDCard_STS_RX_FIFO_FULL_SHIFT)) +#define SDCard_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << SDCard_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define SDCard_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << SDCard_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* TX and RX masks for clear on read bits */ +#define SDCard_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u) +#define SDCard_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u) + +/* StatusI Register Interrupt Enable Control Bits */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_INT_ENABLE (0x10u) /* Enable interrupt from statusi */ +#define SDCard_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */ +#define SDCard_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */ +#define SDCard_FIFO_CLR (SDCard_TX_FIFO_CLR | SDCard_RX_FIFO_CLR) + +/* Bit Counter (7-bit) Control Register Bit Definitions */ +/* As defined by the Register map for the AUX Control Register */ +#define SDCard_CNTR_ENABLE (0x20u) /* Enable CNT7 */ + +/* Bi-Directional mode control bit */ +#define SDCard_CTRL_TX_SIGNAL_EN (0x01u) + +/* Datapath Auxillary Control Register definitions */ +#define SDCard_AUX_CTRL_FIFO0_CLR (0x01u) +#define SDCard_AUX_CTRL_FIFO1_CLR (0x02u) +#define SDCard_AUX_CTRL_FIFO0_LVL (0x04u) +#define SDCard_AUX_CTRL_FIFO1_LVL (0x08u) +#define SDCard_STATUS_ACTL_INT_EN_MASK (0x10u) + +/* Component disabled */ +#define SDCard_DISABLED (0u) + + +/*************************************** +* Macros +***************************************/ + +/* Returns true if componentn enabled */ +#define SDCard_IS_ENABLED (0u != (SDCard_TX_STATUS_ACTL_REG & SDCard_INT_ENABLE)) + +/* Retuns TX status register */ +#define SDCard_GET_STATUS_TX(swTxSts) ( (uint8)(SDCard_TX_STATUS_REG | \ + ((swTxSts) & SDCard_TX_STS_CLR_ON_RD_BYTES_MASK)) ) +/* Retuns RX status register */ +#define SDCard_GET_STATUS_RX(swRxSts) ( (uint8)(SDCard_RX_STATUS_REG | \ + ((swRxSts) & SDCard_RX_STS_CLR_ON_RD_BYTES_MASK)) ) + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ + +#define SDCard_WriteByte SDCard_WriteTxData +#define SDCard_ReadByte SDCard_ReadRxData +void SDCard_SetInterruptMode(uint8 intSrc) ; +uint8 SDCard_ReadStatus(void) ; +void SDCard_EnableInt(void) ; +void SDCard_DisableInt(void) ; + +#define SDCard_TXDATA (SDCard_TXDATA_REG) +#define SDCard_RXDATA (SDCard_RXDATA_REG) +#define SDCard_AUX_CONTROLDP0 (SDCard_AUX_CONTROL_DP0_REG) +#define SDCard_TXBUFFERREAD (SDCard_txBufferRead) +#define SDCard_TXBUFFERWRITE (SDCard_txBufferWrite) +#define SDCard_RXBUFFERREAD (SDCard_rxBufferRead) +#define SDCard_RXBUFFERWRITE (SDCard_rxBufferWrite) + +#define SDCard_COUNTER_PERIOD (SDCard_COUNTER_PERIOD_REG) +#define SDCard_COUNTER_CONTROL (SDCard_COUNTER_CONTROL_REG) +#define SDCard_STATUS (SDCard_TX_STATUS_REG) +#define SDCard_CONTROL (SDCard_CONTROL_REG) +#define SDCard_STATUS_MASK (SDCard_TX_STATUS_MASK_REG) +#define SDCard_STATUS_ACTL (SDCard_TX_STATUS_ACTL_REG) + +#define SDCard_INIT_INTERRUPTS_MASK (SDCard_INT_ON_SPI_DONE | \ + SDCard_INT_ON_TX_EMPTY | \ + SDCard_INT_ON_TX_NOT_FULL_DEF | \ + SDCard_INT_ON_RX_FULL | \ + SDCard_INT_ON_RX_NOT_EMPTY | \ + SDCard_INT_ON_RX_OVER | \ + SDCard_INT_ON_BYTE_COMP) + +#define SDCard_DataWidth (SDCard_DATA_WIDTH) +#define SDCard_InternalClockUsed (SDCard_INTERNAL_CLOCK) +#define SDCard_InternalTxInterruptEnabled (SDCard_INTERNAL_TX_INT_ENABLED) +#define SDCard_InternalRxInterruptEnabled (SDCard_INTERNAL_RX_INT_ENABLED) +#define SDCard_ModeUseZero (SDCard_MODE_USE_ZERO) +#define SDCard_BidirectionalMode (SDCard_BIDIRECTIONAL_MODE) +#define SDCard_Mode (SDCard_MODE) +#define SDCard_DATAWIDHT (SDCard_DATA_WIDTH) +#define SDCard_InternalInterruptEnabled (0u) + +#define SDCard_TXBUFFERSIZE (SDCard_TX_BUFFER_SIZE) +#define SDCard_RXBUFFERSIZE (SDCard_RX_BUFFER_SIZE) + +#define SDCard_TXBUFFER SDCard_txBuffer +#define SDCard_RXBUFFER SDCard_rxBuffer + +#endif /* (CY_SPIM_SDCard_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c new file mode 100644 index 0000000..04dabdc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_INT.c @@ -0,0 +1,206 @@ +/******************************************************************************* +* File Name: SDCard_INT.c +* Version 2.50 +* +* Description: +* This file provides all Interrupt Service Routine (ISR) for the SPI Master +* component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + + +/* User code required at start of ISR */ +/* `#START SDCard_ISR_START_DEF` */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: SDCard_TX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for TX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* SDCard_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified when exist data to +* sending and FIFO Not Full. +* SDCard_txBuffer[SDCard_TX_BUFFER_SIZE] - used to store +* data to sending. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_TX_ISR) +{ + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + #ifdef SDCard_TX_ISR_ENTRY_CALLBACK + SDCard_TX_ISR_EntryCallback(); + #endif /* SDCard_TX_ISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START SDCard_TX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + /* Check if TX data buffer is not empty and there is space in TX FIFO */ + while(SDCard_txBufferRead != SDCard_txBufferWrite) + { + tmpStatus = SDCard_GET_STATUS_TX(SDCard_swStatusTx); + SDCard_swStatusTx = tmpStatus; + + if(0u != (SDCard_swStatusTx & SDCard_STS_TX_FIFO_NOT_FULL)) + { + if(0u == SDCard_txBufferFull) + { + SDCard_txBufferRead++; + + if(SDCard_txBufferRead >= SDCard_TX_BUFFER_SIZE) + { + SDCard_txBufferRead = 0u; + } + } + else + { + SDCard_txBufferFull = 0u; + } + + /* Put data element into the TX FIFO */ + CY_SET_REG8(SDCard_TXDATA_PTR, + SDCard_txBuffer[SDCard_txBufferRead]); + } + else + { + break; + } + } + + if(SDCard_txBufferRead == SDCard_txBufferWrite) + { + /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */ + SDCard_TX_STATUS_MASK_REG &= ((uint8) ~SDCard_STS_TX_FIFO_NOT_FULL); + } + + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_TX_ISR_END` */ + + /* `#END` */ + + #ifdef SDCard_TX_ISR_EXIT_CALLBACK + SDCard_TX_ISR_ExitCallback(); + #endif /* SDCard_TX_ISR_EXIT_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: SDCard_RX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for RX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* SDCard_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer modified when FIFO contains +* new data. +* SDCard_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified when overflow occurred. +* SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE] - used to store +* received data, modified when FIFO contains new data. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(SDCard_RX_ISR) +{ + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + uint8 rxData; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #ifdef SDCard_RX_ISR_ENTRY_CALLBACK + SDCard_RX_ISR_EntryCallback(); + #endif /* SDCard_RX_ISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START SDCard_RX_ISR_START` */ + + /* `#END` */ + + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + + /* Check if RX data FIFO has some data to be moved into the RX Buffer */ + while(0u != (SDCard_swStatusRx & SDCard_STS_RX_FIFO_NOT_EMPTY)) + { + rxData = CY_GET_REG8(SDCard_RXDATA_PTR); + + /* Set next pointer. */ + SDCard_rxBufferWrite++; + if(SDCard_rxBufferWrite >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferWrite = 0u; + } + + if(SDCard_rxBufferWrite == SDCard_rxBufferRead) + { + SDCard_rxBufferRead++; + if(SDCard_rxBufferRead >= SDCard_RX_BUFFER_SIZE) + { + SDCard_rxBufferRead = 0u; + } + + SDCard_rxBufferFull = 1u; + } + + /* Move data from the FIFO to the Buffer */ + SDCard_rxBuffer[SDCard_rxBufferWrite] = rxData; + + tmpStatus = SDCard_GET_STATUS_RX(SDCard_swStatusRx); + SDCard_swStatusRx = tmpStatus; + } + + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START SDCard_RX_ISR_END` */ + + /* `#END` */ + + #ifdef SDCard_RX_ISR_EXIT_CALLBACK + SDCard_RX_ISR_ExitCallback(); + #endif /* SDCard_RX_ISR_EXIT_CALLBACK */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c new file mode 100644 index 0000000..260ec9a --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PM.c @@ -0,0 +1,149 @@ +/******************************************************************************* +* File Name: SDCard_PM.c +* Version 2.50 +* +* Description: +* This file contains the setup, control and status commands to support +* component operations in low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SDCard_PVT.h" + +static SDCard_BACKUP_STRUCT SDCard_backup = +{ + SDCard_DISABLED, + SDCard_BITCTR_INIT, +}; + + +/******************************************************************************* +* Function Name: SDCard_SaveConfig +******************************************************************************** +* +* Summary: +* Empty function. Included for consistency with other components. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SDCard_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: SDCard_RestoreConfig +******************************************************************************** +* +* Summary: +* Empty function. Included for consistency with other components. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void SDCard_RestoreConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: SDCard_Sleep +******************************************************************************** +* +* Summary: +* Prepare SPIM Component goes to sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Sleep(void) +{ + /* Save components enable state */ + SDCard_backup.enableState = ((uint8) SDCard_IS_ENABLED); + + SDCard_Stop(); +} + + +/******************************************************************************* +* Function Name: SDCard_Wakeup +******************************************************************************** +* +* Summary: +* Prepare SPIM Component to wake up. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* SDCard_backup - used when non-retention registers are restored. +* SDCard_txBufferWrite - modified every function call - resets to +* zero. +* SDCard_txBufferRead - modified every function call - resets to +* zero. +* SDCard_rxBufferWrite - modified every function call - resets to +* zero. +* SDCard_rxBufferRead - modified every function call - resets to +* zero. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void SDCard_Wakeup(void) +{ + #if(SDCard_RX_SOFTWARE_BUF_ENABLED) + SDCard_rxBufferFull = 0u; + SDCard_rxBufferRead = 0u; + SDCard_rxBufferWrite = 0u; + #endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + + #if(SDCard_TX_SOFTWARE_BUF_ENABLED) + SDCard_txBufferFull = 0u; + SDCard_txBufferRead = 0u; + SDCard_txBufferWrite = 0u; + #endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + + /* Clear any data from the RX and TX FIFO */ + SDCard_ClearFIFO(); + + /* Restore components block enable state */ + if(0u != SDCard_backup.enableState) + { + SDCard_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h new file mode 100644 index 0000000..abc6d24 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard_PVT.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: .h +* Version 2.50 +* +* Description: +* This private header file contains internal definitions for the SPIM +* component. Do not use these definitions directly in your application. +* +* Note: +* +******************************************************************************** +* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_PVT_SDCard_H) +#define CY_SPIM_PVT_SDCard_H + +#include "SDCard.h" + + +/********************************** +* Functions with external linkage +**********************************/ + + +/********************************** +* Variables with external linkage +**********************************/ + +extern volatile uint8 SDCard_swStatusTx; +extern volatile uint8 SDCard_swStatusRx; + +#if(SDCard_TX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_txBuffer[SDCard_TX_BUFFER_SIZE]; + extern volatile uint8 SDCard_txBufferRead; + extern volatile uint8 SDCard_txBufferWrite; + extern volatile uint8 SDCard_txBufferFull; +#endif /* (SDCard_TX_SOFTWARE_BUF_ENABLED) */ + +#if(SDCard_RX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 SDCard_rxBuffer[SDCard_RX_BUFFER_SIZE]; + extern volatile uint8 SDCard_rxBufferRead; + extern volatile uint8 SDCard_rxBufferWrite; + extern volatile uint8 SDCard_rxBufferFull; +#endif /* (SDCard_RX_SOFTWARE_BUF_ENABLED) */ + +#endif /* CY_SPIM_PVT_SDCard_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c new file mode 100644 index 0000000..5902cad --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SD_CD.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CD.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CD_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_Write +*******************************************************************************/ +void SD_CD_Write(uint8 value) +{ + uint8 staticBits = (SD_CD_DR & (uint8)(~SD_CD_MASK)); + SD_CD_DR = staticBits | ((uint8)(value << SD_CD_SHIFT) & SD_CD_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CD_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_SetDriveMode +*******************************************************************************/ +void SD_CD_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CD_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CD_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_Read +*******************************************************************************/ +uint8 SD_CD_Read(void) +{ + return (SD_CD_PS & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CD_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_CD_Read() API because the +* SD_CD_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_CD_SUT.c usage_SD_CD_ReadDataReg +*******************************************************************************/ +uint8 SD_CD_ReadDataReg(void) +{ + return (SD_CD_DR & SD_CD_MASK) >> SD_CD_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SD_CD_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CD_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_CD_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_CD_0_INTR (First pin in the list) + * - SD_CD_1_INTR (Second pin in the list) + * - ... + * - SD_CD_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_CD_SUT.c usage_SD_CD_SetInterruptMode + *******************************************************************************/ + void SD_CD_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_CD_0_INTR) != 0u) + { + SD_CD_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_CD_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_CD_SUT.c usage_SD_CD_ClearInterrupt + *******************************************************************************/ + uint8 SD_CD_ClearInterrupt(void) + { + return (SD_CD_INTSTAT & SD_CD_MASK) >> SD_CD_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h new file mode 100644 index 0000000..f07c1dc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_H) /* Pins SD_CD_H */ +#define CY_PINS_SD_CD_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CD_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CD__PORT == 15 && ((SD_CD__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SD_CD_Write(uint8 value); +void SD_CD_SetDriveMode(uint8 mode); +uint8 SD_CD_ReadDataReg(void); +uint8 SD_CD_Read(void); +void SD_CD_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_CD_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_CD_SetDriveMode() function. + * @{ + */ + #define SD_CD_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_CD_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_CD_DM_RES_UP PIN_DM_RES_UP + #define SD_CD_DM_RES_DWN PIN_DM_RES_DWN + #define SD_CD_DM_OD_LO PIN_DM_OD_LO + #define SD_CD_DM_OD_HI PIN_DM_OD_HI + #define SD_CD_DM_STRONG PIN_DM_STRONG + #define SD_CD_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SD_CD_MASK SD_CD__MASK +#define SD_CD_SHIFT SD_CD__SHIFT +#define SD_CD_WIDTH 1u + +/* Interrupt constants */ +#if defined(SD_CD__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_CD_SetInterruptMode() function. + * @{ + */ + #define SD_CD_INTR_NONE (uint16)(0x0000u) + #define SD_CD_INTR_RISING (uint16)(0x0001u) + #define SD_CD_INTR_FALLING (uint16)(0x0002u) + #define SD_CD_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_CD_INTR_MASK (0x01u) +#endif /* (SD_CD__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CD_PS (* (reg8 *) SD_CD__PS) +/* Data Register */ +#define SD_CD_DR (* (reg8 *) SD_CD__DR) +/* Port Number */ +#define SD_CD_PRT_NUM (* (reg8 *) SD_CD__PRT) +/* Connect to Analog Globals */ +#define SD_CD_AG (* (reg8 *) SD_CD__AG) +/* Analog MUX bux enable */ +#define SD_CD_AMUX (* (reg8 *) SD_CD__AMUX) +/* Bidirectional Enable */ +#define SD_CD_BIE (* (reg8 *) SD_CD__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CD_BIT_MASK (* (reg8 *) SD_CD__BIT_MASK) +/* Bypass Enable */ +#define SD_CD_BYP (* (reg8 *) SD_CD__BYP) +/* Port wide control signals */ +#define SD_CD_CTL (* (reg8 *) SD_CD__CTL) +/* Drive Modes */ +#define SD_CD_DM0 (* (reg8 *) SD_CD__DM0) +#define SD_CD_DM1 (* (reg8 *) SD_CD__DM1) +#define SD_CD_DM2 (* (reg8 *) SD_CD__DM2) +/* Input Buffer Disable Override */ +#define SD_CD_INP_DIS (* (reg8 *) SD_CD__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CD_LCD_COM_SEG (* (reg8 *) SD_CD__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CD_LCD_EN (* (reg8 *) SD_CD__LCD_EN) +/* Slew Rate Control */ +#define SD_CD_SLW (* (reg8 *) SD_CD__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CD_PRTDSI__CAPS_SEL (* (reg8 *) SD_CD__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CD_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CD__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CD_PRTDSI__OE_SEL0 (* (reg8 *) SD_CD__PRTDSI__OE_SEL0) +#define SD_CD_PRTDSI__OE_SEL1 (* (reg8 *) SD_CD__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CD_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL0) +#define SD_CD_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CD__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CD_PRTDSI__SYNC_OUT (* (reg8 *) SD_CD__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SD_CD__SIO_CFG) + #define SD_CD_SIO_HYST_EN (* (reg8 *) SD_CD__SIO_HYST_EN) + #define SD_CD_SIO_REG_HIFREQ (* (reg8 *) SD_CD__SIO_REG_HIFREQ) + #define SD_CD_SIO_CFG (* (reg8 *) SD_CD__SIO_CFG) + #define SD_CD_SIO_DIFF (* (reg8 *) SD_CD__SIO_DIFF) +#endif /* (SD_CD__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_CD__INTSTAT) + #define SD_CD_INTSTAT (* (reg8 *) SD_CD__INTSTAT) + #define SD_CD_SNAP (* (reg8 *) SD_CD__SNAP) + + #define SD_CD_0_INTTYPE_REG (* (reg8 *) SD_CD__0__INTTYPE) +#endif /* (SD_CD__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CD_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h new file mode 100644 index 0000000..b27b700 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CD_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_CD.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CD_ALIASES_H) /* Pins SD_CD_ALIASES_H */ +#define CY_PINS_SD_CD_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SD_CD_0 (SD_CD__0__PC) +#define SD_CD_0_INTR ((uint16)((uint16)0x0001u << SD_CD__0__SHIFT)) + +#define SD_CD_INTR_ALL ((uint16)(SD_CD_0_INTR)) + +#endif /* End Pins SD_CD_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c new file mode 100644 index 0000000..af942e0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SD_CS.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_CS.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_CS_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_Write +*******************************************************************************/ +void SD_CS_Write(uint8 value) +{ + uint8 staticBits = (SD_CS_DR & (uint8)(~SD_CS_MASK)); + SD_CS_DR = staticBits | ((uint8)(value << SD_CS_SHIFT) & SD_CS_MASK); +} + + +/******************************************************************************* +* Function Name: SD_CS_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_SetDriveMode +*******************************************************************************/ +void SD_CS_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_CS_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_CS_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_Read +*******************************************************************************/ +uint8 SD_CS_Read(void) +{ + return (SD_CS_PS & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_CS_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_CS_Read() API because the +* SD_CS_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_CS_SUT.c usage_SD_CS_ReadDataReg +*******************************************************************************/ +uint8 SD_CS_ReadDataReg(void) +{ + return (SD_CS_DR & SD_CS_MASK) >> SD_CS_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SD_CS_INTSTAT) + + /******************************************************************************* + * Function Name: SD_CS_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_CS_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_CS_0_INTR (First pin in the list) + * - SD_CS_1_INTR (Second pin in the list) + * - ... + * - SD_CS_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_CS_SUT.c usage_SD_CS_SetInterruptMode + *******************************************************************************/ + void SD_CS_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_CS_0_INTR) != 0u) + { + SD_CS_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_CS_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_CS_SUT.c usage_SD_CS_ClearInterrupt + *******************************************************************************/ + uint8 SD_CS_ClearInterrupt(void) + { + return (SD_CS_INTSTAT & SD_CS_MASK) >> SD_CS_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h new file mode 100644 index 0000000..4de1c1e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_H) /* Pins SD_CS_H */ +#define CY_PINS_SD_CS_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_CS_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_CS__PORT == 15 && ((SD_CS__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SD_CS_Write(uint8 value); +void SD_CS_SetDriveMode(uint8 mode); +uint8 SD_CS_ReadDataReg(void); +uint8 SD_CS_Read(void); +void SD_CS_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_CS_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_CS_SetDriveMode() function. + * @{ + */ + #define SD_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_CS_DM_RES_UP PIN_DM_RES_UP + #define SD_CS_DM_RES_DWN PIN_DM_RES_DWN + #define SD_CS_DM_OD_LO PIN_DM_OD_LO + #define SD_CS_DM_OD_HI PIN_DM_OD_HI + #define SD_CS_DM_STRONG PIN_DM_STRONG + #define SD_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SD_CS_MASK SD_CS__MASK +#define SD_CS_SHIFT SD_CS__SHIFT +#define SD_CS_WIDTH 1u + +/* Interrupt constants */ +#if defined(SD_CS__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_CS_SetInterruptMode() function. + * @{ + */ + #define SD_CS_INTR_NONE (uint16)(0x0000u) + #define SD_CS_INTR_RISING (uint16)(0x0001u) + #define SD_CS_INTR_FALLING (uint16)(0x0002u) + #define SD_CS_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_CS_INTR_MASK (0x01u) +#endif /* (SD_CS__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_CS_PS (* (reg8 *) SD_CS__PS) +/* Data Register */ +#define SD_CS_DR (* (reg8 *) SD_CS__DR) +/* Port Number */ +#define SD_CS_PRT_NUM (* (reg8 *) SD_CS__PRT) +/* Connect to Analog Globals */ +#define SD_CS_AG (* (reg8 *) SD_CS__AG) +/* Analog MUX bux enable */ +#define SD_CS_AMUX (* (reg8 *) SD_CS__AMUX) +/* Bidirectional Enable */ +#define SD_CS_BIE (* (reg8 *) SD_CS__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_CS_BIT_MASK (* (reg8 *) SD_CS__BIT_MASK) +/* Bypass Enable */ +#define SD_CS_BYP (* (reg8 *) SD_CS__BYP) +/* Port wide control signals */ +#define SD_CS_CTL (* (reg8 *) SD_CS__CTL) +/* Drive Modes */ +#define SD_CS_DM0 (* (reg8 *) SD_CS__DM0) +#define SD_CS_DM1 (* (reg8 *) SD_CS__DM1) +#define SD_CS_DM2 (* (reg8 *) SD_CS__DM2) +/* Input Buffer Disable Override */ +#define SD_CS_INP_DIS (* (reg8 *) SD_CS__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_CS_LCD_COM_SEG (* (reg8 *) SD_CS__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_CS_LCD_EN (* (reg8 *) SD_CS__LCD_EN) +/* Slew Rate Control */ +#define SD_CS_SLW (* (reg8 *) SD_CS__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_CS_PRTDSI__CAPS_SEL (* (reg8 *) SD_CS__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_CS__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_CS_PRTDSI__OE_SEL0 (* (reg8 *) SD_CS__PRTDSI__OE_SEL0) +#define SD_CS_PRTDSI__OE_SEL1 (* (reg8 *) SD_CS__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_CS_PRTDSI__OUT_SEL0 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL0) +#define SD_CS_PRTDSI__OUT_SEL1 (* (reg8 *) SD_CS__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_CS_PRTDSI__SYNC_OUT (* (reg8 *) SD_CS__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SD_CS__SIO_CFG) + #define SD_CS_SIO_HYST_EN (* (reg8 *) SD_CS__SIO_HYST_EN) + #define SD_CS_SIO_REG_HIFREQ (* (reg8 *) SD_CS__SIO_REG_HIFREQ) + #define SD_CS_SIO_CFG (* (reg8 *) SD_CS__SIO_CFG) + #define SD_CS_SIO_DIFF (* (reg8 *) SD_CS__SIO_DIFF) +#endif /* (SD_CS__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_CS__INTSTAT) + #define SD_CS_INTSTAT (* (reg8 *) SD_CS__INTSTAT) + #define SD_CS_SNAP (* (reg8 *) SD_CS__SNAP) + + #define SD_CS_0_INTTYPE_REG (* (reg8 *) SD_CS__0__INTTYPE) +#endif /* (SD_CS__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_CS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h new file mode 100644 index 0000000..518086b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_CS_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_CS.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_CS_ALIASES_H) /* Pins SD_CS_ALIASES_H */ +#define CY_PINS_SD_CS_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SD_CS_0 (SD_CS__0__PC) +#define SD_CS_0_INTR ((uint16)((uint16)0x0001u << SD_CS__0__SHIFT)) + +#define SD_CS_INTR_ALL ((uint16)(SD_CS_0_INTR)) + +#endif /* End Pins SD_CS_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c new file mode 100644 index 0000000..f674b35 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.c @@ -0,0 +1,63 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.c +* Version 1.70 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "SD_Clk_Ctl.h" + +#if !defined(SD_Clk_Ctl_Sync_ctrl_reg__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void SD_Clk_Ctl_Write(uint8 control) +{ + SD_Clk_Ctl_Control = control; +} + + +/******************************************************************************* +* Function Name: SD_Clk_Ctl_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 SD_Clk_Ctl_Read(void) +{ + return SD_Clk_Ctl_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h new file mode 100644 index 0000000..862a651 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Clk_Ctl.h @@ -0,0 +1,42 @@ +/******************************************************************************* +* File Name: SD_Clk_Ctl.h +* Version 1.70 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_SD_Clk_Ctl_H) /* CY_CONTROL_REG_SD_Clk_Ctl_H */ +#define CY_CONTROL_REG_SD_Clk_Ctl_H + +#include "cytypes.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Clk_Ctl_Write(uint8 control) ; +uint8 SD_Clk_Ctl_Read(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define SD_Clk_Ctl_Control (* (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) +#define SD_Clk_Ctl_Control_PTR ( (reg8 *) SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_SD_Clk_Ctl_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c new file mode 100644 index 0000000..2e91990 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Data_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Data_Clk_CLKEN |= SD_Data_Clk_CLKEN_MASK; + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StopBlock(void) +{ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Data_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Data_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Data_Clk_CLKSTBY &= (uint8)(~SD_Data_Clk_CLKSTBY_MASK); + } + else + { + SD_Data_Clk_CLKSTBY |= SD_Data_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Data_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Data_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Data_Clk__CFG3) + CLK_DIST_AMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Data_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Data_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Data_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Data_Clk_CLKEN &= (uint8)(~SD_Data_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Data_Clk_CLKEN & SD_Data_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Data_Clk_DIV_PTR, clkDivider); + SD_Data_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Data_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Data_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Data_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Data_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Data_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetModeRegister(void) +{ + return SD_Data_Clk_MOD_SRC & (uint8)(SD_Data_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Data_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Data_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Data_Clk_MOD_SRC |= CYCLK_SSS; + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + SD_Data_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Data_Clk_MOD_SRC = + (SD_Data_Clk_MOD_SRC & (uint8)(~SD_Data_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetSourceRegister(void) +{ + return SD_Data_Clk_MOD_SRC & SD_Data_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Data_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Data_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Data_Clk_PHASE = clkPhase & SD_Data_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Data_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Data_Clk_GetPhaseRegister(void) +{ + return SD_Data_Clk_PHASE & SD_Data_Clk_PHASE_MASK; +} + +#endif /* SD_Data_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h new file mode 100644 index 0000000..dc40003 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Data_Clk.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Data_Clk_H) +#define CY_CLOCK_SD_Data_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Data_Clk_Start(void) ; +void SD_Data_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Data_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Data_Clk_StandbyPower(uint8 state) ; +void SD_Data_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Data_Clk_GetDividerRegister(void) ; +void SD_Data_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Data_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Data_Clk_GetModeRegister(void) ; +void SD_Data_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Data_Clk_GetSourceRegister(void) ; +#if defined(SD_Data_Clk__CFG3) +void SD_Data_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Data_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Data_Clk__CFG3) */ + +#define SD_Data_Clk_Enable() SD_Data_Clk_Start() +#define SD_Data_Clk_Disable() SD_Data_Clk_Stop() +#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1u) +#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u) +#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode) +#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource) +#if defined(SD_Data_Clk__CFG3) +#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase) +#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKEN (* (reg8 *) SD_Data_Clk__PM_ACT_CFG) +#define SD_Data_Clk_CLKEN_PTR ((reg8 *) SD_Data_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Data_Clk_CLKSTBY (* (reg8 *) SD_Data_Clk__PM_STBY_CFG) +#define SD_Data_Clk_CLKSTBY_PTR ((reg8 *) SD_Data_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Data_Clk_DIV_LSB (* (reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_LSB_PTR ((reg8 *) SD_Data_Clk__CFG0) +#define SD_Data_Clk_DIV_PTR ((reg16 *) SD_Data_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Data_Clk_DIV_MSB (* (reg8 *) SD_Data_Clk__CFG1) +#define SD_Data_Clk_DIV_MSB_PTR ((reg8 *) SD_Data_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Data_Clk_MOD_SRC (* (reg8 *) SD_Data_Clk__CFG2) +#define SD_Data_Clk_MOD_SRC_PTR ((reg8 *) SD_Data_Clk__CFG2) + +#if defined(SD_Data_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Data_Clk_PHASE (* (reg8 *) SD_Data_Clk__CFG3) +#define SD_Data_Clk_PHASE_PTR ((reg8 *) SD_Data_Clk__CFG3) +#endif /* defined(SD_Data_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Data_Clk_CLKEN_MASK SD_Data_Clk__PM_ACT_MSK +#define SD_Data_Clk_CLKSTBY_MASK SD_Data_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Data_Clk_SRC_SEL_MSK SD_Data_Clk__CFG2_SRC_SEL_MASK +#define SD_Data_Clk_MODE_MASK (~(SD_Data_Clk_SRC_SEL_MSK)) + +#if defined(SD_Data_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Data_Clk_PHASE_MASK SD_Data_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Data_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Data_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c new file mode 100644 index 0000000..b061470 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.c +* Version 2.10 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "SD_Init_Clk.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Start(void) +{ + /* Set the bit to enable the clock. */ + SD_Init_Clk_CLKEN |= SD_Init_Clk_CLKEN_MASK; + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_Stop(void) +{ + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StopBlock(void) +{ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(SD_Init_Clk_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: SD_Init_Clk_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_StandbyPower(uint8 state) +{ + if(state == 0u) + { + SD_Init_Clk_CLKSTBY &= (uint8)(~SD_Init_Clk_CLKSTBY_MASK); + } + else + { + SD_Init_Clk_CLKSTBY |= SD_Init_Clk_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = SD_Init_Clk_GetSourceRegister(); + uint16 oldDivider = SD_Init_Clk_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(SD_Init_Clk__CFG3) + CLK_DIST_AMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = SD_Init_Clk_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* SD_Init_Clk__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((SD_Init_Clk_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + SD_Init_Clk_CLKEN &= (uint8)(~SD_Init_Clk_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((SD_Init_Clk_CLKEN & SD_Init_Clk_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(SD_Init_Clk_DIV_PTR, clkDivider); + SD_Init_Clk_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 SD_Init_Clk_GetDividerRegister(void) +{ + return CY_GET_REG16(SD_Init_Clk_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC |= modeBitMask & (uint8)SD_Init_Clk_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) +{ + SD_Init_Clk_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(SD_Init_Clk_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetModeRegister(void) +{ + return SD_Init_Clk_MOD_SRC & (uint8)(SD_Init_Clk_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = SD_Init_Clk_GetDividerRegister(); + uint8 oldSrc = SD_Init_Clk_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + SD_Init_Clk_MOD_SRC |= CYCLK_SSS; + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + SD_Init_Clk_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + SD_Init_Clk_MOD_SRC = + (SD_Init_Clk_MOD_SRC & (uint8)(~SD_Init_Clk_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetSourceRegister(void) +{ + return SD_Init_Clk_MOD_SRC & SD_Init_Clk_SRC_SEL_MSK; +} + + +#if defined(SD_Init_Clk__CFG3) + + +/******************************************************************************* +* Function Name: SD_Init_Clk_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) +{ + SD_Init_Clk_PHASE = clkPhase & SD_Init_Clk_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: SD_Init_Clk_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 SD_Init_Clk_GetPhaseRegister(void) +{ + return SD_Init_Clk_PHASE & SD_Init_Clk_PHASE_MASK; +} + +#endif /* SD_Init_Clk__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h new file mode 100644 index 0000000..43c2e06 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: SD_Init_Clk.h +* Version 2.10 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_SD_Init_Clk_H) +#define CY_CLOCK_SD_Init_Clk_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_Init_Clk_Start(void) ; +void SD_Init_Clk_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void SD_Init_Clk_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void SD_Init_Clk_StandbyPower(uint8 state) ; +void SD_Init_Clk_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 SD_Init_Clk_GetDividerRegister(void) ; +void SD_Init_Clk_SetModeRegister(uint8 modeBitMask) ; +void SD_Init_Clk_ClearModeRegister(uint8 modeBitMask) ; +uint8 SD_Init_Clk_GetModeRegister(void) ; +void SD_Init_Clk_SetSourceRegister(uint8 clkSource) ; +uint8 SD_Init_Clk_GetSourceRegister(void) ; +#if defined(SD_Init_Clk__CFG3) +void SD_Init_Clk_SetPhaseRegister(uint8 clkPhase) ; +uint8 SD_Init_Clk_GetPhaseRegister(void) ; +#endif /* defined(SD_Init_Clk__CFG3) */ + +#define SD_Init_Clk_Enable() SD_Init_Clk_Start() +#define SD_Init_Clk_Disable() SD_Init_Clk_Stop() +#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u) +#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u) +#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode) +#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource) +#if defined(SD_Init_Clk__CFG3) +#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase) +#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKEN (* (reg8 *) SD_Init_Clk__PM_ACT_CFG) +#define SD_Init_Clk_CLKEN_PTR ((reg8 *) SD_Init_Clk__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define SD_Init_Clk_CLKSTBY (* (reg8 *) SD_Init_Clk__PM_STBY_CFG) +#define SD_Init_Clk_CLKSTBY_PTR ((reg8 *) SD_Init_Clk__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define SD_Init_Clk_DIV_LSB (* (reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_LSB_PTR ((reg8 *) SD_Init_Clk__CFG0) +#define SD_Init_Clk_DIV_PTR ((reg16 *) SD_Init_Clk__CFG0) + +/* Clock MSB divider configuration register. */ +#define SD_Init_Clk_DIV_MSB (* (reg8 *) SD_Init_Clk__CFG1) +#define SD_Init_Clk_DIV_MSB_PTR ((reg8 *) SD_Init_Clk__CFG1) + +/* Mode and source configuration register */ +#define SD_Init_Clk_MOD_SRC (* (reg8 *) SD_Init_Clk__CFG2) +#define SD_Init_Clk_MOD_SRC_PTR ((reg8 *) SD_Init_Clk__CFG2) + +#if defined(SD_Init_Clk__CFG3) +/* Analog clock phase configuration register */ +#define SD_Init_Clk_PHASE (* (reg8 *) SD_Init_Clk__CFG3) +#define SD_Init_Clk_PHASE_PTR ((reg8 *) SD_Init_Clk__CFG3) +#endif /* defined(SD_Init_Clk__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define SD_Init_Clk_CLKEN_MASK SD_Init_Clk__PM_ACT_MSK +#define SD_Init_Clk_CLKSTBY_MASK SD_Init_Clk__PM_STBY_MSK + +/* CFG2 field masks */ +#define SD_Init_Clk_SRC_SEL_MSK SD_Init_Clk__CFG2_SRC_SEL_MASK +#define SD_Init_Clk_MODE_MASK (~(SD_Init_Clk_SRC_SEL_MSK)) + +#if defined(SD_Init_Clk__CFG3) +/* CFG3 phase mask */ +#define SD_Init_Clk_PHASE_MASK SD_Init_Clk__CFG3_PHASE_DLY_MASK +#endif /* defined(SD_Init_Clk__CFG3) */ + +#endif /* CY_CLOCK_SD_Init_Clk_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c new file mode 100644 index 0000000..b0d8ffc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SD_MISO.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MISO.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MISO_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_Write +*******************************************************************************/ +void SD_MISO_Write(uint8 value) +{ + uint8 staticBits = (SD_MISO_DR & (uint8)(~SD_MISO_MASK)); + SD_MISO_DR = staticBits | ((uint8)(value << SD_MISO_SHIFT) & SD_MISO_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MISO_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_SetDriveMode +*******************************************************************************/ +void SD_MISO_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MISO_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MISO_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_Read +*******************************************************************************/ +uint8 SD_MISO_Read(void) +{ + return (SD_MISO_PS & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MISO_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_MISO_Read() API because the +* SD_MISO_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_MISO_SUT.c usage_SD_MISO_ReadDataReg +*******************************************************************************/ +uint8 SD_MISO_ReadDataReg(void) +{ + return (SD_MISO_DR & SD_MISO_MASK) >> SD_MISO_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SD_MISO_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MISO_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_MISO_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_MISO_0_INTR (First pin in the list) + * - SD_MISO_1_INTR (Second pin in the list) + * - ... + * - SD_MISO_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_MISO_SUT.c usage_SD_MISO_SetInterruptMode + *******************************************************************************/ + void SD_MISO_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_MISO_0_INTR) != 0u) + { + SD_MISO_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_MISO_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_MISO_SUT.c usage_SD_MISO_ClearInterrupt + *******************************************************************************/ + uint8 SD_MISO_ClearInterrupt(void) + { + return (SD_MISO_INTSTAT & SD_MISO_MASK) >> SD_MISO_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h new file mode 100644 index 0000000..5969f54 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_H) /* Pins SD_MISO_H */ +#define CY_PINS_SD_MISO_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MISO_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MISO__PORT == 15 && ((SD_MISO__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SD_MISO_Write(uint8 value); +void SD_MISO_SetDriveMode(uint8 mode); +uint8 SD_MISO_ReadDataReg(void); +uint8 SD_MISO_Read(void); +void SD_MISO_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_MISO_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_MISO_SetDriveMode() function. + * @{ + */ + #define SD_MISO_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_MISO_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_MISO_DM_RES_UP PIN_DM_RES_UP + #define SD_MISO_DM_RES_DWN PIN_DM_RES_DWN + #define SD_MISO_DM_OD_LO PIN_DM_OD_LO + #define SD_MISO_DM_OD_HI PIN_DM_OD_HI + #define SD_MISO_DM_STRONG PIN_DM_STRONG + #define SD_MISO_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SD_MISO_MASK SD_MISO__MASK +#define SD_MISO_SHIFT SD_MISO__SHIFT +#define SD_MISO_WIDTH 1u + +/* Interrupt constants */ +#if defined(SD_MISO__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_MISO_SetInterruptMode() function. + * @{ + */ + #define SD_MISO_INTR_NONE (uint16)(0x0000u) + #define SD_MISO_INTR_RISING (uint16)(0x0001u) + #define SD_MISO_INTR_FALLING (uint16)(0x0002u) + #define SD_MISO_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_MISO_INTR_MASK (0x01u) +#endif /* (SD_MISO__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MISO_PS (* (reg8 *) SD_MISO__PS) +/* Data Register */ +#define SD_MISO_DR (* (reg8 *) SD_MISO__DR) +/* Port Number */ +#define SD_MISO_PRT_NUM (* (reg8 *) SD_MISO__PRT) +/* Connect to Analog Globals */ +#define SD_MISO_AG (* (reg8 *) SD_MISO__AG) +/* Analog MUX bux enable */ +#define SD_MISO_AMUX (* (reg8 *) SD_MISO__AMUX) +/* Bidirectional Enable */ +#define SD_MISO_BIE (* (reg8 *) SD_MISO__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MISO_BIT_MASK (* (reg8 *) SD_MISO__BIT_MASK) +/* Bypass Enable */ +#define SD_MISO_BYP (* (reg8 *) SD_MISO__BYP) +/* Port wide control signals */ +#define SD_MISO_CTL (* (reg8 *) SD_MISO__CTL) +/* Drive Modes */ +#define SD_MISO_DM0 (* (reg8 *) SD_MISO__DM0) +#define SD_MISO_DM1 (* (reg8 *) SD_MISO__DM1) +#define SD_MISO_DM2 (* (reg8 *) SD_MISO__DM2) +/* Input Buffer Disable Override */ +#define SD_MISO_INP_DIS (* (reg8 *) SD_MISO__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MISO_LCD_COM_SEG (* (reg8 *) SD_MISO__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MISO_LCD_EN (* (reg8 *) SD_MISO__LCD_EN) +/* Slew Rate Control */ +#define SD_MISO_SLW (* (reg8 *) SD_MISO__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MISO_PRTDSI__CAPS_SEL (* (reg8 *) SD_MISO__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MISO_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MISO__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MISO_PRTDSI__OE_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL0) +#define SD_MISO_PRTDSI__OE_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MISO_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL0) +#define SD_MISO_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MISO__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MISO_PRTDSI__SYNC_OUT (* (reg8 *) SD_MISO__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SD_MISO__SIO_CFG) + #define SD_MISO_SIO_HYST_EN (* (reg8 *) SD_MISO__SIO_HYST_EN) + #define SD_MISO_SIO_REG_HIFREQ (* (reg8 *) SD_MISO__SIO_REG_HIFREQ) + #define SD_MISO_SIO_CFG (* (reg8 *) SD_MISO__SIO_CFG) + #define SD_MISO_SIO_DIFF (* (reg8 *) SD_MISO__SIO_DIFF) +#endif /* (SD_MISO__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_MISO__INTSTAT) + #define SD_MISO_INTSTAT (* (reg8 *) SD_MISO__INTSTAT) + #define SD_MISO_SNAP (* (reg8 *) SD_MISO__SNAP) + + #define SD_MISO_0_INTTYPE_REG (* (reg8 *) SD_MISO__0__INTTYPE) +#endif /* (SD_MISO__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MISO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h new file mode 100644 index 0000000..9b423ad --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MISO_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_MISO.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MISO_ALIASES_H) /* Pins SD_MISO_ALIASES_H */ +#define CY_PINS_SD_MISO_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SD_MISO_0 (SD_MISO__0__PC) +#define SD_MISO_0_INTR ((uint16)((uint16)0x0001u << SD_MISO__0__SHIFT)) + +#define SD_MISO_INTR_ALL ((uint16)(SD_MISO_0_INTR)) + +#endif /* End Pins SD_MISO_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c new file mode 100644 index 0000000..3453f66 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SD_MOSI.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_MOSI.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_MOSI_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Write +*******************************************************************************/ +void SD_MOSI_Write(uint8 value) +{ + uint8 staticBits = (SD_MOSI_DR & (uint8)(~SD_MOSI_MASK)); + SD_MOSI_DR = staticBits | ((uint8)(value << SD_MOSI_SHIFT) & SD_MOSI_MASK); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetDriveMode +*******************************************************************************/ +void SD_MOSI_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_MOSI_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_MOSI_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_Read +*******************************************************************************/ +uint8 SD_MOSI_Read(void) +{ + return (SD_MOSI_PS & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_MOSI_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_MOSI_Read() API because the +* SD_MOSI_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_MOSI_SUT.c usage_SD_MOSI_ReadDataReg +*******************************************************************************/ +uint8 SD_MOSI_ReadDataReg(void) +{ + return (SD_MOSI_DR & SD_MOSI_MASK) >> SD_MOSI_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SD_MOSI_INTSTAT) + + /******************************************************************************* + * Function Name: SD_MOSI_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_MOSI_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_MOSI_0_INTR (First pin in the list) + * - SD_MOSI_1_INTR (Second pin in the list) + * - ... + * - SD_MOSI_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_MOSI_SUT.c usage_SD_MOSI_SetInterruptMode + *******************************************************************************/ + void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_MOSI_0_INTR) != 0u) + { + SD_MOSI_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_MOSI_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_MOSI_SUT.c usage_SD_MOSI_ClearInterrupt + *******************************************************************************/ + uint8 SD_MOSI_ClearInterrupt(void) + { + return (SD_MOSI_INTSTAT & SD_MOSI_MASK) >> SD_MOSI_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h new file mode 100644 index 0000000..a2e6d91 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_H) /* Pins SD_MOSI_H */ +#define CY_PINS_SD_MOSI_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_MOSI_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_MOSI__PORT == 15 && ((SD_MOSI__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SD_MOSI_Write(uint8 value); +void SD_MOSI_SetDriveMode(uint8 mode); +uint8 SD_MOSI_ReadDataReg(void); +uint8 SD_MOSI_Read(void); +void SD_MOSI_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_MOSI_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_MOSI_SetDriveMode() function. + * @{ + */ + #define SD_MOSI_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_MOSI_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_MOSI_DM_RES_UP PIN_DM_RES_UP + #define SD_MOSI_DM_RES_DWN PIN_DM_RES_DWN + #define SD_MOSI_DM_OD_LO PIN_DM_OD_LO + #define SD_MOSI_DM_OD_HI PIN_DM_OD_HI + #define SD_MOSI_DM_STRONG PIN_DM_STRONG + #define SD_MOSI_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SD_MOSI_MASK SD_MOSI__MASK +#define SD_MOSI_SHIFT SD_MOSI__SHIFT +#define SD_MOSI_WIDTH 1u + +/* Interrupt constants */ +#if defined(SD_MOSI__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_MOSI_SetInterruptMode() function. + * @{ + */ + #define SD_MOSI_INTR_NONE (uint16)(0x0000u) + #define SD_MOSI_INTR_RISING (uint16)(0x0001u) + #define SD_MOSI_INTR_FALLING (uint16)(0x0002u) + #define SD_MOSI_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_MOSI_INTR_MASK (0x01u) +#endif /* (SD_MOSI__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_MOSI_PS (* (reg8 *) SD_MOSI__PS) +/* Data Register */ +#define SD_MOSI_DR (* (reg8 *) SD_MOSI__DR) +/* Port Number */ +#define SD_MOSI_PRT_NUM (* (reg8 *) SD_MOSI__PRT) +/* Connect to Analog Globals */ +#define SD_MOSI_AG (* (reg8 *) SD_MOSI__AG) +/* Analog MUX bux enable */ +#define SD_MOSI_AMUX (* (reg8 *) SD_MOSI__AMUX) +/* Bidirectional Enable */ +#define SD_MOSI_BIE (* (reg8 *) SD_MOSI__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_MOSI_BIT_MASK (* (reg8 *) SD_MOSI__BIT_MASK) +/* Bypass Enable */ +#define SD_MOSI_BYP (* (reg8 *) SD_MOSI__BYP) +/* Port wide control signals */ +#define SD_MOSI_CTL (* (reg8 *) SD_MOSI__CTL) +/* Drive Modes */ +#define SD_MOSI_DM0 (* (reg8 *) SD_MOSI__DM0) +#define SD_MOSI_DM1 (* (reg8 *) SD_MOSI__DM1) +#define SD_MOSI_DM2 (* (reg8 *) SD_MOSI__DM2) +/* Input Buffer Disable Override */ +#define SD_MOSI_INP_DIS (* (reg8 *) SD_MOSI__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_MOSI_LCD_COM_SEG (* (reg8 *) SD_MOSI__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_MOSI_LCD_EN (* (reg8 *) SD_MOSI__LCD_EN) +/* Slew Rate Control */ +#define SD_MOSI_SLW (* (reg8 *) SD_MOSI__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_MOSI_PRTDSI__CAPS_SEL (* (reg8 *) SD_MOSI__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_MOSI_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_MOSI__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_MOSI_PRTDSI__OE_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL0) +#define SD_MOSI_PRTDSI__OE_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_MOSI_PRTDSI__OUT_SEL0 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL0) +#define SD_MOSI_PRTDSI__OUT_SEL1 (* (reg8 *) SD_MOSI__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_MOSI_PRTDSI__SYNC_OUT (* (reg8 *) SD_MOSI__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SD_MOSI__SIO_CFG) + #define SD_MOSI_SIO_HYST_EN (* (reg8 *) SD_MOSI__SIO_HYST_EN) + #define SD_MOSI_SIO_REG_HIFREQ (* (reg8 *) SD_MOSI__SIO_REG_HIFREQ) + #define SD_MOSI_SIO_CFG (* (reg8 *) SD_MOSI__SIO_CFG) + #define SD_MOSI_SIO_DIFF (* (reg8 *) SD_MOSI__SIO_DIFF) +#endif /* (SD_MOSI__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_MOSI__INTSTAT) + #define SD_MOSI_INTSTAT (* (reg8 *) SD_MOSI__INTSTAT) + #define SD_MOSI_SNAP (* (reg8 *) SD_MOSI__SNAP) + + #define SD_MOSI_0_INTTYPE_REG (* (reg8 *) SD_MOSI__0__INTTYPE) +#endif /* (SD_MOSI__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_MOSI_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h new file mode 100644 index 0000000..072ad24 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_MOSI_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_MOSI.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_MOSI_ALIASES_H) /* Pins SD_MOSI_ALIASES_H */ +#define CY_PINS_SD_MOSI_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SD_MOSI_0 (SD_MOSI__0__PC) +#define SD_MOSI_0_INTR ((uint16)((uint16)0x0001u << SD_MOSI__0__SHIFT)) + +#define SD_MOSI_INTR_ALL ((uint16)(SD_MOSI_0_INTR)) + +#endif /* End Pins SD_MOSI_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c new file mode 100644 index 0000000..94260ef --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SD_RX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SD_RX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SD_RX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */ + SD_RX_DMA_COMPLETE_SetVector(&SD_RX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_RX_DMA_COMPLETE Interrupt. */ + SD_RX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SD_RX_DMA_COMPLETE_SetPriority((uint8)SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_RX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SD_RX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SD_RX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SD_RX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SD_RX_DMA_COMPLETE_Interrupt) +{ + #ifdef SD_RX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK + SD_RX_DMA_COMPLETE_Interrupt_InterruptCallback(); + #endif /* SD_RX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SD_RX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SD_RX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SD_RX_DMA_COMPLETE_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SD_RX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_RX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx will +* override any effect this API would have had. This API should only be called +* after SD_RX_DMA_COMPLETE_Start or SD_RX_DMA_COMPLETE_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SD_RX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SD_RX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SD_RX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SD_RX_DMA_COMPLETE_INTC_SET_EN = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SD_RX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SD_RX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_RX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SD_RX_DMA_COMPLETE_INTC_CLR_EN = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_SetPending(void) +{ + *SD_RX_DMA_COMPLETE_INTC_SET_PD = SD_RX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_RX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_RX_DMA_COMPLETE_ClearPending(void) +{ + *SD_RX_DMA_COMPLETE_INTC_CLR_PD = SD_RX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h new file mode 100644 index 0000000..6f28592 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SD_RX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SD_RX_DMA_COMPLETE_H) +#define CY_ISR_SD_RX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SD_RX_DMA_COMPLETE_Start(void); +void SD_RX_DMA_COMPLETE_StartEx(cyisraddress address); +void SD_RX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SD_RX_DMA_COMPLETE_Interrupt); + +void SD_RX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SD_RX_DMA_COMPLETE_GetVector(void); + +void SD_RX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SD_RX_DMA_COMPLETE_GetPriority(void); + +void SD_RX_DMA_COMPLETE_Enable(void); +uint8 SD_RX_DMA_COMPLETE_GetState(void); +void SD_RX_DMA_COMPLETE_Disable(void); + +void SD_RX_DMA_COMPLETE_SetPending(void); +void SD_RX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SD_RX_DMA_COMPLETE ISR. */ +#define SD_RX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_RX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SD_RX_DMA_COMPLETE ISR priority. */ +#define SD_RX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_RX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SD_RX_DMA_COMPLETE interrupt state to pending. */ +#define SD_RX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SD_RX_DMA_COMPLETE interrupt. */ +#define SD_RX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SD_RX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c new file mode 100644 index 0000000..b2b9bf1 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SD_RX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SD_RX_DMA__DRQ_CTL_REG +* +* +* SD_RX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SD_RX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SD_RX_DMA__PRIORITY +* +* True if SD_RX_DMA_TERMIN_SEL is used. +* SD_RX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SD_RX_DMA__TERMIN_SEL +* +* +* True if SD_RX_DMA_TERMOUT0_SEL is used. +* SD_RX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SD_RX_DMA__TERMOUT0_SEL +* +* +* True if SD_RX_DMA_TERMOUT1_SEL is used. +* SD_RX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SD_RX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SD_RX_DMA dma channel */ +uint8 SD_RX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SD_RX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SD_RX_DMA_DmaHandle = (uint8)SD_RX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SD_RX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SD_RX_DMA__TERMOUT0_SEL, + (uint8)SD_RX_DMA__TERMOUT1_SEL, + (uint8)SD_RX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SD_RX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SD_RX_DMA_DmaHandle, (uint8)SD_RX_DMA__PRIORITY); + + return SD_RX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SD_RX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SD_RX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SD_RX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SD_RX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h new file mode 100644 index 0000000..c38d0da --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_RX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SD_RX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SD_RX_DMA_DMA_H__) +#define CY_DMA_SD_RX_DMA_DMA_H__ + + + +#include +#include + +#define SD_RX_DMA__TD_TERMOUT_EN (((0 != SD_RX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SD_RX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SD_RX_DMA dma channel */ +extern uint8 SD_RX_DMA_DmaHandle; + + +uint8 SD_RX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SD_RX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SD_RX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c new file mode 100644 index 0000000..83e9d9b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: SD_SCK.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_SCK.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_SCK_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_Write +*******************************************************************************/ +void SD_SCK_Write(uint8 value) +{ + uint8 staticBits = (SD_SCK_DR & (uint8)(~SD_SCK_MASK)); + SD_SCK_DR = staticBits | ((uint8)(value << SD_SCK_SHIFT) & SD_SCK_MASK); +} + + +/******************************************************************************* +* Function Name: SD_SCK_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_SetDriveMode +*******************************************************************************/ +void SD_SCK_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_SCK_0, mode); +} + + +/******************************************************************************* +* Function Name: SD_SCK_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_Read +*******************************************************************************/ +uint8 SD_SCK_Read(void) +{ + return (SD_SCK_PS & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_SCK_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SD_SCK_Read() API because the +* SD_SCK_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SD_SCK_SUT.c usage_SD_SCK_ReadDataReg +*******************************************************************************/ +uint8 SD_SCK_ReadDataReg(void) +{ + return (SD_SCK_DR & SD_SCK_MASK) >> SD_SCK_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SD_SCK_INTSTAT) + + /******************************************************************************* + * Function Name: SD_SCK_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SD_SCK_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SD_SCK_0_INTR (First pin in the list) + * - SD_SCK_1_INTR (Second pin in the list) + * - ... + * - SD_SCK_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SD_SCK_SUT.c usage_SD_SCK_SetInterruptMode + *******************************************************************************/ + void SD_SCK_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SD_SCK_0_INTR) != 0u) + { + SD_SCK_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SD_SCK_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SD_SCK_SUT.c usage_SD_SCK_ClearInterrupt + *******************************************************************************/ + uint8 SD_SCK_ClearInterrupt(void) + { + return (SD_SCK_INTSTAT & SD_SCK_MASK) >> SD_SCK_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h new file mode 100644 index 0000000..a6d9486 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_H) /* Pins SD_SCK_H */ +#define CY_PINS_SD_SCK_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_SCK_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_SCK__PORT == 15 && ((SD_SCK__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SD_SCK_Write(uint8 value); +void SD_SCK_SetDriveMode(uint8 mode); +uint8 SD_SCK_ReadDataReg(void); +uint8 SD_SCK_Read(void); +void SD_SCK_SetInterruptMode(uint16 position, uint16 mode); +uint8 SD_SCK_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SD_SCK_SetDriveMode() function. + * @{ + */ + #define SD_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SD_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SD_SCK_DM_RES_UP PIN_DM_RES_UP + #define SD_SCK_DM_RES_DWN PIN_DM_RES_DWN + #define SD_SCK_DM_OD_LO PIN_DM_OD_LO + #define SD_SCK_DM_OD_HI PIN_DM_OD_HI + #define SD_SCK_DM_STRONG PIN_DM_STRONG + #define SD_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SD_SCK_MASK SD_SCK__MASK +#define SD_SCK_SHIFT SD_SCK__SHIFT +#define SD_SCK_WIDTH 1u + +/* Interrupt constants */ +#if defined(SD_SCK__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SD_SCK_SetInterruptMode() function. + * @{ + */ + #define SD_SCK_INTR_NONE (uint16)(0x0000u) + #define SD_SCK_INTR_RISING (uint16)(0x0001u) + #define SD_SCK_INTR_FALLING (uint16)(0x0002u) + #define SD_SCK_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SD_SCK_INTR_MASK (0x01u) +#endif /* (SD_SCK__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_SCK_PS (* (reg8 *) SD_SCK__PS) +/* Data Register */ +#define SD_SCK_DR (* (reg8 *) SD_SCK__DR) +/* Port Number */ +#define SD_SCK_PRT_NUM (* (reg8 *) SD_SCK__PRT) +/* Connect to Analog Globals */ +#define SD_SCK_AG (* (reg8 *) SD_SCK__AG) +/* Analog MUX bux enable */ +#define SD_SCK_AMUX (* (reg8 *) SD_SCK__AMUX) +/* Bidirectional Enable */ +#define SD_SCK_BIE (* (reg8 *) SD_SCK__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_SCK_BIT_MASK (* (reg8 *) SD_SCK__BIT_MASK) +/* Bypass Enable */ +#define SD_SCK_BYP (* (reg8 *) SD_SCK__BYP) +/* Port wide control signals */ +#define SD_SCK_CTL (* (reg8 *) SD_SCK__CTL) +/* Drive Modes */ +#define SD_SCK_DM0 (* (reg8 *) SD_SCK__DM0) +#define SD_SCK_DM1 (* (reg8 *) SD_SCK__DM1) +#define SD_SCK_DM2 (* (reg8 *) SD_SCK__DM2) +/* Input Buffer Disable Override */ +#define SD_SCK_INP_DIS (* (reg8 *) SD_SCK__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_SCK_LCD_COM_SEG (* (reg8 *) SD_SCK__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_SCK_LCD_EN (* (reg8 *) SD_SCK__LCD_EN) +/* Slew Rate Control */ +#define SD_SCK_SLW (* (reg8 *) SD_SCK__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_SCK_PRTDSI__CAPS_SEL (* (reg8 *) SD_SCK__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_SCK__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_SCK_PRTDSI__OE_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL0) +#define SD_SCK_PRTDSI__OE_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL0) +#define SD_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) SD_SCK__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_SCK_PRTDSI__SYNC_OUT (* (reg8 *) SD_SCK__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SD_SCK__SIO_CFG) + #define SD_SCK_SIO_HYST_EN (* (reg8 *) SD_SCK__SIO_HYST_EN) + #define SD_SCK_SIO_REG_HIFREQ (* (reg8 *) SD_SCK__SIO_REG_HIFREQ) + #define SD_SCK_SIO_CFG (* (reg8 *) SD_SCK__SIO_CFG) + #define SD_SCK_SIO_DIFF (* (reg8 *) SD_SCK__SIO_DIFF) +#endif /* (SD_SCK__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SD_SCK__INTSTAT) + #define SD_SCK_INTSTAT (* (reg8 *) SD_SCK__INTSTAT) + #define SD_SCK_SNAP (* (reg8 *) SD_SCK__SNAP) + + #define SD_SCK_0_INTTYPE_REG (* (reg8 *) SD_SCK__0__INTTYPE) +#endif /* (SD_SCK__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_SCK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h new file mode 100644 index 0000000..efb8d7c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_SCK_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: SD_SCK.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_SCK_ALIASES_H) /* Pins SD_SCK_ALIASES_H */ +#define CY_PINS_SD_SCK_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SD_SCK_0 (SD_SCK__0__PC) +#define SD_SCK_0_INTR ((uint16)((uint16)0x0001u << SD_SCK__0__SHIFT)) + +#define SD_SCK_INTR_ALL ((uint16)(SD_SCK_0_INTR)) + +#endif /* End Pins SD_SCK_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c new file mode 100644 index 0000000..7203eb8 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.c @@ -0,0 +1,409 @@ +/******************************************************************************* +* File Name: SD_TX_DMA_COMPLETE.c +* Version 1.70 +* +* Description: +* API for controlling the state of an interrupt. +* +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include +#include +#include + + +#if !defined(SD_TX_DMA_COMPLETE__REMOVED) /* Check for removal by optimization */ + +/******************************************************************************* +* Place your includes, defines and code here +********************************************************************************/ +/* `#START SD_TX_DMA_COMPLETE_intc` */ + +/* `#END` */ + +#ifndef CYINT_IRQ_BASE +#define CYINT_IRQ_BASE 16 +#endif /* CYINT_IRQ_BASE */ +#ifndef CYINT_VECT_TABLE +#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) +#endif /* CYINT_VECT_TABLE */ + +/* Declared in startup, used to set unused interrupts to. */ +CY_ISR_PROTO(IntDefaultHandler); + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Start +******************************************************************************** +* +* Summary: +* Set up the interrupt and enable it. This function disables the interrupt, +* sets the default interrupt vector, sets the priority from the value in the +* Design Wide Resources Interrupt Editor, then enables the interrupt to the +* interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Start(void) +{ + /* For all we know the interrupt is active. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */ + SD_TX_DMA_COMPLETE_SetVector(&SD_TX_DMA_COMPLETE_Interrupt); + + /* Set the priority. */ + SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_StartEx +******************************************************************************** +* +* Summary: +* Sets up the interrupt and enables it. This function disables the interrupt, +* sets the interrupt vector based on the address passed in, sets the priority +* from the value in the Design Wide Resources Interrupt Editor, then enables +* the interrupt to the interrupt controller. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address) +{ + /* For all we know the interrupt is active. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the SD_TX_DMA_COMPLETE Interrupt. */ + SD_TX_DMA_COMPLETE_SetVector(address); + + /* Set the priority. */ + SD_TX_DMA_COMPLETE_SetPriority((uint8)SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER); + + /* Enable it. */ + SD_TX_DMA_COMPLETE_Enable(); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Stop +******************************************************************************** +* +* Summary: +* Disables and removes the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Stop(void) +{ + /* Disable this interrupt. */ + SD_TX_DMA_COMPLETE_Disable(); + + /* Set the ISR to point to the passive one. */ + SD_TX_DMA_COMPLETE_SetVector(&IntDefaultHandler); +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Interrupt +******************************************************************************** +* +* Summary: +* The default Interrupt Service Routine for SD_TX_DMA_COMPLETE. +* +* Add custom code between the coments to keep the next version of this file +* from over writting your code. +* +* Parameters: +* +* Return: +* None +* +*******************************************************************************/ +CY_ISR(SD_TX_DMA_COMPLETE_Interrupt) +{ + #ifdef SD_TX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK + SD_TX_DMA_COMPLETE_Interrupt_InterruptCallback(); + #endif /* SD_TX_DMA_COMPLETE_INTERRUPT_INTERRUPT_CALLBACK */ + + /* Place your Interrupt code here. */ + /* `#START SD_TX_DMA_COMPLETE_Interrupt` */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetVector +******************************************************************************** +* +* Summary: +* Change the ISR vector for the Interrupt. Note calling SD_TX_DMA_COMPLETE_Start +* will override any effect this method would have had. To set the vector +* before the component has been started use SD_TX_DMA_COMPLETE_StartEx instead. +* +* When defining ISR functions, the CY_ISR and CY_ISR_PROTO macros should be +* used to provide consistent definition across compilers: +* +* Function definition example: +* CY_ISR(MyISR) +* { +* } +* +* Function prototype example: +* CY_ISR_PROTO(MyISR); +* +* Parameters: +* address: Address of the ISR to set in the interrupt vector table. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER] = address; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetVector +******************************************************************************** +* +* Summary: +* Gets the "address" of the current ISR vector for the Interrupt. +* +* Parameters: +* None +* +* Return: +* Address of the ISR in the interrupt vector table. +* +*******************************************************************************/ +cyisraddress SD_TX_DMA_COMPLETE_GetVector(void) +{ + cyisraddress * ramVectorTable; + + ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE; + + return ramVectorTable[CYINT_IRQ_BASE + (uint32)SD_TX_DMA_COMPLETE__INTC_NUMBER]; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetPriority +******************************************************************************** +* +* Summary: +* Sets the Priority of the Interrupt. +* +* Note calling SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx will +* override any effect this API would have had. This API should only be called +* after SD_TX_DMA_COMPLETE_Start or SD_TX_DMA_COMPLETE_StartEx has been called. +* To set the initial priority for the component, use the Design-Wide Resources +* Interrupt Editor. +* +* Note This API has no effect on Non-maskable interrupt NMI). +* +* Parameters: +* priority: Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority) +{ + *SD_TX_DMA_COMPLETE_INTC_PRIOR = priority << 5; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetPriority +******************************************************************************** +* +* Summary: +* Gets the Priority of the Interrupt. +* +* Parameters: +* None +* +* Return: +* Priority of the interrupt, 0 being the highest priority +* PSoC 3 and PSoC 5LP: Priority is from 0 to 7. +* PSoC 4: Priority is from 0 to 3. +* +*******************************************************************************/ +uint8 SD_TX_DMA_COMPLETE_GetPriority(void) +{ + uint8 priority; + + + priority = *SD_TX_DMA_COMPLETE_INTC_PRIOR >> 5; + + return priority; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Enable +******************************************************************************** +* +* Summary: +* Enables the interrupt to the interrupt controller. Do not call this function +* unless ISR_Start() has been called or the functionality of the ISR_Start() +* function, which sets the vector and the priority, has been called. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Enable(void) +{ + /* Enable the general interrupt. */ + *SD_TX_DMA_COMPLETE_INTC_SET_EN = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_GetState +******************************************************************************** +* +* Summary: +* Gets the state (enabled, disabled) of the Interrupt. +* +* Parameters: +* None +* +* Return: +* 1 if enabled, 0 if disabled. +* +*******************************************************************************/ +uint8 SD_TX_DMA_COMPLETE_GetState(void) +{ + /* Get the state of the general interrupt. */ + return ((*SD_TX_DMA_COMPLETE_INTC_SET_EN & (uint32)SD_TX_DMA_COMPLETE__INTC_MASK) != 0u) ? 1u:0u; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_Disable +******************************************************************************** +* +* Summary: +* Disables the Interrupt in the interrupt controller. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_Disable(void) +{ + /* Disable the general interrupt. */ + *SD_TX_DMA_COMPLETE_INTC_CLR_EN = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_SetPending +******************************************************************************** +* +* Summary: +* Causes the Interrupt to enter the pending state, a software method of +* generating the interrupt. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* If interrupts are enabled and the interrupt is set up properly, the ISR is +* entered (depending on the priority of this interrupt and other pending +* interrupts). +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_SetPending(void) +{ + *SD_TX_DMA_COMPLETE_INTC_SET_PD = SD_TX_DMA_COMPLETE__INTC_MASK; +} + + +/******************************************************************************* +* Function Name: SD_TX_DMA_COMPLETE_ClearPending +******************************************************************************** +* +* Summary: +* Clears a pending interrupt in the interrupt controller. +* +* Note Some interrupt sources are clear-on-read and require the block +* interrupt/status register to be read/cleared with the appropriate block API +* (GPIO, UART, and so on). Otherwise the ISR will continue to remain in +* pending state even though the interrupt itself is cleared using this API. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void SD_TX_DMA_COMPLETE_ClearPending(void) +{ + *SD_TX_DMA_COMPLETE_INTC_CLR_PD = SD_TX_DMA_COMPLETE__INTC_MASK; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h new file mode 100644 index 0000000..73c5ff0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_COMPLETE.h @@ -0,0 +1,70 @@ +/******************************************************************************* +* File Name: SD_TX_DMA_COMPLETE.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the Interrupt Controller. +* +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#if !defined(CY_ISR_SD_TX_DMA_COMPLETE_H) +#define CY_ISR_SD_TX_DMA_COMPLETE_H + + +#include +#include + +/* Interrupt Controller API. */ +void SD_TX_DMA_COMPLETE_Start(void); +void SD_TX_DMA_COMPLETE_StartEx(cyisraddress address); +void SD_TX_DMA_COMPLETE_Stop(void); + +CY_ISR_PROTO(SD_TX_DMA_COMPLETE_Interrupt); + +void SD_TX_DMA_COMPLETE_SetVector(cyisraddress address); +cyisraddress SD_TX_DMA_COMPLETE_GetVector(void); + +void SD_TX_DMA_COMPLETE_SetPriority(uint8 priority); +uint8 SD_TX_DMA_COMPLETE_GetPriority(void); + +void SD_TX_DMA_COMPLETE_Enable(void); +uint8 SD_TX_DMA_COMPLETE_GetState(void); +void SD_TX_DMA_COMPLETE_Disable(void); + +void SD_TX_DMA_COMPLETE_SetPending(void); +void SD_TX_DMA_COMPLETE_ClearPending(void); + + +/* Interrupt Controller Constants */ + +/* Address of the INTC.VECT[x] register that contains the Address of the SD_TX_DMA_COMPLETE ISR. */ +#define SD_TX_DMA_COMPLETE_INTC_VECTOR ((reg32 *) SD_TX_DMA_COMPLETE__INTC_VECT) + +/* Address of the SD_TX_DMA_COMPLETE ISR priority. */ +#define SD_TX_DMA_COMPLETE_INTC_PRIOR ((reg8 *) SD_TX_DMA_COMPLETE__INTC_PRIOR_REG) + +/* Priority of the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_PRIOR_NUMBER SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM + +/* Address of the INTC.SET_EN[x] byte to bit enable SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_SET_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_EN_REG) + +/* Address of the INTC.CLR_EN[x] register to bit clear the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_CLR_EN ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG) + +/* Address of the INTC.SET_PD[x] register to set the SD_TX_DMA_COMPLETE interrupt state to pending. */ +#define SD_TX_DMA_COMPLETE_INTC_SET_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_SET_PD_REG) + +/* Address of the INTC.CLR_PD[x] register to clear the SD_TX_DMA_COMPLETE interrupt. */ +#define SD_TX_DMA_COMPLETE_INTC_CLR_PD ((reg32 *) SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG) + + +#endif /* CY_ISR_SD_TX_DMA_COMPLETE_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c new file mode 100644 index 0000000..4f605c2 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.c @@ -0,0 +1,141 @@ +/*************************************************************************** +* File Name: SD_TX_DMA_dma.c +* Version 1.70 +* +* Description: +* Provides an API for the DMAC component. The API includes functions +* for the DMA controller, DMA channels and Transfer Descriptors. +* +* +* Note: +* This module requires the developer to finish or fill in the auto +* generated funcions and setup the dma channel and TD's. +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#include +#include +#include + + + +/**************************************************************************** +* +* The following defines are available in Cyfitter.h +* +* +* +* SD_TX_DMA__DRQ_CTL_REG +* +* +* SD_TX_DMA__DRQ_NUMBER +* +* Number of TD's used by this channel. +* SD_TX_DMA__NUMBEROF_TDS +* +* Priority of this channel. +* SD_TX_DMA__PRIORITY +* +* True if SD_TX_DMA_TERMIN_SEL is used. +* SD_TX_DMA__TERMIN_EN +* +* TERMIN interrupt line to signal terminate. +* SD_TX_DMA__TERMIN_SEL +* +* +* True if SD_TX_DMA_TERMOUT0_SEL is used. +* SD_TX_DMA__TERMOUT0_EN +* +* +* TERMOUT0 interrupt line to signal completion. +* SD_TX_DMA__TERMOUT0_SEL +* +* +* True if SD_TX_DMA_TERMOUT1_SEL is used. +* SD_TX_DMA__TERMOUT1_EN +* +* +* TERMOUT1 interrupt line to signal completion. +* SD_TX_DMA__TERMOUT1_SEL +* +****************************************************************************/ + + +/* Zero based index of SD_TX_DMA dma channel */ +uint8 SD_TX_DMA_DmaHandle = DMA_INVALID_CHANNEL; + +/********************************************************************* +* Function Name: uint8 SD_TX_DMA_DmaInitalize +********************************************************************** +* Summary: +* Allocates and initialises a channel of the DMAC to be used by the +* caller. +* +* Parameters: +* BurstCount. +* +* +* ReqestPerBurst. +* +* +* UpperSrcAddress. +* +* +* UpperDestAddress. +* +* +* Return: +* The channel that can be used by the caller for DMA activity. +* DMA_INVALID_CHANNEL (0xFF) if there are no channels left. +* +* +*******************************************************************/ +uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) +{ + + /* Allocate a DMA channel. */ + SD_TX_DMA_DmaHandle = (uint8)SD_TX_DMA__DRQ_NUMBER; + + /* Configure the channel. */ + (void)CyDmaChSetConfiguration(SD_TX_DMA_DmaHandle, + BurstCount, + ReqestPerBurst, + (uint8)SD_TX_DMA__TERMOUT0_SEL, + (uint8)SD_TX_DMA__TERMOUT1_SEL, + (uint8)SD_TX_DMA__TERMIN_SEL); + + /* Set the extended address for the transfers */ + (void)CyDmaChSetExtendedAddress(SD_TX_DMA_DmaHandle, UpperSrcAddress, UpperDestAddress); + + /* Set the priority for this channel */ + (void)CyDmaChPriority(SD_TX_DMA_DmaHandle, (uint8)SD_TX_DMA__PRIORITY); + + return SD_TX_DMA_DmaHandle; +} + +/********************************************************************* +* Function Name: void SD_TX_DMA_DmaRelease +********************************************************************** +* Summary: +* Frees the channel associated with SD_TX_DMA. +* +* +* Parameters: +* void. +* +* +* +* Return: +* void. +* +*******************************************************************/ +void SD_TX_DMA_DmaRelease(void) +{ + /* Disable the channel */ + (void)CyDmaChDisable(SD_TX_DMA_DmaHandle); +} + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h new file mode 100644 index 0000000..64a7645 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_TX_DMA_dma.h @@ -0,0 +1,35 @@ +/****************************************************************************** +* File Name: SD_TX_DMA_dma.h +* Version 1.70 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* +******************************************************************************** +* Copyright 2008-2010, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ +#if !defined(CY_DMA_SD_TX_DMA_DMA_H__) +#define CY_DMA_SD_TX_DMA_DMA_H__ + + + +#include +#include + +#define SD_TX_DMA__TD_TERMOUT_EN (((0 != SD_TX_DMA__TERMOUT0_EN) ? TD_TERMOUT0_EN : 0) | \ + (SD_TX_DMA__TERMOUT1_EN ? TD_TERMOUT1_EN : 0)) + +/* Zero based index of SD_TX_DMA dma channel */ +extern uint8 SD_TX_DMA_DmaHandle; + + +uint8 SD_TX_DMA_DmaInitialize(uint8 BurstCount, uint8 ReqestPerBurst, uint16 UpperSrcAddress, uint16 UpperDestAddress) ; +void SD_TX_DMA_DmaRelease(void) ; + + +/* CY_DMA_SD_TX_DMA_DMA_H__ */ +#endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.c new file mode 100644 index 0000000..05387be --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.c @@ -0,0 +1,241 @@ +/******************************************************************************* +* File Name: SPI_Pullups.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_Pullups.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SPI_Pullups__PORT == 15 && ((SPI_Pullups__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SPI_Pullups_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_Write +*******************************************************************************/ +void SPI_Pullups_Write(uint8 value) +{ + uint8 staticBits = (SPI_Pullups_DR & (uint8)(~SPI_Pullups_MASK)); + SPI_Pullups_DR = staticBits | ((uint8)(value << SPI_Pullups_SHIFT) & SPI_Pullups_MASK); +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_SetDriveMode +*******************************************************************************/ +void SPI_Pullups_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SPI_Pullups_0, mode); + CyPins_SetPinDriveMode(SPI_Pullups_1, mode); + CyPins_SetPinDriveMode(SPI_Pullups_2, mode); + CyPins_SetPinDriveMode(SPI_Pullups_3, mode); +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_Read +*******************************************************************************/ +uint8 SPI_Pullups_Read(void) +{ + return (SPI_Pullups_PS & SPI_Pullups_MASK) >> SPI_Pullups_SHIFT; +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_Pullups_Read() API because the +* SPI_Pullups_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_ReadDataReg +*******************************************************************************/ +uint8 SPI_Pullups_ReadDataReg(void) +{ + return (SPI_Pullups_DR & SPI_Pullups_MASK) >> SPI_Pullups_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SPI_Pullups_INTSTAT) + + /******************************************************************************* + * Function Name: SPI_Pullups_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SPI_Pullups_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SPI_Pullups_0_INTR (First pin in the list) + * - SPI_Pullups_1_INTR (Second pin in the list) + * - ... + * - SPI_Pullups_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_SetInterruptMode + *******************************************************************************/ + void SPI_Pullups_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SPI_Pullups_0_INTR) != 0u) + { + SPI_Pullups_0_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_Pullups_1_INTR) != 0u) + { + SPI_Pullups_1_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_Pullups_2_INTR) != 0u) + { + SPI_Pullups_2_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_Pullups_3_INTR) != 0u) + { + SPI_Pullups_3_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SPI_Pullups_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SPI_Pullups_SUT.c usage_SPI_Pullups_ClearInterrupt + *******************************************************************************/ + uint8 SPI_Pullups_ClearInterrupt(void) + { + return (SPI_Pullups_INTSTAT & SPI_Pullups_MASK) >> SPI_Pullups_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.h new file mode 100644 index 0000000..31f5c2f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups.h @@ -0,0 +1,168 @@ +/******************************************************************************* +* File Name: SPI_Pullups.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_Pullups_H) /* Pins SPI_Pullups_H */ +#define CY_PINS_SPI_Pullups_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SPI_Pullups_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SPI_Pullups__PORT == 15 && ((SPI_Pullups__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SPI_Pullups_Write(uint8 value); +void SPI_Pullups_SetDriveMode(uint8 mode); +uint8 SPI_Pullups_ReadDataReg(void); +uint8 SPI_Pullups_Read(void); +void SPI_Pullups_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_Pullups_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_Pullups_SetDriveMode() function. + * @{ + */ + #define SPI_Pullups_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SPI_Pullups_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SPI_Pullups_DM_RES_UP PIN_DM_RES_UP + #define SPI_Pullups_DM_RES_DWN PIN_DM_RES_DWN + #define SPI_Pullups_DM_OD_LO PIN_DM_OD_LO + #define SPI_Pullups_DM_OD_HI PIN_DM_OD_HI + #define SPI_Pullups_DM_STRONG PIN_DM_STRONG + #define SPI_Pullups_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SPI_Pullups_MASK SPI_Pullups__MASK +#define SPI_Pullups_SHIFT SPI_Pullups__SHIFT +#define SPI_Pullups_WIDTH 4u + +/* Interrupt constants */ +#if defined(SPI_Pullups__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_Pullups_SetInterruptMode() function. + * @{ + */ + #define SPI_Pullups_INTR_NONE (uint16)(0x0000u) + #define SPI_Pullups_INTR_RISING (uint16)(0x0001u) + #define SPI_Pullups_INTR_FALLING (uint16)(0x0002u) + #define SPI_Pullups_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SPI_Pullups_INTR_MASK (0x01u) +#endif /* (SPI_Pullups__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SPI_Pullups_PS (* (reg8 *) SPI_Pullups__PS) +/* Data Register */ +#define SPI_Pullups_DR (* (reg8 *) SPI_Pullups__DR) +/* Port Number */ +#define SPI_Pullups_PRT_NUM (* (reg8 *) SPI_Pullups__PRT) +/* Connect to Analog Globals */ +#define SPI_Pullups_AG (* (reg8 *) SPI_Pullups__AG) +/* Analog MUX bux enable */ +#define SPI_Pullups_AMUX (* (reg8 *) SPI_Pullups__AMUX) +/* Bidirectional Enable */ +#define SPI_Pullups_BIE (* (reg8 *) SPI_Pullups__BIE) +/* Bit-mask for Aliased Register Access */ +#define SPI_Pullups_BIT_MASK (* (reg8 *) SPI_Pullups__BIT_MASK) +/* Bypass Enable */ +#define SPI_Pullups_BYP (* (reg8 *) SPI_Pullups__BYP) +/* Port wide control signals */ +#define SPI_Pullups_CTL (* (reg8 *) SPI_Pullups__CTL) +/* Drive Modes */ +#define SPI_Pullups_DM0 (* (reg8 *) SPI_Pullups__DM0) +#define SPI_Pullups_DM1 (* (reg8 *) SPI_Pullups__DM1) +#define SPI_Pullups_DM2 (* (reg8 *) SPI_Pullups__DM2) +/* Input Buffer Disable Override */ +#define SPI_Pullups_INP_DIS (* (reg8 *) SPI_Pullups__INP_DIS) +/* LCD Common or Segment Drive */ +#define SPI_Pullups_LCD_COM_SEG (* (reg8 *) SPI_Pullups__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SPI_Pullups_LCD_EN (* (reg8 *) SPI_Pullups__LCD_EN) +/* Slew Rate Control */ +#define SPI_Pullups_SLW (* (reg8 *) SPI_Pullups__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SPI_Pullups_PRTDSI__CAPS_SEL (* (reg8 *) SPI_Pullups__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SPI_Pullups_PRTDSI__DBL_SYNC_IN (* (reg8 *) SPI_Pullups__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SPI_Pullups_PRTDSI__OE_SEL0 (* (reg8 *) SPI_Pullups__PRTDSI__OE_SEL0) +#define SPI_Pullups_PRTDSI__OE_SEL1 (* (reg8 *) SPI_Pullups__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SPI_Pullups_PRTDSI__OUT_SEL0 (* (reg8 *) SPI_Pullups__PRTDSI__OUT_SEL0) +#define SPI_Pullups_PRTDSI__OUT_SEL1 (* (reg8 *) SPI_Pullups__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SPI_Pullups_PRTDSI__SYNC_OUT (* (reg8 *) SPI_Pullups__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SPI_Pullups__SIO_CFG) + #define SPI_Pullups_SIO_HYST_EN (* (reg8 *) SPI_Pullups__SIO_HYST_EN) + #define SPI_Pullups_SIO_REG_HIFREQ (* (reg8 *) SPI_Pullups__SIO_REG_HIFREQ) + #define SPI_Pullups_SIO_CFG (* (reg8 *) SPI_Pullups__SIO_CFG) + #define SPI_Pullups_SIO_DIFF (* (reg8 *) SPI_Pullups__SIO_DIFF) +#endif /* (SPI_Pullups__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SPI_Pullups__INTSTAT) + #define SPI_Pullups_INTSTAT (* (reg8 *) SPI_Pullups__INTSTAT) + #define SPI_Pullups_SNAP (* (reg8 *) SPI_Pullups__SNAP) + + #define SPI_Pullups_0_INTTYPE_REG (* (reg8 *) SPI_Pullups__0__INTTYPE) + #define SPI_Pullups_1_INTTYPE_REG (* (reg8 *) SPI_Pullups__1__INTTYPE) + #define SPI_Pullups_2_INTTYPE_REG (* (reg8 *) SPI_Pullups__2__INTTYPE) + #define SPI_Pullups_3_INTTYPE_REG (* (reg8 *) SPI_Pullups__3__INTTYPE) +#endif /* (SPI_Pullups__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SPI_Pullups_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.c new file mode 100644 index 0000000..6d7705c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.c @@ -0,0 +1,231 @@ +/******************************************************************************* +* File Name: SPI_Pullups_1.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_Pullups_1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SPI_Pullups_1__PORT == 15 && ((SPI_Pullups_1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SPI_Pullups_1_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_Write +*******************************************************************************/ +void SPI_Pullups_1_Write(uint8 value) +{ + uint8 staticBits = (SPI_Pullups_1_DR & (uint8)(~SPI_Pullups_1_MASK)); + SPI_Pullups_1_DR = staticBits | ((uint8)(value << SPI_Pullups_1_SHIFT) & SPI_Pullups_1_MASK); +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_1_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_SetDriveMode +*******************************************************************************/ +void SPI_Pullups_1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SPI_Pullups_1_0, mode); + CyPins_SetPinDriveMode(SPI_Pullups_1_1, mode); +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_1_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_Read +*******************************************************************************/ +uint8 SPI_Pullups_1_Read(void) +{ + return (SPI_Pullups_1_PS & SPI_Pullups_1_MASK) >> SPI_Pullups_1_SHIFT; +} + + +/******************************************************************************* +* Function Name: SPI_Pullups_1_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred SPI_Pullups_1_Read() API because the +* SPI_Pullups_1_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_ReadDataReg +*******************************************************************************/ +uint8 SPI_Pullups_1_ReadDataReg(void) +{ + return (SPI_Pullups_1_DR & SPI_Pullups_1_MASK) >> SPI_Pullups_1_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(SPI_Pullups_1_INTSTAT) + + /******************************************************************************* + * Function Name: SPI_Pullups_1_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use SPI_Pullups_1_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - SPI_Pullups_1_0_INTR (First pin in the list) + * - SPI_Pullups_1_1_INTR (Second pin in the list) + * - ... + * - SPI_Pullups_1_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_SetInterruptMode + *******************************************************************************/ + void SPI_Pullups_1_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & SPI_Pullups_1_0_INTR) != 0u) + { + SPI_Pullups_1_0_INTTYPE_REG = (uint8)mode; + } + if((position & SPI_Pullups_1_1_INTR) != 0u) + { + SPI_Pullups_1_1_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: SPI_Pullups_1_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet SPI_Pullups_1_SUT.c usage_SPI_Pullups_1_ClearInterrupt + *******************************************************************************/ + uint8 SPI_Pullups_1_ClearInterrupt(void) + { + return (SPI_Pullups_1_INTSTAT & SPI_Pullups_1_MASK) >> SPI_Pullups_1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.h new file mode 100644 index 0000000..29d28a4 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1.h @@ -0,0 +1,166 @@ +/******************************************************************************* +* File Name: SPI_Pullups_1.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_Pullups_1_H) /* Pins SPI_Pullups_1_H */ +#define CY_PINS_SPI_Pullups_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SPI_Pullups_1_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SPI_Pullups_1__PORT == 15 && ((SPI_Pullups_1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void SPI_Pullups_1_Write(uint8 value); +void SPI_Pullups_1_SetDriveMode(uint8 mode); +uint8 SPI_Pullups_1_ReadDataReg(void); +uint8 SPI_Pullups_1_Read(void); +void SPI_Pullups_1_SetInterruptMode(uint16 position, uint16 mode); +uint8 SPI_Pullups_1_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the SPI_Pullups_1_SetDriveMode() function. + * @{ + */ + #define SPI_Pullups_1_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define SPI_Pullups_1_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define SPI_Pullups_1_DM_RES_UP PIN_DM_RES_UP + #define SPI_Pullups_1_DM_RES_DWN PIN_DM_RES_DWN + #define SPI_Pullups_1_DM_OD_LO PIN_DM_OD_LO + #define SPI_Pullups_1_DM_OD_HI PIN_DM_OD_HI + #define SPI_Pullups_1_DM_STRONG PIN_DM_STRONG + #define SPI_Pullups_1_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define SPI_Pullups_1_MASK SPI_Pullups_1__MASK +#define SPI_Pullups_1_SHIFT SPI_Pullups_1__SHIFT +#define SPI_Pullups_1_WIDTH 2u + +/* Interrupt constants */ +#if defined(SPI_Pullups_1__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in SPI_Pullups_1_SetInterruptMode() function. + * @{ + */ + #define SPI_Pullups_1_INTR_NONE (uint16)(0x0000u) + #define SPI_Pullups_1_INTR_RISING (uint16)(0x0001u) + #define SPI_Pullups_1_INTR_FALLING (uint16)(0x0002u) + #define SPI_Pullups_1_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define SPI_Pullups_1_INTR_MASK (0x01u) +#endif /* (SPI_Pullups_1__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SPI_Pullups_1_PS (* (reg8 *) SPI_Pullups_1__PS) +/* Data Register */ +#define SPI_Pullups_1_DR (* (reg8 *) SPI_Pullups_1__DR) +/* Port Number */ +#define SPI_Pullups_1_PRT_NUM (* (reg8 *) SPI_Pullups_1__PRT) +/* Connect to Analog Globals */ +#define SPI_Pullups_1_AG (* (reg8 *) SPI_Pullups_1__AG) +/* Analog MUX bux enable */ +#define SPI_Pullups_1_AMUX (* (reg8 *) SPI_Pullups_1__AMUX) +/* Bidirectional Enable */ +#define SPI_Pullups_1_BIE (* (reg8 *) SPI_Pullups_1__BIE) +/* Bit-mask for Aliased Register Access */ +#define SPI_Pullups_1_BIT_MASK (* (reg8 *) SPI_Pullups_1__BIT_MASK) +/* Bypass Enable */ +#define SPI_Pullups_1_BYP (* (reg8 *) SPI_Pullups_1__BYP) +/* Port wide control signals */ +#define SPI_Pullups_1_CTL (* (reg8 *) SPI_Pullups_1__CTL) +/* Drive Modes */ +#define SPI_Pullups_1_DM0 (* (reg8 *) SPI_Pullups_1__DM0) +#define SPI_Pullups_1_DM1 (* (reg8 *) SPI_Pullups_1__DM1) +#define SPI_Pullups_1_DM2 (* (reg8 *) SPI_Pullups_1__DM2) +/* Input Buffer Disable Override */ +#define SPI_Pullups_1_INP_DIS (* (reg8 *) SPI_Pullups_1__INP_DIS) +/* LCD Common or Segment Drive */ +#define SPI_Pullups_1_LCD_COM_SEG (* (reg8 *) SPI_Pullups_1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SPI_Pullups_1_LCD_EN (* (reg8 *) SPI_Pullups_1__LCD_EN) +/* Slew Rate Control */ +#define SPI_Pullups_1_SLW (* (reg8 *) SPI_Pullups_1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SPI_Pullups_1_PRTDSI__CAPS_SEL (* (reg8 *) SPI_Pullups_1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SPI_Pullups_1_PRTDSI__DBL_SYNC_IN (* (reg8 *) SPI_Pullups_1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SPI_Pullups_1_PRTDSI__OE_SEL0 (* (reg8 *) SPI_Pullups_1__PRTDSI__OE_SEL0) +#define SPI_Pullups_1_PRTDSI__OE_SEL1 (* (reg8 *) SPI_Pullups_1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SPI_Pullups_1_PRTDSI__OUT_SEL0 (* (reg8 *) SPI_Pullups_1__PRTDSI__OUT_SEL0) +#define SPI_Pullups_1_PRTDSI__OUT_SEL1 (* (reg8 *) SPI_Pullups_1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SPI_Pullups_1_PRTDSI__SYNC_OUT (* (reg8 *) SPI_Pullups_1__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(SPI_Pullups_1__SIO_CFG) + #define SPI_Pullups_1_SIO_HYST_EN (* (reg8 *) SPI_Pullups_1__SIO_HYST_EN) + #define SPI_Pullups_1_SIO_REG_HIFREQ (* (reg8 *) SPI_Pullups_1__SIO_REG_HIFREQ) + #define SPI_Pullups_1_SIO_CFG (* (reg8 *) SPI_Pullups_1__SIO_CFG) + #define SPI_Pullups_1_SIO_DIFF (* (reg8 *) SPI_Pullups_1__SIO_DIFF) +#endif /* (SPI_Pullups_1__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(SPI_Pullups_1__INTSTAT) + #define SPI_Pullups_1_INTSTAT (* (reg8 *) SPI_Pullups_1__INTSTAT) + #define SPI_Pullups_1_SNAP (* (reg8 *) SPI_Pullups_1__SNAP) + + #define SPI_Pullups_1_0_INTTYPE_REG (* (reg8 *) SPI_Pullups_1__0__INTTYPE) + #define SPI_Pullups_1_1_INTTYPE_REG (* (reg8 *) SPI_Pullups_1__1__INTTYPE) +#endif /* (SPI_Pullups_1__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SPI_Pullups_1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1_aliases.h new file mode 100644 index 0000000..38ceb99 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_1_aliases.h @@ -0,0 +1,39 @@ +/******************************************************************************* +* File Name: SPI_Pullups_1.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_Pullups_1_ALIASES_H) /* Pins SPI_Pullups_1_ALIASES_H */ +#define CY_PINS_SPI_Pullups_1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SPI_Pullups_1_0 (SPI_Pullups_1__0__PC) +#define SPI_Pullups_1_0_INTR ((uint16)((uint16)0x0001u << SPI_Pullups_1__0__SHIFT)) + +#define SPI_Pullups_1_1 (SPI_Pullups_1__1__PC) +#define SPI_Pullups_1_1_INTR ((uint16)((uint16)0x0001u << SPI_Pullups_1__1__SHIFT)) + +#define SPI_Pullups_1_INTR_ALL ((uint16)(SPI_Pullups_1_0_INTR| SPI_Pullups_1_1_INTR)) + +#endif /* End Pins SPI_Pullups_1_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_aliases.h new file mode 100644 index 0000000..241fd07 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/SPI_Pullups_aliases.h @@ -0,0 +1,45 @@ +/******************************************************************************* +* File Name: SPI_Pullups.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_Pullups_ALIASES_H) /* Pins SPI_Pullups_ALIASES_H */ +#define CY_PINS_SPI_Pullups_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define SPI_Pullups_0 (SPI_Pullups__0__PC) +#define SPI_Pullups_0_INTR ((uint16)((uint16)0x0001u << SPI_Pullups__0__SHIFT)) + +#define SPI_Pullups_1 (SPI_Pullups__1__PC) +#define SPI_Pullups_1_INTR ((uint16)((uint16)0x0001u << SPI_Pullups__1__SHIFT)) + +#define SPI_Pullups_2 (SPI_Pullups__2__PC) +#define SPI_Pullups_2_INTR ((uint16)((uint16)0x0001u << SPI_Pullups__2__SHIFT)) + +#define SPI_Pullups_3 (SPI_Pullups__3__PC) +#define SPI_Pullups_3_INTR ((uint16)((uint16)0x0001u << SPI_Pullups__3__SHIFT)) + +#define SPI_Pullups_INTR_ALL ((uint16)(SPI_Pullups_0_INTR| SPI_Pullups_1_INTR| SPI_Pullups_2_INTR| SPI_Pullups_3_INTR)) + +#endif /* End Pins SPI_Pullups_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.c new file mode 100644 index 0000000..7f78738 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: TERM_EN.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "TERM_EN.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + TERM_EN__PORT == 15 && ((TERM_EN__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: TERM_EN_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_Write +*******************************************************************************/ +void TERM_EN_Write(uint8 value) +{ + uint8 staticBits = (TERM_EN_DR & (uint8)(~TERM_EN_MASK)); + TERM_EN_DR = staticBits | ((uint8)(value << TERM_EN_SHIFT) & TERM_EN_MASK); +} + + +/******************************************************************************* +* Function Name: TERM_EN_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_SetDriveMode +*******************************************************************************/ +void TERM_EN_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(TERM_EN_0, mode); +} + + +/******************************************************************************* +* Function Name: TERM_EN_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_Read +*******************************************************************************/ +uint8 TERM_EN_Read(void) +{ + return (TERM_EN_PS & TERM_EN_MASK) >> TERM_EN_SHIFT; +} + + +/******************************************************************************* +* Function Name: TERM_EN_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred TERM_EN_Read() API because the +* TERM_EN_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_ReadDataReg +*******************************************************************************/ +uint8 TERM_EN_ReadDataReg(void) +{ + return (TERM_EN_DR & TERM_EN_MASK) >> TERM_EN_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(TERM_EN_INTSTAT) + + /******************************************************************************* + * Function Name: TERM_EN_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use TERM_EN_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - TERM_EN_0_INTR (First pin in the list) + * - TERM_EN_1_INTR (Second pin in the list) + * - ... + * - TERM_EN_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet TERM_EN_SUT.c usage_TERM_EN_SetInterruptMode + *******************************************************************************/ + void TERM_EN_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & TERM_EN_0_INTR) != 0u) + { + TERM_EN_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: TERM_EN_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet TERM_EN_SUT.c usage_TERM_EN_ClearInterrupt + *******************************************************************************/ + uint8 TERM_EN_ClearInterrupt(void) + { + return (TERM_EN_INTSTAT & TERM_EN_MASK) >> TERM_EN_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.h new file mode 100644 index 0000000..bf5d366 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: TERM_EN.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_TERM_EN_H) /* Pins TERM_EN_H */ +#define CY_PINS_TERM_EN_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "TERM_EN_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + TERM_EN__PORT == 15 && ((TERM_EN__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void TERM_EN_Write(uint8 value); +void TERM_EN_SetDriveMode(uint8 mode); +uint8 TERM_EN_ReadDataReg(void); +uint8 TERM_EN_Read(void); +void TERM_EN_SetInterruptMode(uint16 position, uint16 mode); +uint8 TERM_EN_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the TERM_EN_SetDriveMode() function. + * @{ + */ + #define TERM_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define TERM_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define TERM_EN_DM_RES_UP PIN_DM_RES_UP + #define TERM_EN_DM_RES_DWN PIN_DM_RES_DWN + #define TERM_EN_DM_OD_LO PIN_DM_OD_LO + #define TERM_EN_DM_OD_HI PIN_DM_OD_HI + #define TERM_EN_DM_STRONG PIN_DM_STRONG + #define TERM_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define TERM_EN_MASK TERM_EN__MASK +#define TERM_EN_SHIFT TERM_EN__SHIFT +#define TERM_EN_WIDTH 1u + +/* Interrupt constants */ +#if defined(TERM_EN__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in TERM_EN_SetInterruptMode() function. + * @{ + */ + #define TERM_EN_INTR_NONE (uint16)(0x0000u) + #define TERM_EN_INTR_RISING (uint16)(0x0001u) + #define TERM_EN_INTR_FALLING (uint16)(0x0002u) + #define TERM_EN_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define TERM_EN_INTR_MASK (0x01u) +#endif /* (TERM_EN__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define TERM_EN_PS (* (reg8 *) TERM_EN__PS) +/* Data Register */ +#define TERM_EN_DR (* (reg8 *) TERM_EN__DR) +/* Port Number */ +#define TERM_EN_PRT_NUM (* (reg8 *) TERM_EN__PRT) +/* Connect to Analog Globals */ +#define TERM_EN_AG (* (reg8 *) TERM_EN__AG) +/* Analog MUX bux enable */ +#define TERM_EN_AMUX (* (reg8 *) TERM_EN__AMUX) +/* Bidirectional Enable */ +#define TERM_EN_BIE (* (reg8 *) TERM_EN__BIE) +/* Bit-mask for Aliased Register Access */ +#define TERM_EN_BIT_MASK (* (reg8 *) TERM_EN__BIT_MASK) +/* Bypass Enable */ +#define TERM_EN_BYP (* (reg8 *) TERM_EN__BYP) +/* Port wide control signals */ +#define TERM_EN_CTL (* (reg8 *) TERM_EN__CTL) +/* Drive Modes */ +#define TERM_EN_DM0 (* (reg8 *) TERM_EN__DM0) +#define TERM_EN_DM1 (* (reg8 *) TERM_EN__DM1) +#define TERM_EN_DM2 (* (reg8 *) TERM_EN__DM2) +/* Input Buffer Disable Override */ +#define TERM_EN_INP_DIS (* (reg8 *) TERM_EN__INP_DIS) +/* LCD Common or Segment Drive */ +#define TERM_EN_LCD_COM_SEG (* (reg8 *) TERM_EN__LCD_COM_SEG) +/* Enable Segment LCD */ +#define TERM_EN_LCD_EN (* (reg8 *) TERM_EN__LCD_EN) +/* Slew Rate Control */ +#define TERM_EN_SLW (* (reg8 *) TERM_EN__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define TERM_EN_PRTDSI__CAPS_SEL (* (reg8 *) TERM_EN__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define TERM_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) TERM_EN__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define TERM_EN_PRTDSI__OE_SEL0 (* (reg8 *) TERM_EN__PRTDSI__OE_SEL0) +#define TERM_EN_PRTDSI__OE_SEL1 (* (reg8 *) TERM_EN__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define TERM_EN_PRTDSI__OUT_SEL0 (* (reg8 *) TERM_EN__PRTDSI__OUT_SEL0) +#define TERM_EN_PRTDSI__OUT_SEL1 (* (reg8 *) TERM_EN__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define TERM_EN_PRTDSI__SYNC_OUT (* (reg8 *) TERM_EN__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(TERM_EN__SIO_CFG) + #define TERM_EN_SIO_HYST_EN (* (reg8 *) TERM_EN__SIO_HYST_EN) + #define TERM_EN_SIO_REG_HIFREQ (* (reg8 *) TERM_EN__SIO_REG_HIFREQ) + #define TERM_EN_SIO_CFG (* (reg8 *) TERM_EN__SIO_CFG) + #define TERM_EN_SIO_DIFF (* (reg8 *) TERM_EN__SIO_DIFF) +#endif /* (TERM_EN__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(TERM_EN__INTSTAT) + #define TERM_EN_INTSTAT (* (reg8 *) TERM_EN__INTSTAT) + #define TERM_EN_SNAP (* (reg8 *) TERM_EN__SNAP) + + #define TERM_EN_0_INTTYPE_REG (* (reg8 *) TERM_EN__0__INTTYPE) +#endif /* (TERM_EN__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_TERM_EN_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h new file mode 100644 index 0000000..95659ca --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: TERM_EN.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_TERM_EN_ALIASES_H) /* Pins TERM_EN_ALIASES_H */ +#define CY_PINS_TERM_EN_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define TERM_EN_0 (TERM_EN__0__PC) +#define TERM_EN_0_INTR ((uint16)((uint16)0x0001u << TERM_EN__0__SHIFT)) + +#define TERM_EN_INTR_ALL ((uint16)(TERM_EN_0_INTR)) + +#endif /* End Pins TERM_EN_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c new file mode 100644 index 0000000..5d2b7c7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.c @@ -0,0 +1,2820 @@ +/***************************************************************************//** +* \file USBFS.c +* \version 3.10 +* +* \brief +* This file contains the global USBFS API functions. +* +* Note: +* Many of the functions use an endpoint number. SRAM arrays are sized with 9 +* elements, so they are indexed directly by epNumber. The SIE and ARB +* registers are indexed by variations of epNumber - 1. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_cydmac.h" +#include "USBFS_hid.h" +#include "USBFS_Dp.h" + + +/*************************************** +* Global data allocation +***************************************/ + +/** Indicates whether the USBFS has been initialized. The variable is +* initialized to 0 after device reset and set to 1 the first time USBFS_Start() +* is called. This allows the Component to restart without reinitialization after +* the first call to the USBFS_Start() routine. +* If re-initialization of the Component is required, the variable should be set +* to 0 before the USBFS_Start() routine is called. Alternatively, the USBFS can +* be reinitialized by calling both USBFS_Init() and USBFS_InitComponent() +* functions. +*/ +uint8 USBFS_initVar = 0u; + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + static void USBFS_InitEpDma(void); + + /* DMA chanels assigend for endpoints. */ + const uint8 USBFS_DmaChan[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + #else + /* DMA chanels assigend for endpoints. */ + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + + /* DMA TDs require for PSoC 3/5LP operation. */ + uint8 USBFS_DmaTd[USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + /* Number of DMA bursts. */ + uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + + /* Number of bytes to transfer in last DMA burst. */ + uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + /* Storage for arrays above. */ + uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + /* DMA trigger mux output for usb.dma_req[0-7]. */ + const uint8 USBFS_DmaReqOut[USBFS_MAX_EP] = + { + 0u, + USBFS_ep1_dma__TR_OUTPUT, + USBFS_ep2_dma__TR_OUTPUT, + USBFS_ep3_dma__TR_OUTPUT, + USBFS_ep4_dma__TR_OUTPUT, + 0u, + 0u, + 0u, + 0u, + }; + + /* DMA trigger mux output for usb.dma_burstend[0-7]. */ + const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP] = + { + 0u, + USBFS_BURSTEND_0_TR_OUTPUT, + USBFS_BURSTEND_1_TR_OUTPUT, + USBFS_BURSTEND_2_TR_OUTPUT, + USBFS_BURSTEND_3_TR_OUTPUT, + USBFS_BURSTEND_4_TR_OUTPUT, + USBFS_BURSTEND_5_TR_OUTPUT, + USBFS_BURSTEND_6_TR_OUTPUT, + USBFS_BURSTEND_7_TR_OUTPUT + }; + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT; + uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] = + { + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + 0u, + }; + + volatile uint16 USBFS_inLength[USBFS_MAX_EP]; + const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +/******************************************************************************* +* Function Name: USBFS_Start +****************************************************************************//** +* +* This function performs all required initialization for the USBFS component. +* After this function call, the USB device initiates communication with the +* host by pull-up D+ line. This is the preferred method to begin component +* operation. +* +* Note that global interrupts have to be enabled because interrupts are +* required for USBFS component operation. +* +* PSoC 4200L devices: when USBFS component configured to DMA with Automatic +* Buffer Management, the DMA interrupt priority is changed to the highest +* (priority 0) inside this function. +* +* PSoC 3/PSoC 5LP devices: when USBFS component configured to DMA with +* Automatic Buffer Management, the Arbiter interrupt priority is changed to +* the highest (priority 0) inside this function. +* +* \param device +* Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. +* +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up +* +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up +* +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered.* +* \globalvars +* \ref USBFS_initVar +* +* \sideeffect +* This function will reset all communication states to default. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Start(uint8 device, uint8 mode) +{ + if (0u == USBFS_initVar) + { + USBFS_Init(); + USBFS_initVar = 1u; + } + + USBFS_InitComponent(device, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Init +****************************************************************************//** +* +* This function initializes or restores the component according to the +* customizer Configure dialog settings. It is not necessary to call +* USBFS_Init() because the USBFS_Start() routine calls +* this function and is the preferred method to begin component operation. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Init(void) +{ +#if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; + + /* The internal regulator (CR1.REG_ENABLE) is enabled in + * USBFS_InitComponent() if it is required. + */ + + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Set number of LF CLK to detect UBS bus reset. */ + USBFS_BUS_RST_CNT_REG = USBFS_DEFUALT_BUS_RST_CNT; + + /* Select VBUS detection source and clear PHY isolate. The application level + * must ensure that VBUS is valid. There is no need to wait 2us before VBUS is valid. + */ + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS; + + /* Enable PHY detector and single-ended and differential receivers. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Sets IMO lock options and clear all other bits. */ + USBFS_CR1_REG = USBFS_DEFUALT_CR1; + + /* Configure level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Configure interrupt sources from: SOF, Bus Reset and EP0. */ + USBFS_INTR_SIE_MASK_REG = USBFS_DEFAULT_INTR_SIE_MASK; + +#else + uint8 enableInterrupts = CyEnterCriticalSection(); + +#if (USBFS_EP_MANAGEMENT_DMA) + uint16 i; +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Enable USB block. */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode. */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; + + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE. */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Disable USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted. + * high. These bits will be set low by the power manager out-of-reset. + * Also confirm USBIO pull-up is disabled. + */ + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Select IOMODE to USB mode. */ + USBFS_USBIO_CR1_REG &= (uint8) ~USBFS_USBIO_CR1_IOMODE; + + /* Enable USBIO reference by setting PM.USB_CR0.fsusbio_ref_en. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* Reference is available for 1us after regulator is enabled. */ + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); + /* OR 40us after power is restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Ensure single-ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= (uint8) ~USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG &= (uint8) ~USBFS_DP_MASK; + + /* Enable USBIO. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set USBIO pull-up enable. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Reset Arbiter Write Address register for endpoint 1. */ + CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); + CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); + +#if (USBFS_EP_MANAGEMENT_DMA) + /* Initialize transfer descriptor. This will be used to detect DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; ++i) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + CyExitCriticalSection(enableInterrupts); +#endif /* (CY_PSOC4) */ + + /* Configure interrupts from USB block. */ +#if (CY_PSOC4) + /* Configure hi_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_HI_VECT_NUM, USBFS_INTR_HI_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_HI_VECT_NUM, &USBFS_INTR_HI_ISR); + + /* Configure lo_int: set handler and priority. */ + CyIntSetPriority (USBFS_INTR_LO_VECT_NUM, USBFS_INTR_LO_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_LO_VECT_NUM, &USBFS_INTR_LO_ISR); + + /* Configure med_int: set handler and priority (routed through DSI). */ + CyIntSetPriority (USBFS_INTR_MED_VECT_NUM, USBFS_INTR_MED_PRIORITY); + (void) CyIntSetVector(USBFS_INTR_MED_VECT_NUM, &USBFS_INTR_MED_ISR); + +#else + /* Set bus reset interrupt. */ + CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + + /* Set Control Endpoint Interrupt. */ + CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + + /* Set SOF interrupt. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntSetPriority (USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + /* Set Data Endpoint 1 Interrupt. */ + #if (USBFS_EP1_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + /* Set Data Endpoint 2 Interrupt. */ + #if (USBFS_EP2_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + #endif /* (USBFS_EP2_ISR_ACTIVE) */ + + /* Set Data Endpoint 3 Interrupt. */ + #if (USBFS_EP3_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + #endif /* (USBFS_EP3_ISR_ACTIVE) */ + + /* Set Data Endpoint 4 Interrupt. */ + #if (USBFS_EP4_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + #endif /* (USBFS_EP4_ISR_ACTIVE) */ + + /* Set Data Endpoint 5 Interrupt. */ + #if (USBFS_EP5_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + /* Set Data Endpoint 6 Interrupt. */ + #if (USBFS_EP6_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + #endif /* (USBFS_EP6_ISR_ACTIVE) */ + + /* Set Data Endpoint 7 Interrupt. */ + #if (USBFS_EP7_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + /* Set Data Endpoint 8 Interrupt. */ + #if (USBFS_EP8_ISR_ACTIVE) + CyIntSetPriority (USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ + + /* Set ARB Interrupt. */ + #if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + CyIntSetPriority (USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + #endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + + /* Common: Configure GPIO interrupt for wakeup. */ +#if (USBFS_DP_ISR_ACTIVE) + CyIntSetPriority (USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIORITY); + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) + /* Initialize DMA channels. */ + USBFS_InitEpDma(); +#endif /* (USBFS_EP_MANAGEMENT_DMA && CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: USBFS_InitComponent +****************************************************************************//** +* +* This function initializes the component’s global variables and initiates +* communication with the host by pull-up D+ line. +* +* \param device: +* Contains the device number of the desired device descriptor. The device +* number can be found in the Device Descriptor Tab of "Configure" dialog, +* under the settings of desired Device Descriptor, in the *Device Number* +* field. +* \param mode: +* The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following list. +* +* *USBFS_3V_OPERATION* - Disable voltage regulator and pass- +* through Vcc for pull-up +* +* *USBFS_5V_OPERATION* - Enable voltage regulator and use +* regulator for pull-up +* +* *USBFS_DWR_POWER_OPERATION* - Enable or disable the voltage +* regulator depending on the power supply +* voltage configuration in the DWR tab. +* For PSoC 3/5LP devices, the VDDD supply +* voltage is considered and for PSoC 4A-L, +* the VBUS supply voltage is considered. +* +* \globalvars +* \ref USBFS_device +* \ref USBFS_transferState +* \ref USBFS_configuration +* \ref USBFS_deviceStatus +* +* \ref USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using a +* SET_ADDRESS request. +* +* \ref USBFS_lastPacketSize - Initialized to 0; +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_InitComponent(uint8 device, uint8 mode) +{ + /* Initialize _hidProtocol variable to comply with + * HID 7.2.6 Set_Protocol Request: + * "When initialized, all devices default to report protocol." + */ +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ + + /* Store device number to access descriptor. */ + USBFS_device = device; + + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; + + /* Enable component interrupts. */ +#if (CY_PSOC4) + CyIntEnable(USBFS_INTR_HI_VECT_NUM); + CyIntEnable(USBFS_INTR_MED_VECT_NUM); + CyIntEnable(USBFS_INTR_LO_VECT_NUM); +#else + CyIntEnable(USBFS_BUS_RESET_VECT_NUM); + CyIntEnable(USBFS_EP_0_VECT_NUM); + + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + + #if (CY_PSOC3 || CY_PSOC5) + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* (CY_PSOC3 || CY_PSOC5) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) */ + +/* Arbiter configuration for DMA transfers. */ +#if (USBFS_EP_MANAGEMENT_DMA) + /* Configure Arbiter for Manual or Auto DMA operation and clear configuration completion. */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + + #if (CY_PSOC4) + /* Enable DMA operation. */ + CyDmaEnable(); + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Change DMA priority to be highest. */ + CyIntSetPriority(CYDMA_INTR_NUMBER, USBFS_DMA_AUTO_INTR_PRIO); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (CY_PSOC4) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + /* Enable DMA interrupt to handle DMA management. */ + CyIntEnable(CYDMA_INTR_NUMBER); + #else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /* Initialize interrupts which handle verification of successful DMA transaction. */ + USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR); + USBFS_EP17_DMA_Done_SR_InterruptEnable(); + USBFS_EP8_DMA_Done_SR_InterruptEnable(); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Enable USB regulator depends on operation voltage. IMO Locking is enabled in Init(). */ + switch(mode) + { + case USBFS_3V_OPERATION: + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + break; + + case USBFS_5V_OPERATION: + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + break; + + default: /* Check DWR settings of USB power supply. */ + #if (USBFS_VDDD_MV < USBFS_3500MV) + /* Disable regulator for 3V operation. */ + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + #else + /* Enable regulator for 5V operation. */ + USBFS_CR1_REG |= (uint8) USBFS_CR1_REG_ENABLE; + #endif /* (USBFS_VDDD_MV < USBFS_3500MV) */ + break; + } + +#if (CY_PSOC4) + /* Clear bus activity. */ + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_BUS_ACTIVITY; + + /* Clear EP0 count register. */ + USBFS_EP0_CNT_REG = USBFS_CLEAR_REG; + + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; + + #if (USBFS_LPM_ACTIVE) + if (NULL != USBFS_GetBOSPtr()) + { + /* Enable LPM and acknowledge LPM packets for active device. + * Reset NYET_EN and SUB_RESP bits in the LPM_CTRL register. + */ + USBFS_LPM_CTRL_REG = (USBFS_LPM_CTRL_LPM_EN | \ + USBFS_LPM_CTRL_LPM_ACK_RESP); + } + else + { + /* Disable LPM for active device. */ + USBFS_LPM_CTRL_REG &= (uint32) ~USBFS_LPM_CTRL_LPM_EN; + } + #endif /* (USBFS_LPM_ACTIVE) */ + + /* Enable device to responds to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; + +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; + + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); +#endif /* (CY_PSOC4) */ + + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; +} + + +/******************************************************************************* +* Function Name: USBFS_ReInitComponent +****************************************************************************//** +* +* This function reinitialize the component configuration and is +* intend to be called from the Reset interrupt. +* +* \globalvars +* USBFS_device - Contains the device number of the desired Device +* Descriptor. The device number can be found in the Device Descriptor tab +* of the Configure dialog, under the settings of the desired Device Descriptor, +* in the Device Number field. +* USBFS_transferState - This variable is used by the communication +* functions to handle the current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration - Contains the current configuration number +* set by the Host using a SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. +* USBFS_deviceStatus - Initialized to 0. +* This is a two-bit variable which contains the power status in the first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and the remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in the second bit. +* USBFS_lastPacketSize - Initialized to 0; +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ReInitComponent(void) +{ + /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol + * Request: "When initialized, all devices default to report protocol." + */ +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } +#endif /* USBFS_ENABLE_HID_CLASS */ + + /* Reset component internal variables. */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_lastPacketSize = 0u; + +#if (CY_PSOC4) + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; +#else + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; +#endif /* (CY_PSOC4) */ + + /* Enable device to respond to USB traffic with address 0. */ + USBFS_CR0_REG = USBFS_DEFUALT_CR0; +} + + +/******************************************************************************* +* Function Name: USBFS_Stop +****************************************************************************//** +* +* This function shuts down the USB function including to release +* the D+ pull-up and disabling the SIE. +* +* \globalvars +* \ref USBFS_configuration +* +* USBFS_deviceAddress - Contains the current device address. This +* variable is initialized to zero in this API. The Host starts to communicate +* to the device with address 0 and then sets it to a whatever value using +* a SET_ADDRESS request. +* +* \ref USBFS_deviceStatus +* +* \ref USBFS_configurationChanged +* +* USBFS_intiVar - This variable is set to zero +* +*******************************************************************************/ +void USBFS_Stop(void) +{ + uint8 enableInterrupts; + +#if (USBFS_EP_MANAGEMENT_DMA) + /* Stop all DMA channels. */ + USBFS_Stop_DMA(USBFS_MAX_EP); +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + enableInterrupts = CyEnterCriticalSection(); + + /* Disable USB IP to respond to USB traffic. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; + + /* Disable D+ pull-up. */ + USBFS_USBIO_CR1_REG &= (uint8) ~ USBFS_USBIO_CR1_USBPUEN; + +#if (CY_PSOC4) + /* Disable USBFS block. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_ENABLE; +#else + /* Clear power active and standby mode templates. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + + /* Ensure single-ended disable bits are high (PRT15.INP_DIS[7:6]) + * (input receiver disabled). */ + USBFS_DM_INP_DIS_REG |= (uint8) USBFS_DM_MASK; + USBFS_DP_INP_DIS_REG |= (uint8) USBFS_DP_MASK; + +#endif /* (CY_PSOC4) */ + + CyExitCriticalSection(enableInterrupts); + + /* Disable component interrupts. */ +#if (CY_PSOC4) + CyIntDisable(USBFS_INTR_HI_VECT_NUM); + CyIntDisable(USBFS_INTR_LO_VECT_NUM); + CyIntDisable(USBFS_INTR_MED_VECT_NUM); +#else + + CyIntDisable(USBFS_BUS_RESET_VECT_NUM); + CyIntDisable(USBFS_EP_0_VECT_NUM); + + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ + + #if (USBFS_EP1_ISR_ACTIVE) + CyIntDisable(USBFS_EP_1_VECT_NUM); + #endif /* (USBFS_EP1_ISR_ACTIVE) */ + + #if (USBFS_EP2_ISR_ACTIVE) + CyIntDisable(USBFS_EP_2_VECT_NUM); + #endif /* (USBFS_EP2_ISR_ACTIVE) */ + + #if (USBFS_EP3_ISR_ACTIVE) + CyIntDisable(USBFS_EP_3_VECT_NUM); + #endif /* (USBFS_EP3_ISR_ACTIVE) */ + + #if (USBFS_EP4_ISR_ACTIVE) + CyIntDisable(USBFS_EP_4_VECT_NUM); + #endif /* (USBFS_EP4_ISR_ACTIVE) */ + + #if (USBFS_EP5_ISR_ACTIVE) + CyIntDisable(USBFS_EP_5_VECT_NUM); + #endif /* (USBFS_EP5_ISR_ACTIVE) */ + + #if (USBFS_EP6_ISR_ACTIVE) + CyIntDisable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + + #if (USBFS_EP7_ISR_ACTIVE) + CyIntDisable(USBFS_EP_7_VECT_NUM); + #endif /* (USBFS_EP7_ISR_ACTIVE) */ + + #if (USBFS_EP8_ISR_ACTIVE) + CyIntDisable(USBFS_EP_8_VECT_NUM); + #endif /* (USBFS_EP8_ISR_ACTIVE) */ + + #if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE). */ + +#endif /* (CY_PSOC4) */ + + /* Reset component internal variables. */ + USBFS_configurationChanged = 0u; + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + /* It is mandatory for correct device startup. */ + USBFS_initVar = 0u; +} + + +/******************************************************************************* +* Function Name: USBFS_CheckActivity +****************************************************************************//** +* +* This function returns the activity status of the bus. It clears the hardware +* status to provide updated status on the next call of this function. It +* provides a way to determine whether any USB bus activity occurred. The +* application should use this function to determine if the USB suspend +* conditions are met. +* +* +* \return +* cystatus: Status of the bus since the last call of the function. +* Return Value | Description +* -------------|--------------------------------------------------------------- +* 1 |Bus activity was detected since the last call to this function +* 0 |Bus activity was not detected since the last call to this function +* +* +*******************************************************************************/ +uint8 USBFS_CheckActivity(void) +{ + uint8 cr1Reg = USBFS_CR1_REG; + + /* Clear bus activity. */ + USBFS_CR1_REG = (cr1Reg & (uint8) ~USBFS_CR1_BUS_ACTIVITY); + + /* Get bus activity. */ + return ((0u != (cr1Reg & USBFS_CR1_BUS_ACTIVITY)) ? (1u) : (0u)); +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfiguration +****************************************************************************//** +* +* This function gets the current configuration of the USB device. +* +* \return +* Returns the currently assigned configuration. Returns 0 if the device +* is not configured +* +*******************************************************************************/ +uint8 USBFS_GetConfiguration(void) +{ + return (USBFS_configuration); +} + + +/******************************************************************************* +* Function Name: USBFS_IsConfigurationChanged +****************************************************************************//** +* +* This function returns the clear-on-read configuration state. It is useful +* when the host sends double SET_CONFIGURATION request with the same +* configuration number or changes alternate settings of the interface. +* After configuration has been changed the OUT endpoints must be enabled and IN +* endpoint must be loaded with data to start communication with the host. +* +* \return +* None-zero value when new configuration has been changed, otherwise zero is +* returned. +* +* \globalvars +* +* \ref USBFS_configurationChanged - This variable is set to 1 after +* a SET_CONFIGURATION request and cleared in this function. +* +*******************************************************************************/ +uint8 USBFS_IsConfigurationChanged(void) +{ + uint8 res = 0u; + + if (USBFS_configurationChanged != 0u) + { + res = USBFS_configurationChanged; + USBFS_configurationChanged = 0u; + } + + return (res); +} + + +/******************************************************************************* +* Function Name: USBFS_GetInterfaceSetting +****************************************************************************//** +* +* This function gets the current alternate setting for the specified interface. +* It is useful to identify which alternate settings are active in the specified +* interface. +* +* \param +* interfaceNumber interface number +* +* \return +* Returns the current alternate setting for the specified interface. +* +*******************************************************************************/ +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + +{ + return (USBFS_interfaceSetting[interfaceNumber]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPState +****************************************************************************//** +* +* This function returns the state of the requested endpoint. +* +* \param epNumber Data endpoint number +* +* \return +* Returns the current state of the specified USBFS endpoint. Symbolic names and +* their associated values are given in the following table. Use these constants +* whenever you write code to change the state of the endpoints, such as ISR +* code, to handle data sent or received. +* +* Return Value | Description +* -----------------------|----------------------------------------------------- +* USBFS_NO_EVENT_PENDING |The endpoint is awaiting SIE action +* USBFS_EVENT_PENDING |The endpoint is awaiting CPU action +* USBFS_NO_EVENT_ALLOWED |The endpoint is locked from access +* USBFS_IN_BUFFER_FULL |The IN endpoint is loaded and the mode is set to ACK IN +* USBFS_IN_BUFFER_EMPTY |An IN transaction occurred and more data can be loaded +* USBFS_OUT_BUFFER_EMPTY |The OUT endpoint is set to ACK OUT and is waiting for data +* USBFS_OUT_BUFFER_FULL |An OUT transaction has occurred and data can be read +* +*******************************************************************************/ +uint8 USBFS_GetEPState(uint8 epNumber) +{ + return (USBFS_EP[epNumber].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPCount +****************************************************************************//** +* +* This function supports Data Endpoints only(EP1-EP8). +* Returns the transfer count for the requested endpoint. The value from +* the count registers includes 2 counts for the two byte checksum of the +* packet. This function subtracts the two counts. +* +* \param epNumber Data Endpoint Number. +* Valid values are between 1 and 8. +* +* \return +* Returns the current byte count from the specified endpoint or 0 for an +* invalid endpoint. +* +*******************************************************************************/ +uint16 USBFS_GetEPCount(uint8 epNumber) +{ + uint16 cntr = 0u; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Get 11-bits EP counter where epCnt0 - 3 bits MSB and epCnt1 - 8 bits LSB. */ + cntr = ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0) & USBFS_EPX_CNT0_MASK; + cntr = ((uint16) (cntr << 8u)) | ((uint16) USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1); + cntr -= USBFS_EPX_CNTX_CRC_COUNT; + } + + return (cntr); +} + + +#if (USBFS_EP_MANAGEMENT_DMA) +#if (CY_PSOC4) + /******************************************************************************* + * Function Name: USBFS_InitEpDma + ****************************************************************************//** + * + * This function configures priority for all DMA channels utilized by the + * component. Also sets callbacks for DMA auto mode. + * + *******************************************************************************/ + static void USBFS_InitEpDma(void) + { + #if (USBFS_DMA1_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep1_dma_CHANNEL] = USBFS_ep1_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep2_dma_CHANNEL] = USBFS_ep2_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep3_dma_CHANNEL] = USBFS_ep3_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep4_dma_CHANNEL] = USBFS_ep4_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep5_dma_CHANNEL] = USBFS_ep5_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep6_dma_CHANNEL] = USBFS_ep6_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep7_dma_CHANNEL] = USBFS_ep7_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + CYDMA_CH_CTL_BASE.ctl[USBFS_ep8_dma_CHANNEL] = USBFS_ep8_dma_CHANNEL_CFG; + #endif /* (USBFS_DMA8_ACTIVE) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Initialize DMA channel callbacks. */ + #if (USBFS_DMA1_ACTIVE) + (void) USBFS_ep1_dma_SetInterruptCallback(&USBFS_EP1_DMA_DONE_ISR); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + (void) USBFS_ep2_dma_SetInterruptCallback(&USBFS_EP2_DMA_DONE_ISR); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + (void) USBFS_ep3_dma_SetInterruptCallback(&USBFS_EP3_DMA_DONE_ISR); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + (void) USBFS_ep4_dma_SetInterruptCallback(&USBFS_EP4_DMA_DONE_ISR); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + (void) USBFS_ep5_dma_SetInterruptCallback(&USBFS_EP5_DMA_DONE_ISR); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + (void) USBFS_ep6_dma_SetInterruptCallback(&USBFS_EP6_DMA_DONE_ISR); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + (void) USBFS_ep7_dma_SetInterruptCallback(&USBFS_EP7_DMA_DONE_ISR); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + (void) USBFS_ep8_dma_SetInterruptCallback(&USBFS_EP8_DMA_DONE_ISR); + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } +#else + + + /*************************************************************************** + * Function Name: USBFS_InitEP_DMA + ************************************************************************//** + * + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. It is available when the Endpoint Memory Management parameter + * is set to DMA. + * + * This function is automatically called from the USBFS_LoadInEP() and USBFS_ReadOutEP() APIs. + * + * \param epNumber Contains the data endpoint number. + * Valid values are between 1 and 8. + * \param *pData Pointer to a data array that is related to the EP transfers. + * + * \reentrant No. + * + ***************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) + + { + uint16 src; + uint16 dst; + + #if (CY_PSOC3) + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { + /* IN endpoint: source is memory buffer. */ + src = HI16(pData); + dst = HI16(CYDEV_PERIPH_BASE); + } + else + { + /* OUT endpoint: source is USB IP memory buffer. */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* (CY_PSOC3) */ + + switch(epNumber) + { + #if (USBFS_DMA1_ACTIVE) + case USBFS_EP1: + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + case USBFS_EP2: + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + case USBFS_EP3: + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + case USBFS_EP4: + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + case USBFS_EP5: + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + case USBFS_EP6: + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + case USBFS_EP7: + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + case USBFS_EP8: + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize(USBFS_DMA_BYTES_PER_BURST, + USBFS_DMA_REQUEST_PER_BURST, src, dst); + break; + #endif /* (USBFS_DMA8_ACTIVE) */ + + default: + /* Do nothing for endpoints other than 1-8. */ + break; + } + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate(); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } + } +#endif /* (CY_PSOC4) */ + + /*************************************************************************** + * Function Name: USBFS_Stop_DMA + ************************************************************************//** + * + * This function stops DMA channel associated with endpoint. It is available + * when the Endpoint Buffer Management parameter is set to DMA. Call this + * function when endpoint direction is changed from IN to OUT or vice versa + * to trigger DMA re-configuration when USBFS_LoadInEP() or + * USBFS_ReadOutEP() functions are called the first time. + * + * \param epNumber: The data endpoint number for which associated DMA + * channel is stopped. The range of valid values is between 1 and 8. To stop + * all DMAs associated with endpoints call this function with + * USBFS_MAX_EP argument. + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_Stop_DMA(uint8 epNumber) + { + uint8 i; + + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + + do + { + #if (CY_PSOC4) + if (0u != USBFS_DmaChan[i]) + { + USBFS_CyDmaChDisable(USBFS_DmaChan[i]); + } + #else + if(USBFS_DmaTd[i] != DMA_INVALID_TD) + { + (void) CyDmaChDisable(USBFS_DmaChan[i]); + CyDmaTdFree(USBFS_DmaTd[i]); + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + if(USBFS_DmaNextTd[i] != DMA_INVALID_TD) + { + CyDmaTdFree(USBFS_DmaNextTd[i]); + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + #endif /* (CY_PSOC4) */ + i++; + } + while ((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + +#if (CY_PSOC3 || CY_PSOC5) +#if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /*************************************************************************** + * Function Name: USBFS_LoadNextInEP + ************************************************************************//** + * + * Summary: + * This internal function is used for IN endpoint DMA reconfiguration in + * Auto DMA mode. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * mode: 0 - Configure DMA to send the the rest of data. + * 1 - Configure DMA to repeat 2 last bytes of the first burst. + * + ***************************************************************************/ + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) + { + reg16 *convert; + + if (mode == 0u) + { + /* Configure DMA to send rest of data. */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length. */ + CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST); + /* CyDmaTdSetAddress API is optimized to change source address only. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + USBFS_inBufFull[epNumber] = 1u; + } + else + { + /* Configure DMA to repeat 2 last bytes of the first burst. */ + /* CyDmaTdSetConfiguration API is optimized to change transfer length only and configure TD. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length. */ + CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT); + /* CyDmaTdSetAddress API is optimized to change source address only. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + (USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT))); + } + + /* CyDmaChSetInitialTd API is optimized to initialize TD. */ + CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber]; + } +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: USBFS_LoadInEP +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param *pData A pointer to a data array from which the data for the endpoint space +* is loaded. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 +* (1023 for DMA with Automatic Buffer Management mode). The value 512 +* is applicable if only one endpoint is used. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size.*/ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint8) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint8) LO8(length); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) + { + USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr = pData[i]; + } + } + + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if ((pData != NULL) && (length > 0u)) + { + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + --length; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + #else + /* Configure DMA to transfer data. */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + if (pData != NULL) + { + #if (CY_PSOC4) + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_BYTE | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #else + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inDataPointer[epNumber] = pData; + + /* Configure DMA to send data only for first burst */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], + (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + + /* The second TD will be executed only when the first one fails. + * The intention of this TD is to generate NRQ interrupt + * and repeat 2 last bytes of the first burst. + */ + (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u, + USBFS_DmaNextTd[epNumber], + USBFS_epX_TD_TERMOUT_EN[epNumber]); + + /* Configure DmaNextTd to clear Data Ready status. */ + (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32) &clearInDataRdyStatus), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg)); + #else + /* Configure DMA to send all data. */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) pData), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + + /* Clear any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable DMA. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + } + else + { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if (length > 0u) + { + #if (CY_PSOC4) + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #elif (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inBufFull[epNumber] = 0u; + + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + /* Configure DMA to send data only for first burst. */ + (void) CyDmaTdSetConfiguration( + USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ? + USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR ); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) USBFS_inDataPointer[epNumber]), + LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr)); + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable DMA. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param pData: A pointer to a data array from which the data for the endpoint +* space is loaded. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. +* +* \return +* Number of bytes received, 0 for an invalid endpoint. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + +{ + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Copy data using arbiter data register. */ + uint16 i; + for (i = 0u; i < length; ++i) + { + pData[i] = (uint8) USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr; + } + } + + /* Arm OUT endpoint after data has been copied from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else + + #if (CY_PSOC3 || CY_PSOC5LP) + /* Initialize DMA if it was not initialized. */ + if (DMA_INVALID_TD == USBFS_DmaTd[epNumber]) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)(length - 1u) | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else + /* Configure DMA to transfer data. */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32)pData)); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint8) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + uint32 lengthDescr0, lengthDescr1; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of the data elements transfered in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + (USBFS_DmaEpLastBurstEl[epNumber] - 1u) : + (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_BYTES_PER_BURST - 1u); + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_BYTE | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + #else + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32) &USBFS_ARB_EP_BASE.arbEp[epNumber].rwDr), LO16((uint32) pData)); + + /* Clear Any potential pending DMA requests before starting DMA channel to transfer data. */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + + /* Enable DMA channel. */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (CY_PSOC4) */ + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + else + { + length = 0u; + } + + return (length); +} + + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) +/******************************************************************************* +* Function Name: USBFS_LoadInEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in +* the Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function loads and enables the specified USB data endpoint for an IN +* data transfer. +* +* *DMA with Manual Buffer Management:* +* Configures DMA for a data transfer from system RAM to endpoint buffer. +* Generates request for a transfer. +* +* *DMA with Automatic Buffer Management:* +* Configures DMA. This is required only once, so it is done only when parameter +* pData is not NULL. When the pData pointer is NULL, the function skips this +* task. Sets Data ready status: This generates the first DMA transfer and +* prepares data in endpoint buffer. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param *pData A pointer to a data array from which the data for the endpoint +* space is loaded. It shall be ensured that this pointer address is even +* to ensure the 16-bit transfer is aligned to even address. Else, a hard +* fault condition can occur. +* \param length The number of bytes to transfer from the array and then send as +* a result of an IN request. Valid values are between 0 and 512 (1023 for +* DMA with Automatic Buffer Management mode). The value 512 is applicable +* if only one endpoint is used. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP16(uint8 epNumber, const uint8 pData[], uint16 length) +{ + /* Check array alignment on half-word boundary. */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Limit length to available buffer USB IP buffer size. */ + if (length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Set count and data toggle. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt0 = (uint32) HI8(length) | USBFS_EP[epNumber].epToggle; + USBFS_SIE_EP_BASE.sieEp[epNumber].epCnt1 = (uint32) LO8(length); + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + length += (length & 0x01u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + if (NULL != pData) + { + /* Convert uint8 array to uint16. */ + const uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (length >> 1u); ++i) + { + USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16 = dataBuf[i]; + } + } + + /* IN endpoint buffer is full - read to be read. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* IN endpoint buffer will be fully loaded by DMA shortly. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if ((pData != NULL) && (length > 0u)) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + length = (length >> 1u) - 1u; + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | length | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + if (pData != NULL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Store address of buffer. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | + CYDMA_HALFWORD | CYDMA_ELEMENT_WORD | CYDMA_INC_SRC_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + } + else + { + /* IN endpoint buffer (32 bytes) will shortly be preloaded by DMA. */ + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + if (length > 0u) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (length / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in the last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (length % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark which descriptor is last one to execute. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Restore DMA settings for current transfer. */ + USBFS_CyDmaChDisable(channelNum); + + /* Restore destination address for input endpoint. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber])); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Set number of elements to transfer. */ + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR0, lengthDescr0); + USBFS_CyDmaSetNumDataElements(channelNum, USBFS_DMA_DESCR1, lengthDescr1); + + /* Validate descriptor 0 and command to start with it. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Validate descriptor 1. */ + if (USBFS_DmaEpBurstCnt[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + #if !defined (USBFS_MANUAL_IN_EP_ARM) + /* Set IN data ready to generate DMA request to load data into endpoint buffer. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* (USBFS_MANUAL_IN_EP_ARM) */ + + /* IN endpoint will be armed in ARB_ISR(source: IN_BUF_FULL) after first DMA transfer has been completed. */ + } + else + { + /* When zero-length packet: arm IN endpoint directly. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP16 +****************************************************************************//** +* +* This function performs different functionality depending on the Component’s +* configured Endpoint Buffer Management. This parameter is defined in the +* Descriptor Root in Component Configure window. +* +* *Manual (Static/Dynamic Allocation):* +* This function moves the specified number of bytes from endpoint buffer to +* system RAM. The number of bytes actually transferred from endpoint buffer to +* system RAM is the lesser of the actual number of bytes sent by the host or +* the number of bytes requested by the length parameter. +* +* *DMA with Manual Buffer Management:* +* Configure DMA to transfer data from endpoint buffer to system RAM. Generate +* a DMA request. The firmware must wait until the DMA completes the data +* transfer after calling the USBFS_ReadOutEP() API. For example, +* by checking EPstate: +* +* \snippet /USBFS_sut_02.cydsn/main.c checking EPstatey +* +* The USBFS_EnableOutEP() has to be called to allow host to write data into +* the endpoint buffer after DMA has completed transfer data from OUT endpoint +* buffer to SRAM. +* +* *DMA with Automatic Buffer Management:* +* Configure DMA. This is required only once and automatically generates DMA +* requests as data arrives +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* \param pData: A pointer to a data array into which the data for the endpoint +* space is copied. It shall be ensured that this pointer address is +* even to ensure the 16-bit transfer is aligned to even address. Else, +* a hard fault condition can occur. +* \param length: The number of bytes to transfer from the USB Out endpoint and +* loads it into data array. Valid values are between 0 and 1023. The +* function moves fewer than the requested number of bytes if the host +* sends fewer bytes than requested. +* +* \return +* Number of bytes received, 0 for an invalid endpoint. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length) +{ + uint32 adjLength; + + /* Check array alignment on half-word boundary */ + CYASSERT(0u == (((uint32) pData) & 0x01u)); + + if ((pData != NULL) && (epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Adjust requested length to available data. */ + length = (length > USBFS_GetEPCount(epNumber)) ? USBFS_GetEPCount(epNumber) : length; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Adjust requested length: 2 bytes are handled at one data register access. */ + adjLength = length + ((uint32)length & 1u); + + #if (USBFS_EP_MANAGEMENT_MANUAL) + { + /* Convert uint8 array to uint16. */ + uint16 *dataBuf = (uint16 *) pData; + + /* Copy data using 16-bits arbiter data register. */ + uint16 i; + for (i = 0u; i < (adjLength >> 1u); ++i) + { + dataBuf[i] = (uint16) USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16; + } + } + + /* Arm OUT endpoint after data has been read from endpoint buffer. */ + USBFS_EnableOutEP(epNumber); + #else + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + { + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Configure source and destination. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) pData); + + /* Configure DMA descriptor. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | (uint16)((adjLength >> 1u) - 1u) | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_PREEMPTABLE); + + /* Validate descriptor to execute on following DMA request. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* Generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg |= (uint32) USBFS_ARB_EPX_CFG_DMA_REQ; + USBFS_ARB_EP_BASE.arbEp[epNumber].epCfg &= (uint32) ~USBFS_ARB_EPX_CFG_DMA_REQ; + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + { + uint32 lengthDescr0, lengthDescr1; + uint32 channelNum = (uint32) USBFS_DmaChan[epNumber]; + + /* Get number of full bursts. */ + USBFS_DmaEpBurstCnt[epNumber] = (uint8) (adjLength / USBFS_DMA_BYTES_PER_BURST); + + /* Get number of elements in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (uint8) (adjLength % USBFS_DMA_BYTES_PER_BURST); + + /* Get total number of bursts. */ + USBFS_DmaEpBurstCnt[epNumber] += (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? 1u : 0u; + + /* Adjust number of data elements transferred in last burst. */ + USBFS_DmaEpLastBurstEl[epNumber] = (0u != USBFS_DmaEpLastBurstEl[epNumber]) ? + ((USBFS_DmaEpLastBurstEl[epNumber] >> 1u) - 1u) : + (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Get number of data elements to transfer for descriptor 0 and 1. */ + lengthDescr0 = (1u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + lengthDescr1 = (2u == USBFS_DmaEpBurstCnt[epNumber]) ? USBFS_DmaEpLastBurstEl[epNumber] : (USBFS_DMA_HALFWORDS_PER_BURST - 1u); + + /* Mark last descriptor to be executed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (0u != (USBFS_DmaEpBurstCnt[epNumber] & 0x1u)) ? + USBFS_DMA_DESCR0_MASK : USBFS_DMA_DESCR1_MASK; + + /* Mark if revert number of data elements in descriptor after transfer completion. */ + USBFS_DmaEpLastBurstEl[epNumber] |= (USBFS_DmaEpBurstCnt[epNumber] > 2u) ? USBFS_DMA_DESCR_REVERT : 0u; + + /* Mark that 16-bits access to data register is performed. */ + USBFS_DmaEpLastBurstEl[epNumber] |= USBFS_DMA_DESCR_16BITS; + + /* Store address of buffer and burst counter for endpoint. */ + USBFS_DmaEpBufferAddrBackup[epNumber] = (uint32) pData; + USBFS_DmaEpBurstCntBackup[epNumber] = USBFS_DmaEpBurstCnt[epNumber]; + + /* Adjust burst counter taking to account: 2 valid descriptors and interrupt trigger after valid descriptor were executed. */ + USBFS_DmaEpBurstCnt[epNumber] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCnt[epNumber]); + + /* Disable DMA channel: start configuration. */ + USBFS_CyDmaChDisable(channelNum); + + /* Set destination address. */ + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR0, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + USBFS_CyDmaSetSrcAddress(channelNum, USBFS_DMA_DESCR1, (void*) &USBFS_ARB_EP16_BASE.arbEp[epNumber].rwDr16); + + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) pData)); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) pData + USBFS_DMA_BYTES_PER_BURST)); + + /* Configure DMA descriptor 0. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR0, USBFS_DMA_COMMON_CFG | lengthDescr0 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Configure DMA descriptor 1. */ + USBFS_CyDmaSetConfiguration(channelNum, USBFS_DMA_DESCR1, USBFS_DMA_COMMON_CFG | lengthDescr1 | + CYDMA_HALFWORD | CYDMA_WORD_ELEMENT | CYDMA_INC_DST_ADDR | CYDMA_INVALIDATE | CYDMA_CHAIN); + + /* Enable interrupt from DMA channel. */ + USBFS_CyDmaSetInterruptMask(channelNum); + + /* Validate DMA descriptor 0 and 1. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + + if (USBFS_DmaEpBurstCntBackup[epNumber] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + /* OUT endpoint has to be armed again by user when DMA transfers have been completed. + * NO_EVENT_PENDING: notifies that data has been copied from endpoint buffer. + */ + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + else + { + length = 0u; + } + + return (length); +} +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_EnableOutEP +****************************************************************************//** +* +* This function enables the specified endpoint for OUT transfers. Do not call +* this function for IN endpoints. +* +* \param epNumber: Contains the data endpoint number. Valid values are between +* 1 and 8. +* +* \globalvars +* +* \ref USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_EnableOutEP(uint8 epNumber) +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + + /* Enable OUT endpoint to be written by Host. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_EP[epNumber].epMode; + + } +} + + +/******************************************************************************* +* Function Name: USBFS_DisableOutEP +****************************************************************************//** +* +* This function disables the specified USBFS OUT endpoint. Do not call this +* function for IN endpoints. +* +* \param epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* +*******************************************************************************/ +void USBFS_DisableOutEP(uint8 epNumber) +{ + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Set NAK response for OUT endpoint. */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; + } +} + + +/******************************************************************************* +* Function Name: USBFS_Force +****************************************************************************//** +* +* This function forces a USB J, K, or SE0 state on the D+/D– lines. It provides +* the necessary mechanism for a USB device application to perform a USB Remote +* Wakeup. For more information, see the USB 2.0 Specification for details on +* Suspend and Resume. +* +* \param state A byte indicating which of the four bus states to enable. +* Symbolic names and their associated values are listed here: +* State |Description +* ---------------------------|---------------------------------------------- +* USBFS_FORCE_J | Force a J State onto the D+/D– lines +* USBFS_FORCE_K | Force a K State onto the D+/D– lines +* USBFS_FORCE_SE0 | Force a Single Ended 0 onto the D+/D– lines +* USBFS_FORCE_NONE| Return bus to SIE control +* +* +*******************************************************************************/ +void USBFS_Force(uint8 bState) +{ + /* This registers is used only for manual control of SIE (no masking is + * needed before write into it). + */ + USBFS_USBIO_CR0_REG = bState; +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPAckState +****************************************************************************//** +* +* This function determines whether an ACK transaction occurred on this endpoint +* by reading the ACK bit in the control register of the endpoint. It does not +* clear the ACK bit. +* +* \param epNumber Contains the data endpoint number. +* Valid values are between 1 and 8. +* +* \return +* If an ACKed transaction occurred, this function returns a non-zero value. +* Otherwise, it returns zero. +* +*******************************************************************************/ +uint8 USBFS_GetEPAckState(uint8 epNumber) +{ + uint8 cr = 0u; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + cr = USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 & USBFS_MODE_ACKD; + } + + return ((uint8) cr); +} + + +/******************************************************************************* +* Function Name: USBFS_SetPowerStatus +****************************************************************************//** +* +* This function sets the current power status. The device replies to USB +* GET_STATUS requests based on this value. This allows the device to properly +* report its status for USB Chapter 9 compliance. Devices can change their +* power source from self powered to bus powered at any time and report their +* current power source as part of the device status. You should call this +* function any time your device changes from self powered to bus powered or +* vice versa, and set the status appropriately. +* +* \param powerStatus: Contains the desired power status, one for self powered +* or zero for bus powered. Symbolic names and their associated values are +* given here: +* Power Status |Description +* --------------------------------------------|--------------------------- +* USBFS_DEVICE_STATUS_BUS_POWERED | Set the device to bus powered +* USBFS_DEVICE_STATUS_SELF_POWERED | Set the device to self powered +* +* \globalvars +* +* \ref USBFS_deviceStatus - set power status +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_SetPowerStatus(uint8 powerStatus) +{ + if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) + { + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; + } +} + + +#if (USBFS_VBUS_MONITORING_ENABLE) + /*************************************************************************** + * Function Name: USBFS_VBusPresent + ************************************************************************//** + * + * Determines VBUS presence for self-powered devices. This function is + * available when the VBUS Monitoring option is enabled in the Advanced tab. + * + * \return + * The return value can be the following: + * Return Value | Description + * -------------|----------------- + * 1 | VBUS is present + * 0 | VBUS is absent + * + * + ***************************************************************************/ + uint8 USBFS_VBusPresent(void) + { + return ((0u != (USBFS_VBUS_STATUS_REG & USBFS_VBUS_VALID)) ? (uint8) 1u : (uint8) 0u); + } +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_RWUEnabled +****************************************************************************//** +* +* This function returns the current remote wakeup status. +* If the device supports remote wakeup, the application should use this +* function to determine if remote wakeup was enabled by the host. When the +* device is suspended and it determines the conditions to initiate a remote +* wakeup are met, the application should use the USBFS_Force() function to +* force the appropriate J and K states onto the USB bus, signaling a remote +* wakeup. +* +* +* \return +* Returns non-zero value if remote wakeup is enabled and zero otherwise. +* +* \globalvars +* USBFS_deviceStatus - checked to determine remote status +* +*******************************************************************************/ +uint8 USBFS_RWUEnabled(void) +{ + uint8 result = USBFS_FALSE; + + if (0u != (USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP)) + { + result = USBFS_TRUE; + } + + return (result); +} + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceAddress +****************************************************************************//** +* +* This function returns the currently assigned address for the USB device. +* +* \return +* Returns the currently assigned address. +* Returns 0 if the device has not yet been assigned an address. +* +*******************************************************************************/ +uint8 USBFS_GetDeviceAddress(void) +{ + return (uint8)(USBFS_CR0_REG & USBFS_CR0_DEVICE_ADDRESS_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableSofInt +****************************************************************************//** +* +* This function enables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_EnableSofInt(void) +{ +#if (CY_PSOC4) + /* Enable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG |= (uint32) USBFS_INTR_SIE_SOF_INTR; +#else + /* Enable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntEnable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +/******************************************************************************* +* Function Name: USBFS_DisableSofInt +****************************************************************************//** +* +* This function disables interrupt generation when a Start-of-Frame (SOF) +* packet is received from the host. +* +*******************************************************************************/ +void USBFS_DisableSofInt(void) +{ +#if (CY_PSOC4) + /* Disable SOF interrupt interrupt source. */ + USBFS_INTR_SIE_MASK_REG &= (uint32) ~USBFS_INTR_SIE_SOF_INTR; +#else + /* Disable SOF interrupt if it is present. */ + #if (USBFS_SOF_ISR_ACTIVE) + CyIntDisable(USBFS_SOF_VECT_NUM); + #endif /* (USBFS_SOF_ISR_ACTIVE) */ +#endif /* (CY_PSOC4) */ +} + + +#if (USBFS_BATT_CHARG_DET_ENABLE) + /*************************************************************************** + * Function Name: USBFS_DetectPortType + ************************************************************************//** + * + * This function implements the USB Battery Charger Detection (BCD) + * algorithm to determine the type of USB host downstream port. This API + * is available only for PSoC 4 devices, and should be called when the VBUS + * voltage transition (OFF to ON) is detected on the bus. If the USB device + * functionality is enabled, this API first calls USBFS_Stop() API + * internally to disable the USB device functionality, and then proceeds to + * implement the BCD algorithm to detect the USB host port type. + * The USBFS_Start() API should be called after this API if the USB + * communication needs to be initiated with the host. + * *Note* This API is generated only if the “Enable Battery Charging + * Detection” option is enabled in the “Advanced” tab of the component GUI. + * *Note* API implements the steps 2-4 of the BCD algorithm which are + * - Data Contact Detect + * - Primary Detection + * - Secondary Detection + * + * The first step of BCD algorithm, namely, VBUS detection shall be handled + * at the application firmware level. + * + * \return + * The return value can be the following: + * Return Value |Description + * ----------------------------------|------------------------------------- + * USBFS_BCD_PORT_SDP | Standard downstream port detected + * USBFS_BCD_PORT_CDP | Charging downstream port detected + * USBFS_BCD_PORT_DCP | Dedicated charging port detected + * USBFS_BCD_PORT_UNKNOWN | Unable to detect charging port type (proprietary charger type) + * USBFS_BCD_PORT_ERR | Error condition in detection process + * + * + * \sideeffects + * + * USB device functionality is disabled by this API if not already disabled. + * + ***************************************************************************/ + uint8 USBFS_Bcd_DetectPortType(void) + { + uint32 bkPwrCtrl; + uint32 cr1RegVal; + uint32 secondaryDetection = 0u; + uint8 result = USBFS_BCD_PORT_UNKNOWN; + + /*Check USB Started and Stop it*/ + if(0u != USBFS_initVar) + { + USBFS_Stop(); + } + /*Initialize USBFS IP for Charger detection*/ + + /*Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_CSR_CLK_EN; + + /* Enable USBIO control on drive mode of D+ and D- pins. */ + USBFS_USBIO_CR1_REG &= ~ (uint32) USBFS_USBIO_CR1_IOMODE; + + /* Select VBUS detection source and clear PHY isolate. The application + * level must ensure that VBUS is valid. There is no need to wait 2us + * before VBUS is valid. + */ + bkPwrCtrl = USBFS_POWER_CTRL_REG; + USBFS_POWER_CTRL_REG = USBFS_DEFAULT_POWER_CTRL_VBUS\ + & (~USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN)\ + & (~USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN); + + + /* Enable PHY detector and single-ended and differential receivers. + * Enable charger detection. */ + USBFS_POWER_CTRL_REG |= USBFS_DEFAULT_POWER_CTRL_PHY\ + | USBFS_POWER_CTRL_ENABLE_CHGDET; + + /* Suspend clear sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + /* Data connection detection + * Realization with delay as Hard IP does not support DCD 300 ms. + */ + #if defined (USBFS_NO_DCD) + CyDelay(USBFS_BCD_TIMEOUT); + #else + /* DCD implementation:*/ + + { + uint16 timeout = USBFS_BCD_TIMEOUT; + uint8 connectionApproved = 0u; + uint8 connected = 0u; + + /* BCD spec 1.2: Turns on Idp_src and D- pull-down resistor */ + USBFS_POWER_CTRL_REG |= USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN; + USBFS_CHGDET_CTRL_REG |= USBFS_CHGDET_CTRL_DCD_SRC_EN; + + /* BCD spec 1.2: Waits for D+ to be low for a time of Tdcd_dbnc*/ + while ((0u != timeout) && (0u == connectionApproved)) + { + if (0u == (USBFS_USBIO_CR1_REG & USBFS_USBIO_CR1_DP0)) + { + connected++; + } + else + { + connected = 0u; + } + connectionApproved = (USBFS_BCD_TDCD_DBNC < connected) ? 1u:0u; + CyDelay(1u); + timeout--; + } + + /* BCD spec 1.2: Turns off Idp_src. */ + USBFS_CHGDET_CTRL_REG &= ~USBFS_CHGDET_CTRL_DCD_SRC_EN; + } + #endif /*(USBFS_NO_DCD)*/ + + /* Primary detection: enable VDP_SRC on D+ and IDM_SINK on D-. */ + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_PRIMARY; + CyDelay(USBFS_BCD_PRIMARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 2 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D- line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DM0)) + { + result = USBFS_BCD_PORT_SDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Need Secondary detection. Charging port: DCP or proprietary*/ + secondaryDetection = 1u; + } + + /* Secondary detection: Set CHGDET_CTRL register to enable VDM_SRC on D- and IDP_SINK on D+. */ + + if (0u != secondaryDetection) + { + USBFS_CHGDET_CTRL_REG = USBFS_CHGDET_CTRL_DEFAULT \ + | USBFS_CHGDET_CTRL_SECONDARY; + CyDelay(USBFS_BCD_SECONDARY_WAIT); + cr1RegVal = USBFS_USBIO_CR1_REG; + + /* Check is it SDP or DCP/CDP, read comparator 1 output. */ + if (0u == (USBFS_CHGDET_CTRL_REG & USBFS_CHGDET_CTRL_COMP_OUT)) + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_CDP; + } + else + { + /* ERROR: such combination is impossible. Abort charger + * detection. + */ + result = USBFS_BCD_PORT_ERR; + } + } + else + { + /* Check status of D+ line. */ + if (0u == (cr1RegVal & USBFS_USBIO_CR1_DP0)) + { + result = USBFS_BCD_PORT_DCP; + } + else + { + /* It is may be proprietary charger. Proprietary charge is + * not supported byHardware IP block. + */ + result = USBFS_BCD_PORT_UNKNOWN; + } + } + } + + /* Restore CHGDET_CTRL. */ + USBFS_CHGDET_CTRL_REG = 0u; + + /*Revert registers back*/ + USBFS_POWER_CTRL_REG = bkPwrCtrl; + USBFS_USBIO_CR1_REG |= (uint32) USBFS_USBIO_CR1_IOMODE; + USBFS_USB_CLK_EN_REG = ~USBFS_USB_CLK_CSR_CLK_EN; + + return (result); + } +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + + +#if (USBFS_LPM_ACTIVE) + /*************************************************************************** + * Function Name: USBFS_Lpm_GetBeslValue + ************************************************************************//** + * + * This function returns the Best Effort Service Latency (BESL) value + * sent by the host as part of the LPM token transaction. + * + * \return + * 4-bit BESL value received in the LPM token packet from the host + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetBeslValue(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_BESL_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_RemoteWakeUpAllowed + ************************************************************************//** + * + * This function returns the remote wakeup permission set for the device by + * the host as part of the LPM token transaction. + * + * \return + * 0 - remote wakeup not allowed, 1 - remote wakeup allowed + * + * + ***************************************************************************/ + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void) + { + return (uint32) (USBFS_LPM_STAT_REG & USBFS_LPM_STAT_LPM_REMOTE_WAKE); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_SetResponse + ************************************************************************//** + * + * This function configures the response in the handshake packet the device + * has to send when an LPM token packet is received. + * + * \param response + * type of response to return for an LPM token packet + * Allowed response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be + * responded with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be + * responded with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be + * responded with NYET + * + ***************************************************************************/ + void USBFS_Lpm_SetResponse(uint32 response) + { + uint32 lpmCtrl = USBFS_LPM_CTRL_REG & (uint32) ~USBFS_LPM_CTRL_ACK_NYET_MASK; + + USBFS_LPM_CTRL_REG = lpmCtrl | ((uint32) response & USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + + /*************************************************************************** + * Function Name: USBFS_Lpm_GetResponse + ************************************************************************//** + * + * This function returns the currently configured response value that the + * device will send as part of the handshake packet when an LPM token + * packet is received. + * + * \return + * type of handshake response that will be returned by the device + * for an LPM token packet + * Possible response values: + * - USBFS_LPM_REQ_ACK - next LPM request will be responded + * with ACK + * - USBFS_LPM_REQ_NACK - next LPM request will be responded + * with NACK + * - USBFS_LPM_REQ_NYET - next LPM request will be responded + * with NYET + * + ***************************************************************************/ + uint32 USBFS_Lpm_GetResponse(void) + { + + return ((uint32) USBFS_LPM_CTRL_REG & (uint32)USBFS_LPM_CTRL_ACK_NYET_MASK); + } + + +#endif /* (USBFS_LPM_ACTIVE) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h new file mode 100644 index 0000000..5a3a625 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS.h @@ -0,0 +1,2081 @@ +/***************************************************************************//** +* \file USBFS.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_H) +#define CY_USBFS_USBFS_H + +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cytypes.h" +#include "CyLib.h" + + +/* User supplied definitions. */ +/* `#START USER_DEFINITIONS` Place your declaration here */ + +/* `#END` */ + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/* USB IP memory management options. */ +#define USBFS__EP_MANUAL (0u) +#define USBFS__EP_DMAMANUAL (1u) +#define USBFS__EP_DMAAUTO (2u) + +/* USB IP memory allocation options. */ +#define USBFS__MA_STATIC (0u) +#define USBFS__MA_DYNAMIC (1u) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_NUM_DEVICES (1u) +#define USBFS_ENABLE_MIDI_CLASS (0u) +#define USBFS_ENABLE_MSC_CLASS (0u) +#define USBFS_BOS_ENABLE (0u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_STRINGS +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT (1u) +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x25u) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_HID_RPT_2_SIZE_LSB (0x25u) +#define USBFS_HID_RPT_2_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) + +#define USBFS_MON_VBUS (0u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_POWER_PAD_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#define USBFS_MAX_INTERFACES_NUMBER (2u) +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_ENABLE_BATT_CHARG_DET (0u) +#define USBFS_GEN_16BITS_EP_ACCESS (0u) + +/* Enable Class APIs: MIDI, CDC, MSC. */ +#define USBFS_ENABLE_CDC_CLASS_API (0u != (1u)) + +/* General parameters */ +#define USBFS_EP_ALLOC_STATIC (USBFS_EP_MA == USBFS__MA_STATIC) +#define USBFS_EP_ALLOC_DYNAMIC (USBFS_EP_MA == USBFS__MA_DYNAMIC) +#define USBFS_EP_MANAGEMENT_MANUAL (USBFS_EP_MM == USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA (USBFS_EP_MM != USBFS__EP_MANUAL) +#define USBFS_EP_MANAGEMENT_DMA_MANUAL (USBFS_EP_MM == USBFS__EP_DMAMANUAL) +#define USBFS_EP_MANAGEMENT_DMA_AUTO (USBFS_EP_MM == USBFS__EP_DMAAUTO) +#define USBFS_BATT_CHARG_DET_ENABLE (CY_PSOC4 && (0u != USBFS_ENABLE_BATT_CHARG_DET)) +#define USBFS_16BITS_EP_ACCESS_ENABLE (CY_PSOC4 && (0u != USBFS_GEN_16BITS_EP_ACCESS)) +#define USBFS_VBUS_MONITORING_ENABLE (0u != USBFS_MON_VBUS) +#define USBFS_VBUS_MONITORING_INTERNAL (0u == USBFS_EXTERN_VBUS) +#define USBFS_VBUS_POWER_PAD_ENABLE (0u != USBFS_POWER_PAD_VBUS) + +/* Control endpoints availability */ +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_BUS_RESET_ISR_REMOVE (0u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_LPM_REMOVE (1u) +#define USBFS_SOF_ISR_ACTIVE ((0u == USBFS_SOF_ISR_REMOVE) ? 1u: 0u) +#define USBFS_BUS_RESET_ISR_ACTIVE ((0u == USBFS_BUS_RESET_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP0_ISR_ACTIVE ((0u == USBFS_EP0_ISR_REMOVE) ? 1u: 0u) +#define USBFS_ARB_ISR_ACTIVE ((0u == USBFS_ARB_ISR_REMOVE) ? 1u: 0u) +#define USBFS_DP_ISR_ACTIVE ((0u == USBFS_DP_ISR_REMOVE) ? 1u: 0u) +#define USBFS_LPM_ACTIVE ((CY_PSOC4 && (0u == USBFS_LPM_REMOVE)) ? 1u: 0u) + +/* Data endpoints availability */ +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#define USBFS_EP3_ISR_REMOVE (0u) +#define USBFS_EP4_ISR_REMOVE (0u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP1_ISR_ACTIVE ((0u == USBFS_EP1_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP2_ISR_ACTIVE ((0u == USBFS_EP2_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP3_ISR_ACTIVE ((0u == USBFS_EP3_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP4_ISR_ACTIVE ((0u == USBFS_EP4_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP5_ISR_ACTIVE ((0u == USBFS_EP5_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP6_ISR_ACTIVE ((0u == USBFS_EP6_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP7_ISR_ACTIVE ((0u == USBFS_EP7_ISR_REMOVE) ? 1u: 0u) +#define USBFS_EP8_ISR_ACTIVE ((0u == USBFS_EP8_ISR_REMOVE) ? 1u: 0u) + +#define USBFS_EP_DMA_AUTO_OPT ((CY_PSOC4) ? (1u) : (0u)) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_DMA1_ACTIVE ((0u == USBFS_DMA1_REMOVE) ? 1u: 0u) +#define USBFS_DMA2_ACTIVE ((0u == USBFS_DMA2_REMOVE) ? 1u: 0u) +#define USBFS_DMA3_ACTIVE ((0u == USBFS_DMA3_REMOVE) ? 1u: 0u) +#define USBFS_DMA4_ACTIVE ((0u == USBFS_DMA4_REMOVE) ? 1u: 0u) +#define USBFS_DMA5_ACTIVE ((0u == USBFS_DMA5_REMOVE) ? 1u: 0u) +#define USBFS_DMA6_ACTIVE ((0u == USBFS_DMA6_REMOVE) ? 1u: 0u) +#define USBFS_DMA7_ACTIVE ((0u == USBFS_DMA7_REMOVE) ? 1u: 0u) +#define USBFS_DMA8_ACTIVE ((0u == USBFS_DMA8_REMOVE) ? 1u: 0u) + + +/*************************************** +* Data Structures Definition +***************************************/ + +typedef struct +{ + uint8 attrib; + uint8 apiEpState; + uint8 hwEpState; + uint8 epToggle; + uint8 addr; + uint8 epMode; + uint16 buffOffset; + uint16 bufferSize; + uint8 interface; +} T_USBFS_EP_CTL_BLOCK; + +typedef struct +{ + uint8 interface; + uint8 altSetting; + uint8 addr; + uint8 attributes; + uint16 bufferSize; + uint8 bMisc; +} T_USBFS_EP_SETTINGS_BLOCK; + +typedef struct +{ + uint8 status; + uint16 length; +} T_USBFS_XFER_STATUS_BLOCK; + +typedef struct +{ + uint16 count; + volatile uint8 *pData; + T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; +} T_USBFS_TD; + +typedef struct +{ + uint8 c; + const void *p_list; +} T_USBFS_LUT; + +/* Resume/Suspend API Support */ +typedef struct +{ + uint8 enableState; + uint8 mode; +#if (CY_PSOC4) + uint8 intrSeiMask; +#endif /* (CY_PSOC4) */ +} USBFS_BACKUP_STRUCT; + +/* Number of endpoint 0 data registers. */ +#define USBFS_EP0_DR_MAPPED_REG_CNT (8u) + +/* Structure to access data registers for EP0. */ +typedef struct +{ + uint8 epData[USBFS_EP0_DR_MAPPED_REG_CNT]; +} USBFS_ep0_data_struct; + +/* Number of SIE endpoint registers group. */ +#define USBFS_SIE_EP_REG_SIZE (USBFS_USB__SIE_EP1_CR0 - \ + USBFS_USB__SIE_EP1_CNT0) + +/* Size of gap between SIE endpoint registers groups. */ +#define USBFS_SIE_GAP_CNT (((USBFS_USB__SIE_EP2_CNT0 - \ + (USBFS_USB__SIE_EP1_CNT0 + \ + USBFS_SIE_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to SIE registers for endpoint. */ +typedef struct +{ + uint8 epCnt0; + uint8 epCnt1; + uint8 epCr0; + uint8 gap[USBFS_SIE_GAP_CNT]; +} USBFS_sie_ep_struct; + +/* Number of ARB endpoint registers group. */ +#define USBFS_ARB_EP_REG_SIZE (USBFS_USB__ARB_RW1_DR - \ + USBFS_USB__ARB_EP1_CFG) + +/* Size of gap between ARB endpoint registers groups. */ +#define USBFS_ARB_GAP_CNT (((USBFS_USB__ARB_EP2_CFG - \ + (USBFS_USB__ARB_EP1_CFG + \ + USBFS_ARB_EP_REG_SIZE)) / sizeof(reg8)) - 1u) + +/* Structure to access to ARB registers for endpoint. */ +typedef struct +{ + uint8 epCfg; + uint8 epIntEn; + uint8 epSr; + uint8 reserved; + uint8 rwWa; + uint8 rwWaMsb; + uint8 rwRa; + uint8 rwRaMsb; + uint8 rwDr; + uint8 gap[USBFS_ARB_GAP_CNT]; +} USBFS_arb_ep_struct; + +#if (CY_PSOC4) + /* Number of ARB endpoint registers group (16-bits access). */ + #define USBFS_ARB_EP_REG16_SIZE (USBFS_USB__ARB_RW1_DR16 - \ + USBFS_USB__ARB_RW1_WA16) + + /* Size of gap between ARB endpoint registers groups (16-bits access). */ + #define USBFS_ARB_EP_REG16_GAP_CNT (((USBFS_USB__ARB_RW2_WA16 - \ + (USBFS_USB__ARB_RW1_WA16 + \ + USBFS_ARB_EP_REG16_SIZE)) / sizeof(reg8)) - 1u) + + /* Structure to access to ARB registers for endpoint (16-bits access). */ + typedef struct + { + uint8 rwWa16; + uint8 reserved0; + uint8 rwRa16; + uint8 reserved1; + uint8 rwDr16; + uint8 gap[USBFS_ARB_EP_REG16_GAP_CNT]; + } USBFS_arb_ep_reg16_struct; +#endif /* (CY_PSOC4) */ + +/* Number of endpoint (takes to account that endpoints numbers are 1-8). */ +#define USBFS_NUMBER_EP (9u) + +/* Consoled SIE register groups for endpoints 1-8. */ +typedef struct +{ + USBFS_sie_ep_struct sieEp[USBFS_NUMBER_EP]; +} USBFS_sie_eps_struct; + +/* Consolidate ARB register groups for endpoints 1-8.*/ +typedef struct +{ + USBFS_arb_ep_struct arbEp[USBFS_NUMBER_EP]; +} USBFS_arb_eps_struct; + +#if (CY_PSOC4) + /* Consolidate ARB register groups for endpoints 1-8 (16-bits access). */ + typedef struct + { + USBFS_arb_ep_reg16_struct arbEp[USBFS_NUMBER_EP]; + } USBFS_arb_eps_reg16_struct; +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_InitComponent(uint8 device, uint8 mode) ; +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_Stop(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + ; +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +void USBFS_TerminateEP(uint8 epNumber) ; + +uint8 USBFS_GetDeviceAddress(void) ; + +void USBFS_EnableSofInt(void) ; +void USBFS_DisableSofInt(void) ; + + +#if defined(USBFS_ENABLE_FWSN_STRING) + void USBFS_SerialNumString(uint8 snString[]) ; +#endif /* USBFS_ENABLE_FWSN_STRING */ + +#if (USBFS_VBUS_MONITORING_ENABLE) + uint8 USBFS_VBusPresent(void) ; +#endif /* (USBFS_VBUS_MONITORING_ENABLE) */ + +#if (USBFS_16BITS_EP_ACCESS_ENABLE) + /* PSoC4 specific functions for 16-bit data register access. */ + void USBFS_LoadInEP16 (uint8 epNumber, const uint8 pData[], uint16 length); + uint16 USBFS_ReadOutEP16(uint8 epNumber, uint8 pData[], uint16 length); +#endif /* (USBFS_16BITS_EP_ACCESS_ENABLE) */ + +#if (USBFS_BATT_CHARG_DET_ENABLE) + uint8 USBFS_Bcd_DetectPortType(void); +#endif /* (USBFS_BATT_CHARG_DET_ENABLE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8 *pData) ; + void USBFS_Stop_DMA(uint8 epNumber) ; +/** @} general */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +/** +* \addtogroup group_power +* @{ +*/ +uint8 USBFS_CheckActivity(void) ; +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; +uint8 USBFS_RWUEnabled(void) ; + +#if (USBFS_LPM_ACTIVE) + uint32 USBFS_Lpm_GetBeslValue(void); + uint32 USBFS_Lpm_RemoteWakeUpAllowed(void); + void USBFS_Lpm_SetResponse(uint32 response); + uint32 USBFS_Lpm_GetResponse(void); +#endif /* (USBFS_LPM_ACTIVE) */ + +/** @} power */ + + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) +/** +* \addtogroup group_bootloader +* @{ +*/ + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; + cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; +/** @} bootloader */ + + #define USBFS_BTLDR_OUT_EP (0x01u) + #define USBFS_BTLDR_IN_EP (0x02u) + + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* Endpoint 1 (OUT) buffer size. */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* Endpoint 2 (IN) buffer size. */ + #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER + + #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */ + + /* Map-specific USB bootloader communication functions to common bootloader functions */ + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) + #define CyBtldrCommStart USBFS_CyBtldrCommStart + #define CyBtldrCommStop USBFS_CyBtldrCommStop + #define CyBtldrCommReset USBFS_CyBtldrCommReset + #define CyBtldrCommWrite USBFS_CyBtldrCommWrite + #define CyBtldrCommRead USBFS_CyBtldrCommRead + #endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */ +#endif /* CYDEV_BOOTLOADER_IO_COMP */ + + +/*************************************** +* API Constants +***************************************/ + +#define USBFS_EP0 (0u) +#define USBFS_EP1 (1u) +#define USBFS_EP2 (2u) +#define USBFS_EP3 (3u) +#define USBFS_EP4 (4u) +#define USBFS_EP5 (5u) +#define USBFS_EP6 (6u) +#define USBFS_EP7 (7u) +#define USBFS_EP8 (8u) +#define USBFS_MAX_EP (9u) + +#define USBFS_TRUE (1u) +#define USBFS_FALSE (0u) + +#define USBFS_NO_EVENT_ALLOWED (2u) +#define USBFS_EVENT_PENDING (1u) +#define USBFS_NO_EVENT_PENDING (0u) + +#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING +#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING + +#define USBFS_FORCE_J (0xA0u) +#define USBFS_FORCE_K (0x80u) +#define USBFS_FORCE_SE0 (0xC0u) +#define USBFS_FORCE_NONE (0x00u) + +#define USBFS_IDLE_TIMER_RUNNING (0x02u) +#define USBFS_IDLE_TIMER_EXPIRED (0x01u) +#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) + +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) + +#define USBFS_3V_OPERATION (0x00u) +#define USBFS_5V_OPERATION (0x01u) +#define USBFS_DWR_POWER_OPERATION (0x02u) + +#define USBFS_MODE_DISABLE (0x00u) +#define USBFS_MODE_NAK_IN_OUT (0x01u) +#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) +#define USBFS_MODE_STALL_IN_OUT (0x03u) +#define USBFS_MODE_RESERVED_0100 (0x04u) +#define USBFS_MODE_ISO_OUT (0x05u) +#define USBFS_MODE_STATUS_IN_ONLY (0x06u) +#define USBFS_MODE_ISO_IN (0x07u) +#define USBFS_MODE_NAK_OUT (0x08u) +#define USBFS_MODE_ACK_OUT (0x09u) +#define USBFS_MODE_RESERVED_1010 (0x0Au) +#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) +#define USBFS_MODE_NAK_IN (0x0Cu) +#define USBFS_MODE_ACK_IN (0x0Du) +#define USBFS_MODE_RESERVED_1110 (0x0Eu) +#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) +#define USBFS_MODE_MASK (0x0Fu) +#define USBFS_MODE_STALL_DATA_EP (0x80u) + +#define USBFS_MODE_ACKD (0x10u) +#define USBFS_MODE_OUT_RCVD (0x20u) +#define USBFS_MODE_IN_RCVD (0x40u) +#define USBFS_MODE_SETUP_RCVD (0x80u) + +#define USBFS_RQST_TYPE_MASK (0x60u) +#define USBFS_RQST_TYPE_STD (0x00u) +#define USBFS_RQST_TYPE_CLS (0x20u) +#define USBFS_RQST_TYPE_VND (0x40u) +#define USBFS_RQST_DIR_MASK (0x80u) +#define USBFS_RQST_DIR_D2H (0x80u) +#define USBFS_RQST_DIR_H2D (0x00u) +#define USBFS_RQST_RCPT_MASK (0x03u) +#define USBFS_RQST_RCPT_DEV (0x00u) +#define USBFS_RQST_RCPT_IFC (0x01u) +#define USBFS_RQST_RCPT_EP (0x02u) +#define USBFS_RQST_RCPT_OTHER (0x03u) + +#if (USBFS_LPM_ACTIVE) + #define USBFS_LPM_REQ_ACK (0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_REQ_NACK (0x00u) + #define USBFS_LPM_REQ_NYET (0x01u << USBFS_LPM_CTRL_NYET_EN_POS) +#endif /*(USBFS_LPM_ACTIVE)*/ + +/* USB Class Codes */ +#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ +#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ +#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ +#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ +#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ +#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ +#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ +#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ +#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ +#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ +#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ +#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ +#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Health care device */ +#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ +#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ +#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ +#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ + +/* Standard Request Types (Table 9-4) */ +#define USBFS_GET_STATUS (0x00u) +#define USBFS_CLEAR_FEATURE (0x01u) +#define USBFS_SET_FEATURE (0x03u) +#define USBFS_SET_ADDRESS (0x05u) +#define USBFS_GET_DESCRIPTOR (0x06u) +#define USBFS_SET_DESCRIPTOR (0x07u) +#define USBFS_GET_CONFIGURATION (0x08u) +#define USBFS_SET_CONFIGURATION (0x09u) +#define USBFS_GET_INTERFACE (0x0Au) +#define USBFS_SET_INTERFACE (0x0Bu) +#define USBFS_SYNCH_FRAME (0x0Cu) + +/* Vendor Specific Request Types */ +/* Request for Microsoft OS String Descriptor */ +#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) + +/* Descriptor Types (Table 9-5) */ +#define USBFS_DESCR_DEVICE (1u) +#define USBFS_DESCR_CONFIG (2u) +#define USBFS_DESCR_STRING (3u) +#define USBFS_DESCR_INTERFACE (4u) +#define USBFS_DESCR_ENDPOINT (5u) +#define USBFS_DESCR_DEVICE_QUALIFIER (6u) +#define USBFS_DESCR_OTHER_SPEED (7u) +#define USBFS_DESCR_INTERFACE_POWER (8u) +#if (USBFS_BOS_ENABLE) + #define USBFS_DESCR_BOS (15u) +#endif /* (USBFS_BOS_ENABLE) */ +/* Device Descriptor Defines */ +#define USBFS_DEVICE_DESCR_LENGTH (18u) +#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) + +/* Config Descriptor Shifts and Masks */ +#define USBFS_CONFIG_DESCR_LENGTH (0u) +#define USBFS_CONFIG_DESCR_TYPE (1u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) +#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) +#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) +#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) +#define USBFS_CONFIG_DESCR_ATTRIB (7u) +#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) +#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) + +#if (USBFS_BOS_ENABLE) + /* Config Descriptor BOS */ + #define USBFS_BOS_DESCR_LENGTH (0u) + #define USBFS_BOS_DESCR_TYPE (1u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_LOW (2u) + #define USBFS_BOS_DESCR_TOTAL_LENGTH_HI (3u) + #define USBFS_BOS_DESCR_NUM_DEV_CAPS (4u) +#endif /* (USBFS_BOS_ENABLE) */ + +/* Feature Selectors (Table 9-6) */ +#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) +#define USBFS_ENDPOINT_HALT (0x00u) +#define USBFS_TEST_MODE (0x02u) + +/* USB Device Status (Figure 9-4) */ +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) +#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) + +/* USB Endpoint Status (Figure 9-4) */ +#define USBFS_ENDPOINT_STATUS_HALT (0x01u) + +/* USB Endpoint Directions */ +#define USBFS_DIR_IN (0x80u) +#define USBFS_DIR_OUT (0x00u) +#define USBFS_DIR_UNUSED (0x7Fu) + +/* USB Endpoint Attributes */ +#define USBFS_EP_TYPE_CTRL (0x00u) +#define USBFS_EP_TYPE_ISOC (0x01u) +#define USBFS_EP_TYPE_BULK (0x02u) +#define USBFS_EP_TYPE_INT (0x03u) +#define USBFS_EP_TYPE_MASK (0x03u) + +#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) +#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) +#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) +#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) +#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) + +#define USBFS_EP_USAGE_TYPE_DATA (0x00u) +#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) +#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) +#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) +#define USBFS_EP_USAGE_TYPE_MASK (0x30u) + +/* Point Status defines */ +#define USBFS_EP_STATUS_LENGTH (0x02u) + +/* Point Device defines */ +#define USBFS_DEVICE_STATUS_LENGTH (0x02u) + +#define USBFS_STATUS_LENGTH_MAX \ + ((USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH) + +/* Transfer Completion Notification */ +#define USBFS_XFER_IDLE (0x00u) +#define USBFS_XFER_STATUS_ACK (0x01u) +#define USBFS_XFER_PREMATURE (0x02u) +#define USBFS_XFER_ERROR (0x03u) + +/* Driver State defines */ +#define USBFS_TRANS_STATE_IDLE (0x00u) +#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) +#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) +#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) + +/* String Descriptor defines */ +#define USBFS_STRING_MSOS (0xEEu) +#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) +#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) + +/* Return values */ +#define USBFS_BCD_PORT_SDP (1u) /* Standard downstream port detected */ +#define USBFS_BCD_PORT_CDP (2u) /* Charging downstream port detected */ +#define USBFS_BCD_PORT_DCP (3u) /* Dedicated charging port detected */ +#define USBFS_BCD_PORT_UNKNOWN (0u) /* Unable to detect charging port */ +#define USBFS_BCD_PORT_ERR (4u) /* Error condition in detection process*/ + + +/* Timeouts for BCD */ +#define USBFS_BCD_TIMEOUT (400u) /* Copied from PBK#163 TIMEOUT (300 ms) */ +#define USBFS_BCD_TDCD_DBNC (10u) /*BCD v1.2: DCD debounce time 10 ms*/ +#define USBFS_BCD_PRIMARY_WAIT (40u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SECONDARY_WAIT (47u) /* Copied from PBK#163 TIMEOUT (40 ms) */ +#define USBFS_BCD_SUSPEND_DISABLE_WAIT (2u) /* Copied from PBK#163 TIMEOUT (2 us) */ + +/* Wait cycles required before clearing SUSPEND_DEL in POWER_CTRL: 2us */ +#define USBFS_WAIT_SUSPEND_DEL_DISABLE (2u) + +/* Wait cycles required for USB regulator stabilization after it is enabled : 50ns */ +#define USBFS_WAIT_VREF_STABILITY (0u) + +#if (CY_PSOC3 || CY_PSOC5LP) +/* Wait cycles required for USB reference restore: 40us */ +#define USBFS_WAIT_VREF_RESTORE (40u) + +/* Wait cycles required for stabilization after register is written : 50ns */ +#define USBFS_WAIT_REG_STABILITY_50NS (0u) +#define USBFS_WAIT_REG_STABILITY_1US (1u) + +/* Wait cycles required after CR0 register write: 1 cycle */ +#define USBFS_WAIT_CR0_REG_STABILITY (1u) + +/* Wait cycles required after PD_PULLUP_N bit is set in PM_USB_CR0: 2us */ +#define USBFS_WAIT_PD_PULLUP_N_ENABLE (2u) +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#if (CY_PSOC4) + #if (USBFS_EP_MANAGEMENT_DMA) + #define USBFS_DMA_DESCR0 (0u) + #define USBFS_DMA_DESCR1 (1u) + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_HALFWORDS_PER_BURST (16u) + #define USBFS_DMA_BURST_BYTES_MASK (USBFS_DMA_BYTES_PER_BURST - 1u) + + #define USBFS_DMA_DESCR0_MASK (0x00u) + #define USBFS_DMA_DESCR1_MASK (0x80u) + #define USBFS_DMA_DESCR_REVERT (0x40u) + #define USBFS_DMA_DESCR_16BITS (0x20u) + #define USBFS_DMA_DESCR_SHIFT (7u) + + #define USBFS_DMA_GET_DESCR_NUM(desrc) + #define USBFS_DMA_GET_BURST_CNT(dmaBurstCnt) \ + (((dmaBurstCnt) > 2u)? ((dmaBurstCnt) - 2u) : 0u) + + #define USBFS_DMA_GET_MAX_ELEM_PER_BURST(dmaLastBurstEl) \ + ((0u != ((dmaLastBurstEl) & USBFS_DMA_DESCR_16BITS)) ? \ + (USBFS_DMA_HALFWORDS_PER_BURST - 1u) : (USBFS_DMA_BYTES_PER_BURST - 1u)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#else + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_BYTES_REPEAT (2u) + + /* BUF_SIZE-BYTES_PER_BURST examples: 0x55 - 32 bytes, 0x44 - 16 bytes, 0x33 - 8 bytes, etc. */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) + + #define USBFS_EP17_SR_MASK (0x7Fu) + #define USBFS_EP8_SR_MASK (0x03u) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC4) */ + +/* DIE ID string descriptor defines */ +#if defined(USBFS_ENABLE_IDSN_STRING) + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +/** +* \addtogroup group_globals +* @{ +*/ +extern uint8 USBFS_initVar; +extern volatile uint8 USBFS_device; +extern volatile uint8 USBFS_transferState; +extern volatile uint8 USBFS_configuration; +extern volatile uint8 USBFS_configurationChanged; +extern volatile uint8 USBFS_deviceStatus; +/** @} globals */ + +/** +* \addtogroup group_hid +* @{ +*/ +/* HID Variables */ +#if defined(USBFS_ENABLE_HID_CLASS) + extern volatile uint8 USBFS_hidProtocol [USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate [USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; +#endif /* (USBFS_ENABLE_HID_CLASS) */ +/** @} hid */ + + +/*************************************** +* Registers +***************************************/ + +/* Common registers for all PSoCs: 3/4/5LP */ +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (*(reg8 *) USBFS_USB__ARB_CFG) + +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (*(reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG +#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN +#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR +#define USBFS_ARB_EP_BASE (*(volatile USBFS_arb_eps_struct CYXDATA *) \ + (USBFS_USB__ARB_EP1_CFG - sizeof(USBFS_arb_ep_struct))) + +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (*(reg8 *) USBFS_USB__ARB_EP2_SR) + +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (*(reg8 *) USBFS_USB__ARB_EP3_SR) + +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (*(reg8 *) USBFS_USB__ARB_EP4_SR) + +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (*(reg8 *) USBFS_USB__ARB_EP5_SR) + +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (*(reg8 *) USBFS_USB__ARB_EP6_SR) + +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (*(reg8 *) USBFS_USB__ARB_EP7_SR) + +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (*(reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (*(reg8 *) USBFS_USB__ARB_EP8_SR) + +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (*(reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (*(reg8 *) USBFS_USB__ARB_INT_SR) + +#define USBFS_ARB_RW1_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA) + +#define USBFS_ARB_RW1_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW1_WA_MSB) +#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR +#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA +#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB +#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA +#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB + +#define USBFS_ARB_RW2_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW2_WA_MSB) + +#define USBFS_ARB_RW3_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW3_WA_MSB) + +#define USBFS_ARB_RW4_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW4_WA_MSB) + +#define USBFS_ARB_RW5_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW5_WA_MSB) + +#define USBFS_ARB_RW6_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW6_WA_MSB) + +#define USBFS_ARB_RW7_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW7_WA_MSB) + +#define USBFS_ARB_RW8_DR_PTR ( (reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ( (reg8 *) USBFS_USB__ARB_RW8_WA_MSB) + +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (*(reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (*(reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (*(reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (*(reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (*(reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (*(reg8 *) USBFS_USB__CR1) + +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (*(reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (*(reg8 *) USBFS_USB__DMA_THRES_MSB) + +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (*(reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (*(reg8 *) USBFS_USB__EP_TYPE) + +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (*(reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (*(reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (*(reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (*(reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (*(reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (*(reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (*(reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (*(reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (*(reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (*(reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 +#define USBFS_EP0_DR_BASE (*(volatile USBFS_ep0_data_struct CYXDATA *) USBFS_USB__EP0_DR0) + +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (*(reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (*(reg8 *) USBFS_USB__OSCLK_DR1) + +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (*(reg8 *) USBFS_USB__SIE_EP_INT_SR) + +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 +#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 +#define USBFS_SIE_EP_BASE (*(volatile USBFS_sie_eps_struct CYXDATA *) \ + (USBFS_USB__SIE_EP1_CNT0 - sizeof(USBFS_sie_ep_struct))) + +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP2_CR0) + +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP3_CR0) + +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP4_CR0) + +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP5_CR0) + +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP6_CR0) + +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP7_CR0) + +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (*(reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (*(reg8 *) USBFS_USB__SIE_EP8_CR0) + +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (*(reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (*(reg8 *) USBFS_USB__SOF1) + +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (*(reg8 *) USBFS_USB__USB_CLK_EN) + +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (*(reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (*(reg8 *) USBFS_USB__USBIO_CR1) + +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (*(reg8 *) USBFS_USB__DYN_RECONFIG) + +#if (CY_PSOC4) + #define USBFS_ARB_RW1_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_RA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_RA16) + #define USBFS_ARB_RW1_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_WA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_WA16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_RW1_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW1_DR16) + #define USBFS_ARB_EP16_BASE (*(volatile USBFS_arb_eps_reg16_struct CYXDATA *) \ + (USBFS_USB__ARB_RW1_WA16 - sizeof(USBFS_arb_ep_reg16_struct))) + + #define USBFS_ARB_RW2_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_DR16) + #define USBFS_ARB_RW2_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_RA16) + #define USBFS_ARB_RW2_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW2_WA16) + + #define USBFS_ARB_RW3_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_DR16) + #define USBFS_ARB_RW3_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_RA16) + #define USBFS_ARB_RW3_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW3_WA16) + + #define USBFS_ARB_RW4_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_DR16) + #define USBFS_ARB_RW4_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_RA16) + #define USBFS_ARB_RW4_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW4_WA16) + + #define USBFS_ARB_RW5_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_DR16) + #define USBFS_ARB_RW5_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_RA16) + #define USBFS_ARB_RW5_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW5_WA16) + + #define USBFS_ARB_RW6_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_DR16) + #define USBFS_ARB_RW6_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_RA16) + #define USBFS_ARB_RW6_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW6_WA16) + + #define USBFS_ARB_RW7_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_DR16) + #define USBFS_ARB_RW7_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_RA16) + #define USBFS_ARB_RW7_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW7_WA16) + + #define USBFS_ARB_RW8_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_DR16) + #define USBFS_ARB_RW8_RA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_RA16) + #define USBFS_ARB_RW8_WA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__ARB_RW8_WA16) + + #define USBFS_OSCLK_DR16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + #define USBFS_OSCLK_DR16_REG (*(reg32 *) USBFS_cy_m0s8_usb__OSCLK_DR16) + + #define USBFS_SOF16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__SOF16) + #define USBFS_SOF16_REG (*(reg32 *) USBFS_cy_m0s8_usb__SOF16) + + #define USBFS_CWA16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__CWA16) + #define USBFS_CWA16_REG (*(reg32 *) USBFS_cy_m0s8_usb__CWA16) + + #define USBFS_DMA_THRES16_PTR ( (reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + #define USBFS_DMA_THRES16_REG (*(reg32 *) USBFS_cy_m0s8_usb__DMA_THRES16) + + #define USBFS_USB_CLK_EN_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + #define USBFS_USB_CLK_EN_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CLK_EN) + + #define USBFS_USBIO_CR2_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (*(reg32 *) USBFS_cy_m0s8_usb__USBIO_CR2) + + #define USBFS_USB_MEM ( (reg32 *) USBFS_cy_m0s8_usb__MEM_DATA0) + + #define USBFS_POWER_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + #define USBFS_POWER_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_POWER_CTRL) + + #define USBFS_CHGDET_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + #define USBFS_CHGDET_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_CHGDET_CTRL) + + #define USBFS_USBIO_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + #define USBFS_USBIO_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_USBIO_CTRL) + + #define USBFS_FLOW_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + #define USBFS_FLOW_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_FLOW_CTRL) + + #define USBFS_LPM_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + #define USBFS_LPM_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_CTRL) + + #define USBFS_LPM_STAT_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + #define USBFS_LPM_STAT_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_LPM_STAT) + + #define USBFS_PHY_CONTROL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + #define USBFS_PHY_CONTROL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_PHY_CONTROL) + + #define USBFS_INTR_SIE_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + #define USBFS_INTR_SIE_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE) + + #define USBFS_INTR_SIE_SET_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + #define USBFS_INTR_SIE_SET_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_SET) + + #define USBFS_INTR_SIE_MASK_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + #define USBFS_INTR_SIE_MASK_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASK) + + #define USBFS_INTR_SIE_MASKED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + #define USBFS_INTR_SIE_MASKED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_SIE_MASKED) + + #define USBFS_INTR_LVL_SEL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + #define USBFS_INTR_LVL_SEL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_LVL_SEL) + + #define USBFS_INTR_CAUSE_HI_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + #define USBFS_INTR_CAUSE_HI_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_HI) + + #define USBFS_INTR_CAUSE_LO_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + #define USBFS_INTR_CAUSE_LO_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_LO) + + #define USBFS_INTR_CAUSE_MED_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + #define USBFS_INTR_CAUSE_MED_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_INTR_CAUSE_MED) + + #define USBFS_DFT_CTRL_REG (*(reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + #define USBFS_DFT_CTRL_PTR ( (reg32 *) USBFS_cy_m0s8_usb__USB_DFT_CTRL) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_POWER_PAD_ENABLE) + /* Vbus power pad pin is hard wired to P13[2] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT13_PS) + #define USBFS_VBUS_VALID (0x04u) + #else + /* Vbus valid pin is hard wired to P0[0] */ + #define USBFS_VBUS_STATUS_REG (*(reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_STATUS_PTR ( (reg32 *) CYREG_GPIO_PRT0_PS) + #define USBFS_VBUS_VALID (0x01u) + #endif + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + #define USBFS_BURSTEND_0_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND0_TR_OUTPUT) + #define USBFS_BURSTEND_1_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND1_TR_OUTPUT) + #define USBFS_BURSTEND_2_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND2_TR_OUTPUT) + #define USBFS_BURSTEND_3_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND3_TR_OUTPUT) + #define USBFS_BURSTEND_4_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND4_TR_OUTPUT) + #define USBFS_BURSTEND_5_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND5_TR_OUTPUT) + #define USBFS_BURSTEND_6_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND6_TR_OUTPUT) + #define USBFS_BURSTEND_7_TR_OUTPUT (USBFS_cy_m0s8_usb__BURSTEND7_TR_OUTPUT) + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* USBFS_PM_USB_CR0 */ + #define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) + #define USBFS_PM_USB_CR0_REG (*(reg8 *) CYREG_PM_USB_CR0) + + /* USBFS_PM_ACT/STBY_CFG */ + #define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_ACT_CFG_REG (*(reg8 *) USBFS_USB__PM_ACT_CFG) + #define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) + #define USBFS_PM_STBY_CFG_REG (*(reg8 *) USBFS_USB__PM_STBY_CFG) + + #if (!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) + #endif /* (!CY_PSOC5LP) */ + + /* USBFS_USB_MEM - USB IP memory buffer */ + #define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_VALID (USBFS_VBUS__MASK) + #else + #define USBFS_VBUS_STATUS_REG (*(reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_STATUS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_VALID (USBFS_Vbus_ps_sts_sts_reg__MASK) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Interrupt source constants +***************************************/ + +#define USBFS_DP_INTC_PRIORITY USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +#if (CY_PSOC4) + #define USBFS_DMA_AUTO_INTR_PRIO (0u) + + #define USBFS_INTR_HI_PRIORITY USBFS_high_int__INTC_PRIOR_NUM + #define USBFS_INTR_HI_VECT_NUM USBFS_high_int__INTC_NUMBER + + #define USBFS_INTR_MED_PRIORITY USBFS_med_int__INTC_PRIOR_NUM + #define USBFS_INTR_MED_VECT_NUM USBFS_med_int__INTC_NUMBER + + #define USBFS_INTR_LO_PRIORITY USBFS_lo_int__INTC_PRIOR_NUM + #define USBFS_INTR_LO_VECT_NUM USBFS_lo_int__INTC_NUMBER + + /* Interrupt sources in USBFS_isrCallbacks[] table */ + #define USBFS_SOF_INTR_NUM (0u) + #define USBFS_BUS_RESET_INT_NUM (1u) + #define USBFS_EP0_INTR_NUM (2u) + #define USBFS_LPM_INTR_NUM (3u) + #define USBFS_ARB_EP_INTR_NUM (4u) + #define USBFS_EP1_INTR_NUM (5u) + #define USBFS_EP2_INTR_NUM (6u) + #define USBFS_EP3_INTR_NUM (7u) + #define USBFS_EP4_INTR_NUM (8u) + #define USBFS_EP5_INTR_NUM (9u) + #define USBFS_EP6_INTR_NUM (10u) + #define USBFS_EP7_INTR_NUM (11u) + #define USBFS_EP8_INTR_NUM (12u) + +#else + #define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM + #define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK + #define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + + #define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM + #define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK + #define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + + #define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM + #define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK + #define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + + #define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM + #define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK + #define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + + #define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM + #define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK + #define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + + #define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM + #define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK + #define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + + #define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM + #define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK + #define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + + #define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM + #define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK + #define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + + #define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM + #define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK + #define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + + #define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM + #define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK + #define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + + #define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM + #define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK + #define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + + /* Set ARB ISR priority 0 to be highest for all EPX ISRs. */ + #define USBFS_ARB_PRIOR (0u) + #define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK + #define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Endpoint 0 offsets (Table 9-2) +***************************************/ +#define USBFS_bmRequestTypeReg USBFS_EP0_DR_BASE.epData[0u] +#define USBFS_bRequestReg USBFS_EP0_DR_BASE.epData[1u] +#define USBFS_wValueLoReg USBFS_EP0_DR_BASE.epData[2u] +#define USBFS_wValueHiReg USBFS_EP0_DR_BASE.epData[3u] +#define USBFS_wIndexLoReg USBFS_EP0_DR_BASE.epData[4u] +#define USBFS_wIndexHiReg USBFS_EP0_DR_BASE.epData[5u] +#define USBFS_wLengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_wLengthHiReg USBFS_EP0_DR_BASE.epData[7u] + +/* Compatibility defines */ +#define USBFS_lengthLoReg USBFS_EP0_DR_BASE.epData[6u] +#define USBFS_lengthHiReg USBFS_EP0_DR_BASE.epData[7u] + + +/*************************************** +* Register Constants +***************************************/ + +#define USBFS_3500MV (3500u) +#if (CY_PSOC4) + #define USBFS_VDDD_MV (CYDEV_VBUS_MV) +#else + #define USBFS_VDDD_MV (CYDEV_VDDD_MV) +#endif /* (CY_PSOC4) */ + + +/* USBFS_USB_CLK */ +#define USBFS_USB_CLK_CSR_CLK_EN_POS (0u) +#define USBFS_USB_CLK_CSR_CLK_EN ((uint8) ((uint8) 0x1u << USBFS_USB_CLK_CSR_CLK_EN_POS)) +#define USBFS_USB_CLK_ENABLE (USBFS_USB_CLK_CSR_CLK_EN) + +/* USBFS_CR0 */ +#define USBFS_CR0_DEVICE_ADDRESS_POS (0u) +#define USBFS_CR0_ENABLE_POS (7u) +#define USBFS_CR0_DEVICE_ADDRESS_MASK ((uint8) ((uint8) 0x7Fu << USBFS_CR0_DEVICE_ADDRESS_POS)) +#define USBFS_CR0_ENABLE ((uint8) ((uint8) 0x01u << USBFS_CR0_ENABLE_POS)) + + +/* USBFS_CR1 */ +#define USBFS_CR1_REG_ENABLE_POS (0u) +#define USBFS_CR1_ENABLE_LOCK_POS (1u) +#define USBFS_CR1_BUS_ACTIVITY_POS (2u) +#define USBFS_CR1_TRIM_OFFSET_MSB_POS (3u) +#define USBFS_CR1_REG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_CR1_REG_ENABLE_POS)) +#define USBFS_CR1_ENABLE_LOCK ((uint8) ((uint8) 0x1u << USBFS_CR1_ENABLE_LOCK_POS)) +#define USBFS_CR1_BUS_ACTIVITY ((uint8) ((uint8) 0x1u << USBFS_CR1_BUS_ACTIVITY_POS)) +#define USBFS_CR1_TRIM_OFFSET_MSB ((uint8) ((uint8) 0x1u << USBFS_CR1_TRIM_OFFSET_MSB_POS)) + +/* USBFS_EPX_CNT */ +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +/* USBFS_USBIO_CR0 */ + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +/* USBFS_USBIO_CR1 */ +#define USBFS_USBIO_CR1_DM0_POS (0u) +#define USBFS_USBIO_CR1_DP0_POS (1u) +#define USBFS_USBIO_CR1_USBPUEN_POS (2u) +#define USBFS_USBIO_CR1_IOMODE_POS (5u) +#define USBFS_USBIO_CR1_DM0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DM0_POS)) +#define USBFS_USBIO_CR1_DP0 ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_DP0_POS)) +#define USBFS_USBIO_CR1_USBPUEN ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_USBPUEN_POS)) +#define USBFS_USBIO_CR1_IOMODE ((uint8) ((uint8) 0x1u << USBFS_USBIO_CR1_IOMODE_POS)) + +/* USBFS_FASTCLK_IMO_CR */ +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +/* USBFS_ARB_EPX_CFG */ +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS (0u) +#define USBFS_ARB_EPX_CFG_DMA_REQ_POS (1u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS_POS (2u) +#define USBFS_ARB_EPX_CFG_RESET_POS (3u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_IN_DATA_RDY_POS)) +#define USBFS_ARB_EPX_CFG_DMA_REQ ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_DMA_REQ_POS)) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_CRC_BYPASS_POS)) +#define USBFS_ARB_EPX_CFG_RESET ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_CFG_RESET_POS)) + +/* USBFS_ARB_EPX_INT / SR */ +#define USBFS_ARB_EPX_INT_IN_BUF_FULL_POS (0u) +#define USBFS_ARB_EPX_INT_DMA_GNT_POS (1u) +#define USBFS_ARB_EPX_INT_BUF_OVER_POS (2u) +#define USBFS_ARB_EPX_INT_BUF_UNDER_POS (3u) +#define USBFS_ARB_EPX_INT_ERR_INT_POS (4u) +#define USBFS_ARB_EPX_INT_IN_BUF_FULL ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_IN_BUF_FULL_POS)) +#define USBFS_ARB_EPX_INT_DMA_GNT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_GNT_POS)) +#define USBFS_ARB_EPX_INT_BUF_OVER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_OVER_POS)) +#define USBFS_ARB_EPX_INT_BUF_UNDER ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_BUF_UNDER_POS)) +#define USBFS_ARB_EPX_INT_ERR_INT ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_ERR_INT_POS)) + +#if (CY_PSOC4) +#define USBFS_ARB_EPX_INT_DMA_TERMIN_POS (5u) +#define USBFS_ARB_EPX_INT_DMA_TERMIN ((uint8) ((uint8) 0x1u << USBFS_ARB_EPX_INT_DMA_TERMIN_POS)) +#endif /* (CY_PSOC4) */ + +/* Common arbiter interrupt sources for all PSoC devices. */ +#define USBFS_ARB_EPX_INT_COMMON (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_DMA_GNT | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT) + +#if (CY_PSOC4) + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON | USBFS_ARB_EPX_INT_DMA_TERMIN) +#else + #define USBFS_ARB_EPX_INT_ALL (USBFS_ARB_EPX_INT_COMMON) +#endif /* (CY_PSOC4) */ + +/* USBFS_ARB_CFG */ +#define USBFS_ARB_CFG_AUTO_MEM_POS (4u) +#define USBFS_ARB_CFG_DMA_CFG_POS (5u) +#define USBFS_ARB_CFG_CFG_CMP_POS (7u) +#define USBFS_ARB_CFG_AUTO_MEM ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_AUTO_MEM_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MASK ((uint8) ((uint8) 0x3u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_NONE ((uint8) ((uint8) 0x0u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_MANUAL ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_DMA_CFG_AUTO ((uint8) ((uint8) 0x2u << USBFS_ARB_CFG_DMA_CFG_POS)) +#define USBFS_ARB_CFG_CFG_CMP ((uint8) ((uint8) 0x1u << USBFS_ARB_CFG_CFG_CMP_POS)) + +/* USBFS_DYN_RECONFIG */ +#define USBFS_DYN_RECONFIG_EP_SHIFT (1u) +#define USBFS_DYN_RECONFIG_ENABLE_POS (0u) +#define USBFS_DYN_RECONFIG_EPNO_POS (1u) +#define USBFS_DYN_RECONFIG_RDY_STS_POS (4u) +#define USBFS_DYN_RECONFIG_ENABLE ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_ENABLE_POS)) +#define USBFS_DYN_RECONFIG_EPNO_MASK ((uint8) ((uint8) 0x7u << USBFS_DYN_RECONFIG_EPNO_POS)) +#define USBFS_DYN_RECONFIG_RDY_STS ((uint8) ((uint8) 0x1u << USBFS_DYN_RECONFIG_RDY_STS_POS)) + +/* USBFS_ARB_INT */ +#define USBFS_ARB_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_ARB_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_ARB_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_ARB_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_ARB_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_ARB_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_ARB_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_ARB_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_ARB_INT_EP1_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP1_INTR_POS)) +#define USBFS_ARB_INT_EP2_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP2_INTR_POS)) +#define USBFS_ARB_INT_EP3_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP3_INTR_POS)) +#define USBFS_ARB_INT_EP4_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP4_INTR_POS)) +#define USBFS_ARB_INT_EP5_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP5_INTR_POS)) +#define USBFS_ARB_INT_EP6_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP6_INTR_POS)) +#define USBFS_ARB_INT_EP7_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP7_INTR_POS)) +#define USBFS_ARB_INT_EP8_INTR ((uint8) ((uint8) 0x1u << USBFS_ARB_INT_EP8_INTR_POS)) + +/* USBFS_SIE_INT */ +#define USBFS_SIE_INT_EP1_INTR_POS (0u) /* [0] Interrupt for USB EP1 */ +#define USBFS_SIE_INT_EP2_INTR_POS (1u) /* [1] Interrupt for USB EP2 */ +#define USBFS_SIE_INT_EP3_INTR_POS (2u) /* [2] Interrupt for USB EP3 */ +#define USBFS_SIE_INT_EP4_INTR_POS (3u) /* [3] Interrupt for USB EP4 */ +#define USBFS_SIE_INT_EP5_INTR_POS (4u) /* [4] Interrupt for USB EP5 */ +#define USBFS_SIE_INT_EP6_INTR_POS (5u) /* [5] Interrupt for USB EP6 */ +#define USBFS_SIE_INT_EP7_INTR_POS (6u) /* [6] Interrupt for USB EP7 */ +#define USBFS_SIE_INT_EP8_INTR_POS (7u) /* [7] Interrupt for USB EP8 */ +#define USBFS_SIE_INT_EP1_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP1_INTR_POS)) +#define USBFS_SIE_INT_EP2_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP2_INTR_POS)) +#define USBFS_SIE_INT_EP3_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP3_INTR_POS)) +#define USBFS_SIE_INT_EP4_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP4_INTR_POS)) +#define USBFS_SIE_INT_EP5_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP5_INTR_POS)) +#define USBFS_SIE_INT_EP6_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP6_INTR_POS)) +#define USBFS_SIE_INT_EP7_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP7_INTR_POS)) +#define USBFS_SIE_INT_EP8_INTR ((uint8) ((uint8) 0x01u << USBFS_SIE_INT_EP8_INTR_POS)) + +#if (CY_PSOC4) + /* USBFS_POWER_CTRL_REG */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_POS (0u) /* [0] */ + #define USBFS_POWER_CTRL_SUSPEND_POS (2u) /* [1] */ + #define USBFS_POWER_CTRL_SUSPEND_DEL_POS (3u) /* [3] */ + #define USBFS_POWER_CTRL_ISOLATE_POS (4u) /* [4] */ + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_POS (5u) /* [5] */ + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS (25u) /* [25] */ + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS (26u) /* [26] */ + #define USBFS_POWER_CTRL_ENABLE_RCVR_POS (27u) /* [27] */ + #define USBFS_POWER_CTRL_ENABLE_DPO_POS (28u) /* [28] */ + #define USBFS_POWER_CTRL_ENABLE_DMO_POS (29u) /* [29] */ + #define USBFS_POWER_CTRL_ENABLE_CHGDET_POS (30u) /* [30] */ + #define USBFS_POWER_CTRL_ENABLE_POS (31u) /* [31] */ + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_0 ((uint32) 0x00u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_1 ((uint32) 0x01u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO ((uint32) 0x02u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY ((uint32) 0x03u << USBFS_POWER_CTRL_VBUS_VALID_OVR_POS) + #define USBFS_POWER_CTRL_SUSPEND ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_POS) + #define USBFS_POWER_CTRL_SUSPEND_DEL ((uint32) 0x01u << USBFS_POWER_CTRL_SUSPEND_DEL_POS) + #define USBFS_POWER_CTRL_ISOLATE ((uint32) 0x01u << USBFS_POWER_CTRL_ISOLATE_POS) + #define USBFS_POWER_CTRL_CHDET_PWR_CTL_MASK ((uint32) 0x03u << USBFS_POWER_CTRL_CHDET_PWR_CTL_POS) + #define USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DM_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN_POS) + #define USBFS_POWER_CTRL_ENABLE_RCVR ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_RCVR_POS) + #define USBFS_POWER_CTRL_ENABLE_DPO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DPO_POS) + #define USBFS_POWER_CTRL_ENABLE_DMO ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_DMO_POS) + #define USBFS_POWER_CTRL_ENABLE_CHGDET ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_CHGDET_POS) + #define USBFS_POWER_CTRL_ENABLE ((uint32) 0x01u << USBFS_POWER_CTRL_ENABLE_POS) + + /* USBFS_CHGDET_CTRL_REG */ + #define USBFS_CHGDET_CTRL_COMP_DP_POS (0u) /* [0] */ + #define USBFS_CHGDET_CTRL_COMP_DM_POS (1u) /* [1] */ + #define USBFS_CHGDET_CTRL_COMP_EN_POS (2u) /* [2] */ + #define USBFS_CHGDET_CTRL_REF_DP_POS (3u) /* [3] */ + #define USBFS_CHGDET_CTRL_REF_DM_POS (4u) /* [4] */ + #define USBFS_CHGDET_CTRL_REF_EN_POS (5u) /* [5] */ + #define USBFS_CHGDET_CTRL_DCD_SRC_EN_POS (6u) /* [6] */ + #define USBFS_CHGDET_CTRL_ADFT_CTRL_POS (12u) /* [12] */ + #define USBFS_CHGDET_CTRL_COMP_OUT_POS (31u) /* [31] */ + #define USBFS_CHGDET_CTRL_COMP_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DP_POS) + #define USBFS_CHGDET_CTRL_COMP_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_DM_POS) + #define USBFS_CHGDET_CTRL_COMP_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_EN_POS) + #define USBFS_CHGDET_CTRL_REF_DP ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DP_POS) + #define USBFS_CHGDET_CTRL_REF_DM ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_DM_POS) + #define USBFS_CHGDET_CTRL_REF_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_REF_EN_POS) + #define USBFS_CHGDET_CTRL_DCD_SRC_EN ((uint32) 0x01u << USBFS_CHGDET_CTRL_DCD_SRC_EN_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_MASK ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_NORMAL ((uint32) 0x00u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_VBG ((uint32) 0x01u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_DONTUSE ((uint32) 0x02u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_ADFT_CTRL_ADFTIN ((uint32) 0x03u << USBFS_CHGDET_CTRL_ADFT_CTRL_POS) + #define USBFS_CHGDET_CTRL_COMP_OUT ((uint32) 0x01u << USBFS_CHGDET_CTRL_COMP_OUT_POS) + + /* USBFS_LPM_CTRL */ + #define USBFS_LPM_CTRL_LPM_EN_POS (0u) + #define USBFS_LPM_CTRL_LPM_ACK_RESP_POS (1u) + #define USBFS_LPM_CTRL_NYET_EN_POS (2u) + #define USBFS_LPM_CTRL_SUB_RESP_POS (4u) + #define USBFS_LPM_CTRL_LPM_EN ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_EN_POS) + #define USBFS_LPM_CTRL_LPM_ACK_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_NYET_EN ((uint32) 0x01u << USBFS_LPM_CTRL_NYET_EN_POS) + #define USBFS_LPM_CTRL_ACK_NYET_MASK ((uint32) 0x03u << USBFS_LPM_CTRL_LPM_ACK_RESP_POS) + #define USBFS_LPM_CTRL_SUB_RESP ((uint32) 0x01u << USBFS_LPM_CTRL_SUB_RESP_POS) + + #define USBFS_LPM_STAT_LPM_BESL_POS (0u) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS (4u) + #define USBFS_LPM_STAT_LPM_BESL_MASK ((uint32) 0x0Fu << USBFS_LPM_STAT_LPM_BESL_POS) + #define USBFS_LPM_STAT_LPM_REMOTE_WAKE ((uint32) 0x01u << USBFS_LPM_STAT_LPM_REMOTE_WAKE_POS) + + /* USBFS_INTR_SIE */ + #define USBFS_INTR_SIE_SOF_INTR_POS (0u) /* [0] Interrupt for USB SOF */ + #define USBFS_INTR_SIE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt for BUS RESET */ + #define USBFS_INTR_SIE_EP0_INTR_POS (2u) /* [2] Interrupt for EP0 */ + #define USBFS_INTR_SIE_LPM_INTR_POS (3u) /* [3] Interrupt for LPM */ + #define USBFS_INTR_SIE_RESUME_INTR_POS (4u) /* [4] Interrupt for RESUME (not used by component) */ + #define USBFS_INTR_SIE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_SIE_SOF_INTR_POS) + #define USBFS_INTR_SIE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_SIE_BUS_RESET_INTR_POS) + #define USBFS_INTR_SIE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_SIE_EP0_INTR_POS) + #define USBFS_INTR_SIE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_SIE_LPM_INTR_POS) + #define USBFS_INTR_SIE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_SIE_RESUME_INTR_POS) + + /* USBFS_INTR_CAUSE_LO, MED and HI */ + #define USBFS_INTR_CAUSE_SOF_INTR_POS (0u) /* [0] Interrupt status for USB SOF */ + #define USBFS_INTR_CAUSE_BUS_RESET_INTR_POS (1u) /* [1] Interrupt status for USB BUS RSET */ + #define USBFS_INTR_CAUSE_EP0_INTR_POS (2u) /* [2] Interrupt status for USB EP0 */ + #define USBFS_INTR_CAUSE_LPM_INTR_POS (3u) /* [3] Interrupt status for USB LPM */ + #define USBFS_INTR_CAUSE_RESUME_INTR_POS (4u) /* [4] Interrupt status for USB RESUME */ + #define USBFS_INTR_CAUSE_ARB_INTR_POS (7u) /* [7] Interrupt status for USB ARB */ + #define USBFS_INTR_CAUSE_EP1_INTR_POS (8u) /* [8] Interrupt status for USB EP1 */ + #define USBFS_INTR_CAUSE_EP2_INTR_POS (9u) /* [9] Interrupt status for USB EP2 */ + #define USBFS_INTR_CAUSE_EP3_INTR_POS (10u) /* [10] Interrupt status for USB EP3 */ + #define USBFS_INTR_CAUSE_EP4_INTR_POS (11u) /* [11] Interrupt status for USB EP4 */ + #define USBFS_INTR_CAUSE_EP5_INTR_POS (12u) /* [12] Interrupt status for USB EP5 */ + #define USBFS_INTR_CAUSE_EP6_INTR_POS (13u) /* [13] Interrupt status for USB EP6 */ + #define USBFS_INTR_CAUSE_EP7_INTR_POS (14u) /* [14] Interrupt status for USB EP7 */ + #define USBFS_INTR_CAUSE_EP8_INTR_POS (15u) /* [15] Interrupt status for USB EP8 */ + #define USBFS_INTR_CAUSE_SOF_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_SOF_INTR_POS) + #define USBFS_INTR_CAUSE_BUS_RESET_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_BUS_RESET_INTR_POS) + #define USBFS_INTR_CAUSE_EP0_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP0_INTR_POS) + #define USBFS_INTR_CAUSE_LPM_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_LPM_INTR_POS) + #define USBFS_INTR_CAUSE_RESUME_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_RESUME_INTR_POS) + #define USBFS_INTR_CAUSE_ARB_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_ARB_INTR_POS) + #define USBFS_INTR_CAUSE_EP1_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP1_INTR_POS) + #define USBFS_INTR_CAUSE_EP2_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP2_INTR_POS) + #define USBFS_INTR_CAUSE_EP3_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP3_INTR_POS) + #define USBFS_INTR_CAUSE_EP4_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP4_INTR_POS) + #define USBFS_INTR_CAUSE_EP5_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP5_INTR_POS) + #define USBFS_INTR_CAUSE_EP6_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP6_INTR_POS) + #define USBFS_INTR_CAUSE_EP7_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP7_INTR_POS) + #define USBFS_INTR_CAUSE_EP8_INTR ((uint32) 0x01u << USBFS_INTR_CAUSE_EP8_INTR_POS) + + #define USBFS_INTR_CAUSE_CTRL_INTR_MASK (USBFS_INTR_CAUSE_SOF_INTR | \ + USBFS_INTR_CAUSE_BUS_RESET_INTR | \ + USBFS_INTR_CAUSE_EP0_INTR | \ + USBFS_INTR_CAUSE_LPM_INTR) + + #define USBFS_INTR_CAUSE_EP1_8_INTR_MASK (USBFS_INTR_CAUSE_EP1_INTR | \ + USBFS_INTR_CAUSE_EP2_INTR | \ + USBFS_INTR_CAUSE_EP3_INTR | \ + USBFS_INTR_CAUSE_EP4_INTR | \ + USBFS_INTR_CAUSE_EP5_INTR | \ + USBFS_INTR_CAUSE_EP6_INTR | \ + USBFS_INTR_CAUSE_EP7_INTR | \ + USBFS_INTR_CAUSE_EP8_INTR) + + #define USBFS_INTR_CAUSE_EP_INTR_SHIFT (USBFS_INTR_CAUSE_ARB_INTR_POS - \ + (USBFS_INTR_CAUSE_LPM_INTR_POS + 1u)) + #define USBFS_INTR_CAUSE_SRC_COUNT (13u) + + #define USBFS_CHGDET_CTRL_PRIMARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DM | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DP) + + #define USBFS_CHGDET_CTRL_SECONDARY (USBFS_CHGDET_CTRL_COMP_EN | \ + USBFS_CHGDET_CTRL_COMP_DP | \ + USBFS_CHGDET_CTRL_REF_EN | \ + USBFS_CHGDET_CTRL_REF_DM) + + #define USBFS_CHGDET_CTRL_DEFAULT (0x00000900u) + + +#else /* (CY_PSOC3 || CY_PSOC5LP) */ + #define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK + #define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK + #define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + + #define USBFS_PM_USB_CR0_REF_EN (0x01u) + #define USBFS_PM_USB_CR0_PD_N (0x02u) + #define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) +#endif /* (CY_PSOC4) */ + + +/*************************************** +* Macros Definitions +***************************************/ + +#if (CY_PSOC4) + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ \ + USBFS_INTR_SIE_REG = (uint32) (intMask); \ + }while(0) +#else + #define USBFS_ClearSieInterruptSource(intMask) \ + do{ /* Does nothing. */ }while(0) +#endif /* (CY_PSOC4) */ + +#define USBFS_ClearSieEpInterruptSource(intMask) \ + do{ \ + USBFS_SIE_EP_INT_SR_REG = (uint8) (intMask); \ + }while(0) + +#define USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_IN) : (USBFS_MODE_ACK_IN)) + +#define USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType) (((epType) == USBFS_EP_TYPE_ISOC) ? \ + (USBFS_MODE_ISO_OUT) : (USBFS_MODE_ACK_OUT)) + +#define USBFS_GET_EP_TYPE(epNumber) (USBFS_EP[epNumber].attrib & USBFS_EP_TYPE_MASK) + +#define USBFS_GET_UINT16(hi, low) (((uint16) ((uint16) (hi) << 8u)) | ((uint16) (low) & 0xFFu)) + + +/*************************************** +* Initialization Register Settings +***************************************/ + +/* Clear device address and enable USB IP respond to USB traffic. */ +#define USBFS_DEFUALT_CR0 (USBFS_CR0_ENABLE) + +/* Arbiter configuration depends on memory management mode. */ +#define USBFS_DEFAULT_ARB_CFG ((USBFS_EP_MANAGEMENT_MANUAL) ? (USBFS_ARB_CFG_DMA_CFG_NONE) : \ + ((USBFS_EP_MANAGEMENT_DMA_MANUAL) ? \ + (USBFS_ARB_CFG_DMA_CFG_MANUAL) : \ + (USBFS_ARB_CFG_AUTO_MEM | USBFS_ARB_CFG_DMA_CFG_AUTO))) + +/* Enable arbiter interrupt for active endpoints only */ +#define USBFS_DEFAULT_ARB_INT_EN \ + ((uint8) ((uint8) USBFS_DMA1_ACTIVE << USBFS_ARB_INT_EP1_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA2_ACTIVE << USBFS_ARB_INT_EP2_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA3_ACTIVE << USBFS_ARB_INT_EP3_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA4_ACTIVE << USBFS_ARB_INT_EP4_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA5_ACTIVE << USBFS_ARB_INT_EP5_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA6_ACTIVE << USBFS_ARB_INT_EP6_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA7_ACTIVE << USBFS_ARB_INT_EP7_INTR_POS) | \ + (uint8) ((uint8) USBFS_DMA8_ACTIVE << USBFS_ARB_INT_EP8_INTR_POS)) + +/* Enable all SIE endpoints interrupts */ +#define USBFS_DEFAULT_SIE_EP_INT_EN (USBFS_SIE_INT_EP1_INTR | \ + USBFS_SIE_INT_EP2_INTR | \ + USBFS_SIE_INT_EP3_INTR | \ + USBFS_SIE_INT_EP4_INTR | \ + USBFS_SIE_INT_EP5_INTR | \ + USBFS_SIE_INT_EP6_INTR | \ + USBFS_SIE_INT_EP7_INTR | \ + USBFS_SIE_INT_EP8_INTR) + +#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \ + USBFS_ARB_EPX_CFG_CRC_BYPASS) + +/* Default EP arbiter interrupt source register */ +#define USBFS_ARB_EPX_INT_COMMON_MASK (USBFS_ARB_EPX_INT_IN_BUF_FULL | \ + USBFS_ARB_EPX_INT_BUF_OVER | \ + USBFS_ARB_EPX_INT_BUF_UNDER | \ + USBFS_ARB_EPX_INT_ERR_INT | \ + (USBFS_EP_MANAGEMENT_DMA_MANUAL ? USBFS_ARB_EPX_INT_DMA_GNT : 0u)) + +#define USBFS_CLEAR_REG (0u) + +#if (CY_PSOC4) + /* Set USB lock option when IMO is locked to USB traffic. */ + #define USBFS_DEFUALT_CR1 ((0u != CySysClkImoGetUsbLock()) ? (USBFS_CR1_ENABLE_LOCK) : (0u)) + + /* Recommended value is increased from 3 to 10 due to suppress glitch on + * RSE0 with USB2.0 hubs (LF CLK = 32kHz equal to 350us). */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) + + /* Select VBUS sources as: valid, PHY of GPIO, and clears isolate bit. */ + /* Application level must ensure that VBUS is valid valid to use. */ + #define USBFS_DEFAULT_POWER_CTRL_VBUS (USBFS_POWER_CTRL_ENABLE_VBUS_PULLDOWN | \ + ((!USBFS_VBUS_MONITORING_ENABLE) ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_1) : \ + (USBFS_VBUS_POWER_PAD_ENABLE ? \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_PHY) : \ + (USBFS_POWER_CTRL_VBUS_VALID_OVR_GPIO)))) + /* Enable USB IP. */ + #define USBFS_DEFAULT_POWER_CTRL_PHY (USBFS_POWER_CTRL_SUSPEND | \ + USBFS_POWER_CTRL_SUSPEND_DEL | \ + USBFS_POWER_CTRL_ENABLE_RCVR | \ + USBFS_POWER_CTRL_ENABLE_DPO | \ + USBFS_POWER_CTRL_ENABLE_DMO | \ + USBFS_POWER_CTRL_ENABLE) + + /* Assign interrupt between levels lo, med, hi. */ + #define USBFS_DEFAULT_INTR_LVL_SEL ((uint32) (USBFS_INTR_LVL_SEL)) + + /* Enable interrupt source in the INTR_SIE. The SOF is always disabled and EP0 is enabled. */ + #define USBFS_DEFAULT_INTR_SIE_MASK \ + ((uint32) ((uint32) USBFS_BUS_RESET_ISR_ACTIVE << USBFS_INTR_SIE_BUS_RESET_INTR_POS) | \ + (uint32) ((uint32) USBFS_SOF_ISR_ACTIVE << USBFS_INTR_SIE_SOF_INTR_POS) | \ + (uint32) ((uint32) USBFS_LPM_ACTIVE << USBFS_INTR_SIE_LPM_INTR_POS) | \ + (uint32) ((uint32) USBFS_INTR_SIE_EP0_INTR)) + + /* Arbiter interrupt sources */ + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK | \ + (USBFS_EP_MANAGEMENT_DMA_AUTO ? USBFS_ARB_EPX_INT_DMA_TERMIN : 0u)) + + /* Common DMA configuration */ + #define USBFS_DMA_COMMON_CFG (CYDMA_PULSE | CYDMA_ENTIRE_DESCRIPTOR | \ + CYDMA_NON_PREEMPTABLE) + + +#else + #define USBFS_ARB_EPX_INT_MASK (USBFS_ARB_EPX_INT_COMMON_MASK) + + #define USBFS_DEFUALT_CR1 (USBFS_CR1_ENABLE_LOCK) + + /* Recommended value is 3 for LF CLK = 100kHz equal to 100us. */ + #define USBFS_DEFUALT_BUS_RST_CNT (10u) +#endif /* (CY_PSOC4) */ + +/* +* \addtogroup group_deprecated +* @{ +*/ + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +/* Renamed type definitions */ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* __C51__ */ +#define USBFS_NULL NULL +/** @} deprecated */ +/* Renamed structure fields */ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable */ +#define CurrentTD USBFS_currentTD +#define USBFS_interfaceSetting_last USBFS_interfaceSettingLast + +/* Renamed global constants */ +#define USBFS_DWR_VDDD_OPERATION (USBFS_DWR_POWER_OPERATION) + +/* Renamed functions */ +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + +/* Replace with register access. */ +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + +/* Rename VBUS monitoring registers. */ +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_VBUS_MONITORING_ENABLE) + #if (USBFS_VBUS_MONITORING_INTERNAL) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (*(reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (*(reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG) + #define USBFS_VBUS_MASK (0x01u) + #endif /* (USBFS_VBUS_MONITORING_INTERNAL) */ + #endif /*(USBFS_VBUS_MONITORING_ENABLE) */ + + /* Pointer DIE structure in flash (8 bytes): Y and X location, wafer, lot msb, lot lsb, + * work week, fab/year, minor. */ + #define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_DMA1_ACTIVE) + #define USBFS_ep1_TD_TERMOUT_EN (USBFS_ep1__TD_TERMOUT_EN) + #else + #define USBFS_ep1_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + #define USBFS_ep2_TD_TERMOUT_EN (USBFS_ep2__TD_TERMOUT_EN) + #else + #define USBFS_ep2_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + #define USBFS_ep3_TD_TERMOUT_EN (USBFS_ep3__TD_TERMOUT_EN) + #else + #define USBFS_ep3_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + #define USBFS_ep4_TD_TERMOUT_EN (USBFS_ep4__TD_TERMOUT_EN) + #else + #define USBFS_ep4_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + #define USBFS_ep5_TD_TERMOUT_EN (USBFS_ep5__TD_TERMOUT_EN) + #else + #define USBFS_ep5_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + #define USBFS_ep6_TD_TERMOUT_EN (USBFS_ep6__TD_TERMOUT_EN) + #else + #define USBFS_ep6_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + #define USBFS_ep7_TD_TERMOUT_EN (USBFS_ep7__TD_TERMOUT_EN) + #else + #define USBFS_ep7_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + #define USBFS_ep8_TD_TERMOUT_EN (USBFS_ep8__TD_TERMOUT_EN) + #else + #define USBFS_ep8_TD_TERMOUT_EN (0u) + #endif /* (USBFS_DMA8_ACTIVE) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +/* Rename USB IP registers. */ +#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR + +#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR +#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR +#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR + +#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR +#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR +#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR + +#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR +#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR +#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR + +#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR +#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR +#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR + +#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR +#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR +#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR + +#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR +#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR +#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR + +#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR +#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR +#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR + +#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR +#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR +#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR + +#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR +#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR + +#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR +#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR +#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR +#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR +#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR + +#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR +#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR +#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR +#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR +#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR + +#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR +#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR +#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR +#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR +#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR + +#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR +#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR +#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR +#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR +#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR + +#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR +#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR +#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR +#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR +#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR + +#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR +#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR +#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR +#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR +#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR + +#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR +#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR +#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR +#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR +#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR + +#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR +#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR +#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR +#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR +#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR + +#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR +#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR +#define USBFS_CR0 USBFS_CR0_PTR +#define USBFS_CR1 USBFS_CR1_PTR +#define USBFS_CWA USBFS_CWA_PTR +#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR + +#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR +#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR + +#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR +#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR + +#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR +#define USBFS_EP0_CR USBFS_EP0_CR_PTR +#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR +#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR +#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR +#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR +#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR +#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR +#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR +#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR + +#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR +#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR + +#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR +#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR + +#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR +#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR + +#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR +#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR +#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR + +#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR +#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR +#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR + +#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR +#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR +#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR + +#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR +#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR +#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR + +#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR +#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR +#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR + +#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR +#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR +#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR + +#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR +#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR +#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR + +#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR +#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR +#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR + +#define USBFS_SOF0 USBFS_SOF0_PTR +#define USBFS_SOF1 USBFS_SOF1_PTR + +#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR + +#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR +#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR +#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR + +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (*(reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (*(reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (*(reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK + +#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) +#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) +#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) +#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) +#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) +#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) +#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) +#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) + +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) + +#define USBFS_ARB_EPX_INT_EN_ALL USBFS_ARB_EPX_INT_ALL + +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) + +#define USBFS_BUS_RST_COUNT USBFS_DEFUALT_BUS_RST_CNT + +#define USBFS_ARB_INT_MASK USBFS_DEFAULT_ARB_INT_EN + +#if (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* CY_PSOC3 interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif (CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* CY_PSOC5LP interrupt registers */ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* CYDEV_CHIP_DIE_EXPECT */ + + +#endif /* (CY_USBFS_USBFS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c new file mode 100644 index 0000000..57ad545 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: USBFS_Dm.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dm.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dm_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Write +*******************************************************************************/ +void USBFS_Dm_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); + USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetDriveMode +*******************************************************************************/ +void USBFS_Dm_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dm_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_Read +*******************************************************************************/ +uint8 USBFS_Dm_Read(void) +{ + return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred USBFS_Dm_Read() API because the +* USBFS_Dm_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ReadDataReg +*******************************************************************************/ +uint8 USBFS_Dm_ReadDataReg(void) +{ + return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(USBFS_Dm_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dm_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use USBFS_Dm_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - USBFS_Dm_0_INTR (First pin in the list) + * - USBFS_Dm_1_INTR (Second pin in the list) + * - ... + * - USBFS_Dm_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_SetInterruptMode + *******************************************************************************/ + void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & USBFS_Dm_0_INTR) != 0u) + { + USBFS_Dm_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: USBFS_Dm_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet USBFS_Dm_SUT.c usage_USBFS_Dm_ClearInterrupt + *******************************************************************************/ + uint8 USBFS_Dm_ClearInterrupt(void) + { + return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h new file mode 100644 index 0000000..f8ad500 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */ +#define CY_PINS_USBFS_Dm_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dm_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_Dm_Write(uint8 value); +void USBFS_Dm_SetDriveMode(uint8 mode); +uint8 USBFS_Dm_ReadDataReg(void); +uint8 USBFS_Dm_Read(void); +void USBFS_Dm_SetInterruptMode(uint16 position, uint16 mode); +uint8 USBFS_Dm_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the USBFS_Dm_SetDriveMode() function. + * @{ + */ + #define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP + #define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN + #define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO + #define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI + #define USBFS_Dm_DM_STRONG PIN_DM_STRONG + #define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define USBFS_Dm_MASK USBFS_Dm__MASK +#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT +#define USBFS_Dm_WIDTH 1u + +/* Interrupt constants */ +#if defined(USBFS_Dm__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in USBFS_Dm_SetInterruptMode() function. + * @{ + */ + #define USBFS_Dm_INTR_NONE (uint16)(0x0000u) + #define USBFS_Dm_INTR_RISING (uint16)(0x0001u) + #define USBFS_Dm_INTR_FALLING (uint16)(0x0002u) + #define USBFS_Dm_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define USBFS_Dm_INTR_MASK (0x01u) +#endif /* (USBFS_Dm__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dm_PS (* (reg8 *) USBFS_Dm__PS) +/* Data Register */ +#define USBFS_Dm_DR (* (reg8 *) USBFS_Dm__DR) +/* Port Number */ +#define USBFS_Dm_PRT_NUM (* (reg8 *) USBFS_Dm__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dm_AG (* (reg8 *) USBFS_Dm__AG) +/* Analog MUX bux enable */ +#define USBFS_Dm_AMUX (* (reg8 *) USBFS_Dm__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dm_BIE (* (reg8 *) USBFS_Dm__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dm_BIT_MASK (* (reg8 *) USBFS_Dm__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dm_BYP (* (reg8 *) USBFS_Dm__BYP) +/* Port wide control signals */ +#define USBFS_Dm_CTL (* (reg8 *) USBFS_Dm__CTL) +/* Drive Modes */ +#define USBFS_Dm_DM0 (* (reg8 *) USBFS_Dm__DM0) +#define USBFS_Dm_DM1 (* (reg8 *) USBFS_Dm__DM1) +#define USBFS_Dm_DM2 (* (reg8 *) USBFS_Dm__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dm_INP_DIS (* (reg8 *) USBFS_Dm__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dm_LCD_COM_SEG (* (reg8 *) USBFS_Dm__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dm_LCD_EN (* (reg8 *) USBFS_Dm__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dm_SLW (* (reg8 *) USBFS_Dm__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) +#define USBFS_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) +#define USBFS_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(USBFS_Dm__SIO_CFG) + #define USBFS_Dm_SIO_HYST_EN (* (reg8 *) USBFS_Dm__SIO_HYST_EN) + #define USBFS_Dm_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dm__SIO_REG_HIFREQ) + #define USBFS_Dm_SIO_CFG (* (reg8 *) USBFS_Dm__SIO_CFG) + #define USBFS_Dm_SIO_DIFF (* (reg8 *) USBFS_Dm__SIO_DIFF) +#endif /* (USBFS_Dm__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(USBFS_Dm__INTSTAT) + #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) + #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) + + #define USBFS_Dm_0_INTTYPE_REG (* (reg8 *) USBFS_Dm__0__INTTYPE) +#endif /* (USBFS_Dm__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dm_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h new file mode 100644 index 0000000..1540de9 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_ALIASES_H) /* Pins USBFS_Dm_ALIASES_H */ +#define CY_PINS_USBFS_Dm_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dm_0 (USBFS_Dm__0__PC) +#define USBFS_Dm_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dm__0__SHIFT)) + +#define USBFS_Dm_INTR_ALL ((uint16)(USBFS_Dm_0_INTR)) + +#endif /* End Pins USBFS_Dm_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c new file mode 100644 index 0000000..e48e0dc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: USBFS_Dp.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dp.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dp_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Write +*******************************************************************************/ +void USBFS_Dp_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); + USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetDriveMode +*******************************************************************************/ +void USBFS_Dp_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dp_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_Read +*******************************************************************************/ +uint8 USBFS_Dp_Read(void) +{ + return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred USBFS_Dp_Read() API because the +* USBFS_Dp_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ReadDataReg +*******************************************************************************/ +uint8 USBFS_Dp_ReadDataReg(void) +{ + return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(USBFS_Dp_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dp_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use USBFS_Dp_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - USBFS_Dp_0_INTR (First pin in the list) + * - USBFS_Dp_1_INTR (Second pin in the list) + * - ... + * - USBFS_Dp_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_SetInterruptMode + *******************************************************************************/ + void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & USBFS_Dp_0_INTR) != 0u) + { + USBFS_Dp_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet USBFS_Dp_SUT.c usage_USBFS_Dp_ClearInterrupt + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) + { + return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h new file mode 100644 index 0000000..ca2c627 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ +#define CY_PINS_USBFS_Dp_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dp_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void USBFS_Dp_Write(uint8 value); +void USBFS_Dp_SetDriveMode(uint8 mode); +uint8 USBFS_Dp_ReadDataReg(void); +uint8 USBFS_Dp_Read(void); +void USBFS_Dp_SetInterruptMode(uint16 position, uint16 mode); +uint8 USBFS_Dp_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the USBFS_Dp_SetDriveMode() function. + * @{ + */ + #define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP + #define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN + #define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO + #define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI + #define USBFS_Dp_DM_STRONG PIN_DM_STRONG + #define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define USBFS_Dp_MASK USBFS_Dp__MASK +#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT +#define USBFS_Dp_WIDTH 1u + +/* Interrupt constants */ +#if defined(USBFS_Dp__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in USBFS_Dp_SetInterruptMode() function. + * @{ + */ + #define USBFS_Dp_INTR_NONE (uint16)(0x0000u) + #define USBFS_Dp_INTR_RISING (uint16)(0x0001u) + #define USBFS_Dp_INTR_FALLING (uint16)(0x0002u) + #define USBFS_Dp_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define USBFS_Dp_INTR_MASK (0x01u) +#endif /* (USBFS_Dp__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) +/* Data Register */ +#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) +/* Port Number */ +#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) +/* Analog MUX bux enable */ +#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) +/* Port wide control signals */ +#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) +/* Drive Modes */ +#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) +#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) +#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) +#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) +#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_HYST_EN (* (reg8 *) USBFS_Dp__SIO_HYST_EN) + #define USBFS_Dp_SIO_REG_HIFREQ (* (reg8 *) USBFS_Dp__SIO_REG_HIFREQ) + #define USBFS_Dp_SIO_CFG (* (reg8 *) USBFS_Dp__SIO_CFG) + #define USBFS_Dp_SIO_DIFF (* (reg8 *) USBFS_Dp__SIO_DIFF) +#endif /* (USBFS_Dp__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(USBFS_Dp__INTSTAT) + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + + #define USBFS_Dp_0_INTTYPE_REG (* (reg8 *) USBFS_Dp__0__INTTYPE) +#endif /* (USBFS_Dp__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dp_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h new file mode 100644 index 0000000..ca74cce --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ +#define CY_PINS_USBFS_Dp_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dp_0 (USBFS_Dp__0__PC) +#define USBFS_Dp_0_INTR ((uint16)((uint16)0x0001u << USBFS_Dp__0__SHIFT)) + +#define USBFS_Dp_INTR_ALL ((uint16)(USBFS_Dp_0_INTR)) + +#endif /* End Pins USBFS_Dp_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c new file mode 100644 index 0000000..9e0ecd3 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.c @@ -0,0 +1,380 @@ +/***************************************************************************//** +* \file USBFS_audio.c +* \version 3.10 +* +* \brief +* This file contains the USB AUDIO Class request handler. +* +* Related Document: +* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_audio.h" +#include "USBFS_pvt.h" + + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if !defined(USER_SUPPLIED_AUDIO_HANDLER) + +/*************************************** +* AUDIO Variables +***************************************/ + +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + /** Contains the current audio sample frequency. It is set by the host using a SET_CUR request to the endpoint.*/ + volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; + /** Used as a flag for the user code, to inform it that the host has been sent a request + * to change the sample frequency. The sample frequency will be sent on the next OUT transaction. + * It contains the endpoint address when set. The following code is recommended for + * detecting new sample frequency in main code: + * \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency + * + * The USBFS_transferState variable is checked to make sure that the transfer completes. */ + volatile uint8 USBFS_frequencyChanged; + /** Contains the mute configuration set by the host.*/ + volatile uint8 USBFS_currentMute; + /** Contains the volume level set by the host.*/ + volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; + volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, + USBFS_VOL_MIN_MSB}; + volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MAX_LSB, + USBFS_VOL_MAX_MSB}; + volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB, + USBFS_VOL_RES_MSB}; +#endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchAUDIOClassRqst +****************************************************************************//** +* +* This routine dispatches class requests +* +* \return +* Results of Audio Class request handling: +* - USBFS_TRUE - request was handled without errors +* - USBFS_FALSE - error occurs during handling of request +* +* \globalvars +* USBFS_currentSampleFrequency: Contains the current audio Sample +* Frequency. It is set by the Host using SET_CUR request to the endpoint. +* USBFS_frequencyChanged: This variable is used as a flag for the +* user code, to be aware that Host has been sent request for changing +* Sample Frequency. Sample frequency will be sent on the next OUT +* transaction. It is contains endpoint address when set. The following +* code is recommended for detecting new Sample Frequency in main code: +* +* \snippet /USBFS_sut_02.cydsn/main.c Detecting new Sample Frequency +* +* USBFS_transferState variable is checked to be sure that transfer +* completes. +* USBFS_currentMute: Contains mute configuration set by Host. +* USBFS_currentVolume: Contains volume level set by Host. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchAUDIOClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + uint8 RqstRcpt = (uint8)(USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK); +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + uint8 wValueHi = (uint8) USBFS_wValueHiReg; + uint8 epNumber = (uint8) USBFS_wIndexLoReg & USBFS_DIR_UNUSED; +#endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + if (USBFS_RQST_RCPT_EP == RqstRcpt) + { + /* Request recipient is to endpoint. */ + switch (USBFS_bRequestReg) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL) + { + /* point Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + + requestHandled = USBFS_InitControlRead(); + } + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK) */ + break; + + default: + /* Do not handle this request unless callback is defined. */ + break; + } + + } + else if (USBFS_RQST_RCPT_IFC == RqstRcpt) + { + /* Request recipient is interface or entity ID. */ + switch (USBFS_bRequestReg) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if (wValueHi == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK) */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + + requestHandled = USBFS_InitControlRead(); + } + else if (wValueHi == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK) */ + + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + + requestHandled = USBFS_InitControlRead(); + } + else + { + /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK) */ + } + break; + + case USBFS_GET_MIN: + if (wValueHi == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_minimumVolume[0]; + + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_GET_MAX: + if (wValueHi == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_maximumVolume[0]; + + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_GET_RES: + if (wValueHi == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; + + requestHandled = USBFS_InitControlRead(); + } + break; + + /* The contents of the status message is reserved for future use. + * For the time being, a null packet should be returned in the data stage of the + * control transfer, and the received null packet should be ACKed. + */ + case USBFS_GET_STAT: + USBFS_currentTD.wCount = 0u; + + requestHandled = USBFS_InitControlWrite(); + + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK) */ + break; + + default: + /* Do not handle this request. */ + break; + } + } + else + { + /* Do not handle other requests recipients. */ + } + } + else + { + /* Handle direction from host to device. */ + + if (USBFS_RQST_RCPT_EP == RqstRcpt) + { + /* Request recipient is endpoint. */ + switch (USBFS_bRequestReg) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if (wValueHi == USBFS_SAMPLING_FREQ_CONTROL) + { + /* point Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + USBFS_frequencyChanged = (uint8) epNumber; + + requestHandled = USBFS_InitControlWrite(); + } + #endif /* (USBFS_ENABLE_AUDIO_STREAMING) */ + + /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK) */ + break; + + default: + /* Do not handle this request. */ + break; + } + } + else if(USBFS_RQST_RCPT_IFC == RqstRcpt) + { + /* Request recipient is interface or entity ID. */ + switch (USBFS_bRequestReg) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if (wValueHi == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK) */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + + requestHandled = USBFS_InitControlWrite(); + } + else if (wValueHi == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK) */ + + /* Entity ID Control Selector is VOLUME */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + + requestHandled = USBFS_InitControlWrite(); + } + else + { + /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK) */ + } + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + + /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK) */ + break; + + default: + /* Do not handle this request. */ + break; + } + } + else + { + /* Do not handle other requests recipients. */ + } + } + + return (requestHandled); +} +#endif /* (USER_SUPPLIED_AUDIO_HANDLER) */ + + +/******************************************************************************* +* Additional user functions supporting AUDIO Requests +********************************************************************************/ + +/* `#START AUDIO_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* (USBFS_ENABLE_AUDIO_CLASS) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h new file mode 100644 index 0000000..2c61cf0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_audio.h @@ -0,0 +1,104 @@ +/***************************************************************************//** +* \file USBFS_audio.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* Audio class. +* +* Related Document: +* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_audio_H) +#define CY_USBFS_USBFS_audio_H + +#include "USBFS.h" + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_CONSTANTS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Constants for USBFS_audio API. +***************************************/ + +/* Audio Class-Specific Request Codes (AUDIO Table A-9) */ +#define USBFS_REQUEST_CODE_UNDEFINED (0x00u) +#define USBFS_SET_CUR (0x01u) +#define USBFS_GET_CUR (0x81u) +#define USBFS_SET_MIN (0x02u) +#define USBFS_GET_MIN (0x82u) +#define USBFS_SET_MAX (0x03u) +#define USBFS_GET_MAX (0x83u) +#define USBFS_SET_RES (0x04u) +#define USBFS_GET_RES (0x84u) +#define USBFS_SET_MEM (0x05u) +#define USBFS_GET_MEM (0x85u) +#define USBFS_GET_STAT (0xFFu) + +/* point Control Selectors (AUDIO Table A-19) */ +#define USBFS_EP_CONTROL_UNDEFINED (0x00u) +#define USBFS_SAMPLING_FREQ_CONTROL (0x01u) +#define USBFS_PITCH_CONTROL (0x02u) + +/* Feature Unit Control Selectors (AUDIO Table A-11) */ +#define USBFS_FU_CONTROL_UNDEFINED (0x00u) +#define USBFS_MUTE_CONTROL (0x01u) +#define USBFS_VOLUME_CONTROL (0x02u) +#define USBFS_BASS_CONTROL (0x03u) +#define USBFS_MID_CONTROL (0x04u) +#define USBFS_TREBLE_CONTROL (0x05u) +#define USBFS_GRAPHIC_EQUALIZER_CONTROL (0x06u) +#define USBFS_AUTOMATIC_GAIN_CONTROL (0x07u) +#define USBFS_DELAY_CONTROL (0x08u) +#define USBFS_BASS_BOOST_CONTROL (0x09u) +#define USBFS_LOUDNESS_CONTROL (0x0Au) + +#define USBFS_SAMPLE_FREQ_LEN (3u) +#define USBFS_VOLUME_LEN (2u) + +#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE) + #define USBFS_VOL_MIN_MSB (0x80u) + #define USBFS_VOL_MIN_LSB (0x01u) + #define USBFS_VOL_MAX_MSB (0x7Fu) + #define USBFS_VOL_MAX_LSB (0xFFu) + #define USBFS_VOL_RES_MSB (0x00u) + #define USBFS_VOL_RES_LSB (0x01u) +#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */ + + +/*************************************** +* External data references +***************************************/ +/** +* \addtogroup group_audio +* @{ +*/ +extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; +extern volatile uint8 USBFS_frequencyChanged; +extern volatile uint8 USBFS_currentMute; +extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; +/** @} audio */ + +extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; + +#endif /* CY_USBFS_USBFS_audio_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c new file mode 100644 index 0000000..dfb3e9e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_boot.c @@ -0,0 +1,243 @@ +/***************************************************************************//** +* \file USBFS_boot.c +* \version 3.10 +* +* \brief +* This file contains the Bootloader API for USBFS Component. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + +/*************************************** +* Bootloader Variables +***************************************/ + + +static uint8 USBFS_started = 0u; + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStart +****************************************************************************//** +* +* This function performs all required initialization for the USBFS component, +* waits on enumeration, and enables communication. +* +* \sideeffect +* This function starts the USB with 3V or 5V operation. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStart(void) +{ + /* Enable Global Interrupts. Interrupts are mandatory for USBFS component operation. */ + CyGlobalIntEnable; + + /* Start USBFS Operation: device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR. */ + USBFS_Start(0u, USBFS_DWR_POWER_OPERATION); + + /* USB component started, the correct enumeration will be checked in the first Read operation. */ + USBFS_started = 1u; +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStop. +****************************************************************************//** +* +* This function performs all necessary shutdown tasks required for the USBFS +* component. +* +* \sideeffect +* Calls the USBFS_Stop() function. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStop(void) +{ + USBFS_Stop(); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommReset. +****************************************************************************//** +* +* This function resets receive and transmit communication buffers. +* +* \reentrant +* No +* +*******************************************************************************/ +void USBFS_CyBtldrCommReset(void) +{ + USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommWrite. +****************************************************************************//** +* +* This function allows the caller to write data to the bootloader host. It +* handles polling to allow a block of data to be completely sent to the host +* device. +* +* \param pData A pointer to the block of data to send to the device +* \param size The number of bytes to write. +* \param count Pointer to an unsigned short variable to write the number of +* bytes actually written. +* \param timeOut Number of units to wait before returning because of a timeout. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value that +* best describes the problem. For more information, see the “Return Codes” +* section of the System Reference Guide. +* +* \reentrant +* No +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus retCode; + uint16 timeoutMs; + + /* Convert 10mS checks into 1mS checks. */ + timeoutMs = ((uint16) 10u * timeOut); + + /* Load data into IN endpoint to be read by host. */ + USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); + + /* Wait unitl host reads data from IN endpoint. */ + while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && + (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) + { + retCode = CYRET_TIMEOUT; + } + else + { + *count = size; + retCode = CYRET_SUCCESS; + } + + return (retCode); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommRead. +****************************************************************************//** +* +* This function allows the caller to read data from the bootloader host. It +* handles polling to allow a block of data to be completely received from the +* host device. +* +* \param pData A pointer to the area to store the block of data received +* from the device. +* \param size The number of bytes to read. +* \param count Pointer to an unsigned short variable to write the number +* of bytes actually read. +* \param timeOut Number of units to wait before returning because of a timeOut. +* Timeout is measured in 10s of ms. +* +* \return +* Returns CYRET_SUCCESS if no problem was encountered or returns the value that +* best describes the problem. For more information, see the “Return Codes” +* section of the System Reference Guide. +* +* \reentrant +* No +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus retCode; + uint16 timeoutMs; + + /* Convert 10mS checks into 1mS checks. */ + timeoutMs = ((uint16) 10u * timeOut); + + if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) + { + size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; + } + + /* Wait for enumeration first time. */ + if (0u != USBFS_started) + { + /* Wait for device enumeration. */ + while ((0u == USBFS_GetConfiguration()) && (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + /* Enable OUT after enumeration. */ + if (0u != USBFS_GetConfiguration()) + { + (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status. */ + USBFS_CyBtldrCommReset(); + + USBFS_started = 0u; + } + } + else /* Check for configuration changes, has been done by Host. */ + { + if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET. */ + { + if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured. */ + { + USBFS_CyBtldrCommReset(); + } + } + } + + timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */ + + /* Wait unitl host writes data into OUT endpoint. */ + while ((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ + (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + /* Read data from OUT endpoint if host wrote data into it. */ + if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) + { + *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); + retCode = CYRET_SUCCESS; + } + else + { + *count = 0u; + retCode = CYRET_TIMEOUT; + } + + return (retCode); +} + +#endif /* (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c new file mode 100644 index 0000000..1fd9741 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.c @@ -0,0 +1,1114 @@ +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.10 +* +* \brief +* This file contains the USB CDC class request handler. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" + + +#if defined(USBFS_ENABLE_CDC_CLASS) + +/******************************************************************************* +* CDC Variables +*******************************************************************************/ + +/*PUBLIC*/ +/** Contains the current line coding structure. The host sets it using a + * SET_LINE_CODING request and returns it to the user code using the + * USBFS_GetDTERate(), USBFS_GetCharFormat(), + * USBFS_GetParityType(), and USBFS_GetDataBits() APIs. + * It is an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE] = +{ + /*COM Port 1*/ + { + 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ + 0x00u, /* 1 Stop bit */ + 0x00u, /* None parity */ + 0x08u /* 8 data bits */ + }, + /*COM Port 2*/ + { + 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ + 0x00u, /* 1 Stop bit */ + 0x00u, /* None parity */ + 0x08u /* 8 data bits */ + } +}; + +/**Used as a flag for the USBFS_IsLineChanged() API, to inform it that the + * host has been sent a request to change line coding or control bitmap. It is + * an array of 2 elements for COM port 1 and COM port 2 for MultiCOM port + * support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the current control-signal bitmap. The host sets it using a + * SET_CONTROL_LINE request and returns it to the user code using the + * USBFS_GetLineControl() API. It is an array of 2 elements for COM + * port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, data + * is in 0 element.*/ +volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the 16-bit serial state value that was sent using the + * \ref USBFS_SendSerialState() API. . It is an array of 2 elements + * for COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM + * port, data is in 0 element.*/ +volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number. It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in CDC APIs + * to send data to the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data OUT endpoint number. It is initialized after a + * SET_CONFIGURATION request based on user descriptor. It is used in CDC APIs to + * receive data from the PC. It is an array of 2 elements for COM port 1 and COM + * port 2 for MultiCOM port support. In case of 1 COM port, data is in 0 element.*/ +volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +/** Contains the data IN endpoint number for COMMUNICATION interface. It is + * initialized after a SET_CONFIGURATION request based on a user descriptor. It + * is used in CDC APIs to send data to the PC. It is an array of 2 elements for + * COM port 1 and COM port 2 for MultiCOM port support. In case of 1 COM port, + * data is in 0 element.*/ +volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; + +/*PRIVATE*/ + +#define USBFS_CDC_IN_EP (0u) +#define USBFS_CDC_OUT_EP (1u) +#define USBFS_CDC_NOTE_EP (2u) + +#define USBFS_CDC_EP_MASK (0x01u) + +#define USBFS_GET_EP_COM_NUM(cdcComNums, epType) (((cdcComNums) >> (epType)) & USBFS_CDC_EP_MASK) + + +/*************************************** +* Static Function Prototypes +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + static uint16 USBFS_StrLen(const char8 string[]) ; + static t_USBFS_cdc_notification USBFS_serialStateNotification = + { + + USBFS_SERIAL_STATE_REQUEST_TYPE, /* bRequestType */ + USBFS_SERIAL_STATE, /* bNotification */ + 0u, /* wValue */ + 0u, /* wValueMSB */ + 0u, /* wIndex */ + 0u, /* wIndexMSB */ + USBFS_SERIAL_STATE_LENGTH, /* wLength */ + 0u, /* wLengthMSB */ + 0u, /* wSerialState */ + 0u, /* wSerialStateMSB */ + }; + static uint8 USBFS_activeCom = 0u; +#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchCDCClassRqst +****************************************************************************//** +* +* This routine dispatches CDC class requests. +* +* \return +* requestHandled +* +* \globalvars +* USBFS_linesCoding: Contains the current line coding structure. +* It is set by the Host using SET_LINE_CODING request and returned to the +* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), +* USBFS_GetParityType(), USBFS_GetDataBits() APIs. +* USBFS_linesControlBitmap: Contains the current control signal +* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned +* to the user code by the USBFS_GetLineControl() API. +* USBFS_linesChanged: This variable is used as a flag for the +* USBFS_IsLineChanged() API, to be aware that Host has been sent request +* for changing Line Coding or Control Bitmap. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchCDCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 comPort; + + comPort = USBFS_GetInterfaceComPort((uint8)USBFS_wIndexLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_CDC_GET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; + requestHandled = USBFS_InitControlRead(); + break; + + /* `#START CDC_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: + /* Do not handle this request unless callback is defined. */ + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK + requestHandled = USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK) */ + break; + } + } + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) + { + case USBFS_CDC_SET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_linesCoding[comPort]; + USBFS_linesChanged[comPort] |= USBFS_LINE_CODING_CHANGED; + + requestHandled = USBFS_InitControlWrite(); + break; + + case USBFS_CDC_SET_CONTROL_LINE_STATE: + USBFS_linesControlBitmap[comPort] = (uint8) USBFS_wValueLoReg; + USBFS_linesChanged[comPort] |= USBFS_LINE_CONTROL_CHANGED; + + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + default: + /* Do not handle this request unless callback is defined. */ + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK + requestHandled = USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback(); + #endif /* (USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK) */ + break; + } + } + + return(requestHandled); +} + + +/*************************************************************************** +* Function Name: USBFS_GetInterfaceComPort +************************************************************************//** +* \internal +* Internal function which gets number of COM port by specified interface +* number. +* +* \param uint8 interface +* Interface number +* +* \return +* COM port number (0 or 1) or error 0xFF +* +***************************************************************************/ +uint8 USBFS_GetInterfaceComPort(uint8 interface) +{ + uint8 comPort = 0u; + uint8 res = 0xFFu; + uint8 notEp; + + while (comPort < USBFS_MAX_MULTI_COM_NUM) + { + notEp = USBFS_cdcCommInInterruptEp[comPort]; + + if (USBFS_EP[notEp].interface == interface) + { + res = comPort; + comPort = USBFS_MAX_MULTI_COM_NUM; + } + + comPort++; + } + return (res); +} + + +/*************************************** +* Optional CDC APIs +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) +/*************************************************************************** +* Function Name: USBFS_CDC_Init +************************************************************************//** +* +* This function initializes the CDC interface to be ready to receive data +* from the PC. The API set active communication port to 0 in the case of +* multiple communication port support.This API should be called after the +* device has been started and configured using USBUART_Start() API to +* initialize and start the USBFS component operation. Then call the +* USBUART_GetConfiguration() API to wait until the host has enumerated and +* configured the device. For example: +* +* \snippet /USBFS_sut_02.cydsn/main.c wait for enumeration +* +* \return +* cystatus: +* Return Value Description +* USBFS_SUCCESS CDC interface was initialized correctly +* USBFS_FAILURE CDC interface was not initialized +* +* \globalvars +* USBFS_linesChanged: Initialized to zero. +* USBFS_cdcDataOutEp: Used as an OUT endpoint number. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_CDC_Init(void) +{ + uint8 comPort; + uint8 outEp; + uint8 ret = USBFS_SUCCESS; + + USBFS_activeCom = 0u; + USBFS_linesChanged[USBFS_COM_PORT1] = 0u; + USBFS_linesChanged[USBFS_COM_PORT2] = 0u; + + for(comPort = 0u; comPort outEp)) + { + USBFS_EnableOutEP(outEp); + } + + } + + /* COM Port 1 should be correct to proceed. */ + if ((0u == USBFS_cdcDataInEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcDataOutEp[USBFS_COM_PORT1]) \ + || (0u == USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1]) + || (USBFS_cdcDataInEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcDataOutEp[USBFS_COM_PORT1] >= USBFS_MAX_EP) + || (USBFS_cdcCommInInterruptEp[USBFS_COM_PORT1] >= USBFS_MAX_EP)) + { + ret = USBFS_FAILURE; + } + + return (ret); +} + + +/******************************************************************************* +* Function Name: USBFS_PutData +****************************************************************************//** +* +* This function sends a specified number of bytes from the location specified +* by a pointer to the PC. The USBFS_CDCIsReady() function should be +* called before sending new data, to be sure that the previous data has +* finished sending. +* If the last sent packet is less than maximum packet size the USB transfer +* of this short packet will identify the end of the segment. If the last sent +* packet is exactly maximum packet size, it shall be followed by a zero-length +* packet (which is a short packet) to assure the end of segment is properly +* identified. To send zero-length packet, use USBFS_PutData() API +* with length parameter set to zero. +* +* \param pData: pointer to the buffer containing data to be sent. +* \param length: Specifies the number of bytes to send from the pData +* buffer. Maximum length will be limited by the maximum packet +* size for the endpoint. Data will be lost if length is greater than Max +* Packet Size. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutData(const uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Limit length to maximum packet size for endpoint. */ + if (length > USBFS_EP[epNumber].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Size. */ + length = USBFS_EP[epNumber].bufferSize; + + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + + USBFS_LoadInEP(epNumber, pData, length); +} + + +/******************************************************************************* +* Function Name: USBFS_StrLen +****************************************************************************//** +* +* Calculates length of a null terminated string. +* +* \param string: pointer to the string. +* +* \return +* Length of the string +* +*******************************************************************************/ +static uint16 USBFS_StrLen(const char8 string[]) +{ + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return ((uint16) len); +} + + +/*************************************************************************** +* Function Name: USBFS_PutString +************************************************************************//** +* +* This function sends a null terminated string to the PC. This function will +* block if there is not enough memory to place the whole string. It will block +* until the entire string has been written to the transmit buffer. +* The USBFS_CDCIsReady() function should be called before +* sending data with a new call to USBFS_PutString(), to be sure +* that the previous data has finished sending. This function sends +* zero-length packet automatically, if the length of the last packet, sent +* by this API, is equal to Max Packet Size +* +* \param string: pointer to the string to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutString(const char8 string[]) +{ + uint16 strLength; + uint16 sendLength; + uint16 bufIndex = 0u; + + uint8 epNumber = USBFS_cdcDataInEp[USBFS_activeCom]; + + /* Get length string length (it is terminated with zero). */ + strLength = USBFS_StrLen(string); + + do + { + /* Limit length to maximum packet size of endpoint. */ + sendLength = (strLength > USBFS_EP[epNumber].bufferSize) ? + USBFS_EP[epNumber].bufferSize : strLength; + + /* Load IN endpoint and expose it to host. */ + USBFS_LoadInEP(epNumber, (const uint8 *)&string[bufIndex], sendLength); + strLength -= sendLength; + + /* If more data are present to send or full packet was sent */ + if ((strLength > 0u) || (sendLength == USBFS_EP[epNumber].bufferSize)) + { + bufIndex += sendLength; + + /* Wait until host read data from IN endpoint buffer. */ + while (USBFS_IN_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) + { + } + + /* If last packet is exactly maximum packet size, it shall be followed + * by a zero-length packet to assure the end of segment is properly + * identified by the terminal. + */ + if (0u == strLength) + { + USBFS_LoadInEP(epNumber, NULL, 0u); + } + } + } + while (strLength > 0u); +} + + +/*************************************************************************** +* Function Name: USBFS_PutChar +************************************************************************//** +* +* This function writes a single character to the PC at a time. This is an +* inefficient way to send large amounts of data. +* +* \param txDataByte: Character to be sent to the PC. +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +***************************************************************************/ +void USBFS_PutChar(char8 txDataByte) +{ + uint8 dataByte; + dataByte = (uint8) txDataByte; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], &dataByte, 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_PutCRLF +****************************************************************************//** +* +* This function sends a carriage return (0x0D) and line feed (0x0A) to the +* PC. This APIis provided to mimic API provided by our other UART components +* +* \globalvars +* +* USBFS_cdcDataInEp: CDC IN endpoint number used for sending +* data. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_PutCRLF(void) +{ + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdcDataInEp[USBFS_activeCom], (const uint8 *)txData, 2u); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCount +****************************************************************************//** +* +* This function returns the number of bytes that were received from the PC. +* The returned length value should be passed to USBFS_GetData() as +* a parameter to read all received data. If all of the received data is not +* read at one time by the USBFS_GetData() API, the unread data will +* be lost. +* +* \return +* Returns the number of received bytes. The maximum amount of received data at +* a time is limited by the maximum packet size for the endpoint. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint16 USBFS_GetCount(void) +{ + uint16 bytesCount; + + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + if (USBFS_OUT_BUFFER_FULL == USBFS_EP[epNumber].apiEpState) + { + bytesCount = USBFS_GetEPCount(epNumber); + } + else + { + bytesCount = 0u; + } + + return (bytesCount); +} + + +/******************************************************************************* +* Function Name: USBFS_DataIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component received data or +* received zero-length packet. The USBFS_GetAll() or +* USBFS_GetData() API should be called to read data from the buffer +* and reinitialize the OUT endpoint even when a zero-length packet is +* received. These APIs will return zero value when zero-length packet is +* received. +* +* \return +* If the OUT packet is received, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_DataIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataOutEp[USBFS_activeCom])); +} + + +/******************************************************************************* +* Function Name: USBFS_CDCIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the component is ready to send more +* data to the PC; otherwise, it returns zero. The function should be called +* before sending new data when using any of the following APIs: +* USBFS_PutData(),USBFS_PutString(), +* USBFS_PutChar or USBFS_PutCRLF(), +* to be sure that the previous data has finished sending. +* +* \return +* If the buffer can accept new data, this function returns a non-zero value. +* Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_CDCIsReady(void) +{ + return (USBFS_GetEPState(USBFS_cdcDataInEp[USBFS_activeCom])); +} + + +/*************************************************************************** +* Function Name: USBFS_GetData +************************************************************************//** +* +* This function gets a specified number of bytes from the input buffer and +* places them in a data array specified by the passed pointer. +* The USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. If all received data will not be read at +* once, the unread data will be lost. The USBFS_GetData() API should +* be called to get the number of bytes that were received. +* +* \param pData: Pointer to the data array where data will be placed. +* \param Length: Number of bytes to read into the data array from the RX buffer. +* Maximum length is limited by the the number of received bytes +* or 64 bytes. +* +* \return +* Number of bytes which function moves from endpoint RAM into the +* data array. The function moves fewer than the requested number +* of bytes if the host sends fewer bytes than requested or sends +* zero-length packet. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint16 USBFS_GetData(uint8* pData, uint16 length) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + /* Read data from OUT endpoint buffer. */ + length = USBFS_ReadOutEP(epNumber, pData, length); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (length); +} + + +/******************************************************************************* +* Function Name: USBFS_GetAll +****************************************************************************//** +* +* This function gets all bytes of received data from the input buffer and +* places them into a specified data array. The +* USBFS_DataIsReady() API should be called first, to be sure +* that data is received from the host. +* +* \param pData: Pointer to the data array where data will be placed. +* +* \return +* Number of bytes received. The maximum amount of the received at a time +* data is 64 bytes. +* +* \globalvars +* - \ref USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* - \ref USBFS_EP[].bufferSize: EP max packet size is used as a +* length to read all data from the EP buffer. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint16 USBFS_GetAll(uint8* pData) +{ + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + uint16 dataLength; + + /* Read data from OUT endpoint buffer. */ + dataLength = USBFS_ReadOutEP(epNumber, pData, USBFS_EP[epNumber].bufferSize); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (dataLength); +} + + +/*************************************************************************** +* Function Name: USBFS_GetChar +************************************************************************//** +* +* This function reads one byte of received data from the buffer. If more than +* one byte has been received from the host, the rest of the data will be lost. +* +* \return +* Received one character. +* +* \globalvars +* USBFS_cdcDataOutEp: CDC OUT endpoint number used. +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_GetChar(void) +{ + uint8 rxData; + uint8 epNumber = USBFS_cdcDataOutEp[USBFS_activeCom]; + + (void) USBFS_ReadOutEP(epNumber, &rxData, 1u); + +#if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(epNumber)) + { + } + + /* Enable OUT endpoint to communicate with host. */ + USBFS_EnableOutEP(epNumber); +#endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + return (rxData); +} + + +/******************************************************************************* +* Function Name: USBFS_IsLineChanged +****************************************************************************//** +* +* This function returns clear on read status of the line. It returns not zero +* value when the host sends updated coding or control information to the +* device. The USBFS_GetDTERate(), USBFS_GetCharFormat() +* or USBFS_GetParityType() or USBFS_GetDataBits() API +* should be called to read data coding information. +* The USBFS_GetLineControl() API should be called to read line +* control information. +* +* \return +* If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it +* returns a non-zero value. Otherwise, it returns zero. +* Return Value | Description +* -----------------------------|-------------------------- +* USBUART_LINE_CODING_CHANGED | Line coding changed +* USBUART_LINE_CONTROL_CHANGED | Line control changed +* +* \globalvars +* - \ref USBFS_transferState: it is checked to be sure then OUT +* data phase has been complete, and data written to the lineCoding or +* Control Bitmap buffer. +* - \ref USBFS_linesChanged: used as a flag to be aware that +* Host has been sent request for changing Line Coding or Control Bitmap. +* +*******************************************************************************/ +uint8 USBFS_IsLineChanged(void) +{ + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if (USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if (USBFS_linesChanged[USBFS_activeCom] != 0u) + { + state = USBFS_linesChanged[USBFS_activeCom]; + USBFS_linesChanged[USBFS_activeCom] = 0u; + } + } + + return (state); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDTERate +************************************************************************//** +* +* This function returns the data terminal rate set for this port in bits +* per second. +* +* \return +* Returns a uint32 value of the data rate in bits per second. +* +* \globalvars +* USBFS_linesCoding: First four bytes converted to uint32 +* depend on compiler, and returned as a data rate. +* +*******************************************************************************/ +uint32 USBFS_GetDTERate(void) +{ + uint32 rate; + + rate = USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_RATE]; + + return (rate); +} + + +/******************************************************************************* +* Function Name: USBFS_GetCharFormat +****************************************************************************//** +* +* Returns the number of stop bits. +* +* \return +* Returns the number of stop bits. +* Return |Value Description +* ---------------------|------------------- +* USBUART_1_STOPBIT | 1 stop bit +* USBUART_1_5_STOPBITS | 1,5 stop bits +* USBUART_2_STOPBITS | 2 stop bits +* +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetCharFormat(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_STOP_BITS]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetParityType +****************************************************************************//** +* +* This function returns the parity type for the CDC port. +* +* \return +* Returns the parity type. +* Return | Value Description +* ----------------------|------------------- +* USBUART_PARITY_NONE | 1 stop bit +* USBUART_PARITY_ODD | 1,5 stop bits +* USBUART_PARITY_EVEN | 2 stop bits +* USBUART_PARITY_MARK | Mark +* USBUART_PARITY_SPACE | Space +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetParityType(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_PARITY]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetDataBits +************************************************************************//** +* +* This function returns the number of data bits for the CDC port. +* +* \return +* Returns the number of data bits. +* The number of data bits can be 5, 6, 7, 8 or 16. +* +* \globalvars +* USBFS_linesCoding: used to get a parameter. +* +*******************************************************************************/ +uint8 USBFS_GetDataBits(void) +{ + return (USBFS_linesCoding[USBFS_activeCom][USBFS_LINE_CODING_DATA_BITS]); +} + + +/*************************************************************************** +* Function Name: USBFS_GetLineControl +************************************************************************//** +* +* This function returns Line control bitmap that the host sends to the +* device. +* +* \return +* Returns Line control bitmap. +* Return |Value Notes +* -------------------------|----------------------------------------------- +* USBUART_LINE_CONTROL_DTR |Indicates that a DTR signal is present. This signal corresponds to V.24 signal 108/2 and RS232 signal DTR. +* USBUART_LINE_CONTROL_RTS |Carrier control for half-duplex modems. This signal corresponds to V.24 signal 105 and RS232 signal RTS. +* RESERVED |The rest of the bits are reserved. +* +* *Note* Some terminal emulation programs do not properly handle these +* control signals. They update information about DTR and RTS state only +* when the RTS signal changes the state. +* +* \globalvars +* USBFS_linesControlBitmap: used to get a parameter. +* +*******************************************************************************/ +uint16 USBFS_GetLineControl(void) +{ + return (USBFS_linesControlBitmap[USBFS_activeCom]); +} + + +/******************************************************************************* +* Function Name: USBFS_SendSerialState +****************************************************************************//** +* +* Sends the serial state notification to the host using the interrupt +* endpoint for the COM port selected using the API SetComPort().The +* USBFS_NotificationIsReady() API must be called to check if the +* Component is ready to send more serial state to the host. The API will +* not send the notification data if the interrupt endpoint Max Packet Size +* is less than the required 10 bytes. +* +* \param uint16 serialState +* 16-bit value that will be sent from the device to the +* host as SERIAL_STATE notification using the IN interrupt endpoint. Refer +* to revision 1.2 of the CDC PSTN Subclass specification for bit field +* definitions of the 16-bit serial state value. +* +*******************************************************************************/ +void USBFS_SendSerialState (uint16 serialState) +{ + uint8 epNumber = USBFS_cdcCommInInterruptEp[USBFS_activeCom]; + + if(USBFS_SERIAL_STATE_SIZE <= USBFS_EP[epNumber].bufferSize) + { + /* Save current SERIAL_STATE bitmap. */ + USBFS_serialStateBitmap[USBFS_activeCom] = serialState; + + /* Add interface number */ + USBFS_serialStateNotification.wIndex = USBFS_EP[epNumber].interface; + + /*Form SERIAL_STATE data*/ + USBFS_serialStateNotification.wSerialState = LO8(USBFS_serialStateBitmap[USBFS_activeCom]); + USBFS_serialStateNotification.wSerialStateMSB = HI8(USBFS_serialStateBitmap[USBFS_activeCom]); + + USBFS_LoadInEP(epNumber, (uint8 *) &USBFS_serialStateNotification, sizeof(USBFS_serialStateNotification)); + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetSerialState +****************************************************************************//** +* +* This function returns the current serial state value for the COM port +* selected using the API SetComPort(). +* +* \return +* 16-bit serial state value. Refer to revision 1.2 of the CDC PSTN Subclass +* specification for bit field definitions of the 16-bit serial state value. +* +*******************************************************************************/ +uint16 USBFS_GetSerialState(void) +{ + return USBFS_serialStateBitmap[USBFS_activeCom]; +} + + +/******************************************************************************* +* Function Name: USBFS_NotificationIsReady +****************************************************************************//** +* +* This function returns a non-zero value if the Component is ready to send +* more notifications to the host; otherwise, it returns zero. The function +* should be called before sending new notifications when using +* USBFS_SendSerialState() to ensure that any previous +* notification data has been already sent to the host. +* +* \return +* If the buffer can accept new data(endpoint buffer not full), this +* function returns a non-zero value. Otherwise, it returns zero. +* +* \globalvars +* USBFS_cdcDataInEp: CDC IN endpoint number used. +* +*******************************************************************************/ +uint8 USBFS_NotificationIsReady(void) +{ + return (USBFS_EP[USBFS_cdcCommInInterruptEp[USBFS_activeCom]].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_SetComPort +****************************************************************************//** +* +* This function allows the user to select from one of the two COM ports +* they wish to address in the instance of having multiple COM ports +* instantiated though the use of a composite device. Once set, all future +* function calls related to the USBUART will be affected. This addressed +* COM port can be changed during run time. +* +* \param comNumber +* Contains the COM interface the user wishes to address. Value can either +* be 0 or 1 since a maximum of only 2 COM ports can be supported. Note that +* this COM port number is not the COM port number assigned on the PC side +* for the UART communication. If a value greater than 1 is passed, the +* function returns without performing any action. +* +*******************************************************************************/ +void USBFS_SetComPort(uint8 comNumber) +{ + if ((USBFS_activeCom != comNumber) && \ + (comNumber < USBFS_MAX_MULTI_COM_NUM )) + { + USBFS_activeCom = comNumber; + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetComPort +****************************************************************************//** +* +* This function returns the current selected COM port that the user is +* currently addressing in the instance of having multiple COM ports +* instantiated though the use of a composite device. +* +* \return +* Returns the currently selected COM port. Value can either be 0 or 1 since +* a maximum of only 2 COM ports can be supported. . Note that this COM port +* number is not the COM port number assigned on the PC side for the UART +* communication. +* +*******************************************************************************/ +uint8 USBFS_GetComPort(void) +{ + return (USBFS_activeCom); +} + + +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ + + +/*************************************************************************** +* Function Name: USBFS_Cdc_EpInit +************************************************************************//** +* +* \internal +* This routine decide type of endpoint (IN, OUT, Notification) and same to +* appropriate global variables according to COM port number. +* USBFS_cdcDataInEp[], USBFS_cdcCommInInterruptEp[], +* USBFS_cdcDataOutEp[] +* +* \param pEP: Pointer to structure with current EP description. +* \param epNum: EP number +* \param cdcComNums: Bit array of current COM ports for CDC IN, OUT, +* and notification EPs(0 - COM port 1, 1- COM port 2) +* +* \return +* Updated cdcComNums +* +* \reentrant +* No. +* +***************************************************************************/ +uint8 USBFS_Cdc_EpInit(const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) +{ + uint8 epType; + + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + if (epType != USBFS_EP_TYPE_INT) + { + USBFS_cdcDataInEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_IN_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_IN_EP); + } + else + { + + USBFS_cdcCommInInterruptEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_NOTE_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_NOTE_EP); + } + } + else + { + if (epType != USBFS_EP_TYPE_INT) + { + USBFS_cdcDataOutEp[USBFS_GET_EP_COM_NUM(cdcComNums, USBFS_CDC_OUT_EP)] = epNum; + cdcComNums |= (uint8)(USBFS_COM_PORT2 << USBFS_CDC_OUT_EP); + } + } + return (cdcComNums); +} + + +/******************************************************************************* +* Additional user functions supporting CDC Requests +********************************************************************************/ + +/* `#START CDC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h new file mode 100644 index 0000000..a362a57 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.h @@ -0,0 +1,139 @@ +/***************************************************************************//** +* \file USBFS_cdc.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* CDC class. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cdc_H) +#define CY_USBFS_USBFS_cdc_H + +#include "USBFS.h" + + +/******************************************************************************* +* Prototypes of the USBFS_cdc API. +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + uint8 USBFS_CDC_Init(void) ; + void USBFS_PutData(const uint8* pData, uint16 length) ; + void USBFS_PutString(const char8 string[]) ; + void USBFS_PutChar(char8 txDataByte) ; + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; + void USBFS_SendSerialState (uint16 serialState) ; + uint16 USBFS_GetSerialState (void) ; + void USBFS_SetComPort (uint8 comNumber) ; + uint8 USBFS_GetComPort (void) ; + uint8 USBFS_NotificationIsReady(void) ; + +#endif /* (USBFS_ENABLE_CDC_CLASS_API) */ +/** @} cdc */ + +/******************************************************************************* +* Constants for USBFS_cdc API. +*******************************************************************************/ + +/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ +#define USBFS_CDC_SET_LINE_CODING (0x20u) +#define USBFS_CDC_GET_LINE_CODING (0x21u) +#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) + +/*PSTN Subclass Specific Notifications (CDC ver 1.2 Table 30)*/ +#define USBFS_SERIAL_STATE (0x20u) + +#define USBFS_LINE_CODING_CHANGED (0x01u) +#define USBFS_LINE_CONTROL_CHANGED (0x02u) + +#define USBFS_1_STOPBIT (0x00u) +#define USBFS_1_5_STOPBITS (0x01u) +#define USBFS_2_STOPBITS (0x02u) + +#define USBFS_PARITY_NONE (0x00u) +#define USBFS_PARITY_ODD (0x01u) +#define USBFS_PARITY_EVEN (0x02u) +#define USBFS_PARITY_MARK (0x03u) +#define USBFS_PARITY_SPACE (0x04u) + +#define USBFS_LINE_CODING_SIZE (0x07u) +#define USBFS_LINE_CODING_RATE (0x00u) +#define USBFS_LINE_CODING_STOP_BITS (0x04u) +#define USBFS_LINE_CODING_PARITY (0x05u) +#define USBFS_LINE_CODING_DATA_BITS (0x06u) + +#define USBFS_LINE_CONTROL_DTR (0x01u) +#define USBFS_LINE_CONTROL_RTS (0x02u) + +#define USBFS_MAX_MULTI_COM_NUM (2u) + +#define USBFS_COM_PORT1 (0u) +#define USBFS_COM_PORT2 (1u) + +#define USBFS_SUCCESS (0u) +#define USBFS_FAILURE (1u) + +#define USBFS_SERIAL_STATE_SIZE (10u) + +/* SerialState constants*/ +#define USBFS_SERIAL_STATE_REQUEST_TYPE (0xA1u) +#define USBFS_SERIAL_STATE_LENGTH (0x2u) + +/******************************************************************************* +* External data references +*******************************************************************************/ +/** +* \addtogroup group_cdc +* @{ +*/ +extern volatile uint8 USBFS_linesCoding[USBFS_MAX_MULTI_COM_NUM][USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_linesChanged[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_linesControlBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint16 USBFS_serialStateBitmap[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataInEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcDataOutEp[USBFS_MAX_MULTI_COM_NUM]; +extern volatile uint8 USBFS_cdcCommInInterruptEp[USBFS_MAX_MULTI_COM_NUM]; +/** @} cdc */ + +/******************************************************************************* +* The following code is DEPRECATED and +* must not be used. +*******************************************************************************/ + + +#define USBFS_lineCoding USBFS_linesCoding[0] +#define USBFS_lineChanged USBFS_linesChanged[0] +#define USBFS_lineControlBitmap USBFS_linesControlBitmap[0] +#define USBFS_cdc_data_in_ep USBFS_cdcDataInEp[0] +#define USBFS_cdc_data_out_ep USBFS_cdcDataOutEp[0] + +#endif /* (CY_USBFS_USBFS_cdc_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf new file mode 100644 index 0000000..d967202 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf @@ -0,0 +1,137 @@ +;****************************************************************************** +; File Name: USBFS_cdc.inf +; Version 3.10 +; +; Description: +; Windows USB CDC setup file for USBUART Device. +; +;****************************************************************************** +; Copyright 2007-2016, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;****************************************************************************** + +[Version] +Signature="$Windows NT$" +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%PROVIDER% +LayoutFile=layout.inf +DriverVer=03/05/2007,2.0.0000.0 + +[Manufacturer] +%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64 + +[DestinationDirs] +DefaultDestDir=12 + +[SourceDisksFiles] + +[SourceDisksNames] + +[DeviceList.NTx86] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 + +[DeviceList.NTia64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 + +[DeviceList.NTamd64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_00 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_01 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_02 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_03 +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232&MI_04 + + +;------------------------------------------------------------------------------ +; 32 bit section for Windows 2000/2003/XP/Vista +;------------------------------------------------------------------------------ + +[DriverInstall.NTx86] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTx86.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTx86.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTx86.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for Intel Itanium based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTia64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTia64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTia64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTia64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for AMD64 and Intel EM64T based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; +;------------------------------------------------------------------------------ + +[DriverService] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ + +[Strings] +PROVIDER="Cypress" +MFGNAME="Cypress Semiconductor Corporation" +DESCRIPTION="Cypress USB UART" +SERVICE="USB UART" diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c new file mode 100644 index 0000000..c954026 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cls.c @@ -0,0 +1,149 @@ +/***************************************************************************//** +* \file USBFS_cls.c +* \version 3.10 +* +* \brief +* This file contains the USB Class request handler. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + + +#if(USBFS_EXTERN_CLS == USBFS_FALSE) + +/*************************************** +* User Implemented Class Driver Declarations. +***************************************/ +/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchClassRqst +****************************************************************************//** +* This routine dispatches class specific requests depend on interface class. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchClassRqst(void) +{ + uint8 requestHandled; + uint8 interfaceNumber; + + /* Get interface to which request is intended. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_IFC: + /* Class-specific request directed to interface: wIndexLoReg + * contains interface number. + */ + interfaceNumber = (uint8) USBFS_wIndexLoReg; + break; + + case USBFS_RQST_RCPT_EP: + /* Class-specific request directed to endpoint: wIndexLoReg contains + * endpoint number. Find interface related to endpoint, + */ + interfaceNumber = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].interface; + break; + + default: + /* Default interface is zero. */ + interfaceNumber = 0u; + break; + } + +#if (defined(USBFS_ENABLE_HID_CLASS) ||\ + defined(USBFS_ENABLE_AUDIO_CLASS) ||\ + defined(USBFS_ENABLE_CDC_CLASS) ||\ + USBFS_ENABLE_MSC_CLASS) + + /* Handle class request depends on interface type. */ + switch (USBFS_interfaceClass[interfaceNumber]) + { + #if defined(USBFS_ENABLE_HID_CLASS) + case USBFS_CLASS_HID: + requestHandled = USBFS_DispatchHIDClassRqst(); + break; + #endif /* (USBFS_ENABLE_HID_CLASS) */ + + #if defined(USBFS_ENABLE_AUDIO_CLASS) + case USBFS_CLASS_AUDIO: + requestHandled = USBFS_DispatchAUDIOClassRqst(); + break; + #endif /* (USBFS_CLASS_AUDIO) */ + + #if defined(USBFS_ENABLE_CDC_CLASS) + case USBFS_CLASS_CDC: + requestHandled = USBFS_DispatchCDCClassRqst(); + break; + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_ENABLE_MSC_CLASS) + case USBFS_CLASS_MSD: + #if (USBFS_HANDLE_MSC_REQUESTS) + /* MSC requests are handled by the component. */ + requestHandled = USBFS_DispatchMSCClassRqst(); + #elif defined(USBFS_DISPATCH_MSC_CLASS_RQST_CALLBACK) + /* MSC requests are handled by user defined callbcak. */ + requestHandled = USBFS_DispatchMSCClassRqst_Callback(); + #else + /* MSC requests are not handled. */ + requestHandled = USBFS_FALSE; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + break; + #endif /* (USBFS_ENABLE_MSC_CLASS) */ + + default: + /* Request is not handled: unknown class request type. */ + requestHandled = USBFS_FALSE; + break; + } +#else /*No class is defined*/ + if (0u != interfaceNumber) + { + /* Suppress warning message */ + } + requestHandled = USBFS_FALSE; +#endif /*HID or AUDIO or MSC or CDC class enabled*/ + + /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ + + /* `#END` */ + +#ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_DispatchClassRqst_Callback(interfaceNumber); + } +#endif /* (USBFS_DISPATCH_CLASS_RQST_CALLBACK) */ + + return (requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Class Specific Requests +********************************************************************************/ + +/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_CLS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h new file mode 100644 index 0000000..2fd19d6 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_cydmac.h @@ -0,0 +1,278 @@ +/***************************************************************************//** +* \file USBFS_cydmac.h +* \version 3.10 +* +* \brief +* This file provides macros implemenation of DMA_P4 functions. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cydmac_H) +#define CY_USBFS_USBFS_cydmac_H + +#include "USBFS_pvt.h" + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetConfiguration +****************************************************************************//** +* +* Sets configuration information for the specified descriptor. +* +* \param ch: DMA ch modified by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param cfg: Descriptor control register. +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. This function should not be called while +* the descriptor is active. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetConfiguration(ch, descr, cfg) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[ch][descr].ctl = (cfg); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetInterruptMask +****************************************************************************//** +* +* Enables the DMA channel interrupt. +* +* \param ch: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetInterruptMask(ch) \ + do{ \ + CYDMA_INTR_MASK_REG |= ((uint32)(1UL << (ch))); \ + }while(0) + + +/******************************************************************************* +* Function Name:USBFS_CyDmaSetDescriptor0Next +****************************************************************************//** +* +* Sets the descriptor 0 that should be run the next time the channel is +* triggered. +* +* \param channel: Channel used by this function. +* +* +*******************************************************************************/ +#define USBFS_CyDmaSetDescriptor0Next(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_DESCRIPTOR; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetNumDataElements +****************************************************************************//** +* +* Sets the number of data elements to transfer for specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param numEl: Total number of data elements this descriptor transfers - 1u. +* Valid ranges are 0 to 65535. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetNumDataElements(ch, descr, numEl) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl = \ + ((CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].ctl & (uint32) ~CYDMA_DATA_NR) | ((uint32) (numEl))); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetSrcAddress +****************************************************************************//** +* +* Returns the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Source address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetSrcAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetSrcAddress +****************************************************************************//** +* +* Configures the source address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param srcAddress: Address of DMA transfer source. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetSrcAddress(ch, descr, srcAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].src = (srcAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaGetDstAddress +****************************************************************************//** +* +* Returns the destination address for the specified descriptor, set by +* CyDmaSetDstAddress(). +* +* \param ch: Channel used by this function. +* \param descr: Specifies descriptor (0 or 1) used by this function. +* +* \return +* Destination address written to specified descriptor. +* +*******************************************************************************/ +#define USBFS_CyDmaGetDstAddress(ch, descr) CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst + + +/******************************************************************************* +* Function Name: USBFS_CyDmaSetDstAddress +****************************************************************************//** +* +* Configures the destination address for the specified descriptor. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* \param dstAddress: Address of DMA transfer destination. +* +* +* \sideeffect +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaSetDstAddress(ch, descr, dstAddress) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].dst = (dstAddress); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaValidateDescriptor +****************************************************************************//** +* +* Validates the specified descriptor after it has been invalidated. +* +* \param ch: Channel used by this function. +* \param descr: Descriptor (0 or 1) modified by this function. +* +* +* \sideeffect +* The status register associated with the specified descriptor is reset to +* zero after this function call. +* This function should not be called when the specified descriptor is active +* in the DMA transfer engine. This can be checked by calling CyDmaGetStatus(). +* +*******************************************************************************/ +#define USBFS_CyDmaValidateDescriptor(ch, descr) \ + do{ \ + CYDMA_DESCR_BASE.descriptor[(ch)][(descr)].status = CYDMA_VALID; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaChEnable +****************************************************************************//** +* +* Enables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called before DMA is completely configured the operation +* of the DMA is undefined and could result in system data corruption. +* +*******************************************************************************/ +#define USBFS_CyDmaChEnable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] |= CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: CyDmaChDisable +****************************************************************************//** +* +* Disables the DMA ch. +* +* \param ch: Channel used by this function. +* +* +* \sideeffect +* If this function is called during a DMA transfer the transfer is aborted. +* +*******************************************************************************/ +#define USBFS_CyDmaChDisable(ch) \ + do{ \ + CYDMA_CH_CTL_BASE.ctl[(ch)] &= (uint32) ~CYDMA_ENABLED; \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerIn +****************************************************************************//** +* +* Triggers the DMA channel to execute a transfer. The tr_in signal is +* triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_REQ_TR_OUT (0xC0020100U) +#define USBFS_CyDmaTriggerIn(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_REQ_TR_OUT | (uint32)(trSel); \ + }while(0) + + +/******************************************************************************* +* Function Name: USBFS_CyDmaTriggerOut +****************************************************************************//** +* +* Triggers the DMA channel to generate a transfer completion signal without +* actual transfer executed. The tr_out signal is triggered. +* +* \param trSel: trigger to be activated. +* +* +*******************************************************************************/ +#define USBFS_DMA_USB_BURST_END_TR_OUT (0xC0020300U) +#define USBFS_CyDmaTriggerOut(trSel) \ + do{ \ + CYDMA_TR_CTL_REG = USBFS_DMA_USB_BURST_END_TR_OUT | (uint32)(trSel); \ + }while(0) + + +#endif /* (CY_USBFS_USBFS_cydmac_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c new file mode 100644 index 0000000..638f491 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -0,0 +1,443 @@ +/***************************************************************************//** +* \file USBFS_descr.c +* \version 3.10 +* +* \brief +* This file contains the USB descriptors and storage. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + + +/***************************************************************************** +* User supplied descriptors. If you want to specify your own descriptors, +* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors. +*****************************************************************************/ +/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* USB Customizer Generated Descriptors +***************************************/ + +#if !defined(USER_SUPPLIED_DESCRIPTORS) +/********************************************************************* +* Device Descriptors +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { +/* Descriptor Length */ 0x12u, +/* DescriptorType: DEVICE */ 0x01u, +/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, +/* bDeviceClass */ 0x00u, +/* bDeviceSubClass */ 0x00u, +/* bDeviceProtocol */ 0x00u, +/* bMaxPacketSize0 */ 0x08u, +/* idVendor */ 0xB4u, 0x04u, +/* idProduct */ 0x37u, 0x13u, +/* bcdDevice */ 0x03u, 0x30u, +/* iManufacturer */ 0x02u, +/* iProduct */ 0x01u, +/* iSerialNumber */ 0x80u, +/* bNumConfigurations */ 0x01u +}; +/********************************************************************* +* Config Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x49u, 0x00u, +/* bNumInterfaces */ 0x02u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x00u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0xFAu, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x00u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x00u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x01u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x20u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x82u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x20u, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x01u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x00u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_2_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_2_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x03u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x20u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x84u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x20u +}; + +/********************************************************************* +* String Descriptor Table +*********************************************************************/ +const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u] = { +/********************************************************************* +* Language ID Descriptor +*********************************************************************/ +/* Descriptor Length */ 0x04u, +/* DescriptorType: STRING */ 0x03u, +/* Language Id */ 0x09u, 0x04u, +/********************************************************************* +* String Descriptor: "SCSI2SD" +*********************************************************************/ +/* Descriptor Length */ 0x10u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'S', 0u,(uint8)'C', 0u,(uint8)'S', 0u,(uint8)'I', 0u,(uint8)'2', 0u, + (uint8)'S', 0u,(uint8)'D', 0u, +/********************************************************************* +* String Descriptor: "codesrc.com" +*********************************************************************/ +/* Descriptor Length */ 0x18u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'c', 0u,(uint8)'o', 0u,(uint8)'d', 0u,(uint8)'e', 0u,(uint8)'s', 0u, + (uint8)'r', 0u,(uint8)'c', 0u,(uint8)'.', 0u,(uint8)'c', 0u,(uint8)'o', 0u, + (uint8)'m', 0u, +/*********************************************************************/ +/* Marks the end of the list. */ 0x00u}; +/*********************************************************************/ + +/********************************************************************* +* Serial Number String Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10] = { +/* Descriptor Length */ 0x0Au, +/* DescriptorType: STRING */ 0x03u, +(uint8)'1', 0u,(uint8)'2', 0u,(uint8)'3', 0u,(uint8)'4', 0u +}; + +/********************************************************************* +* HID Report Descriptor: Generic HID - Vendor FF00 +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[41u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, +USBFS_HID_RPT_1_SIZE_MSB, +/* USAGE_PAGE */ 0x06u, 0x00u, 0xFFu, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ +/********************************************************************* +* HID Report Descriptor: Generic HID - Vendor FF01 +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR2[41u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_2_SIZE_LSB, +USBFS_HID_RPT_2_SIZE_MSB, +/* USAGE_PAGE */ 0x06u, 0x01u, 0xFFu, +/* USAGE */ 0x09u, 0x01u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ + +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, NULL}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */ +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, NULL}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR2[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[50]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_HID_RPT_STORAGE */ + +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE} +}; +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE} +}; +/********************************************************************* +* Endpoint Setting Table -- This table contain the endpoint setting +* for each endpoint in the configuration. It +* contains the necessary information to +* configure the endpoint hardware for each +* interface and alternate setting. +*********************************************************************/ +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u}, +{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u}, +{0x01u, 0x00u, 0x03u, 0x03u, 0x0040u, 0x03u}, +{0x01u, 0x00u, 0x84u, 0x03u, 0x0040u, 0x03u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u] = { +0x03u, 0x03u +}; +/********************************************************************* +* Config Dispatch Table -- Points to the Config Descriptor and each of +* and endpoint setup table and to each +* interface table if it specifies a USB Class +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x04u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +/********************************************************************* +* Device Dispatch Table -- Points to the Device Descriptor and each of +* and Configuration Tables for this Device +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u] = { + {0x01u, &USBFS_DEVICE0_DESCR}, + {0x00u, NULL}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} +}; +/********************************************************************* +* Device Table -- Indexed by the device number. +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { + {0x01u, &USBFS_DEVICE0_TABLE} +}; + +#endif /* USER_SUPPLIED_DESCRIPTORS */ + +#if defined(USBFS_ENABLE_MSOS_STRING) + + /****************************************************************************** + * USB Microsoft OS String Descriptor + * "MSFT" identifies a Microsoft host + * "100" specifies version 1.00 + * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value + * in a host vendor device/class request + ******************************************************************************/ + + const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { + /* Descriptor Length */ 0x12u, + /* DescriptorType: STRING */ 0x03u, + /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, + (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, + /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, + /* bPad */ 0x00u + }; + + /* Extended Configuration Descriptor */ + + const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { + /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, + /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, + /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, + /* bCount - Count of device functions. */ 0x01u, + /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + /* bFirstInterfaceNumber */ 0x00u, + /* Reserved */ 0x01u, + /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', + 0x00u, 0x00u, 0x00u, + /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', + 0x00u, 0x00u, 0x00u, + /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u + }; + +#endif /* USBFS_ENABLE_MSOS_STRING */ + +/* DIE ID string descriptor for 8 bytes ID */ +#if defined(USBFS_ENABLE_IDSN_STRING) + uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c new file mode 100644 index 0000000..766f149 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_drv.c @@ -0,0 +1,796 @@ +/***************************************************************************//** +* \file USBFS_drv.c +* \version 3.10 +* +* \brief +* This file contains the Endpoint 0 Driver for the USBFS Component. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + + + +/*************************************** +* Global data allocation +***************************************/ + +volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; + +/** Contains the current configuration number, which is set by the host using a + * SET_CONFIGURATION request. This variable is initialized to zero in + * USBFS_InitComponent() API and can be read by the USBFS_GetConfiguration() + * API.*/ +volatile uint8 USBFS_configuration; + +/** Contains the current interface number.*/ +volatile uint8 USBFS_interfaceNumber; + +/** This variable is set to one after SET_CONFIGURATION and SET_INTERFACE + *requests. It can be read by the USBFS_IsConfigurationChanged() API */ +volatile uint8 USBFS_configurationChanged; + +/** Contains the current device address.*/ +volatile uint8 USBFS_deviceAddress; + +/** This is a two-bit variable that contains power status in the bit 0 + * (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote wakeup + * status (DEVICE_STATUS_REMOTE_WAKEUP) in the bit 1. This variable is + * initialized to zero in USBFS_InitComponent() API, configured by the + * USBFS_SetPowerStatus() API. The remote wakeup status cannot be set using the + * API SetPowerStatus(). */ +volatile uint8 USBFS_deviceStatus; + +volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; + +/** Contains the started device number. This variable is set by the + * USBFS_Start() or USBFS_InitComponent() APIs.*/ +volatile uint8 USBFS_device; + +/** Initialized class array for each interface. It is used for handling Class + * specific requests depend on interface class. Different classes in multiple + * alternate settings are not supported.*/ +const uint8 CYCODE *USBFS_interfaceClass; + + +/*************************************** +* Local data allocation +***************************************/ + +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; + +/** This variable is used by the communication functions to handle the current +* transfer state. +* Initialized to TRANS_STATE_IDLE in the USBFS_InitComponent() API and after a +* complete transfer in the status stage. +* Changed to the TRANS_STATE_CONTROL_READ or TRANS_STATE_CONTROL_WRITE in setup +* transaction depending on the request type. +*/ +volatile uint8 USBFS_transferState; +volatile T_USBFS_TD USBFS_currentTD; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; +volatile uint16 USBFS_transferByteCount; + + +/******************************************************************************* +* Function Name: USBFS_ep_0_Interrupt +****************************************************************************//** +* +* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. +* It dispatches setup requests and handles the data and status stages. +* +* +*******************************************************************************/ +CY_ISR(USBFS_EP_0_ISR) +{ + uint8 tempReg; + uint8 modifyReg; + +#ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK + USBFS_EP_0_ISR_EntryCallback(); +#endif /* (USBFS_EP_0_ISR_ENTRY_CALLBACK) */ + + tempReg = USBFS_EP0_CR_REG; + if ((tempReg & USBFS_MODE_ACKD) != 0u) + { + modifyReg = 1u; + if ((tempReg & USBFS_MODE_SETUP_RCVD) != 0u) + { + if ((tempReg & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + { + /* Mode not equal to NAK_IN_OUT: invalid setup */ + modifyReg = 0u; + } + else + { + USBFS_HandleSetup(); + + if ((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + { + /* SETUP bit set: exit without mode modificaiton */ + modifyReg = 0u; + } + } + } + else if ((tempReg & USBFS_MODE_IN_RCVD) != 0u) + { + USBFS_HandleIN(); + } + else if ((tempReg & USBFS_MODE_OUT_RCVD) != 0u) + { + USBFS_HandleOUT(); + } + else + { + modifyReg = 0u; + } + + /* Modify the EP0_CR register */ + if (modifyReg != 0u) + { + + tempReg = USBFS_EP0_CR_REG; + + /* Make sure that SETUP bit is cleared before modification */ + if ((tempReg & USBFS_MODE_SETUP_RCVD) == 0u) + { + /* Update count register */ + tempReg = (uint8) USBFS_ep0Toggle | USBFS_ep0Count; + USBFS_EP0_CNT_REG = tempReg; + + /* Make sure that previous write operaiton was successful */ + if (tempReg == USBFS_EP0_CNT_REG) + { + /* Repeat until next successful write operation */ + do + { + /* Init temporary variable */ + modifyReg = USBFS_ep0Mode; + + /* Unlock register */ + tempReg = (uint8) (USBFS_EP0_CR_REG & USBFS_MODE_SETUP_RCVD); + + /* Check if SETUP bit is not set */ + if (0u == tempReg) + { + /* Set the Mode Register */ + USBFS_EP0_CR_REG = USBFS_ep0Mode; + + /* Writing check */ + modifyReg = USBFS_EP0_CR_REG & USBFS_MODE_MASK; + } + } + while (modifyReg != USBFS_ep0Mode); + } + } + } + } + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_EP0_INTR); + +#ifdef USBFS_EP_0_ISR_EXIT_CALLBACK + USBFS_EP_0_ISR_ExitCallback(); +#endif /* (USBFS_EP_0_ISR_EXIT_CALLBACK) */ +} + + +/******************************************************************************* +* Function Name: USBFS_HandleSetup +****************************************************************************//** +* +* This Routine dispatches requests for the four USB request types +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleSetup(void) +{ + uint8 requestHandled; + + /* Clear register lock by SIE (read register) and clear setup bit + * (write any value in register). + */ + requestHandled = (uint8) USBFS_EP0_CR_REG; + USBFS_EP0_CR_REG = (uint8) requestHandled; + requestHandled = (uint8) USBFS_EP0_CR_REG; + + if ((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + { + /* SETUP bit is set: exit without mode modification. */ + USBFS_ep0Mode = requestHandled; + } + else + { + /* In case the previous transfer did not complete, close it out */ + USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); + + /* Check request type. */ + switch (USBFS_bmRequestTypeReg & USBFS_RQST_TYPE_MASK) + { + case USBFS_RQST_TYPE_STD: + requestHandled = USBFS_HandleStandardRqst(); + break; + + case USBFS_RQST_TYPE_CLS: + requestHandled = USBFS_DispatchClassRqst(); + break; + + case USBFS_RQST_TYPE_VND: + requestHandled = USBFS_HandleVendorRqst(); + break; + + default: + requestHandled = USBFS_FALSE; + break; + } + + /* If request is not recognized. Stall endpoint 0 IN and OUT. */ + if (requestHandled == USBFS_FALSE) + { + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleIN +****************************************************************************//** +* +* This routine handles EP0 IN transfers. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleIN(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadDataStage(); + break; + + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteStatusStage(); + break; + + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + USBFS_NoDataControlStatusStage(); + break; + + default: /* there are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleOUT +****************************************************************************//** +* +* This routine handles EP0 OUT transfers. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_HandleOUT(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadStatusStage(); + break; + + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteDataStage(); + break; + + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + break; + + default: + /* There are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_LoadEP0 +****************************************************************************//** +* +* This routine loads the EP0 data registers for OUT transfers. It uses the +* currentTD (previously initialized by the _InitControlWrite function and +* updated for each OUT transfer, and the bLastPacketSize) to determine how +* many uint8s to transfer on the current OUT. +* +* If the number of uint8s remaining is zero and the last transfer was full, +* we need to send a zero length packet. Otherwise we send the minimum +* of the control endpoint size (8) or remaining number of uint8s for the +* transaction. +* +* +* \globalvars +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded to the SIE memory in +* current packet. +* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the +* next packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_LoadEP0(void) +{ + uint8 ep0Count = 0u; + + /* Update the transfer byte count from the last transaction */ + USBFS_transferByteCount += USBFS_lastPacketSize; + + /* Now load the next transaction */ + while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) + { + USBFS_EP0_DR_BASE.epData[ep0Count] = (uint8) *USBFS_currentTD.pData; + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + ep0Count++; + USBFS_currentTD.count--; + } + + /* Support zero-length packet */ + if ((USBFS_lastPacketSize == 8u) || (ep0Count > 0u)) + { + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + else + { + /* Expect Status Stage Out */ + USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + + /* Save the packet size for next time */ + USBFS_ep0Count = (uint8) ep0Count; + USBFS_lastPacketSize = (uint8) ep0Count; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlRead +****************************************************************************//** +* +* Initialize a control read transaction. It is used to send data to the host. +* The following global variables should be initialized before this function +* called. To send zero length packet use InitZeroLengthControlTransfer +* function. +* +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_currentTD.count - counts of data to be sent. +* USBFS_currentTD.pData - data pointer. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlRead(void) +{ + uint16 xferCount; + + if (USBFS_currentTD.count == 0u) + { + (void) USBFS_InitZeroLengthControlTransfer(); + } + else + { + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + + /* Set the toggle, it gets updated in LoadEP */ + USBFS_ep0Toggle = 0u; + + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + USBFS_LoadEP0(); + } + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_InitZeroLengthControlTransfer +****************************************************************************//** +* +* Initialize a zero length data IN transfer. +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* USBFS_ep0Count - cleared, means the zero-length packet. +* USBFS_lastPacketSize - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitZeroLengthControlTransfer(void) + +{ + /* Update the state */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + + /* Set the data toggle */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + + /* Save the packet size for next time */ + USBFS_lastPacketSize = 0u; + + USBFS_ep0Count = 0u; + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadDataStage +****************************************************************************//** +* +* Handle the Data Stage of a control read transfer. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlReadDataStage(void) + +{ + USBFS_LoadEP0(); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadStatusStage +****************************************************************************//** +* +* Handle the Status Stage of a control read transfer. +* +* +* \globalvars +* USBFS_USBFS_transferByteCount - updated with last packet size. +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlReadStatusStage(void) +{ + /* Update the transfer byte count */ + USBFS_transferByteCount += USBFS_lastPacketSize; + + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlWrite +****************************************************************************//** +* +* Initialize a control write transaction +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlWrite(void) +{ + uint16 xferCount; + + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + + /* This might not be necessary */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = ((uint16)((uint16) USBFS_lengthHiReg << 8u) | ((uint16) USBFS_lengthLoReg)); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteDataStage +****************************************************************************//** +* +* Handle the Data Stage of a control write transfer +* 1. Get the data (We assume the destination was validated previously) +* 2. Update the count and data toggle +* 3. Update the mode register for the next transaction +* +* +* \globalvars +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded from the SIE memory +* in current packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteDataStage(void) +{ + uint8 ep0Count; + uint8 regIndex = 0u; + + ep0Count = (USBFS_EP0_CNT_REG & USBFS_EPX_CNT0_MASK) - USBFS_EPX_CNTX_CRC_COUNT; + + USBFS_transferByteCount += (uint8)ep0Count; + + while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) + { + *USBFS_currentTD.pData = (uint8) USBFS_EP0_DR_BASE.epData[regIndex]; + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + regIndex++; + ep0Count--; + USBFS_currentTD.count--; + } + + USBFS_ep0Count = (uint8)ep0Count; + + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteStatusStage +****************************************************************************//** +* +* Handle the Status Stage of a control write transfer +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteStatusStage(void) +{ + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitNoDataControlTransfer +****************************************************************************//** +* +* Initialize a no data control transfer +* +* \return +* requestHandled state. +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. +* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. +* USBFS_ep0Count - cleared. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_InitNoDataControlTransfer(void) +{ + USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; + + return (USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_NoDataControlStatusStage +****************************************************************************//** +* Handle the Status Stage of a no data control transfer. +* +* SET_ADDRESS is special, since we need to receive the status stage with +* the old address. +* +* \globalvars +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_deviceAddress - used to set new address and cleared +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_NoDataControlStatusStage(void) +{ + if (0u != USBFS_deviceAddress) + { + /* Update device address if we got new address. */ + USBFS_CR0_REG = (uint8) USBFS_deviceAddress | USBFS_CR0_ENABLE; + USBFS_deviceAddress = 0u; + } + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Update the completion block. */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + + /* Stall IN and OUT, no more data is expected. */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_UpdateStatusBlock +****************************************************************************//** +* +* Update the Completion Status Block for a Request. The block is updated +* with the completion code the USBFS_transferByteCount. The +* StatusBlock Pointer is set to NULL. +* +* completionCode - status. +* +* +* \globalvars +* USBFS_currentTD.pStatusBlock->status - updated by the +* completionCode parameter. +* USBFS_currentTD.pStatusBlock->length - updated. +* USBFS_currentTD.pStatusBlock - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_UpdateStatusBlock(uint8 completionCode) +{ + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = completionCode; + USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; + USBFS_currentTD.pStatusBlock = NULL; + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitializeStatusBlock +****************************************************************************//** +* +* Initialize the Completion Status Block for a Request. The completion +* code is set to USB_XFER_IDLE. +* +* Also, initializes USBFS_transferByteCount. Save some space, +* this is the only consumer. +* +* \globalvars +* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. +* USBFS_currentTD.pStatusBlock->length - cleared. +* USBFS_transferByteCount - cleared. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_InitializeStatusBlock(void) +{ + USBFS_transferByteCount = 0u; + + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; + USBFS_currentTD.pStatusBlock->length = 0u; + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c new file mode 100644 index 0000000..f6464a3 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_episr.c @@ -0,0 +1,1354 @@ +/***************************************************************************//** +* \file USBFS_episr.c +* \version 3.10 +* +* \brief +* This file contains the Data endpoint Interrupt Service Routines. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_cydmac.h" + + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if (USBFS_EP1_ISR_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP_1_ISR + ***************************************************************************//** + * + * Endpoint 1 Interrupt Service Routine + * + ******************************************************************************/ + CY_ISR(USBFS_EP_1_ISR) + { + + #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK + USBFS_EP_1_ISR_EntryCallback(); + #endif /* (USBFS_EP_1_ISR_ENTRY_CALLBACK) */ + + /* `#START EP1_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP1_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP1].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP1].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP1) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP1_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK + USBFS_EP_1_ISR_ExitCallback(); + #endif /* (USBFS_EP_1_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } + +#endif /* (USBFS_EP1_ISR_ACTIVE) */ + + +#if (USBFS_EP2_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_2_ISR + ****************************************************************************//** + * + * Endpoint 2 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_2_ISR) + { + #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK + USBFS_EP_2_ISR_EntryCallback(); + #endif /* (USBFS_EP_2_ISR_ENTRY_CALLBACK) */ + + /* `#START EP2_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP2_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP2].addr & USBFS_DIR_IN)) + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP2].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP2) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP2_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK + USBFS_EP_2_ISR_ExitCallback(); + #endif /* (USBFS_EP_2_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP2_ISR_ACTIVE) */ + + +#if (USBFS_EP3_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_3_ISR + ****************************************************************************//** + * + * Endpoint 3 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_3_ISR) + { + #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK + USBFS_EP_3_ISR_EntryCallback(); + #endif /* (USBFS_EP_3_ISR_ENTRY_CALLBACK) */ + + /* `#START EP3_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP3_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to be read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP3].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP3].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP3) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP3_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK + USBFS_EP_3_ISR_ExitCallback(); + #endif /* (USBFS_EP_3_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP3_ISR_ACTIVE) */ + + +#if (USBFS_EP4_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_4_ISR + ****************************************************************************//** + * + * Endpoint 4 Interrupt Service Routine. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_4_ISR) + { + #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK + USBFS_EP_4_ISR_EntryCallback(); + #endif /* (USBFS_EP_4_ISR_ENTRY_CALLBACK) */ + + /* `#START EP4_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP4_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP4].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP4].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP4) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP4) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP4_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK + USBFS_EP_4_ISR_ExitCallback(); + #endif /* (USBFS_EP_4_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP4_ISR_ACTIVE) */ + + +#if (USBFS_EP5_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_5_ISR + ****************************************************************************//** + * + * Endpoint 5 Interrupt Service Routine + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_5_ISR) + { + #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK + USBFS_EP_5_ISR_EntryCallback(); + #endif /* (USBFS_EP_5_ISR_ENTRY_CALLBACK) */ + + /* `#START EP5_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP5_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP5].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP5].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP5) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP5_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK + USBFS_EP_5_ISR_ExitCallback(); + #endif /* (USBFS_EP_5_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP5_ISR_ACTIVE) */ + + +#if (USBFS_EP6_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_6_ISR + ****************************************************************************//** + * + * Endpoint 6 Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_6_ISR) + { + #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK + USBFS_EP_6_ISR_EntryCallback(); + #endif /* (USBFS_EP_6_ISR_ENTRY_CALLBACK) */ + + /* `#START EP6_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP6_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP6].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP6].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP6) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP6_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK + USBFS_EP_6_ISR_ExitCallback(); + #endif /* (USBFS_EP_6_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP6_ISR_ACTIVE) */ + + +#if (USBFS_EP7_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_7_ISR + ****************************************************************************//** + * + * Endpoint 7 Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_7_ISR) + { + #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK + USBFS_EP_7_ISR_EntryCallback(); + #endif /* (USBFS_EP_7_ISR_ENTRY_CALLBACK) */ + + /* `#START EP7_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP7_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP7].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP7].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP7) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + } + + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP7) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP7_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK + USBFS_EP_7_ISR_ExitCallback(); + #endif /* (USBFS_EP_7_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP7_ISR_ACTIVE) */ + + +#if (USBFS_EP8_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_EP_8_ISR + ****************************************************************************//** + * + * Endpoint 8 Interrupt Service Routine + * + * + *******************************************************************************/ + CY_ISR(USBFS_EP_8_ISR) + { + #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK + USBFS_EP_8_ISR_EntryCallback(); + #endif /* (USBFS_EP_8_ISR_ENTRY_CALLBACK) */ + + /* `#START EP8_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + { + uint8 intEn = EA; + CyGlobalIntEnable; /* Enable nested interrupts. */ + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + + USBFS_ClearSieEpInterruptSource(USBFS_SIE_INT_EP8_INTR); + + /* Notifies user that transfer IN or OUT transfer is completed. + * IN endpoint: endpoint buffer can be reloaded, Host is read data. + * OUT endpoint: data is ready to read from endpoint buffer. + */ + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + if (0u != (USBFS_EP[USBFS_EP8].addr & USBFS_DIR_IN)) + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + { + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[USBFS_EP8].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(USBFS_EP8) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* EP_MANAGEMENT_DMA_AUTO (Ticket ID# 214187): For OUT endpoint this event is used to notify + * user that DMA has completed copying data from OUT endpoint which is not completely true. + * Because last chunk of data is being copied. + * For CY_PSOC 3/5LP: it is acceptable as DMA is really fast. + * For CY_PSOC4: this event is set in Arbiter interrupt (source is DMA_TERMIN). + */ + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + } + + #if (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + #endif /* (!(CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO)) */ + + /* `#START EP8_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK + USBFS_EP_8_ISR_ExitCallback(); + #endif /* (USBFS_EP_8_ISR_EXIT_CALLBACK) */ + + #if (CY_PSOC3 && defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + + EA = intEn; /* Restore nested interrupt configuration. */ + } + #endif /* (CY_PSOC3 && USBFS_ISR_SERVICE_MIDI_OUT) */ + } +#endif /* (USBFS_EP8_ISR_ACTIVE) */ + + +#if (USBFS_SOF_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_SOF_ISR + ****************************************************************************//** + * + * Start of Frame Interrupt Service Routine. + * + * + *******************************************************************************/ + CY_ISR(USBFS_SOF_ISR) + { + #ifdef USBFS_SOF_ISR_ENTRY_CALLBACK + USBFS_SOF_ISR_EntryCallback(); + #endif /* (USBFS_SOF_ISR_ENTRY_CALLBACK) */ + + /* `#START SOF_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_SOF_INTR); + + #ifdef USBFS_SOF_ISR_EXIT_CALLBACK + USBFS_SOF_ISR_ExitCallback(); + #endif /* (USBFS_SOF_ISR_EXIT_CALLBACK) */ + } +#endif /* (USBFS_SOF_ISR_ACTIVE) */ + + +#if (USBFS_BUS_RESET_ISR_ACTIVE) +/******************************************************************************* +* Function Name: USBFS_BUS_RESET_ISR +****************************************************************************//** +* +* USB Bus Reset Interrupt Service Routine. Calls _Start with the same +* parameters as the last USER call to _Start +* +* +*******************************************************************************/ +CY_ISR(USBFS_BUS_RESET_ISR) +{ +#ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK + USBFS_BUS_RESET_ISR_EntryCallback(); +#endif /* (USBFS_BUS_RESET_ISR_ENTRY_CALLBACK) */ + + /* `#START BUS_RESET_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_BUS_RESET_INTR); + + USBFS_ReInitComponent(); + +#ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK + USBFS_BUS_RESET_ISR_ExitCallback(); +#endif /* (USBFS_BUS_RESET_ISR_EXIT_CALLBACK) */ +} +#endif /* (USBFS_BUS_RESET_ISR_ACTIVE) */ + + +#if (USBFS_LPM_ACTIVE) +/*************************************************************************** +* Function Name: USBFS_INTR_LPM_ISR +************************************************************************//** +* +* Interrupt Service Routine for LPM of the interrupt sources. +* +* +***************************************************************************/ +CY_ISR(USBFS_LPM_ISR) +{ +#ifdef USBFS_LPM_ISR_ENTRY_CALLBACK + USBFS_LPM_ISR_EntryCallback(); +#endif /* (USBFS_LPM_ISR_ENTRY_CALLBACK) */ + + /* `#START LPM_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ClearSieInterruptSource(USBFS_INTR_SIE_LPM_INTR); + + /* `#START LPM_END_USER_CODE` Place your code here */ + + /* `#END` */ + +#ifdef USBFS_LPM_ISR_EXIT_CALLBACK + USBFS_LPM_ISR_ExitCallback(); +#endif /* (USBFS_LPM_ISR_EXIT_CALLBACK) */ +} +#endif /* (USBFS_LPM_ACTIVE) */ + + +#if (USBFS_EP_MANAGEMENT_DMA && USBFS_ARB_ISR_ACTIVE) + /*************************************************************************** + * Function Name: USBFS_ARB_ISR + ************************************************************************//** + * + * Arbiter Interrupt Service Routine. + * + * + ***************************************************************************/ + CY_ISR(USBFS_ARB_ISR) + { + uint8 arbIntrStatus; + uint8 epStatus; + uint8 ep = USBFS_EP1; + + #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK + USBFS_ARB_ISR_EntryCallback(); + #endif /* (USBFS_ARB_ISR_ENTRY_CALLBACK) */ + + /* `#START ARB_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Get pending ARB interrupt sources. */ + arbIntrStatus = USBFS_ARB_INT_SR_REG; + + while (0u != arbIntrStatus) + { + /* Check which EP is interrupt source. */ + if (0u != (arbIntrStatus & 0x01u)) + { + /* Get endpoint enable interrupt sources. */ + epStatus = (USBFS_ARB_EP_BASE.arbEp[ep].epSr & USBFS_ARB_EP_BASE.arbEp[ep].epIntEn); + + /* Handle IN endpoint buffer full event: happens only once when endpoint buffer is loaded. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_IN_BUF_FULL)) + { + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Clear data ready status. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + #if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /* Set up common area DMA with rest of data. */ + if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST) + { + USBFS_LoadNextInEP(ep, 0u); + } + else + { + USBFS_inBufFull[ep] = 1u; + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + /* Arm IN endpoint. */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_EP[ep].epMode; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if (ep == USBFS_midi_in_ep) + { + /* Clear MIDI input pointer. */ + USBFS_midiInPointer = 0u; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + } + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_SR_DMA_GNT)) + { + if (0u == (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + + /* DMA done coping data: OUT endpoint has to be re-armed by user. */ + } + } + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + + #if (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Handle DMA completion event for OUT endpoints. */ + if (0u != (epStatus & USBFS_ARB_EPX_INT_DMA_TERMIN)) + { + uint32 channelNum = USBFS_DmaChan[ep]; + + /* Restore burst counter for endpoint. */ + USBFS_DmaEpBurstCnt[ep] = USBFS_DMA_GET_BURST_CNT(USBFS_DmaEpBurstCntBackup[ep]); + + /* Disable DMA channel to restore descriptor configuration. The on-going transfer is aborted. */ + USBFS_CyDmaChDisable(channelNum); + + /* Generate DMA tr_out signal to notify USB IP that DMA is done. This signal is not generated + * when transfer was aborted (it occurs when host writes less bytes than buffer size). + */ + USBFS_CyDmaTriggerOut(USBFS_DmaBurstEndOut[ep]); + + /* Restore destination address for output endpoint. */ + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR0, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep])); + USBFS_CyDmaSetDstAddress(channelNum, USBFS_DMA_DESCR1, (void*) ((uint32) USBFS_DmaEpBufferAddrBackup[ep] + + USBFS_DMA_BYTES_PER_BURST)); + + /* Restore number of data elements to transfer which was adjusted for last burst. */ + if (0u != (USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_DESCR_REVERT)) + { + USBFS_CyDmaSetNumDataElements(channelNum, (USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + USBFS_DMA_GET_MAX_ELEM_PER_BURST(USBFS_DmaEpLastBurstEl[ep])); + } + + /* Validate descriptor 0 and 1 (also reset current state). Command to start with descriptor 0. */ + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR0); + if (USBFS_DmaEpBurstCntBackup[ep] > 1u) + { + USBFS_CyDmaValidateDescriptor(channelNum, USBFS_DMA_DESCR1); + } + USBFS_CyDmaSetDescriptor0Next(channelNum); + + /* Enable DMA channel: configuration complete. */ + USBFS_CyDmaChEnable(channelNum); + + + /* Read CR0 register to clear SIE lock. */ + (void) USBFS_SIE_EP_BASE.sieEp[ep].epCr0; + + /* Toggle all endpoint types except ISOC. */ + if (USBFS_GET_EP_TYPE(ep) != USBFS_EP_TYPE_ISOC) + { + USBFS_EP[ep].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + + /* Notify user that data has been copied from endpoint buffer. */ + USBFS_EP[ep].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && \ + !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && USBFS_ISR_SERVICE_MIDI_OUT) + if (USBFS_midi_out_ep == ep) + { + USBFS_MIDI_OUT_Service(); + } + #endif /* (USBFS_ISR_SERVICE_MIDI_OUT) */ + } + #endif /* (CY_PSOC4 && USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_CALLBACK + USBFS_ARB_ISR_Callback(ep, epStatus); + #endif /* (USBFS_ARB_ISR_CALLBACK) */ + + /* Clear serviced endpoint interrupt sources. */ + USBFS_ARB_EP_BASE.arbEp[ep].epSr = epStatus; + } + + ++ep; + arbIntrStatus >>= 1u; + } + + /* `#START ARB_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_EXIT_CALLBACK + USBFS_ARB_ISR_ExitCallback(); + #endif /* (USBFS_ARB_ISR_EXIT_CALLBACK) */ + } + +#endif /* (USBFS_ARB_ISR_ACTIVE && USBFS_EP_MANAGEMENT_DMA) */ + + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + + /****************************************************************************** + * Function Name: USBFS_EPxDmaDone + ***************************************************************************//** + * + * \internal + * Endpoint DMA Done Interrupt Service Routine basic function . + * + * \param dmaCh + * number of DMA channel + * + * \param ep + * number of USB end point + * + * \param dmaDone + * transfer completion flag + * + * \return + * updated transfer completion flag + * + ******************************************************************************/ + CY_INLINE static void USBFS_EPxDmaDone(uint8 dmaCh, uint8 ep) + { + uint32 nextAddr; + + /* Manage data elements which remain to transfer. */ + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + if(USBFS_DmaEpBurstCnt[ep] <= 2u) + { + /* Adjust length of last burst. */ + USBFS_CyDmaSetNumDataElements(dmaCh, + ((uint32) USBFS_DmaEpLastBurstEl[ep] >> USBFS_DMA_DESCR_SHIFT), + ((uint32) USBFS_DmaEpLastBurstEl[ep] & USBFS_DMA_BURST_BYTES_MASK)); + } + + + /* Advance source for input endpoint or destination for output endpoint. */ + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + /* Change source for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetSrcAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change source for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetSrcAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + else + { + /* Change destination for descriptor 0. */ + nextAddr = (uint32) USBFS_CyDmaGetDstAddress(dmaCh, USBFS_DMA_DESCR0); + nextAddr += (2u * USBFS_DMA_BYTES_PER_BURST); + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR0, (void *) nextAddr); + + /* Change destination for descriptor 1. */ + nextAddr += USBFS_DMA_BYTES_PER_BURST; + USBFS_CyDmaSetDstAddress(dmaCh, USBFS_DMA_DESCR1, (void *) nextAddr); + } + + /* Enable DMA to execute transfer as it was disabled because there were no valid descriptor. */ + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR0); + + --USBFS_DmaEpBurstCnt[ep]; + if (0u != USBFS_DmaEpBurstCnt[ep]) + { + USBFS_CyDmaValidateDescriptor(dmaCh, USBFS_DMA_DESCR1); + --USBFS_DmaEpBurstCnt[ep]; + } + + USBFS_CyDmaChEnable (dmaCh); + USBFS_CyDmaTriggerIn(USBFS_DmaReqOut[ep]); + } + else + { + /* No data to transfer. False DMA trig. Ignore. */ + } + + } + + #if (USBFS_DMA1_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP1_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 1 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP1_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP1_DMA_CH, + USBFS_EP1); + + } + #endif /* (USBFS_DMA1_ACTIVE) */ + + + #if (USBFS_DMA2_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP2_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 2 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP2_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP2_DMA_CH, + USBFS_EP2); + } + #endif /* (USBFS_DMA2_ACTIVE) */ + + + #if (USBFS_DMA3_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP3_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 3 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP3_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP3_DMA_CH, + USBFS_EP3); + } + #endif /* (USBFS_DMA3_ACTIVE) */ + + + #if (USBFS_DMA4_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP4_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 4 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP4_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP4_DMA_CH, + USBFS_EP4); + } + #endif /* (USBFS_DMA4_ACTIVE) */ + + + #if (USBFS_DMA5_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP5_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 5 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP5_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP5_DMA_CH, + USBFS_EP5); + } + #endif /* (USBFS_DMA5_ACTIVE) */ + + + #if (USBFS_DMA6_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP6_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 6 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP6_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP6_DMA_CH, + USBFS_EP6); + } + #endif /* (USBFS_DMA6_ACTIVE) */ + + + #if (USBFS_DMA7_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP7_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 7 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP7_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP7_DMA_CH, + USBFS_EP7); + } + #endif /* (USBFS_DMA7_ACTIVE) */ + + + #if (USBFS_DMA8_ACTIVE) + /****************************************************************************** + * Function Name: USBFS_EP8_DMA_DONE_ISR + ***************************************************************************//** + * + * Endpoint 8 DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + void USBFS_EP8_DMA_DONE_ISR(void) + { + + USBFS_EPxDmaDone((uint8)USBFS_EP8_DMA_CH, + USBFS_EP8); + } + #endif /* (USBFS_DMA8_ACTIVE) */ + + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + /****************************************************************************** + * Function Name: USBFS_EP_DMA_DONE_ISR + ***************************************************************************//** + * + * DMA Done Interrupt Service Routine. + * + * + ******************************************************************************/ + CY_ISR(USBFS_EP_DMA_DONE_ISR) + { + uint8 int8Status; + uint8 int17Status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + + #ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK + USBFS_EP_DMA_DONE_ISR_EntryCallback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK) */ + + /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Read clear on read status register with EP source of interrupt. */ + int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK; + int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK; + + while (int8Status != 0u) + { + while (int17Status != 0u) + { + if ((int17Status & 1u) != 0u) /* If EpX interrupt present. */ + { + /* Read Endpoint Status Register. */ + ep_status = USBFS_ARB_EP_BASE.arbEp[ep].epSr; + + if ((0u == (ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL)) && + (0u ==USBFS_inBufFull[ep])) + { + /* `#START EP_DMA_DONE_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK + USBFS_EP_DMA_DONE_ISR_Callback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_CALLBACK) */ + + /* Transfer again 2 last bytes into pre-fetch endpoint area. */ + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = 0u; + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = (USBFS_DMA_BYTES_PER_BURST * ep) - USBFS_DMA_BYTES_REPEAT; + USBFS_LoadNextInEP(ep, 1u); + + /* Set Data ready status to generate DMA request. */ + USBFS_ARB_EP_BASE.arbEp[ep].epCfg |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + } + } + + ep++; + int17Status >>= 1u; + } + + int8Status >>= 1u; + + if (int8Status != 0u) + { + /* Prepare pointer for EP8. */ + ep = USBFS_EP8; + int17Status = int8Status & 0x01u; + } + } + + /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK + USBFS_EP_DMA_DONE_ISR_ExitCallback(); + #endif /* (USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK) */ + } + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +#if (CY_PSOC4) + /*************************************************************************** + * Function Name: USBFS_IntrHandler + ************************************************************************//** + * + * Interrupt handler for Hi/Mid/Low ISRs. + * + * regCause - The cause register of interrupt. One of the three variants: + * USBFS_INTR_CAUSE_LO_REG - Low interrupts. + * USBFS_INTR_CAUSE_MED_REG - Med interrupts. + * USBFS_INTR_CAUSE_HI_REG - - High interrupts. + * + * + ***************************************************************************/ + CY_INLINE static void USBFS_IntrHandler(uint32 intrCause) + { + /* Array of pointers to component interrupt handlers. */ + static const cyisraddress USBFS_isrCallbacks[] = + { + + }; + + uint32 cbIdx = 0u; + + /* Check arbiter interrupt source first. */ + if (0u != (intrCause & USBFS_INTR_CAUSE_ARB_INTR)) + { + USBFS_isrCallbacks[USBFS_ARB_EP_INTR_NUM](); + } + + /* Check all other interrupt sources (except arbiter and resume). */ + intrCause = (intrCause & USBFS_INTR_CAUSE_CTRL_INTR_MASK) | + ((intrCause & USBFS_INTR_CAUSE_EP1_8_INTR_MASK) >> + USBFS_INTR_CAUSE_EP_INTR_SHIFT); + + /* Call interrupt handlers for active interrupt sources. */ + while (0u != intrCause) + { + if (0u != (intrCause & 0x1u)) + { + USBFS_isrCallbacks[cbIdx](); + } + + intrCause >>= 1u; + ++cbIdx; + } + } + + + /*************************************************************************** + * Function Name: USBFS_INTR_HI_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the high group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_HI_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_HI_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_MED_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the medium group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_MED_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_MED_REG); + } + + /*************************************************************************** + * Function Name: USBFS_INTR_LO_ISR + ************************************************************************//** + * + * Interrupt Service Routine for the low group of the interrupt sources. + * + * + ***************************************************************************/ + CY_ISR(USBFS_INTR_LO_ISR) + { + USBFS_IntrHandler(USBFS_INTR_CAUSE_LO_REG); + } +#endif /* (CY_PSOC4) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c new file mode 100644 index 0000000..d0bf3a4 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.c @@ -0,0 +1,451 @@ +/***************************************************************************//** +* \file USBFS_hid.c +* \version 3.10 +* +* \brief +* This file contains the USB HID Class request handler. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_hid.h" +#include "USBFS_pvt.h" + + + +#if defined(USBFS_ENABLE_HID_CLASS) + +/*************************************** +* HID Variables +***************************************/ +/** This variable is initialized in the USBFS_InitComponent() API to the + * PROTOCOL_REPORT value. It is controlled by the host using the + * HID_SET_PROTOCOL request. The value is returned to the user code by the + * USBFS_GetProtocol() API.*/ +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; + +/** This variable controls the HID report rate. It is controlled by the host + * using the HID_SET_IDLE request and used by the USBFS_UpdateHIDTimer() API to + * reload timer.*/ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + +/** This variable contains the timer counter, which is decremented and reloaded + * by the USBFS_UpdateHIDTimer() API.*/ +volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_UpdateHIDTimer +****************************************************************************//** +* +* This function updates the HID Report idle timer and returns the status and +* reloads the timer if it expires. +* +* \param interface Contains the interface number. +* +* \return +* Returns the state of the HID timer. Symbolic names and their associated values are given here: +* Return Value |Notes +* ---------------------------|------------------------------------------------ +* USBFS_IDLE_TIMER_EXPIRED | The timer expired. +* USBFS_IDLE_TIMER_RUNNING | The timer is running. +* USBFS_IDLE_TIMER_IDEFINITE | The report is sent when data or state changes. +* +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) +{ + uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; + + if(USBFS_hidIdleRate[interface] != 0u) + { + if(USBFS_hidIdleTimer[interface] > 0u) + { + USBFS_hidIdleTimer[interface]--; + stat = USBFS_IDLE_TIMER_RUNNING; + } + else + { + USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; + stat = USBFS_IDLE_TIMER_EXPIRED; + } + } + + return((uint8)stat); +} + + +/******************************************************************************* +* Function Name: USBFS_GetProtocol +****************************************************************************//** +* +* This function returns the HID protocol value for the selected interface. +* +* \param interface: Contains the interface number. +* +* \return +* Returns the protocol value. +* +*******************************************************************************/ +uint8 USBFS_GetProtocol(uint8 interface) +{ + return(USBFS_hidProtocol[interface]); +} + + +/******************************************************************************* +* Function Name: USBFS_DispatchHIDClassRqst +****************************************************************************//** +* +* This routine dispatches class requests +* +* \return +* Results of HID Class request handling: +* - USBFS_TRUE - request was handled without errors +* - USBFS_FALSE - error occurs during handling of request +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchHIDClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + uint8 interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_GET_DESCRIPTOR: + if (USBFS_wValueHiReg == USBFS_DESCR_HID_CLASS) + { + USBFS_FindHidClassDecriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else if (USBFS_wValueHiReg == USBFS_DESCR_HID_REPORT) + { + USBFS_FindReportDescriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else + { + /* Do not handle this request. */ + } + break; + + case USBFS_HID_GET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_IDLE: + /* This function does not support multiple reports per interface*/ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_PROTOCOL: + /* Validate interfaceNumber */ + if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { + /* Handle direction from host to device. */ + + switch (USBFS_bRequestReg) + { + case USBFS_HID_SET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlWrite(); + } + break; + + case USBFS_HID_SET_IDLE: + /* This function does not support multiple reports per interface */ + /* Validate interfaceNumber and Report ID (should be 0): Do not support Idle per Report ID */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg == 0u)) + { + USBFS_hidIdleRate[interfaceNumber] = (uint8)USBFS_wValueHiReg; + /* With regards to HID spec: "7.2.4 Set_Idle Request" + * Latency. If the current period has gone past the + * newly proscribed time duration, then a report + * will be generated immediately. + */ + if(USBFS_hidIdleRate[interfaceNumber] < + USBFS_hidIdleTimer[interfaceNumber]) + { + /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ + USBFS_hidIdleTimer[interfaceNumber] = 0u; + } + /* If the new request is received within 4 milliseconds + * (1 count) of the end of the current period, then the + * new request will have no effect until after the report. + */ + else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) + { + /* Do nothing. + * Let the UpdateHIDTimer() API continue to work and + * return IDLE_TIMER_EXPIRED status + */ + } + else + { /* Reload the timer*/ + USBFS_hidIdleTimer[interfaceNumber] = + USBFS_hidIdleRate[interfaceNumber]; + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_HID_SET_PROTOCOL: + /* Validate interfaceNumber and protocol (must be 0 or 1) */ + if ((interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && (USBFS_wValueLoReg <= 1u)) + { + USBFS_hidProtocol[interfaceNumber] = (uint8)USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + default: + /* Unknown class request is not handled. */ + break; + } + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USB_FindHidClassDescriptor +****************************************************************************//** +* +* This routine find Hid Class Descriptor pointer based on the Interface number +* and Alternate setting then loads the currentTD structure with the address of +* the buffer and the size. +* The HID Class Descriptor resides inside the config descriptor. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindHidClassDecriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + + interfaceN = (uint8) USBFS_wIndexLoReg; + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number*/ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ + pTmp = &pTmp[4u]; + pDescr = (volatile uint8 *)pTmp->p_list; + + /* The first byte contains the descriptor length */ + USBFS_currentTD.count = *pDescr; + USBFS_currentTD.pData = pDescr; +} + + +/******************************************************************************* +* Function Name: USB_FindReportDescriptor +****************************************************************************//** +* +* This routine find Hid Report Descriptor pointer based on the Interface +* number, then loads the currentTD structure with the address of the buffer +* and the size. +* Hid Report Descriptor is located after IN/OUT/FEATURE reports. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindReportDescriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = (uint8) USBFS_wIndexLoReg; + + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Fourth entry in the LUT starts the Hid Report Descriptor */ + pTmp = &pTmp[3u]; + pDescr = (volatile uint8 *)pTmp->p_list; + + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ + USBFS_currentTD.count = ((uint16)((uint16) pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.pData = &pDescr[2u]; +} + + +/******************************************************************************* +* Function Name: USBFS_FindReport +****************************************************************************//** +* +* This routine sets up a transfer based on the Interface number, Report Type +* and Report ID, then loads the currentTD structure with the address of the +* buffer and the size. The caller has to decide if it is a control read or +* control write. +* +* \return +* currentTD +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_FindReport(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + T_USBFS_TD *pTD; + uint8 reportType; + uint8 interfaceN; + + /* `#START HID_FINDREPORT` Place custom handling here */ + + /* `#END` */ + +#ifdef USBFS_FIND_REPORT_CALLBACK + USBFS_FindReport_Callback(); +#endif /* (USBFS_FIND_REPORT_CALLBACK) */ + + USBFS_currentTD.count = 0u; /* Init not supported condition */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + reportType = (uint8) USBFS_wValueHiReg; + interfaceN = (uint8) USBFS_wIndexLoReg; + + /* Third entry in the LUT Configuration Table starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + if (interfaceN < USBFS_MAX_INTERFACES_NUMBER) + { + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ + if ((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + { + /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ + pTmp = &pTmp[reportType - 1u]; + + /* Get reportID */ + reportType = (uint8) USBFS_wValueLoReg; + + /* Validate table support by the HID descriptor, compare table count with reportID */ + if (pTmp->c >= reportType) + { + pTD = (T_USBFS_TD *) pTmp->p_list; + pTD = &pTD[reportType]; /* select entry depend on report ID*/ + USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ + USBFS_currentTD.count = pTD->count; /* Buffer Size */ + USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; + } + } + } +} + + +/******************************************************************************* +* Additional user functions supporting HID Requests +********************************************************************************/ + +/* `#START HID_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h new file mode 100644 index 0000000..697b6e6 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_hid.h @@ -0,0 +1,71 @@ +/***************************************************************************//** +* \file USBFS_hid.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* HID class. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_hid_H) +#define CY_USBFS_USBFS_hid_H + +#include "USBFS.h" + +/*************************************** +* Prototypes of the USBFS_hid API. +***************************************/ +/** +* \addtogroup group_hid +* @{ +*/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) ; +uint8 USBFS_GetProtocol(uint8 interface) ; +/** @} hid */ + +/*************************************** +*Renamed Functions for backward compatible +***************************************/ + +#define USBFS_bGetProtocol USBFS_GetProtocol + + +/*************************************** +* Constants for USBFS_hid API. +***************************************/ + +#define USBFS_PROTOCOL_BOOT (0x00u) +#define USBFS_PROTOCOL_REPORT (0x01u) + +/* Request Types (HID Chapter 7.2) */ +#define USBFS_HID_GET_REPORT (0x01u) +#define USBFS_HID_GET_IDLE (0x02u) +#define USBFS_HID_GET_PROTOCOL (0x03u) +#define USBFS_HID_SET_REPORT (0x09u) +#define USBFS_HID_SET_IDLE (0x0Au) +#define USBFS_HID_SET_PROTOCOL (0x0Bu) + +/* Descriptor Types (HID Chapter 7.1) */ +#define USBFS_DESCR_HID_CLASS (0x21u) +#define USBFS_DESCR_HID_REPORT (0x22u) +#define USBFS_DESCR_HID_PHYSICAL (0x23u) + +/* Report Request Types (HID Chapter 7.2.1) */ +#define USBFS_HID_GET_REPORT_INPUT (0x01u) +#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) +#define USBFS_HID_GET_REPORT_FEATURE (0x03u) + +#endif /* CY_USBFS_USBFS_hid_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c new file mode 100644 index 0000000..64ecbe4 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.c @@ -0,0 +1,1391 @@ +/***************************************************************************//** +* \file USBFS_midi.c +* \version 3.10 +* +* \brief +* MIDI Streaming request handler. +* This file contains routines for sending and receiving MIDI +* messages, and handles running status in both directions. +* +* Related Document: +* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0 +* MIDI 1.0 Detailed Specification Document Version 4.2 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_midi.h" +#include "USBFS_pvt.h" + + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +/*************************************** +* MIDI Constants +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + /* The Size of the MIDI messages (MIDI Table 4-1) */ + static const uint8 CYCODE USBFS_MIDI_SIZE[] = { + /* Miscellaneous function codes(Reserved) */ 0x03u, + /* Cable events (Reserved) */ 0x03u, + /* Two-byte System Common messages */ 0x02u, + /* Three-byte System Common messages */ 0x03u, + /* SysEx starts or continues */ 0x03u, + /* Single-byte System Common Message or + SysEx ends with following single byte */ 0x01u, + /* SysEx ends with following two bytes */ 0x02u, + /* SysEx ends with following three bytes */ 0x03u, + /* Note-off */ 0x03u, + /* Note-on */ 0x03u, + /* Poly-KeyPress */ 0x03u, + /* Control Change */ 0x03u, + /* Program Change */ 0x02u, + /* Channel Pressure */ 0x02u, + /* PitchBend Change */ 0x03u, + /* Single Byte */ 0x01u + }; +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + + +/*************************************** +* Global variables +***************************************/ + + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + /** Input endpoint buffer pointer. This pointer is used as an index for the + * USBMIDI_midiInBuffer to write data. It is cleared to zero by the + * USBMIDI_MIDI_EP_Init() function.*/ + volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */ + /** Contains the midi IN endpoint number, It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in MIDI + * APIs to send data to the host.*/ + volatile uint8 USBFS_midi_in_ep; + /** Input endpoint buffer with a length equal to MIDI IN EP Max Packet Size. + * This buffer is used to save and combine the data received from the UARTs, + * generated internally by USBMIDI_PutUsbMidiIn() function messages, or both. + * The USBMIDI_MIDI_IN_Service() function transfers the data from this buffer to the host.*/ + uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /** Contains the midi OUT endpoint number. It is initialized after a + * SET_CONFIGURATION request based on a user descriptor. It is used in + * MIDI APIs to receive data from the host.*/ + volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + /** Output endpoint buffer with a length equal to MIDI OUT EP Max Packet Size. + * This buffer is used by the USBMIDI_MIDI_OUT_EP_Service() function to save + * the data received from the host. The received data is then parsed. The + * parsed data is transferred to the UARTs buffer and also used for internal + * processing by the USBMIDI_callbackLocalMidiEvent() function.*/ + uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + + static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ + /** The USBFS supports a maximum of two external Jacks. The two flag variables + * are used to represent the status of two external Jacks. These optional variables + * are allocated when External Mode is enabled. The following flags help to + * detect and generate responses for SysEx messages. The USBMIDI_MIDI2_InqFlags + * is optional and is not available when only one external Jack is configured. + * Flag | Description + * ------------------------------|--------------------------------------- + * USBMIDI_INQ_SYSEX_FLAG | Non-real-time SysEx message received. + * USBMIDI_INQ_IDENTITY_REQ_FLAG | Identity Request received. You should clear this bit when an Identity Reply message is generated. + * SysEX messages are intended for local device and shouldn't go out on the + * external MIDI jack, this flag indicates when a MIDI SysEx OUT message is + * in progress for the application */ + volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ + /** See description of \ref USBFS_MIDI1_InqFlags*/ + volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if (USBFS_ENABLE_MIDI_API != 0u) +/******************************************************************************* +* Function Name: USBFS_MIDI_Init +****************************************************************************//** +* +* This function initializes the MIDI interface and UART(s) to be ready to +* receive data from the PC and MIDI ports. +* +* \globalvars +* +* \ref USBFS_midiInBuffer: This buffer is used for saving and combining +* the received data from UART(s) and(or) generated internally by +* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() +* function transfers the data from this buffer to the PC. +* +* \ref USBFS_midiOutBuffer: This buffer is used by the +* USBFS_MIDI_OUT_Service() function for saving the received +* from the PC data, then the data are parsed and transferred to UART(s) +* buffer and to the internal processing by the +* +* \ref USBFS_callbackLocalMidiEvent function. +* +* \ref USBFS_midi_out_ep: Used as an OUT endpoint number. +* +* \ref USBFS_midi_in_ep: Used as an IN endpoint number. +* +* \ref USBFS_midiInPointer: Initialized to zero. +* +* \sideeffect +* The priority of the UART RX ISR should be higher than UART TX ISR. To do +* that this function changes the priority of the UARTs TX and RX interrupts. +* +* \reentrant +* No +* +*******************************************************************************/ +void USBFS_MIDI_Init(void) +{ +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + USBFS_midiInPointer = 0u; +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + /* Provide buffer for IN endpoint. */ + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + USBFS_MIDI_IN_BUFF_SIZE); + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /* Provide buffer for OUT endpoint. */ + (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, + USBFS_MIDI_OUT_BUFF_SIZE); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + USBFS_EnableOutEP(USBFS_midi_out_ep); +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + + /* Initialize the MIDI port(s) */ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + USBFS_MIDI_InitInterface(); +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ +} + + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /******************************************************************************* + * Function Name: USBFS_MIDI_OUT_Service + ****************************************************************************//** + * + * This function services the traffic from the USBMIDI OUT endpoint and + * sends the data to the MIDI output ports (TX UARTs). It is blocked by the + * UART when not enough space is available in the UART TX buffer. + * This function is automatically called from OUT EP ISR in DMA with + * Automatic Memory Management mode. In Manual and DMA with Manual EP + * Management modes you must call it from the main foreground task. + * + * \globalvars + * + * \ref USBFS_midiOutBuffer: Used as temporary buffer between USB + * internal memory and UART TX buffer. + * + * \ref USBFS_midi_out_ep: Used as an OUT endpoint number. + * + * \reentrant + * No + * + *******************************************************************************/ + void USBFS_MIDI_OUT_Service(void) + { + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + uint16 outLength; + uint16 outPointer; + #else + uint8 outLength; + uint8 outPointer; + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + /* Service the USB MIDI output endpoint. */ + if (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep)) + { + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #else + outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, outLength); + #else + outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, (uint16) outLength); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + #if (USBFS_EP_MANAGEMENT_DMA_MANUAL) + /* Wait until DMA complete transferring data from OUT endpoint buffer. */ + while (USBFS_OUT_BUFFER_FULL == USBFS_GetEPState(USBFS_midi_out_ep)) + { + } + + /* Enable OUT endpoint for communication with host. */ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_EP_MANAGEMENT_DMA_MANUAL) */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + if (outLength >= USBFS_EVENT_LENGTH) + { + outPointer = 0u; + while (outPointer < outLength) + { + /* In some OS OUT packet could be appended by nulls which could be skipped. */ + if (USBFS_midiOutBuffer[outPointer] == 0u) + { + break; + } + + /* Route USB MIDI to the External connection */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_00) + { + USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + } + else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_01) + { + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + else + { + /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK + USBFS_MIDI_OUT_EP_Service_Callback(); + #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */ + } + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + /* Process any local MIDI output functions */ + USBFS_callbackLocalMidiEvent(USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, + &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); + outPointer += USBFS_EVENT_LENGTH; + } + } + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Enable OUT endpoint for communiation. */ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + } +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_EP_Service + ****************************************************************************//** + * + * Services the USB MIDI IN endpoint. Non-blocking. + * Checks that previous packet was processed by HOST, otherwise service the + * input endpoint on the subsequent call. It is called from the + * USBFS_MIDI_IN_Service() and from the + * USBFS_PutUsbMidiIn() function. + * + * \globalvars + * USBFS_midi_in_ep: Used as an IN endpoint number. + * USBFS_midiInBuffer: Function loads the data from this buffer to + * the USB IN endpoint. + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * \reentrant + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_EP_Service(void) + { + /* Service the USB MIDI input endpoint */ + /* Check that previous packet was processed by HOST, otherwise service the USB later */ + if (USBFS_midiInPointer != 0u) + { + if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) + { + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); + #else + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + (uint16) USBFS_midiInPointer); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ + #if (USBFS_EP_MANAGEMENT_MANUAL) + USBFS_midiInPointer = 0u; + #endif /* (USBFS_EP_MANAGEMENT_MANUAL) */ + } + } + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_Service + ****************************************************************************//** + * + * This function services the traffic from the MIDI input ports (RX UART) + * and prepare data in USB MIDI IN endpoint buffer. + * Calls the USBFS_MIDI_IN_EP_Service() function to sent the + * data from buffer to PC. Non-blocking. Should be called from main foreground + * task. + * This function is not protected from the reentrant calls. When it is required + * to use this function in UART RX ISR to guaranty low latency, care should be + * taken to protect from reentrant calls. + * In PSoC 3, if this function is called from an ISR, you must declare this + * function as re-entrant so that different variable storage space is + * created by the compiler. This is automatically taken care for PSoC 4 and + * PSoC 5LP devices by the compiler. + * + * \globalvars + * + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * \reentrant + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_Service(void) + { + /* Service the MIDI UART inputs until either both receivers have no more + * events or until the input endpoint buffer fills up. + */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + uint8 m1 = 0u; + uint8 m2 = 0u; + + if (0u == USBFS_midiInPointer) + { + do + { + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI1 input port for a complete event */ + m1 = USBFS_MIDI1_GetEvent(); + if (m1 != 0u) + { + USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], + USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); + } + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + if (USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI2 input port for a complete event */ + m2 = USBFS_MIDI2_GetEvent(); + if (m2 != 0u) + { + USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], + USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); + } + } + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + while((USBFS_midiInPointer <= (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) && + ((m1 != 0u) || (m2 != 0u))); + } + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + /* Service the USB MIDI input endpoint */ + USBFS_MIDI_IN_EP_Service(); + } + + + /*************************************************************************** + * Function Name: USBFS_PutUsbMidiIn + ************************************************************************//** + * + * This function puts one MIDI message into the USB MIDI In endpoint buffer. + * This is a MIDI input message to the host. This function is used only if + * the device has internal MIDI input functionality. + * The USBFS_MIDI_IN_Service() function should also be called to + * send the message from local buffer to the IN endpoint. + * + * \param ic: The length of the MIDI message or command is described on the + * following table. + * Value | Description + * ---------------|--------------------------------------------------------- + * 0 | No message (should never happen) + * 1 - 3 | Complete MIDI message in midiMsg + * 3 IN EP LENGTH | Complete SySEx message(without EOSEX byte) in midiMsg. The length is limited by the max BULK EP size(64) + * MIDI_SYSEX | Start or continuation of SysEx message (put event bytes in midiMsg buffer) + * MIDI_EOSEX | End of SysEx message (put event bytes in midiMsg buffer) + * MIDI_TUNEREQ | Tune Request message (single byte system common msg) + * 0xF8 - 0xFF | Single byte real-time message + * + * \param midiMsg: pointer to MIDI message. + * \param cable: cable number. + * + * \return + * Return Value | Description + * ----------------------|----------------------------------------- + * USBFS_TRUE | Host is not ready to receive this message + * USBFS_FALSE | Success transfer + * + * \globalvars + * + * \ref USBFS_midi_in_ep: MIDI IN endpoint number used for + * sending data. + * + * \ref USBFS_midiInPointer: Checked this variable to see if + * there is enough free space in the IN endpoint buffer. If buffer is + * full, initiate sending to PC. + * + * \reentrant + * No + * + ***************************************************************************/ + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + + { + uint8 retError = USBFS_FALSE; + uint8 msgIndex; + + /* Protect PrepareInBuffer() function from concurrent calls */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_DisableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_DisableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + } + + if (USBFS_midiInPointer <= + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + if((ic < USBFS_EVENT_LENGTH) || (ic >= USBFS_MIDI_STATUS_MASK)) + { + USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); + } + else + { + /* Only SysEx message is greater than 4 bytes */ + msgIndex = 0u; + + do + { + USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], + USBFS_EVENT_BYTE3, cable); + + ic -= USBFS_EVENT_BYTE3; + msgIndex += USBFS_EVENT_BYTE3; + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + break; + } + } + } + while (ic > USBFS_EVENT_BYTE3); + + if (retError == USBFS_FALSE) + { + USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); + } + } + } + else + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_EnableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_EnableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + return (retError); + } + + + /******************************************************************************* + * Function Name: USBFS_PrepareInBuffer + ****************************************************************************//** + * + * Builds a USB MIDI event in the input endpoint buffer at the current pointer. + * Puts one MIDI message into the USB MIDI In endpoint buffer. + * + * \param ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message at pMdat[0] + * MIDI_SYSEX = Start or continuation of SysEx message + * (put eventLen bytes in buffer) + * MIDI_EOSEX = End of SysEx message + * (put eventLen bytes in buffer, + * and append MIDI_EOSEX) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * + * \param srcBuff: pointer to MIDI data + * \param eventLen: number of bytes in MIDI event + * \param cable: MIDI source port number + * + * \globalvars + * USBFS_midiInBuffer: This buffer is used for saving and combine the + * received from UART(s) and(or) generated internally by + * USBFS_PutUsbMidiIn() function messages. + * USBFS_midiInPointer: Used as an index for midiInBuffer to + * write data. + * + * \reentrant + * No + * + *******************************************************************************/ + void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + + { + uint8 srcBuffZero; + uint8 srcBuffOne; + + srcBuffZero = srcBuff[0u]; + srcBuffOne = srcBuff[1u]; + + if (ic >= (USBFS_MIDI_STATUS_MASK | USBFS_MIDI_SINGLE_BYTE_MASK)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SINGLE_BYTE | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = ic; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + } + else if((ic < USBFS_EVENT_LENGTH) || (ic == USBFS_MIDI_SYSEX)) + { + if(ic == USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SYSEX | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero < USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = (srcBuffZero >> 4u) | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_TUNEREQ) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_1BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if ((srcBuffZero == USBFS_MIDI_QFM) || (srcBuffZero == USBFS_MIDI_SONGSEL)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_2BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_SPP) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_3BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else + { + } + + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuff[2u]; + USBFS_midiInPointer++; + } + else if (ic == USBFS_MIDI_EOSEX) + { + switch (eventLen) + { + case 0u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH1 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 1u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH2 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 2u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH3 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + break; + default: + break; + } + } + else + { + } + } + +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + +/* The implementation for external serial input and output connections +* to route USB MIDI data to and from those connections. +*/ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + /******************************************************************************* + * Function Name: USBFS_MIDI_InitInterface + ****************************************************************************//** + * + * Initializes MIDI variables and starts the UART(s) hardware block(s). + * + * \sideeffect + * Change the priority of the UART(s) TX interrupts to be higher than the + * default EP ISR priority. + * + * \globalvars + * USBFS_MIDI_Event: initialized to zero. + * USBFS_MIDI_TxRunStat: initialized to zero. + * + *******************************************************************************/ + void USBFS_MIDI_InitInterface(void) + { + USBFS_MIDI1_Event.length = 0u; + USBFS_MIDI1_Event.count = 0u; + USBFS_MIDI1_Event.size = 0u; + USBFS_MIDI1_Event.runstat = 0u; + USBFS_MIDI1_TxRunStat = 0u; + USBFS_MIDI1_InqFlags = 0u; + + /* Start UART block */ + MIDI1_UART_Start(); + + /* Change the priority of the UART TX and RX interrupt */ + CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_Event.length = 0u; + USBFS_MIDI2_Event.count = 0u; + USBFS_MIDI2_Event.size = 0u; + USBFS_MIDI2_Event.runstat = 0u; + USBFS_MIDI2_TxRunStat = 0u; + USBFS_MIDI2_InqFlags = 0u; + + /* Start second UART block */ + MIDI2_UART_Start(); + + /* Change the priority of the UART TX interrupt */ + CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + + /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ + + /* `#END` */ + + #ifdef USBFS_MIDI_INIT_CALLBACK + USBFS_MIDI_Init_Callback(); + #endif /* (USBFS_MIDI_INIT_CALLBACK) */ + } + + + /******************************************************************************* + * Function Name: USBFS_ProcessMidiIn + ****************************************************************************//** + * + * Processes one byte of incoming MIDI data. + * + * mData = current MIDI input data byte + * *rxStat = pointer to a MIDI_RX_STATUS structure + * + * \return + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + *******************************************************************************/ + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + + { + uint8 midiReturn = 0u; + + /* Check for a MIDI status byte. All status bytes, except real time messages, + * which are a single byte, force the start of a new buffer cycle. + */ + if ((mData & USBFS_MIDI_STATUS_BYTE_MASK) != 0u) + { + if ((mData & USBFS_MIDI_STATUS_MASK) == USBFS_MIDI_STATUS_MASK) + { + if ((mData & USBFS_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */ + { + midiReturn = mData; + } + else /* System Common Messages */ + { + switch (mData) + { + case USBFS_MIDI_SYSEX: + rxStat->msgBuff[0u] = USBFS_MIDI_SYSEX; + rxStat->runstat = USBFS_MIDI_SYSEX; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_EOSEX: + rxStat->runstat = 0u; + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_EOSEX; + break; + case USBFS_MIDI_SPP: + rxStat->msgBuff[0u] = USBFS_MIDI_SPP; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_SONGSEL: + rxStat->msgBuff[0u] = USBFS_MIDI_SONGSEL; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_QFM: + rxStat->msgBuff[0u] = USBFS_MIDI_QFM; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_TUNEREQ: + rxStat->msgBuff[0u] = USBFS_MIDI_TUNEREQ; + rxStat->runstat = 0u; + rxStat->size = 1u; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + break; + } + } + } + else /* Channel Messages */ + { + rxStat->msgBuff[0u] = mData; + rxStat->runstat = mData; + rxStat->count = 1u; + switch (mData & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->length = 2u; + break; + default: + rxStat->runstat = 0u; + rxStat->count = 0u; + break; + } + } + } + + /* Otherwise, it's a data byte */ + else + { + if (rxStat->runstat == USBFS_MIDI_SYSEX) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_SYSEX; + } + } + else if (rxStat->count > 0u) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + } + } + else if (rxStat->runstat != 0u) + { + rxStat->msgBuff[0u] = rxStat->runstat; + rxStat->msgBuff[1u] = mData; + rxStat->count = 2u; + switch (rxStat->runstat & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + rxStat->count = 0u; + break; + } + } + else + { + } + } + return (midiReturn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_GetEvent + ****************************************************************************//** + * + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * \return + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * \globalvars + * USBFS_MIDI1_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI1_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI1_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* (CY_PSOC3) */ + #else + uint8 rxBufferRead; + #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */ + + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + + if ((MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + rxBufferRead = MIDI1_UART_rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI1_UART_rxBufferWrite; + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary buffer pointer + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + { + rxData = MIDI1_UART_rxBuffer[rxBufferRead]; + /* Increment pointer with a wrap */ + rxBufferRead++; + if (rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if (rxBufferLoopDetect != 0u ) + { + MIDI1_UART_rxBufferLoopDetect = 0u; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI1_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_ProcessUsbOut + ****************************************************************************//** + * + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * \param *epBuf: pointer on MIDI event. + * + * \globalvars + * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI1_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI1_PROCESS_OUT_BEGIN` */ + + /* `#END` */ + + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI1_ProcessUsbOut_EntryCallback(); + #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK) */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + + if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if (cmd == USBFS_SYSEX) + { + if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { + /* Non-Real Time SySEx starts */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if (cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if (cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if (cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if ((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if ((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { + /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + + /* Running Status for Voice and Mode messages only. */ + if ((cmd >= USBFS_NOTE_OFF) && (cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if (USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { + /* Skip the repeated Status byte */ + i++; + } + else + { + /* Save Status byte for next event */ + USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { + /* Clear Running Status */ + USBFS_MIDI1_TxRunStat = 0u; + } + + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI1_UART_PutChar(epBuf[i]); + i++; + } + while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI1_PROCESS_OUT_END` */ + + /* `#END` */ + + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI1_ProcessUsbOut_ExitCallback(); + #endif /* (USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK) */ + } + + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + /******************************************************************************* + * Function Name: USBFS_MIDI2_GetEvent + ****************************************************************************//** + * + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * \return + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * \globalvars + * USBFS_MIDI2_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI2_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + + #if (MIDI2_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* (CY_PSOC3) */ + #else + uint8 rxBufferRead; + #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */ + + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + + if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + rxBufferRead = MIDI2_UART_rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI2_UART_rxBufferWrite; + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary output pointer to + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + { + rxData = MIDI2_UART_rxBuffer[rxBufferRead]; + rxBufferRead++; + if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if (rxBufferLoopDetect != 0u) + { + MIDI2_UART_rxBufferLoopDetect = 0u; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI2_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_ProcessUsbOut + ****************************************************************************//** + * + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * \param *epBuf: pointer on MIDI event. + * + * \globalvars + * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI2_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI2_PROCESS_OUT_START` */ + + /* `#END` */ + + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI2_ProcessUsbOut_EntryCallback(); + #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK) */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + + if ((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { + /* SySEx starts */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if ((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + + /* Running Status for Voice and Mode messages only. */ + if ((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if (USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI2_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI2_TxRunStat = 0u; + } + + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI2_UART_PutChar(epBuf[i]); + i++; + } + while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI2_PROCESS_OUT_END` */ + + /* `#END` */ + + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI2_ProcessUsbOut_ExitCallback(); + #endif /* (USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK) */ + } +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + +#endif /* (USBFS_ENABLE_MIDI_API != 0u) */ + + +/* `#START MIDI_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h new file mode 100644 index 0000000..cf4344b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_midi.h @@ -0,0 +1,277 @@ +/***************************************************************************//** +* \file USBFS_midi.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* MIDI class support. +* +* Related Document: +* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0 +* MIDI 1.0 Detailed Specification Document Version 4.2 +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_midi_H) +#define CY_USBFS_USBFS_midi_H + +#include "USBFS.h" + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_ENABLE_MIDI_API (0u != (1u)) +#define USBFS_MIDI_EXT_MODE (0u) + + +/* Number of external interfaces (UARTs). */ +#define USBFS_ONE_EXT_INTRF (0x01u) +#define USBFS_TWO_EXT_INTRF (0x02u) + +#define USBFS_ISR_SERVICE_MIDI_OUT \ + ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_OUT_BUFF_SIZE > 0) && \ + (USBFS_EP_MANAGEMENT_DMA_AUTO)) + +#define USBFS_ISR_SERVICE_MIDI_IN \ + ((USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + + +/*************************************** +* External References +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #include "MIDI1_UART.h" +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + #include "MIDI2_UART.h" +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + + +/*************************************** +* Data Structure Definition +***************************************/ + +/* The following structure is used to hold status information for +* building and parsing incoming MIDI messages. +*/ +typedef struct +{ + uint8 length; /* expected length */ + uint8 count; /* current byte count */ + uint8 size; /* complete size */ + uint8 runstat; /* running status */ + uint8 msgBuff[4u]; /* message buffer */ +} USBFS_MIDI_RX_STATUS; + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_midi +* @{ +*/ +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + void USBFS_MIDI_Init(void) ; + + #if (USBFS_MIDI_IN_BUFF_SIZE > 0u) + void USBFS_MIDI_IN_Service(void) ; + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) ; + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0u) */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0u) + void USBFS_MIDI_OUT_Service(void) ; + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0u) */ +#endif /* (USBFS_ENABLE_MIDI_API != 0u) */ + + +/******************************************************************************* +* Callback Function Prototypes +*******************************************************************************/ + +/******************************************************************************* +* Function Name: USBFS_callbackLocalMidiEvent +****************************************************************************//** +* +* This is a callback function that locally processes data received from the PC +* in main.c. You should implement this function if you want to use it. It is +* called from the USB output processing routine for each MIDI output event +* processed (decoded) from the output endpoint buffer. +* +* \param cable: Cable number +* +* \param midiMsg: Pointer to the 3-byte MIDI message +* +* +***************************************************************************/ +void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) + ; +/** @} midi */ + +/*************************************** +* MIDI Constants. +***************************************/ + +/* Flag definitions for use with MIDI device inquiry */ +#define USBFS_INQ_SYSEX_FLAG (0x01u) +#define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) + +/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */ +#define USBFS_CIN_MASK (0x0Fu) +#define USBFS_RESERVED0 (0x00u) +#define USBFS_RESERVED1 (0x01u) +#define USBFS_2BYTE_COMMON (0x02u) +#define USBFS_3BYTE_COMMON (0x03u) +#define USBFS_SYSEX (0x04u) +#define USBFS_1BYTE_COMMON (0x05u) +#define USBFS_SYSEX_ENDS_WITH1 (0x05u) +#define USBFS_SYSEX_ENDS_WITH2 (0x06u) +#define USBFS_SYSEX_ENDS_WITH3 (0x07u) +#define USBFS_NOTE_OFF (0x08u) +#define USBFS_NOTE_ON (0x09u) +#define USBFS_POLY_KEY_PRESSURE (0x0Au) +#define USBFS_CONTROL_CHANGE (0x0Bu) +#define USBFS_PROGRAM_CHANGE (0x0Cu) +#define USBFS_CHANNEL_PRESSURE (0x0Du) +#define USBFS_PITCH_BEND_CHANGE (0x0Eu) +#define USBFS_SINGLE_BYTE (0x0Fu) + +#define USBFS_CABLE_MASK (0xF0u) +#define USBFS_MIDI_CABLE_00 (0x00u) +#define USBFS_MIDI_CABLE_01 (0x10u) + +#define USBFS_EVENT_BYTE0 (0x00u) +#define USBFS_EVENT_BYTE1 (0x01u) +#define USBFS_EVENT_BYTE2 (0x02u) +#define USBFS_EVENT_BYTE3 (0x03u) +#define USBFS_EVENT_LENGTH (0x04u) + +#define USBFS_MIDI_STATUS_BYTE_MASK (0x80u) +#define USBFS_MIDI_STATUS_MASK (0xF0u) +#define USBFS_MIDI_SINGLE_BYTE_MASK (0x08u) +#define USBFS_MIDI_NOTE_OFF (0x80u) +#define USBFS_MIDI_NOTE_ON (0x90u) +#define USBFS_MIDI_POLY_KEY_PRESSURE (0xA0u) +#define USBFS_MIDI_CONTROL_CHANGE (0xB0u) +#define USBFS_MIDI_PROGRAM_CHANGE (0xC0u) +#define USBFS_MIDI_CHANNEL_PRESSURE (0xD0u) +#define USBFS_MIDI_PITCH_BEND_CHANGE (0xE0u) +#define USBFS_MIDI_SYSEX (0xF0u) +#define USBFS_MIDI_EOSEX (0xF7u) +#define USBFS_MIDI_QFM (0xF1u) +#define USBFS_MIDI_SPP (0xF2u) +#define USBFS_MIDI_SONGSEL (0xF3u) +#define USBFS_MIDI_TUNEREQ (0xF6u) +#define USBFS_MIDI_ACTIVESENSE (0xFEu) + +/* MIDI Universal System Exclusive defines */ +#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) +#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) + +/* ID of target device */ +#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) + +/* Sub-ID#1*/ +#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) +#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) + +/* Sub-ID#2*/ +#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) +#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) +#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) +#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) + +/* UART TX and RX interrupt priority. */ +#if (CY_PSOC4) + #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x01u) + #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x02u) +#else + #define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) + #define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) +#endif /* (CYPSOC4) */ + + +/*************************************** +* Private Function Prototypes +***************************************/ + +void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + ; +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + void USBFS_MIDI_InitInterface(void) ; + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + ; + uint8 USBFS_MIDI1_GetEvent(void) ; + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + ; + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + uint8 USBFS_MIDI2_GetEvent(void) ; + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + ; + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + +/*************************************** +* Vars with External Linkage +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) +/** +* \addtogroup group_midi +* @{ +*/ + extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ +/** @} midi*/ + #else + extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* (USBFS_MIDI_IN_BUFF_SIZE >=256) */ +/** +* \addtogroup group_midi +* @{ +*/ + extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ +/** @} midi */ +#endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + + +/*************************************** +* The following code is DEPRECATED and +* must not be used. +***************************************/ + +#define USBFS_MIDI_EP_Init USBFS_MIDI_Init +#define USBFS_MIDI_OUT_EP_Service USBFS_MIDI_OUT_Service + +#endif /* (CY_USBFS_USBFS_midi_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c new file mode 100644 index 0000000..20a9a86 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.c @@ -0,0 +1,150 @@ +/***************************************************************************//** +* \file USBFS_cdc.c +* \version 3.10 +* +* \brief +* This file contains the USB MSC Class request handler and global API for MSC +* class. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* \copyright +* Copyright 2012-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_msc.h" +#include "USBFS_pvt.h" + + +#if (USBFS_HANDLE_MSC_REQUESTS) + +/*************************************** +* Internal variables +***************************************/ + +static uint8 USBFS_lunCount = USBFS_MSC_LUN_NUMBER; + + +/******************************************************************************* +* Function Name: USBFS_DispatchMSCClassRqst +****************************************************************************//** +* +* \internal +* This routine dispatches MSC class requests. +* +* \return +* Status of request processing: handled or not handled. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchMSCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + /* Get request data. */ + uint16 value = USBFS_GET_UINT16(USBFS_wValueHiReg, USBFS_wValueLoReg); + uint16 dataLength = USBFS_GET_UINT16(USBFS_wLengthHiReg, USBFS_wLengthLoReg); + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + if (USBFS_MSC_GET_MAX_LUN == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_GET_MAX_LUN_WVALUE) && + (dataLength == USBFS_MSC_GET_MAX_LUN_WLENGTH)) + { + /* Reply to Get Max LUN request: setup control read. */ + USBFS_currentTD.pData = &USBFS_lunCount; + USBFS_currentTD.count = USBFS_MSC_GET_MAX_LUN_WLENGTH; + + requestHandled = USBFS_InitControlRead(); + } + } + } + else + { + /* Handle direction from host to device. */ + + if (USBFS_MSC_RESET == USBFS_bRequestReg) + { + /* Check request fields. */ + if ((value == USBFS_MSC_RESET_WVALUE) && + (dataLength == USBFS_MSC_RESET_WLENGTH)) + { + /* Handle to Bulk-Only Reset request: no data control transfer. */ + USBFS_currentTD.count = USBFS_MSC_RESET_WLENGTH; + + #ifdef USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK + USBFS_DispatchMSCClass_MSC_RESET_RQST_Callback(); + #endif /* (USBFS_DISPATCH_MSC_CLASS_MSC_RESET_RQST_CALLBACK) */ + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + } + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_SetLunCount +****************************************************************************//** +* +* This function sets the number of logical units supported in the application. +* The default number of logical units is set in the component customizer. +* +* \param lunCount: Count of the logical units. Valid range is between 1 and 16. +* +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_MSC_SetLunCount(uint8 lunCount) +{ + USBFS_lunCount = (lunCount - 1u); +} + + +/******************************************************************************* +* Function Name: USBFS_MSC_GetLunCount +****************************************************************************//** +* +* This function returns the number of logical units. +* +* \return +* Number of the logical units. +* +* \globalvars +* USBFS_lunCount - stores number of LUN (logical units). +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_MSC_GetLunCount(void) +{ + return (USBFS_lunCount + 1u); +} + +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h new file mode 100644 index 0000000..551900f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_msc.h @@ -0,0 +1,64 @@ +/***************************************************************************//** +* \file USBFS_msc.h +* \version 3.10 +* +* \brief +* This file provides function prototypes and constants for the USBFS component +* MSC class support. +* +* Related Document: +* Device Class Definition for Mass Storage (MSC) Version TDB +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_msc_H) +#define CY_USBFS_USBFS_msc_H + +#include "USBFS.h" + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_HANDLE_MSC_REQUESTS (0u != (1u)) +#define USBFS_MSC_LUN_NUMBER (1u - 1u) + + +/*************************************** +* Function Prototypes +***************************************/ +/** +* \addtogroup group_msc +* @{ +*/ +#if (USBFS_HANDLE_MSC_REQUESTS) + void USBFS_MSC_SetLunCount(uint8 lunCount) ; + uint8 USBFS_MSC_GetLunCount(void) ; +#endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +/** @} msc */ + +/*************************************** +* Constants +***************************************/ + +/* MSC Class-Specific requests */ +#define USBFS_MSC_RESET (0xFFu) +#define USBFS_MSC_GET_MAX_LUN (0xFEu) + +/* MSC Class-Specific requests constant fields. */ +#define USBFS_MSC_RESET_WVALUE (0u) +#define USBFS_MSC_RESET_WLENGTH (0u) + +#define USBFS_MSC_GET_MAX_LUN_WVALUE (0u) +#define USBFS_MSC_GET_MAX_LUN_WLENGTH (1u) + +#endif /* CY_USBFS_USBFS_msc_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c new file mode 100644 index 0000000..64fae06 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pm.c @@ -0,0 +1,332 @@ +/***************************************************************************//** +* \file USBFS_pm.c +* \version 3.10 +* +* \brief +* This file provides Suspend/Resume APIs implementation. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" +#include "USBFS_Dp.h" + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Local data allocation +***************************************/ + +static USBFS_BACKUP_STRUCT USBFS_backup; + +#if (USBFS_DP_ISR_ACTIVE) + /******************************************************************************* + * Function Name: USBFS_DP_ISR + ****************************************************************************//** + * + * This Interrupt Service Routine handles DP pin changes for wake-up from + * the sleep mode. + * + *******************************************************************************/ + CY_ISR(USBFS_DP_ISR) + { + #ifdef USBFS_DP_ISR_ENTRY_CALLBACK + USBFS_DP_ISR_EntryCallback(); + #endif /* (USBFS_DP_ISR_ENTRY_CALLBACK) */ + + /* `#START DP_USER_CODE` Place your code here */ + + /* `#END` */ + + (void) USBFS_Dp_ClearInterrupt(); + + #ifdef USBFS_DP_ISR_EXIT_CALLBACK + USBFS_DP_ISR_ExitCallback(); + #endif /* (USBFS_DP_ISR_EXIT_CALLBACK) */ + } +#endif /* (USBFS_DP_ISR_ACTIVE) */ + + +/******************************************************************************* +* Function Name: USBFS_SaveConfig +****************************************************************************//** +* +* Saves the current user configuration. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_SaveConfig(void) +{ + /* Empty function added for the compatibility purpose. */ +} + + +/******************************************************************************* +* Function Name: USBFS_RestoreConfig +****************************************************************************//** +* +* Restores the current user configuration. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_RestoreConfig(void) +{ + if (USBFS_configuration != 0u) + { + USBFS_ConfigReg(); + USBFS_EpStateInit(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Suspend +****************************************************************************//** +* +* This function prepares the USBFS component to enter low power mode. The +* interrupt on falling edge on Dp pin is configured to wakeup device when the +* host drives resume condition. The pull-up is enabled on the Dp line while +* device is in low power mode. The supported low power modes are Deep Sleep +* (PSoC 4200L) and Sleep (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called before +* entering Sleep. +* +* *Note* After enter low power mode, the data which is left in the IN or OUT +* endpoint buffers is not restored after wakeup and lost. Therefore it should +* be stored in the SRAM for OUT endpoint or read by the host for IN endpoint +* before enter low power mode. +* +* \globalvars +* USBFS_backup.enable: modified. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Suspend(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + if (0u != (USBFS_CR0_REG & USBFS_CR0_ENABLE)) + { + /* USB block is enabled. */ + USBFS_backup.enableState = 1u; + + #if (USBFS_EP_MANAGEMENT_DMA) + USBFS_Stop_DMA(USBFS_MAX_EP); + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + #if (CY_PSOC4) + /* Suspend enter sequence. */ + USBFS_POWER_CTRL_REG |= (USBFS_POWER_CTRL_SUSPEND | + USBFS_POWER_CTRL_SUSPEND_DEL); + + /* Store state of USB regulator and disable it. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint32) ~USBFS_CR1_REG_ENABLE; + + /* Store SIE interrupt sources. Valid bits are 0 - 4. */ + USBFS_backup.intrSeiMask = (uint8) USBFS_INTR_SIE_MASK_REG; + + #else + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled. */ + USBFS_USBIO_CR0_REG &= (uint8) ~USBFS_USBIO_CR0_TEN; + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /*~50ns delay. */ + + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ + USBFS_PM_USB_CR0_REG &= (uint8) ~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Disable the SIE. */ + USBFS_CR0_REG &= (uint8) ~USBFS_CR0_ENABLE; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_50NS); /* ~50ns delay. */ + /* Store mode and disable VRegulator. */ + USBFS_backup.mode = (uint8) (USBFS_CR1_REG & USBFS_CR1_REG_ENABLE); + USBFS_CR1_REG &= (uint8) ~USBFS_CR1_REG_ENABLE; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ + + /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG &= (uint8) ~USBFS_PM_USB_CR0_REF_EN; + + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pull-up. */ + USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; + + /* Disable USBFS block. */ + /* Clear power active and standby mode templates: disable USB block. */ + USBFS_PM_ACT_CFG_REG &= (uint8) ~USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG &= (uint8) ~USBFS_PM_STBY_EN_FSUSB; + + CyDelayUs(USBFS_WAIT_REG_STABILITY_1US); /* min 0.5us delay required. */ + #endif /* (CY_PSOC4) */ + } + else + { + USBFS_backup.enableState = 0u; + } + + CyExitCriticalSection(enableInterrupts); + +#if (USBFS_DP_ISR_ACTIVE) + /* Clear active mode Dp interrupt source history. */ + (void) USBFS_Dp_ClearInterrupt(); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + + CyIntEnable (USBFS_DP_INTC_VECT_NUM); +#endif /* (USBFS_DP_ISR_ACTIVE). */ +} + + +/******************************************************************************* +* Function Name: USBFS_Resume +****************************************************************************//** +* +* This function prepares the USBFS component for active mode operation after +* exit low power mode. It restores the component active mode configuration such +* as device address assigned previously by the host, endpoints buffer and disables +* interrupt on Dp pin. +* The supported low power modes are Deep Sleep (PSoC 4200L) and Sleep +* (PSoC 3/ PSoC 5LP). +* +* *Note* For PSoC 4200L devices, this function should not be called after +* exiting Sleep. +* +* *Note* To resume communication with the host, the data endpoints must be +* managed: the OUT endpoints must be enabled and IN endpoints must be loaded +* with data. For DMA with Automatic Buffer Management, all endpoints buffers +* must be initialized again before making them available to the host. +* +* +* \globalvars +* USBFS_backup - checked. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Resume(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + + if (0u != USBFS_backup.enableState) + { + #if (USBFS_DP_ISR_ACTIVE) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_ACTIVE) */ + + #if (CY_PSOC4) + /* Enable clock to USB IP. */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_CSR_CLK_EN; + + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Restore level (hi, lo, med) for each interrupt source. */ + USBFS_INTR_LVL_SEL_REG = USBFS_DEFAULT_INTR_LVL_SEL; + + /* Store SIE interrupt sources. */ + USBFS_INTR_SIE_MASK_REG = (uint32) USBFS_backup.intrSeiMask; + + /* Set EP0.CR: ACK Setup, NAK IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_NAK_IN_OUT; + + /* Restore data EP1-8 configuration. */ + USBFS_RestoreConfig(); + + /* Restore state of USB regulator and wait until it supples stable power. */ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(USBFS_WAIT_VREF_STABILITY); + + /* Suspend exit sequence. */ + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND; + CyDelayUs(USBFS_WAIT_SUSPEND_DEL_DISABLE); + USBFS_POWER_CTRL_REG &= (uint32) ~USBFS_POWER_CTRL_SUSPEND_DEL; + + #else + /* Set power active and standby mode templates: enable USB block. */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock. */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + + /* The reference is available ~40us after power restored. */ + CyDelayUs(USBFS_WAIT_VREF_RESTORE); + /* Restore state of USB regulator and wait until it supples stable power. */ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(USBFS_WAIT_VREF_STABILITY); /*~50ns delay. */ + + /* Enable USBIO. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(USBFS_WAIT_PD_PULLUP_N_ENABLE); + /* Set the USBIO pull-up enable. */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Restore arbiter configuration for DMA transfers. */ + #if (USBFS_EP_MANAGEMENT_DMA) + #if (USBFS_ARB_ISR_ACTIVE) + /* Enable ARB EP interrupt sources. */ + USBFS_ARB_INT_EN_REG = USBFS_DEFAULT_ARB_INT_EN; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Configure arbiter for Manual or Auto DMA operation and clear + * configuration completion. + */ + USBFS_ARB_CFG_REG = USBFS_DEFAULT_ARB_CFG; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + /* Set EP0.CR: ACK Setup, STALL IN/OUT. */ + USBFS_EP0_CR_REG = USBFS_MODE_STALL_IN_OUT; + + /* Enable the USB IP to respond to USB traffic with the last address. */ + USBFS_CR0_REG |= USBFS_CR0_ENABLE; + CyDelayCycles(USBFS_WAIT_CR0_REG_STABILITY); + + /* Enable D+ pull-up and keep USB control on IO. */ + USBFS_USBIO_CR1_REG = USBFS_USBIO_CR1_USBPUEN; + + /* Restore data EP1-8 configuration. */ + USBFS_RestoreConfig(); + #endif /* (CY_PSOC4) */ + } + + CyExitCriticalSection(enableInterrupts); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h new file mode 100644 index 0000000..6e662a2 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_pvt.h @@ -0,0 +1,412 @@ +/***************************************************************************//** +* \file .h +* \version 3.10 +* +* \brief +* This file provides private function prototypes and constants for the +* USBFS component. It is not intended to be used in the user project. +* +******************************************************************************** +* \copyright +* Copyright 2013-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_pvt_H) +#define CY_USBFS_USBFS_pvt_H + +#include "USBFS.h" + +#ifdef USBFS_ENABLE_AUDIO_CLASS + #include "USBFS_audio.h" +#endif /* USBFS_ENABLE_AUDIO_CLASS */ + +#ifdef USBFS_ENABLE_CDC_CLASS + #include "USBFS_cdc.h" +#endif /* USBFS_ENABLE_CDC_CLASS */ + +#if (USBFS_ENABLE_MIDI_CLASS) + #include "USBFS_midi.h" +#endif /* (USBFS_ENABLE_MIDI_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #include "USBFS_msc.h" +#endif /* (USBFS_ENABLE_MSC_CLASS) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + #include + #else + #include + #if ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + #include "USBFS_EP_DMA_Done_isr.h" + #include "USBFS_EP8_DMA_Done_SR.h" + #include "USBFS_EP17_DMA_Done_SR.h" + #endif /* ((USBFS_EP_MANAGEMENT_DMA_AUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DMA1_ACTIVE) + #include "USBFS_ep1_dma.h" + #define USBFS_EP1_DMA_CH (USBFS_ep1_dma_CHANNEL) +#endif /* (USBFS_DMA1_ACTIVE) */ + +#if (USBFS_DMA2_ACTIVE) + #include "USBFS_ep2_dma.h" + #define USBFS_EP2_DMA_CH (USBFS_ep2_dma_CHANNEL) +#endif /* (USBFS_DMA2_ACTIVE) */ + +#if (USBFS_DMA3_ACTIVE) + #include "USBFS_ep3_dma.h" + #define USBFS_EP3_DMA_CH (USBFS_ep3_dma_CHANNEL) +#endif /* (USBFS_DMA3_ACTIVE) */ + +#if (USBFS_DMA4_ACTIVE) + #include "USBFS_ep4_dma.h" + #define USBFS_EP4_DMA_CH (USBFS_ep4_dma_CHANNEL) +#endif /* (USBFS_DMA4_ACTIVE) */ + +#if (USBFS_DMA5_ACTIVE) + #include "USBFS_ep5_dma.h" + #define USBFS_EP5_DMA_CH (USBFS_ep5_dma_CHANNEL) +#endif /* (USBFS_DMA5_ACTIVE) */ + +#if (USBFS_DMA6_ACTIVE) + #include "USBFS_ep6_dma.h" + #define USBFS_EP6_DMA_CH (USBFS_ep6_dma_CHANNEL) +#endif /* (USBFS_DMA6_ACTIVE) */ + +#if (USBFS_DMA7_ACTIVE) + #include "USBFS_ep7_dma.h" + #define USBFS_EP7_DMA_CH (USBFS_ep7_dma_CHANNEL) +#endif /* (USBFS_DMA7_ACTIVE) */ + +#if (USBFS_DMA8_ACTIVE) + #include "USBFS_ep8_dma.h" + #define USBFS_EP8_DMA_CH (USBFS_ep8_dma_CHANNEL) +#endif /* (USBFS_DMA8_ACTIVE) */ + + +/*************************************** +* Private Variables +***************************************/ + +/* Generated external references for descriptors. */ +extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[73u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_TABLE[1u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[4u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[2u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[5u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[3u]; +extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; +extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; +extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[45u]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[41u]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR2[41u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE1_ALTERNATE0_HID_TABLE[5u]; + + +extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; +extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; +#if defined(USBFS_ENABLE_IDSN_STRING) + extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + +extern volatile uint8 USBFS_interfaceNumber; +extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSettingLast[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_deviceAddress; +extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +extern const uint8 CYCODE *USBFS_interfaceClass; + +extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +extern volatile T_USBFS_TD USBFS_currentTD; + +#if (USBFS_EP_MANAGEMENT_DMA) + #if (CY_PSOC4) + extern const uint8 USBFS_DmaChan[USBFS_MAX_EP]; + #else + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd [USBFS_MAX_EP]; + #endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + extern uint8 USBFS_DmaEpBurstCnt [USBFS_MAX_EP]; + extern uint8 USBFS_DmaEpLastBurstEl[USBFS_MAX_EP]; + + extern uint8 USBFS_DmaEpBurstCntBackup [USBFS_MAX_EP]; + extern uint32 USBFS_DmaEpBufferAddrBackup[USBFS_MAX_EP]; + + extern const uint8 USBFS_DmaReqOut [USBFS_MAX_EP]; + extern const uint8 USBFS_DmaBurstEndOut[USBFS_MAX_EP]; +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + extern volatile uint16 USBFS_inLength [USBFS_MAX_EP]; + extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; + extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP]; + extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* CY_PSOC4 */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + +extern volatile uint8 USBFS_ep0Toggle; +extern volatile uint8 USBFS_lastPacketSize; +extern volatile uint8 USBFS_ep0Mode; +extern volatile uint8 USBFS_ep0Count; +extern volatile uint16 USBFS_transferByteCount; + + +/*************************************** +* Private Function Prototypes +***************************************/ +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void); +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; +void USBFS_UpdateStatusBlock(uint8 completionCode) ; +uint8 USBFS_DispatchClassRqst(void) ; + +void USBFS_Config(uint8 clearAltSetting) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; +void USBFS_EpStateInit(void) ; + + +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex); +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) ; +#if (USBFS_BOS_ENABLE) + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) ; +#endif /* (USBFS_BOS_ENABLE) */ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) ;uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; + +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if (CY_PSOC3 || CY_PSOC5LP) + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +#if defined(USBFS_ENABLE_IDSN_STRING) + void USBFS_ReadDieID(uint8 descr[]) ; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 USBFS_DispatchHIDClassRqst(void) ; +#endif /* (USBFS_ENABLE_HID_CLASS) */ + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + uint8 USBFS_DispatchAUDIOClassRqst(void) ; +#endif /* (USBFS_ENABLE_AUDIO_CLASS) */ + +#if defined(USBFS_ENABLE_CDC_CLASS) + uint8 USBFS_DispatchCDCClassRqst(void) ; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + +#if (USBFS_ENABLE_MSC_CLASS) + #if (USBFS_HANDLE_MSC_REQUESTS) + uint8 USBFS_DispatchMSCClassRqst(void) ; + #endif /* (USBFS_HANDLE_MSC_REQUESTS) */ +#endif /* (USBFS_ENABLE_MSC_CLASS */ + +CY_ISR_PROTO(USBFS_EP_0_ISR); +CY_ISR_PROTO(USBFS_BUS_RESET_ISR); + +#if (USBFS_SOF_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_SOF_ISR); +#endif /* (USBFS_SOF_ISR_ACTIVE) */ + +#if (USBFS_EP1_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* (USBFS_EP1_ISR_ACTIVE) */ + +#if (USBFS_EP2_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* (USBFS_EP2_ISR_ACTIVE) */ + +#if (USBFS_EP3_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* (USBFS_EP3_ISR_ACTIVE) */ + +#if (USBFS_EP4_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* (USBFS_EP4_ISR_ACTIVE) */ + +#if (USBFS_EP5_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* (USBFS_EP5_ISR_ACTIVE) */ + +#if (USBFS_EP6_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* (USBFS_EP6_ISR_ACTIVE) */ + +#if (USBFS_EP7_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* (USBFS_EP7_ISR_ACTIVE) */ + +#if (USBFS_EP8_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* (USBFS_EP8_ISR_ACTIVE) */ + +#if (USBFS_EP_MANAGEMENT_DMA) + CY_ISR_PROTO(USBFS_ARB_ISR); +#endif /* (USBFS_EP_MANAGEMENT_DMA) */ + +#if (USBFS_DP_ISR_ACTIVE) + CY_ISR_PROTO(USBFS_DP_ISR); +#endif /* (USBFS_DP_ISR_ACTIVE) */ + +#if (CY_PSOC4) + CY_ISR_PROTO(USBFS_INTR_HI_ISR); + CY_ISR_PROTO(USBFS_INTR_MED_ISR); + CY_ISR_PROTO(USBFS_INTR_LO_ISR); + #if (USBFS_LPM_ACTIVE) + CY_ISR_PROTO(USBFS_LPM_ISR); + #endif /* (USBFS_LPM_ACTIVE) */ +#endif /* (CY_PSOC4) */ + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) +#if (CY_PSOC4) + #if (USBFS_DMA1_ACTIVE) + void USBFS_EP1_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA1_ACTIVE) */ + + #if (USBFS_DMA2_ACTIVE) + void USBFS_EP2_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA2_ACTIVE) */ + + #if (USBFS_DMA3_ACTIVE) + void USBFS_EP3_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA3_ACTIVE) */ + + #if (USBFS_DMA4_ACTIVE) + void USBFS_EP4_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA4_ACTIVE) */ + + #if (USBFS_DMA5_ACTIVE) + void USBFS_EP5_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA5_ACTIVE) */ + + #if (USBFS_DMA6_ACTIVE) + void USBFS_EP6_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA6_ACTIVE) */ + + #if (USBFS_DMA7_ACTIVE) + void USBFS_EP7_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA7_ACTIVE) */ + + #if (USBFS_DMA8_ACTIVE) + void USBFS_EP8_DMA_DONE_ISR(void); + #endif /* (USBFS_DMA8_ACTIVE) */ + +#else + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ +#endif /* (CY_PSOC4) */ +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + +/*************************************** +* Request Handlers +***************************************/ + +uint8 USBFS_HandleStandardRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; + + +/*************************************** +* HID Internal references +***************************************/ + +#if defined(USBFS_ENABLE_HID_CLASS) + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; + void USBFS_FindHidClassDecriptor(void) ; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* MIDI Internal references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + + +/*************************************** +* CDC Internal references +***************************************/ + +#if defined(USBFS_ENABLE_CDC_CLASS) + + typedef struct + { + uint8 bRequestType; + uint8 bNotification; + uint8 wValue; + uint8 wValueMSB; + uint8 wIndex; + uint8 wIndexMSB; + uint8 wLength; + uint8 wLengthMSB; + uint8 wSerialState; + uint8 wSerialStateMSB; + } t_USBFS_cdc_notification; + + uint8 USBFS_GetInterfaceComPort(uint8 interface) ; + uint8 USBFS_Cdc_EpInit( const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP, uint8 epNum, uint8 cdcComNums) ; + + extern volatile uint8 USBFS_cdc_dataInEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_dataOutEpList[USBFS_MAX_MULTI_COM_NUM]; + extern volatile uint8 USBFS_cdc_commInEpList[USBFS_MAX_MULTI_COM_NUM]; +#endif /* (USBFS_ENABLE_CDC_CLASS) */ + + +#endif /* CY_USBFS_USBFS_pvt_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c new file mode 100644 index 0000000..35b36d9 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_std.c @@ -0,0 +1,1262 @@ +/***************************************************************************//** +* \file USBFS_std.c +* \version 3.10 +* +* \brief +* This file contains the USB Standard request handler. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + +/*************************************** +* Static data allocation +***************************************/ + +#if defined(USBFS_ENABLE_FWSN_STRING) + static volatile uint8* USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* (USBFS_ENABLE_FWSN_STRING) */ + +#if defined(USBFS_ENABLE_FWSN_STRING) + /*************************************************************************** + * Function Name: USBFS_SerialNumString + ************************************************************************//** + * + * This function is available only when the User Call Back option in the + * Serial Number String descriptor properties is selected. Application + * firmware can provide the source of the USB device serial number string + * descriptor during run time. The default string is used if the application + * firmware does not use this function or sets the wrong string descriptor. + * + * \param snString: Pointer to the user-defined string descriptor. The + * string descriptor should meet the Universal Serial Bus Specification + * revision 2.0 chapter 9.6.7 + * Offset|Size|Value|Description + * ------|----|------|--------------------------------- + * 0 |1 |N |Size of this descriptor in bytes + * 1 |1 |0x03 |STRING Descriptor Type + * 2 |N-2 |Number|UNICODE encoded string + * + * *For example:* uint8 snString[16]={0x0E,0x03,'F',0,'W',0,'S',0,'N',0,'0',0,'1',0}; + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_SerialNumString(uint8 snString[]) + { + USBFS_snStringConfirm = USBFS_FALSE; + + if (snString != NULL) + { + /* Check descriptor validation */ + if ((snString[0u] > 1u) && (snString[1u] == USBFS_DESCR_STRING)) + { + USBFS_fwSerialNumberStringDescriptor = snString; + USBFS_snStringConfirm = USBFS_TRUE; + } + } + } +#endif /* USBFS_ENABLE_FWSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_HandleStandardRqst +****************************************************************************//** +* +* This Routine dispatches standard requests +* +* +* \return +* TRUE if request handled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleStandardRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + uint8 configurationN; + uint8 bmRequestType = USBFS_bmRequestTypeReg; + +#if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ +#endif /* (USBFS_ENABLE_STRINGS) */ + + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; + const T_USBFS_LUT CYCODE *pTmp; + + USBFS_currentTD.count = 0u; + + if (USBFS_RQST_DIR_D2H == (bmRequestType & USBFS_RQST_DIR_MASK)) + { + /* Control Read */ + switch (USBFS_bRequestReg) + { + case USBFS_GET_DESCRIPTOR: + if (USBFS_DESCR_DEVICE ==USBFS_wValueHiReg) + { + pTmp = USBFS_GetDeviceTablePtr(); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + + requestHandled = USBFS_InitControlRead(); + } + else if (USBFS_DESCR_CONFIG == USBFS_wValueHiReg) + { + pTmp = USBFS_GetConfigTablePtr((uint8) USBFS_wValueLoReg); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = (uint16)((uint16)(USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + + #if(USBFS_BOS_ENABLE) + else if (USBFS_DESCR_BOS == USBFS_wValueHiReg) + { + pTmp = USBFS_GetBOSPtr(); + + /* Verify that requested descriptor exists */ + if (pTmp != NULL) + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp; + USBFS_currentTD.count = ((uint16)((uint16)(USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_HI] << 8u)) | \ + (USBFS_currentTD.pData)[USBFS_BOS_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /*(USBFS_BOS_ENABLE)*/ + + #if defined(USBFS_ENABLE_STRINGS) + else if (USBFS_DESCR_STRING == USBFS_wValueHiReg) + { + /* Descriptor Strings */ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *) &USBFS_STRING_DESCRIPTORS[0u]; + + while ((USBFS_wValueLoReg > nStr) && (*pStr != 0u)) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* (USBFS_ENABLE_DESCRIPTOR_STRINGS) */ + + /* Microsoft OS String */ + #if defined(USBFS_ENABLE_MSOS_STRING) + if (USBFS_STRING_MSOS == USBFS_wValueLoReg) + { + pStr = (volatile uint8 *)& USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* (USBFS_ENABLE_MSOS_STRING) */ + + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if ((USBFS_wValueLoReg != 0u) && + (USBFS_wValueLoReg == USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT])) + { + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #elif defined(USBFS_ENABLE_FWSN_STRING) + + if(USBFS_snStringConfirm != USBFS_FALSE) + { + pStr = USBFS_fwSerialNumberStringDescriptor; + } + else + { + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + } + #else + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #endif /* (USBFS_ENABLE_IDSN_STRING) */ + } + #endif /* (USBFS_ENABLE_SN_STRING) */ + + if (*pStr != 0u) + { + USBFS_currentTD.count = *pStr; + USBFS_currentTD.pData = pStr; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /* USBFS_ENABLE_STRINGS */ + else + { + requestHandled = USBFS_DispatchClassRqst(); + } + break; + + case USBFS_GET_STATUS: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_EP[USBFS_wIndexLoReg & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_RQST_RCPT_DEV: + USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + case USBFS_GET_CONFIGURATION: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_configuration; + requestHandled = USBFS_InitControlRead(); + break; + + case USBFS_GET_INTERFACE: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_interfaceSetting[USBFS_wIndexLoReg]; + requestHandled = USBFS_InitControlRead(); + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { + /* Control Write */ + switch (USBFS_bRequestReg) + { + case USBFS_SET_ADDRESS: + /* Store address to be set in USBFS_NoDataControlStatusStage(). */ + USBFS_deviceAddress = (uint8) USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + case USBFS_SET_CONFIGURATION: + configurationN = USBFS_wValueLoReg; + + /* Verify that configuration descriptor exists */ + if(configurationN > 0u) + { + pTmp = USBFS_GetConfigTablePtr((uint8) configurationN - 1u); + } + + /* Responds with a Request Error when configuration number is invalid */ + if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u)) + { + /* Set new configuration if it has been changed */ + if(configurationN != USBFS_configuration) + { + USBFS_configuration = (uint8) configurationN; + USBFS_configurationChanged = USBFS_TRUE; + USBFS_Config(USBFS_TRUE); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_SET_INTERFACE: + if (0u != USBFS_ValidateAlternateSetting()) + { + /* Get interface number from the request. */ + interfaceNumber = USBFS_wIndexLoReg; + USBFS_interfaceNumber = (uint8) USBFS_wIndexLoReg; + + /* Check if alternate settings is changed for interface. */ + if (USBFS_interfaceSettingLast[interfaceNumber] != USBFS_interfaceSetting[interfaceNumber]) + { + USBFS_configurationChanged = USBFS_TRUE; + + /* Change alternate setting for the endpoints. */ + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) + USBFS_Config(USBFS_FALSE); + #else + USBFS_ConfigAltChanged(); + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ + } + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_CLEAR_FEATURE: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_ClearEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Clear device REMOTE_WAKEUP */ + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + case USBFS_SET_FEATURE: + switch (bmRequestType & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (USBFS_wValueLoReg == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_SetEndpointHalt(); + } + break; + + case USBFS_RQST_RCPT_DEV: + /* Set device REMOTE_WAKEUP */ + if (USBFS_wValueLoReg == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (USBFS_wIndexLoReg < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[USBFS_wIndexLoReg] &= (uint8) ~USBFS_wValueLoReg; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + + return (requestHandled); +} + + +#if defined(USBFS_ENABLE_IDSN_STRING) + /*************************************************************************** + * Function Name: USBFS_ReadDieID + ************************************************************************//** + * + * This routine read Die ID and generate Serial Number string descriptor. + * + * \param descr: pointer on string descriptor. This string size has to be equal or + * greater than USBFS_IDSN_DESCR_LENGTH. + * + * + * \reentrant + * No. + * + ***************************************************************************/ + void USBFS_ReadDieID(uint8 descr[]) + { + const char8 CYCODE hex[] = "0123456789ABCDEF"; + uint8 i; + uint8 j = 0u; + uint8 uniqueId[8u]; + + if (NULL != descr) + { + /* Initialize descriptor header. */ + descr[0u] = USBFS_IDSN_DESCR_LENGTH; + descr[1u] = USBFS_DESCR_STRING; + + /* Unique ID size is 8 bytes. */ + CyGetUniqueId((uint32 *) uniqueId); + + /* Fill descriptor with unique device ID. */ + for (i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + { + descr[i] = (uint8) hex[(uniqueId[j] >> 4u)]; + descr[i + 1u] = 0u; + descr[i + 2u] = (uint8) hex[(uniqueId[j] & 0x0Fu)]; + descr[i + 3u] = 0u; + ++j; + } + } + } +#endif /* (USBFS_ENABLE_IDSN_STRING) */ + + +/******************************************************************************* +* Function Name: USBFS_ConfigReg +****************************************************************************//** +* +* This routine configures hardware registers from the variables. +* It is called from USBFS_Config() function and from RestoreConfig +* after Wakeup. +* +*******************************************************************************/ +void USBFS_ConfigReg(void) +{ + uint8 ep; + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + uint8 epType = 0u; +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Go thought all endpoints and set hardware configuration */ + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) + { + USBFS_ARB_EP_BASE.arbEp[ep].epCfg = USBFS_ARB_EPX_CFG_DEFAULT; + + #if (USBFS_EP_MANAGEMENT_DMA) + /* Enable arbiter endpoint interrupt sources */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn = USBFS_ARB_EPX_INT_MASK; + #endif /* (USBFS_EP_MANAGEMENT_DMA) */ + + if (USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + { + if (0u != (USBFS_EP[ep].addr & USBFS_DIR_IN)) + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint. */ + USBFS_ARB_EP_BASE.arbEp[ep].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO && CY_PSOC4) */ + } + else + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* (CY_PSOC4): DMA_TERMIN for OUT endpoint is set above. */ + + /* Prepare endpoint type mask. */ + epType |= (uint8) (0x01u << (ep - USBFS_EP1)); + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + } + else + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_STALL_DATA_EP; + } + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[ep].rwRa16 = (uint32) USBFS_EP[ep].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[ep].rwWa16 = (uint32) USBFS_EP[ep].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[ep].rwRa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwRaMsb = HI8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWa = LO8(USBFS_EP[ep].buffOffset); + USBFS_ARB_EP_BASE.arbEp[ep].rwWaMsb = HI8(USBFS_EP[ep].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + +#if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* BUF_SIZE depend on DMA_THRESS value:0x55-32 bytes 0x44-16 bytes 0x33-8 bytes 0x22-4 bytes 0x11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; + + /* Configure DMA burst threshold */ +#if (CY_PSOC4) + USBFS_DMA_THRES16_REG = USBFS_DMA_BYTES_PER_BURST; +#else + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; + USBFS_DMA_THRES_MSB_REG = 0u; +#endif /* (CY_PSOC4) */ + USBFS_EP_ACTIVE_REG = USBFS_DEFAULT_ARB_INT_EN; + USBFS_EP_TYPE_REG = epType; + + /* Cfg_cmp bit set to 1 once configuration is complete. */ + /* Lock arbiter configtuation */ + USBFS_ARB_CFG_REG |= (uint8) USBFS_ARB_CFG_CFG_CMP; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG &= (uint8) ~USBFS_ARB_CFG_CFG_CMP; + +#endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Enable interrupt SIE interurpt source from EP0-EP1 */ + USBFS_SIE_EP_INT_EN_REG = (uint8) USBFS_DEFAULT_SIE_EP_INT_EN; +} + + +/******************************************************************************* +* Function Name: USBFS_EpStateInit +****************************************************************************//** +* +* This routine initialize state of Data end points based of its type: +* IN - USBFS_IN_BUFFER_EMPTY (USBFS_EVENT_PENDING) +* OUT - USBFS_OUT_BUFFER_EMPTY (USBFS_NO_EVENT_PENDING) +* +*******************************************************************************/ +void USBFS_EpStateInit(void) +{ + uint8 i; + + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + if (0u != (USBFS_EP[i].addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + } + } + +} + + +/******************************************************************************* +* Function Name: USBFS_Config +****************************************************************************//** +* +* This routine configures endpoints for the entire configuration by scanning +* the configuration descriptor. +* +* \param clearAltSetting: It configures the bAlternateSetting 0 for each interface. +* +* USBFS_interfaceClass - Initialized class array for each interface. +* It is used for handling Class specific requests depend on interface class. +* Different classes in multiple Alternate settings does not supported. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_Config(uint8 clearAltSetting) +{ + uint8 ep; + uint8 curEp; + uint8 i; + uint8 epType; + const uint8 *pDescr; + + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + uint16 buffCount = 0u; + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Clear endpoints settings */ + for (ep = 0u; ep < USBFS_MAX_EP; ++ep) + { + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].bufferSize = 0u; + USBFS_EP[ep].interface = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + } + + /* Clear Alternate settings for all interfaces. */ + if (0u != clearAltSetting) + { + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; ++i) + { + USBFS_interfaceSetting[i] = 0u; + USBFS_interfaceSettingLast[i] = 0u; + } + } + + /* Init Endpoints and Device Status if configured */ + if (USBFS_configuration > 0u) + { + #if defined(USBFS_ENABLE_CDC_CLASS) + uint8 cdcComNums = 0u; + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + + /* Set Power status for current configuration */ + pDescr = (const uint8 *)pTmp->p_list; + if ((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + { + USBFS_deviceStatus |= (uint8) USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8) ~USBFS_DEVICE_STATUS_SELF_POWERED; + } + + /* Move to next element */ + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + #if (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) + /* Configure for dynamic EP memory allocation */ + /* p_list points the endpoint setting table. */ + pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + + for (i = 0u; i < ep; i++) + { + /* Compare current Alternate setting with EP Alt */ + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + curEp = pEP->addr & USBFS_DIR_UNUSED; + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + else + { + /* OUT Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = curEp; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + + #if(defined (USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, curEp, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + } + + pEP = &pEP[1u]; + } + + #else + for (i = USBFS_EP1; i < USBFS_MAX_EP; ++i) + { + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + /* Find max length for each EP and select it (length could be different in different Alt settings) */ + /* but other settings should be correct with regards to Interface alt Setting */ + + for (curEp = 0u; curEp < ep; ++curEp) + { + if (i == (pEP->addr & USBFS_DIR_UNUSED)) + { + /* Compare endpoint buffers size with current size to find greater. */ + if (USBFS_EP[i].bufferSize < pEP->bufferSize) + { + USBFS_EP[i].bufferSize = pEP->bufferSize; + } + + /* Compare current Alternate setting with EP Alt */ + if (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_IN_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_MIDI_OUT_BUFF_SIZE > 0)) + if ((pEP->bMisc == USBFS_CLASS_AUDIO) && (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* (USBFS_ENABLE_MIDI_STREAMING) */ + } + + #if (defined(USBFS_ENABLE_CDC_CLASS)) + if((pEP->bMisc == USBFS_CLASS_CDC_DATA) ||(pEP->bMisc == USBFS_CLASS_CDC)) + { + cdcComNums = USBFS_Cdc_EpInit(pEP, i, cdcComNums); + } + #endif /* (USBFS_ENABLE_CDC_CLASS) */ + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + break; /* Use first EP setting in Auto memory management */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + } + + pEP = &pEP[1u]; + } + } + #endif /* (USBFS_EP_MANAGEMENT_MANUAL && USBFS_EP_ALLOC_DYNAMIC) */ + + /* Init class array for each interface and interface number for each EP. + * It is used for handling Class specific requests directed to either an + * interface or the endpoint. + */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Configure interface number for each EP */ + USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; + pEP = &pEP[1u]; + } + + /* Init pointer on interface class table */ + USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); + + /* Set the endpoint buffer addresses */ + #if (!USBFS_EP_MANAGEMENT_DMA_AUTO) + buffCount = 0u; + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ++ep) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + + #if (USBFS_GEN_16BITS_EP_ACCESS) + /* Align EP buffers to be event size to access 16-bits DR register. */ + buffCount += (0u != (buffCount & 0x01u)) ? 1u : 0u; + #endif /* (USBFS_GEN_16BITS_EP_ACCESS) */ + } + #endif /* (!USBFS_EP_MANAGEMENT_DMA_AUTO) */ + + /* Configure hardware registers */ + USBFS_ConfigReg(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_ConfigAltChanged +****************************************************************************//** +* +* This routine update configuration for the required endpoints only. +* It is called after SET_INTERFACE request when Static memory allocation used. +* +* \reentrant +* No. +* +*******************************************************************************/ +void USBFS_ConfigAltChanged(void) +{ + uint8 ep; + uint8 curEp; + uint8 epType; + uint8 i; + uint8 interfaceNum; + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Init Endpoints and Device Status if configured */ + if (USBFS_configuration > 0u) + { + /* Get number of endpoints configurations (ep). */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + pTmp = &pTmp[1u]; + ep = pTmp->c; + + /* Get pointer to endpoints setting table (pEP). */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + + /* Look through all possible endpoint configurations. Find endpoints + * which belong to current interface and alternate settings for + * re-configuration. + */ + interfaceNum = USBFS_interfaceNumber; + for (i = 0u; i < ep; i++) + { + /* Find endpoints which belong to current interface and alternate settings. */ + if ((interfaceNum == pEP->interface) && + (USBFS_interfaceSetting[interfaceNum] == pEP->altSetting)) + { + curEp = ((uint8) pEP->addr & USBFS_DIR_UNUSED); + epType = ((uint8) pEP->attributes & USBFS_EP_TYPE_MASK); + + /* Change the SIE mode for the selected EP to NAK ALL */ + USBFS_EP[curEp].epToggle = 0u; + USBFS_EP[curEp].addr = pEP->addr; + USBFS_EP[curEp].attrib = pEP->attributes; + USBFS_EP[curEp].bufferSize = pEP->bufferSize; + + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* IN Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_IN_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_EVENT_PENDING; + } + else + { + /* OUT Endpoint */ + USBFS_EP[curEp].epMode = USBFS_GET_ACTIVE_OUT_EP_CR0_MODE(epType); + USBFS_EP[curEp].apiEpState = USBFS_NO_EVENT_PENDING; + } + + /* Make SIE to NAK any endpoint requests */ + USBFS_SIE_EP_BASE.sieEp[curEp].epCr0 = USBFS_MODE_NAK_IN_OUT; + + #if (USBFS_EP_MANAGEMENT_DMA_AUTO) + /* Clear IN data ready. */ + USBFS_ARB_EP_BASE.arbEp[curEp].epCfg &= (uint8) ~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + /* Select endpoint number of reconfiguration */ + USBFS_DYN_RECONFIG_REG = (uint8) ((curEp - 1u) << USBFS_DYN_RECONFIG_EP_SHIFT); + + /* Request for dynamic re-configuration of endpoint. */ + USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; + + /* Wait until block is ready for re-configuration */ + while (0u == (USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS)) + { + } + + /* Once DYN_RECONFIG_RDY_STS bit is set, FW can change the EP configuration. */ + /* Change EP Type with new direction */ + if (0u != (pEP->addr & USBFS_DIR_IN)) + { + /* Set endpoint type: 0 - IN and 1 - OUT. */ + USBFS_EP_TYPE_REG &= (uint8) ~(uint8)((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Clear DMA_TERMIN for IN endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn &= (uint32) ~USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ + } + else + { + /* Set endpoint type: 0 - IN and 1- OUT. */ + USBFS_EP_TYPE_REG |= (uint8) ((uint8) 0x01u << (curEp - 1u)); + + #if (CY_PSOC4) + /* Set DMA_TERMIN for OUT endpoint */ + USBFS_ARB_EP_BASE.arbEp[curEp].epIntEn |= (uint32) USBFS_ARB_EPX_INT_DMA_TERMIN; + #endif /* (CY_PSOC4) */ + } + + /* Complete dynamic re-configuration: all endpoint related status and signals + * are set into the default state. + */ + USBFS_DYN_RECONFIG_REG &= (uint8) ~USBFS_DYN_RECONFIG_ENABLE; + + #else + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt0 = HI8(USBFS_EP[curEp].bufferSize); + USBFS_SIE_EP_BASE.sieEp[curEp].epCnt1 = LO8(USBFS_EP[curEp].bufferSize); + + #if (CY_PSOC4) + USBFS_ARB_EP16_BASE.arbEp[curEp].rwRa16 = (uint32) USBFS_EP[curEp].buffOffset; + USBFS_ARB_EP16_BASE.arbEp[curEp].rwWa16 = (uint32) USBFS_EP[curEp].buffOffset; + #else + USBFS_ARB_EP_BASE.arbEp[curEp].rwRa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwRaMsb = HI8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWa = LO8(USBFS_EP[curEp].buffOffset); + USBFS_ARB_EP_BASE.arbEp[curEp].rwWaMsb = HI8(USBFS_EP[curEp].buffOffset); + #endif /* (CY_PSOC4) */ + #endif /* (USBFS_EP_MANAGEMENT_DMA_AUTO) */ + } + + pEP = &pEP[1u]; /* Get next EP element */ + } + + /* The main loop has to re-enable DMA and OUT endpoint */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfigTablePtr +****************************************************************************//** +* +* This routine returns a pointer a configuration table entry +* +* \param confIndex: Configuration Index +* +* \return +* Device Descriptor pointer or NULL when descriptor does not exist. +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) + +{ + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the second entry point to the BOS Descriptor + * the rest configuration entries. + * Set pointer to the first Configuration Descriptor + */ + pTmp = &pTmp[2u]; + /* For this table, c is the number of configuration descriptors */ + if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */ + { + pTmp = (const T_USBFS_LUT CYCODE *) NULL; + } + else + { + pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list; + } + + return (pTmp); +} + + +#if (USBFS_BOS_ENABLE) + /******************************************************************************* + * Function Name: USBFS_GetBOSPtr + ****************************************************************************//** + * + * This routine returns a pointer a BOS table entry + * + * + * + * \return + * BOS Descriptor pointer or NULL when descriptor does not exist. + * + *******************************************************************************/ + const T_USBFS_LUT CYCODE *USBFS_GetBOSPtr(void) + + { + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the second entry points to the BOS Descriptor + */ + pTmp = &pTmp[1u]; + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + return (pTmp); + } +#endif /* (USBFS_BOS_ENABLE) */ + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceTablePtr +****************************************************************************//** +* +* This routine returns a pointer to the Device table +* +* \return +* Device Table pointer +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + +{ + /* Device Table */ + return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); +} + + +/******************************************************************************* +* Function Name: USB_GetInterfaceClassTablePtr +****************************************************************************//** +* +* This routine returns Interface Class table pointer, which contains +* the relation between interface number and interface class. +* +* \return +* Interface Class table pointer. +* +*******************************************************************************/ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + +{ + const T_USBFS_LUT CYCODE *pTmp; + const uint8 CYCODE *pInterfaceClass; + uint8 currentInterfacesNum; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + if (pTmp != NULL) + { + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + /* Third entry in the LUT starts the Interface Table pointers */ + /* The INTERFACE_CLASS table is located after all interfaces */ + pTmp = &pTmp[currentInterfacesNum + 2u]; + pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list; + } + else + { + pInterfaceClass = (const uint8 CYCODE *) NULL; + } + + return (pInterfaceClass); +} + + +/******************************************************************************* +* Function Name: USBFS_TerminateEP +****************************************************************************//** +* +* This function terminates the specified USBFS endpoint. +* This function should be used before endpoint reconfiguration. +* +* \param ep Contains the data endpoint number. +* +* \reentrant +* No. +* +* \sideeffect +* +* The device responds with a NAK for any transactions on the selected endpoint. +* +*******************************************************************************/ +void USBFS_TerminateEP(uint8 epNumber) +{ + /* Get endpoint number */ + epNumber &= USBFS_DIR_UNUSED; + + if ((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[epNumber].hwEpState |= USBFS_ENDPOINT_STATUS_HALT; + + /* Clear the data toggle */ + USBFS_EP[epNumber].epToggle = 0u; + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_IN; + } + else + { + /* OUT Endpoint */ + USBFS_SIE_EP_BASE.sieEp[epNumber].epCr0 = USBFS_MODE_NAK_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_SetEndpointHalt +****************************************************************************//** +* +* This routine handles set endpoint halt. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_SetEndpointHalt(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 ep; + + /* Set endpoint halt */ + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = (USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return (requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ClearEndpointHalt +****************************************************************************//** +* +* This routine handles clear endpoint halt. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_ClearEndpointHalt(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 ep; + + /* Clear endpoint halt */ + ep = USBFS_wIndexLoReg & USBFS_DIR_UNUSED; + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Clear the endpoint Halt */ + USBFS_EP[ep].hwEpState &= (uint8) ~USBFS_ENDPOINT_STATUS_HALT; + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + + /* Clear toggle bit for already armed packet */ + USBFS_SIE_EP_BASE.sieEp[ep].epCnt0 = (uint8) ~(uint8)USBFS_EPX_CNT_DATA_TOGGLE; + + /* Return API State as it was defined before */ + USBFS_EP[ep].apiEpState &= (uint8) ~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) + { + /* Wait for next packet from application */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_IN; + } + else /* Continue armed transfer */ + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_IN; + } + } + else + { + /* OUT Endpoint */ + if (USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + /* Allow application to read full buffer */ + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_NAK_OUT; + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + USBFS_SIE_EP_BASE.sieEp[ep].epCr0 = USBFS_MODE_ACK_OUT; + } + } + + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ValidateAlternateSetting +****************************************************************************//** +* +* Validates (and records) a SET INTERFACE request. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_ValidateAlternateSetting(void) +{ + uint8 requestHandled = USBFS_FALSE; + + uint8 interfaceNum; + uint8 curInterfacesNum; + const T_USBFS_LUT CYCODE *pTmp; + + /* Get interface number from the request. */ + interfaceNum = (uint8) USBFS_wIndexLoReg; + + /* Get number of interfaces for current configuration. */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + curInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + + /* Validate that interface number is within range. */ + if ((interfaceNum <= curInterfacesNum) || (interfaceNum <= USBFS_MAX_INTERFACES_NUMBER)) + { + /* Save current and new alternate settings (come with request) to make + * desicion about following endpoint re-configuration. + */ + USBFS_interfaceSettingLast[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = (uint8) USBFS_wValueLoReg; + + requestHandled = USBFS_TRUE; + } + + return (requestHandled); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c new file mode 100644 index 0000000..d28b9a2 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/USBFS_vnd.c @@ -0,0 +1,100 @@ +/***************************************************************************//** +* \file USBFS_vnd.c +* \version 3.10 +* +* \brief +* This file contains the USB vendor request handler. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS_pvt.h" + + +#if(USBFS_EXTERN_VND == USBFS_FALSE) + +/*************************************** +* Vendor Specific Declarations +***************************************/ + +/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_HandleVendorRqst +****************************************************************************//** +* +* This routine provide users with a method to implement vendor specific +* requests. +* +* To implement vendor specific requests, add your code in this function to +* decode and disposition the request. If the request is handled, your code +* must set the variable "requestHandled" to TRUE, indicating that the +* request has been handled. +* +* \return +* requestHandled. +* +* \reentrant +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleVendorRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + /* Check request direction: D2H or H2D. */ + if (0u != (USBFS_bmRequestTypeReg & USBFS_RQST_DIR_D2H)) + { + /* Handle direction from device to host. */ + + switch (USBFS_bRequestReg) + { + case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *) &USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* (USBFS_ENABLE_MSOS_STRING) */ + break; + + default: + break; + } + } + + /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ + + /* `#END` */ + +#ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK + if (USBFS_FALSE == requestHandled) + { + requestHandled = USBFS_HandleVendorRqst_Callback(); + } +#endif /* (USBFS_HANDLE_VENDOR_RQST_CALLBACK) */ + + return (requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Vendor Specific Requests +********************************************************************************/ + +/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + + +#endif /* USBFS_EXTERN_VND */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld new file mode 100644 index 0000000..fa5425c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -0,0 +1,393 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cy_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + +/* Code sharing support */ +INCLUDE cycodeshareexport.ld +INCLUDE cycodeshareimport.ld + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 256; +CY_ECC_ROW_SIZE = 32; +CY_EE_IN_BTLDR = 0x00; +CY_APPL_LOADABLE = 1; +CY_EE_SIZE = 2048; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; +CY_APPL_LOADABLE = 1; +CY_CHECKSUM_EXCLUDE_SIZE = ALIGN(0, CY_FLASH_ROW_SIZE); + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in interrupt routines & vector */ +EXTERN(main) + +/* Bring in meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); +PROVIDE(__cy_heap_end = __cy_stack - 0x1000); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; + ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + PROVIDE(CY_ECC_OFFSET = ecc_offset); + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + *(.romvectors) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + *(.text.Reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + + + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + + + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + + + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + + /*************************************************************************** + * Checksum Exclude Section for non-bootloadable projects. See below. + ***************************************************************************/ + + + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + + + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + + + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0400; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x1000) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x1000; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + + /*************************************************************************** + * Checksum Exclude Section + *************************************************************************** + * + * For the normal and bootloader projects this section is placed at any + * place. For the Bootloadable applications, it is placed at the specific + * address. + * + * Case # 1. Bootloadable application + * + * _______________________________ + * | Metadata (BTLDBL) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | | + * | | + * | BTLDBL | + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDR | + * |_______________________________| + * + * + * Case # 2. Bootloadable application for Dual-Application Bootloader + * + * _______________________________ + * | Metadata (BTLDBL # 1) | + * |-------------------------------| + * | Metadata (BTLDBL # 2) | + * |-------------------------------| + * | Checksum Exclude (BTLDBL # 2) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 2 | + * |_______________________________|____BTLDBL # 2 Start address___ + * | Checksum Exclude (BTLDBL # 1) | + * |-------------------------------| + * | | + * | | + * | | + * |-------------------------------| + * | | + * | BTLDBL # 1 | + * | | + * |-------------------------------| + * | BTLDR | + * |_______________________________| + */ + .cy_checksum_exclude ((LENGTH(rom) - CY_FLASH_ROW_SIZE * CY_APPL_MAX) - CY_CHECKSUM_EXCLUDE_SIZE): { KEEP(*(.cy_checksum_exclude)) } + + + /* Bootloadable applications only: verify that size of the data in the section is within the specified limit. */ + cy_checksum_exclude_size = (CY_APPL_LOADABLE == 1) ? SIZEOF(.cy_checksum_exclude) : 0; + ASSERT(cy_checksum_exclude_size <= CY_CHECKSUM_EXCLUDE_SIZE, "CY_BOOT: Section .cy_checksum_exclude size exceedes specified limit.") + + + .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : + { + KEEP(*(.cyloadermeta)) + } :NONE + + .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + + .cyconfigecc (0x80000000 + ecc_offset) : + { + KEEP(*(.cyconfigecc)) + } :NONE + + .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE + .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + + .cyeeprom (0x90200000 + ee_offset) : + { + KEEP(*(.cyeeprom)) + ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); + } :NONE + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h new file mode 100644 index 0000000..74c49c6 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_armcc.h @@ -0,0 +1,734 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h new file mode 100644 index 0000000..bb89fbb --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cmsis_gcc.h @@ -0,0 +1,1373 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS Cortex-M Core Function/Instruction Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + int32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return(result); +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __builtin_clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) ); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +#endif /* __CMSIS_GCC_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h new file mode 100644 index 0000000..b4ac4c7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -0,0 +1,1763 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03U) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __CSMC__ ) + #define __packed + #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ + #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */ + #define __STATIC_INLINE static inline + +#else + #error Unknown compiler +#endif + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_PCS_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "core_cmInstr.h" /* Core Instruction Access */ +#include "core_cmFunc.h" /* Core Function Access */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200U)) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable External Interrupt + \details Enables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Disable External Interrupt + \details Disables a device-specific interrupt in the NVIC interrupt controller. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Pending Interrupt + \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of an external interrupt. + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of an external interrupt. + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in NVIC and returns the active bit. + \param [in] IRQn Interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of an interrupt. + \note The priority cannot be set for every core interrupt. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) < 0) + { + SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of an interrupt. + The interrupt number can be positive to specify an external (device specific) interrupt, + or negative to specify an internal (core) interrupt. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) < 0) + { + return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h new file mode 100644 index 0000000..ad2d786 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,52 @@ +/******************************************************************************* +* \file core_cm3_psoc5.h +* \version 5.50 +* +* \brief Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#define __CHECK_DEVICE_DEFINES + +#define __CM3_REV 0x0201 + +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +#include + + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h new file mode 100644 index 0000000..652a48a --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h new file mode 100644 index 0000000..f474b0e --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmInstr.h @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V4.30 + * @date 20. October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/*------------------ RealView Compiler -----------------*/ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + +/*------------------ ARM Compiler V6 -------------------*/ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #include "cmsis_armcc_V6.h" + +/*------------------ GNU Compiler ----------------------*/ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + +/*------------------ ICC Compiler ----------------------*/ +#elif defined ( __ICCARM__ ) + #include + +/*------------------ TI CCS Compiler -------------------*/ +#elif defined ( __TMS470__ ) + #include + +/*------------------ TASKING Compiler ------------------*/ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +/*------------------ COSMIC Compiler -------------------*/ +#elif defined ( __CSMC__ ) + #include + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c new file mode 100644 index 0000000..e5c0d2b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c @@ -0,0 +1,1858 @@ +/***************************************************************************//** +* \file cyPm.c +* \version 5.50 +* +* \brief Provides an API for the power management. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" + + + +/******************************************************************* +* Place your includes, defines, and code here. Do not use the merge +* region below unless any component datasheet suggests doing so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +****************************************************************************//** +* +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all the states of the clocking system that do not persist +* during sleep/hibernate or that need to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* \sideeffect +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* Master clock - save source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Switch Master clock's source from PLL's output to PLL's source */ + if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc) + { + switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK) + { + case CY_PM_CLKDIST_PLL_SRC_IMO: + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + break; + + case CY_PM_CLKDIST_PLL_SRC_XTAL: + CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL); + break; + + case CY_PM_CLKDIST_PLL_SRC_DSI: + CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI); + break; + + default: + CYASSERT(0u != 0u); + break; + } + } + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* Enable the IMO. Use software delay instead of the FTW-based inside */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + + /* Settling time of the IMO is of the order of less than 6us */ + CyDelayUs(6u); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to IMO */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* No change if master clock divider is 1 */ + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* No change if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for flash according to CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save the enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and its value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +****************************************************************************//** +* +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after a hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is +* not verified after a hold-off timeout. +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + cystatus status = CYRET_TIMEOUT; + uint16 i; + uint16 clkBusDivTmp; + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both bandgap and delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabilize the value is crystal specific. + *******************************************************************/ + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_EcoTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_ECO_TIMEOUT_CALLBACK */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temporary set maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + status = CYRET_TIMEOUT; + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Read to clear lock status after delay */ + CyDelayUs((uint32)80u); + (void) CY_PM_FASTCLK_PLL_SR_REG; + + /* It should take 250 us lock: 251-80 = 171 */ + for(i = 171u; i > 0u; i--) + { + CyDelayUs((uint32)1u); + + /* Accept PLL is OK after two consecutive polls indicate PLL lock */ + if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) && + (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED))) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when PLL is not ready. + *******************************************************************/ + /* `#START_PLL_TIMEOUT` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK + CyBoot_CyPmRestoreClocks_PllTimeout_Callback(); + #endif /* CY_BOOT_CY_PM_RESTORE_CLOCKS_PLL_TIMEOUT_CALLBACK */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - disable if it was originally disabled */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* Bus clock - restore divider, if needed */ + clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +****************************************************************************//** +* +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on the wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* \param PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* \param PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* \param PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* \param PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* \param PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* \param PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* \param PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* \param PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* \param PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* \param PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* \param PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* \param *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified, the associated timer will +* be included as a wakeup source. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* \param *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* \param **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource, an instance specific define +* that will track with the specific comparator that the instance +* is placed into should be used. As an example, for a Comparator instance named +* \param MyComp the value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with a corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Reentrant: +* No +* +* \sideeffect +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; +} + + +/******************************************************************************* +* Function Name: CyPmSleep +****************************************************************************//** +* +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as the wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be a combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate interrupt. +* +* \param wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* \param PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* \param PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* \param PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* \param PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* \param PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* \param PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* \param PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* \param PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* \param PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* \param PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* \param PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* \param PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* \param PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* \param wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* \param *Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* \param value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + + /*********************************************************************** + * PSoC3 < TO6: + * - Hardware buzz must be disabled before the sleep mode entry. + * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must + * be also disabled. + * + * PSoC3 >= TO6: + * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware + * buzz must be enabled before the sleep mode entry and restored on + * the wakeup. + ***********************************************************************/ + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + } + + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* LVI/HVI requires hardware buzz to be enabled */ + CYASSERT(0u != 0u); + } + else + { + if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) + { + cyPmBackup.hardwareBuzz = CY_PM_DISABLED; + CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; + } + else + { + cyPmBackup.hardwareBuzz = CY_PM_ENABLED; + } + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices,interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + CyPmHibSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /******************************************************************* + * Do not use the merge region below unless any component datasheet + * suggests doing so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK + CyBoot_CyPmSleep_BeforeSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_BEFORE_SLEEP_CALLBACK */ + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + #ifdef CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK + CyBoot_CyPmSleep_AfterSleep_Callback(); + #endif /* CY_BOOT_CY_PM_SLEEP_AFTER_SLEEP_CALLBACK */ + + /* Restore hardware configuration */ + CyPmHibSlpRestore(); + + + /* Disable hardware buzz, if it was previously enabled */ + #if(CY_PSOC3) + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL >= 5u) + { + if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) + { + CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); + } + } + } + + #endif /* (CY_PSOC3) */ + + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +****************************************************************************//** +* +* Puts the part into the Hibernate state. +* +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* Reentrant: +* No +* +* \sideeffect +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + CyPmHibernateEx(CY_PM_HIB_SRC_PICU); +} + + +/******************************************************************************* +* Function Name: CyPmHibernateEx +****************************************************************************//** +* +* Puts the part into the Hibernate state. +* +* The following wake up sources can be configured: PICU interrupt, Comparator0, +* Comparator1, Comparator2, and Comparator3 output. +* +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. +* +* If using PICU as the wake up source, make sure you have at least one pin +* configured to generate a PICU interrupt. For pin Px.y, the register +* "PICU_INTTYPE_PICUx_INTTYPEy" controls the PICU behavior. In the TRM, this +* register is "PICU[0..15]_INTTYPE[0..7]." In the Pins component datasheet, +* this register is referred to as the IRQ option. Once the wakeup occurs, the +* PICU wakeup source bit is restored and the PSoC returns to the Active state. +* +* If using a comparator as the wake up source, make sure you call this function +* with the 'wakeupSource' parameter set to the appropriate comparator. The part +* is configured for the requested wakeup source by setting the corresponding +* bits in PM_WAKEUP_CFG1 register. +* +* Function call CyPmHibernateEx(CY_PM_HIB_SRC_PICU) will act in the same way as +* CyPmHibernate(). +* +* \param wakeupSource: +* Parameter Value Description +* CY_PM_HIB_SRC_PICU PICU interrupt is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR0 Comparator 0 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR1 Comparator 1 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR2 Comparator 2 is set as the wake up source. +* CY_PM_HIB_SRC_COMPARATOR3 Comparator 3 is set as the wake up source. +* +* Reentrant: +* No +* +* \sideeffect +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin +* is instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernateEx(uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter the Sleep and + * Hibernate modes. The holdoff delay is measured using the rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + CyPmHibSaveSet(); + + + /* Save and set new wake up configuration */ + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = ((uint8) (wakeupSource >> 4u) & CY_PM_WAKEUP_PICU); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +****************************************************************************//** +* +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* \param mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* \return +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus & (CY_PM_FTW_INT | CY_PM_CTW_INT | CY_PM_ONEPPS_INT); + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +****************************************************************************//** +* +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Saves ILO power down mode state and enable it +* - Saves state of 1 kHz and 100 kHz ILO and disable them +* - Disables sleep regulator and shorts vccd to vpwrsleep +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If the I2C backup regulator is enabled, all the fixed-function registers + * store their values while the device is in the low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that the I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. The I2C sleep APIs is responsible for + * restoration. + ***********************************************************************/ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set the power mode wakeup trim registers + ***************************************************************************/ + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +****************************************************************************//** +* +* Restores the device for the proper Hibernate mode exit: +* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores ILO power down mode state and enables it +* - Restores the state of 1 kHz and 100 kHz ILO and disables them +* - Restores the sleep regulator settings +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + + /*************************************************************************** + * Restore the power mode wakeup trim registers + ***************************************************************************/ + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +****************************************************************************//** +* +* Performs the CTW configuration: +* - Disables the CTW interrupt +* - Enables 1 kHz ILO +* - Sets a new CTW interval +* +* \param ctwInterval: the CTW interval to be set. +* +* \sideeffect +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +****************************************************************************//** +* +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interrupts +* - Enables 1PPS +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +****************************************************************************//** +* +* Performs the FTW configuration: +* - Disables the FTW interrupt +* - Enables 100 kHz ILO +* - Sets a new FTW interval. +* +* \param ftwInterval The FTW counter interval. +* +* \sideeffect +* Enables the ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Interval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +****************************************************************************//** +* +* This API is used for preparing the device for the Sleep and Hibernate low +* power modes entry: +* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5) +* - Saves the SC/CT routing connections (PSoC 3/5/5LP) +* - Disables the Serial Wire Viewer (SWV) (PSoC 3) +* - Saves the boost reference selection and sets it to internal +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +****************************************************************************//** +* +* This API is used for restoring the device configurations after wakeup from +* the Sleep and Hibernate low power modes: +* - Restores the SC/CT routing connections +* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3) +* - Restores the boost reference selection +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +****************************************************************************//** +* +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at specified Vddd threshold */ + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at specified Vdda threshold */ + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +****************************************************************************//** +* +* Restores the analog and digital LVI and HVI configuration. +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h new file mode 100644 index 0000000..090009b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h @@ -0,0 +1,683 @@ +/***************************************************************************//** +* \file cyPm.h +* \version 5.50 +* +* \brief Provides the function definitions for the power management API. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; +void CyPmHibernateEx(uint16 wakeupSource) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +/* Wake up sources for Sleep mode */ +#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) +#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) +#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) +#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) +#define PM_SLEEP_SRC_PICU (0x0040u) +#define PM_SLEEP_SRC_I2C (0x0080u) +#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) +#define PM_SLEEP_SRC_VD (0x0400u) +#define PM_SLEEP_SRC_CTW (0x0800u) +#define PM_SLEEP_SRC_ONE_PPS (0x0800u) +#define PM_SLEEP_SRC_LCD (0x1000u) + +/* Wake up sources for Hibernate mode */ +#define CY_PM_HIB_SRC_PICU (0x0040u) +#define CY_PM_HIB_SRC_COMPARATOR0 (0x0001u) +#define CY_PM_HIB_SRC_COMPARATOR1 (0x0002u) +#define CY_PM_HIB_SRC_COMPARATOR2 (0x0004u) +#define CY_PM_HIB_SRC_COMPARATOR3 (0x0008u) + +/* Wake up sources for Alternate Active mode */ +#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) +#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) +#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) +#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) +#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) +#define PM_ALT_ACT_SRC_PICU (0x0040u) +#define PM_ALT_ACT_SRC_I2C (0x0080u) +#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) +#define PM_ALT_ACT_SRC_FTW (0x0400u) +#define PM_ALT_ACT_SRC_VD (0x0400u) +#define PM_ALT_ACT_SRC_CTW (0x0800u) +#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) +#define PM_ALT_ACT_SRC_LCD (0x1000u) + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) + + +/* Delay line bandgap current settling time starting from wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ \ + ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC & IAR */ + #define CY_PM_WFI __asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + uint8 hardwareBuzz; + + #endif /* (CY_PSOC3) */ + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + uint8 scctData[28u]; /* SC/CT routing registers */ + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +/* Sleep Regulator Trim Register */ +#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) +#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* Power Mode Wakeup Mask Configuration Register 0 */ +#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) +#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + +/* Power Mode Wakeup Mask Configuration Register 1 */ +#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) +#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + +/* Power Mode Wakeup Mask Configuration Register 2 */ +#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) +#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN ) + #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN ) + +#endif /* (CY_PSOC3) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u) +#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u) +#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u) +#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u) + +/* Waiting for hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares system to disable LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* High-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* Low-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* Low-voltage-interrupt feature on external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +/* Allows system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + +/* Holdoff mask sleep trim */ +#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +/* Disables sleep regulator and shorts vccd to vpwrsleep */ +#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_CLK (0x01u) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Lock Status Flag. If lock is acquired this flag will stay set (regardless of +* whether lock is subsequently lost) until it is read. Upon reading it will +* clear. If lock is still true then the bit will simply set again. If lock +* happens to be false when the clear on read occurs then the bit will stay +* cleared until the next lock event. +*******************************************************************************/ +#define CY_PM_FASTCLK_PLL_LOCKED (0x01u) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c new file mode 100644 index 0000000..ce94d9c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h new file mode 100644 index 0000000..4aef67b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c new file mode 100644 index 0000000..3012ade --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.c @@ -0,0 +1,1273 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +#include "cytypes.h" + +#if (!CYDEV_BOOTLOADER_ENABLE) + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyloadermeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyloadermeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_loader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x51u, 0x01u, 0x00u, 0x01u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; +#endif /* (!CYDEV_BOOTLOADER_ENABLE) */ + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cybootloader"), used)) +#elif defined(__ICCARM__) +#pragma location=".cybootloader" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_bootloader[] = { + 0x00u, 0x40u, 0x00u, 0x20u, 0x11u, 0x00u, 0x00u, 0x00u, + 0x95u, 0x03u, 0x00u, 0x00u, 0x95u, 0x03u, 0x00u, 0x00u, + 0x08u, 0xB5u, 0x05u, 0x4Bu, 0x1Au, 0x68u, 0x03u, 0xF5u, + 0x3Fu, 0x53u, 0x02u, 0x33u, 0x1Au, 0x60u, 0x00u, 0xF0u, + 0x99u, 0xFAu, 0x00u, 0xF0u, 0xB9u, 0xF9u, 0x00u, 0xBFu, + 0xFAu, 0x46u, 0x00u, 0x40u, 0x10u, 0xB5u, 0x05u, 0x4Cu, + 0x23u, 0x78u, 0x33u, 0xB9u, 0x04u, 0x4Bu, 0x13u, 0xB1u, + 0x04u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x01u, 0x23u, + 0x23u, 0x70u, 0x10u, 0xBDu, 0xE8u, 0xC0u, 0xFFu, 0x1Fu, + 0x00u, 0x00u, 0x00u, 0x00u, 0x8Cu, 0x21u, 0x00u, 0x00u, + 0x08u, 0x4Bu, 0x10u, 0xB5u, 0x1Bu, 0xB1u, 0x08u, 0x49u, + 0x08u, 0x48u, 0xAFu, 0xF3u, 0x00u, 0x80u, 0x08u, 0x48u, + 0x03u, 0x68u, 0x03u, 0xB9u, 0x10u, 0xBDu, 0x07u, 0x4Bu, + 0x00u, 0x2Bu, 0xFBu, 0xD0u, 0xBDu, 0xE8u, 0x10u, 0x40u, + 0x18u, 0x47u, 0x00u, 0xBFu, 0x00u, 0x00u, 0x00u, 0x00u, + 0xECu, 0xC0u, 0xFFu, 0x1Fu, 0x8Cu, 0x21u, 0x00u, 0x00u, + 0xC8u, 0xC0u, 0xFFu, 0x1Fu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x70u, 0xB5u, 0x45u, 0x4Au, 0x45u, 0x4Du, 0x13u, 0x78u, + 0x5Bu, 0x3Au, 0x43u, 0xF0u, 0x01u, 0x03u, 0x82u, 0xF8u, + 0x5Bu, 0x30u, 0x13u, 0x78u, 0x42u, 0x4Cu, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x13u, 0x70u, 0x93u, 0x79u, 0x64u, 0x26u, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0x93u, 0x71u, 0x12u, 0xF8u, + 0x19u, 0x3Cu, 0x03u, 0xF0u, 0xFEu, 0x03u, 0x02u, 0xF8u, + 0x19u, 0x3Cu, 0x12u, 0xF8u, 0x1Du, 0x3Cu, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x02u, 0xF8u, 0x1Du, 0x3Cu, 0x53u, 0x78u, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0x53u, 0x70u, 0x12u, 0xF8u, + 0x1Bu, 0x3Cu, 0x03u, 0xF0u, 0xFEu, 0x03u, 0x02u, 0xF8u, + 0x1Bu, 0x3Cu, 0x12u, 0xF8u, 0x1Fu, 0x3Cu, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x02u, 0xF8u, 0x1Fu, 0x3Cu, 0xD3u, 0x7Du, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0xD3u, 0x75u, 0x15u, 0x32u, + 0x13u, 0x78u, 0x03u, 0xF0u, 0xFEu, 0x03u, 0x13u, 0x70u, + 0x92u, 0xF8u, 0x30u, 0x30u, 0x03u, 0xF0u, 0xFEu, 0x03u, + 0x82u, 0xF8u, 0x30u, 0x30u, 0x12u, 0xF8u, 0x1Eu, 0x3Cu, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0x02u, 0xF8u, 0x1Eu, 0x3Cu, + 0x12u, 0xF8u, 0x20u, 0x3Cu, 0x03u, 0xF0u, 0xFEu, 0x03u, + 0x02u, 0xF8u, 0x20u, 0x3Cu, 0x12u, 0xF8u, 0x22u, 0x3Cu, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0x02u, 0xF8u, 0x22u, 0x3Cu, + 0x12u, 0xF8u, 0x24u, 0x3Cu, 0x03u, 0xF0u, 0xFEu, 0x03u, + 0x02u, 0xF8u, 0x24u, 0x3Cu, 0x92u, 0xF8u, 0x48u, 0x30u, + 0x03u, 0xF0u, 0xFEu, 0x03u, 0x82u, 0xF8u, 0x48u, 0x30u, + 0x12u, 0xF8u, 0x03u, 0x3Cu, 0x03u, 0xF0u, 0xFEu, 0x03u, + 0x02u, 0xF8u, 0x03u, 0x3Cu, 0x2Bu, 0x78u, 0x43u, 0xF0u, + 0x01u, 0x03u, 0x2Bu, 0x70u, 0x23u, 0x78u, 0x43u, 0xF0u, + 0x01u, 0x03u, 0x23u, 0x70u, 0x00u, 0xF0u, 0x82u, 0xFEu, + 0x20u, 0xB9u, 0x64u, 0x20u, 0x00u, 0xF0u, 0x4Eu, 0xFDu, + 0x01u, 0x3Eu, 0xF7u, 0xD1u, 0x00u, 0xF0u, 0x7Au, 0xFEu, + 0x50u, 0xB9u, 0x2Bu, 0x78u, 0x40u, 0x22u, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x2Bu, 0x70u, 0x23u, 0x78u, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x23u, 0x70u, 0x09u, 0x4Bu, 0x1Au, 0x70u, + 0x00u, 0xF0u, 0x04u, 0xFCu, 0x2Bu, 0x78u, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x2Bu, 0x70u, 0x23u, 0x78u, 0x03u, 0xF0u, + 0xFEu, 0x03u, 0x23u, 0x70u, 0xF6u, 0xE7u, 0x00u, 0xBFu, + 0x7Bu, 0x50u, 0x00u, 0x40u, 0x62u, 0x50u, 0x00u, 0x40u, + 0x63u, 0x50u, 0x00u, 0x40u, 0xFAu, 0x46u, 0x00u, 0x40u, + 0xF8u, 0xB5u, 0x72u, 0xB6u, 0x64u, 0x4Bu, 0x61u, 0x22u, + 0x1Au, 0x70u, 0x06u, 0x22u, 0xA3u, 0xF5u, 0xA0u, 0x63u, + 0x1Au, 0x70u, 0x52u, 0x22u, 0xA3u, 0xF5u, 0x80u, 0x73u, + 0x1Au, 0x70u, 0x60u, 0x4Bu, 0x60u, 0x4Au, 0x1Bu, 0x78u, + 0x60u, 0x4Eu, 0xDBu, 0xB2u, 0x13u, 0x70u, 0x40u, 0xF6u, + 0x18u, 0x02u, 0x5Fu, 0x4Bu, 0x19u, 0x25u, 0x1Au, 0x80u, + 0x41u, 0xF2u, 0x51u, 0x22u, 0x00u, 0x24u, 0x23u, 0xF8u, + 0x02u, 0x2Cu, 0x33u, 0x78u, 0x4Fu, 0xF4u, 0xF0u, 0x70u, + 0x03u, 0xF0u, 0x01u, 0x03u, 0x43u, 0xEAu, 0x44u, 0x04u, + 0x00u, 0xF0u, 0x3Eu, 0xFEu, 0x01u, 0x3Du, 0x04u, 0xF0u, + 0x03u, 0x04u, 0x1Cu, 0xD0u, 0x03u, 0x2Cu, 0xF0u, 0xD1u, + 0x54u, 0x4Bu, 0x4Fu, 0xF4u, 0x80u, 0x72u, 0x1Au, 0x80u, + 0x07u, 0x22u, 0x1Au, 0x70u, 0x52u, 0x4Au, 0x00u, 0x24u, + 0x48u, 0x21u, 0x14u, 0x70u, 0x91u, 0x70u, 0x02u, 0x22u, + 0x1Cu, 0x70u, 0x5Cu, 0x71u, 0x03u, 0xF8u, 0x03u, 0x2Cu, + 0x01u, 0x22u, 0x83u, 0xF8u, 0xFCu, 0x27u, 0x4Du, 0x4Au, + 0x4Du, 0x4Du, 0x13u, 0x78u, 0x06u, 0x26u, 0x43u, 0xF0u, + 0x04u, 0x03u, 0x13u, 0x70u, 0x00u, 0xE0u, 0xFEu, 0xE7u, + 0x06u, 0xFBu, 0x04u, 0x53u, 0x00u, 0x21u, 0x9Au, 0x88u, + 0x18u, 0x68u, 0x01u, 0x34u, 0x01u, 0xF0u, 0x91u, 0xFFu, + 0x06u, 0x2Cu, 0xF5u, 0xD1u, 0x00u, 0x22u, 0x11u, 0x46u, + 0x44u, 0x4Cu, 0x04u, 0xF1u, 0x30u, 0x05u, 0x54u, 0xF8u, + 0x21u, 0x00u, 0x05u, 0xEBu, 0x42u, 0x03u, 0x20u, 0xF0u, + 0xFFu, 0x06u, 0xC0u, 0xB2u, 0x02u, 0x44u, 0x05u, 0xEBu, + 0x42u, 0x00u, 0x01u, 0x33u, 0x03u, 0x30u, 0x02u, 0x33u, + 0x98u, 0x42u, 0x06u, 0xD0u, 0x13u, 0xF8u, 0x03u, 0x7Cu, + 0x13u, 0xF8u, 0x02u, 0xECu, 0x07u, 0xF8u, 0x06u, 0xE0u, + 0xF5u, 0xE7u, 0x01u, 0x31u, 0x0Cu, 0x29u, 0xE6u, 0xD1u, + 0x37u, 0x4Au, 0x13u, 0x78u, 0x43u, 0xF0u, 0x02u, 0x03u, + 0x13u, 0x70u, 0x13u, 0x7Cu, 0x43u, 0xF0u, 0x02u, 0x03u, + 0x13u, 0x74u, 0x34u, 0x4Bu, 0x34u, 0x4Au, 0x1Cu, 0x46u, + 0x18u, 0x68u, 0x59u, 0x68u, 0x03u, 0xC2u, 0x54u, 0xF8u, + 0x0Au, 0x0Fu, 0x19u, 0x89u, 0xB8u, 0x32u, 0x22u, 0xF8u, + 0xB8u, 0x1Cu, 0x61u, 0x68u, 0x03u, 0xC2u, 0x21u, 0x89u, + 0x1Cu, 0x46u, 0x54u, 0xF8u, 0x14u, 0x0Fu, 0x11u, 0x80u, + 0x61u, 0x68u, 0x28u, 0x32u, 0x03u, 0xC2u, 0x21u, 0x89u, + 0x2Au, 0x48u, 0x11u, 0x80u, 0x19u, 0x46u, 0x51u, 0xF8u, + 0x1Eu, 0x2Fu, 0x29u, 0x4Cu, 0x02u, 0x60u, 0x4Au, 0x68u, + 0x19u, 0x46u, 0x42u, 0x60u, 0x51u, 0xF8u, 0x26u, 0x2Fu, + 0x02u, 0x61u, 0x4Au, 0x68u, 0x19u, 0x46u, 0x42u, 0x61u, + 0x51u, 0xF8u, 0x2Eu, 0x2Fu, 0x02u, 0x62u, 0x4Au, 0x68u, + 0x19u, 0x46u, 0x42u, 0x62u, 0x51u, 0xF8u, 0x36u, 0x2Fu, + 0x02u, 0x63u, 0x4Au, 0x68u, 0x1Fu, 0x49u, 0x42u, 0x63u, + 0x53u, 0xF8u, 0x3Eu, 0x2Fu, 0x0Au, 0x60u, 0x5Au, 0x68u, + 0x4Au, 0x60u, 0x1Du, 0x4Au, 0x13u, 0x78u, 0x43u, 0xF0u, + 0x08u, 0x03u, 0x13u, 0x70u, 0x1Bu, 0x4Bu, 0x02u, 0xF5u, + 0xAAu, 0x52u, 0x1Bu, 0x78u, 0x0Cu, 0x32u, 0xDBu, 0xB2u, + 0x03u, 0xF0u, 0x07u, 0x01u, 0x1Bu, 0x09u, 0x11u, 0x70u, + 0x53u, 0x70u, 0x17u, 0x4Bu, 0x44u, 0x22u, 0x1Au, 0x70u, + 0xA3u, 0xF5u, 0xA6u, 0x53u, 0x16u, 0x3Bu, 0x0Fu, 0xCBu, + 0x07u, 0xC4u, 0x23u, 0x80u, 0xF8u, 0xBDu, 0x00u, 0xBFu, + 0x00u, 0x48u, 0x00u, 0x40u, 0x0Fu, 0x01u, 0x00u, 0x49u, + 0xA1u, 0x46u, 0x00u, 0x40u, 0x25u, 0x42u, 0x00u, 0x40u, + 0x22u, 0x42u, 0x00u, 0x40u, 0x04u, 0x40u, 0x00u, 0x40u, + 0x06u, 0x40u, 0x00u, 0x40u, 0xE8u, 0x46u, 0x00u, 0x40u, + 0x90u, 0x21u, 0x00u, 0x00u, 0xB4u, 0x21u, 0x00u, 0x00u, + 0x03u, 0x50u, 0x01u, 0x40u, 0x16u, 0x22u, 0x00u, 0x00u, + 0x00u, 0x51u, 0x00u, 0x40u, 0x12u, 0x51u, 0x00u, 0x40u, + 0xB0u, 0x43u, 0x00u, 0x40u, 0x62u, 0x51u, 0x00u, 0x40u, + 0x22u, 0x43u, 0x00u, 0x40u, 0xCFu, 0x01u, 0x00u, 0x49u, + 0x76u, 0x58u, 0x00u, 0x40u, 0xFEu, 0xE7u, 0x00u, 0x00u, + 0x80u, 0xB5u, 0x11u, 0x48u, 0x11u, 0x4Bu, 0x00u, 0x25u, + 0xC0u, 0xB1u, 0xA3u, 0xF1u, 0x10u, 0x01u, 0x92u, 0xC9u, + 0x22u, 0x46u, 0x04u, 0x39u, 0x16u, 0x1Bu, 0xB7u, 0x42u, + 0x04u, 0xD0u, 0x51u, 0xF8u, 0x04u, 0x6Fu, 0x42u, 0xF8u, + 0x04u, 0x6Bu, 0xF7u, 0xE7u, 0x11u, 0x46u, 0x53u, 0xF8u, + 0x04u, 0x6Cu, 0x8Cu, 0x1Au, 0xA6u, 0x42u, 0x02u, 0xD0u, + 0x41u, 0xF8u, 0x04u, 0x5Bu, 0xF9u, 0xE7u, 0x01u, 0x38u, + 0x10u, 0x33u, 0xE5u, 0xE7u, 0x01u, 0xF0u, 0x9Cu, 0xFEu, + 0xFFu, 0xF7u, 0x56u, 0xFEu, 0xFEu, 0xE7u, 0x00u, 0xBFu, + 0x01u, 0x00u, 0x00u, 0x00u, 0xECu, 0x23u, 0x00u, 0x00u, + 0x10u, 0x4Au, 0x11u, 0x4Bu, 0x10u, 0xB4u, 0x1Au, 0x60u, + 0x10u, 0x4Au, 0x11u, 0x4Cu, 0x13u, 0x68u, 0x11u, 0x48u, + 0x43u, 0xF4u, 0x00u, 0x73u, 0x13u, 0x60u, 0x00u, 0x23u, + 0x03u, 0x2Bu, 0x98u, 0xBFu, 0x54u, 0xF8u, 0x23u, 0x20u, + 0x4Fu, 0xEAu, 0x83u, 0x01u, 0x88u, 0xBFu, 0x0Cu, 0x4Au, + 0x01u, 0x33u, 0x30u, 0x2Bu, 0x42u, 0x50u, 0xF3u, 0xD1u, + 0x0Au, 0x4Bu, 0x1Au, 0x78u, 0x0Au, 0x4Bu, 0x1Au, 0x70u, + 0x0Au, 0x4Bu, 0x06u, 0x4Au, 0x10u, 0xBCu, 0x1Au, 0x60u, + 0xFFu, 0xF7u, 0xC2u, 0xBEu, 0x00u, 0x04u, 0xFAu, 0x05u, + 0x0Cu, 0xEDu, 0x00u, 0xE0u, 0x14u, 0xEDu, 0x00u, 0xE0u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xC0u, 0xFFu, 0x1Fu, + 0x95u, 0x03u, 0x00u, 0x00u, 0xBCu, 0x76u, 0x00u, 0x40u, + 0xC0u, 0xC0u, 0xFFu, 0x1Fu, 0x08u, 0xEDu, 0x00u, 0xE0u, + 0x00u, 0x47u, 0x00u, 0x23u, 0x01u, 0x44u, 0x22u, 0xB1u, + 0x01u, 0x3Au, 0x88u, 0x5Cu, 0x03u, 0x44u, 0xDBu, 0xB2u, + 0xF9u, 0xE7u, 0x18u, 0x46u, 0x70u, 0x47u, 0xF0u, 0xB5u, + 0x03u, 0x46u, 0xC1u, 0xB0u, 0x6Au, 0x46u, 0x23u, 0xF0u, + 0xFFu, 0x04u, 0x0Eu, 0x46u, 0x65u, 0x1Eu, 0x04u, 0xF1u, + 0xFFu, 0x07u, 0xC0u, 0xF3u, 0x07u, 0x40u, 0xC3u, 0xF3u, + 0x07u, 0x21u, 0x14u, 0x1Bu, 0x15u, 0xF8u, 0x01u, 0xEFu, + 0xBDu, 0x42u, 0x04u, 0xF8u, 0x05u, 0xE0u, 0xF9u, 0xD1u, + 0xDBu, 0xB2u, 0xD6u, 0x54u, 0x00u, 0xF0u, 0x66u, 0xFBu, + 0x00u, 0xF0u, 0xBCu, 0xFBu, 0x41u, 0xB0u, 0xF0u, 0xBDu, + 0x01u, 0x38u, 0x09u, 0x28u, 0x42u, 0xD8u, 0xDFu, 0xE8u, + 0x00u, 0xF0u, 0x05u, 0x0Bu, 0x11u, 0x17u, 0x1Du, 0x23u, + 0x2Fu, 0x29u, 0x35u, 0x3Bu, 0x09u, 0x02u, 0xC1u, 0xF5u, + 0xFFu, 0x31u, 0x01u, 0xF5u, 0xE0u, 0x71u, 0x3Bu, 0xE0u, + 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u, + 0xC1u, 0x11u, 0x38u, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u, + 0xFFu, 0x31u, 0x01u, 0xF2u, 0xC5u, 0x11u, 0x2Au, 0xE0u, + 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u, + 0xC9u, 0x11u, 0x2Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u, + 0xFFu, 0x31u, 0x01u, 0xF5u, 0xE8u, 0x71u, 0x23u, 0xE0u, + 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF2u, + 0xD1u, 0x11u, 0x1Du, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u, + 0xFFu, 0x31u, 0x01u, 0xF5u, 0xEBu, 0x71u, 0x12u, 0xE0u, + 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u, + 0xE9u, 0x71u, 0x0Cu, 0xE0u, 0x09u, 0x02u, 0xC1u, 0xF5u, + 0xFFu, 0x31u, 0x01u, 0xF5u, 0xEAu, 0x71u, 0x06u, 0xE0u, + 0x09u, 0x02u, 0xC1u, 0xF5u, 0xFFu, 0x31u, 0x01u, 0xF5u, + 0xECu, 0x71u, 0x08u, 0xE0u, 0x00u, 0x21u, 0x0Bu, 0x78u, + 0x48u, 0x78u, 0x43u, 0xEAu, 0x00u, 0x20u, 0x70u, 0x47u, + 0x08u, 0x78u, 0xC0u, 0xB2u, 0x70u, 0x47u, 0x0Bu, 0x78u, + 0x4Au, 0x78u, 0x88u, 0x78u, 0x00u, 0x04u, 0x40u, 0xEAu, + 0x02u, 0x20u, 0x18u, 0x43u, 0xCBu, 0x78u, 0x40u, 0xEAu, + 0x03u, 0x60u, 0x70u, 0x47u, 0x10u, 0xB5u, 0x0Bu, 0x4Au, + 0x13u, 0x78u, 0x03u, 0xF0u, 0xC0u, 0x03u, 0x80u, 0x2Bu, + 0x0Eu, 0xD1u, 0x00u, 0x24u, 0x14u, 0x70u, 0x21u, 0x46u, + 0x02u, 0x20u, 0xFFu, 0xF7u, 0x99u, 0xFFu, 0x38u, 0xB1u, + 0x21u, 0x46u, 0x02u, 0x20u, 0xFFu, 0xF7u, 0x94u, 0xFFu, + 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, 0x68u, 0xBFu, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0xFAu, 0x46u, 0x00u, 0x40u, + 0xF8u, 0xB5u, 0x01u, 0x46u, 0x05u, 0x46u, 0x03u, 0x20u, + 0xFFu, 0xF7u, 0x86u, 0xFFu, 0x29u, 0x46u, 0x04u, 0x46u, + 0x04u, 0x20u, 0xFFu, 0xF7u, 0x81u, 0xFFu, 0x29u, 0x46u, + 0x06u, 0x46u, 0x06u, 0x20u, 0xFFu, 0xF7u, 0x7Cu, 0xFFu, + 0x01u, 0x28u, 0x3Fu, 0xD0u, 0x29u, 0x46u, 0x03u, 0x20u, + 0x01u, 0x34u, 0xFFu, 0xF7u, 0x75u, 0xFFu, 0x06u, 0xEBu, + 0x04u, 0x26u, 0x00u, 0x24u, 0x27u, 0x46u, 0x01u, 0x30u, + 0x00u, 0x02u, 0x86u, 0x42u, 0x09u, 0xD9u, 0x10u, 0xF8u, + 0x01u, 0x3Bu, 0x5Au, 0x1Eu, 0xD2u, 0xB2u, 0xFDu, 0x2Au, + 0x1Cu, 0x44u, 0x98u, 0xBFu, 0x01u, 0x27u, 0xE4u, 0xB2u, + 0xF3u, 0xE7u, 0x29u, 0x46u, 0x03u, 0x20u, 0xFFu, 0xF7u, + 0x5Fu, 0xFFu, 0x14u, 0x4Bu, 0x01u, 0x30u, 0x9Eu, 0x42u, + 0x4Fu, 0xEAu, 0x00u, 0x20u, 0x4Fu, 0xEAu, 0xD0u, 0x00u, + 0x14u, 0xBFu, 0xF6u, 0x08u, 0x4Fu, 0xF4u, 0x80u, 0x46u, + 0xB0u, 0x42u, 0x06u, 0xD2u, 0x00u, 0xF1u, 0x90u, 0x43u, + 0x1Bu, 0x78u, 0x01u, 0x30u, 0x1Cu, 0x44u, 0xE4u, 0xB2u, + 0xF6u, 0xE7u, 0x29u, 0x46u, 0x01u, 0x20u, 0xFFu, 0xF7u, + 0x47u, 0xFFu, 0x64u, 0x42u, 0xE4u, 0xB2u, 0x84u, 0x42u, + 0x0Au, 0xD1u, 0x4Fu, 0xB1u, 0x28u, 0x02u, 0xC0u, 0xF5u, + 0xFFu, 0x30u, 0x01u, 0x21u, 0x00u, 0xF2u, 0xD1u, 0x10u, + 0xFFu, 0xF7u, 0x1Du, 0xFFu, 0x00u, 0x20u, 0xF8u, 0xBDu, + 0x06u, 0x20u, 0xF8u, 0xBDu, 0xC0u, 0xFFu, 0x01u, 0x00u, + 0x2Du, 0xE9u, 0x80u, 0x48u, 0xADu, 0xF5u, 0x61u, 0x7Du, + 0x00u, 0xF0u, 0x2Au, 0xFCu, 0x62u, 0xB6u, 0x00u, 0x25u, + 0x2Fu, 0x46u, 0x2Eu, 0x46u, 0xDFu, 0xF8u, 0x40u, 0x83u, + 0xFFu, 0x23u, 0x01u, 0xAAu, 0x4Fu, 0xF4u, 0x96u, 0x71u, + 0x4Au, 0xA8u, 0x00u, 0xF0u, 0x4Bu, 0xFCu, 0x00u, 0x28u, + 0xF6u, 0xD1u, 0xBDu, 0xF8u, 0x04u, 0x30u, 0x06u, 0x2Bu, + 0x53u, 0xD9u, 0x9Du, 0xF8u, 0x28u, 0x21u, 0x01u, 0x2Au, + 0x4Fu, 0xD1u, 0xBDu, 0xF8u, 0x2Au, 0x41u, 0xE2u, 0x1Du, + 0x9Au, 0x42u, 0x47u, 0xD8u, 0x4Au, 0xABu, 0x23u, 0x44u, + 0x9Bu, 0x79u, 0x17u, 0x2Bu, 0x45u, 0xD1u, 0x23u, 0x1Du, + 0x9Bu, 0xB2u, 0x0Du, 0xF2u, 0x27u, 0x12u, 0x2Bu, 0xB1u, + 0xD1u, 0x5Cu, 0x01u, 0x3Bu, 0x08u, 0x44u, 0x80u, 0xB2u, + 0x9Bu, 0xB2u, 0xF8u, 0xE7u, 0x4Au, 0xABu, 0x1Au, 0x19u, + 0x51u, 0x79u, 0x13u, 0x79u, 0x40u, 0x42u, 0x43u, 0xEAu, + 0x01u, 0x23u, 0x80u, 0xB2u, 0x83u, 0x42u, 0x32u, 0xD0u, + 0x08u, 0x24u, 0x00u, 0x21u, 0x01u, 0x23u, 0x8Du, 0xF8u, + 0x28u, 0x31u, 0x0Au, 0x1Du, 0x00u, 0x23u, 0x8Du, 0xF8u, + 0x29u, 0x41u, 0xADu, 0xF8u, 0x06u, 0x10u, 0x8Du, 0xF8u, + 0x2Au, 0x11u, 0x8Du, 0xF8u, 0x2Bu, 0x31u, 0x92u, 0xB2u, + 0x0Du, 0xF2u, 0x27u, 0x14u, 0xA0u, 0x5Cu, 0x01u, 0x3Au, + 0x03u, 0x44u, 0x92u, 0xB2u, 0x9Bu, 0xB2u, 0x00u, 0x2Au, + 0xF8u, 0xD1u, 0x5Bu, 0x42u, 0x4Bu, 0xAAu, 0x9Bu, 0xB2u, + 0x53u, 0x54u, 0x0Du, 0xF2u, 0x2Du, 0x12u, 0x1Bu, 0x0Au, + 0x53u, 0x54u, 0x0Du, 0xF5u, 0x97u, 0x73u, 0x17u, 0x22u, + 0x5Au, 0x54u, 0x07u, 0x31u, 0x96u, 0x23u, 0x0Du, 0xF1u, + 0x06u, 0x02u, 0x89u, 0xB2u, 0x4Au, 0xA8u, 0x00u, 0xF0u, + 0xD6u, 0xFBu, 0xA1u, 0xE7u, 0x03u, 0x24u, 0xD0u, 0xE7u, + 0x25u, 0xBBu, 0x04u, 0x24u, 0xCDu, 0xE7u, 0x9Du, 0xF8u, + 0x29u, 0x21u, 0x9Du, 0xF8u, 0x2Cu, 0x91u, 0xA2u, 0xF1u, + 0x31u, 0x03u, 0x0Au, 0x2Bu, 0x00u, 0xF2u, 0x2Bu, 0x81u, + 0x01u, 0xA1u, 0x51u, 0xF8u, 0x23u, 0xF0u, 0x00u, 0xBFu, + 0x11u, 0x07u, 0x00u, 0x00u, 0x75u, 0x07u, 0x00u, 0x00u, + 0x7Fu, 0x09u, 0x00u, 0x00u, 0xB9u, 0x07u, 0x00u, 0x00u, + 0x7Bu, 0x08u, 0x00u, 0x00u, 0x7Fu, 0x09u, 0x00u, 0x00u, + 0x85u, 0x08u, 0x00u, 0x00u, 0xADu, 0x08u, 0x00u, 0x00u, + 0xB9u, 0x07u, 0x00u, 0x00u, 0xCBu, 0x08u, 0x00u, 0x00u, + 0x59u, 0x09u, 0x00u, 0x00u, 0x00u, 0x2Cu, 0xD8u, 0xD1u, + 0x20u, 0x46u, 0xFFu, 0xF7u, 0x11u, 0xFFu, 0xB0u, 0xFAu, + 0x80u, 0xF0u, 0x40u, 0x09u, 0x8Du, 0xF8u, 0x2Cu, 0x01u, + 0x29u, 0x46u, 0x9Fu, 0xE7u, 0x00u, 0x2Du, 0xCCu, 0xD0u, + 0x01u, 0x2Cu, 0xCAu, 0xD1u, 0xB9u, 0xF1u, 0x01u, 0x0Fu, + 0xC7u, 0xD8u, 0x80u, 0x4Bu, 0x1Bu, 0x68u, 0x1Bu, 0x68u, + 0xC3u, 0xF3u, 0x07u, 0x42u, 0x91u, 0x45u, 0x02u, 0xD1u, + 0xC3u, 0xF3u, 0x07u, 0x23u, 0x03u, 0xE0u, 0x8Cu, 0xBFu, + 0x00u, 0x23u, 0x4Fu, 0xF4u, 0x80u, 0x73u, 0x8Du, 0xF8u, + 0x2Cu, 0x31u, 0x1Bu, 0x0Au, 0x8Du, 0xF8u, 0x2Du, 0x31u, + 0x00u, 0x24u, 0xFFu, 0x23u, 0x8Du, 0xF8u, 0x2Eu, 0x31u, + 0x8Du, 0xF8u, 0x2Fu, 0x41u, 0x04u, 0x21u, 0x7Du, 0xE7u, + 0x34u, 0x2Au, 0x10u, 0xD1u, 0x00u, 0x2Du, 0xA8u, 0xD0u, + 0x03u, 0x2Cu, 0xA6u, 0xD1u, 0xA9u, 0xF1u, 0x40u, 0x03u, + 0x3Fu, 0x2Bu, 0x8Cu, 0xBFu, 0x4Fu, 0xF4u, 0x90u, 0x76u, + 0x10u, 0x26u, 0x32u, 0x46u, 0x00u, 0x21u, 0x95u, 0xA8u, + 0x01u, 0xF0u, 0xCBu, 0xFCu, 0x03u, 0xE0u, 0x00u, 0x2Du, + 0x97u, 0xD0u, 0x02u, 0x2Cu, 0x95u, 0xD9u, 0x95u, 0xABu, + 0x03u, 0x3Cu, 0x98u, 0x19u, 0x22u, 0x46u, 0x0Du, 0xF2u, + 0x2Fu, 0x11u, 0x01u, 0xF0u, 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0x88u, 0x9Bu, 0xB2u, + 0x4Bu, 0xB3u, 0xBDu, 0xE8u, 0x10u, 0x40u, 0xFFu, 0xF7u, + 0xCFu, 0xBEu, 0x23u, 0xBBu, 0x17u, 0x4Bu, 0x1Bu, 0x78u, + 0x03u, 0xF0u, 0xFFu, 0x01u, 0xFBu, 0xB9u, 0x13u, 0x4Bu, + 0x15u, 0x4Au, 0x1Bu, 0x78u, 0xDBu, 0xB2u, 0x13u, 0x70u, + 0x16u, 0x4Bu, 0x14u, 0x78u, 0x18u, 0x78u, 0x84u, 0x42u, + 0x01u, 0xD2u, 0x19u, 0x70u, 0x0Fu, 0xE0u, 0x19u, 0x78u, + 0x01u, 0x29u, 0x0Cu, 0xD9u, 0x12u, 0x78u, 0xD2u, 0xB2u, + 0x1Au, 0x70u, 0x08u, 0xE0u, 0x5Bu, 0xB9u, 0x0Bu, 0x4Bu, + 0x1Au, 0x78u, 0x01u, 0x2Au, 0x07u, 0xD8u, 0x1Bu, 0x78u, + 0x0Au, 0x4Au, 0xDBu, 0xB2u, 0x13u, 0x70u, 0xBDu, 0xE8u, + 0x10u, 0x40u, 0xFFu, 0xF7u, 0x61u, 0xBDu, 0x00u, 0x20u, + 0x10u, 0xBDu, 0x00u, 0xBFu, 0x04u, 0x60u, 0x00u, 0x40u, + 0x00u, 0x60u, 0x00u, 0x40u, 0x03u, 0x60u, 0x00u, 0x40u, + 0x18u, 0xC1u, 0xFFu, 0x1Fu, 0x02u, 0x60u, 0x00u, 0x40u, + 0xA2u, 0xC1u, 0xFFu, 0x1Fu, 0xA4u, 0xC1u, 0xFFu, 0x1Fu, + 0x01u, 0x60u, 0x00u, 0x40u, 0xA3u, 0xC1u, 0xFFu, 0x1Fu, + 0xF0u, 0xB5u, 0x1Fu, 0x4Du, 0x1Fu, 0x4Bu, 0x2Fu, 0x46u, + 0x1Fu, 0x4Eu, 0x01u, 0x21u, 0x0Cu, 0x20u, 0x4Fu, 0xF0u, + 0x80u, 0x0Eu, 0x4Fu, 0xF0u, 0x08u, 0x0Cu, 0x00u, 0xFBu, + 0x01u, 0x52u, 0x83u, 0xF8u, 0x72u, 0x00u, 0x54u, 0x79u, + 0x34u, 0xB1u, 0x12u, 0x79u, 0x12u, 0x06u, 0x4Cu, 0xBFu, + 0x18u, 0x70u, 0x83u, 0xF8u, 0x00u, 0xC0u, 0x01u, 0xE0u, + 0x83u, 0xF8u, 0x00u, 0xE0u, 0x00u, 0xFBu, 0x01u, 0x72u, + 0x14u, 0x89u, 0x10u, 0x33u, 0xC4u, 0xF3u, 0x07u, 0x24u, + 0x03u, 0xF8u, 0x12u, 0x4Cu, 0x14u, 0x89u, 0x01u, 0x31u, + 0xE4u, 0xB2u, 0x03u, 0xF8u, 0x11u, 0x4Cu, 0xD4u, 0x88u, + 0xE4u, 0xB2u, 0x83u, 0xF8u, 0x68u, 0x40u, 0xD4u, 0x88u, + 0xC4u, 0xF3u, 0x07u, 0x24u, 0x83u, 0xF8u, 0x69u, 0x40u, + 0xD4u, 0x88u, 0xE4u, 0xB2u, 0x83u, 0xF8u, 0x66u, 0x40u, + 0xD2u, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u, 0x83u, 0xF8u, + 0x67u, 0x20u, 0xB3u, 0x42u, 0xCFu, 0xD1u, 0x05u, 0x4Bu, + 0xFFu, 0x22u, 0x1Au, 0x70u, 0xF0u, 0xBDu, 0x00u, 0xBFu, + 0x30u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u, + 0x8Eu, 0x60u, 0x00u, 0x40u, 0x0Au, 0x60u, 0x00u, 0x40u, + 0x06u, 0x4Bu, 0x07u, 0x4Au, 0x1Bu, 0x78u, 0x02u, 0xEBu, + 0xC3u, 0x02u, 0x53u, 0x68u, 0x1Au, 0x7Au, 0x82u, 0x42u, + 0x86u, 0xBFu, 0x03u, 0xEBu, 0xC0u, 0x03u, 0xD8u, 0x68u, + 0x00u, 0x20u, 0x70u, 0x47u, 0x24u, 0xC1u, 0xFFu, 0x1Fu, + 0x64u, 0x22u, 0x00u, 0x00u, 0x2Du, 0xE9u, 0xF0u, 0x47u, + 0x43u, 0x4Bu, 0x1Au, 0x78u, 0x00u, 0x2Au, 0x00u, 0xF0u, + 0x81u, 0x80u, 0x18u, 0x78u, 0x41u, 0x4Fu, 0x01u, 0x38u, + 0xC0u, 0xB2u, 0xFFu, 0xF7u, 0xE1u, 0xFFu, 0xC3u, 0x68u, + 0x05u, 0x7Au, 0xDFu, 0xF8u, 0x08u, 0x81u, 0xDFu, 0xF8u, + 0x08u, 0x91u, 0x3Du, 0x48u, 0x03u, 0xEBu, 0xC5u, 0x05u, + 0x0Cu, 0x26u, 0x4Fu, 0xF0u, 0x01u, 0x0Eu, 0x4Fu, 0xF0u, + 0x00u, 0x0Cu, 0xABu, 0x42u, 0x6Au, 0xD0u, 0x1Au, 0x78u, + 0xBCu, 0x5Cu, 0x18u, 0xF8u, 0x02u, 0x10u, 0x8Cu, 0x42u, + 0x62u, 0xD0u, 0xB9u, 0x5Cu, 0x5Cu, 0x78u, 0x8Cu, 0x42u, + 0x5Eu, 0xD1u, 0x99u, 0xF8u, 0x00u, 0x10u, 0x8Au, 0x42u, + 0x5Au, 0xD1u, 0x93u, 0xF8u, 0x02u, 0xA0u, 0xDCu, 0x78u, + 0x0Au, 0xF0u, 0x7Fu, 0x01u, 0x4Au, 0x1Eu, 0x12u, 0x01u, + 0x1Au, 0xF0u, 0x80u, 0x0Fu, 0xD2u, 0xB2u, 0x04u, 0xF0u, + 0x03u, 0x04u, 0x06u, 0xFBu, 0x01u, 0x0Au, 0x06u, 0xD0u, + 0x01u, 0x2Cu, 0x8Au, 0xF8u, 0x01u, 0xE0u, 0x0Cu, 0xBFu, + 0x07u, 0x24u, 0x0Du, 0x24u, 0x05u, 0xE0u, 0x01u, 0x2Cu, + 0x8Au, 0xF8u, 0x01u, 0xC0u, 0x0Cu, 0xBFu, 0x05u, 0x24u, + 0x09u, 0x24u, 0x8Au, 0xF8u, 0x05u, 0x40u, 0x23u, 0x4Cu, + 0x04u, 0xF8u, 0x02u, 0xE0u, 0x06u, 0xFBu, 0x01u, 0xF4u, + 0xB3u, 0xF8u, 0x04u, 0xA0u, 0x01u, 0x19u, 0xA1u, 0xF8u, + 0x08u, 0xA0u, 0x93u, 0xF8u, 0x02u, 0xA0u, 0x81u, 0xF8u, + 0x04u, 0xA0u, 0x93u, 0xF8u, 0x03u, 0xA0u, 0x00u, 0xF8u, + 0x04u, 0xA0u, 0x81u, 0xF8u, 0x03u, 0xC0u, 0xB1u, 0xF8u, + 0x08u, 0xA0u, 0x19u, 0x4Cu, 0xCAu, 0xF3u, 0x07u, 0x2Au, + 0x04u, 0xF8u, 0x02u, 0xA0u, 0xB1u, 0xF8u, 0x08u, 0xA0u, + 0x01u, 0x34u, 0x5Fu, 0xFAu, 0x8Au, 0xFAu, 0x04u, 0xF8u, + 0x02u, 0xA0u, 0xB1u, 0xF8u, 0x06u, 0xA0u, 0x79u, 0x34u, + 0x5Fu, 0xFAu, 0x8Au, 0xFAu, 0x04u, 0xF8u, 0x02u, 0xA0u, + 0xB1u, 0xF8u, 0x06u, 0xA0u, 0x01u, 0x34u, 0xCAu, 0xF3u, + 0x07u, 0x2Au, 0x04u, 0xF8u, 0x02u, 0xA0u, 0xB1u, 0xF8u, + 0x06u, 0xA0u, 0x03u, 0x3Cu, 0x5Fu, 0xFAu, 0x8Au, 0xFAu, + 0x04u, 0xF8u, 0x02u, 0xA0u, 0x01u, 0x34u, 0x14u, 0x44u, + 0xCAu, 0x88u, 0xC2u, 0xF3u, 0x07u, 0x22u, 0x22u, 0x70u, + 0x08u, 0x33u, 0x92u, 0xE7u, 0xBDu, 0xE8u, 0xF0u, 0x87u, + 0x29u, 0xC1u, 0xFFu, 0x1Fu, 0x16u, 0xC1u, 0xFFu, 0x1Fu, + 0x30u, 0xC1u, 0xFFu, 0x1Fu, 0x0Eu, 0x60u, 0x00u, 0x40u, + 0x0Cu, 0x60u, 0x00u, 0x40u, 0x9Cu, 0xC1u, 0xFFu, 0x1Fu, + 0x04u, 0x60u, 0x00u, 0x40u, 0x08u, 0xB5u, 0x06u, 0x4Bu, + 0x18u, 0x78u, 0x01u, 0x38u, 0xC0u, 0xB2u, 0xFFu, 0xF7u, + 0x4Fu, 0xFFu, 0x20u, 0xB1u, 0x43u, 0x68u, 0x1Bu, 0x79u, + 0x00u, 0xEBu, 0xC3u, 0x00u, 0x40u, 0x69u, 0x08u, 0xBDu, + 0x29u, 0xC1u, 0xFFu, 0x1Fu, 0x00u, 0x21u, 0x2Du, 0xE9u, + 0xF8u, 0x4Fu, 0x0Bu, 0x46u, 0x4Au, 0x4Eu, 0x0Cu, 0x27u, + 0x07u, 0xFBu, 0x01u, 0xF5u, 0x01u, 0x31u, 0x72u, 0x19u, + 0x09u, 0x29u, 0x73u, 0x55u, 0x4Fu, 0xF0u, 0x00u, 0x04u, + 0x93u, 0x70u, 0x45u, 0x4Du, 0x53u, 0x70u, 0xD3u, 0x70u, + 0x53u, 0x71u, 0x13u, 0x81u, 0x93u, 0x72u, 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0x41u, 0x01u, 0x40u, 0x02u, 0x42u, 0x01u, 0x40u, + 0x02u, 0x43u, 0x01u, 0x40u, 0x03u, 0x47u, 0x01u, 0x40u, + 0x03u, 0x48u, 0x01u, 0x40u, 0x02u, 0x4Cu, 0x01u, 0x40u, + 0x01u, 0x51u, 0x01u, 0x40u, 0x7Eu, 0x02u, 0x04u, 0x01u, + 0x1Cu, 0xFFu, 0x64u, 0x03u, 0x7Cu, 0x40u, 0xEEu, 0x0Au, + 0xEEu, 0x0Au, 0x33u, 0x80u, 0x36u, 0x40u, 0xCCu, 0x30u, + 0xA6u, 0x40u, 0xA7u, 0x80u, 0xA6u, 0x40u, 0xA7u, 0x80u, + 0xA6u, 0x40u, 0xA7u, 0x80u, 0x08u, 0x08u, 0x0Fu, 0x40u, + 0xC2u, 0x0Cu, 0xAEu, 0x40u, 0xAFu, 0x80u, 0xEEu, 0x50u, + 0xACu, 0x08u, 0xAFu, 0x40u, 0x00u, 0x0Au, 0x01u, 0x00u, + 0x00u, 0xABu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x0Fu, 0x00u, 0x00u, 0x2Fu, 0x20u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x28u, 0x28u, 0x00u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x00u, 0x0Bu, 0x0Bu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xAAu, 0xAAu, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x43u, 0x43u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0xA4u, 0xA4u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x69u, 0x30u, 0x13u, 0x2Eu, + 0x00u, 0x1Eu, 0x01u, 0x01u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x6Cu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0xA6u, 0x23u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x7Cu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0x7Du, 0x23u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, + 0x9Eu, 0x22u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, + 0xB0u, 0x22u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x9Cu, 0x22u, 0x00u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x82u, 0x03u, 0x40u, 0x00u, 0x03u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xB8u, 0x22u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xECu, 0x22u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0xE0u, 0x22u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0xF8u, 0x22u, 0x00u, 0x00u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x8Fu, 0x23u, 0x00u, 0x00u, + 0x41u, 0x00u, 0x00u, 0x00u, 0xEBu, 0xC1u, 0xFFu, 0x1Fu, + 0x2Cu, 0xC2u, 0xFFu, 0x1Fu, 0x41u, 0x00u, 0x00u, 0x00u, + 0xAAu, 0xC1u, 0xFFu, 0x1Fu, 0xA6u, 0xC1u, 0xFFu, 0x1Fu, + 0x24u, 0x00u, 0x05u, 0x01u, 0x09u, 0x00u, 0xA1u, 0x00u, + 0x09u, 0x00u, 0xA1u, 0x00u, 0x09u, 0x00u, 0x15u, 0x00u, + 0x25u, 0xFFu, 0x75u, 0x08u, 0x95u, 0x40u, 0x91u, 0x02u, + 0x09u, 0x00u, 0x15u, 0x00u, 0x25u, 0xFFu, 0x75u, 0x08u, + 0x95u, 0x40u, 0x81u, 0x02u, 0xC0u, 0xC0u, 0x00u, 0x00u, + 0x0Au, 0x03u, 0x30u, 0x00u, 0x30u, 0x00u, 0x30u, 0x00u, + 0x31u, 0x00u, 0x04u, 0x03u, 0x09u, 0x04u, 0x2Cu, 0x03u, + 0x43u, 0x00u, 0x79u, 0x00u, 0x70u, 0x00u, 0x72u, 0x00u, + 0x65u, 0x00u, 0x73u, 0x00u, 0x73u, 0x00u, 0x20u, 0x00u, + 0x53u, 0x00u, 0x65u, 0x00u, 0x6Du, 0x00u, 0x69u, 0x00u, + 0x63u, 0x00u, 0x6Fu, 0x00u, 0x6Eu, 0x00u, 0x64u, 0x00u, + 0x75u, 0x00u, 0x63u, 0x00u, 0x74u, 0x00u, 0x6Fu, 0x00u, + 0x72u, 0x00u, 0x22u, 0x03u, 0x50u, 0x00u, 0x53u, 0x00u, + 0x6Fu, 0x00u, 0x43u, 0x00u, 0x33u, 0x00u, 0x20u, 0x00u, + 0x42u, 0x00u, 0x6Fu, 0x00u, 0x6Fu, 0x00u, 0x74u, 0x00u, + 0x6Cu, 0x00u, 0x6Fu, 0x00u, 0x61u, 0x00u, 0x64u, 0x00u, + 0x65u, 0x00u, 0x72u, 0x00u, 0x00u, 0x09u, 0x02u, 0x29u, + 0x00u, 0x01u, 0x01u, 0x00u, 0x80u, 0x00u, 0x09u, 0x04u, + 0x00u, 0x00u, 0x02u, 0x03u, 0x00u, 0x00u, 0x02u, 0x09u, + 0x21u, 0x11u, 0x01u, 0x00u, 0x01u, 0x22u, 0x24u, 0x00u, + 0x07u, 0x05u, 0x01u, 0x03u, 0x40u, 0x00u, 0x01u, 0x07u, + 0x05u, 0x82u, 0x03u, 0x40u, 0x00u, 0x01u, 0x12u, 0x01u, + 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0x08u, 0xB4u, 0x04u, + 0x1Du, 0xB7u, 0x03u, 0x30u, 0x01u, 0x02u, 0x80u, 0x01u, + 0xF8u, 0xB5u, 0x00u, 0xBFu, 0xF8u, 0xBCu, 0x08u, 0xBCu, + 0x9Eu, 0x46u, 0x70u, 0x47u, 0x51u, 0x00u, 0x00u, 0x00u, + 0xE9u, 0x03u, 0x00u, 0x00u, 0xF8u, 0xB5u, 0x00u, 0xBFu, + 0xF8u, 0xBCu, 0x08u, 0xBCu, 0x9Eu, 0x46u, 0x70u, 0x47u, + 0x2Du, 0x00u, 0x00u, 0x00u, 0xF0u, 0x23u, 0x00u, 0x00u, + 0xC8u, 0xC0u, 0xFFu, 0x1Fu, 0x20u, 0x00u, 0x00u, 0x00u, + 0x48u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x84u, 0x21u, 0x00u, 0x00u, + 0x88u, 0x21u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x7Du, + 0x00u, 0xFAu, 0x00u, 0x00u, 0x40u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x90u, 0xD0u, 0x03u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cymeta"), used)) +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_metadata[] = { + 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, + 0x2Eu, 0x20u, 0x7Du, 0xBCu}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cycustnvl"), used)) +#elif defined(__ICCARM__) +#pragma location=".cycustnvl" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_custnvl[] = { + 0x80u, 0x80u, 0x40u, 0x05u}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cywolatch"), used)) +#elif defined(__ICCARM__) +#pragma location=".cywolatch" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_wonvl[] = { + 0xBCu, 0x90u, 0xACu, 0xAFu}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +__attribute__ ((__section__(".cyflashprotect"), used)) +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8 cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf new file mode 100644 index 0000000..6e96b03 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cybootloader.icf @@ -0,0 +1,3 @@ +/* GENERATED CODE -- CHANGES WILL BE OVERWRITTEN */ + +define symbol CYDEV_BTLDR_SIZE = 0x00002500; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h new file mode 100644 index 0000000..59d3e2c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* File Name: cydevice.h +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h new file mode 100644 index 0000000..b05fd82 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE_MSIZE 0x00004000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc new file mode 100644 index 0000000..754b960 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* File Name: cydevicegnu.inc +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYDEV_FLASH_DATA_MBASE, 0x00000000 +.set CYDEV_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA_MBASE, 0x20000000 +.set CYDEV_SRAM_DATA_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 +.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 +.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 +.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 +.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 +.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYDEV_CLKDIST_CR, 0x40004000 +.set CYDEV_CLKDIST_LD, 0x40004001 +.set CYDEV_CLKDIST_WRK0, 0x40004002 +.set CYDEV_CLKDIST_WRK1, 0x40004003 +.set CYDEV_CLKDIST_MSTR0, 0x40004004 +.set CYDEV_CLKDIST_MSTR1, 0x40004005 +.set CYDEV_CLKDIST_BCFG0, 0x40004006 +.set CYDEV_CLKDIST_BCFG1, 0x40004007 +.set CYDEV_CLKDIST_BCFG2, 0x40004008 +.set CYDEV_CLKDIST_UCFG, 0x40004009 +.set CYDEV_CLKDIST_DLY0, 0x4000400a +.set CYDEV_CLKDIST_DLY1, 0x4000400b +.set CYDEV_CLKDIST_DMASK, 0x40004010 +.set CYDEV_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYDEV_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 +.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 +.set CYDEV_FASTCLK_PLL_P, 0x40004222 +.set CYDEV_FASTCLK_PLL_Q, 0x40004223 +.set CYDEV_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 +.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYDEV_SLOWCLK_X32_CR, 0x40004308 +.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 +.set CYDEV_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYDEV_BOOST_CR0, 0x40004320 +.set CYDEV_BOOST_CR1, 0x40004321 +.set CYDEV_BOOST_CR2, 0x40004322 +.set CYDEV_BOOST_CR3, 0x40004323 +.set CYDEV_BOOST_SR, 0x40004324 +.set CYDEV_BOOST_CR4, 0x40004325 +.set CYDEV_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYDEV_PWRSYS_CR0, 0x40004330 +.set CYDEV_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYDEV_PM_TW_CFG0, 0x40004380 +.set CYDEV_PM_TW_CFG1, 0x40004381 +.set CYDEV_PM_TW_CFG2, 0x40004382 +.set CYDEV_PM_WDT_CFG, 0x40004383 +.set CYDEV_PM_WDT_CR, 0x40004384 +.set CYDEV_PM_INT_SR, 0x40004390 +.set CYDEV_PM_MODE_CFG0, 0x40004391 +.set CYDEV_PM_MODE_CFG1, 0x40004392 +.set CYDEV_PM_MODE_CSR, 0x40004393 +.set CYDEV_PM_USB_CR0, 0x40004394 +.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 +.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 +.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYDEV_PM_ACT_CFG0, 0x400043a0 +.set CYDEV_PM_ACT_CFG1, 0x400043a1 +.set CYDEV_PM_ACT_CFG2, 0x400043a2 +.set CYDEV_PM_ACT_CFG3, 0x400043a3 +.set CYDEV_PM_ACT_CFG4, 0x400043a4 +.set CYDEV_PM_ACT_CFG5, 0x400043a5 +.set CYDEV_PM_ACT_CFG6, 0x400043a6 +.set CYDEV_PM_ACT_CFG7, 0x400043a7 +.set CYDEV_PM_ACT_CFG8, 0x400043a8 +.set CYDEV_PM_ACT_CFG9, 0x400043a9 +.set CYDEV_PM_ACT_CFG10, 0x400043aa +.set CYDEV_PM_ACT_CFG11, 0x400043ab +.set CYDEV_PM_ACT_CFG12, 0x400043ac +.set CYDEV_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYDEV_PM_STBY_CFG0, 0x400043b0 +.set CYDEV_PM_STBY_CFG1, 0x400043b1 +.set CYDEV_PM_STBY_CFG2, 0x400043b2 +.set CYDEV_PM_STBY_CFG3, 0x400043b3 +.set CYDEV_PM_STBY_CFG4, 0x400043b4 +.set CYDEV_PM_STBY_CFG5, 0x400043b5 +.set CYDEV_PM_STBY_CFG6, 0x400043b6 +.set CYDEV_PM_STBY_CFG7, 0x400043b7 +.set CYDEV_PM_STBY_CFG8, 0x400043b8 +.set CYDEV_PM_STBY_CFG9, 0x400043b9 +.set CYDEV_PM_STBY_CFG10, 0x400043ba +.set CYDEV_PM_STBY_CFG11, 0x400043bb +.set CYDEV_PM_STBY_CFG12, 0x400043bc +.set CYDEV_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYDEV_PM_AVAIL_CR0, 0x400043c0 +.set CYDEV_PM_AVAIL_CR1, 0x400043c1 +.set CYDEV_PM_AVAIL_CR2, 0x400043c2 +.set CYDEV_PM_AVAIL_CR3, 0x400043c3 +.set CYDEV_PM_AVAIL_CR4, 0x400043c4 +.set CYDEV_PM_AVAIL_CR5, 0x400043c5 +.set CYDEV_PM_AVAIL_CR6, 0x400043c6 +.set CYDEV_PM_AVAIL_SR0, 0x400043d0 +.set CYDEV_PM_AVAIL_SR1, 0x400043d1 +.set CYDEV_PM_AVAIL_SR2, 0x400043d2 +.set CYDEV_PM_AVAIL_SR3, 0x400043d3 +.set CYDEV_PM_AVAIL_SR4, 0x400043d4 +.set CYDEV_PM_AVAIL_SR5, 0x400043d5 +.set CYDEV_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 +.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 +.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 +.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 +.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 +.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYDEV_MFGCFG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 +.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 +.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 +.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 +.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 +.set CYDEV_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYDEV_RESET_IPOR_CR0, 0x400046f0 +.set CYDEV_RESET_IPOR_CR1, 0x400046f1 +.set CYDEV_RESET_IPOR_CR2, 0x400046f2 +.set CYDEV_RESET_IPOR_CR3, 0x400046f3 +.set CYDEV_RESET_CR0, 0x400046f4 +.set CYDEV_RESET_CR1, 0x400046f5 +.set CYDEV_RESET_CR2, 0x400046f6 +.set CYDEV_RESET_CR3, 0x400046f7 +.set CYDEV_RESET_CR4, 0x400046f8 +.set CYDEV_RESET_CR5, 0x400046f9 +.set CYDEV_RESET_SR0, 0x400046fa +.set CYDEV_RESET_SR1, 0x400046fb +.set CYDEV_RESET_SR2, 0x400046fc +.set CYDEV_RESET_SR3, 0x400046fd +.set CYDEV_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYDEV_SPC_FM_EE_CR, 0x40004700 +.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYDEV_SPC_EE_SCR, 0x40004702 +.set CYDEV_SPC_EE_ERR, 0x40004703 +.set CYDEV_SPC_CPU_DATA, 0x40004720 +.set CYDEV_SPC_DMA_DATA, 0x40004721 +.set CYDEV_SPC_SR, 0x40004722 +.set CYDEV_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYDEV_CACHE_CC_CTL, 0x40004800 +.set CYDEV_CACHE_ECC_CORR, 0x40004880 +.set CYDEV_CACHE_ECC_ERR, 0x40004888 +.set CYDEV_CACHE_FLASH_ERR, 0x40004890 +.set CYDEV_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYDEV_I2C_XCFG, 0x400049c8 +.set CYDEV_I2C_ADR, 0x400049ca +.set CYDEV_I2C_CFG, 0x400049d6 +.set CYDEV_I2C_CSR, 0x400049d7 +.set CYDEV_I2C_D, 0x400049d8 +.set CYDEV_I2C_MCSR, 0x400049d9 +.set CYDEV_I2C_CLK_DIV1, 0x400049db +.set CYDEV_I2C_CLK_DIV2, 0x400049dc +.set CYDEV_I2C_TMOUT_CSR, 0x400049dd +.set CYDEV_I2C_TMOUT_SR, 0x400049de +.set CYDEV_I2C_TMOUT_CFG0, 0x400049df +.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYDEV_DEC_CR, 0x40004e00 +.set CYDEV_DEC_SR, 0x40004e01 +.set CYDEV_DEC_SHIFT1, 0x40004e02 +.set CYDEV_DEC_SHIFT2, 0x40004e03 +.set CYDEV_DEC_DR2, 0x40004e04 +.set CYDEV_DEC_DR2H, 0x40004e05 +.set CYDEV_DEC_DR1, 0x40004e06 +.set CYDEV_DEC_OCOR, 0x40004e08 +.set CYDEV_DEC_OCORM, 0x40004e09 +.set CYDEV_DEC_OCORH, 0x40004e0a +.set CYDEV_DEC_GCOR, 0x40004e0c +.set CYDEV_DEC_GCORH, 0x40004e0d +.set CYDEV_DEC_GVAL, 0x40004e0e +.set CYDEV_DEC_OUTSAMP, 0x40004e10 +.set CYDEV_DEC_OUTSAMPM, 0x40004e11 +.set CYDEV_DEC_OUTSAMPH, 0x40004e12 +.set CYDEV_DEC_OUTSAMPS, 0x40004e13 +.set CYDEV_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYDEV_TMR0_CFG0, 0x40004f00 +.set CYDEV_TMR0_CFG1, 0x40004f01 +.set CYDEV_TMR0_CFG2, 0x40004f02 +.set CYDEV_TMR0_SR0, 0x40004f03 +.set CYDEV_TMR0_PER0, 0x40004f04 +.set CYDEV_TMR0_PER1, 0x40004f05 +.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 +.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 +.set CYDEV_TMR0_CAP0, 0x40004f08 +.set CYDEV_TMR0_CAP1, 0x40004f09 +.set CYDEV_TMR0_RT0, 0x40004f0a +.set CYDEV_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYDEV_TMR1_CFG0, 0x40004f0c +.set CYDEV_TMR1_CFG1, 0x40004f0d +.set CYDEV_TMR1_CFG2, 0x40004f0e +.set CYDEV_TMR1_SR0, 0x40004f0f +.set CYDEV_TMR1_PER0, 0x40004f10 +.set CYDEV_TMR1_PER1, 0x40004f11 +.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 +.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 +.set CYDEV_TMR1_CAP0, 0x40004f14 +.set CYDEV_TMR1_CAP1, 0x40004f15 +.set CYDEV_TMR1_RT0, 0x40004f16 +.set CYDEV_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYDEV_TMR2_CFG0, 0x40004f18 +.set CYDEV_TMR2_CFG1, 0x40004f19 +.set CYDEV_TMR2_CFG2, 0x40004f1a +.set CYDEV_TMR2_SR0, 0x40004f1b +.set CYDEV_TMR2_PER0, 0x40004f1c +.set CYDEV_TMR2_PER1, 0x40004f1d +.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e +.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f +.set CYDEV_TMR2_CAP0, 0x40004f20 +.set CYDEV_TMR2_CAP1, 0x40004f21 +.set CYDEV_TMR2_RT0, 0x40004f22 +.set CYDEV_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYDEV_TMR3_CFG0, 0x40004f24 +.set CYDEV_TMR3_CFG1, 0x40004f25 +.set CYDEV_TMR3_CFG2, 0x40004f26 +.set CYDEV_TMR3_SR0, 0x40004f27 +.set CYDEV_TMR3_PER0, 0x40004f28 +.set CYDEV_TMR3_PER1, 0x40004f29 +.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a +.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b +.set CYDEV_TMR3_CAP0, 0x40004f2c +.set CYDEV_TMR3_CAP1, 0x40004f2d +.set CYDEV_TMR3_RT0, 0x40004f2e +.set CYDEV_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 +.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 +.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 +.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 +.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 +.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 +.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 +.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 +.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 +.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a +.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b +.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c +.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d +.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e +.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 +.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 +.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 +.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 +.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 +.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 +.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 +.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 +.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 +.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a +.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b +.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c +.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d +.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e +.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 +.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 +.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 +.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 +.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 +.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 +.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 +.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 +.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 +.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a +.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b +.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c +.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d +.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e +.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 +.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 +.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 +.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 +.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 +.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 +.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 +.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 +.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 +.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 +.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 +.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 +.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 +.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 +.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 +.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 +.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a +.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b +.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c +.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 +.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 +.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 +.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 +.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 +.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 +.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 +.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 +.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 +.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 +.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a +.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b +.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c +.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d +.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e +.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 +.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 +.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 +.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 +.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 +.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 +.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 +.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 +.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 +.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 +.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a +.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b +.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c +.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d +.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e +.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 +.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 +.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 +.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 +.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 +.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 +.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 +.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 +.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 +.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 +.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a +.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b +.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c +.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d +.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e +.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 +.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 +.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 +.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 +.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 +.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 +.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 +.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 +.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 +.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 +.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a +.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b +.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c +.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d +.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e +.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 +.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 +.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 +.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 +.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 +.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 +.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 +.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 +.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 +.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 +.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a +.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b +.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c +.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d +.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e +.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 +.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 +.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 +.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 +.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 +.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 +.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 +.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 +.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 +.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 +.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a +.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b +.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c +.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d +.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e +.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 +.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 +.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 +.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 +.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 +.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 +.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 +.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 +.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 +.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 +.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a +.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b +.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c +.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d +.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e +.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 +.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 +.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 +.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 +.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 +.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 +.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 +.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 +.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca +.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb +.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd +.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce +.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 +.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 +.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 +.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 +.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 +.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 +.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 +.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 +.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 +.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa +.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb +.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc +.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd +.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe +.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 +.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 +.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 +.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 +.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 +.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 +.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 +.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a +.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b +.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d +.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 +.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 +.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 +.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 +.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 +.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 +.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 +.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a +.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b +.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d +.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 +.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 +.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 +.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 +.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 +.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 +.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 +.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a +.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b +.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d +.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 +.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 +.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 +.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 +.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 +.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 +.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 +.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 +.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 +.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 +.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 +.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a +.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b +.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d +.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYDEV_EMIF_NO_UDB, 0x40005400 +.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYDEV_EMIF_MEM_DWN, 0x40005402 +.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 +.set CYDEV_EMIF_CLOCK_EN, 0x40005404 +.set CYDEV_EMIF_EM_TYPE, 0x40005405 +.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 +.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 +.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 +.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d +.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 +.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 +.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 +.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d +.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d +.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e +.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 +.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 +.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 +.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 +.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 +.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 +.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 +.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 +.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 +.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a +.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b +.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c +.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d +.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e +.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f +.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 +.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 +.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 +.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 +.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 +.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 +.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 +.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 +.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 +.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 +.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a +.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b +.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c +.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d +.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e +.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 +.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 +.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 +.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 +.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 +.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 +.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a +.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b +.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c +.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d +.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 +.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 +.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 +.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 +.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 +.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 +.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a +.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b +.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 +.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 +.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 +.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 +.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 +.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 +.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a +.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b +.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 +.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 +.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 +.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 +.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 +.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 +.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a +.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b +.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 +.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 +.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 +.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 +.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 +.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 +.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a +.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b +.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 +.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 +.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 +.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a +.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b +.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c +.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 +.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 +.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 +.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a +.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b +.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c +.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 +.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 +.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 +.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 +.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca +.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb +.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc +.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace +.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 +.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 +.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 +.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 +.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada +.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb +.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc +.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade +.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 +.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 +.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 +.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 +.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 +.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 +.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 +.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 +.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a +.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b +.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c +.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e +.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 +.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 +.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 +.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a +.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d +.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e +.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f +.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 +.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 +.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 +.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 +.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 +.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a +.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b +.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYDEV_USB_EP0_DR0, 0x40006000 +.set CYDEV_USB_EP0_DR1, 0x40006001 +.set CYDEV_USB_EP0_DR2, 0x40006002 +.set CYDEV_USB_EP0_DR3, 0x40006003 +.set CYDEV_USB_EP0_DR4, 0x40006004 +.set CYDEV_USB_EP0_DR5, 0x40006005 +.set CYDEV_USB_EP0_DR6, 0x40006006 +.set CYDEV_USB_EP0_DR7, 0x40006007 +.set CYDEV_USB_CR0, 0x40006008 +.set CYDEV_USB_CR1, 0x40006009 +.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a +.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c +.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d +.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e +.set CYDEV_USB_USBIO_CR0, 0x40006010 +.set CYDEV_USB_USBIO_CR1, 0x40006012 +.set CYDEV_USB_DYN_RECONFIG, 0x40006014 +.set CYDEV_USB_SOF0, 0x40006018 +.set CYDEV_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c +.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d +.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e +.set CYDEV_USB_EP0_CR, 0x40006028 +.set CYDEV_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c +.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d +.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c +.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d +.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c +.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d +.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c +.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d +.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c +.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d +.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c +.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d +.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 +.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYDEV_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW1_WA, 0x40006084 +.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYDEV_USB_ARB_RW1_RA, 0x40006086 +.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYDEV_USB_ARB_RW1_DR, 0x40006088 +.set CYDEV_USB_BUF_SIZE, 0x4000608c +.set CYDEV_USB_EP_ACTIVE, 0x4000608e +.set CYDEV_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 +.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYDEV_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW2_WA, 0x40006094 +.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYDEV_USB_ARB_RW2_RA, 0x40006096 +.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYDEV_USB_ARB_RW2_DR, 0x40006098 +.set CYDEV_USB_ARB_CFG, 0x4000609c +.set CYDEV_USB_USB_CLK_EN, 0x4000609d +.set CYDEV_USB_ARB_INT_EN, 0x4000609e +.set CYDEV_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 +.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 +.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 +.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 +.set CYDEV_USB_CWA, 0x400060ac +.set CYDEV_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 +.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 +.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 +.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 +.set CYDEV_USB_DMA_THRES, 0x400060bc +.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 +.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 +.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 +.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 +.set CYDEV_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 +.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 +.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 +.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 +.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 +.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 +.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 +.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 +.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 +.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 +.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f +.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f +.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 +.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 +.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 +.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 +.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 +.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 +.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 +.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 +.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 +.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 +.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a +.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b +.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c +.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d +.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e +.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a +.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b +.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c +.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d +.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e +.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa +.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab +.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac +.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad +.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae +.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b +.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b +.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 +.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 +.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 +.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 +.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 +.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 +.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a +.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a +.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa +.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYDEV_PHUB_CFG, 0x40007000 +.set CYDEV_PHUB_ERR, 0x40007004 +.set CYDEV_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYDEV_PHUB_CH0_ACTION, 0x40007014 +.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYDEV_PHUB_CH1_ACTION, 0x40007024 +.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYDEV_PHUB_CH2_ACTION, 0x40007034 +.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYDEV_PHUB_CH3_ACTION, 0x40007044 +.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYDEV_PHUB_CH4_ACTION, 0x40007054 +.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYDEV_PHUB_CH5_ACTION, 0x40007064 +.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYDEV_PHUB_CH6_ACTION, 0x40007074 +.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYDEV_PHUB_CH7_ACTION, 0x40007084 +.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYDEV_PHUB_CH8_ACTION, 0x40007094 +.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 +.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 +.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 +.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 +.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 +.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 +.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYDEV_PHUB_CH15_ACTION, 0x40007104 +.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYDEV_PHUB_CH16_ACTION, 0x40007114 +.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYDEV_PHUB_CH17_ACTION, 0x40007124 +.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYDEV_PHUB_CH18_ACTION, 0x40007134 +.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYDEV_PHUB_CH19_ACTION, 0x40007144 +.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYDEV_PHUB_CH20_ACTION, 0x40007154 +.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYDEV_PHUB_CH21_ACTION, 0x40007164 +.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYDEV_PHUB_CH22_ACTION, 0x40007174 +.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYDEV_PHUB_CH23_ACTION, 0x40007184 +.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYDEV_EE_DATA_MBASE, 0x40008000 +.set CYDEV_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 +.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 +.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYDEV_CAN0_CSR_CMD, 0x4000a010 +.set CYDEV_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYDEV_CAN0_TX0_CMD, 0x4000a020 +.set CYDEV_CAN0_TX0_ID, 0x4000a024 +.set CYDEV_CAN0_TX0_DH, 0x4000a028 +.set CYDEV_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYDEV_CAN0_TX1_CMD, 0x4000a030 +.set CYDEV_CAN0_TX1_ID, 0x4000a034 +.set CYDEV_CAN0_TX1_DH, 0x4000a038 +.set CYDEV_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYDEV_CAN0_TX2_CMD, 0x4000a040 +.set CYDEV_CAN0_TX2_ID, 0x4000a044 +.set CYDEV_CAN0_TX2_DH, 0x4000a048 +.set CYDEV_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYDEV_CAN0_TX3_CMD, 0x4000a050 +.set CYDEV_CAN0_TX3_ID, 0x4000a054 +.set CYDEV_CAN0_TX3_DH, 0x4000a058 +.set CYDEV_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYDEV_CAN0_TX4_CMD, 0x4000a060 +.set CYDEV_CAN0_TX4_ID, 0x4000a064 +.set CYDEV_CAN0_TX4_DH, 0x4000a068 +.set CYDEV_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYDEV_CAN0_TX5_CMD, 0x4000a070 +.set CYDEV_CAN0_TX5_ID, 0x4000a074 +.set CYDEV_CAN0_TX5_DH, 0x4000a078 +.set CYDEV_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYDEV_CAN0_TX6_CMD, 0x4000a080 +.set CYDEV_CAN0_TX6_ID, 0x4000a084 +.set CYDEV_CAN0_TX6_DH, 0x4000a088 +.set CYDEV_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYDEV_CAN0_TX7_CMD, 0x4000a090 +.set CYDEV_CAN0_TX7_ID, 0x4000a094 +.set CYDEV_CAN0_TX7_DH, 0x4000a098 +.set CYDEV_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 +.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 +.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 +.set CYDEV_CAN0_RX0_DL, 0x4000a0ac +.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 +.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 +.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 +.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 +.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 +.set CYDEV_CAN0_RX1_DL, 0x4000a0cc +.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 +.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 +.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 +.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 +.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 +.set CYDEV_CAN0_RX2_DL, 0x4000a0ec +.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 +.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 +.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYDEV_CAN0_RX3_CMD, 0x4000a100 +.set CYDEV_CAN0_RX3_ID, 0x4000a104 +.set CYDEV_CAN0_RX3_DH, 0x4000a108 +.set CYDEV_CAN0_RX3_DL, 0x4000a10c +.set CYDEV_CAN0_RX3_AMR, 0x4000a110 +.set CYDEV_CAN0_RX3_ACR, 0x4000a114 +.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 +.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYDEV_CAN0_RX4_CMD, 0x4000a120 +.set CYDEV_CAN0_RX4_ID, 0x4000a124 +.set CYDEV_CAN0_RX4_DH, 0x4000a128 +.set CYDEV_CAN0_RX4_DL, 0x4000a12c +.set CYDEV_CAN0_RX4_AMR, 0x4000a130 +.set CYDEV_CAN0_RX4_ACR, 0x4000a134 +.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 +.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYDEV_CAN0_RX5_CMD, 0x4000a140 +.set CYDEV_CAN0_RX5_ID, 0x4000a144 +.set CYDEV_CAN0_RX5_DH, 0x4000a148 +.set CYDEV_CAN0_RX5_DL, 0x4000a14c +.set CYDEV_CAN0_RX5_AMR, 0x4000a150 +.set CYDEV_CAN0_RX5_ACR, 0x4000a154 +.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 +.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYDEV_CAN0_RX6_CMD, 0x4000a160 +.set CYDEV_CAN0_RX6_ID, 0x4000a164 +.set CYDEV_CAN0_RX6_DH, 0x4000a168 +.set CYDEV_CAN0_RX6_DL, 0x4000a16c +.set CYDEV_CAN0_RX6_AMR, 0x4000a170 +.set CYDEV_CAN0_RX6_ACR, 0x4000a174 +.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 +.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYDEV_CAN0_RX7_CMD, 0x4000a180 +.set CYDEV_CAN0_RX7_ID, 0x4000a184 +.set CYDEV_CAN0_RX7_DH, 0x4000a188 +.set CYDEV_CAN0_RX7_DL, 0x4000a18c +.set CYDEV_CAN0_RX7_AMR, 0x4000a190 +.set CYDEV_CAN0_RX7_ACR, 0x4000a194 +.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 +.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 +.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 +.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 +.set CYDEV_CAN0_RX8_DL, 0x4000a1ac +.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 +.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 +.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 +.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 +.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 +.set CYDEV_CAN0_RX9_DL, 0x4000a1cc +.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 +.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 +.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 +.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 +.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 +.set CYDEV_CAN0_RX10_DL, 0x4000a1ec +.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 +.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 +.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYDEV_CAN0_RX11_CMD, 0x4000a200 +.set CYDEV_CAN0_RX11_ID, 0x4000a204 +.set CYDEV_CAN0_RX11_DH, 0x4000a208 +.set CYDEV_CAN0_RX11_DL, 0x4000a20c +.set CYDEV_CAN0_RX11_AMR, 0x4000a210 +.set CYDEV_CAN0_RX11_ACR, 0x4000a214 +.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 +.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYDEV_CAN0_RX12_CMD, 0x4000a220 +.set CYDEV_CAN0_RX12_ID, 0x4000a224 +.set CYDEV_CAN0_RX12_DH, 0x4000a228 +.set CYDEV_CAN0_RX12_DL, 0x4000a22c +.set CYDEV_CAN0_RX12_AMR, 0x4000a230 +.set CYDEV_CAN0_RX12_ACR, 0x4000a234 +.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 +.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYDEV_CAN0_RX13_CMD, 0x4000a240 +.set CYDEV_CAN0_RX13_ID, 0x4000a244 +.set CYDEV_CAN0_RX13_DH, 0x4000a248 +.set CYDEV_CAN0_RX13_DL, 0x4000a24c +.set CYDEV_CAN0_RX13_AMR, 0x4000a250 +.set CYDEV_CAN0_RX13_ACR, 0x4000a254 +.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 +.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYDEV_CAN0_RX14_CMD, 0x4000a260 +.set CYDEV_CAN0_RX14_ID, 0x4000a264 +.set CYDEV_CAN0_RX14_DH, 0x4000a268 +.set CYDEV_CAN0_RX14_DL, 0x4000a26c +.set CYDEV_CAN0_RX14_AMR, 0x4000a270 +.set CYDEV_CAN0_RX14_ACR, 0x4000a274 +.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 +.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYDEV_CAN0_RX15_CMD, 0x4000a280 +.set CYDEV_CAN0_RX15_ID, 0x4000a284 +.set CYDEV_CAN0_RX15_DH, 0x4000a288 +.set CYDEV_CAN0_RX15_DL, 0x4000a28c +.set CYDEV_CAN0_RX15_AMR, 0x4000a290 +.set CYDEV_CAN0_RX15_ACR, 0x4000a294 +.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 +.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYDEV_DFB0_CR, 0x4000c780 +.set CYDEV_DFB0_SR, 0x4000c784 +.set CYDEV_DFB0_RAM_EN, 0x4000c788 +.set CYDEV_DFB0_RAM_DIR, 0x4000c78c +.set CYDEV_DFB0_SEMA, 0x4000c790 +.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 +.set CYDEV_DFB0_INT_CTRL, 0x4000c798 +.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c +.set CYDEV_DFB0_STAGEA, 0x4000c7a0 +.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 +.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 +.set CYDEV_DFB0_STAGEB, 0x4000c7a4 +.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 +.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 +.set CYDEV_DFB0_HOLDA, 0x4000c7a8 +.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 +.set CYDEV_DFB0_HOLDAH, 0x4000c7aa +.set CYDEV_DFB0_HOLDAS, 0x4000c7ab +.set CYDEV_DFB0_HOLDB, 0x4000c7ac +.set CYDEV_DFB0_HOLDBM, 0x4000c7ad +.set CYDEV_DFB0_HOLDBH, 0x4000c7ae +.set CYDEV_DFB0_HOLDBS, 0x4000c7af +.set CYDEV_DFB0_COHER, 0x4000c7b0 +.set CYDEV_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 +.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 +.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 +.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 +.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 +.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 +.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 +.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 +.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 +.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 +.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a +.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b +.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c +.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d +.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e +.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f +.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 +.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 +.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 +.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 +.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 +.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 +.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 +.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 +.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 +.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 +.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a +.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b +.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c +.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d +.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e +.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f +.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 +.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 +.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 +.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 +.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 +.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a +.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c +.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 +.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 +.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 +.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 +.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 +.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 +.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 +.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 +.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 +.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 +.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca +.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb +.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc +.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd +.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce +.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf +.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 +.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 +.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 +.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 +.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 +.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 +.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 +.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 +.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 +.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 +.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da +.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db +.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc +.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd +.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de +.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df +.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea +.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec +.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 +.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 +.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 +.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 +.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 +.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 +.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 +.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 +.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 +.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 +.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a +.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b +.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c +.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d +.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e +.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f +.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 +.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 +.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 +.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 +.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 +.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 +.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 +.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 +.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 +.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 +.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a +.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b +.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c +.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d +.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e +.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f +.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 +.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 +.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 +.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 +.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 +.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a +.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c +.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 +.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 +.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 +.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 +.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 +.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 +.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 +.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 +.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 +.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 +.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca +.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb +.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc +.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd +.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce +.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf +.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 +.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 +.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 +.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 +.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 +.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 +.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 +.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 +.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 +.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 +.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da +.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db +.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc +.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd +.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de +.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df +.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea +.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec +.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 +.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 +.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 +.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 +.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 +.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 +.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 +.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 +.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 +.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 +.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a +.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b +.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c +.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d +.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e +.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f +.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 +.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 +.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 +.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 +.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 +.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 +.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 +.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 +.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 +.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 +.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a +.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b +.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c +.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d +.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e +.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f +.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 +.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 +.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 +.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 +.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 +.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a +.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c +.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 +.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 +.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 +.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 +.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 +.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 +.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 +.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 +.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 +.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 +.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca +.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb +.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc +.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd +.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce +.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf +.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 +.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 +.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 +.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 +.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 +.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 +.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 +.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 +.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 +.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 +.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da +.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db +.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc +.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd +.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de +.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df +.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea +.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec +.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 +.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 +.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 +.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 +.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 +.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 +.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 +.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 +.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 +.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 +.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a +.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b +.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c +.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d +.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e +.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f +.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 +.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 +.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 +.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 +.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 +.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 +.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 +.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 +.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 +.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 +.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a +.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b +.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c +.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d +.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e +.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f +.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 +.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 +.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 +.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 +.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 +.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a +.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c +.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 +.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 +.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 +.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 +.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 +.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 +.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 +.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 +.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 +.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 +.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca +.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb +.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc +.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd +.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce +.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf +.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 +.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 +.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 +.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 +.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 +.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 +.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 +.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 +.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 +.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 +.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da +.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db +.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc +.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd +.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de +.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df +.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea +.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec +.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 +.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 +.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 +.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 +.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 +.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 +.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 +.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 +.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 +.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 +.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a +.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b +.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c +.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d +.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e +.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f +.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 +.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 +.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 +.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 +.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 +.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 +.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 +.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 +.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 +.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 +.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a +.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b +.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c +.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d +.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e +.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f +.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 +.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 +.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 +.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 +.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 +.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a +.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c +.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 +.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 +.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 +.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 +.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 +.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 +.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 +.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 +.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 +.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 +.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca +.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb +.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc +.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd +.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce +.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf +.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 +.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 +.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 +.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 +.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 +.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 +.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 +.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 +.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 +.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 +.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da +.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db +.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc +.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd +.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de +.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df +.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea +.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec +.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 +.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 +.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 +.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 +.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 +.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 +.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 +.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 +.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 +.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 +.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a +.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b +.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c +.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d +.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e +.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f +.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 +.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 +.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 +.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 +.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 +.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 +.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 +.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 +.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 +.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 +.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a +.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b +.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c +.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d +.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e +.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f +.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca +.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb +.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc +.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd +.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace +.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf +.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada +.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb +.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc +.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add +.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade +.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf +.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea +.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec +.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 +.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 +.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 +.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 +.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 +.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 +.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 +.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 +.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 +.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 +.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a +.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b +.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c +.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d +.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e +.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f +.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 +.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 +.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 +.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 +.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 +.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 +.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 +.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 +.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 +.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 +.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a +.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b +.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c +.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d +.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e +.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f +.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca +.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb +.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc +.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd +.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce +.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf +.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda +.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb +.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc +.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd +.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde +.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf +.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea +.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec +.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 +.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 +.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 +.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 +.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 +.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 +.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 +.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 +.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 +.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 +.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a +.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b +.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c +.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d +.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e +.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f +.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 +.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 +.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 +.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 +.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 +.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 +.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 +.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 +.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 +.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 +.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a +.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b +.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c +.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d +.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e +.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f +.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca +.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb +.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc +.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd +.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece +.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf +.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda +.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb +.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc +.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd +.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede +.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf +.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea +.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec +.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 +.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 +.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 +.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 +.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 +.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 +.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 +.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 +.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 +.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 +.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a +.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b +.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c +.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d +.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e +.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f +.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 +.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 +.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 +.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 +.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 +.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 +.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 +.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 +.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 +.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 +.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a +.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b +.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c +.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d +.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e +.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f +.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 +.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 +.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 +.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 +.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 +.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a +.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c +.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 +.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 +.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 +.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 +.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 +.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 +.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 +.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 +.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 +.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 +.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca +.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb +.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc +.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd +.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce +.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf +.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 +.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 +.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 +.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 +.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 +.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 +.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 +.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 +.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 +.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 +.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da +.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db +.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc +.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd +.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de +.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df +.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea +.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec +.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 +.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 +.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 +.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 +.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 +.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 +.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 +.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 +.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 +.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 +.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a +.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b +.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c +.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d +.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e +.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f +.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 +.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 +.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 +.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 +.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 +.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 +.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 +.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 +.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 +.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 +.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a +.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b +.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c +.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d +.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e +.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f +.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 +.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 +.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 +.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 +.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 +.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a +.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c +.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 +.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 +.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 +.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 +.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 +.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 +.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 +.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 +.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 +.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 +.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca +.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb +.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc +.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd +.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce +.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf +.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 +.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 +.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 +.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 +.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 +.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 +.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 +.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 +.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 +.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 +.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da +.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db +.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc +.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd +.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de +.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df +.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea +.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec +.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 +.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 +.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 +.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 +.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 +.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 +.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 +.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 +.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 +.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 +.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a +.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b +.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c +.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d +.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e +.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f +.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 +.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 +.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 +.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 +.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 +.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 +.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 +.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 +.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 +.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 +.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a +.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b +.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c +.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d +.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e +.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f +.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 +.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 +.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 +.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 +.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 +.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a +.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c +.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 +.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 +.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 +.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 +.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 +.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 +.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 +.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 +.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 +.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 +.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca +.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb +.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc +.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd +.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce +.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf +.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 +.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 +.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 +.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 +.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 +.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 +.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 +.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 +.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 +.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 +.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da +.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db +.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc +.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd +.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de +.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df +.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea +.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec +.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 +.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 +.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 +.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 +.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 +.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 +.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 +.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 +.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 +.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 +.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a +.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b +.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c +.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d +.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e +.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f +.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 +.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 +.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 +.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 +.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 +.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 +.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 +.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 +.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 +.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 +.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a +.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b +.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c +.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d +.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e +.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f +.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca +.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb +.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc +.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd +.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace +.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf +.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada +.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb +.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc +.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add +.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade +.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf +.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea +.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec +.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 +.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 +.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 +.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 +.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 +.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 +.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a +.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b +.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c +.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d +.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e +.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 +.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 +.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 +.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 +.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 +.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 +.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a +.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b +.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c +.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d +.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e +.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 +.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 +.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 +.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 +.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 +.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 +.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 +.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 +.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 +.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 +.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 +.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 +.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 +.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 +.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYDEV_SFR_GPIO0, 0x40050180 +.set CYDEV_SFR_GPIRD0, 0x40050189 +.set CYDEV_SFR_GPIO0_SEL, 0x4005018a +.set CYDEV_SFR_GPIO1, 0x40050190 +.set CYDEV_SFR_GPIRD1, 0x40050191 +.set CYDEV_SFR_GPIO2, 0x40050198 +.set CYDEV_SFR_GPIRD2, 0x40050199 +.set CYDEV_SFR_GPIO2_SEL, 0x4005019a +.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 +.set CYDEV_SFR_GPIO3, 0x400501b0 +.set CYDEV_SFR_GPIRD3, 0x400501b1 +.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 +.set CYDEV_SFR_GPIO4, 0x400501c0 +.set CYDEV_SFR_GPIRD4, 0x400501c1 +.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 +.set CYDEV_SFR_GPIO5, 0x400501c8 +.set CYDEV_SFR_GPIRD5, 0x400501c9 +.set CYDEV_SFR_GPIO5_SEL, 0x400501ca +.set CYDEV_SFR_GPIO6, 0x400501d8 +.set CYDEV_SFR_GPIRD6, 0x400501d9 +.set CYDEV_SFR_GPIO6_SEL, 0x400501da +.set CYDEV_SFR_GPIO12, 0x400501e8 +.set CYDEV_SFR_GPIRD12, 0x400501e9 +.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 +.set CYDEV_SFR_GPIO15, 0x400501f8 +.set CYDEV_SFR_GPIRD15, 0x400501f9 +.set CYDEV_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYDEV_P3BA_Y_START, 0x40050300 +.set CYDEV_P3BA_YROLL, 0x40050301 +.set CYDEV_P3BA_YCFG, 0x40050302 +.set CYDEV_P3BA_X_START1, 0x40050303 +.set CYDEV_P3BA_X_START2, 0x40050304 +.set CYDEV_P3BA_XROLL1, 0x40050305 +.set CYDEV_P3BA_XROLL2, 0x40050306 +.set CYDEV_P3BA_XINC, 0x40050307 +.set CYDEV_P3BA_XCFG, 0x40050308 +.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 +.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a +.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b +.set CYDEV_P3BA_ABSADDR1, 0x4005030c +.set CYDEV_P3BA_ABSADDR2, 0x4005030d +.set CYDEV_P3BA_ABSADDR3, 0x4005030e +.set CYDEV_P3BA_ABSADDR4, 0x4005030f +.set CYDEV_P3BA_DATCFG1, 0x40050310 +.set CYDEV_P3BA_DATCFG2, 0x40050311 +.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 +.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 +.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 +.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 +.set CYDEV_P3BA_DATA_REG1, 0x40050318 +.set CYDEV_P3BA_DATA_REG2, 0x40050319 +.set CYDEV_P3BA_DATA_REG3, 0x4005031a +.set CYDEV_P3BA_DATA_REG4, 0x4005031b +.set CYDEV_P3BA_EXP_DATA1, 0x4005031c +.set CYDEV_P3BA_EXP_DATA2, 0x4005031d +.set CYDEV_P3BA_EXP_DATA3, 0x4005031e +.set CYDEV_P3BA_EXP_DATA4, 0x4005031f +.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYDEV_P3BA_BIST_EN, 0x40050324 +.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYDEV_P3BA_SEQCFG1, 0x40050326 +.set CYDEV_P3BA_SEQCFG2, 0x40050327 +.set CYDEV_P3BA_Y_CURR, 0x40050328 +.set CYDEV_P3BA_X_CURR1, 0x40050329 +.set CYDEV_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 +.set CYDEV_PANTHER_WAITPIPE, 0x40080004 +.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 +.set CYDEV_PANTHER_DBG_CFG, 0x4008000c +.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 +.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 +.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 +.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYDEV_ITM_TRACE_EN, 0xe0000e00 +.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 +.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYDEV_ITM_PID4, 0xe0000fd0 +.set CYDEV_ITM_PID5, 0xe0000fd4 +.set CYDEV_ITM_PID6, 0xe0000fd8 +.set CYDEV_ITM_PID7, 0xe0000fdc +.set CYDEV_ITM_PID0, 0xe0000fe0 +.set CYDEV_ITM_PID1, 0xe0000fe4 +.set CYDEV_ITM_PID2, 0xe0000fe8 +.set CYDEV_ITM_PID3, 0xe0000fec +.set CYDEV_ITM_CID0, 0xe0000ff0 +.set CYDEV_ITM_CID1, 0xe0000ff4 +.set CYDEV_ITM_CID2, 0xe0000ff8 +.set CYDEV_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYDEV_DWT_CTRL, 0xe0001000 +.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 +.set CYDEV_DWT_CPI_COUNT, 0xe0001008 +.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 +.set CYDEV_DWT_LSU_COUNT, 0xe0001014 +.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 +.set CYDEV_DWT_PC_SAMPLE, 0xe000101c +.set CYDEV_DWT_COMP_0, 0xe0001020 +.set CYDEV_DWT_MASK_0, 0xe0001024 +.set CYDEV_DWT_FUNCTION_0, 0xe0001028 +.set CYDEV_DWT_COMP_1, 0xe0001030 +.set CYDEV_DWT_MASK_1, 0xe0001034 +.set CYDEV_DWT_FUNCTION_1, 0xe0001038 +.set CYDEV_DWT_COMP_2, 0xe0001040 +.set CYDEV_DWT_MASK_2, 0xe0001044 +.set CYDEV_DWT_FUNCTION_2, 0xe0001048 +.set CYDEV_DWT_COMP_3, 0xe0001050 +.set CYDEV_DWT_MASK_3, 0xe0001054 +.set CYDEV_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYDEV_FPB_CTRL, 0xe0002000 +.set CYDEV_FPB_REMAP, 0xe0002004 +.set CYDEV_FPB_FP_COMP_0, 0xe0002008 +.set CYDEV_FPB_FP_COMP_1, 0xe000200c +.set CYDEV_FPB_FP_COMP_2, 0xe0002010 +.set CYDEV_FPB_FP_COMP_3, 0xe0002014 +.set CYDEV_FPB_FP_COMP_4, 0xe0002018 +.set CYDEV_FPB_FP_COMP_5, 0xe000201c +.set CYDEV_FPB_FP_COMP_6, 0xe0002020 +.set CYDEV_FPB_FP_COMP_7, 0xe0002024 +.set CYDEV_FPB_PID4, 0xe0002fd0 +.set CYDEV_FPB_PID5, 0xe0002fd4 +.set CYDEV_FPB_PID6, 0xe0002fd8 +.set CYDEV_FPB_PID7, 0xe0002fdc +.set CYDEV_FPB_PID0, 0xe0002fe0 +.set CYDEV_FPB_PID1, 0xe0002fe4 +.set CYDEV_FPB_PID2, 0xe0002fe8 +.set CYDEV_FPB_PID3, 0xe0002fec +.set CYDEV_FPB_CID0, 0xe0002ff0 +.set CYDEV_FPB_CID1, 0xe0002ff4 +.set CYDEV_FPB_CID2, 0xe0002ff8 +.set CYDEV_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYDEV_NVIC_SETENA0, 0xe000e100 +.set CYDEV_NVIC_CLRENA0, 0xe000e180 +.set CYDEV_NVIC_SETPEND0, 0xe000e200 +.set CYDEV_NVIC_CLRPEND0, 0xe000e280 +.set CYDEV_NVIC_ACTIVE0, 0xe000e300 +.set CYDEV_NVIC_PRI_0, 0xe000e400 +.set CYDEV_NVIC_PRI_1, 0xe000e401 +.set CYDEV_NVIC_PRI_2, 0xe000e402 +.set CYDEV_NVIC_PRI_3, 0xe000e403 +.set CYDEV_NVIC_PRI_4, 0xe000e404 +.set CYDEV_NVIC_PRI_5, 0xe000e405 +.set CYDEV_NVIC_PRI_6, 0xe000e406 +.set CYDEV_NVIC_PRI_7, 0xe000e407 +.set CYDEV_NVIC_PRI_8, 0xe000e408 +.set CYDEV_NVIC_PRI_9, 0xe000e409 +.set CYDEV_NVIC_PRI_10, 0xe000e40a +.set CYDEV_NVIC_PRI_11, 0xe000e40b +.set CYDEV_NVIC_PRI_12, 0xe000e40c +.set CYDEV_NVIC_PRI_13, 0xe000e40d +.set CYDEV_NVIC_PRI_14, 0xe000e40e +.set CYDEV_NVIC_PRI_15, 0xe000e40f +.set CYDEV_NVIC_PRI_16, 0xe000e410 +.set CYDEV_NVIC_PRI_17, 0xe000e411 +.set CYDEV_NVIC_PRI_18, 0xe000e412 +.set CYDEV_NVIC_PRI_19, 0xe000e413 +.set CYDEV_NVIC_PRI_20, 0xe000e414 +.set CYDEV_NVIC_PRI_21, 0xe000e415 +.set CYDEV_NVIC_PRI_22, 0xe000e416 +.set CYDEV_NVIC_PRI_23, 0xe000e417 +.set CYDEV_NVIC_PRI_24, 0xe000e418 +.set CYDEV_NVIC_PRI_25, 0xe000e419 +.set CYDEV_NVIC_PRI_26, 0xe000e41a +.set CYDEV_NVIC_PRI_27, 0xe000e41b +.set CYDEV_NVIC_PRI_28, 0xe000e41c +.set CYDEV_NVIC_PRI_29, 0xe000e41d +.set CYDEV_NVIC_PRI_30, 0xe000e41e +.set CYDEV_NVIC_PRI_31, 0xe000e41f +.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 +.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c +.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 +.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 +.set CYDEV_TPIU_ITETMDATA, 0xe0040eec +.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYDEV_TPIU_ITITMDATA, 0xe0040efc +.set CYDEV_TPIU_ITCTRL, 0xe0040f00 +.set CYDEV_TPIU_DEVID, 0xe0040fc8 +.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc +.set CYDEV_TPIU_PID4, 0xe0040fd0 +.set CYDEV_TPIU_PID5, 0xe0040fd4 +.set CYDEV_TPIU_PID6, 0xe0040fd8 +.set CYDEV_TPIU_PID7, 0xe0040fdc +.set CYDEV_TPIU_PID0, 0xe0040fe0 +.set CYDEV_TPIU_PID1, 0xe0040fe4 +.set CYDEV_TPIU_PID2, 0xe0040fe8 +.set CYDEV_TPIU_PID3, 0xe0040fec +.set CYDEV_TPIU_CID0, 0xe0040ff0 +.set CYDEV_TPIU_CID1, 0xe0040ff4 +.set CYDEV_TPIU_CID2, 0xe0040ff8 +.set CYDEV_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYDEV_ETM_CTL, 0xe0041000 +.set CYDEV_ETM_CFG_CODE, 0xe0041004 +.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 +.set CYDEV_ETM_STATUS, 0xe0041010 +.set CYDEV_ETM_SYS_CFG, 0xe0041014 +.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 +.set CYDEV_ETM_ETM_ID, 0xe00411e4 +.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 +.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYDEV_ETM_PDSR, 0xe0041314 +.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 +.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 +.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 +.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc +.set CYDEV_ETM_PID4, 0xe0041fd0 +.set CYDEV_ETM_PID5, 0xe0041fd4 +.set CYDEV_ETM_PID6, 0xe0041fd8 +.set CYDEV_ETM_PID7, 0xe0041fdc +.set CYDEV_ETM_PID0, 0xe0041fe0 +.set CYDEV_ETM_PID1, 0xe0041fe4 +.set CYDEV_ETM_PID2, 0xe0041fe8 +.set CYDEV_ETM_PID3, 0xe0041fec +.set CYDEV_ETM_CID0, 0xe0041ff0 +.set CYDEV_ETM_CID1, 0xe0041ff4 +.set CYDEV_ETM_CID2, 0xe0041ff8 +.set CYDEV_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 +.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 +.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 +.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c +.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 +.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 +.set CYDEV_ROM_TABLE_END, 0xe00ff018 +.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 +.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 +.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 +.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc +.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 +.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 +.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 +.set CYDEV_ROM_TABLE_PID3, 0xe00fffec +.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 +.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 +.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 +.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc new file mode 100644 index 0000000..e2e2aa7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* File Name: cydevicegnu_trm.inc +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYREG_SRAM_CODE_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 +.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 +.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 +.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 +.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYREG_DMA_SRAM_MBASE, 0x2000f000 +.set CYREG_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYREG_CLKDIST_CR, 0x40004000 +.set CYREG_CLKDIST_LD, 0x40004001 +.set CYREG_CLKDIST_WRK0, 0x40004002 +.set CYREG_CLKDIST_WRK1, 0x40004003 +.set CYREG_CLKDIST_MSTR0, 0x40004004 +.set CYREG_CLKDIST_MSTR1, 0x40004005 +.set CYREG_CLKDIST_BCFG0, 0x40004006 +.set CYREG_CLKDIST_BCFG1, 0x40004007 +.set CYREG_CLKDIST_BCFG2, 0x40004008 +.set CYREG_CLKDIST_UCFG, 0x40004009 +.set CYREG_CLKDIST_DLY0, 0x4000400a +.set CYREG_CLKDIST_DLY1, 0x4000400b +.set CYREG_CLKDIST_DMASK, 0x40004010 +.set CYREG_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYREG_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 +.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 +.set CYREG_FASTCLK_PLL_P, 0x40004222 +.set CYREG_FASTCLK_PLL_Q, 0x40004223 +.set CYREG_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 +.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYREG_SLOWCLK_X32_CR, 0x40004308 +.set CYREG_SLOWCLK_X32_CFG, 0x40004309 +.set CYREG_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYREG_BOOST_CR0, 0x40004320 +.set CYREG_BOOST_CR1, 0x40004321 +.set CYREG_BOOST_CR2, 0x40004322 +.set CYREG_BOOST_CR3, 0x40004323 +.set CYREG_BOOST_SR, 0x40004324 +.set CYREG_BOOST_CR4, 0x40004325 +.set CYREG_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYREG_PWRSYS_CR0, 0x40004330 +.set CYREG_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYREG_PM_TW_CFG0, 0x40004380 +.set CYREG_PM_TW_CFG1, 0x40004381 +.set CYREG_PM_TW_CFG2, 0x40004382 +.set CYREG_PM_WDT_CFG, 0x40004383 +.set CYREG_PM_WDT_CR, 0x40004384 +.set CYREG_PM_INT_SR, 0x40004390 +.set CYREG_PM_MODE_CFG0, 0x40004391 +.set CYREG_PM_MODE_CFG1, 0x40004392 +.set CYREG_PM_MODE_CSR, 0x40004393 +.set CYREG_PM_USB_CR0, 0x40004394 +.set CYREG_PM_WAKEUP_CFG0, 0x40004398 +.set CYREG_PM_WAKEUP_CFG1, 0x40004399 +.set CYREG_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYREG_PM_ACT_CFG0, 0x400043a0 +.set CYREG_PM_ACT_CFG1, 0x400043a1 +.set CYREG_PM_ACT_CFG2, 0x400043a2 +.set CYREG_PM_ACT_CFG3, 0x400043a3 +.set CYREG_PM_ACT_CFG4, 0x400043a4 +.set CYREG_PM_ACT_CFG5, 0x400043a5 +.set CYREG_PM_ACT_CFG6, 0x400043a6 +.set CYREG_PM_ACT_CFG7, 0x400043a7 +.set CYREG_PM_ACT_CFG8, 0x400043a8 +.set CYREG_PM_ACT_CFG9, 0x400043a9 +.set CYREG_PM_ACT_CFG10, 0x400043aa +.set CYREG_PM_ACT_CFG11, 0x400043ab +.set CYREG_PM_ACT_CFG12, 0x400043ac +.set CYREG_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYREG_PM_STBY_CFG0, 0x400043b0 +.set CYREG_PM_STBY_CFG1, 0x400043b1 +.set CYREG_PM_STBY_CFG2, 0x400043b2 +.set CYREG_PM_STBY_CFG3, 0x400043b3 +.set CYREG_PM_STBY_CFG4, 0x400043b4 +.set CYREG_PM_STBY_CFG5, 0x400043b5 +.set CYREG_PM_STBY_CFG6, 0x400043b6 +.set CYREG_PM_STBY_CFG7, 0x400043b7 +.set CYREG_PM_STBY_CFG8, 0x400043b8 +.set CYREG_PM_STBY_CFG9, 0x400043b9 +.set CYREG_PM_STBY_CFG10, 0x400043ba +.set CYREG_PM_STBY_CFG11, 0x400043bb +.set CYREG_PM_STBY_CFG12, 0x400043bc +.set CYREG_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYREG_PM_AVAIL_CR0, 0x400043c0 +.set CYREG_PM_AVAIL_CR1, 0x400043c1 +.set CYREG_PM_AVAIL_CR2, 0x400043c2 +.set CYREG_PM_AVAIL_CR3, 0x400043c3 +.set CYREG_PM_AVAIL_CR4, 0x400043c4 +.set CYREG_PM_AVAIL_CR5, 0x400043c5 +.set CYREG_PM_AVAIL_CR6, 0x400043c6 +.set CYREG_PM_AVAIL_SR0, 0x400043d0 +.set CYREG_PM_AVAIL_SR1, 0x400043d1 +.set CYREG_PM_AVAIL_SR2, 0x400043d2 +.set CYREG_PM_AVAIL_SR3, 0x400043d3 +.set CYREG_PM_AVAIL_SR4, 0x400043d4 +.set CYREG_PM_AVAIL_SR5, 0x400043d5 +.set CYREG_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYREG_PICU0_INTTYPE0, 0x40004500 +.set CYREG_PICU0_INTTYPE1, 0x40004501 +.set CYREG_PICU0_INTTYPE2, 0x40004502 +.set CYREG_PICU0_INTTYPE3, 0x40004503 +.set CYREG_PICU0_INTTYPE4, 0x40004504 +.set CYREG_PICU0_INTTYPE5, 0x40004505 +.set CYREG_PICU0_INTTYPE6, 0x40004506 +.set CYREG_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYREG_PICU1_INTTYPE0, 0x40004508 +.set CYREG_PICU1_INTTYPE1, 0x40004509 +.set CYREG_PICU1_INTTYPE2, 0x4000450a +.set CYREG_PICU1_INTTYPE3, 0x4000450b +.set CYREG_PICU1_INTTYPE4, 0x4000450c +.set CYREG_PICU1_INTTYPE5, 0x4000450d +.set CYREG_PICU1_INTTYPE6, 0x4000450e +.set CYREG_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYREG_PICU2_INTTYPE0, 0x40004510 +.set CYREG_PICU2_INTTYPE1, 0x40004511 +.set CYREG_PICU2_INTTYPE2, 0x40004512 +.set CYREG_PICU2_INTTYPE3, 0x40004513 +.set CYREG_PICU2_INTTYPE4, 0x40004514 +.set CYREG_PICU2_INTTYPE5, 0x40004515 +.set CYREG_PICU2_INTTYPE6, 0x40004516 +.set CYREG_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYREG_PICU3_INTTYPE0, 0x40004518 +.set CYREG_PICU3_INTTYPE1, 0x40004519 +.set CYREG_PICU3_INTTYPE2, 0x4000451a +.set CYREG_PICU3_INTTYPE3, 0x4000451b +.set CYREG_PICU3_INTTYPE4, 0x4000451c +.set CYREG_PICU3_INTTYPE5, 0x4000451d +.set CYREG_PICU3_INTTYPE6, 0x4000451e +.set CYREG_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYREG_PICU4_INTTYPE0, 0x40004520 +.set CYREG_PICU4_INTTYPE1, 0x40004521 +.set CYREG_PICU4_INTTYPE2, 0x40004522 +.set CYREG_PICU4_INTTYPE3, 0x40004523 +.set CYREG_PICU4_INTTYPE4, 0x40004524 +.set CYREG_PICU4_INTTYPE5, 0x40004525 +.set CYREG_PICU4_INTTYPE6, 0x40004526 +.set CYREG_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYREG_PICU5_INTTYPE0, 0x40004528 +.set CYREG_PICU5_INTTYPE1, 0x40004529 +.set CYREG_PICU5_INTTYPE2, 0x4000452a +.set CYREG_PICU5_INTTYPE3, 0x4000452b +.set CYREG_PICU5_INTTYPE4, 0x4000452c +.set CYREG_PICU5_INTTYPE5, 0x4000452d +.set CYREG_PICU5_INTTYPE6, 0x4000452e +.set CYREG_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYREG_PICU6_INTTYPE0, 0x40004530 +.set CYREG_PICU6_INTTYPE1, 0x40004531 +.set CYREG_PICU6_INTTYPE2, 0x40004532 +.set CYREG_PICU6_INTTYPE3, 0x40004533 +.set CYREG_PICU6_INTTYPE4, 0x40004534 +.set CYREG_PICU6_INTTYPE5, 0x40004535 +.set CYREG_PICU6_INTTYPE6, 0x40004536 +.set CYREG_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYREG_PICU12_INTTYPE0, 0x40004560 +.set CYREG_PICU12_INTTYPE1, 0x40004561 +.set CYREG_PICU12_INTTYPE2, 0x40004562 +.set CYREG_PICU12_INTTYPE3, 0x40004563 +.set CYREG_PICU12_INTTYPE4, 0x40004564 +.set CYREG_PICU12_INTTYPE5, 0x40004565 +.set CYREG_PICU12_INTTYPE6, 0x40004566 +.set CYREG_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYREG_PICU15_INTTYPE0, 0x40004578 +.set CYREG_PICU15_INTTYPE1, 0x40004579 +.set CYREG_PICU15_INTTYPE2, 0x4000457a +.set CYREG_PICU15_INTTYPE3, 0x4000457b +.set CYREG_PICU15_INTTYPE4, 0x4000457c +.set CYREG_PICU15_INTTYPE5, 0x4000457d +.set CYREG_PICU15_INTTYPE6, 0x4000457e +.set CYREG_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYREG_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYREG_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYREG_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYREG_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYREG_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_TR0, 0x40004620 +.set CYREG_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_TR0, 0x40004622 +.set CYREG_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_TR0, 0x40004624 +.set CYREG_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_TR0, 0x40004626 +.set CYREG_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYREG_CMP0_TR0, 0x40004630 +.set CYREG_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYREG_CMP1_TR0, 0x40004632 +.set CYREG_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYREG_CMP2_TR0, 0x40004634 +.set CYREG_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYREG_CMP3_TR0, 0x40004636 +.set CYREG_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYREG_PWRSYS_HIB_TR0, 0x40004680 +.set CYREG_PWRSYS_HIB_TR1, 0x40004681 +.set CYREG_PWRSYS_I2C_TR, 0x40004682 +.set CYREG_PWRSYS_SLP_TR, 0x40004683 +.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYREG_PWRSYS_BREF_TR, 0x40004687 +.set CYREG_PWRSYS_BG_TR, 0x40004688 +.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYREG_ILO_TR0, 0x40004690 +.set CYREG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYREG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYREG_IMO_TR0, 0x400046a0 +.set CYREG_IMO_TR1, 0x400046a1 +.set CYREG_IMO_GAIN, 0x400046a2 +.set CYREG_IMO_C36M, 0x400046a3 +.set CYREG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYREG_XMHZ_TR, 0x400046a8 +.set CYREG_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYREG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYREG_MLOGIC_SEG_CR, 0x400046e4 +.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYREG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYREG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYREG_RESET_IPOR_CR0, 0x400046f0 +.set CYREG_RESET_IPOR_CR1, 0x400046f1 +.set CYREG_RESET_IPOR_CR2, 0x400046f2 +.set CYREG_RESET_IPOR_CR3, 0x400046f3 +.set CYREG_RESET_CR0, 0x400046f4 +.set CYREG_RESET_CR1, 0x400046f5 +.set CYREG_RESET_CR2, 0x400046f6 +.set CYREG_RESET_CR3, 0x400046f7 +.set CYREG_RESET_CR4, 0x400046f8 +.set CYREG_RESET_CR5, 0x400046f9 +.set CYREG_RESET_SR0, 0x400046fa +.set CYREG_RESET_SR1, 0x400046fb +.set CYREG_RESET_SR2, 0x400046fc +.set CYREG_RESET_SR3, 0x400046fd +.set CYREG_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYREG_SPC_FM_EE_CR, 0x40004700 +.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYREG_SPC_EE_SCR, 0x40004702 +.set CYREG_SPC_EE_ERR, 0x40004703 +.set CYREG_SPC_CPU_DATA, 0x40004720 +.set CYREG_SPC_DMA_DATA, 0x40004721 +.set CYREG_SPC_SR, 0x40004722 +.set CYREG_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYREG_CACHE_CC_CTL, 0x40004800 +.set CYREG_CACHE_ECC_CORR, 0x40004880 +.set CYREG_CACHE_ECC_ERR, 0x40004888 +.set CYREG_CACHE_FLASH_ERR, 0x40004890 +.set CYREG_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYREG_I2C_XCFG, 0x400049c8 +.set CYREG_I2C_ADR, 0x400049ca +.set CYREG_I2C_CFG, 0x400049d6 +.set CYREG_I2C_CSR, 0x400049d7 +.set CYREG_I2C_D, 0x400049d8 +.set CYREG_I2C_MCSR, 0x400049d9 +.set CYREG_I2C_CLK_DIV1, 0x400049db +.set CYREG_I2C_CLK_DIV2, 0x400049dc +.set CYREG_I2C_TMOUT_CSR, 0x400049dd +.set CYREG_I2C_TMOUT_SR, 0x400049de +.set CYREG_I2C_TMOUT_CFG0, 0x400049df +.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYREG_DEC_CR, 0x40004e00 +.set CYREG_DEC_SR, 0x40004e01 +.set CYREG_DEC_SHIFT1, 0x40004e02 +.set CYREG_DEC_SHIFT2, 0x40004e03 +.set CYREG_DEC_DR2, 0x40004e04 +.set CYREG_DEC_DR2H, 0x40004e05 +.set CYREG_DEC_DR1, 0x40004e06 +.set CYREG_DEC_OCOR, 0x40004e08 +.set CYREG_DEC_OCORM, 0x40004e09 +.set CYREG_DEC_OCORH, 0x40004e0a +.set CYREG_DEC_GCOR, 0x40004e0c +.set CYREG_DEC_GCORH, 0x40004e0d +.set CYREG_DEC_GVAL, 0x40004e0e +.set CYREG_DEC_OUTSAMP, 0x40004e10 +.set CYREG_DEC_OUTSAMPM, 0x40004e11 +.set CYREG_DEC_OUTSAMPH, 0x40004e12 +.set CYREG_DEC_OUTSAMPS, 0x40004e13 +.set CYREG_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYREG_TMR0_CFG0, 0x40004f00 +.set CYREG_TMR0_CFG1, 0x40004f01 +.set CYREG_TMR0_CFG2, 0x40004f02 +.set CYREG_TMR0_SR0, 0x40004f03 +.set CYREG_TMR0_PER0, 0x40004f04 +.set CYREG_TMR0_PER1, 0x40004f05 +.set CYREG_TMR0_CNT_CMP0, 0x40004f06 +.set CYREG_TMR0_CNT_CMP1, 0x40004f07 +.set CYREG_TMR0_CAP0, 0x40004f08 +.set CYREG_TMR0_CAP1, 0x40004f09 +.set CYREG_TMR0_RT0, 0x40004f0a +.set CYREG_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYREG_TMR1_CFG0, 0x40004f0c +.set CYREG_TMR1_CFG1, 0x40004f0d +.set CYREG_TMR1_CFG2, 0x40004f0e +.set CYREG_TMR1_SR0, 0x40004f0f +.set CYREG_TMR1_PER0, 0x40004f10 +.set CYREG_TMR1_PER1, 0x40004f11 +.set CYREG_TMR1_CNT_CMP0, 0x40004f12 +.set CYREG_TMR1_CNT_CMP1, 0x40004f13 +.set CYREG_TMR1_CAP0, 0x40004f14 +.set CYREG_TMR1_CAP1, 0x40004f15 +.set CYREG_TMR1_RT0, 0x40004f16 +.set CYREG_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYREG_TMR2_CFG0, 0x40004f18 +.set CYREG_TMR2_CFG1, 0x40004f19 +.set CYREG_TMR2_CFG2, 0x40004f1a +.set CYREG_TMR2_SR0, 0x40004f1b +.set CYREG_TMR2_PER0, 0x40004f1c +.set CYREG_TMR2_PER1, 0x40004f1d +.set CYREG_TMR2_CNT_CMP0, 0x40004f1e +.set CYREG_TMR2_CNT_CMP1, 0x40004f1f +.set CYREG_TMR2_CAP0, 0x40004f20 +.set CYREG_TMR2_CAP1, 0x40004f21 +.set CYREG_TMR2_RT0, 0x40004f22 +.set CYREG_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYREG_TMR3_CFG0, 0x40004f24 +.set CYREG_TMR3_CFG1, 0x40004f25 +.set CYREG_TMR3_CFG2, 0x40004f26 +.set CYREG_TMR3_SR0, 0x40004f27 +.set CYREG_TMR3_PER0, 0x40004f28 +.set CYREG_TMR3_PER1, 0x40004f29 +.set CYREG_TMR3_CNT_CMP0, 0x40004f2a +.set CYREG_TMR3_CNT_CMP1, 0x40004f2b +.set CYREG_TMR3_CAP0, 0x40004f2c +.set CYREG_TMR3_CAP1, 0x40004f2d +.set CYREG_TMR3_RT0, 0x40004f2e +.set CYREG_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYREG_PRT0_PC0, 0x40005000 +.set CYREG_PRT0_PC1, 0x40005001 +.set CYREG_PRT0_PC2, 0x40005002 +.set CYREG_PRT0_PC3, 0x40005003 +.set CYREG_PRT0_PC4, 0x40005004 +.set CYREG_PRT0_PC5, 0x40005005 +.set CYREG_PRT0_PC6, 0x40005006 +.set CYREG_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYREG_PRT1_PC0, 0x40005008 +.set CYREG_PRT1_PC1, 0x40005009 +.set CYREG_PRT1_PC2, 0x4000500a +.set CYREG_PRT1_PC3, 0x4000500b +.set CYREG_PRT1_PC4, 0x4000500c +.set CYREG_PRT1_PC5, 0x4000500d +.set CYREG_PRT1_PC6, 0x4000500e +.set CYREG_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYREG_PRT2_PC0, 0x40005010 +.set CYREG_PRT2_PC1, 0x40005011 +.set CYREG_PRT2_PC2, 0x40005012 +.set CYREG_PRT2_PC3, 0x40005013 +.set CYREG_PRT2_PC4, 0x40005014 +.set CYREG_PRT2_PC5, 0x40005015 +.set CYREG_PRT2_PC6, 0x40005016 +.set CYREG_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYREG_PRT3_PC0, 0x40005018 +.set CYREG_PRT3_PC1, 0x40005019 +.set CYREG_PRT3_PC2, 0x4000501a +.set CYREG_PRT3_PC3, 0x4000501b +.set CYREG_PRT3_PC4, 0x4000501c +.set CYREG_PRT3_PC5, 0x4000501d +.set CYREG_PRT3_PC6, 0x4000501e +.set CYREG_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYREG_PRT4_PC0, 0x40005020 +.set CYREG_PRT4_PC1, 0x40005021 +.set CYREG_PRT4_PC2, 0x40005022 +.set CYREG_PRT4_PC3, 0x40005023 +.set CYREG_PRT4_PC4, 0x40005024 +.set CYREG_PRT4_PC5, 0x40005025 +.set CYREG_PRT4_PC6, 0x40005026 +.set CYREG_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYREG_PRT5_PC0, 0x40005028 +.set CYREG_PRT5_PC1, 0x40005029 +.set CYREG_PRT5_PC2, 0x4000502a +.set CYREG_PRT5_PC3, 0x4000502b +.set CYREG_PRT5_PC4, 0x4000502c +.set CYREG_PRT5_PC5, 0x4000502d +.set CYREG_PRT5_PC6, 0x4000502e +.set CYREG_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYREG_PRT6_PC0, 0x40005030 +.set CYREG_PRT6_PC1, 0x40005031 +.set CYREG_PRT6_PC2, 0x40005032 +.set CYREG_PRT6_PC3, 0x40005033 +.set CYREG_PRT6_PC4, 0x40005034 +.set CYREG_PRT6_PC5, 0x40005035 +.set CYREG_PRT6_PC6, 0x40005036 +.set CYREG_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYREG_PRT12_PC0, 0x40005060 +.set CYREG_PRT12_PC1, 0x40005061 +.set CYREG_PRT12_PC2, 0x40005062 +.set CYREG_PRT12_PC3, 0x40005063 +.set CYREG_PRT12_PC4, 0x40005064 +.set CYREG_PRT12_PC5, 0x40005065 +.set CYREG_PRT12_PC6, 0x40005066 +.set CYREG_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYREG_IO_PC_PRT15_PC0, 0x40005078 +.set CYREG_IO_PC_PRT15_PC1, 0x40005079 +.set CYREG_IO_PC_PRT15_PC2, 0x4000507a +.set CYREG_IO_PC_PRT15_PC3, 0x4000507b +.set CYREG_IO_PC_PRT15_PC4, 0x4000507c +.set CYREG_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYREG_PRT0_DR, 0x40005100 +.set CYREG_PRT0_PS, 0x40005101 +.set CYREG_PRT0_DM0, 0x40005102 +.set CYREG_PRT0_DM1, 0x40005103 +.set CYREG_PRT0_DM2, 0x40005104 +.set CYREG_PRT0_SLW, 0x40005105 +.set CYREG_PRT0_BYP, 0x40005106 +.set CYREG_PRT0_BIE, 0x40005107 +.set CYREG_PRT0_INP_DIS, 0x40005108 +.set CYREG_PRT0_CTL, 0x40005109 +.set CYREG_PRT0_PRT, 0x4000510a +.set CYREG_PRT0_BIT_MASK, 0x4000510b +.set CYREG_PRT0_AMUX, 0x4000510c +.set CYREG_PRT0_AG, 0x4000510d +.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e +.set CYREG_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYREG_PRT1_DR, 0x40005110 +.set CYREG_PRT1_PS, 0x40005111 +.set CYREG_PRT1_DM0, 0x40005112 +.set CYREG_PRT1_DM1, 0x40005113 +.set CYREG_PRT1_DM2, 0x40005114 +.set CYREG_PRT1_SLW, 0x40005115 +.set CYREG_PRT1_BYP, 0x40005116 +.set CYREG_PRT1_BIE, 0x40005117 +.set CYREG_PRT1_INP_DIS, 0x40005118 +.set CYREG_PRT1_CTL, 0x40005119 +.set CYREG_PRT1_PRT, 0x4000511a +.set CYREG_PRT1_BIT_MASK, 0x4000511b +.set CYREG_PRT1_AMUX, 0x4000511c +.set CYREG_PRT1_AG, 0x4000511d +.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e +.set CYREG_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYREG_PRT2_DR, 0x40005120 +.set CYREG_PRT2_PS, 0x40005121 +.set CYREG_PRT2_DM0, 0x40005122 +.set CYREG_PRT2_DM1, 0x40005123 +.set CYREG_PRT2_DM2, 0x40005124 +.set CYREG_PRT2_SLW, 0x40005125 +.set CYREG_PRT2_BYP, 0x40005126 +.set CYREG_PRT2_BIE, 0x40005127 +.set CYREG_PRT2_INP_DIS, 0x40005128 +.set CYREG_PRT2_CTL, 0x40005129 +.set CYREG_PRT2_PRT, 0x4000512a +.set CYREG_PRT2_BIT_MASK, 0x4000512b +.set CYREG_PRT2_AMUX, 0x4000512c +.set CYREG_PRT2_AG, 0x4000512d +.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e +.set CYREG_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYREG_PRT3_DR, 0x40005130 +.set CYREG_PRT3_PS, 0x40005131 +.set CYREG_PRT3_DM0, 0x40005132 +.set CYREG_PRT3_DM1, 0x40005133 +.set CYREG_PRT3_DM2, 0x40005134 +.set CYREG_PRT3_SLW, 0x40005135 +.set CYREG_PRT3_BYP, 0x40005136 +.set CYREG_PRT3_BIE, 0x40005137 +.set CYREG_PRT3_INP_DIS, 0x40005138 +.set CYREG_PRT3_CTL, 0x40005139 +.set CYREG_PRT3_PRT, 0x4000513a +.set CYREG_PRT3_BIT_MASK, 0x4000513b +.set CYREG_PRT3_AMUX, 0x4000513c +.set CYREG_PRT3_AG, 0x4000513d +.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e +.set CYREG_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYREG_PRT4_DR, 0x40005140 +.set CYREG_PRT4_PS, 0x40005141 +.set CYREG_PRT4_DM0, 0x40005142 +.set CYREG_PRT4_DM1, 0x40005143 +.set CYREG_PRT4_DM2, 0x40005144 +.set CYREG_PRT4_SLW, 0x40005145 +.set CYREG_PRT4_BYP, 0x40005146 +.set CYREG_PRT4_BIE, 0x40005147 +.set CYREG_PRT4_INP_DIS, 0x40005148 +.set CYREG_PRT4_CTL, 0x40005149 +.set CYREG_PRT4_PRT, 0x4000514a +.set CYREG_PRT4_BIT_MASK, 0x4000514b +.set CYREG_PRT4_AMUX, 0x4000514c +.set CYREG_PRT4_AG, 0x4000514d +.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e +.set CYREG_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYREG_PRT5_DR, 0x40005150 +.set CYREG_PRT5_PS, 0x40005151 +.set CYREG_PRT5_DM0, 0x40005152 +.set CYREG_PRT5_DM1, 0x40005153 +.set CYREG_PRT5_DM2, 0x40005154 +.set CYREG_PRT5_SLW, 0x40005155 +.set CYREG_PRT5_BYP, 0x40005156 +.set CYREG_PRT5_BIE, 0x40005157 +.set CYREG_PRT5_INP_DIS, 0x40005158 +.set CYREG_PRT5_CTL, 0x40005159 +.set CYREG_PRT5_PRT, 0x4000515a +.set CYREG_PRT5_BIT_MASK, 0x4000515b +.set CYREG_PRT5_AMUX, 0x4000515c +.set CYREG_PRT5_AG, 0x4000515d +.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e +.set CYREG_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYREG_PRT6_DR, 0x40005160 +.set CYREG_PRT6_PS, 0x40005161 +.set CYREG_PRT6_DM0, 0x40005162 +.set CYREG_PRT6_DM1, 0x40005163 +.set CYREG_PRT6_DM2, 0x40005164 +.set CYREG_PRT6_SLW, 0x40005165 +.set CYREG_PRT6_BYP, 0x40005166 +.set CYREG_PRT6_BIE, 0x40005167 +.set CYREG_PRT6_INP_DIS, 0x40005168 +.set CYREG_PRT6_CTL, 0x40005169 +.set CYREG_PRT6_PRT, 0x4000516a +.set CYREG_PRT6_BIT_MASK, 0x4000516b +.set CYREG_PRT6_AMUX, 0x4000516c +.set CYREG_PRT6_AG, 0x4000516d +.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e +.set CYREG_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYREG_PRT12_DR, 0x400051c0 +.set CYREG_PRT12_PS, 0x400051c1 +.set CYREG_PRT12_DM0, 0x400051c2 +.set CYREG_PRT12_DM1, 0x400051c3 +.set CYREG_PRT12_DM2, 0x400051c4 +.set CYREG_PRT12_SLW, 0x400051c5 +.set CYREG_PRT12_BYP, 0x400051c6 +.set CYREG_PRT12_BIE, 0x400051c7 +.set CYREG_PRT12_INP_DIS, 0x400051c8 +.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYREG_PRT12_PRT, 0x400051ca +.set CYREG_PRT12_BIT_MASK, 0x400051cb +.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYREG_PRT12_AG, 0x400051cd +.set CYREG_PRT12_SIO_CFG, 0x400051ce +.set CYREG_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYREG_PRT15_DR, 0x400051f0 +.set CYREG_PRT15_PS, 0x400051f1 +.set CYREG_PRT15_DM0, 0x400051f2 +.set CYREG_PRT15_DM1, 0x400051f3 +.set CYREG_PRT15_DM2, 0x400051f4 +.set CYREG_PRT15_SLW, 0x400051f5 +.set CYREG_PRT15_BYP, 0x400051f6 +.set CYREG_PRT15_BIE, 0x400051f7 +.set CYREG_PRT15_INP_DIS, 0x400051f8 +.set CYREG_PRT15_CTL, 0x400051f9 +.set CYREG_PRT15_PRT, 0x400051fa +.set CYREG_PRT15_BIT_MASK, 0x400051fb +.set CYREG_PRT15_AMUX, 0x400051fc +.set CYREG_PRT15_AG, 0x400051fd +.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe +.set CYREG_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYREG_PRT0_OUT_SEL0, 0x40005200 +.set CYREG_PRT0_OUT_SEL1, 0x40005201 +.set CYREG_PRT0_OE_SEL0, 0x40005202 +.set CYREG_PRT0_OE_SEL1, 0x40005203 +.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYREG_PRT0_SYNC_OUT, 0x40005205 +.set CYREG_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYREG_PRT1_OUT_SEL0, 0x40005208 +.set CYREG_PRT1_OUT_SEL1, 0x40005209 +.set CYREG_PRT1_OE_SEL0, 0x4000520a +.set CYREG_PRT1_OE_SEL1, 0x4000520b +.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYREG_PRT1_SYNC_OUT, 0x4000520d +.set CYREG_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYREG_PRT2_OUT_SEL0, 0x40005210 +.set CYREG_PRT2_OUT_SEL1, 0x40005211 +.set CYREG_PRT2_OE_SEL0, 0x40005212 +.set CYREG_PRT2_OE_SEL1, 0x40005213 +.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYREG_PRT2_SYNC_OUT, 0x40005215 +.set CYREG_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYREG_PRT3_OUT_SEL0, 0x40005218 +.set CYREG_PRT3_OUT_SEL1, 0x40005219 +.set CYREG_PRT3_OE_SEL0, 0x4000521a +.set CYREG_PRT3_OE_SEL1, 0x4000521b +.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYREG_PRT3_SYNC_OUT, 0x4000521d +.set CYREG_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYREG_PRT4_OUT_SEL0, 0x40005220 +.set CYREG_PRT4_OUT_SEL1, 0x40005221 +.set CYREG_PRT4_OE_SEL0, 0x40005222 +.set CYREG_PRT4_OE_SEL1, 0x40005223 +.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYREG_PRT4_SYNC_OUT, 0x40005225 +.set CYREG_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYREG_PRT5_OUT_SEL0, 0x40005228 +.set CYREG_PRT5_OUT_SEL1, 0x40005229 +.set CYREG_PRT5_OE_SEL0, 0x4000522a +.set CYREG_PRT5_OE_SEL1, 0x4000522b +.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYREG_PRT5_SYNC_OUT, 0x4000522d +.set CYREG_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYREG_PRT6_OUT_SEL0, 0x40005230 +.set CYREG_PRT6_OUT_SEL1, 0x40005231 +.set CYREG_PRT6_OE_SEL0, 0x40005232 +.set CYREG_PRT6_OE_SEL1, 0x40005233 +.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYREG_PRT6_SYNC_OUT, 0x40005235 +.set CYREG_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYREG_PRT12_OUT_SEL0, 0x40005260 +.set CYREG_PRT12_OUT_SEL1, 0x40005261 +.set CYREG_PRT12_OE_SEL0, 0x40005262 +.set CYREG_PRT12_OE_SEL1, 0x40005263 +.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYREG_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYREG_PRT15_OUT_SEL0, 0x40005278 +.set CYREG_PRT15_OUT_SEL1, 0x40005279 +.set CYREG_PRT15_OE_SEL0, 0x4000527a +.set CYREG_PRT15_OE_SEL1, 0x4000527b +.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYREG_PRT15_SYNC_OUT, 0x4000527d +.set CYREG_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYREG_EMIF_NO_UDB, 0x40005400 +.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYREG_EMIF_MEM_DWN, 0x40005402 +.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 +.set CYREG_EMIF_CLOCK_EN, 0x40005404 +.set CYREG_EMIF_EM_TYPE, 0x40005405 +.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYREG_SC0_CR0, 0x40005800 +.set CYREG_SC0_CR1, 0x40005801 +.set CYREG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYREG_SC1_CR0, 0x40005804 +.set CYREG_SC1_CR1, 0x40005805 +.set CYREG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYREG_SC2_CR0, 0x40005808 +.set CYREG_SC2_CR1, 0x40005809 +.set CYREG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYREG_SC3_CR0, 0x4000580c +.set CYREG_SC3_CR1, 0x4000580d +.set CYREG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYREG_DAC0_CR0, 0x40005820 +.set CYREG_DAC0_CR1, 0x40005821 +.set CYREG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYREG_DAC1_CR0, 0x40005824 +.set CYREG_DAC1_CR1, 0x40005825 +.set CYREG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYREG_DAC2_CR0, 0x40005828 +.set CYREG_DAC2_CR1, 0x40005829 +.set CYREG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYREG_DAC3_CR0, 0x4000582c +.set CYREG_DAC3_CR1, 0x4000582d +.set CYREG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYREG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYREG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYREG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYREG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYREG_LUT0_CR, 0x40005848 +.set CYREG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYREG_LUT1_CR, 0x4000584a +.set CYREG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYREG_LUT2_CR, 0x4000584c +.set CYREG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYREG_LUT3_CR, 0x4000584e +.set CYREG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_CR, 0x40005858 +.set CYREG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_CR, 0x4000585a +.set CYREG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_CR, 0x4000585c +.set CYREG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_CR, 0x4000585e +.set CYREG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYREG_LCDDAC_CR0, 0x40005868 +.set CYREG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYREG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYREG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYREG_BG_CR0, 0x4000586c +.set CYREG_BG_RSVD, 0x4000586d +.set CYREG_BG_DFT0, 0x4000586e +.set CYREG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYREG_CAPSL_CFG0, 0x40005870 +.set CYREG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYREG_CAPSR_CFG0, 0x40005872 +.set CYREG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYREG_PUMP_CR0, 0x40005876 +.set CYREG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYREG_LPF0_CR0, 0x40005878 +.set CYREG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYREG_LPF1_CR0, 0x4000587a +.set CYREG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYREG_DSM0_CR0, 0x40005880 +.set CYREG_DSM0_CR1, 0x40005881 +.set CYREG_DSM0_CR2, 0x40005882 +.set CYREG_DSM0_CR3, 0x40005883 +.set CYREG_DSM0_CR4, 0x40005884 +.set CYREG_DSM0_CR5, 0x40005885 +.set CYREG_DSM0_CR6, 0x40005886 +.set CYREG_DSM0_CR7, 0x40005887 +.set CYREG_DSM0_CR8, 0x40005888 +.set CYREG_DSM0_CR9, 0x40005889 +.set CYREG_DSM0_CR10, 0x4000588a +.set CYREG_DSM0_CR11, 0x4000588b +.set CYREG_DSM0_CR12, 0x4000588c +.set CYREG_DSM0_CR13, 0x4000588d +.set CYREG_DSM0_CR14, 0x4000588e +.set CYREG_DSM0_CR15, 0x4000588f +.set CYREG_DSM0_CR16, 0x40005890 +.set CYREG_DSM0_CR17, 0x40005891 +.set CYREG_DSM0_REF0, 0x40005892 +.set CYREG_DSM0_REF1, 0x40005893 +.set CYREG_DSM0_REF2, 0x40005894 +.set CYREG_DSM0_REF3, 0x40005895 +.set CYREG_DSM0_DEM0, 0x40005896 +.set CYREG_DSM0_DEM1, 0x40005897 +.set CYREG_DSM0_TST0, 0x40005898 +.set CYREG_DSM0_TST1, 0x40005899 +.set CYREG_DSM0_BUF0, 0x4000589a +.set CYREG_DSM0_BUF1, 0x4000589b +.set CYREG_DSM0_BUF2, 0x4000589c +.set CYREG_DSM0_BUF3, 0x4000589d +.set CYREG_DSM0_MISC, 0x4000589e +.set CYREG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYREG_SAR0_CSR0, 0x40005900 +.set CYREG_SAR0_CSR1, 0x40005901 +.set CYREG_SAR0_CSR2, 0x40005902 +.set CYREG_SAR0_CSR3, 0x40005903 +.set CYREG_SAR0_CSR4, 0x40005904 +.set CYREG_SAR0_CSR5, 0x40005905 +.set CYREG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYREG_SAR1_CSR0, 0x40005908 +.set CYREG_SAR1_CSR1, 0x40005909 +.set CYREG_SAR1_CSR2, 0x4000590a +.set CYREG_SAR1_CSR3, 0x4000590b +.set CYREG_SAR1_CSR4, 0x4000590c +.set CYREG_SAR1_CSR5, 0x4000590d +.set CYREG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYREG_SC0_SW0, 0x40005a00 +.set CYREG_SC0_SW2, 0x40005a02 +.set CYREG_SC0_SW3, 0x40005a03 +.set CYREG_SC0_SW4, 0x40005a04 +.set CYREG_SC0_SW6, 0x40005a06 +.set CYREG_SC0_SW7, 0x40005a07 +.set CYREG_SC0_SW8, 0x40005a08 +.set CYREG_SC0_SW10, 0x40005a0a +.set CYREG_SC0_CLK, 0x40005a0b +.set CYREG_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYREG_SC1_SW0, 0x40005a10 +.set CYREG_SC1_SW2, 0x40005a12 +.set CYREG_SC1_SW3, 0x40005a13 +.set CYREG_SC1_SW4, 0x40005a14 +.set CYREG_SC1_SW6, 0x40005a16 +.set CYREG_SC1_SW7, 0x40005a17 +.set CYREG_SC1_SW8, 0x40005a18 +.set CYREG_SC1_SW10, 0x40005a1a +.set CYREG_SC1_CLK, 0x40005a1b +.set CYREG_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYREG_SC2_SW0, 0x40005a20 +.set CYREG_SC2_SW2, 0x40005a22 +.set CYREG_SC2_SW3, 0x40005a23 +.set CYREG_SC2_SW4, 0x40005a24 +.set CYREG_SC2_SW6, 0x40005a26 +.set CYREG_SC2_SW7, 0x40005a27 +.set CYREG_SC2_SW8, 0x40005a28 +.set CYREG_SC2_SW10, 0x40005a2a +.set CYREG_SC2_CLK, 0x40005a2b +.set CYREG_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYREG_SC3_SW0, 0x40005a30 +.set CYREG_SC3_SW2, 0x40005a32 +.set CYREG_SC3_SW3, 0x40005a33 +.set CYREG_SC3_SW4, 0x40005a34 +.set CYREG_SC3_SW6, 0x40005a36 +.set CYREG_SC3_SW7, 0x40005a37 +.set CYREG_SC3_SW8, 0x40005a38 +.set CYREG_SC3_SW10, 0x40005a3a +.set CYREG_SC3_CLK, 0x40005a3b +.set CYREG_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYREG_DAC0_SW0, 0x40005a80 +.set CYREG_DAC0_SW2, 0x40005a82 +.set CYREG_DAC0_SW3, 0x40005a83 +.set CYREG_DAC0_SW4, 0x40005a84 +.set CYREG_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYREG_DAC1_SW0, 0x40005a88 +.set CYREG_DAC1_SW2, 0x40005a8a +.set CYREG_DAC1_SW3, 0x40005a8b +.set CYREG_DAC1_SW4, 0x40005a8c +.set CYREG_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYREG_DAC2_SW0, 0x40005a90 +.set CYREG_DAC2_SW2, 0x40005a92 +.set CYREG_DAC2_SW3, 0x40005a93 +.set CYREG_DAC2_SW4, 0x40005a94 +.set CYREG_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYREG_DAC3_SW0, 0x40005a98 +.set CYREG_DAC3_SW2, 0x40005a9a +.set CYREG_DAC3_SW3, 0x40005a9b +.set CYREG_DAC3_SW4, 0x40005a9c +.set CYREG_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYREG_CMP0_SW0, 0x40005ac0 +.set CYREG_CMP0_SW2, 0x40005ac2 +.set CYREG_CMP0_SW3, 0x40005ac3 +.set CYREG_CMP0_SW4, 0x40005ac4 +.set CYREG_CMP0_SW6, 0x40005ac6 +.set CYREG_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYREG_CMP1_SW0, 0x40005ac8 +.set CYREG_CMP1_SW2, 0x40005aca +.set CYREG_CMP1_SW3, 0x40005acb +.set CYREG_CMP1_SW4, 0x40005acc +.set CYREG_CMP1_SW6, 0x40005ace +.set CYREG_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYREG_CMP2_SW0, 0x40005ad0 +.set CYREG_CMP2_SW2, 0x40005ad2 +.set CYREG_CMP2_SW3, 0x40005ad3 +.set CYREG_CMP2_SW4, 0x40005ad4 +.set CYREG_CMP2_SW6, 0x40005ad6 +.set CYREG_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYREG_CMP3_SW0, 0x40005ad8 +.set CYREG_CMP3_SW2, 0x40005ada +.set CYREG_CMP3_SW3, 0x40005adb +.set CYREG_CMP3_SW4, 0x40005adc +.set CYREG_CMP3_SW6, 0x40005ade +.set CYREG_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYREG_DSM0_SW0, 0x40005b00 +.set CYREG_DSM0_SW2, 0x40005b02 +.set CYREG_DSM0_SW3, 0x40005b03 +.set CYREG_DSM0_SW4, 0x40005b04 +.set CYREG_DSM0_SW6, 0x40005b06 +.set CYREG_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYREG_SAR0_SW0, 0x40005b20 +.set CYREG_SAR0_SW2, 0x40005b22 +.set CYREG_SAR0_SW3, 0x40005b23 +.set CYREG_SAR0_SW4, 0x40005b24 +.set CYREG_SAR0_SW6, 0x40005b26 +.set CYREG_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYREG_SAR1_SW0, 0x40005b28 +.set CYREG_SAR1_SW2, 0x40005b2a +.set CYREG_SAR1_SW3, 0x40005b2b +.set CYREG_SAR1_SW4, 0x40005b2c +.set CYREG_SAR1_SW6, 0x40005b2e +.set CYREG_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_MX, 0x40005b40 +.set CYREG_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_MX, 0x40005b42 +.set CYREG_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_MX, 0x40005b44 +.set CYREG_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_MX, 0x40005b46 +.set CYREG_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYREG_LCDDAC_SW0, 0x40005b50 +.set CYREG_LCDDAC_SW1, 0x40005b51 +.set CYREG_LCDDAC_SW2, 0x40005b52 +.set CYREG_LCDDAC_SW3, 0x40005b53 +.set CYREG_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYREG_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYREG_BUS_SW0, 0x40005b58 +.set CYREG_BUS_SW2, 0x40005b5a +.set CYREG_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYREG_DFT_CR0, 0x40005b5c +.set CYREG_DFT_CR1, 0x40005b5d +.set CYREG_DFT_CR2, 0x40005b5e +.set CYREG_DFT_CR3, 0x40005b5f +.set CYREG_DFT_CR4, 0x40005b60 +.set CYREG_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYREG_DSM0_OUT0, 0x40005b88 +.set CYREG_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYREG_LUT_SR, 0x40005b90 +.set CYREG_LUT_WRK1, 0x40005b91 +.set CYREG_LUT_MSK, 0x40005b92 +.set CYREG_LUT_CLK, 0x40005b93 +.set CYREG_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYREG_CMP_WRK, 0x40005b96 +.set CYREG_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYREG_SC_SR, 0x40005b98 +.set CYREG_SC_WRK1, 0x40005b99 +.set CYREG_SC_MSK, 0x40005b9a +.set CYREG_SC_CMPINV, 0x40005b9b +.set CYREG_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYREG_SAR0_WRK0, 0x40005ba0 +.set CYREG_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYREG_SAR1_WRK0, 0x40005ba2 +.set CYREG_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYREG_USB_EP0_DR0, 0x40006000 +.set CYREG_USB_EP0_DR1, 0x40006001 +.set CYREG_USB_EP0_DR2, 0x40006002 +.set CYREG_USB_EP0_DR3, 0x40006003 +.set CYREG_USB_EP0_DR4, 0x40006004 +.set CYREG_USB_EP0_DR5, 0x40006005 +.set CYREG_USB_EP0_DR6, 0x40006006 +.set CYREG_USB_EP0_DR7, 0x40006007 +.set CYREG_USB_CR0, 0x40006008 +.set CYREG_USB_CR1, 0x40006009 +.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a +.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c +.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d +.set CYREG_USB_SIE_EP1_CR0, 0x4000600e +.set CYREG_USB_USBIO_CR0, 0x40006010 +.set CYREG_USB_USBIO_CR1, 0x40006012 +.set CYREG_USB_DYN_RECONFIG, 0x40006014 +.set CYREG_USB_SOF0, 0x40006018 +.set CYREG_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c +.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d +.set CYREG_USB_SIE_EP2_CR0, 0x4000601e +.set CYREG_USB_EP0_CR, 0x40006028 +.set CYREG_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c +.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d +.set CYREG_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c +.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d +.set CYREG_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c +.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d +.set CYREG_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c +.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d +.set CYREG_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c +.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d +.set CYREG_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c +.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d +.set CYREG_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP1_CFG, 0x40006080 +.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYREG_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW1_WA, 0x40006084 +.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYREG_USB_ARB_RW1_RA, 0x40006086 +.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYREG_USB_ARB_RW1_DR, 0x40006088 +.set CYREG_USB_BUF_SIZE, 0x4000608c +.set CYREG_USB_EP_ACTIVE, 0x4000608e +.set CYREG_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP2_CFG, 0x40006090 +.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYREG_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW2_WA, 0x40006094 +.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYREG_USB_ARB_RW2_RA, 0x40006096 +.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYREG_USB_ARB_RW2_DR, 0x40006098 +.set CYREG_USB_ARB_CFG, 0x4000609c +.set CYREG_USB_USB_CLK_EN, 0x4000609d +.set CYREG_USB_ARB_INT_EN, 0x4000609e +.set CYREG_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 +.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYREG_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW3_WA, 0x400060a4 +.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYREG_USB_ARB_RW3_RA, 0x400060a6 +.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYREG_USB_ARB_RW3_DR, 0x400060a8 +.set CYREG_USB_CWA, 0x400060ac +.set CYREG_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 +.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYREG_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW4_WA, 0x400060b4 +.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYREG_USB_ARB_RW4_RA, 0x400060b6 +.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYREG_USB_ARB_RW4_DR, 0x400060b8 +.set CYREG_USB_DMA_THRES, 0x400060bc +.set CYREG_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 +.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYREG_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW5_WA, 0x400060c4 +.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYREG_USB_ARB_RW5_RA, 0x400060c6 +.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYREG_USB_ARB_RW5_DR, 0x400060c8 +.set CYREG_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 +.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYREG_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW6_WA, 0x400060d4 +.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYREG_USB_ARB_RW6_RA, 0x400060d6 +.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYREG_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 +.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYREG_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW7_WA, 0x400060e4 +.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYREG_USB_ARB_RW7_RA, 0x400060e6 +.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYREG_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 +.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYREG_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW8_WA, 0x400060f4 +.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYREG_USB_ARB_RW8_RA, 0x400060f6 +.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYREG_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 +.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYREG_B0_UDB00_A0, 0x40006400 +.set CYREG_B0_UDB01_A0, 0x40006401 +.set CYREG_B0_UDB02_A0, 0x40006402 +.set CYREG_B0_UDB03_A0, 0x40006403 +.set CYREG_B0_UDB04_A0, 0x40006404 +.set CYREG_B0_UDB05_A0, 0x40006405 +.set CYREG_B0_UDB06_A0, 0x40006406 +.set CYREG_B0_UDB07_A0, 0x40006407 +.set CYREG_B0_UDB08_A0, 0x40006408 +.set CYREG_B0_UDB09_A0, 0x40006409 +.set CYREG_B0_UDB10_A0, 0x4000640a +.set CYREG_B0_UDB11_A0, 0x4000640b +.set CYREG_B0_UDB12_A0, 0x4000640c +.set CYREG_B0_UDB13_A0, 0x4000640d +.set CYREG_B0_UDB14_A0, 0x4000640e +.set CYREG_B0_UDB15_A0, 0x4000640f +.set CYREG_B0_UDB00_A1, 0x40006410 +.set CYREG_B0_UDB01_A1, 0x40006411 +.set CYREG_B0_UDB02_A1, 0x40006412 +.set CYREG_B0_UDB03_A1, 0x40006413 +.set CYREG_B0_UDB04_A1, 0x40006414 +.set CYREG_B0_UDB05_A1, 0x40006415 +.set CYREG_B0_UDB06_A1, 0x40006416 +.set CYREG_B0_UDB07_A1, 0x40006417 +.set CYREG_B0_UDB08_A1, 0x40006418 +.set CYREG_B0_UDB09_A1, 0x40006419 +.set CYREG_B0_UDB10_A1, 0x4000641a +.set CYREG_B0_UDB11_A1, 0x4000641b +.set CYREG_B0_UDB12_A1, 0x4000641c +.set CYREG_B0_UDB13_A1, 0x4000641d +.set CYREG_B0_UDB14_A1, 0x4000641e +.set CYREG_B0_UDB15_A1, 0x4000641f +.set CYREG_B0_UDB00_D0, 0x40006420 +.set CYREG_B0_UDB01_D0, 0x40006421 +.set CYREG_B0_UDB02_D0, 0x40006422 +.set CYREG_B0_UDB03_D0, 0x40006423 +.set CYREG_B0_UDB04_D0, 0x40006424 +.set CYREG_B0_UDB05_D0, 0x40006425 +.set CYREG_B0_UDB06_D0, 0x40006426 +.set CYREG_B0_UDB07_D0, 0x40006427 +.set CYREG_B0_UDB08_D0, 0x40006428 +.set CYREG_B0_UDB09_D0, 0x40006429 +.set CYREG_B0_UDB10_D0, 0x4000642a +.set CYREG_B0_UDB11_D0, 0x4000642b +.set CYREG_B0_UDB12_D0, 0x4000642c +.set CYREG_B0_UDB13_D0, 0x4000642d +.set CYREG_B0_UDB14_D0, 0x4000642e +.set CYREG_B0_UDB15_D0, 0x4000642f +.set CYREG_B0_UDB00_D1, 0x40006430 +.set CYREG_B0_UDB01_D1, 0x40006431 +.set CYREG_B0_UDB02_D1, 0x40006432 +.set CYREG_B0_UDB03_D1, 0x40006433 +.set CYREG_B0_UDB04_D1, 0x40006434 +.set CYREG_B0_UDB05_D1, 0x40006435 +.set CYREG_B0_UDB06_D1, 0x40006436 +.set CYREG_B0_UDB07_D1, 0x40006437 +.set CYREG_B0_UDB08_D1, 0x40006438 +.set CYREG_B0_UDB09_D1, 0x40006439 +.set CYREG_B0_UDB10_D1, 0x4000643a +.set CYREG_B0_UDB11_D1, 0x4000643b +.set CYREG_B0_UDB12_D1, 0x4000643c +.set CYREG_B0_UDB13_D1, 0x4000643d +.set CYREG_B0_UDB14_D1, 0x4000643e +.set CYREG_B0_UDB15_D1, 0x4000643f +.set CYREG_B0_UDB00_F0, 0x40006440 +.set CYREG_B0_UDB01_F0, 0x40006441 +.set CYREG_B0_UDB02_F0, 0x40006442 +.set CYREG_B0_UDB03_F0, 0x40006443 +.set CYREG_B0_UDB04_F0, 0x40006444 +.set CYREG_B0_UDB05_F0, 0x40006445 +.set CYREG_B0_UDB06_F0, 0x40006446 +.set CYREG_B0_UDB07_F0, 0x40006447 +.set CYREG_B0_UDB08_F0, 0x40006448 +.set CYREG_B0_UDB09_F0, 0x40006449 +.set CYREG_B0_UDB10_F0, 0x4000644a +.set CYREG_B0_UDB11_F0, 0x4000644b +.set CYREG_B0_UDB12_F0, 0x4000644c +.set CYREG_B0_UDB13_F0, 0x4000644d +.set CYREG_B0_UDB14_F0, 0x4000644e +.set CYREG_B0_UDB15_F0, 0x4000644f +.set CYREG_B0_UDB00_F1, 0x40006450 +.set CYREG_B0_UDB01_F1, 0x40006451 +.set CYREG_B0_UDB02_F1, 0x40006452 +.set CYREG_B0_UDB03_F1, 0x40006453 +.set CYREG_B0_UDB04_F1, 0x40006454 +.set CYREG_B0_UDB05_F1, 0x40006455 +.set CYREG_B0_UDB06_F1, 0x40006456 +.set CYREG_B0_UDB07_F1, 0x40006457 +.set CYREG_B0_UDB08_F1, 0x40006458 +.set CYREG_B0_UDB09_F1, 0x40006459 +.set CYREG_B0_UDB10_F1, 0x4000645a +.set CYREG_B0_UDB11_F1, 0x4000645b +.set CYREG_B0_UDB12_F1, 0x4000645c +.set CYREG_B0_UDB13_F1, 0x4000645d +.set CYREG_B0_UDB14_F1, 0x4000645e +.set CYREG_B0_UDB15_F1, 0x4000645f +.set CYREG_B0_UDB00_ST, 0x40006460 +.set CYREG_B0_UDB01_ST, 0x40006461 +.set CYREG_B0_UDB02_ST, 0x40006462 +.set CYREG_B0_UDB03_ST, 0x40006463 +.set CYREG_B0_UDB04_ST, 0x40006464 +.set CYREG_B0_UDB05_ST, 0x40006465 +.set CYREG_B0_UDB06_ST, 0x40006466 +.set CYREG_B0_UDB07_ST, 0x40006467 +.set CYREG_B0_UDB08_ST, 0x40006468 +.set CYREG_B0_UDB09_ST, 0x40006469 +.set CYREG_B0_UDB10_ST, 0x4000646a +.set CYREG_B0_UDB11_ST, 0x4000646b +.set CYREG_B0_UDB12_ST, 0x4000646c +.set CYREG_B0_UDB13_ST, 0x4000646d +.set CYREG_B0_UDB14_ST, 0x4000646e +.set CYREG_B0_UDB15_ST, 0x4000646f +.set CYREG_B0_UDB00_CTL, 0x40006470 +.set CYREG_B0_UDB01_CTL, 0x40006471 +.set CYREG_B0_UDB02_CTL, 0x40006472 +.set CYREG_B0_UDB03_CTL, 0x40006473 +.set CYREG_B0_UDB04_CTL, 0x40006474 +.set CYREG_B0_UDB05_CTL, 0x40006475 +.set CYREG_B0_UDB06_CTL, 0x40006476 +.set CYREG_B0_UDB07_CTL, 0x40006477 +.set CYREG_B0_UDB08_CTL, 0x40006478 +.set CYREG_B0_UDB09_CTL, 0x40006479 +.set CYREG_B0_UDB10_CTL, 0x4000647a +.set CYREG_B0_UDB11_CTL, 0x4000647b +.set CYREG_B0_UDB12_CTL, 0x4000647c +.set CYREG_B0_UDB13_CTL, 0x4000647d +.set CYREG_B0_UDB14_CTL, 0x4000647e +.set CYREG_B0_UDB15_CTL, 0x4000647f +.set CYREG_B0_UDB00_MSK, 0x40006480 +.set CYREG_B0_UDB01_MSK, 0x40006481 +.set CYREG_B0_UDB02_MSK, 0x40006482 +.set CYREG_B0_UDB03_MSK, 0x40006483 +.set CYREG_B0_UDB04_MSK, 0x40006484 +.set CYREG_B0_UDB05_MSK, 0x40006485 +.set CYREG_B0_UDB06_MSK, 0x40006486 +.set CYREG_B0_UDB07_MSK, 0x40006487 +.set CYREG_B0_UDB08_MSK, 0x40006488 +.set CYREG_B0_UDB09_MSK, 0x40006489 +.set CYREG_B0_UDB10_MSK, 0x4000648a +.set CYREG_B0_UDB11_MSK, 0x4000648b +.set CYREG_B0_UDB12_MSK, 0x4000648c +.set CYREG_B0_UDB13_MSK, 0x4000648d +.set CYREG_B0_UDB14_MSK, 0x4000648e +.set CYREG_B0_UDB15_MSK, 0x4000648f +.set CYREG_B0_UDB00_ACTL, 0x40006490 +.set CYREG_B0_UDB01_ACTL, 0x40006491 +.set CYREG_B0_UDB02_ACTL, 0x40006492 +.set CYREG_B0_UDB03_ACTL, 0x40006493 +.set CYREG_B0_UDB04_ACTL, 0x40006494 +.set CYREG_B0_UDB05_ACTL, 0x40006495 +.set CYREG_B0_UDB06_ACTL, 0x40006496 +.set CYREG_B0_UDB07_ACTL, 0x40006497 +.set CYREG_B0_UDB08_ACTL, 0x40006498 +.set CYREG_B0_UDB09_ACTL, 0x40006499 +.set CYREG_B0_UDB10_ACTL, 0x4000649a +.set CYREG_B0_UDB11_ACTL, 0x4000649b +.set CYREG_B0_UDB12_ACTL, 0x4000649c +.set CYREG_B0_UDB13_ACTL, 0x4000649d +.set CYREG_B0_UDB14_ACTL, 0x4000649e +.set CYREG_B0_UDB15_ACTL, 0x4000649f +.set CYREG_B0_UDB00_MC, 0x400064a0 +.set CYREG_B0_UDB01_MC, 0x400064a1 +.set CYREG_B0_UDB02_MC, 0x400064a2 +.set CYREG_B0_UDB03_MC, 0x400064a3 +.set CYREG_B0_UDB04_MC, 0x400064a4 +.set CYREG_B0_UDB05_MC, 0x400064a5 +.set CYREG_B0_UDB06_MC, 0x400064a6 +.set CYREG_B0_UDB07_MC, 0x400064a7 +.set CYREG_B0_UDB08_MC, 0x400064a8 +.set CYREG_B0_UDB09_MC, 0x400064a9 +.set CYREG_B0_UDB10_MC, 0x400064aa +.set CYREG_B0_UDB11_MC, 0x400064ab +.set CYREG_B0_UDB12_MC, 0x400064ac +.set CYREG_B0_UDB13_MC, 0x400064ad +.set CYREG_B0_UDB14_MC, 0x400064ae +.set CYREG_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYREG_B1_UDB04_A0, 0x40006504 +.set CYREG_B1_UDB05_A0, 0x40006505 +.set CYREG_B1_UDB06_A0, 0x40006506 +.set CYREG_B1_UDB07_A0, 0x40006507 +.set CYREG_B1_UDB08_A0, 0x40006508 +.set CYREG_B1_UDB09_A0, 0x40006509 +.set CYREG_B1_UDB10_A0, 0x4000650a +.set CYREG_B1_UDB11_A0, 0x4000650b +.set CYREG_B1_UDB04_A1, 0x40006514 +.set CYREG_B1_UDB05_A1, 0x40006515 +.set CYREG_B1_UDB06_A1, 0x40006516 +.set CYREG_B1_UDB07_A1, 0x40006517 +.set CYREG_B1_UDB08_A1, 0x40006518 +.set CYREG_B1_UDB09_A1, 0x40006519 +.set CYREG_B1_UDB10_A1, 0x4000651a +.set CYREG_B1_UDB11_A1, 0x4000651b +.set CYREG_B1_UDB04_D0, 0x40006524 +.set CYREG_B1_UDB05_D0, 0x40006525 +.set CYREG_B1_UDB06_D0, 0x40006526 +.set CYREG_B1_UDB07_D0, 0x40006527 +.set CYREG_B1_UDB08_D0, 0x40006528 +.set CYREG_B1_UDB09_D0, 0x40006529 +.set CYREG_B1_UDB10_D0, 0x4000652a +.set CYREG_B1_UDB11_D0, 0x4000652b +.set CYREG_B1_UDB04_D1, 0x40006534 +.set CYREG_B1_UDB05_D1, 0x40006535 +.set CYREG_B1_UDB06_D1, 0x40006536 +.set CYREG_B1_UDB07_D1, 0x40006537 +.set CYREG_B1_UDB08_D1, 0x40006538 +.set CYREG_B1_UDB09_D1, 0x40006539 +.set CYREG_B1_UDB10_D1, 0x4000653a +.set CYREG_B1_UDB11_D1, 0x4000653b +.set CYREG_B1_UDB04_F0, 0x40006544 +.set CYREG_B1_UDB05_F0, 0x40006545 +.set CYREG_B1_UDB06_F0, 0x40006546 +.set CYREG_B1_UDB07_F0, 0x40006547 +.set CYREG_B1_UDB08_F0, 0x40006548 +.set CYREG_B1_UDB09_F0, 0x40006549 +.set CYREG_B1_UDB10_F0, 0x4000654a +.set CYREG_B1_UDB11_F0, 0x4000654b +.set CYREG_B1_UDB04_F1, 0x40006554 +.set CYREG_B1_UDB05_F1, 0x40006555 +.set CYREG_B1_UDB06_F1, 0x40006556 +.set CYREG_B1_UDB07_F1, 0x40006557 +.set CYREG_B1_UDB08_F1, 0x40006558 +.set CYREG_B1_UDB09_F1, 0x40006559 +.set CYREG_B1_UDB10_F1, 0x4000655a +.set CYREG_B1_UDB11_F1, 0x4000655b +.set CYREG_B1_UDB04_ST, 0x40006564 +.set CYREG_B1_UDB05_ST, 0x40006565 +.set CYREG_B1_UDB06_ST, 0x40006566 +.set CYREG_B1_UDB07_ST, 0x40006567 +.set CYREG_B1_UDB08_ST, 0x40006568 +.set CYREG_B1_UDB09_ST, 0x40006569 +.set CYREG_B1_UDB10_ST, 0x4000656a +.set CYREG_B1_UDB11_ST, 0x4000656b +.set CYREG_B1_UDB04_CTL, 0x40006574 +.set CYREG_B1_UDB05_CTL, 0x40006575 +.set CYREG_B1_UDB06_CTL, 0x40006576 +.set CYREG_B1_UDB07_CTL, 0x40006577 +.set CYREG_B1_UDB08_CTL, 0x40006578 +.set CYREG_B1_UDB09_CTL, 0x40006579 +.set CYREG_B1_UDB10_CTL, 0x4000657a +.set CYREG_B1_UDB11_CTL, 0x4000657b +.set CYREG_B1_UDB04_MSK, 0x40006584 +.set CYREG_B1_UDB05_MSK, 0x40006585 +.set CYREG_B1_UDB06_MSK, 0x40006586 +.set CYREG_B1_UDB07_MSK, 0x40006587 +.set CYREG_B1_UDB08_MSK, 0x40006588 +.set CYREG_B1_UDB09_MSK, 0x40006589 +.set CYREG_B1_UDB10_MSK, 0x4000658a +.set CYREG_B1_UDB11_MSK, 0x4000658b +.set CYREG_B1_UDB04_ACTL, 0x40006594 +.set CYREG_B1_UDB05_ACTL, 0x40006595 +.set CYREG_B1_UDB06_ACTL, 0x40006596 +.set CYREG_B1_UDB07_ACTL, 0x40006597 +.set CYREG_B1_UDB08_ACTL, 0x40006598 +.set CYREG_B1_UDB09_ACTL, 0x40006599 +.set CYREG_B1_UDB10_ACTL, 0x4000659a +.set CYREG_B1_UDB11_ACTL, 0x4000659b +.set CYREG_B1_UDB04_MC, 0x400065a4 +.set CYREG_B1_UDB05_MC, 0x400065a5 +.set CYREG_B1_UDB06_MC, 0x400065a6 +.set CYREG_B1_UDB07_MC, 0x400065a7 +.set CYREG_B1_UDB08_MC, 0x400065a8 +.set CYREG_B1_UDB09_MC, 0x400065a9 +.set CYREG_B1_UDB10_MC, 0x400065aa +.set CYREG_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYREG_B0_UDB00_A0_A1, 0x40006800 +.set CYREG_B0_UDB01_A0_A1, 0x40006802 +.set CYREG_B0_UDB02_A0_A1, 0x40006804 +.set CYREG_B0_UDB03_A0_A1, 0x40006806 +.set CYREG_B0_UDB04_A0_A1, 0x40006808 +.set CYREG_B0_UDB05_A0_A1, 0x4000680a +.set CYREG_B0_UDB06_A0_A1, 0x4000680c +.set CYREG_B0_UDB07_A0_A1, 0x4000680e +.set CYREG_B0_UDB08_A0_A1, 0x40006810 +.set CYREG_B0_UDB09_A0_A1, 0x40006812 +.set CYREG_B0_UDB10_A0_A1, 0x40006814 +.set CYREG_B0_UDB11_A0_A1, 0x40006816 +.set CYREG_B0_UDB12_A0_A1, 0x40006818 +.set CYREG_B0_UDB13_A0_A1, 0x4000681a +.set CYREG_B0_UDB14_A0_A1, 0x4000681c +.set CYREG_B0_UDB15_A0_A1, 0x4000681e +.set CYREG_B0_UDB00_D0_D1, 0x40006840 +.set CYREG_B0_UDB01_D0_D1, 0x40006842 +.set CYREG_B0_UDB02_D0_D1, 0x40006844 +.set CYREG_B0_UDB03_D0_D1, 0x40006846 +.set CYREG_B0_UDB04_D0_D1, 0x40006848 +.set CYREG_B0_UDB05_D0_D1, 0x4000684a +.set CYREG_B0_UDB06_D0_D1, 0x4000684c +.set CYREG_B0_UDB07_D0_D1, 0x4000684e +.set CYREG_B0_UDB08_D0_D1, 0x40006850 +.set CYREG_B0_UDB09_D0_D1, 0x40006852 +.set CYREG_B0_UDB10_D0_D1, 0x40006854 +.set CYREG_B0_UDB11_D0_D1, 0x40006856 +.set CYREG_B0_UDB12_D0_D1, 0x40006858 +.set CYREG_B0_UDB13_D0_D1, 0x4000685a +.set CYREG_B0_UDB14_D0_D1, 0x4000685c +.set CYREG_B0_UDB15_D0_D1, 0x4000685e +.set CYREG_B0_UDB00_F0_F1, 0x40006880 +.set CYREG_B0_UDB01_F0_F1, 0x40006882 +.set CYREG_B0_UDB02_F0_F1, 0x40006884 +.set CYREG_B0_UDB03_F0_F1, 0x40006886 +.set CYREG_B0_UDB04_F0_F1, 0x40006888 +.set CYREG_B0_UDB05_F0_F1, 0x4000688a +.set CYREG_B0_UDB06_F0_F1, 0x4000688c +.set CYREG_B0_UDB07_F0_F1, 0x4000688e +.set CYREG_B0_UDB08_F0_F1, 0x40006890 +.set CYREG_B0_UDB09_F0_F1, 0x40006892 +.set CYREG_B0_UDB10_F0_F1, 0x40006894 +.set CYREG_B0_UDB11_F0_F1, 0x40006896 +.set CYREG_B0_UDB12_F0_F1, 0x40006898 +.set CYREG_B0_UDB13_F0_F1, 0x4000689a +.set CYREG_B0_UDB14_F0_F1, 0x4000689c +.set CYREG_B0_UDB15_F0_F1, 0x4000689e +.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 +.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 +.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 +.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 +.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 +.set CYREG_B0_UDB05_ST_CTL, 0x400068ca +.set CYREG_B0_UDB06_ST_CTL, 0x400068cc +.set CYREG_B0_UDB07_ST_CTL, 0x400068ce +.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 +.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 +.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 +.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 +.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 +.set CYREG_B0_UDB13_ST_CTL, 0x400068da +.set CYREG_B0_UDB14_ST_CTL, 0x400068dc +.set CYREG_B0_UDB15_ST_CTL, 0x400068de +.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYREG_B0_UDB00_MC_00, 0x40006940 +.set CYREG_B0_UDB01_MC_00, 0x40006942 +.set CYREG_B0_UDB02_MC_00, 0x40006944 +.set CYREG_B0_UDB03_MC_00, 0x40006946 +.set CYREG_B0_UDB04_MC_00, 0x40006948 +.set CYREG_B0_UDB05_MC_00, 0x4000694a +.set CYREG_B0_UDB06_MC_00, 0x4000694c +.set CYREG_B0_UDB07_MC_00, 0x4000694e +.set CYREG_B0_UDB08_MC_00, 0x40006950 +.set CYREG_B0_UDB09_MC_00, 0x40006952 +.set CYREG_B0_UDB10_MC_00, 0x40006954 +.set CYREG_B0_UDB11_MC_00, 0x40006956 +.set CYREG_B0_UDB12_MC_00, 0x40006958 +.set CYREG_B0_UDB13_MC_00, 0x4000695a +.set CYREG_B0_UDB14_MC_00, 0x4000695c +.set CYREG_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYREG_B1_UDB04_A0_A1, 0x40006a08 +.set CYREG_B1_UDB05_A0_A1, 0x40006a0a +.set CYREG_B1_UDB06_A0_A1, 0x40006a0c +.set CYREG_B1_UDB07_A0_A1, 0x40006a0e +.set CYREG_B1_UDB08_A0_A1, 0x40006a10 +.set CYREG_B1_UDB09_A0_A1, 0x40006a12 +.set CYREG_B1_UDB10_A0_A1, 0x40006a14 +.set CYREG_B1_UDB11_A0_A1, 0x40006a16 +.set CYREG_B1_UDB04_D0_D1, 0x40006a48 +.set CYREG_B1_UDB05_D0_D1, 0x40006a4a +.set CYREG_B1_UDB06_D0_D1, 0x40006a4c +.set CYREG_B1_UDB07_D0_D1, 0x40006a4e +.set CYREG_B1_UDB08_D0_D1, 0x40006a50 +.set CYREG_B1_UDB09_D0_D1, 0x40006a52 +.set CYREG_B1_UDB10_D0_D1, 0x40006a54 +.set CYREG_B1_UDB11_D0_D1, 0x40006a56 +.set CYREG_B1_UDB04_F0_F1, 0x40006a88 +.set CYREG_B1_UDB05_F0_F1, 0x40006a8a +.set CYREG_B1_UDB06_F0_F1, 0x40006a8c +.set CYREG_B1_UDB07_F0_F1, 0x40006a8e +.set CYREG_B1_UDB08_F0_F1, 0x40006a90 +.set CYREG_B1_UDB09_F0_F1, 0x40006a92 +.set CYREG_B1_UDB10_F0_F1, 0x40006a94 +.set CYREG_B1_UDB11_F0_F1, 0x40006a96 +.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYREG_B1_UDB05_ST_CTL, 0x40006aca +.set CYREG_B1_UDB06_ST_CTL, 0x40006acc +.set CYREG_B1_UDB07_ST_CTL, 0x40006ace +.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYREG_B1_UDB04_MC_00, 0x40006b48 +.set CYREG_B1_UDB05_MC_00, 0x40006b4a +.set CYREG_B1_UDB06_MC_00, 0x40006b4c +.set CYREG_B1_UDB07_MC_00, 0x40006b4e +.set CYREG_B1_UDB08_MC_00, 0x40006b50 +.set CYREG_B1_UDB09_MC_00, 0x40006b52 +.set CYREG_B1_UDB10_MC_00, 0x40006b54 +.set CYREG_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYREG_B0_UDB00_01_A0, 0x40006800 +.set CYREG_B0_UDB01_02_A0, 0x40006802 +.set CYREG_B0_UDB02_03_A0, 0x40006804 +.set CYREG_B0_UDB03_04_A0, 0x40006806 +.set CYREG_B0_UDB04_05_A0, 0x40006808 +.set CYREG_B0_UDB05_06_A0, 0x4000680a +.set CYREG_B0_UDB06_07_A0, 0x4000680c +.set CYREG_B0_UDB07_08_A0, 0x4000680e +.set CYREG_B0_UDB08_09_A0, 0x40006810 +.set CYREG_B0_UDB09_10_A0, 0x40006812 +.set CYREG_B0_UDB10_11_A0, 0x40006814 +.set CYREG_B0_UDB11_12_A0, 0x40006816 +.set CYREG_B0_UDB12_13_A0, 0x40006818 +.set CYREG_B0_UDB13_14_A0, 0x4000681a +.set CYREG_B0_UDB14_15_A0, 0x4000681c +.set CYREG_B0_UDB00_01_A1, 0x40006820 +.set CYREG_B0_UDB01_02_A1, 0x40006822 +.set CYREG_B0_UDB02_03_A1, 0x40006824 +.set CYREG_B0_UDB03_04_A1, 0x40006826 +.set CYREG_B0_UDB04_05_A1, 0x40006828 +.set CYREG_B0_UDB05_06_A1, 0x4000682a +.set CYREG_B0_UDB06_07_A1, 0x4000682c +.set CYREG_B0_UDB07_08_A1, 0x4000682e +.set CYREG_B0_UDB08_09_A1, 0x40006830 +.set CYREG_B0_UDB09_10_A1, 0x40006832 +.set CYREG_B0_UDB10_11_A1, 0x40006834 +.set CYREG_B0_UDB11_12_A1, 0x40006836 +.set CYREG_B0_UDB12_13_A1, 0x40006838 +.set CYREG_B0_UDB13_14_A1, 0x4000683a +.set CYREG_B0_UDB14_15_A1, 0x4000683c +.set CYREG_B0_UDB00_01_D0, 0x40006840 +.set CYREG_B0_UDB01_02_D0, 0x40006842 +.set CYREG_B0_UDB02_03_D0, 0x40006844 +.set CYREG_B0_UDB03_04_D0, 0x40006846 +.set CYREG_B0_UDB04_05_D0, 0x40006848 +.set CYREG_B0_UDB05_06_D0, 0x4000684a +.set CYREG_B0_UDB06_07_D0, 0x4000684c +.set CYREG_B0_UDB07_08_D0, 0x4000684e +.set CYREG_B0_UDB08_09_D0, 0x40006850 +.set CYREG_B0_UDB09_10_D0, 0x40006852 +.set CYREG_B0_UDB10_11_D0, 0x40006854 +.set CYREG_B0_UDB11_12_D0, 0x40006856 +.set CYREG_B0_UDB12_13_D0, 0x40006858 +.set CYREG_B0_UDB13_14_D0, 0x4000685a +.set CYREG_B0_UDB14_15_D0, 0x4000685c +.set CYREG_B0_UDB00_01_D1, 0x40006860 +.set CYREG_B0_UDB01_02_D1, 0x40006862 +.set CYREG_B0_UDB02_03_D1, 0x40006864 +.set CYREG_B0_UDB03_04_D1, 0x40006866 +.set CYREG_B0_UDB04_05_D1, 0x40006868 +.set CYREG_B0_UDB05_06_D1, 0x4000686a +.set CYREG_B0_UDB06_07_D1, 0x4000686c +.set CYREG_B0_UDB07_08_D1, 0x4000686e +.set CYREG_B0_UDB08_09_D1, 0x40006870 +.set CYREG_B0_UDB09_10_D1, 0x40006872 +.set CYREG_B0_UDB10_11_D1, 0x40006874 +.set CYREG_B0_UDB11_12_D1, 0x40006876 +.set CYREG_B0_UDB12_13_D1, 0x40006878 +.set CYREG_B0_UDB13_14_D1, 0x4000687a +.set CYREG_B0_UDB14_15_D1, 0x4000687c +.set CYREG_B0_UDB00_01_F0, 0x40006880 +.set CYREG_B0_UDB01_02_F0, 0x40006882 +.set CYREG_B0_UDB02_03_F0, 0x40006884 +.set CYREG_B0_UDB03_04_F0, 0x40006886 +.set CYREG_B0_UDB04_05_F0, 0x40006888 +.set CYREG_B0_UDB05_06_F0, 0x4000688a +.set CYREG_B0_UDB06_07_F0, 0x4000688c +.set CYREG_B0_UDB07_08_F0, 0x4000688e +.set CYREG_B0_UDB08_09_F0, 0x40006890 +.set CYREG_B0_UDB09_10_F0, 0x40006892 +.set CYREG_B0_UDB10_11_F0, 0x40006894 +.set CYREG_B0_UDB11_12_F0, 0x40006896 +.set CYREG_B0_UDB12_13_F0, 0x40006898 +.set CYREG_B0_UDB13_14_F0, 0x4000689a +.set CYREG_B0_UDB14_15_F0, 0x4000689c +.set CYREG_B0_UDB00_01_F1, 0x400068a0 +.set CYREG_B0_UDB01_02_F1, 0x400068a2 +.set CYREG_B0_UDB02_03_F1, 0x400068a4 +.set CYREG_B0_UDB03_04_F1, 0x400068a6 +.set CYREG_B0_UDB04_05_F1, 0x400068a8 +.set CYREG_B0_UDB05_06_F1, 0x400068aa +.set CYREG_B0_UDB06_07_F1, 0x400068ac +.set CYREG_B0_UDB07_08_F1, 0x400068ae +.set CYREG_B0_UDB08_09_F1, 0x400068b0 +.set CYREG_B0_UDB09_10_F1, 0x400068b2 +.set CYREG_B0_UDB10_11_F1, 0x400068b4 +.set CYREG_B0_UDB11_12_F1, 0x400068b6 +.set CYREG_B0_UDB12_13_F1, 0x400068b8 +.set CYREG_B0_UDB13_14_F1, 0x400068ba +.set CYREG_B0_UDB14_15_F1, 0x400068bc +.set CYREG_B0_UDB00_01_ST, 0x400068c0 +.set CYREG_B0_UDB01_02_ST, 0x400068c2 +.set CYREG_B0_UDB02_03_ST, 0x400068c4 +.set CYREG_B0_UDB03_04_ST, 0x400068c6 +.set CYREG_B0_UDB04_05_ST, 0x400068c8 +.set CYREG_B0_UDB05_06_ST, 0x400068ca +.set CYREG_B0_UDB06_07_ST, 0x400068cc +.set CYREG_B0_UDB07_08_ST, 0x400068ce +.set CYREG_B0_UDB08_09_ST, 0x400068d0 +.set CYREG_B0_UDB09_10_ST, 0x400068d2 +.set CYREG_B0_UDB10_11_ST, 0x400068d4 +.set CYREG_B0_UDB11_12_ST, 0x400068d6 +.set CYREG_B0_UDB12_13_ST, 0x400068d8 +.set CYREG_B0_UDB13_14_ST, 0x400068da +.set CYREG_B0_UDB14_15_ST, 0x400068dc +.set CYREG_B0_UDB00_01_CTL, 0x400068e0 +.set CYREG_B0_UDB01_02_CTL, 0x400068e2 +.set CYREG_B0_UDB02_03_CTL, 0x400068e4 +.set CYREG_B0_UDB03_04_CTL, 0x400068e6 +.set CYREG_B0_UDB04_05_CTL, 0x400068e8 +.set CYREG_B0_UDB05_06_CTL, 0x400068ea +.set CYREG_B0_UDB06_07_CTL, 0x400068ec +.set CYREG_B0_UDB07_08_CTL, 0x400068ee +.set CYREG_B0_UDB08_09_CTL, 0x400068f0 +.set CYREG_B0_UDB09_10_CTL, 0x400068f2 +.set CYREG_B0_UDB10_11_CTL, 0x400068f4 +.set CYREG_B0_UDB11_12_CTL, 0x400068f6 +.set CYREG_B0_UDB12_13_CTL, 0x400068f8 +.set CYREG_B0_UDB13_14_CTL, 0x400068fa +.set CYREG_B0_UDB14_15_CTL, 0x400068fc +.set CYREG_B0_UDB00_01_MSK, 0x40006900 +.set CYREG_B0_UDB01_02_MSK, 0x40006902 +.set CYREG_B0_UDB02_03_MSK, 0x40006904 +.set CYREG_B0_UDB03_04_MSK, 0x40006906 +.set CYREG_B0_UDB04_05_MSK, 0x40006908 +.set CYREG_B0_UDB05_06_MSK, 0x4000690a +.set CYREG_B0_UDB06_07_MSK, 0x4000690c +.set CYREG_B0_UDB07_08_MSK, 0x4000690e +.set CYREG_B0_UDB08_09_MSK, 0x40006910 +.set CYREG_B0_UDB09_10_MSK, 0x40006912 +.set CYREG_B0_UDB10_11_MSK, 0x40006914 +.set CYREG_B0_UDB11_12_MSK, 0x40006916 +.set CYREG_B0_UDB12_13_MSK, 0x40006918 +.set CYREG_B0_UDB13_14_MSK, 0x4000691a +.set CYREG_B0_UDB14_15_MSK, 0x4000691c +.set CYREG_B0_UDB00_01_ACTL, 0x40006920 +.set CYREG_B0_UDB01_02_ACTL, 0x40006922 +.set CYREG_B0_UDB02_03_ACTL, 0x40006924 +.set CYREG_B0_UDB03_04_ACTL, 0x40006926 +.set CYREG_B0_UDB04_05_ACTL, 0x40006928 +.set CYREG_B0_UDB05_06_ACTL, 0x4000692a +.set CYREG_B0_UDB06_07_ACTL, 0x4000692c +.set CYREG_B0_UDB07_08_ACTL, 0x4000692e +.set CYREG_B0_UDB08_09_ACTL, 0x40006930 +.set CYREG_B0_UDB09_10_ACTL, 0x40006932 +.set CYREG_B0_UDB10_11_ACTL, 0x40006934 +.set CYREG_B0_UDB11_12_ACTL, 0x40006936 +.set CYREG_B0_UDB12_13_ACTL, 0x40006938 +.set CYREG_B0_UDB13_14_ACTL, 0x4000693a +.set CYREG_B0_UDB14_15_ACTL, 0x4000693c +.set CYREG_B0_UDB00_01_MC, 0x40006940 +.set CYREG_B0_UDB01_02_MC, 0x40006942 +.set CYREG_B0_UDB02_03_MC, 0x40006944 +.set CYREG_B0_UDB03_04_MC, 0x40006946 +.set CYREG_B0_UDB04_05_MC, 0x40006948 +.set CYREG_B0_UDB05_06_MC, 0x4000694a +.set CYREG_B0_UDB06_07_MC, 0x4000694c +.set CYREG_B0_UDB07_08_MC, 0x4000694e +.set CYREG_B0_UDB08_09_MC, 0x40006950 +.set CYREG_B0_UDB09_10_MC, 0x40006952 +.set CYREG_B0_UDB10_11_MC, 0x40006954 +.set CYREG_B0_UDB11_12_MC, 0x40006956 +.set CYREG_B0_UDB12_13_MC, 0x40006958 +.set CYREG_B0_UDB13_14_MC, 0x4000695a +.set CYREG_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYREG_B1_UDB04_05_A0, 0x40006a08 +.set CYREG_B1_UDB05_06_A0, 0x40006a0a +.set CYREG_B1_UDB06_07_A0, 0x40006a0c +.set CYREG_B1_UDB07_08_A0, 0x40006a0e +.set CYREG_B1_UDB08_09_A0, 0x40006a10 +.set CYREG_B1_UDB09_10_A0, 0x40006a12 +.set CYREG_B1_UDB10_11_A0, 0x40006a14 +.set CYREG_B1_UDB11_12_A0, 0x40006a16 +.set CYREG_B1_UDB04_05_A1, 0x40006a28 +.set CYREG_B1_UDB05_06_A1, 0x40006a2a +.set CYREG_B1_UDB06_07_A1, 0x40006a2c +.set CYREG_B1_UDB07_08_A1, 0x40006a2e +.set CYREG_B1_UDB08_09_A1, 0x40006a30 +.set CYREG_B1_UDB09_10_A1, 0x40006a32 +.set CYREG_B1_UDB10_11_A1, 0x40006a34 +.set CYREG_B1_UDB11_12_A1, 0x40006a36 +.set CYREG_B1_UDB04_05_D0, 0x40006a48 +.set CYREG_B1_UDB05_06_D0, 0x40006a4a +.set CYREG_B1_UDB06_07_D0, 0x40006a4c +.set CYREG_B1_UDB07_08_D0, 0x40006a4e +.set CYREG_B1_UDB08_09_D0, 0x40006a50 +.set CYREG_B1_UDB09_10_D0, 0x40006a52 +.set CYREG_B1_UDB10_11_D0, 0x40006a54 +.set CYREG_B1_UDB11_12_D0, 0x40006a56 +.set CYREG_B1_UDB04_05_D1, 0x40006a68 +.set CYREG_B1_UDB05_06_D1, 0x40006a6a +.set CYREG_B1_UDB06_07_D1, 0x40006a6c +.set CYREG_B1_UDB07_08_D1, 0x40006a6e +.set CYREG_B1_UDB08_09_D1, 0x40006a70 +.set CYREG_B1_UDB09_10_D1, 0x40006a72 +.set CYREG_B1_UDB10_11_D1, 0x40006a74 +.set CYREG_B1_UDB11_12_D1, 0x40006a76 +.set CYREG_B1_UDB04_05_F0, 0x40006a88 +.set CYREG_B1_UDB05_06_F0, 0x40006a8a +.set CYREG_B1_UDB06_07_F0, 0x40006a8c +.set CYREG_B1_UDB07_08_F0, 0x40006a8e +.set CYREG_B1_UDB08_09_F0, 0x40006a90 +.set CYREG_B1_UDB09_10_F0, 0x40006a92 +.set CYREG_B1_UDB10_11_F0, 0x40006a94 +.set CYREG_B1_UDB11_12_F0, 0x40006a96 +.set CYREG_B1_UDB04_05_F1, 0x40006aa8 +.set CYREG_B1_UDB05_06_F1, 0x40006aaa +.set CYREG_B1_UDB06_07_F1, 0x40006aac +.set CYREG_B1_UDB07_08_F1, 0x40006aae +.set CYREG_B1_UDB08_09_F1, 0x40006ab0 +.set CYREG_B1_UDB09_10_F1, 0x40006ab2 +.set CYREG_B1_UDB10_11_F1, 0x40006ab4 +.set CYREG_B1_UDB11_12_F1, 0x40006ab6 +.set CYREG_B1_UDB04_05_ST, 0x40006ac8 +.set CYREG_B1_UDB05_06_ST, 0x40006aca +.set CYREG_B1_UDB06_07_ST, 0x40006acc +.set CYREG_B1_UDB07_08_ST, 0x40006ace +.set CYREG_B1_UDB08_09_ST, 0x40006ad0 +.set CYREG_B1_UDB09_10_ST, 0x40006ad2 +.set CYREG_B1_UDB10_11_ST, 0x40006ad4 +.set CYREG_B1_UDB11_12_ST, 0x40006ad6 +.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 +.set CYREG_B1_UDB05_06_CTL, 0x40006aea +.set CYREG_B1_UDB06_07_CTL, 0x40006aec +.set CYREG_B1_UDB07_08_CTL, 0x40006aee +.set CYREG_B1_UDB08_09_CTL, 0x40006af0 +.set CYREG_B1_UDB09_10_CTL, 0x40006af2 +.set CYREG_B1_UDB10_11_CTL, 0x40006af4 +.set CYREG_B1_UDB11_12_CTL, 0x40006af6 +.set CYREG_B1_UDB04_05_MSK, 0x40006b08 +.set CYREG_B1_UDB05_06_MSK, 0x40006b0a +.set CYREG_B1_UDB06_07_MSK, 0x40006b0c +.set CYREG_B1_UDB07_08_MSK, 0x40006b0e +.set CYREG_B1_UDB08_09_MSK, 0x40006b10 +.set CYREG_B1_UDB09_10_MSK, 0x40006b12 +.set CYREG_B1_UDB10_11_MSK, 0x40006b14 +.set CYREG_B1_UDB11_12_MSK, 0x40006b16 +.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 +.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a +.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c +.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e +.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 +.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 +.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 +.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 +.set CYREG_B1_UDB04_05_MC, 0x40006b48 +.set CYREG_B1_UDB05_06_MC, 0x40006b4a +.set CYREG_B1_UDB06_07_MC, 0x40006b4c +.set CYREG_B1_UDB07_08_MC, 0x40006b4e +.set CYREG_B1_UDB08_09_MC, 0x40006b50 +.set CYREG_B1_UDB09_10_MC, 0x40006b52 +.set CYREG_B1_UDB10_11_MC, 0x40006b54 +.set CYREG_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYREG_PHUB_CFG, 0x40007000 +.set CYREG_PHUB_ERR, 0x40007004 +.set CYREG_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYREG_PHUB_CH0_ACTION, 0x40007014 +.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYREG_PHUB_CH1_ACTION, 0x40007024 +.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYREG_PHUB_CH2_ACTION, 0x40007034 +.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYREG_PHUB_CH3_ACTION, 0x40007044 +.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYREG_PHUB_CH4_ACTION, 0x40007054 +.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYREG_PHUB_CH5_ACTION, 0x40007064 +.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYREG_PHUB_CH6_ACTION, 0x40007074 +.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYREG_PHUB_CH7_ACTION, 0x40007084 +.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYREG_PHUB_CH8_ACTION, 0x40007094 +.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYREG_PHUB_CH9_ACTION, 0x400070a4 +.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYREG_PHUB_CH10_ACTION, 0x400070b4 +.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYREG_PHUB_CH11_ACTION, 0x400070c4 +.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYREG_PHUB_CH12_ACTION, 0x400070d4 +.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYREG_PHUB_CH13_ACTION, 0x400070e4 +.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYREG_PHUB_CH14_ACTION, 0x400070f4 +.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYREG_PHUB_CH15_ACTION, 0x40007104 +.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYREG_PHUB_CH16_ACTION, 0x40007114 +.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYREG_PHUB_CH17_ACTION, 0x40007124 +.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYREG_PHUB_CH18_ACTION, 0x40007134 +.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYREG_PHUB_CH19_ACTION, 0x40007144 +.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYREG_PHUB_CH20_ACTION, 0x40007154 +.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYREG_PHUB_CH21_ACTION, 0x40007164 +.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYREG_PHUB_CH22_ACTION, 0x40007174 +.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYREG_PHUB_CH23_ACTION, 0x40007184 +.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYREG_EE_DATA_MBASE, 0x40008000 +.set CYREG_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 +.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 +.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYREG_CAN0_CSR_CMD, 0x4000a010 +.set CYREG_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYREG_CAN0_TX0_CMD, 0x4000a020 +.set CYREG_CAN0_TX0_ID, 0x4000a024 +.set CYREG_CAN0_TX0_DH, 0x4000a028 +.set CYREG_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYREG_CAN0_TX1_CMD, 0x4000a030 +.set CYREG_CAN0_TX1_ID, 0x4000a034 +.set CYREG_CAN0_TX1_DH, 0x4000a038 +.set CYREG_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYREG_CAN0_TX2_CMD, 0x4000a040 +.set CYREG_CAN0_TX2_ID, 0x4000a044 +.set CYREG_CAN0_TX2_DH, 0x4000a048 +.set CYREG_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYREG_CAN0_TX3_CMD, 0x4000a050 +.set CYREG_CAN0_TX3_ID, 0x4000a054 +.set CYREG_CAN0_TX3_DH, 0x4000a058 +.set CYREG_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYREG_CAN0_TX4_CMD, 0x4000a060 +.set CYREG_CAN0_TX4_ID, 0x4000a064 +.set CYREG_CAN0_TX4_DH, 0x4000a068 +.set CYREG_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYREG_CAN0_TX5_CMD, 0x4000a070 +.set CYREG_CAN0_TX5_ID, 0x4000a074 +.set CYREG_CAN0_TX5_DH, 0x4000a078 +.set CYREG_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYREG_CAN0_TX6_CMD, 0x4000a080 +.set CYREG_CAN0_TX6_ID, 0x4000a084 +.set CYREG_CAN0_TX6_DH, 0x4000a088 +.set CYREG_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYREG_CAN0_TX7_CMD, 0x4000a090 +.set CYREG_CAN0_TX7_ID, 0x4000a094 +.set CYREG_CAN0_TX7_DH, 0x4000a098 +.set CYREG_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 +.set CYREG_CAN0_RX0_ID, 0x4000a0a4 +.set CYREG_CAN0_RX0_DH, 0x4000a0a8 +.set CYREG_CAN0_RX0_DL, 0x4000a0ac +.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 +.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 +.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 +.set CYREG_CAN0_RX1_ID, 0x4000a0c4 +.set CYREG_CAN0_RX1_DH, 0x4000a0c8 +.set CYREG_CAN0_RX1_DL, 0x4000a0cc +.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 +.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 +.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 +.set CYREG_CAN0_RX2_ID, 0x4000a0e4 +.set CYREG_CAN0_RX2_DH, 0x4000a0e8 +.set CYREG_CAN0_RX2_DL, 0x4000a0ec +.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 +.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 +.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYREG_CAN0_RX3_CMD, 0x4000a100 +.set CYREG_CAN0_RX3_ID, 0x4000a104 +.set CYREG_CAN0_RX3_DH, 0x4000a108 +.set CYREG_CAN0_RX3_DL, 0x4000a10c +.set CYREG_CAN0_RX3_AMR, 0x4000a110 +.set CYREG_CAN0_RX3_ACR, 0x4000a114 +.set CYREG_CAN0_RX3_AMRD, 0x4000a118 +.set CYREG_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYREG_CAN0_RX4_CMD, 0x4000a120 +.set CYREG_CAN0_RX4_ID, 0x4000a124 +.set CYREG_CAN0_RX4_DH, 0x4000a128 +.set CYREG_CAN0_RX4_DL, 0x4000a12c +.set CYREG_CAN0_RX4_AMR, 0x4000a130 +.set CYREG_CAN0_RX4_ACR, 0x4000a134 +.set CYREG_CAN0_RX4_AMRD, 0x4000a138 +.set CYREG_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYREG_CAN0_RX5_CMD, 0x4000a140 +.set CYREG_CAN0_RX5_ID, 0x4000a144 +.set CYREG_CAN0_RX5_DH, 0x4000a148 +.set CYREG_CAN0_RX5_DL, 0x4000a14c +.set CYREG_CAN0_RX5_AMR, 0x4000a150 +.set CYREG_CAN0_RX5_ACR, 0x4000a154 +.set CYREG_CAN0_RX5_AMRD, 0x4000a158 +.set CYREG_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYREG_CAN0_RX6_CMD, 0x4000a160 +.set CYREG_CAN0_RX6_ID, 0x4000a164 +.set CYREG_CAN0_RX6_DH, 0x4000a168 +.set CYREG_CAN0_RX6_DL, 0x4000a16c +.set CYREG_CAN0_RX6_AMR, 0x4000a170 +.set CYREG_CAN0_RX6_ACR, 0x4000a174 +.set CYREG_CAN0_RX6_AMRD, 0x4000a178 +.set CYREG_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYREG_CAN0_RX7_CMD, 0x4000a180 +.set CYREG_CAN0_RX7_ID, 0x4000a184 +.set CYREG_CAN0_RX7_DH, 0x4000a188 +.set CYREG_CAN0_RX7_DL, 0x4000a18c +.set CYREG_CAN0_RX7_AMR, 0x4000a190 +.set CYREG_CAN0_RX7_ACR, 0x4000a194 +.set CYREG_CAN0_RX7_AMRD, 0x4000a198 +.set CYREG_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 +.set CYREG_CAN0_RX8_ID, 0x4000a1a4 +.set CYREG_CAN0_RX8_DH, 0x4000a1a8 +.set CYREG_CAN0_RX8_DL, 0x4000a1ac +.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 +.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 +.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 +.set CYREG_CAN0_RX9_ID, 0x4000a1c4 +.set CYREG_CAN0_RX9_DH, 0x4000a1c8 +.set CYREG_CAN0_RX9_DL, 0x4000a1cc +.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 +.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 +.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 +.set CYREG_CAN0_RX10_ID, 0x4000a1e4 +.set CYREG_CAN0_RX10_DH, 0x4000a1e8 +.set CYREG_CAN0_RX10_DL, 0x4000a1ec +.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 +.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 +.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYREG_CAN0_RX11_CMD, 0x4000a200 +.set CYREG_CAN0_RX11_ID, 0x4000a204 +.set CYREG_CAN0_RX11_DH, 0x4000a208 +.set CYREG_CAN0_RX11_DL, 0x4000a20c +.set CYREG_CAN0_RX11_AMR, 0x4000a210 +.set CYREG_CAN0_RX11_ACR, 0x4000a214 +.set CYREG_CAN0_RX11_AMRD, 0x4000a218 +.set CYREG_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYREG_CAN0_RX12_CMD, 0x4000a220 +.set CYREG_CAN0_RX12_ID, 0x4000a224 +.set CYREG_CAN0_RX12_DH, 0x4000a228 +.set CYREG_CAN0_RX12_DL, 0x4000a22c +.set CYREG_CAN0_RX12_AMR, 0x4000a230 +.set CYREG_CAN0_RX12_ACR, 0x4000a234 +.set CYREG_CAN0_RX12_AMRD, 0x4000a238 +.set CYREG_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYREG_CAN0_RX13_CMD, 0x4000a240 +.set CYREG_CAN0_RX13_ID, 0x4000a244 +.set CYREG_CAN0_RX13_DH, 0x4000a248 +.set CYREG_CAN0_RX13_DL, 0x4000a24c +.set CYREG_CAN0_RX13_AMR, 0x4000a250 +.set CYREG_CAN0_RX13_ACR, 0x4000a254 +.set CYREG_CAN0_RX13_AMRD, 0x4000a258 +.set CYREG_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYREG_CAN0_RX14_CMD, 0x4000a260 +.set CYREG_CAN0_RX14_ID, 0x4000a264 +.set CYREG_CAN0_RX14_DH, 0x4000a268 +.set CYREG_CAN0_RX14_DL, 0x4000a26c +.set CYREG_CAN0_RX14_AMR, 0x4000a270 +.set CYREG_CAN0_RX14_ACR, 0x4000a274 +.set CYREG_CAN0_RX14_AMRD, 0x4000a278 +.set CYREG_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYREG_CAN0_RX15_CMD, 0x4000a280 +.set CYREG_CAN0_RX15_ID, 0x4000a284 +.set CYREG_CAN0_RX15_DH, 0x4000a288 +.set CYREG_CAN0_RX15_DL, 0x4000a28c +.set CYREG_CAN0_RX15_AMR, 0x4000a290 +.set CYREG_CAN0_RX15_ACR, 0x4000a294 +.set CYREG_CAN0_RX15_AMRD, 0x4000a298 +.set CYREG_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYREG_DFB0_CR, 0x4000c780 +.set CYREG_DFB0_SR, 0x4000c784 +.set CYREG_DFB0_RAM_EN, 0x4000c788 +.set CYREG_DFB0_RAM_DIR, 0x4000c78c +.set CYREG_DFB0_SEMA, 0x4000c790 +.set CYREG_DFB0_DSI_CTRL, 0x4000c794 +.set CYREG_DFB0_INT_CTRL, 0x4000c798 +.set CYREG_DFB0_DMA_CTRL, 0x4000c79c +.set CYREG_DFB0_STAGEA, 0x4000c7a0 +.set CYREG_DFB0_STAGEAM, 0x4000c7a1 +.set CYREG_DFB0_STAGEAH, 0x4000c7a2 +.set CYREG_DFB0_STAGEB, 0x4000c7a4 +.set CYREG_DFB0_STAGEBM, 0x4000c7a5 +.set CYREG_DFB0_STAGEBH, 0x4000c7a6 +.set CYREG_DFB0_HOLDA, 0x4000c7a8 +.set CYREG_DFB0_HOLDAM, 0x4000c7a9 +.set CYREG_DFB0_HOLDAH, 0x4000c7aa +.set CYREG_DFB0_HOLDAS, 0x4000c7ab +.set CYREG_DFB0_HOLDB, 0x4000c7ac +.set CYREG_DFB0_HOLDBM, 0x4000c7ad +.set CYREG_DFB0_HOLDBH, 0x4000c7ae +.set CYREG_DFB0_HOLDBS, 0x4000c7af +.set CYREG_DFB0_COHER, 0x4000c7b0 +.set CYREG_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYREG_B0_P0_U0_CFG0, 0x40010040 +.set CYREG_B0_P0_U0_CFG1, 0x40010041 +.set CYREG_B0_P0_U0_CFG2, 0x40010042 +.set CYREG_B0_P0_U0_CFG3, 0x40010043 +.set CYREG_B0_P0_U0_CFG4, 0x40010044 +.set CYREG_B0_P0_U0_CFG5, 0x40010045 +.set CYREG_B0_P0_U0_CFG6, 0x40010046 +.set CYREG_B0_P0_U0_CFG7, 0x40010047 +.set CYREG_B0_P0_U0_CFG8, 0x40010048 +.set CYREG_B0_P0_U0_CFG9, 0x40010049 +.set CYREG_B0_P0_U0_CFG10, 0x4001004a +.set CYREG_B0_P0_U0_CFG11, 0x4001004b +.set CYREG_B0_P0_U0_CFG12, 0x4001004c +.set CYREG_B0_P0_U0_CFG13, 0x4001004d +.set CYREG_B0_P0_U0_CFG14, 0x4001004e +.set CYREG_B0_P0_U0_CFG15, 0x4001004f +.set CYREG_B0_P0_U0_CFG16, 0x40010050 +.set CYREG_B0_P0_U0_CFG17, 0x40010051 +.set CYREG_B0_P0_U0_CFG18, 0x40010052 +.set CYREG_B0_P0_U0_CFG19, 0x40010053 +.set CYREG_B0_P0_U0_CFG20, 0x40010054 +.set CYREG_B0_P0_U0_CFG21, 0x40010055 +.set CYREG_B0_P0_U0_CFG22, 0x40010056 +.set CYREG_B0_P0_U0_CFG23, 0x40010057 +.set CYREG_B0_P0_U0_CFG24, 0x40010058 +.set CYREG_B0_P0_U0_CFG25, 0x40010059 +.set CYREG_B0_P0_U0_CFG26, 0x4001005a +.set CYREG_B0_P0_U0_CFG27, 0x4001005b +.set CYREG_B0_P0_U0_CFG28, 0x4001005c +.set CYREG_B0_P0_U0_CFG29, 0x4001005d +.set CYREG_B0_P0_U0_CFG30, 0x4001005e +.set CYREG_B0_P0_U0_CFG31, 0x4001005f +.set CYREG_B0_P0_U0_DCFG0, 0x40010060 +.set CYREG_B0_P0_U0_DCFG1, 0x40010062 +.set CYREG_B0_P0_U0_DCFG2, 0x40010064 +.set CYREG_B0_P0_U0_DCFG3, 0x40010066 +.set CYREG_B0_P0_U0_DCFG4, 0x40010068 +.set CYREG_B0_P0_U0_DCFG5, 0x4001006a +.set CYREG_B0_P0_U0_DCFG6, 0x4001006c +.set CYREG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYREG_B0_P0_U1_CFG0, 0x400100c0 +.set CYREG_B0_P0_U1_CFG1, 0x400100c1 +.set CYREG_B0_P0_U1_CFG2, 0x400100c2 +.set CYREG_B0_P0_U1_CFG3, 0x400100c3 +.set CYREG_B0_P0_U1_CFG4, 0x400100c4 +.set CYREG_B0_P0_U1_CFG5, 0x400100c5 +.set CYREG_B0_P0_U1_CFG6, 0x400100c6 +.set CYREG_B0_P0_U1_CFG7, 0x400100c7 +.set CYREG_B0_P0_U1_CFG8, 0x400100c8 +.set CYREG_B0_P0_U1_CFG9, 0x400100c9 +.set CYREG_B0_P0_U1_CFG10, 0x400100ca +.set CYREG_B0_P0_U1_CFG11, 0x400100cb +.set CYREG_B0_P0_U1_CFG12, 0x400100cc +.set CYREG_B0_P0_U1_CFG13, 0x400100cd +.set CYREG_B0_P0_U1_CFG14, 0x400100ce +.set CYREG_B0_P0_U1_CFG15, 0x400100cf +.set CYREG_B0_P0_U1_CFG16, 0x400100d0 +.set CYREG_B0_P0_U1_CFG17, 0x400100d1 +.set CYREG_B0_P0_U1_CFG18, 0x400100d2 +.set CYREG_B0_P0_U1_CFG19, 0x400100d3 +.set CYREG_B0_P0_U1_CFG20, 0x400100d4 +.set CYREG_B0_P0_U1_CFG21, 0x400100d5 +.set CYREG_B0_P0_U1_CFG22, 0x400100d6 +.set CYREG_B0_P0_U1_CFG23, 0x400100d7 +.set CYREG_B0_P0_U1_CFG24, 0x400100d8 +.set CYREG_B0_P0_U1_CFG25, 0x400100d9 +.set CYREG_B0_P0_U1_CFG26, 0x400100da +.set CYREG_B0_P0_U1_CFG27, 0x400100db +.set CYREG_B0_P0_U1_CFG28, 0x400100dc +.set CYREG_B0_P0_U1_CFG29, 0x400100dd +.set CYREG_B0_P0_U1_CFG30, 0x400100de +.set CYREG_B0_P0_U1_CFG31, 0x400100df +.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYREG_B0_P0_U1_DCFG5, 0x400100ea +.set CYREG_B0_P0_U1_DCFG6, 0x400100ec +.set CYREG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYREG_B0_P1_U0_CFG0, 0x40010240 +.set CYREG_B0_P1_U0_CFG1, 0x40010241 +.set CYREG_B0_P1_U0_CFG2, 0x40010242 +.set CYREG_B0_P1_U0_CFG3, 0x40010243 +.set CYREG_B0_P1_U0_CFG4, 0x40010244 +.set CYREG_B0_P1_U0_CFG5, 0x40010245 +.set CYREG_B0_P1_U0_CFG6, 0x40010246 +.set CYREG_B0_P1_U0_CFG7, 0x40010247 +.set CYREG_B0_P1_U0_CFG8, 0x40010248 +.set CYREG_B0_P1_U0_CFG9, 0x40010249 +.set CYREG_B0_P1_U0_CFG10, 0x4001024a +.set CYREG_B0_P1_U0_CFG11, 0x4001024b +.set CYREG_B0_P1_U0_CFG12, 0x4001024c +.set CYREG_B0_P1_U0_CFG13, 0x4001024d +.set CYREG_B0_P1_U0_CFG14, 0x4001024e +.set CYREG_B0_P1_U0_CFG15, 0x4001024f +.set CYREG_B0_P1_U0_CFG16, 0x40010250 +.set CYREG_B0_P1_U0_CFG17, 0x40010251 +.set CYREG_B0_P1_U0_CFG18, 0x40010252 +.set CYREG_B0_P1_U0_CFG19, 0x40010253 +.set CYREG_B0_P1_U0_CFG20, 0x40010254 +.set CYREG_B0_P1_U0_CFG21, 0x40010255 +.set CYREG_B0_P1_U0_CFG22, 0x40010256 +.set CYREG_B0_P1_U0_CFG23, 0x40010257 +.set CYREG_B0_P1_U0_CFG24, 0x40010258 +.set CYREG_B0_P1_U0_CFG25, 0x40010259 +.set CYREG_B0_P1_U0_CFG26, 0x4001025a +.set CYREG_B0_P1_U0_CFG27, 0x4001025b +.set CYREG_B0_P1_U0_CFG28, 0x4001025c +.set CYREG_B0_P1_U0_CFG29, 0x4001025d +.set CYREG_B0_P1_U0_CFG30, 0x4001025e +.set CYREG_B0_P1_U0_CFG31, 0x4001025f +.set CYREG_B0_P1_U0_DCFG0, 0x40010260 +.set CYREG_B0_P1_U0_DCFG1, 0x40010262 +.set CYREG_B0_P1_U0_DCFG2, 0x40010264 +.set CYREG_B0_P1_U0_DCFG3, 0x40010266 +.set CYREG_B0_P1_U0_DCFG4, 0x40010268 +.set CYREG_B0_P1_U0_DCFG5, 0x4001026a +.set CYREG_B0_P1_U0_DCFG6, 0x4001026c +.set CYREG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYREG_B0_P1_U1_CFG0, 0x400102c0 +.set CYREG_B0_P1_U1_CFG1, 0x400102c1 +.set CYREG_B0_P1_U1_CFG2, 0x400102c2 +.set CYREG_B0_P1_U1_CFG3, 0x400102c3 +.set CYREG_B0_P1_U1_CFG4, 0x400102c4 +.set CYREG_B0_P1_U1_CFG5, 0x400102c5 +.set CYREG_B0_P1_U1_CFG6, 0x400102c6 +.set CYREG_B0_P1_U1_CFG7, 0x400102c7 +.set CYREG_B0_P1_U1_CFG8, 0x400102c8 +.set CYREG_B0_P1_U1_CFG9, 0x400102c9 +.set CYREG_B0_P1_U1_CFG10, 0x400102ca +.set CYREG_B0_P1_U1_CFG11, 0x400102cb +.set CYREG_B0_P1_U1_CFG12, 0x400102cc +.set CYREG_B0_P1_U1_CFG13, 0x400102cd +.set CYREG_B0_P1_U1_CFG14, 0x400102ce +.set CYREG_B0_P1_U1_CFG15, 0x400102cf +.set CYREG_B0_P1_U1_CFG16, 0x400102d0 +.set CYREG_B0_P1_U1_CFG17, 0x400102d1 +.set CYREG_B0_P1_U1_CFG18, 0x400102d2 +.set CYREG_B0_P1_U1_CFG19, 0x400102d3 +.set CYREG_B0_P1_U1_CFG20, 0x400102d4 +.set CYREG_B0_P1_U1_CFG21, 0x400102d5 +.set CYREG_B0_P1_U1_CFG22, 0x400102d6 +.set CYREG_B0_P1_U1_CFG23, 0x400102d7 +.set CYREG_B0_P1_U1_CFG24, 0x400102d8 +.set CYREG_B0_P1_U1_CFG25, 0x400102d9 +.set CYREG_B0_P1_U1_CFG26, 0x400102da +.set CYREG_B0_P1_U1_CFG27, 0x400102db +.set CYREG_B0_P1_U1_CFG28, 0x400102dc +.set CYREG_B0_P1_U1_CFG29, 0x400102dd +.set CYREG_B0_P1_U1_CFG30, 0x400102de +.set CYREG_B0_P1_U1_CFG31, 0x400102df +.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYREG_B0_P1_U1_DCFG5, 0x400102ea +.set CYREG_B0_P1_U1_DCFG6, 0x400102ec +.set CYREG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYREG_B0_P2_U0_CFG0, 0x40010440 +.set CYREG_B0_P2_U0_CFG1, 0x40010441 +.set CYREG_B0_P2_U0_CFG2, 0x40010442 +.set CYREG_B0_P2_U0_CFG3, 0x40010443 +.set CYREG_B0_P2_U0_CFG4, 0x40010444 +.set CYREG_B0_P2_U0_CFG5, 0x40010445 +.set CYREG_B0_P2_U0_CFG6, 0x40010446 +.set CYREG_B0_P2_U0_CFG7, 0x40010447 +.set CYREG_B0_P2_U0_CFG8, 0x40010448 +.set CYREG_B0_P2_U0_CFG9, 0x40010449 +.set CYREG_B0_P2_U0_CFG10, 0x4001044a +.set CYREG_B0_P2_U0_CFG11, 0x4001044b +.set CYREG_B0_P2_U0_CFG12, 0x4001044c +.set CYREG_B0_P2_U0_CFG13, 0x4001044d +.set CYREG_B0_P2_U0_CFG14, 0x4001044e +.set CYREG_B0_P2_U0_CFG15, 0x4001044f +.set CYREG_B0_P2_U0_CFG16, 0x40010450 +.set CYREG_B0_P2_U0_CFG17, 0x40010451 +.set CYREG_B0_P2_U0_CFG18, 0x40010452 +.set CYREG_B0_P2_U0_CFG19, 0x40010453 +.set CYREG_B0_P2_U0_CFG20, 0x40010454 +.set CYREG_B0_P2_U0_CFG21, 0x40010455 +.set CYREG_B0_P2_U0_CFG22, 0x40010456 +.set CYREG_B0_P2_U0_CFG23, 0x40010457 +.set CYREG_B0_P2_U0_CFG24, 0x40010458 +.set CYREG_B0_P2_U0_CFG25, 0x40010459 +.set CYREG_B0_P2_U0_CFG26, 0x4001045a +.set CYREG_B0_P2_U0_CFG27, 0x4001045b +.set CYREG_B0_P2_U0_CFG28, 0x4001045c +.set CYREG_B0_P2_U0_CFG29, 0x4001045d +.set CYREG_B0_P2_U0_CFG30, 0x4001045e +.set CYREG_B0_P2_U0_CFG31, 0x4001045f +.set CYREG_B0_P2_U0_DCFG0, 0x40010460 +.set CYREG_B0_P2_U0_DCFG1, 0x40010462 +.set CYREG_B0_P2_U0_DCFG2, 0x40010464 +.set CYREG_B0_P2_U0_DCFG3, 0x40010466 +.set CYREG_B0_P2_U0_DCFG4, 0x40010468 +.set CYREG_B0_P2_U0_DCFG5, 0x4001046a +.set CYREG_B0_P2_U0_DCFG6, 0x4001046c +.set CYREG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYREG_B0_P2_U1_CFG0, 0x400104c0 +.set CYREG_B0_P2_U1_CFG1, 0x400104c1 +.set CYREG_B0_P2_U1_CFG2, 0x400104c2 +.set CYREG_B0_P2_U1_CFG3, 0x400104c3 +.set CYREG_B0_P2_U1_CFG4, 0x400104c4 +.set CYREG_B0_P2_U1_CFG5, 0x400104c5 +.set CYREG_B0_P2_U1_CFG6, 0x400104c6 +.set CYREG_B0_P2_U1_CFG7, 0x400104c7 +.set CYREG_B0_P2_U1_CFG8, 0x400104c8 +.set CYREG_B0_P2_U1_CFG9, 0x400104c9 +.set CYREG_B0_P2_U1_CFG10, 0x400104ca +.set CYREG_B0_P2_U1_CFG11, 0x400104cb +.set CYREG_B0_P2_U1_CFG12, 0x400104cc +.set CYREG_B0_P2_U1_CFG13, 0x400104cd +.set CYREG_B0_P2_U1_CFG14, 0x400104ce +.set CYREG_B0_P2_U1_CFG15, 0x400104cf +.set CYREG_B0_P2_U1_CFG16, 0x400104d0 +.set CYREG_B0_P2_U1_CFG17, 0x400104d1 +.set CYREG_B0_P2_U1_CFG18, 0x400104d2 +.set CYREG_B0_P2_U1_CFG19, 0x400104d3 +.set CYREG_B0_P2_U1_CFG20, 0x400104d4 +.set CYREG_B0_P2_U1_CFG21, 0x400104d5 +.set CYREG_B0_P2_U1_CFG22, 0x400104d6 +.set CYREG_B0_P2_U1_CFG23, 0x400104d7 +.set CYREG_B0_P2_U1_CFG24, 0x400104d8 +.set CYREG_B0_P2_U1_CFG25, 0x400104d9 +.set CYREG_B0_P2_U1_CFG26, 0x400104da +.set CYREG_B0_P2_U1_CFG27, 0x400104db +.set CYREG_B0_P2_U1_CFG28, 0x400104dc +.set CYREG_B0_P2_U1_CFG29, 0x400104dd +.set CYREG_B0_P2_U1_CFG30, 0x400104de +.set CYREG_B0_P2_U1_CFG31, 0x400104df +.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYREG_B0_P2_U1_DCFG5, 0x400104ea +.set CYREG_B0_P2_U1_DCFG6, 0x400104ec +.set CYREG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYREG_B0_P3_U0_CFG0, 0x40010640 +.set CYREG_B0_P3_U0_CFG1, 0x40010641 +.set CYREG_B0_P3_U0_CFG2, 0x40010642 +.set CYREG_B0_P3_U0_CFG3, 0x40010643 +.set CYREG_B0_P3_U0_CFG4, 0x40010644 +.set CYREG_B0_P3_U0_CFG5, 0x40010645 +.set CYREG_B0_P3_U0_CFG6, 0x40010646 +.set CYREG_B0_P3_U0_CFG7, 0x40010647 +.set CYREG_B0_P3_U0_CFG8, 0x40010648 +.set CYREG_B0_P3_U0_CFG9, 0x40010649 +.set CYREG_B0_P3_U0_CFG10, 0x4001064a +.set CYREG_B0_P3_U0_CFG11, 0x4001064b +.set CYREG_B0_P3_U0_CFG12, 0x4001064c +.set CYREG_B0_P3_U0_CFG13, 0x4001064d +.set CYREG_B0_P3_U0_CFG14, 0x4001064e +.set CYREG_B0_P3_U0_CFG15, 0x4001064f +.set CYREG_B0_P3_U0_CFG16, 0x40010650 +.set CYREG_B0_P3_U0_CFG17, 0x40010651 +.set CYREG_B0_P3_U0_CFG18, 0x40010652 +.set CYREG_B0_P3_U0_CFG19, 0x40010653 +.set CYREG_B0_P3_U0_CFG20, 0x40010654 +.set CYREG_B0_P3_U0_CFG21, 0x40010655 +.set CYREG_B0_P3_U0_CFG22, 0x40010656 +.set CYREG_B0_P3_U0_CFG23, 0x40010657 +.set CYREG_B0_P3_U0_CFG24, 0x40010658 +.set CYREG_B0_P3_U0_CFG25, 0x40010659 +.set CYREG_B0_P3_U0_CFG26, 0x4001065a +.set CYREG_B0_P3_U0_CFG27, 0x4001065b +.set CYREG_B0_P3_U0_CFG28, 0x4001065c +.set CYREG_B0_P3_U0_CFG29, 0x4001065d +.set CYREG_B0_P3_U0_CFG30, 0x4001065e +.set CYREG_B0_P3_U0_CFG31, 0x4001065f +.set CYREG_B0_P3_U0_DCFG0, 0x40010660 +.set CYREG_B0_P3_U0_DCFG1, 0x40010662 +.set CYREG_B0_P3_U0_DCFG2, 0x40010664 +.set CYREG_B0_P3_U0_DCFG3, 0x40010666 +.set CYREG_B0_P3_U0_DCFG4, 0x40010668 +.set CYREG_B0_P3_U0_DCFG5, 0x4001066a +.set CYREG_B0_P3_U0_DCFG6, 0x4001066c +.set CYREG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYREG_B0_P3_U1_CFG0, 0x400106c0 +.set CYREG_B0_P3_U1_CFG1, 0x400106c1 +.set CYREG_B0_P3_U1_CFG2, 0x400106c2 +.set CYREG_B0_P3_U1_CFG3, 0x400106c3 +.set CYREG_B0_P3_U1_CFG4, 0x400106c4 +.set CYREG_B0_P3_U1_CFG5, 0x400106c5 +.set CYREG_B0_P3_U1_CFG6, 0x400106c6 +.set CYREG_B0_P3_U1_CFG7, 0x400106c7 +.set CYREG_B0_P3_U1_CFG8, 0x400106c8 +.set CYREG_B0_P3_U1_CFG9, 0x400106c9 +.set CYREG_B0_P3_U1_CFG10, 0x400106ca +.set CYREG_B0_P3_U1_CFG11, 0x400106cb +.set CYREG_B0_P3_U1_CFG12, 0x400106cc +.set CYREG_B0_P3_U1_CFG13, 0x400106cd +.set CYREG_B0_P3_U1_CFG14, 0x400106ce +.set CYREG_B0_P3_U1_CFG15, 0x400106cf +.set CYREG_B0_P3_U1_CFG16, 0x400106d0 +.set CYREG_B0_P3_U1_CFG17, 0x400106d1 +.set CYREG_B0_P3_U1_CFG18, 0x400106d2 +.set CYREG_B0_P3_U1_CFG19, 0x400106d3 +.set CYREG_B0_P3_U1_CFG20, 0x400106d4 +.set CYREG_B0_P3_U1_CFG21, 0x400106d5 +.set CYREG_B0_P3_U1_CFG22, 0x400106d6 +.set CYREG_B0_P3_U1_CFG23, 0x400106d7 +.set CYREG_B0_P3_U1_CFG24, 0x400106d8 +.set CYREG_B0_P3_U1_CFG25, 0x400106d9 +.set CYREG_B0_P3_U1_CFG26, 0x400106da +.set CYREG_B0_P3_U1_CFG27, 0x400106db +.set CYREG_B0_P3_U1_CFG28, 0x400106dc +.set CYREG_B0_P3_U1_CFG29, 0x400106dd +.set CYREG_B0_P3_U1_CFG30, 0x400106de +.set CYREG_B0_P3_U1_CFG31, 0x400106df +.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYREG_B0_P3_U1_DCFG5, 0x400106ea +.set CYREG_B0_P3_U1_DCFG6, 0x400106ec +.set CYREG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYREG_B0_P4_U0_CFG0, 0x40010840 +.set CYREG_B0_P4_U0_CFG1, 0x40010841 +.set CYREG_B0_P4_U0_CFG2, 0x40010842 +.set CYREG_B0_P4_U0_CFG3, 0x40010843 +.set CYREG_B0_P4_U0_CFG4, 0x40010844 +.set CYREG_B0_P4_U0_CFG5, 0x40010845 +.set CYREG_B0_P4_U0_CFG6, 0x40010846 +.set CYREG_B0_P4_U0_CFG7, 0x40010847 +.set CYREG_B0_P4_U0_CFG8, 0x40010848 +.set CYREG_B0_P4_U0_CFG9, 0x40010849 +.set CYREG_B0_P4_U0_CFG10, 0x4001084a +.set CYREG_B0_P4_U0_CFG11, 0x4001084b +.set CYREG_B0_P4_U0_CFG12, 0x4001084c +.set CYREG_B0_P4_U0_CFG13, 0x4001084d +.set CYREG_B0_P4_U0_CFG14, 0x4001084e +.set CYREG_B0_P4_U0_CFG15, 0x4001084f +.set CYREG_B0_P4_U0_CFG16, 0x40010850 +.set CYREG_B0_P4_U0_CFG17, 0x40010851 +.set CYREG_B0_P4_U0_CFG18, 0x40010852 +.set CYREG_B0_P4_U0_CFG19, 0x40010853 +.set CYREG_B0_P4_U0_CFG20, 0x40010854 +.set CYREG_B0_P4_U0_CFG21, 0x40010855 +.set CYREG_B0_P4_U0_CFG22, 0x40010856 +.set CYREG_B0_P4_U0_CFG23, 0x40010857 +.set CYREG_B0_P4_U0_CFG24, 0x40010858 +.set CYREG_B0_P4_U0_CFG25, 0x40010859 +.set CYREG_B0_P4_U0_CFG26, 0x4001085a +.set CYREG_B0_P4_U0_CFG27, 0x4001085b +.set CYREG_B0_P4_U0_CFG28, 0x4001085c +.set CYREG_B0_P4_U0_CFG29, 0x4001085d +.set CYREG_B0_P4_U0_CFG30, 0x4001085e +.set CYREG_B0_P4_U0_CFG31, 0x4001085f +.set CYREG_B0_P4_U0_DCFG0, 0x40010860 +.set CYREG_B0_P4_U0_DCFG1, 0x40010862 +.set CYREG_B0_P4_U0_DCFG2, 0x40010864 +.set CYREG_B0_P4_U0_DCFG3, 0x40010866 +.set CYREG_B0_P4_U0_DCFG4, 0x40010868 +.set CYREG_B0_P4_U0_DCFG5, 0x4001086a +.set CYREG_B0_P4_U0_DCFG6, 0x4001086c +.set CYREG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYREG_B0_P4_U1_CFG0, 0x400108c0 +.set CYREG_B0_P4_U1_CFG1, 0x400108c1 +.set CYREG_B0_P4_U1_CFG2, 0x400108c2 +.set CYREG_B0_P4_U1_CFG3, 0x400108c3 +.set CYREG_B0_P4_U1_CFG4, 0x400108c4 +.set CYREG_B0_P4_U1_CFG5, 0x400108c5 +.set CYREG_B0_P4_U1_CFG6, 0x400108c6 +.set CYREG_B0_P4_U1_CFG7, 0x400108c7 +.set CYREG_B0_P4_U1_CFG8, 0x400108c8 +.set CYREG_B0_P4_U1_CFG9, 0x400108c9 +.set CYREG_B0_P4_U1_CFG10, 0x400108ca +.set CYREG_B0_P4_U1_CFG11, 0x400108cb +.set CYREG_B0_P4_U1_CFG12, 0x400108cc +.set CYREG_B0_P4_U1_CFG13, 0x400108cd +.set CYREG_B0_P4_U1_CFG14, 0x400108ce +.set CYREG_B0_P4_U1_CFG15, 0x400108cf +.set CYREG_B0_P4_U1_CFG16, 0x400108d0 +.set CYREG_B0_P4_U1_CFG17, 0x400108d1 +.set CYREG_B0_P4_U1_CFG18, 0x400108d2 +.set CYREG_B0_P4_U1_CFG19, 0x400108d3 +.set CYREG_B0_P4_U1_CFG20, 0x400108d4 +.set CYREG_B0_P4_U1_CFG21, 0x400108d5 +.set CYREG_B0_P4_U1_CFG22, 0x400108d6 +.set CYREG_B0_P4_U1_CFG23, 0x400108d7 +.set CYREG_B0_P4_U1_CFG24, 0x400108d8 +.set CYREG_B0_P4_U1_CFG25, 0x400108d9 +.set CYREG_B0_P4_U1_CFG26, 0x400108da +.set CYREG_B0_P4_U1_CFG27, 0x400108db +.set CYREG_B0_P4_U1_CFG28, 0x400108dc +.set CYREG_B0_P4_U1_CFG29, 0x400108dd +.set CYREG_B0_P4_U1_CFG30, 0x400108de +.set CYREG_B0_P4_U1_CFG31, 0x400108df +.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYREG_B0_P4_U1_DCFG5, 0x400108ea +.set CYREG_B0_P4_U1_DCFG6, 0x400108ec +.set CYREG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYREG_B0_P5_U0_CFG0, 0x40010a40 +.set CYREG_B0_P5_U0_CFG1, 0x40010a41 +.set CYREG_B0_P5_U0_CFG2, 0x40010a42 +.set CYREG_B0_P5_U0_CFG3, 0x40010a43 +.set CYREG_B0_P5_U0_CFG4, 0x40010a44 +.set CYREG_B0_P5_U0_CFG5, 0x40010a45 +.set CYREG_B0_P5_U0_CFG6, 0x40010a46 +.set CYREG_B0_P5_U0_CFG7, 0x40010a47 +.set CYREG_B0_P5_U0_CFG8, 0x40010a48 +.set CYREG_B0_P5_U0_CFG9, 0x40010a49 +.set CYREG_B0_P5_U0_CFG10, 0x40010a4a +.set CYREG_B0_P5_U0_CFG11, 0x40010a4b +.set CYREG_B0_P5_U0_CFG12, 0x40010a4c +.set CYREG_B0_P5_U0_CFG13, 0x40010a4d +.set CYREG_B0_P5_U0_CFG14, 0x40010a4e +.set CYREG_B0_P5_U0_CFG15, 0x40010a4f +.set CYREG_B0_P5_U0_CFG16, 0x40010a50 +.set CYREG_B0_P5_U0_CFG17, 0x40010a51 +.set CYREG_B0_P5_U0_CFG18, 0x40010a52 +.set CYREG_B0_P5_U0_CFG19, 0x40010a53 +.set CYREG_B0_P5_U0_CFG20, 0x40010a54 +.set CYREG_B0_P5_U0_CFG21, 0x40010a55 +.set CYREG_B0_P5_U0_CFG22, 0x40010a56 +.set CYREG_B0_P5_U0_CFG23, 0x40010a57 +.set CYREG_B0_P5_U0_CFG24, 0x40010a58 +.set CYREG_B0_P5_U0_CFG25, 0x40010a59 +.set CYREG_B0_P5_U0_CFG26, 0x40010a5a +.set CYREG_B0_P5_U0_CFG27, 0x40010a5b +.set CYREG_B0_P5_U0_CFG28, 0x40010a5c +.set CYREG_B0_P5_U0_CFG29, 0x40010a5d +.set CYREG_B0_P5_U0_CFG30, 0x40010a5e +.set CYREG_B0_P5_U0_CFG31, 0x40010a5f +.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYREG_B0_P5_U1_CFG10, 0x40010aca +.set CYREG_B0_P5_U1_CFG11, 0x40010acb +.set CYREG_B0_P5_U1_CFG12, 0x40010acc +.set CYREG_B0_P5_U1_CFG13, 0x40010acd +.set CYREG_B0_P5_U1_CFG14, 0x40010ace +.set CYREG_B0_P5_U1_CFG15, 0x40010acf +.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYREG_B0_P5_U1_CFG26, 0x40010ada +.set CYREG_B0_P5_U1_CFG27, 0x40010adb +.set CYREG_B0_P5_U1_CFG28, 0x40010adc +.set CYREG_B0_P5_U1_CFG29, 0x40010add +.set CYREG_B0_P5_U1_CFG30, 0x40010ade +.set CYREG_B0_P5_U1_CFG31, 0x40010adf +.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYREG_B0_P5_U1_DCFG5, 0x40010aea +.set CYREG_B0_P5_U1_DCFG6, 0x40010aec +.set CYREG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYREG_B0_P6_U0_CFG0, 0x40010c40 +.set CYREG_B0_P6_U0_CFG1, 0x40010c41 +.set CYREG_B0_P6_U0_CFG2, 0x40010c42 +.set CYREG_B0_P6_U0_CFG3, 0x40010c43 +.set CYREG_B0_P6_U0_CFG4, 0x40010c44 +.set CYREG_B0_P6_U0_CFG5, 0x40010c45 +.set CYREG_B0_P6_U0_CFG6, 0x40010c46 +.set CYREG_B0_P6_U0_CFG7, 0x40010c47 +.set CYREG_B0_P6_U0_CFG8, 0x40010c48 +.set CYREG_B0_P6_U0_CFG9, 0x40010c49 +.set CYREG_B0_P6_U0_CFG10, 0x40010c4a +.set CYREG_B0_P6_U0_CFG11, 0x40010c4b +.set CYREG_B0_P6_U0_CFG12, 0x40010c4c +.set CYREG_B0_P6_U0_CFG13, 0x40010c4d +.set CYREG_B0_P6_U0_CFG14, 0x40010c4e +.set CYREG_B0_P6_U0_CFG15, 0x40010c4f +.set CYREG_B0_P6_U0_CFG16, 0x40010c50 +.set CYREG_B0_P6_U0_CFG17, 0x40010c51 +.set CYREG_B0_P6_U0_CFG18, 0x40010c52 +.set CYREG_B0_P6_U0_CFG19, 0x40010c53 +.set CYREG_B0_P6_U0_CFG20, 0x40010c54 +.set CYREG_B0_P6_U0_CFG21, 0x40010c55 +.set CYREG_B0_P6_U0_CFG22, 0x40010c56 +.set CYREG_B0_P6_U0_CFG23, 0x40010c57 +.set CYREG_B0_P6_U0_CFG24, 0x40010c58 +.set CYREG_B0_P6_U0_CFG25, 0x40010c59 +.set CYREG_B0_P6_U0_CFG26, 0x40010c5a +.set CYREG_B0_P6_U0_CFG27, 0x40010c5b +.set CYREG_B0_P6_U0_CFG28, 0x40010c5c +.set CYREG_B0_P6_U0_CFG29, 0x40010c5d +.set CYREG_B0_P6_U0_CFG30, 0x40010c5e +.set CYREG_B0_P6_U0_CFG31, 0x40010c5f +.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYREG_B0_P6_U1_CFG10, 0x40010cca +.set CYREG_B0_P6_U1_CFG11, 0x40010ccb +.set CYREG_B0_P6_U1_CFG12, 0x40010ccc +.set CYREG_B0_P6_U1_CFG13, 0x40010ccd +.set CYREG_B0_P6_U1_CFG14, 0x40010cce +.set CYREG_B0_P6_U1_CFG15, 0x40010ccf +.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYREG_B0_P6_U1_CFG26, 0x40010cda +.set CYREG_B0_P6_U1_CFG27, 0x40010cdb +.set CYREG_B0_P6_U1_CFG28, 0x40010cdc +.set CYREG_B0_P6_U1_CFG29, 0x40010cdd +.set CYREG_B0_P6_U1_CFG30, 0x40010cde +.set CYREG_B0_P6_U1_CFG31, 0x40010cdf +.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYREG_B0_P6_U1_DCFG5, 0x40010cea +.set CYREG_B0_P6_U1_DCFG6, 0x40010cec +.set CYREG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYREG_B0_P7_U0_CFG0, 0x40010e40 +.set CYREG_B0_P7_U0_CFG1, 0x40010e41 +.set CYREG_B0_P7_U0_CFG2, 0x40010e42 +.set CYREG_B0_P7_U0_CFG3, 0x40010e43 +.set CYREG_B0_P7_U0_CFG4, 0x40010e44 +.set CYREG_B0_P7_U0_CFG5, 0x40010e45 +.set CYREG_B0_P7_U0_CFG6, 0x40010e46 +.set CYREG_B0_P7_U0_CFG7, 0x40010e47 +.set CYREG_B0_P7_U0_CFG8, 0x40010e48 +.set CYREG_B0_P7_U0_CFG9, 0x40010e49 +.set CYREG_B0_P7_U0_CFG10, 0x40010e4a +.set CYREG_B0_P7_U0_CFG11, 0x40010e4b +.set CYREG_B0_P7_U0_CFG12, 0x40010e4c +.set CYREG_B0_P7_U0_CFG13, 0x40010e4d +.set CYREG_B0_P7_U0_CFG14, 0x40010e4e +.set CYREG_B0_P7_U0_CFG15, 0x40010e4f +.set CYREG_B0_P7_U0_CFG16, 0x40010e50 +.set CYREG_B0_P7_U0_CFG17, 0x40010e51 +.set CYREG_B0_P7_U0_CFG18, 0x40010e52 +.set CYREG_B0_P7_U0_CFG19, 0x40010e53 +.set CYREG_B0_P7_U0_CFG20, 0x40010e54 +.set CYREG_B0_P7_U0_CFG21, 0x40010e55 +.set CYREG_B0_P7_U0_CFG22, 0x40010e56 +.set CYREG_B0_P7_U0_CFG23, 0x40010e57 +.set CYREG_B0_P7_U0_CFG24, 0x40010e58 +.set CYREG_B0_P7_U0_CFG25, 0x40010e59 +.set CYREG_B0_P7_U0_CFG26, 0x40010e5a +.set CYREG_B0_P7_U0_CFG27, 0x40010e5b +.set CYREG_B0_P7_U0_CFG28, 0x40010e5c +.set CYREG_B0_P7_U0_CFG29, 0x40010e5d +.set CYREG_B0_P7_U0_CFG30, 0x40010e5e +.set CYREG_B0_P7_U0_CFG31, 0x40010e5f +.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYREG_B0_P7_U1_CFG10, 0x40010eca +.set CYREG_B0_P7_U1_CFG11, 0x40010ecb +.set CYREG_B0_P7_U1_CFG12, 0x40010ecc +.set CYREG_B0_P7_U1_CFG13, 0x40010ecd +.set CYREG_B0_P7_U1_CFG14, 0x40010ece +.set CYREG_B0_P7_U1_CFG15, 0x40010ecf +.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYREG_B0_P7_U1_CFG26, 0x40010eda +.set CYREG_B0_P7_U1_CFG27, 0x40010edb +.set CYREG_B0_P7_U1_CFG28, 0x40010edc +.set CYREG_B0_P7_U1_CFG29, 0x40010edd +.set CYREG_B0_P7_U1_CFG30, 0x40010ede +.set CYREG_B0_P7_U1_CFG31, 0x40010edf +.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYREG_B0_P7_U1_DCFG5, 0x40010eea +.set CYREG_B0_P7_U1_DCFG6, 0x40010eec +.set CYREG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYREG_B1_P2_U0_CFG0, 0x40011440 +.set CYREG_B1_P2_U0_CFG1, 0x40011441 +.set CYREG_B1_P2_U0_CFG2, 0x40011442 +.set CYREG_B1_P2_U0_CFG3, 0x40011443 +.set CYREG_B1_P2_U0_CFG4, 0x40011444 +.set CYREG_B1_P2_U0_CFG5, 0x40011445 +.set CYREG_B1_P2_U0_CFG6, 0x40011446 +.set CYREG_B1_P2_U0_CFG7, 0x40011447 +.set CYREG_B1_P2_U0_CFG8, 0x40011448 +.set CYREG_B1_P2_U0_CFG9, 0x40011449 +.set CYREG_B1_P2_U0_CFG10, 0x4001144a +.set CYREG_B1_P2_U0_CFG11, 0x4001144b +.set CYREG_B1_P2_U0_CFG12, 0x4001144c +.set CYREG_B1_P2_U0_CFG13, 0x4001144d +.set CYREG_B1_P2_U0_CFG14, 0x4001144e +.set CYREG_B1_P2_U0_CFG15, 0x4001144f +.set CYREG_B1_P2_U0_CFG16, 0x40011450 +.set CYREG_B1_P2_U0_CFG17, 0x40011451 +.set CYREG_B1_P2_U0_CFG18, 0x40011452 +.set CYREG_B1_P2_U0_CFG19, 0x40011453 +.set CYREG_B1_P2_U0_CFG20, 0x40011454 +.set CYREG_B1_P2_U0_CFG21, 0x40011455 +.set CYREG_B1_P2_U0_CFG22, 0x40011456 +.set CYREG_B1_P2_U0_CFG23, 0x40011457 +.set CYREG_B1_P2_U0_CFG24, 0x40011458 +.set CYREG_B1_P2_U0_CFG25, 0x40011459 +.set CYREG_B1_P2_U0_CFG26, 0x4001145a +.set CYREG_B1_P2_U0_CFG27, 0x4001145b +.set CYREG_B1_P2_U0_CFG28, 0x4001145c +.set CYREG_B1_P2_U0_CFG29, 0x4001145d +.set CYREG_B1_P2_U0_CFG30, 0x4001145e +.set CYREG_B1_P2_U0_CFG31, 0x4001145f +.set CYREG_B1_P2_U0_DCFG0, 0x40011460 +.set CYREG_B1_P2_U0_DCFG1, 0x40011462 +.set CYREG_B1_P2_U0_DCFG2, 0x40011464 +.set CYREG_B1_P2_U0_DCFG3, 0x40011466 +.set CYREG_B1_P2_U0_DCFG4, 0x40011468 +.set CYREG_B1_P2_U0_DCFG5, 0x4001146a +.set CYREG_B1_P2_U0_DCFG6, 0x4001146c +.set CYREG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYREG_B1_P2_U1_CFG0, 0x400114c0 +.set CYREG_B1_P2_U1_CFG1, 0x400114c1 +.set CYREG_B1_P2_U1_CFG2, 0x400114c2 +.set CYREG_B1_P2_U1_CFG3, 0x400114c3 +.set CYREG_B1_P2_U1_CFG4, 0x400114c4 +.set CYREG_B1_P2_U1_CFG5, 0x400114c5 +.set CYREG_B1_P2_U1_CFG6, 0x400114c6 +.set CYREG_B1_P2_U1_CFG7, 0x400114c7 +.set CYREG_B1_P2_U1_CFG8, 0x400114c8 +.set CYREG_B1_P2_U1_CFG9, 0x400114c9 +.set CYREG_B1_P2_U1_CFG10, 0x400114ca +.set CYREG_B1_P2_U1_CFG11, 0x400114cb +.set CYREG_B1_P2_U1_CFG12, 0x400114cc +.set CYREG_B1_P2_U1_CFG13, 0x400114cd +.set CYREG_B1_P2_U1_CFG14, 0x400114ce +.set CYREG_B1_P2_U1_CFG15, 0x400114cf +.set CYREG_B1_P2_U1_CFG16, 0x400114d0 +.set CYREG_B1_P2_U1_CFG17, 0x400114d1 +.set CYREG_B1_P2_U1_CFG18, 0x400114d2 +.set CYREG_B1_P2_U1_CFG19, 0x400114d3 +.set CYREG_B1_P2_U1_CFG20, 0x400114d4 +.set CYREG_B1_P2_U1_CFG21, 0x400114d5 +.set CYREG_B1_P2_U1_CFG22, 0x400114d6 +.set CYREG_B1_P2_U1_CFG23, 0x400114d7 +.set CYREG_B1_P2_U1_CFG24, 0x400114d8 +.set CYREG_B1_P2_U1_CFG25, 0x400114d9 +.set CYREG_B1_P2_U1_CFG26, 0x400114da +.set CYREG_B1_P2_U1_CFG27, 0x400114db +.set CYREG_B1_P2_U1_CFG28, 0x400114dc +.set CYREG_B1_P2_U1_CFG29, 0x400114dd +.set CYREG_B1_P2_U1_CFG30, 0x400114de +.set CYREG_B1_P2_U1_CFG31, 0x400114df +.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYREG_B1_P2_U1_DCFG5, 0x400114ea +.set CYREG_B1_P2_U1_DCFG6, 0x400114ec +.set CYREG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYREG_B1_P3_U0_CFG0, 0x40011640 +.set CYREG_B1_P3_U0_CFG1, 0x40011641 +.set CYREG_B1_P3_U0_CFG2, 0x40011642 +.set CYREG_B1_P3_U0_CFG3, 0x40011643 +.set CYREG_B1_P3_U0_CFG4, 0x40011644 +.set CYREG_B1_P3_U0_CFG5, 0x40011645 +.set CYREG_B1_P3_U0_CFG6, 0x40011646 +.set CYREG_B1_P3_U0_CFG7, 0x40011647 +.set CYREG_B1_P3_U0_CFG8, 0x40011648 +.set CYREG_B1_P3_U0_CFG9, 0x40011649 +.set CYREG_B1_P3_U0_CFG10, 0x4001164a +.set CYREG_B1_P3_U0_CFG11, 0x4001164b +.set CYREG_B1_P3_U0_CFG12, 0x4001164c +.set CYREG_B1_P3_U0_CFG13, 0x4001164d +.set CYREG_B1_P3_U0_CFG14, 0x4001164e +.set CYREG_B1_P3_U0_CFG15, 0x4001164f +.set CYREG_B1_P3_U0_CFG16, 0x40011650 +.set CYREG_B1_P3_U0_CFG17, 0x40011651 +.set CYREG_B1_P3_U0_CFG18, 0x40011652 +.set CYREG_B1_P3_U0_CFG19, 0x40011653 +.set CYREG_B1_P3_U0_CFG20, 0x40011654 +.set CYREG_B1_P3_U0_CFG21, 0x40011655 +.set CYREG_B1_P3_U0_CFG22, 0x40011656 +.set CYREG_B1_P3_U0_CFG23, 0x40011657 +.set CYREG_B1_P3_U0_CFG24, 0x40011658 +.set CYREG_B1_P3_U0_CFG25, 0x40011659 +.set CYREG_B1_P3_U0_CFG26, 0x4001165a +.set CYREG_B1_P3_U0_CFG27, 0x4001165b +.set CYREG_B1_P3_U0_CFG28, 0x4001165c +.set CYREG_B1_P3_U0_CFG29, 0x4001165d +.set CYREG_B1_P3_U0_CFG30, 0x4001165e +.set CYREG_B1_P3_U0_CFG31, 0x4001165f +.set CYREG_B1_P3_U0_DCFG0, 0x40011660 +.set CYREG_B1_P3_U0_DCFG1, 0x40011662 +.set CYREG_B1_P3_U0_DCFG2, 0x40011664 +.set CYREG_B1_P3_U0_DCFG3, 0x40011666 +.set CYREG_B1_P3_U0_DCFG4, 0x40011668 +.set CYREG_B1_P3_U0_DCFG5, 0x4001166a +.set CYREG_B1_P3_U0_DCFG6, 0x4001166c +.set CYREG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYREG_B1_P3_U1_CFG0, 0x400116c0 +.set CYREG_B1_P3_U1_CFG1, 0x400116c1 +.set CYREG_B1_P3_U1_CFG2, 0x400116c2 +.set CYREG_B1_P3_U1_CFG3, 0x400116c3 +.set CYREG_B1_P3_U1_CFG4, 0x400116c4 +.set CYREG_B1_P3_U1_CFG5, 0x400116c5 +.set CYREG_B1_P3_U1_CFG6, 0x400116c6 +.set CYREG_B1_P3_U1_CFG7, 0x400116c7 +.set CYREG_B1_P3_U1_CFG8, 0x400116c8 +.set CYREG_B1_P3_U1_CFG9, 0x400116c9 +.set CYREG_B1_P3_U1_CFG10, 0x400116ca +.set CYREG_B1_P3_U1_CFG11, 0x400116cb +.set CYREG_B1_P3_U1_CFG12, 0x400116cc +.set CYREG_B1_P3_U1_CFG13, 0x400116cd +.set CYREG_B1_P3_U1_CFG14, 0x400116ce +.set CYREG_B1_P3_U1_CFG15, 0x400116cf +.set CYREG_B1_P3_U1_CFG16, 0x400116d0 +.set CYREG_B1_P3_U1_CFG17, 0x400116d1 +.set CYREG_B1_P3_U1_CFG18, 0x400116d2 +.set CYREG_B1_P3_U1_CFG19, 0x400116d3 +.set CYREG_B1_P3_U1_CFG20, 0x400116d4 +.set CYREG_B1_P3_U1_CFG21, 0x400116d5 +.set CYREG_B1_P3_U1_CFG22, 0x400116d6 +.set CYREG_B1_P3_U1_CFG23, 0x400116d7 +.set CYREG_B1_P3_U1_CFG24, 0x400116d8 +.set CYREG_B1_P3_U1_CFG25, 0x400116d9 +.set CYREG_B1_P3_U1_CFG26, 0x400116da +.set CYREG_B1_P3_U1_CFG27, 0x400116db +.set CYREG_B1_P3_U1_CFG28, 0x400116dc +.set CYREG_B1_P3_U1_CFG29, 0x400116dd +.set CYREG_B1_P3_U1_CFG30, 0x400116de +.set CYREG_B1_P3_U1_CFG31, 0x400116df +.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYREG_B1_P3_U1_DCFG5, 0x400116ea +.set CYREG_B1_P3_U1_DCFG6, 0x400116ec +.set CYREG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYREG_B1_P4_U0_CFG0, 0x40011840 +.set CYREG_B1_P4_U0_CFG1, 0x40011841 +.set CYREG_B1_P4_U0_CFG2, 0x40011842 +.set CYREG_B1_P4_U0_CFG3, 0x40011843 +.set CYREG_B1_P4_U0_CFG4, 0x40011844 +.set CYREG_B1_P4_U0_CFG5, 0x40011845 +.set CYREG_B1_P4_U0_CFG6, 0x40011846 +.set CYREG_B1_P4_U0_CFG7, 0x40011847 +.set CYREG_B1_P4_U0_CFG8, 0x40011848 +.set CYREG_B1_P4_U0_CFG9, 0x40011849 +.set CYREG_B1_P4_U0_CFG10, 0x4001184a +.set CYREG_B1_P4_U0_CFG11, 0x4001184b +.set CYREG_B1_P4_U0_CFG12, 0x4001184c +.set CYREG_B1_P4_U0_CFG13, 0x4001184d +.set CYREG_B1_P4_U0_CFG14, 0x4001184e +.set CYREG_B1_P4_U0_CFG15, 0x4001184f +.set CYREG_B1_P4_U0_CFG16, 0x40011850 +.set CYREG_B1_P4_U0_CFG17, 0x40011851 +.set CYREG_B1_P4_U0_CFG18, 0x40011852 +.set CYREG_B1_P4_U0_CFG19, 0x40011853 +.set CYREG_B1_P4_U0_CFG20, 0x40011854 +.set CYREG_B1_P4_U0_CFG21, 0x40011855 +.set CYREG_B1_P4_U0_CFG22, 0x40011856 +.set CYREG_B1_P4_U0_CFG23, 0x40011857 +.set CYREG_B1_P4_U0_CFG24, 0x40011858 +.set CYREG_B1_P4_U0_CFG25, 0x40011859 +.set CYREG_B1_P4_U0_CFG26, 0x4001185a +.set CYREG_B1_P4_U0_CFG27, 0x4001185b +.set CYREG_B1_P4_U0_CFG28, 0x4001185c +.set CYREG_B1_P4_U0_CFG29, 0x4001185d +.set CYREG_B1_P4_U0_CFG30, 0x4001185e +.set CYREG_B1_P4_U0_CFG31, 0x4001185f +.set CYREG_B1_P4_U0_DCFG0, 0x40011860 +.set CYREG_B1_P4_U0_DCFG1, 0x40011862 +.set CYREG_B1_P4_U0_DCFG2, 0x40011864 +.set CYREG_B1_P4_U0_DCFG3, 0x40011866 +.set CYREG_B1_P4_U0_DCFG4, 0x40011868 +.set CYREG_B1_P4_U0_DCFG5, 0x4001186a +.set CYREG_B1_P4_U0_DCFG6, 0x4001186c +.set CYREG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYREG_B1_P4_U1_CFG0, 0x400118c0 +.set CYREG_B1_P4_U1_CFG1, 0x400118c1 +.set CYREG_B1_P4_U1_CFG2, 0x400118c2 +.set CYREG_B1_P4_U1_CFG3, 0x400118c3 +.set CYREG_B1_P4_U1_CFG4, 0x400118c4 +.set CYREG_B1_P4_U1_CFG5, 0x400118c5 +.set CYREG_B1_P4_U1_CFG6, 0x400118c6 +.set CYREG_B1_P4_U1_CFG7, 0x400118c7 +.set CYREG_B1_P4_U1_CFG8, 0x400118c8 +.set CYREG_B1_P4_U1_CFG9, 0x400118c9 +.set CYREG_B1_P4_U1_CFG10, 0x400118ca +.set CYREG_B1_P4_U1_CFG11, 0x400118cb +.set CYREG_B1_P4_U1_CFG12, 0x400118cc +.set CYREG_B1_P4_U1_CFG13, 0x400118cd +.set CYREG_B1_P4_U1_CFG14, 0x400118ce +.set CYREG_B1_P4_U1_CFG15, 0x400118cf +.set CYREG_B1_P4_U1_CFG16, 0x400118d0 +.set CYREG_B1_P4_U1_CFG17, 0x400118d1 +.set CYREG_B1_P4_U1_CFG18, 0x400118d2 +.set CYREG_B1_P4_U1_CFG19, 0x400118d3 +.set CYREG_B1_P4_U1_CFG20, 0x400118d4 +.set CYREG_B1_P4_U1_CFG21, 0x400118d5 +.set CYREG_B1_P4_U1_CFG22, 0x400118d6 +.set CYREG_B1_P4_U1_CFG23, 0x400118d7 +.set CYREG_B1_P4_U1_CFG24, 0x400118d8 +.set CYREG_B1_P4_U1_CFG25, 0x400118d9 +.set CYREG_B1_P4_U1_CFG26, 0x400118da +.set CYREG_B1_P4_U1_CFG27, 0x400118db +.set CYREG_B1_P4_U1_CFG28, 0x400118dc +.set CYREG_B1_P4_U1_CFG29, 0x400118dd +.set CYREG_B1_P4_U1_CFG30, 0x400118de +.set CYREG_B1_P4_U1_CFG31, 0x400118df +.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYREG_B1_P4_U1_DCFG5, 0x400118ea +.set CYREG_B1_P4_U1_DCFG6, 0x400118ec +.set CYREG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYREG_B1_P5_U0_CFG0, 0x40011a40 +.set CYREG_B1_P5_U0_CFG1, 0x40011a41 +.set CYREG_B1_P5_U0_CFG2, 0x40011a42 +.set CYREG_B1_P5_U0_CFG3, 0x40011a43 +.set CYREG_B1_P5_U0_CFG4, 0x40011a44 +.set CYREG_B1_P5_U0_CFG5, 0x40011a45 +.set CYREG_B1_P5_U0_CFG6, 0x40011a46 +.set CYREG_B1_P5_U0_CFG7, 0x40011a47 +.set CYREG_B1_P5_U0_CFG8, 0x40011a48 +.set CYREG_B1_P5_U0_CFG9, 0x40011a49 +.set CYREG_B1_P5_U0_CFG10, 0x40011a4a +.set CYREG_B1_P5_U0_CFG11, 0x40011a4b +.set CYREG_B1_P5_U0_CFG12, 0x40011a4c +.set CYREG_B1_P5_U0_CFG13, 0x40011a4d +.set CYREG_B1_P5_U0_CFG14, 0x40011a4e +.set CYREG_B1_P5_U0_CFG15, 0x40011a4f +.set CYREG_B1_P5_U0_CFG16, 0x40011a50 +.set CYREG_B1_P5_U0_CFG17, 0x40011a51 +.set CYREG_B1_P5_U0_CFG18, 0x40011a52 +.set CYREG_B1_P5_U0_CFG19, 0x40011a53 +.set CYREG_B1_P5_U0_CFG20, 0x40011a54 +.set CYREG_B1_P5_U0_CFG21, 0x40011a55 +.set CYREG_B1_P5_U0_CFG22, 0x40011a56 +.set CYREG_B1_P5_U0_CFG23, 0x40011a57 +.set CYREG_B1_P5_U0_CFG24, 0x40011a58 +.set CYREG_B1_P5_U0_CFG25, 0x40011a59 +.set CYREG_B1_P5_U0_CFG26, 0x40011a5a +.set CYREG_B1_P5_U0_CFG27, 0x40011a5b +.set CYREG_B1_P5_U0_CFG28, 0x40011a5c +.set CYREG_B1_P5_U0_CFG29, 0x40011a5d +.set CYREG_B1_P5_U0_CFG30, 0x40011a5e +.set CYREG_B1_P5_U0_CFG31, 0x40011a5f +.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYREG_B1_P5_U1_CFG10, 0x40011aca +.set CYREG_B1_P5_U1_CFG11, 0x40011acb +.set CYREG_B1_P5_U1_CFG12, 0x40011acc +.set CYREG_B1_P5_U1_CFG13, 0x40011acd +.set CYREG_B1_P5_U1_CFG14, 0x40011ace +.set CYREG_B1_P5_U1_CFG15, 0x40011acf +.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYREG_B1_P5_U1_CFG26, 0x40011ada +.set CYREG_B1_P5_U1_CFG27, 0x40011adb +.set CYREG_B1_P5_U1_CFG28, 0x40011adc +.set CYREG_B1_P5_U1_CFG29, 0x40011add +.set CYREG_B1_P5_U1_CFG30, 0x40011ade +.set CYREG_B1_P5_U1_CFG31, 0x40011adf +.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYREG_B1_P5_U1_DCFG5, 0x40011aea +.set CYREG_B1_P5_U1_DCFG6, 0x40011aec +.set CYREG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYREG_BCTL0_MDCLK_EN, 0x40015000 +.set CYREG_BCTL0_MBCLK_EN, 0x40015001 +.set CYREG_BCTL0_WAIT_CFG, 0x40015002 +.set CYREG_BCTL0_BANK_CTL, 0x40015003 +.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYREG_BCTL0_DCLK_EN0, 0x40015008 +.set CYREG_BCTL0_BCLK_EN0, 0x40015009 +.set CYREG_BCTL0_DCLK_EN1, 0x4001500a +.set CYREG_BCTL0_BCLK_EN1, 0x4001500b +.set CYREG_BCTL0_DCLK_EN2, 0x4001500c +.set CYREG_BCTL0_BCLK_EN2, 0x4001500d +.set CYREG_BCTL0_DCLK_EN3, 0x4001500e +.set CYREG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYREG_BCTL1_MDCLK_EN, 0x40015010 +.set CYREG_BCTL1_MBCLK_EN, 0x40015011 +.set CYREG_BCTL1_WAIT_CFG, 0x40015012 +.set CYREG_BCTL1_BANK_CTL, 0x40015013 +.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYREG_BCTL1_DCLK_EN0, 0x40015018 +.set CYREG_BCTL1_BCLK_EN0, 0x40015019 +.set CYREG_BCTL1_DCLK_EN1, 0x4001501a +.set CYREG_BCTL1_BCLK_EN1, 0x4001501b +.set CYREG_BCTL1_DCLK_EN2, 0x4001501c +.set CYREG_BCTL1_BCLK_EN2, 0x4001501d +.set CYREG_BCTL1_DCLK_EN3, 0x4001501e +.set CYREG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 +.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 +.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 +.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 +.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 +.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 +.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 +.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 +.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 +.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 +.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 +.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 +.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 +.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 +.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYREG_SFR_GPIO0, 0x40050180 +.set CYREG_SFR_GPIRD0, 0x40050189 +.set CYREG_SFR_GPIO0_SEL, 0x4005018a +.set CYREG_SFR_GPIO1, 0x40050190 +.set CYREG_SFR_GPIRD1, 0x40050191 +.set CYREG_SFR_GPIO2, 0x40050198 +.set CYREG_SFR_GPIRD2, 0x40050199 +.set CYREG_SFR_GPIO2_SEL, 0x4005019a +.set CYREG_SFR_GPIO1_SEL, 0x400501a2 +.set CYREG_SFR_GPIO3, 0x400501b0 +.set CYREG_SFR_GPIRD3, 0x400501b1 +.set CYREG_SFR_GPIO3_SEL, 0x400501b2 +.set CYREG_SFR_GPIO4, 0x400501c0 +.set CYREG_SFR_GPIRD4, 0x400501c1 +.set CYREG_SFR_GPIO4_SEL, 0x400501c2 +.set CYREG_SFR_GPIO5, 0x400501c8 +.set CYREG_SFR_GPIRD5, 0x400501c9 +.set CYREG_SFR_GPIO5_SEL, 0x400501ca +.set CYREG_SFR_GPIO6, 0x400501d8 +.set CYREG_SFR_GPIRD6, 0x400501d9 +.set CYREG_SFR_GPIO6_SEL, 0x400501da +.set CYREG_SFR_GPIO12, 0x400501e8 +.set CYREG_SFR_GPIRD12, 0x400501e9 +.set CYREG_SFR_GPIO12_SEL, 0x400501f2 +.set CYREG_SFR_GPIO15, 0x400501f8 +.set CYREG_SFR_GPIRD15, 0x400501f9 +.set CYREG_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYREG_P3BA_Y_START, 0x40050300 +.set CYREG_P3BA_YROLL, 0x40050301 +.set CYREG_P3BA_YCFG, 0x40050302 +.set CYREG_P3BA_X_START1, 0x40050303 +.set CYREG_P3BA_X_START2, 0x40050304 +.set CYREG_P3BA_XROLL1, 0x40050305 +.set CYREG_P3BA_XROLL2, 0x40050306 +.set CYREG_P3BA_XINC, 0x40050307 +.set CYREG_P3BA_XCFG, 0x40050308 +.set CYREG_P3BA_OFFSETADDR1, 0x40050309 +.set CYREG_P3BA_OFFSETADDR2, 0x4005030a +.set CYREG_P3BA_OFFSETADDR3, 0x4005030b +.set CYREG_P3BA_ABSADDR1, 0x4005030c +.set CYREG_P3BA_ABSADDR2, 0x4005030d +.set CYREG_P3BA_ABSADDR3, 0x4005030e +.set CYREG_P3BA_ABSADDR4, 0x4005030f +.set CYREG_P3BA_DATCFG1, 0x40050310 +.set CYREG_P3BA_DATCFG2, 0x40050311 +.set CYREG_P3BA_CMP_RSLT1, 0x40050314 +.set CYREG_P3BA_CMP_RSLT2, 0x40050315 +.set CYREG_P3BA_CMP_RSLT3, 0x40050316 +.set CYREG_P3BA_CMP_RSLT4, 0x40050317 +.set CYREG_P3BA_DATA_REG1, 0x40050318 +.set CYREG_P3BA_DATA_REG2, 0x40050319 +.set CYREG_P3BA_DATA_REG3, 0x4005031a +.set CYREG_P3BA_DATA_REG4, 0x4005031b +.set CYREG_P3BA_EXP_DATA1, 0x4005031c +.set CYREG_P3BA_EXP_DATA2, 0x4005031d +.set CYREG_P3BA_EXP_DATA3, 0x4005031e +.set CYREG_P3BA_EXP_DATA4, 0x4005031f +.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYREG_P3BA_BIST_EN, 0x40050324 +.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYREG_P3BA_SEQCFG1, 0x40050326 +.set CYREG_P3BA_SEQCFG2, 0x40050327 +.set CYREG_P3BA_Y_CURR, 0x40050328 +.set CYREG_P3BA_X_CURR1, 0x40050329 +.set CYREG_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 +.set CYREG_PANTHER_WAITPIPE, 0x40080004 +.set CYREG_PANTHER_TRACE_CFG, 0x40080008 +.set CYREG_PANTHER_DBG_CFG, 0x4008000c +.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYREG_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYREG_FLSECC_DATA_MBASE, 0x48000000 +.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 +.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 +.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYREG_ITM_TRACE_EN, 0xe0000e00 +.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 +.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYREG_ITM_PID4, 0xe0000fd0 +.set CYREG_ITM_PID5, 0xe0000fd4 +.set CYREG_ITM_PID6, 0xe0000fd8 +.set CYREG_ITM_PID7, 0xe0000fdc +.set CYREG_ITM_PID0, 0xe0000fe0 +.set CYREG_ITM_PID1, 0xe0000fe4 +.set CYREG_ITM_PID2, 0xe0000fe8 +.set CYREG_ITM_PID3, 0xe0000fec +.set CYREG_ITM_CID0, 0xe0000ff0 +.set CYREG_ITM_CID1, 0xe0000ff4 +.set CYREG_ITM_CID2, 0xe0000ff8 +.set CYREG_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYREG_DWT_CTRL, 0xe0001000 +.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 +.set CYREG_DWT_CPI_COUNT, 0xe0001008 +.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 +.set CYREG_DWT_LSU_COUNT, 0xe0001014 +.set CYREG_DWT_FOLD_COUNT, 0xe0001018 +.set CYREG_DWT_PC_SAMPLE, 0xe000101c +.set CYREG_DWT_COMP_0, 0xe0001020 +.set CYREG_DWT_MASK_0, 0xe0001024 +.set CYREG_DWT_FUNCTION_0, 0xe0001028 +.set CYREG_DWT_COMP_1, 0xe0001030 +.set CYREG_DWT_MASK_1, 0xe0001034 +.set CYREG_DWT_FUNCTION_1, 0xe0001038 +.set CYREG_DWT_COMP_2, 0xe0001040 +.set CYREG_DWT_MASK_2, 0xe0001044 +.set CYREG_DWT_FUNCTION_2, 0xe0001048 +.set CYREG_DWT_COMP_3, 0xe0001050 +.set CYREG_DWT_MASK_3, 0xe0001054 +.set CYREG_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYREG_FPB_CTRL, 0xe0002000 +.set CYREG_FPB_REMAP, 0xe0002004 +.set CYREG_FPB_FP_COMP_0, 0xe0002008 +.set CYREG_FPB_FP_COMP_1, 0xe000200c +.set CYREG_FPB_FP_COMP_2, 0xe0002010 +.set CYREG_FPB_FP_COMP_3, 0xe0002014 +.set CYREG_FPB_FP_COMP_4, 0xe0002018 +.set CYREG_FPB_FP_COMP_5, 0xe000201c +.set CYREG_FPB_FP_COMP_6, 0xe0002020 +.set CYREG_FPB_FP_COMP_7, 0xe0002024 +.set CYREG_FPB_PID4, 0xe0002fd0 +.set CYREG_FPB_PID5, 0xe0002fd4 +.set CYREG_FPB_PID6, 0xe0002fd8 +.set CYREG_FPB_PID7, 0xe0002fdc +.set CYREG_FPB_PID0, 0xe0002fe0 +.set CYREG_FPB_PID1, 0xe0002fe4 +.set CYREG_FPB_PID2, 0xe0002fe8 +.set CYREG_FPB_PID3, 0xe0002fec +.set CYREG_FPB_CID0, 0xe0002ff0 +.set CYREG_FPB_CID1, 0xe0002ff4 +.set CYREG_FPB_CID2, 0xe0002ff8 +.set CYREG_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYREG_NVIC_SETENA0, 0xe000e100 +.set CYREG_NVIC_CLRENA0, 0xe000e180 +.set CYREG_NVIC_SETPEND0, 0xe000e200 +.set CYREG_NVIC_CLRPEND0, 0xe000e280 +.set CYREG_NVIC_ACTIVE0, 0xe000e300 +.set CYREG_NVIC_PRI_0, 0xe000e400 +.set CYREG_NVIC_PRI_1, 0xe000e401 +.set CYREG_NVIC_PRI_2, 0xe000e402 +.set CYREG_NVIC_PRI_3, 0xe000e403 +.set CYREG_NVIC_PRI_4, 0xe000e404 +.set CYREG_NVIC_PRI_5, 0xe000e405 +.set CYREG_NVIC_PRI_6, 0xe000e406 +.set CYREG_NVIC_PRI_7, 0xe000e407 +.set CYREG_NVIC_PRI_8, 0xe000e408 +.set CYREG_NVIC_PRI_9, 0xe000e409 +.set CYREG_NVIC_PRI_10, 0xe000e40a +.set CYREG_NVIC_PRI_11, 0xe000e40b +.set CYREG_NVIC_PRI_12, 0xe000e40c +.set CYREG_NVIC_PRI_13, 0xe000e40d +.set CYREG_NVIC_PRI_14, 0xe000e40e +.set CYREG_NVIC_PRI_15, 0xe000e40f +.set CYREG_NVIC_PRI_16, 0xe000e410 +.set CYREG_NVIC_PRI_17, 0xe000e411 +.set CYREG_NVIC_PRI_18, 0xe000e412 +.set CYREG_NVIC_PRI_19, 0xe000e413 +.set CYREG_NVIC_PRI_20, 0xe000e414 +.set CYREG_NVIC_PRI_21, 0xe000e415 +.set CYREG_NVIC_PRI_22, 0xe000e416 +.set CYREG_NVIC_PRI_23, 0xe000e417 +.set CYREG_NVIC_PRI_24, 0xe000e418 +.set CYREG_NVIC_PRI_25, 0xe000e419 +.set CYREG_NVIC_PRI_26, 0xe000e41a +.set CYREG_NVIC_PRI_27, 0xe000e41b +.set CYREG_NVIC_PRI_28, 0xe000e41c +.set CYREG_NVIC_PRI_29, 0xe000e41d +.set CYREG_NVIC_PRI_30, 0xe000e41e +.set CYREG_NVIC_PRI_31, 0xe000e41f +.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 +.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c +.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYREG_TPIU_PROTOCOL, 0xe00400f0 +.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYREG_TPIU_TRIGGER, 0xe0040ee8 +.set CYREG_TPIU_ITETMDATA, 0xe0040eec +.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYREG_TPIU_ITITMDATA, 0xe0040efc +.set CYREG_TPIU_ITCTRL, 0xe0040f00 +.set CYREG_TPIU_DEVID, 0xe0040fc8 +.set CYREG_TPIU_DEVTYPE, 0xe0040fcc +.set CYREG_TPIU_PID4, 0xe0040fd0 +.set CYREG_TPIU_PID5, 0xe0040fd4 +.set CYREG_TPIU_PID6, 0xe0040fd8 +.set CYREG_TPIU_PID7, 0xe0040fdc +.set CYREG_TPIU_PID0, 0xe0040fe0 +.set CYREG_TPIU_PID1, 0xe0040fe4 +.set CYREG_TPIU_PID2, 0xe0040fe8 +.set CYREG_TPIU_PID3, 0xe0040fec +.set CYREG_TPIU_CID0, 0xe0040ff0 +.set CYREG_TPIU_CID1, 0xe0040ff4 +.set CYREG_TPIU_CID2, 0xe0040ff8 +.set CYREG_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYREG_ETM_CTL, 0xe0041000 +.set CYREG_ETM_CFG_CODE, 0xe0041004 +.set CYREG_ETM_TRIG_EVENT, 0xe0041008 +.set CYREG_ETM_STATUS, 0xe0041010 +.set CYREG_ETM_SYS_CFG, 0xe0041014 +.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 +.set CYREG_ETM_ETM_ID, 0xe00411e4 +.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 +.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYREG_ETM_PDSR, 0xe0041314 +.set CYREG_ETM_ITMISCIN, 0xe0041ee0 +.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 +.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 +.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYREG_ETM_DEV_TYPE, 0xe0041fcc +.set CYREG_ETM_PID4, 0xe0041fd0 +.set CYREG_ETM_PID5, 0xe0041fd4 +.set CYREG_ETM_PID6, 0xe0041fd8 +.set CYREG_ETM_PID7, 0xe0041fdc +.set CYREG_ETM_PID0, 0xe0041fe0 +.set CYREG_ETM_PID1, 0xe0041fe4 +.set CYREG_ETM_PID2, 0xe0041fe8 +.set CYREG_ETM_PID3, 0xe0041fec +.set CYREG_ETM_CID0, 0xe0041ff0 +.set CYREG_ETM_CID1, 0xe0041ff4 +.set CYREG_ETM_CID2, 0xe0041ff8 +.set CYREG_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 +.set CYREG_ROM_TABLE_DWT, 0xe00ff004 +.set CYREG_ROM_TABLE_FPB, 0xe00ff008 +.set CYREG_ROM_TABLE_ITM, 0xe00ff00c +.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 +.set CYREG_ROM_TABLE_ETM, 0xe00ff014 +.set CYREG_ROM_TABLE_END, 0xe00ff018 +.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 +.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 +.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 +.set CYREG_ROM_TABLE_PID7, 0xe00fffdc +.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 +.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 +.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 +.set CYREG_ROM_TABLE_PID3, 0xe00fffec +.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 +.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 +.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 +.set CYREG_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc new file mode 100644 index 0000000..147a861 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -0,0 +1,5356 @@ +; +; File Name: cydeviceiar.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYDEV_FLASH_DATA_MBASE 0x00000000 +#define CYDEV_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000 +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000 +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000 +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA_MBASE 0x20000000 +#define CYDEV_SRAM_DATA_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000 +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000 +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000 +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000 +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000 +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000 +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000 +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000 +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000 +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000 +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000 +#define CYDEV_DMA_SRAM_MBASE 0x2000f000 +#define CYDEV_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYDEV_CLKDIST_CR 0x40004000 +#define CYDEV_CLKDIST_LD 0x40004001 +#define CYDEV_CLKDIST_WRK0 0x40004002 +#define CYDEV_CLKDIST_WRK1 0x40004003 +#define CYDEV_CLKDIST_MSTR0 0x40004004 +#define CYDEV_CLKDIST_MSTR1 0x40004005 +#define CYDEV_CLKDIST_BCFG0 0x40004006 +#define CYDEV_CLKDIST_BCFG1 0x40004007 +#define CYDEV_CLKDIST_BCFG2 0x40004008 +#define CYDEV_CLKDIST_UCFG 0x40004009 +#define CYDEV_CLKDIST_DLY0 0x4000400a +#define CYDEV_CLKDIST_DLY1 0x4000400b +#define CYDEV_CLKDIST_DMASK 0x40004010 +#define CYDEV_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYDEV_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210 +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220 +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221 +#define CYDEV_FASTCLK_PLL_P 0x40004222 +#define CYDEV_FASTCLK_PLL_Q 0x40004223 +#define CYDEV_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300 +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYDEV_SLOWCLK_X32_CR 0x40004308 +#define CYDEV_SLOWCLK_X32_CFG 0x40004309 +#define CYDEV_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYDEV_BOOST_CR0 0x40004320 +#define CYDEV_BOOST_CR1 0x40004321 +#define CYDEV_BOOST_CR2 0x40004322 +#define CYDEV_BOOST_CR3 0x40004323 +#define CYDEV_BOOST_SR 0x40004324 +#define CYDEV_BOOST_CR4 0x40004325 +#define CYDEV_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYDEV_PWRSYS_CR0 0x40004330 +#define CYDEV_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYDEV_PM_TW_CFG0 0x40004380 +#define CYDEV_PM_TW_CFG1 0x40004381 +#define CYDEV_PM_TW_CFG2 0x40004382 +#define CYDEV_PM_WDT_CFG 0x40004383 +#define CYDEV_PM_WDT_CR 0x40004384 +#define CYDEV_PM_INT_SR 0x40004390 +#define CYDEV_PM_MODE_CFG0 0x40004391 +#define CYDEV_PM_MODE_CFG1 0x40004392 +#define CYDEV_PM_MODE_CSR 0x40004393 +#define CYDEV_PM_USB_CR0 0x40004394 +#define CYDEV_PM_WAKEUP_CFG0 0x40004398 +#define CYDEV_PM_WAKEUP_CFG1 0x40004399 +#define CYDEV_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYDEV_PM_ACT_CFG0 0x400043a0 +#define CYDEV_PM_ACT_CFG1 0x400043a1 +#define CYDEV_PM_ACT_CFG2 0x400043a2 +#define CYDEV_PM_ACT_CFG3 0x400043a3 +#define CYDEV_PM_ACT_CFG4 0x400043a4 +#define CYDEV_PM_ACT_CFG5 0x400043a5 +#define CYDEV_PM_ACT_CFG6 0x400043a6 +#define CYDEV_PM_ACT_CFG7 0x400043a7 +#define CYDEV_PM_ACT_CFG8 0x400043a8 +#define CYDEV_PM_ACT_CFG9 0x400043a9 +#define CYDEV_PM_ACT_CFG10 0x400043aa +#define CYDEV_PM_ACT_CFG11 0x400043ab +#define CYDEV_PM_ACT_CFG12 0x400043ac +#define CYDEV_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYDEV_PM_STBY_CFG0 0x400043b0 +#define CYDEV_PM_STBY_CFG1 0x400043b1 +#define CYDEV_PM_STBY_CFG2 0x400043b2 +#define CYDEV_PM_STBY_CFG3 0x400043b3 +#define CYDEV_PM_STBY_CFG4 0x400043b4 +#define CYDEV_PM_STBY_CFG5 0x400043b5 +#define CYDEV_PM_STBY_CFG6 0x400043b6 +#define CYDEV_PM_STBY_CFG7 0x400043b7 +#define CYDEV_PM_STBY_CFG8 0x400043b8 +#define CYDEV_PM_STBY_CFG9 0x400043b9 +#define CYDEV_PM_STBY_CFG10 0x400043ba +#define CYDEV_PM_STBY_CFG11 0x400043bb +#define CYDEV_PM_STBY_CFG12 0x400043bc +#define CYDEV_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYDEV_PM_AVAIL_CR0 0x400043c0 +#define CYDEV_PM_AVAIL_CR1 0x400043c1 +#define CYDEV_PM_AVAIL_CR2 0x400043c2 +#define CYDEV_PM_AVAIL_CR3 0x400043c3 +#define CYDEV_PM_AVAIL_CR4 0x400043c4 +#define CYDEV_PM_AVAIL_CR5 0x400043c5 +#define CYDEV_PM_AVAIL_CR6 0x400043c6 +#define CYDEV_PM_AVAIL_SR0 0x400043d0 +#define CYDEV_PM_AVAIL_SR1 0x400043d1 +#define CYDEV_PM_AVAIL_SR2 0x400043d2 +#define CYDEV_PM_AVAIL_SR3 0x400043d3 +#define CYDEV_PM_AVAIL_SR4 0x400043d4 +#define CYDEV_PM_AVAIL_SR5 0x400043d5 +#define CYDEV_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681 +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682 +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683 +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686 +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687 +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYDEV_MFGCFG_ILO_TR0 0x40004690 +#define CYDEV_MFGCFG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYDEV_MFGCFG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0 +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1 +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2 +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3 +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8 +#define CYDEV_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYDEV_RESET_IPOR_CR0 0x400046f0 +#define CYDEV_RESET_IPOR_CR1 0x400046f1 +#define CYDEV_RESET_IPOR_CR2 0x400046f2 +#define CYDEV_RESET_IPOR_CR3 0x400046f3 +#define CYDEV_RESET_CR0 0x400046f4 +#define CYDEV_RESET_CR1 0x400046f5 +#define CYDEV_RESET_CR2 0x400046f6 +#define CYDEV_RESET_CR3 0x400046f7 +#define CYDEV_RESET_CR4 0x400046f8 +#define CYDEV_RESET_CR5 0x400046f9 +#define CYDEV_RESET_SR0 0x400046fa +#define CYDEV_RESET_SR1 0x400046fb +#define CYDEV_RESET_SR2 0x400046fc +#define CYDEV_RESET_SR3 0x400046fd +#define CYDEV_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYDEV_SPC_FM_EE_CR 0x40004700 +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYDEV_SPC_EE_SCR 0x40004702 +#define CYDEV_SPC_EE_ERR 0x40004703 +#define CYDEV_SPC_CPU_DATA 0x40004720 +#define CYDEV_SPC_DMA_DATA 0x40004721 +#define CYDEV_SPC_SR 0x40004722 +#define CYDEV_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYDEV_CACHE_CC_CTL 0x40004800 +#define CYDEV_CACHE_ECC_CORR 0x40004880 +#define CYDEV_CACHE_ECC_ERR 0x40004888 +#define CYDEV_CACHE_FLASH_ERR 0x40004890 +#define CYDEV_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYDEV_I2C_XCFG 0x400049c8 +#define CYDEV_I2C_ADR 0x400049ca +#define CYDEV_I2C_CFG 0x400049d6 +#define CYDEV_I2C_CSR 0x400049d7 +#define CYDEV_I2C_D 0x400049d8 +#define CYDEV_I2C_MCSR 0x400049d9 +#define CYDEV_I2C_CLK_DIV1 0x400049db +#define CYDEV_I2C_CLK_DIV2 0x400049dc +#define CYDEV_I2C_TMOUT_CSR 0x400049dd +#define CYDEV_I2C_TMOUT_SR 0x400049de +#define CYDEV_I2C_TMOUT_CFG0 0x400049df +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYDEV_DEC_CR 0x40004e00 +#define CYDEV_DEC_SR 0x40004e01 +#define CYDEV_DEC_SHIFT1 0x40004e02 +#define CYDEV_DEC_SHIFT2 0x40004e03 +#define CYDEV_DEC_DR2 0x40004e04 +#define CYDEV_DEC_DR2H 0x40004e05 +#define CYDEV_DEC_DR1 0x40004e06 +#define CYDEV_DEC_OCOR 0x40004e08 +#define CYDEV_DEC_OCORM 0x40004e09 +#define CYDEV_DEC_OCORH 0x40004e0a +#define CYDEV_DEC_GCOR 0x40004e0c +#define CYDEV_DEC_GCORH 0x40004e0d +#define CYDEV_DEC_GVAL 0x40004e0e +#define CYDEV_DEC_OUTSAMP 0x40004e10 +#define CYDEV_DEC_OUTSAMPM 0x40004e11 +#define CYDEV_DEC_OUTSAMPH 0x40004e12 +#define CYDEV_DEC_OUTSAMPS 0x40004e13 +#define CYDEV_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYDEV_TMR0_CFG0 0x40004f00 +#define CYDEV_TMR0_CFG1 0x40004f01 +#define CYDEV_TMR0_CFG2 0x40004f02 +#define CYDEV_TMR0_SR0 0x40004f03 +#define CYDEV_TMR0_PER0 0x40004f04 +#define CYDEV_TMR0_PER1 0x40004f05 +#define CYDEV_TMR0_CNT_CMP0 0x40004f06 +#define CYDEV_TMR0_CNT_CMP1 0x40004f07 +#define CYDEV_TMR0_CAP0 0x40004f08 +#define CYDEV_TMR0_CAP1 0x40004f09 +#define CYDEV_TMR0_RT0 0x40004f0a +#define CYDEV_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYDEV_TMR1_CFG0 0x40004f0c +#define CYDEV_TMR1_CFG1 0x40004f0d +#define CYDEV_TMR1_CFG2 0x40004f0e +#define CYDEV_TMR1_SR0 0x40004f0f +#define CYDEV_TMR1_PER0 0x40004f10 +#define CYDEV_TMR1_PER1 0x40004f11 +#define CYDEV_TMR1_CNT_CMP0 0x40004f12 +#define CYDEV_TMR1_CNT_CMP1 0x40004f13 +#define CYDEV_TMR1_CAP0 0x40004f14 +#define CYDEV_TMR1_CAP1 0x40004f15 +#define CYDEV_TMR1_RT0 0x40004f16 +#define CYDEV_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYDEV_TMR2_CFG0 0x40004f18 +#define CYDEV_TMR2_CFG1 0x40004f19 +#define CYDEV_TMR2_CFG2 0x40004f1a +#define CYDEV_TMR2_SR0 0x40004f1b +#define CYDEV_TMR2_PER0 0x40004f1c +#define CYDEV_TMR2_PER1 0x40004f1d +#define CYDEV_TMR2_CNT_CMP0 0x40004f1e +#define CYDEV_TMR2_CNT_CMP1 0x40004f1f +#define CYDEV_TMR2_CAP0 0x40004f20 +#define CYDEV_TMR2_CAP1 0x40004f21 +#define CYDEV_TMR2_RT0 0x40004f22 +#define CYDEV_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYDEV_TMR3_CFG0 0x40004f24 +#define CYDEV_TMR3_CFG1 0x40004f25 +#define CYDEV_TMR3_CFG2 0x40004f26 +#define CYDEV_TMR3_SR0 0x40004f27 +#define CYDEV_TMR3_PER0 0x40004f28 +#define CYDEV_TMR3_PER1 0x40004f29 +#define CYDEV_TMR3_CNT_CMP0 0x40004f2a +#define CYDEV_TMR3_CNT_CMP1 0x40004f2b +#define CYDEV_TMR3_CAP0 0x40004f2c +#define CYDEV_TMR3_CAP1 0x40004f2d +#define CYDEV_TMR3_RT0 0x40004f2e +#define CYDEV_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT0_PC0 0x40005000 +#define CYDEV_IO_PC_PRT0_PC1 0x40005001 +#define CYDEV_IO_PC_PRT0_PC2 0x40005002 +#define CYDEV_IO_PC_PRT0_PC3 0x40005003 +#define CYDEV_IO_PC_PRT0_PC4 0x40005004 +#define CYDEV_IO_PC_PRT0_PC5 0x40005005 +#define CYDEV_IO_PC_PRT0_PC6 0x40005006 +#define CYDEV_IO_PC_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT1_PC0 0x40005008 +#define CYDEV_IO_PC_PRT1_PC1 0x40005009 +#define CYDEV_IO_PC_PRT1_PC2 0x4000500a +#define CYDEV_IO_PC_PRT1_PC3 0x4000500b +#define CYDEV_IO_PC_PRT1_PC4 0x4000500c +#define CYDEV_IO_PC_PRT1_PC5 0x4000500d +#define CYDEV_IO_PC_PRT1_PC6 0x4000500e +#define CYDEV_IO_PC_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT2_PC0 0x40005010 +#define CYDEV_IO_PC_PRT2_PC1 0x40005011 +#define CYDEV_IO_PC_PRT2_PC2 0x40005012 +#define CYDEV_IO_PC_PRT2_PC3 0x40005013 +#define CYDEV_IO_PC_PRT2_PC4 0x40005014 +#define CYDEV_IO_PC_PRT2_PC5 0x40005015 +#define CYDEV_IO_PC_PRT2_PC6 0x40005016 +#define CYDEV_IO_PC_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT3_PC0 0x40005018 +#define CYDEV_IO_PC_PRT3_PC1 0x40005019 +#define CYDEV_IO_PC_PRT3_PC2 0x4000501a +#define CYDEV_IO_PC_PRT3_PC3 0x4000501b +#define CYDEV_IO_PC_PRT3_PC4 0x4000501c +#define CYDEV_IO_PC_PRT3_PC5 0x4000501d +#define CYDEV_IO_PC_PRT3_PC6 0x4000501e +#define CYDEV_IO_PC_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT4_PC0 0x40005020 +#define CYDEV_IO_PC_PRT4_PC1 0x40005021 +#define CYDEV_IO_PC_PRT4_PC2 0x40005022 +#define CYDEV_IO_PC_PRT4_PC3 0x40005023 +#define CYDEV_IO_PC_PRT4_PC4 0x40005024 +#define CYDEV_IO_PC_PRT4_PC5 0x40005025 +#define CYDEV_IO_PC_PRT4_PC6 0x40005026 +#define CYDEV_IO_PC_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT5_PC0 0x40005028 +#define CYDEV_IO_PC_PRT5_PC1 0x40005029 +#define CYDEV_IO_PC_PRT5_PC2 0x4000502a +#define CYDEV_IO_PC_PRT5_PC3 0x4000502b +#define CYDEV_IO_PC_PRT5_PC4 0x4000502c +#define CYDEV_IO_PC_PRT5_PC5 0x4000502d +#define CYDEV_IO_PC_PRT5_PC6 0x4000502e +#define CYDEV_IO_PC_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT6_PC0 0x40005030 +#define CYDEV_IO_PC_PRT6_PC1 0x40005031 +#define CYDEV_IO_PC_PRT6_PC2 0x40005032 +#define CYDEV_IO_PC_PRT6_PC3 0x40005033 +#define CYDEV_IO_PC_PRT6_PC4 0x40005034 +#define CYDEV_IO_PC_PRT6_PC5 0x40005035 +#define CYDEV_IO_PC_PRT6_PC6 0x40005036 +#define CYDEV_IO_PC_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT12_PC0 0x40005060 +#define CYDEV_IO_PC_PRT12_PC1 0x40005061 +#define CYDEV_IO_PC_PRT12_PC2 0x40005062 +#define CYDEV_IO_PC_PRT12_PC3 0x40005063 +#define CYDEV_IO_PC_PRT12_PC4 0x40005064 +#define CYDEV_IO_PC_PRT12_PC5 0x40005065 +#define CYDEV_IO_PC_PRT12_PC6 0x40005066 +#define CYDEV_IO_PC_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYDEV_IO_PC_PRT15_PC0 0x40005078 +#define CYDEV_IO_PC_PRT15_PC1 0x40005079 +#define CYDEV_IO_PC_PRT15_PC2 0x4000507a +#define CYDEV_IO_PC_PRT15_PC3 0x4000507b +#define CYDEV_IO_PC_PRT15_PC4 0x4000507c +#define CYDEV_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT0_DR 0x40005100 +#define CYDEV_IO_PRT_PRT0_PS 0x40005101 +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102 +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103 +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104 +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105 +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106 +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107 +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108 +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109 +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c +#define CYDEV_IO_PRT_PRT0_AG 0x4000510d +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT1_DR 0x40005110 +#define CYDEV_IO_PRT_PRT1_PS 0x40005111 +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112 +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113 +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114 +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115 +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116 +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117 +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118 +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119 +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c +#define CYDEV_IO_PRT_PRT1_AG 0x4000511d +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT2_DR 0x40005120 +#define CYDEV_IO_PRT_PRT2_PS 0x40005121 +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122 +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123 +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124 +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125 +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126 +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127 +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128 +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129 +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c +#define CYDEV_IO_PRT_PRT2_AG 0x4000512d +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT3_DR 0x40005130 +#define CYDEV_IO_PRT_PRT3_PS 0x40005131 +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132 +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133 +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134 +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135 +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136 +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137 +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138 +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139 +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c +#define CYDEV_IO_PRT_PRT3_AG 0x4000513d +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT4_DR 0x40005140 +#define CYDEV_IO_PRT_PRT4_PS 0x40005141 +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142 +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143 +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144 +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145 +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146 +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147 +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148 +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149 +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c +#define CYDEV_IO_PRT_PRT4_AG 0x4000514d +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT5_DR 0x40005150 +#define CYDEV_IO_PRT_PRT5_PS 0x40005151 +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152 +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153 +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154 +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155 +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156 +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157 +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158 +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159 +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c +#define CYDEV_IO_PRT_PRT5_AG 0x4000515d +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT6_DR 0x40005160 +#define CYDEV_IO_PRT_PRT6_PS 0x40005161 +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162 +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163 +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164 +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165 +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166 +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167 +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168 +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169 +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c +#define CYDEV_IO_PRT_PRT6_AG 0x4000516d +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0 +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1 +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2 +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3 +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4 +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5 +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6 +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7 +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8 +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9 +#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYDEV_IO_PRT_PRT12_AG 0x400051cd +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0 +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1 +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2 +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3 +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4 +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5 +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6 +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7 +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8 +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9 +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc +#define CYDEV_IO_PRT_PRT15_AG 0x400051fd +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200 +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201 +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202 +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203 +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204 +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205 +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208 +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209 +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210 +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211 +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212 +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213 +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214 +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215 +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218 +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219 +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220 +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221 +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222 +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223 +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224 +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225 +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228 +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229 +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230 +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231 +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232 +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233 +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234 +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235 +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260 +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261 +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262 +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263 +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264 +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278 +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279 +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYDEV_EMIF_NO_UDB 0x40005400 +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401 +#define CYDEV_EMIF_MEM_DWN 0x40005402 +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403 +#define CYDEV_EMIF_CLOCK_EN 0x40005404 +#define CYDEV_EMIF_EM_TYPE 0x40005405 +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801 +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805 +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809 +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821 +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825 +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829 +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881 +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882 +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883 +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884 +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885 +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886 +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887 +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888 +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889 +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890 +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891 +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892 +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893 +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894 +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895 +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896 +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897 +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898 +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899 +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901 +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902 +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903 +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904 +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905 +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909 +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02 +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03 +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04 +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06 +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07 +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08 +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12 +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13 +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14 +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16 +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17 +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18 +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22 +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23 +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24 +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26 +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27 +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28 +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32 +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33 +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34 +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36 +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37 +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38 +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82 +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83 +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84 +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92 +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93 +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94 +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2 +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3 +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4 +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6 +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2 +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3 +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4 +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6 +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02 +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03 +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04 +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06 +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22 +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23 +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24 +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26 +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51 +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52 +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53 +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60 +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91 +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92 +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93 +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99 +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYDEV_USB_EP0_DR0 0x40006000 +#define CYDEV_USB_EP0_DR1 0x40006001 +#define CYDEV_USB_EP0_DR2 0x40006002 +#define CYDEV_USB_EP0_DR3 0x40006003 +#define CYDEV_USB_EP0_DR4 0x40006004 +#define CYDEV_USB_EP0_DR5 0x40006005 +#define CYDEV_USB_EP0_DR6 0x40006006 +#define CYDEV_USB_EP0_DR7 0x40006007 +#define CYDEV_USB_CR0 0x40006008 +#define CYDEV_USB_CR1 0x40006009 +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d +#define CYDEV_USB_SIE_EP1_CR0 0x4000600e +#define CYDEV_USB_USBIO_CR0 0x40006010 +#define CYDEV_USB_USBIO_CR1 0x40006012 +#define CYDEV_USB_DYN_RECONFIG 0x40006014 +#define CYDEV_USB_SOF0 0x40006018 +#define CYDEV_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d +#define CYDEV_USB_SIE_EP2_CR0 0x4000601e +#define CYDEV_USB_EP0_CR 0x40006028 +#define CYDEV_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d +#define CYDEV_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d +#define CYDEV_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d +#define CYDEV_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d +#define CYDEV_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d +#define CYDEV_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d +#define CYDEV_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP1_CFG 0x40006080 +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081 +#define CYDEV_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW1_WA 0x40006084 +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYDEV_USB_ARB_RW1_RA 0x40006086 +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYDEV_USB_ARB_RW1_DR 0x40006088 +#define CYDEV_USB_BUF_SIZE 0x4000608c +#define CYDEV_USB_EP_ACTIVE 0x4000608e +#define CYDEV_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP2_CFG 0x40006090 +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091 +#define CYDEV_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW2_WA 0x40006094 +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYDEV_USB_ARB_RW2_RA 0x40006096 +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYDEV_USB_ARB_RW2_DR 0x40006098 +#define CYDEV_USB_ARB_CFG 0x4000609c +#define CYDEV_USB_USB_CLK_EN 0x4000609d +#define CYDEV_USB_ARB_INT_EN 0x4000609e +#define CYDEV_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0 +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYDEV_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW3_WA 0x400060a4 +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYDEV_USB_ARB_RW3_RA 0x400060a6 +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYDEV_USB_ARB_RW3_DR 0x400060a8 +#define CYDEV_USB_CWA 0x400060ac +#define CYDEV_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0 +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYDEV_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW4_WA 0x400060b4 +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYDEV_USB_ARB_RW4_RA 0x400060b6 +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYDEV_USB_ARB_RW4_DR 0x400060b8 +#define CYDEV_USB_DMA_THRES 0x400060bc +#define CYDEV_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0 +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYDEV_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW5_WA 0x400060c4 +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYDEV_USB_ARB_RW5_RA 0x400060c6 +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYDEV_USB_ARB_RW5_DR 0x400060c8 +#define CYDEV_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0 +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYDEV_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW6_WA 0x400060d4 +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYDEV_USB_ARB_RW6_RA 0x400060d6 +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYDEV_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0 +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYDEV_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW7_WA 0x400060e4 +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYDEV_USB_ARB_RW7_RA 0x400060e6 +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYDEV_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0 +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYDEV_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW8_WA 0x400060f4 +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYDEV_USB_ARB_RW8_RA 0x400060f6 +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYDEV_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100 +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470 +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471 +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472 +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473 +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474 +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475 +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476 +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477 +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478 +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479 +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574 +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575 +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576 +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577 +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578 +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579 +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYDEV_PHUB_CFG 0x40007000 +#define CYDEV_PHUB_ERR 0x40007004 +#define CYDEV_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYDEV_PHUB_CH0_ACTION 0x40007014 +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYDEV_PHUB_CH1_ACTION 0x40007024 +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYDEV_PHUB_CH2_ACTION 0x40007034 +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYDEV_PHUB_CH3_ACTION 0x40007044 +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYDEV_PHUB_CH4_ACTION 0x40007054 +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYDEV_PHUB_CH5_ACTION 0x40007064 +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYDEV_PHUB_CH6_ACTION 0x40007074 +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYDEV_PHUB_CH7_ACTION 0x40007084 +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYDEV_PHUB_CH8_ACTION 0x40007094 +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYDEV_PHUB_CH9_ACTION 0x400070a4 +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYDEV_PHUB_CH10_ACTION 0x400070b4 +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYDEV_PHUB_CH11_ACTION 0x400070c4 +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYDEV_PHUB_CH12_ACTION 0x400070d4 +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYDEV_PHUB_CH13_ACTION 0x400070e4 +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYDEV_PHUB_CH14_ACTION 0x400070f4 +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYDEV_PHUB_CH15_ACTION 0x40007104 +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYDEV_PHUB_CH16_ACTION 0x40007114 +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYDEV_PHUB_CH17_ACTION 0x40007124 +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYDEV_PHUB_CH18_ACTION 0x40007134 +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYDEV_PHUB_CH19_ACTION 0x40007144 +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYDEV_PHUB_CH20_ACTION 0x40007154 +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYDEV_PHUB_CH21_ACTION 0x40007164 +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYDEV_PHUB_CH22_ACTION 0x40007174 +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYDEV_PHUB_CH23_ACTION 0x40007184 +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYDEV_EE_DATA_MBASE 0x40008000 +#define CYDEV_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000 +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004 +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008 +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c +#define CYDEV_CAN0_CSR_CMD 0x4000a010 +#define CYDEV_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYDEV_CAN0_TX0_CMD 0x4000a020 +#define CYDEV_CAN0_TX0_ID 0x4000a024 +#define CYDEV_CAN0_TX0_DH 0x4000a028 +#define CYDEV_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYDEV_CAN0_TX1_CMD 0x4000a030 +#define CYDEV_CAN0_TX1_ID 0x4000a034 +#define CYDEV_CAN0_TX1_DH 0x4000a038 +#define CYDEV_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYDEV_CAN0_TX2_CMD 0x4000a040 +#define CYDEV_CAN0_TX2_ID 0x4000a044 +#define CYDEV_CAN0_TX2_DH 0x4000a048 +#define CYDEV_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYDEV_CAN0_TX3_CMD 0x4000a050 +#define CYDEV_CAN0_TX3_ID 0x4000a054 +#define CYDEV_CAN0_TX3_DH 0x4000a058 +#define CYDEV_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYDEV_CAN0_TX4_CMD 0x4000a060 +#define CYDEV_CAN0_TX4_ID 0x4000a064 +#define CYDEV_CAN0_TX4_DH 0x4000a068 +#define CYDEV_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYDEV_CAN0_TX5_CMD 0x4000a070 +#define CYDEV_CAN0_TX5_ID 0x4000a074 +#define CYDEV_CAN0_TX5_DH 0x4000a078 +#define CYDEV_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYDEV_CAN0_TX6_CMD 0x4000a080 +#define CYDEV_CAN0_TX6_ID 0x4000a084 +#define CYDEV_CAN0_TX6_DH 0x4000a088 +#define CYDEV_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYDEV_CAN0_TX7_CMD 0x4000a090 +#define CYDEV_CAN0_TX7_ID 0x4000a094 +#define CYDEV_CAN0_TX7_DH 0x4000a098 +#define CYDEV_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0 +#define CYDEV_CAN0_RX0_ID 0x4000a0a4 +#define CYDEV_CAN0_RX0_DH 0x4000a0a8 +#define CYDEV_CAN0_RX0_DL 0x4000a0ac +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0 +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4 +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8 +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0 +#define CYDEV_CAN0_RX1_ID 0x4000a0c4 +#define CYDEV_CAN0_RX1_DH 0x4000a0c8 +#define CYDEV_CAN0_RX1_DL 0x4000a0cc +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0 +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4 +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8 +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0 +#define CYDEV_CAN0_RX2_ID 0x4000a0e4 +#define CYDEV_CAN0_RX2_DH 0x4000a0e8 +#define CYDEV_CAN0_RX2_DL 0x4000a0ec +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0 +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4 +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8 +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYDEV_CAN0_RX3_CMD 0x4000a100 +#define CYDEV_CAN0_RX3_ID 0x4000a104 +#define CYDEV_CAN0_RX3_DH 0x4000a108 +#define CYDEV_CAN0_RX3_DL 0x4000a10c +#define CYDEV_CAN0_RX3_AMR 0x4000a110 +#define CYDEV_CAN0_RX3_ACR 0x4000a114 +#define CYDEV_CAN0_RX3_AMRD 0x4000a118 +#define CYDEV_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYDEV_CAN0_RX4_CMD 0x4000a120 +#define CYDEV_CAN0_RX4_ID 0x4000a124 +#define CYDEV_CAN0_RX4_DH 0x4000a128 +#define CYDEV_CAN0_RX4_DL 0x4000a12c +#define CYDEV_CAN0_RX4_AMR 0x4000a130 +#define CYDEV_CAN0_RX4_ACR 0x4000a134 +#define CYDEV_CAN0_RX4_AMRD 0x4000a138 +#define CYDEV_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYDEV_CAN0_RX5_CMD 0x4000a140 +#define CYDEV_CAN0_RX5_ID 0x4000a144 +#define CYDEV_CAN0_RX5_DH 0x4000a148 +#define CYDEV_CAN0_RX5_DL 0x4000a14c +#define CYDEV_CAN0_RX5_AMR 0x4000a150 +#define CYDEV_CAN0_RX5_ACR 0x4000a154 +#define CYDEV_CAN0_RX5_AMRD 0x4000a158 +#define CYDEV_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYDEV_CAN0_RX6_CMD 0x4000a160 +#define CYDEV_CAN0_RX6_ID 0x4000a164 +#define CYDEV_CAN0_RX6_DH 0x4000a168 +#define CYDEV_CAN0_RX6_DL 0x4000a16c +#define CYDEV_CAN0_RX6_AMR 0x4000a170 +#define CYDEV_CAN0_RX6_ACR 0x4000a174 +#define CYDEV_CAN0_RX6_AMRD 0x4000a178 +#define CYDEV_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYDEV_CAN0_RX7_CMD 0x4000a180 +#define CYDEV_CAN0_RX7_ID 0x4000a184 +#define CYDEV_CAN0_RX7_DH 0x4000a188 +#define CYDEV_CAN0_RX7_DL 0x4000a18c +#define CYDEV_CAN0_RX7_AMR 0x4000a190 +#define CYDEV_CAN0_RX7_ACR 0x4000a194 +#define CYDEV_CAN0_RX7_AMRD 0x4000a198 +#define CYDEV_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0 +#define CYDEV_CAN0_RX8_ID 0x4000a1a4 +#define CYDEV_CAN0_RX8_DH 0x4000a1a8 +#define CYDEV_CAN0_RX8_DL 0x4000a1ac +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0 +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4 +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8 +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0 +#define CYDEV_CAN0_RX9_ID 0x4000a1c4 +#define CYDEV_CAN0_RX9_DH 0x4000a1c8 +#define CYDEV_CAN0_RX9_DL 0x4000a1cc +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0 +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4 +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8 +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0 +#define CYDEV_CAN0_RX10_ID 0x4000a1e4 +#define CYDEV_CAN0_RX10_DH 0x4000a1e8 +#define CYDEV_CAN0_RX10_DL 0x4000a1ec +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0 +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4 +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8 +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYDEV_CAN0_RX11_CMD 0x4000a200 +#define CYDEV_CAN0_RX11_ID 0x4000a204 +#define CYDEV_CAN0_RX11_DH 0x4000a208 +#define CYDEV_CAN0_RX11_DL 0x4000a20c +#define CYDEV_CAN0_RX11_AMR 0x4000a210 +#define CYDEV_CAN0_RX11_ACR 0x4000a214 +#define CYDEV_CAN0_RX11_AMRD 0x4000a218 +#define CYDEV_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYDEV_CAN0_RX12_CMD 0x4000a220 +#define CYDEV_CAN0_RX12_ID 0x4000a224 +#define CYDEV_CAN0_RX12_DH 0x4000a228 +#define CYDEV_CAN0_RX12_DL 0x4000a22c +#define CYDEV_CAN0_RX12_AMR 0x4000a230 +#define CYDEV_CAN0_RX12_ACR 0x4000a234 +#define CYDEV_CAN0_RX12_AMRD 0x4000a238 +#define CYDEV_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYDEV_CAN0_RX13_CMD 0x4000a240 +#define CYDEV_CAN0_RX13_ID 0x4000a244 +#define CYDEV_CAN0_RX13_DH 0x4000a248 +#define CYDEV_CAN0_RX13_DL 0x4000a24c +#define CYDEV_CAN0_RX13_AMR 0x4000a250 +#define CYDEV_CAN0_RX13_ACR 0x4000a254 +#define CYDEV_CAN0_RX13_AMRD 0x4000a258 +#define CYDEV_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYDEV_CAN0_RX14_CMD 0x4000a260 +#define CYDEV_CAN0_RX14_ID 0x4000a264 +#define CYDEV_CAN0_RX14_DH 0x4000a268 +#define CYDEV_CAN0_RX14_DL 0x4000a26c +#define CYDEV_CAN0_RX14_AMR 0x4000a270 +#define CYDEV_CAN0_RX14_ACR 0x4000a274 +#define CYDEV_CAN0_RX14_AMRD 0x4000a278 +#define CYDEV_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYDEV_CAN0_RX15_CMD 0x4000a280 +#define CYDEV_CAN0_RX15_ID 0x4000a284 +#define CYDEV_CAN0_RX15_DH 0x4000a288 +#define CYDEV_CAN0_RX15_DL 0x4000a28c +#define CYDEV_CAN0_RX15_AMR 0x4000a290 +#define CYDEV_CAN0_RX15_ACR 0x4000a294 +#define CYDEV_CAN0_RX15_AMRD 0x4000a298 +#define CYDEV_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYDEV_DFB0_CR 0x4000c780 +#define CYDEV_DFB0_SR 0x4000c784 +#define CYDEV_DFB0_RAM_EN 0x4000c788 +#define CYDEV_DFB0_RAM_DIR 0x4000c78c +#define CYDEV_DFB0_SEMA 0x4000c790 +#define CYDEV_DFB0_DSI_CTRL 0x4000c794 +#define CYDEV_DFB0_INT_CTRL 0x4000c798 +#define CYDEV_DFB0_DMA_CTRL 0x4000c79c +#define CYDEV_DFB0_STAGEA 0x4000c7a0 +#define CYDEV_DFB0_STAGEAM 0x4000c7a1 +#define CYDEV_DFB0_STAGEAH 0x4000c7a2 +#define CYDEV_DFB0_STAGEB 0x4000c7a4 +#define CYDEV_DFB0_STAGEBM 0x4000c7a5 +#define CYDEV_DFB0_STAGEBH 0x4000c7a6 +#define CYDEV_DFB0_HOLDA 0x4000c7a8 +#define CYDEV_DFB0_HOLDAM 0x4000c7a9 +#define CYDEV_DFB0_HOLDAH 0x4000c7aa +#define CYDEV_DFB0_HOLDAS 0x4000c7ab +#define CYDEV_DFB0_HOLDB 0x4000c7ac +#define CYDEV_DFB0_HOLDBM 0x4000c7ad +#define CYDEV_DFB0_HOLDBH 0x4000c7ae +#define CYDEV_DFB0_HOLDBS 0x4000c7af +#define CYDEV_DFB0_COHER 0x4000c7b0 +#define CYDEV_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040 +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041 +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042 +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043 +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044 +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045 +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046 +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047 +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048 +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049 +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050 +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051 +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052 +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053 +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054 +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055 +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056 +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057 +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058 +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059 +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060 +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062 +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064 +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066 +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068 +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0 +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1 +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2 +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3 +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4 +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5 +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6 +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7 +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8 +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9 +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0 +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1 +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2 +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3 +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4 +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5 +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6 +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7 +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8 +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9 +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0 +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2 +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4 +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6 +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8 +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240 +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241 +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242 +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243 +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244 +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245 +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246 +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247 +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248 +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249 +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250 +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251 +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252 +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253 +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254 +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255 +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256 +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257 +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258 +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259 +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260 +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262 +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264 +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266 +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268 +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0 +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1 +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2 +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3 +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4 +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5 +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6 +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7 +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8 +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9 +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0 +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1 +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2 +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3 +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4 +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5 +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6 +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7 +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8 +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9 +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0 +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2 +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4 +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6 +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8 +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440 +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441 +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442 +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443 +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444 +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445 +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446 +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447 +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448 +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449 +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450 +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451 +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452 +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453 +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454 +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455 +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456 +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457 +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458 +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459 +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460 +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462 +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464 +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466 +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468 +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0 +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1 +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2 +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3 +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4 +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5 +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6 +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7 +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8 +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9 +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0 +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1 +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2 +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3 +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4 +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5 +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6 +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7 +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8 +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9 +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0 +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2 +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4 +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6 +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8 +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640 +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641 +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642 +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643 +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644 +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645 +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646 +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647 +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648 +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649 +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650 +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651 +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652 +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653 +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654 +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655 +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656 +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657 +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658 +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659 +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660 +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662 +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664 +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666 +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668 +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0 +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1 +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2 +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3 +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4 +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5 +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6 +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7 +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8 +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9 +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0 +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1 +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2 +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3 +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4 +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5 +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6 +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7 +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8 +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9 +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0 +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2 +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4 +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6 +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8 +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840 +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841 +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842 +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843 +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844 +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845 +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846 +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847 +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848 +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849 +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850 +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851 +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852 +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853 +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854 +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855 +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856 +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857 +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858 +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859 +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860 +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862 +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864 +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866 +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868 +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0 +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1 +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2 +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3 +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4 +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5 +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6 +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7 +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8 +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9 +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0 +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1 +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2 +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3 +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4 +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5 +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6 +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7 +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8 +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9 +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0 +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2 +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4 +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6 +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8 +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40 +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41 +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42 +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43 +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44 +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45 +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46 +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47 +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48 +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49 +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50 +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51 +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52 +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53 +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54 +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55 +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56 +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57 +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58 +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59 +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60 +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62 +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64 +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66 +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68 +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0 +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1 +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2 +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3 +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4 +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5 +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6 +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7 +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8 +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9 +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0 +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1 +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2 +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3 +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4 +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5 +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6 +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7 +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8 +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9 +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40 +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41 +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42 +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43 +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44 +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45 +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46 +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47 +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48 +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49 +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50 +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51 +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52 +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53 +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54 +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55 +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56 +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57 +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58 +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59 +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60 +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62 +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64 +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66 +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68 +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0 +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1 +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2 +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3 +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4 +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5 +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6 +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7 +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8 +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9 +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0 +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1 +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2 +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3 +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4 +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5 +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6 +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7 +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8 +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9 +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40 +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41 +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42 +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43 +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44 +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45 +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46 +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47 +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48 +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49 +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50 +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51 +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52 +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53 +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54 +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55 +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56 +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57 +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58 +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59 +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60 +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62 +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64 +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66 +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68 +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0 +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1 +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2 +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3 +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4 +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5 +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6 +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7 +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8 +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9 +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0 +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1 +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2 +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3 +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4 +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5 +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6 +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7 +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8 +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9 +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440 +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441 +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442 +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443 +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444 +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445 +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446 +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447 +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448 +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449 +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450 +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451 +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452 +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453 +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454 +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455 +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456 +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457 +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458 +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459 +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460 +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462 +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464 +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466 +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468 +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0 +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1 +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2 +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3 +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4 +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5 +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6 +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7 +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8 +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9 +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0 +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1 +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2 +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3 +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4 +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5 +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6 +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7 +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8 +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9 +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0 +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2 +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4 +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6 +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8 +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640 +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641 +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642 +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643 +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644 +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645 +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646 +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647 +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648 +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649 +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650 +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651 +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652 +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653 +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654 +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655 +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656 +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657 +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658 +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659 +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660 +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662 +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664 +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666 +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668 +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0 +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1 +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2 +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3 +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4 +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5 +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6 +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7 +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8 +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9 +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0 +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1 +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2 +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3 +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4 +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5 +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6 +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7 +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8 +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9 +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0 +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2 +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4 +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6 +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8 +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840 +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841 +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842 +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843 +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844 +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845 +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846 +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847 +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848 +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849 +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850 +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851 +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852 +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853 +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854 +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855 +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856 +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857 +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858 +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859 +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860 +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862 +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864 +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866 +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868 +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0 +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1 +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2 +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3 +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4 +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5 +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6 +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7 +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8 +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9 +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0 +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1 +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2 +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3 +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4 +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5 +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6 +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7 +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8 +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9 +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0 +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2 +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4 +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6 +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8 +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40 +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41 +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42 +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43 +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44 +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45 +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46 +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47 +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48 +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49 +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50 +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51 +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52 +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53 +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54 +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55 +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56 +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57 +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58 +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59 +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60 +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62 +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64 +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66 +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68 +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0 +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1 +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2 +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3 +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4 +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5 +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6 +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7 +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8 +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9 +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0 +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1 +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2 +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3 +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4 +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5 +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6 +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7 +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8 +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9 +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000 +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001 +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002 +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003 +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007 +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008 +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009 +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010 +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011 +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012 +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013 +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017 +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018 +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019 +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100 +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101 +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102 +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103 +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104 +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105 +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106 +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107 +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110 +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111 +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112 +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113 +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114 +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000 +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYDEV_SFR_GPIO0 0x40050180 +#define CYDEV_SFR_GPIRD0 0x40050189 +#define CYDEV_SFR_GPIO0_SEL 0x4005018a +#define CYDEV_SFR_GPIO1 0x40050190 +#define CYDEV_SFR_GPIRD1 0x40050191 +#define CYDEV_SFR_GPIO2 0x40050198 +#define CYDEV_SFR_GPIRD2 0x40050199 +#define CYDEV_SFR_GPIO2_SEL 0x4005019a +#define CYDEV_SFR_GPIO1_SEL 0x400501a2 +#define CYDEV_SFR_GPIO3 0x400501b0 +#define CYDEV_SFR_GPIRD3 0x400501b1 +#define CYDEV_SFR_GPIO3_SEL 0x400501b2 +#define CYDEV_SFR_GPIO4 0x400501c0 +#define CYDEV_SFR_GPIRD4 0x400501c1 +#define CYDEV_SFR_GPIO4_SEL 0x400501c2 +#define CYDEV_SFR_GPIO5 0x400501c8 +#define CYDEV_SFR_GPIRD5 0x400501c9 +#define CYDEV_SFR_GPIO5_SEL 0x400501ca +#define CYDEV_SFR_GPIO6 0x400501d8 +#define CYDEV_SFR_GPIRD6 0x400501d9 +#define CYDEV_SFR_GPIO6_SEL 0x400501da +#define CYDEV_SFR_GPIO12 0x400501e8 +#define CYDEV_SFR_GPIRD12 0x400501e9 +#define CYDEV_SFR_GPIO12_SEL 0x400501f2 +#define CYDEV_SFR_GPIO15 0x400501f8 +#define CYDEV_SFR_GPIRD15 0x400501f9 +#define CYDEV_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYDEV_P3BA_Y_START 0x40050300 +#define CYDEV_P3BA_YROLL 0x40050301 +#define CYDEV_P3BA_YCFG 0x40050302 +#define CYDEV_P3BA_X_START1 0x40050303 +#define CYDEV_P3BA_X_START2 0x40050304 +#define CYDEV_P3BA_XROLL1 0x40050305 +#define CYDEV_P3BA_XROLL2 0x40050306 +#define CYDEV_P3BA_XINC 0x40050307 +#define CYDEV_P3BA_XCFG 0x40050308 +#define CYDEV_P3BA_OFFSETADDR1 0x40050309 +#define CYDEV_P3BA_OFFSETADDR2 0x4005030a +#define CYDEV_P3BA_OFFSETADDR3 0x4005030b +#define CYDEV_P3BA_ABSADDR1 0x4005030c +#define CYDEV_P3BA_ABSADDR2 0x4005030d +#define CYDEV_P3BA_ABSADDR3 0x4005030e +#define CYDEV_P3BA_ABSADDR4 0x4005030f +#define CYDEV_P3BA_DATCFG1 0x40050310 +#define CYDEV_P3BA_DATCFG2 0x40050311 +#define CYDEV_P3BA_CMP_RSLT1 0x40050314 +#define CYDEV_P3BA_CMP_RSLT2 0x40050315 +#define CYDEV_P3BA_CMP_RSLT3 0x40050316 +#define CYDEV_P3BA_CMP_RSLT4 0x40050317 +#define CYDEV_P3BA_DATA_REG1 0x40050318 +#define CYDEV_P3BA_DATA_REG2 0x40050319 +#define CYDEV_P3BA_DATA_REG3 0x4005031a +#define CYDEV_P3BA_DATA_REG4 0x4005031b +#define CYDEV_P3BA_EXP_DATA1 0x4005031c +#define CYDEV_P3BA_EXP_DATA2 0x4005031d +#define CYDEV_P3BA_EXP_DATA3 0x4005031e +#define CYDEV_P3BA_EXP_DATA4 0x4005031f +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320 +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321 +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322 +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323 +#define CYDEV_P3BA_BIST_EN 0x40050324 +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYDEV_P3BA_SEQCFG1 0x40050326 +#define CYDEV_P3BA_SEQCFG2 0x40050327 +#define CYDEV_P3BA_Y_CURR 0x40050328 +#define CYDEV_P3BA_X_CURR1 0x40050329 +#define CYDEV_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000 +#define CYDEV_PANTHER_WAITPIPE 0x40080004 +#define CYDEV_PANTHER_TRACE_CFG 0x40080008 +#define CYDEV_PANTHER_DBG_CFG 0x4008000c +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYDEV_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYDEV_FLSECC_DATA_MBASE 0x48000000 +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000 +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000 +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYDEV_ITM_TRACE_EN 0xe0000e00 +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80 +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4 +#define CYDEV_ITM_PID4 0xe0000fd0 +#define CYDEV_ITM_PID5 0xe0000fd4 +#define CYDEV_ITM_PID6 0xe0000fd8 +#define CYDEV_ITM_PID7 0xe0000fdc +#define CYDEV_ITM_PID0 0xe0000fe0 +#define CYDEV_ITM_PID1 0xe0000fe4 +#define CYDEV_ITM_PID2 0xe0000fe8 +#define CYDEV_ITM_PID3 0xe0000fec +#define CYDEV_ITM_CID0 0xe0000ff0 +#define CYDEV_ITM_CID1 0xe0000ff4 +#define CYDEV_ITM_CID2 0xe0000ff8 +#define CYDEV_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYDEV_DWT_CTRL 0xe0001000 +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004 +#define CYDEV_DWT_CPI_COUNT 0xe0001008 +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010 +#define CYDEV_DWT_LSU_COUNT 0xe0001014 +#define CYDEV_DWT_FOLD_COUNT 0xe0001018 +#define CYDEV_DWT_PC_SAMPLE 0xe000101c +#define CYDEV_DWT_COMP_0 0xe0001020 +#define CYDEV_DWT_MASK_0 0xe0001024 +#define CYDEV_DWT_FUNCTION_0 0xe0001028 +#define CYDEV_DWT_COMP_1 0xe0001030 +#define CYDEV_DWT_MASK_1 0xe0001034 +#define CYDEV_DWT_FUNCTION_1 0xe0001038 +#define CYDEV_DWT_COMP_2 0xe0001040 +#define CYDEV_DWT_MASK_2 0xe0001044 +#define CYDEV_DWT_FUNCTION_2 0xe0001048 +#define CYDEV_DWT_COMP_3 0xe0001050 +#define CYDEV_DWT_MASK_3 0xe0001054 +#define CYDEV_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYDEV_FPB_CTRL 0xe0002000 +#define CYDEV_FPB_REMAP 0xe0002004 +#define CYDEV_FPB_FP_COMP_0 0xe0002008 +#define CYDEV_FPB_FP_COMP_1 0xe000200c +#define CYDEV_FPB_FP_COMP_2 0xe0002010 +#define CYDEV_FPB_FP_COMP_3 0xe0002014 +#define CYDEV_FPB_FP_COMP_4 0xe0002018 +#define CYDEV_FPB_FP_COMP_5 0xe000201c +#define CYDEV_FPB_FP_COMP_6 0xe0002020 +#define CYDEV_FPB_FP_COMP_7 0xe0002024 +#define CYDEV_FPB_PID4 0xe0002fd0 +#define CYDEV_FPB_PID5 0xe0002fd4 +#define CYDEV_FPB_PID6 0xe0002fd8 +#define CYDEV_FPB_PID7 0xe0002fdc +#define CYDEV_FPB_PID0 0xe0002fe0 +#define CYDEV_FPB_PID1 0xe0002fe4 +#define CYDEV_FPB_PID2 0xe0002fe8 +#define CYDEV_FPB_PID3 0xe0002fec +#define CYDEV_FPB_CID0 0xe0002ff0 +#define CYDEV_FPB_CID1 0xe0002ff4 +#define CYDEV_FPB_CID2 0xe0002ff8 +#define CYDEV_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010 +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c +#define CYDEV_NVIC_SETENA0 0xe000e100 +#define CYDEV_NVIC_CLRENA0 0xe000e180 +#define CYDEV_NVIC_SETPEND0 0xe000e200 +#define CYDEV_NVIC_CLRPEND0 0xe000e280 +#define CYDEV_NVIC_ACTIVE0 0xe000e300 +#define CYDEV_NVIC_PRI_0 0xe000e400 +#define CYDEV_NVIC_PRI_1 0xe000e401 +#define CYDEV_NVIC_PRI_2 0xe000e402 +#define CYDEV_NVIC_PRI_3 0xe000e403 +#define CYDEV_NVIC_PRI_4 0xe000e404 +#define CYDEV_NVIC_PRI_5 0xe000e405 +#define CYDEV_NVIC_PRI_6 0xe000e406 +#define CYDEV_NVIC_PRI_7 0xe000e407 +#define CYDEV_NVIC_PRI_8 0xe000e408 +#define CYDEV_NVIC_PRI_9 0xe000e409 +#define CYDEV_NVIC_PRI_10 0xe000e40a +#define CYDEV_NVIC_PRI_11 0xe000e40b +#define CYDEV_NVIC_PRI_12 0xe000e40c +#define CYDEV_NVIC_PRI_13 0xe000e40d +#define CYDEV_NVIC_PRI_14 0xe000e40e +#define CYDEV_NVIC_PRI_15 0xe000e40f +#define CYDEV_NVIC_PRI_16 0xe000e410 +#define CYDEV_NVIC_PRI_17 0xe000e411 +#define CYDEV_NVIC_PRI_18 0xe000e412 +#define CYDEV_NVIC_PRI_19 0xe000e413 +#define CYDEV_NVIC_PRI_20 0xe000e414 +#define CYDEV_NVIC_PRI_21 0xe000e415 +#define CYDEV_NVIC_PRI_22 0xe000e416 +#define CYDEV_NVIC_PRI_23 0xe000e417 +#define CYDEV_NVIC_PRI_24 0xe000e418 +#define CYDEV_NVIC_PRI_25 0xe000e419 +#define CYDEV_NVIC_PRI_26 0xe000e41a +#define CYDEV_NVIC_PRI_27 0xe000e41b +#define CYDEV_NVIC_PRI_28 0xe000e41c +#define CYDEV_NVIC_PRI_29 0xe000e41d +#define CYDEV_NVIC_PRI_30 0xe000e41e +#define CYDEV_NVIC_PRI_31 0xe000e41f +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00 +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08 +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYDEV_TPIU_PROTOCOL 0xe00400f0 +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYDEV_TPIU_TRIGGER 0xe0040ee8 +#define CYDEV_TPIU_ITETMDATA 0xe0040eec +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0 +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8 +#define CYDEV_TPIU_ITITMDATA 0xe0040efc +#define CYDEV_TPIU_ITCTRL 0xe0040f00 +#define CYDEV_TPIU_DEVID 0xe0040fc8 +#define CYDEV_TPIU_DEVTYPE 0xe0040fcc +#define CYDEV_TPIU_PID4 0xe0040fd0 +#define CYDEV_TPIU_PID5 0xe0040fd4 +#define CYDEV_TPIU_PID6 0xe0040fd8 +#define CYDEV_TPIU_PID7 0xe0040fdc +#define CYDEV_TPIU_PID0 0xe0040fe0 +#define CYDEV_TPIU_PID1 0xe0040fe4 +#define CYDEV_TPIU_PID2 0xe0040fe8 +#define CYDEV_TPIU_PID3 0xe0040fec +#define CYDEV_TPIU_CID0 0xe0040ff0 +#define CYDEV_TPIU_CID1 0xe0040ff4 +#define CYDEV_TPIU_CID2 0xe0040ff8 +#define CYDEV_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYDEV_ETM_CTL 0xe0041000 +#define CYDEV_ETM_CFG_CODE 0xe0041004 +#define CYDEV_ETM_TRIG_EVENT 0xe0041008 +#define CYDEV_ETM_STATUS 0xe0041010 +#define CYDEV_ETM_SYS_CFG 0xe0041014 +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0 +#define CYDEV_ETM_ETM_ID 0xe00411e4 +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200 +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYDEV_ETM_PDSR 0xe0041314 +#define CYDEV_ETM_ITMISCIN 0xe0041ee0 +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8 +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0 +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8 +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4 +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8 +#define CYDEV_ETM_DEV_TYPE 0xe0041fcc +#define CYDEV_ETM_PID4 0xe0041fd0 +#define CYDEV_ETM_PID5 0xe0041fd4 +#define CYDEV_ETM_PID6 0xe0041fd8 +#define CYDEV_ETM_PID7 0xe0041fdc +#define CYDEV_ETM_PID0 0xe0041fe0 +#define CYDEV_ETM_PID1 0xe0041fe4 +#define CYDEV_ETM_PID2 0xe0041fe8 +#define CYDEV_ETM_PID3 0xe0041fec +#define CYDEV_ETM_CID0 0xe0041ff0 +#define CYDEV_ETM_CID1 0xe0041ff4 +#define CYDEV_ETM_CID2 0xe0041ff8 +#define CYDEV_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000 +#define CYDEV_ROM_TABLE_DWT 0xe00ff004 +#define CYDEV_ROM_TABLE_FPB 0xe00ff008 +#define CYDEV_ROM_TABLE_ITM 0xe00ff00c +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010 +#define CYDEV_ROM_TABLE_ETM 0xe00ff014 +#define CYDEV_ROM_TABLE_END 0xe00ff018 +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0 +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4 +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8 +#define CYDEV_ROM_TABLE_PID7 0xe00fffdc +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0 +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4 +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8 +#define CYDEV_ROM_TABLE_PID3 0xe00fffec +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0 +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4 +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8 +#define CYDEV_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc new file mode 100644 index 0000000..30429cd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -0,0 +1,5356 @@ +; +; File Name: cydeviceiar_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000 +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000 +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000 +#define CYREG_SRAM_CODE_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE_MSIZE 0x00004000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 +#define CYREG_SRAM_DATA16K_MBASE 0x20001000 +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000 +#define CYREG_SRAM_DATA32K_MBASE 0x20002000 +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000 +#define CYREG_SRAM_DATA64K_MBASE 0x20004000 +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYREG_DMA_SRAM64K_MBASE 0x20008000 +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000 +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000 +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000 +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000 +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000 +#define CYREG_DMA_SRAM_MBASE 0x2000f000 +#define CYREG_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYREG_CLKDIST_CR 0x40004000 +#define CYREG_CLKDIST_LD 0x40004001 +#define CYREG_CLKDIST_WRK0 0x40004002 +#define CYREG_CLKDIST_WRK1 0x40004003 +#define CYREG_CLKDIST_MSTR0 0x40004004 +#define CYREG_CLKDIST_MSTR1 0x40004005 +#define CYREG_CLKDIST_BCFG0 0x40004006 +#define CYREG_CLKDIST_BCFG1 0x40004007 +#define CYREG_CLKDIST_BCFG2 0x40004008 +#define CYREG_CLKDIST_UCFG 0x40004009 +#define CYREG_CLKDIST_DLY0 0x4000400a +#define CYREG_CLKDIST_DLY1 0x4000400b +#define CYREG_CLKDIST_DMASK 0x40004010 +#define CYREG_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYREG_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210 +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYREG_FASTCLK_PLL_CFG0 0x40004220 +#define CYREG_FASTCLK_PLL_CFG1 0x40004221 +#define CYREG_FASTCLK_PLL_P 0x40004222 +#define CYREG_FASTCLK_PLL_Q 0x40004223 +#define CYREG_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYREG_SLOWCLK_ILO_CR0 0x40004300 +#define CYREG_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYREG_SLOWCLK_X32_CR 0x40004308 +#define CYREG_SLOWCLK_X32_CFG 0x40004309 +#define CYREG_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYREG_BOOST_CR0 0x40004320 +#define CYREG_BOOST_CR1 0x40004321 +#define CYREG_BOOST_CR2 0x40004322 +#define CYREG_BOOST_CR3 0x40004323 +#define CYREG_BOOST_SR 0x40004324 +#define CYREG_BOOST_CR4 0x40004325 +#define CYREG_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYREG_PWRSYS_CR0 0x40004330 +#define CYREG_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYREG_PM_TW_CFG0 0x40004380 +#define CYREG_PM_TW_CFG1 0x40004381 +#define CYREG_PM_TW_CFG2 0x40004382 +#define CYREG_PM_WDT_CFG 0x40004383 +#define CYREG_PM_WDT_CR 0x40004384 +#define CYREG_PM_INT_SR 0x40004390 +#define CYREG_PM_MODE_CFG0 0x40004391 +#define CYREG_PM_MODE_CFG1 0x40004392 +#define CYREG_PM_MODE_CSR 0x40004393 +#define CYREG_PM_USB_CR0 0x40004394 +#define CYREG_PM_WAKEUP_CFG0 0x40004398 +#define CYREG_PM_WAKEUP_CFG1 0x40004399 +#define CYREG_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYREG_PM_ACT_CFG0 0x400043a0 +#define CYREG_PM_ACT_CFG1 0x400043a1 +#define CYREG_PM_ACT_CFG2 0x400043a2 +#define CYREG_PM_ACT_CFG3 0x400043a3 +#define CYREG_PM_ACT_CFG4 0x400043a4 +#define CYREG_PM_ACT_CFG5 0x400043a5 +#define CYREG_PM_ACT_CFG6 0x400043a6 +#define CYREG_PM_ACT_CFG7 0x400043a7 +#define CYREG_PM_ACT_CFG8 0x400043a8 +#define CYREG_PM_ACT_CFG9 0x400043a9 +#define CYREG_PM_ACT_CFG10 0x400043aa +#define CYREG_PM_ACT_CFG11 0x400043ab +#define CYREG_PM_ACT_CFG12 0x400043ac +#define CYREG_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYREG_PM_STBY_CFG0 0x400043b0 +#define CYREG_PM_STBY_CFG1 0x400043b1 +#define CYREG_PM_STBY_CFG2 0x400043b2 +#define CYREG_PM_STBY_CFG3 0x400043b3 +#define CYREG_PM_STBY_CFG4 0x400043b4 +#define CYREG_PM_STBY_CFG5 0x400043b5 +#define CYREG_PM_STBY_CFG6 0x400043b6 +#define CYREG_PM_STBY_CFG7 0x400043b7 +#define CYREG_PM_STBY_CFG8 0x400043b8 +#define CYREG_PM_STBY_CFG9 0x400043b9 +#define CYREG_PM_STBY_CFG10 0x400043ba +#define CYREG_PM_STBY_CFG11 0x400043bb +#define CYREG_PM_STBY_CFG12 0x400043bc +#define CYREG_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYREG_PM_AVAIL_CR0 0x400043c0 +#define CYREG_PM_AVAIL_CR1 0x400043c1 +#define CYREG_PM_AVAIL_CR2 0x400043c2 +#define CYREG_PM_AVAIL_CR3 0x400043c3 +#define CYREG_PM_AVAIL_CR4 0x400043c4 +#define CYREG_PM_AVAIL_CR5 0x400043c5 +#define CYREG_PM_AVAIL_CR6 0x400043c6 +#define CYREG_PM_AVAIL_SR0 0x400043d0 +#define CYREG_PM_AVAIL_SR1 0x400043d1 +#define CYREG_PM_AVAIL_SR2 0x400043d2 +#define CYREG_PM_AVAIL_SR3 0x400043d3 +#define CYREG_PM_AVAIL_SR4 0x400043d4 +#define CYREG_PM_AVAIL_SR5 0x400043d5 +#define CYREG_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYREG_PICU0_INTTYPE0 0x40004500 +#define CYREG_PICU0_INTTYPE1 0x40004501 +#define CYREG_PICU0_INTTYPE2 0x40004502 +#define CYREG_PICU0_INTTYPE3 0x40004503 +#define CYREG_PICU0_INTTYPE4 0x40004504 +#define CYREG_PICU0_INTTYPE5 0x40004505 +#define CYREG_PICU0_INTTYPE6 0x40004506 +#define CYREG_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYREG_PICU1_INTTYPE0 0x40004508 +#define CYREG_PICU1_INTTYPE1 0x40004509 +#define CYREG_PICU1_INTTYPE2 0x4000450a +#define CYREG_PICU1_INTTYPE3 0x4000450b +#define CYREG_PICU1_INTTYPE4 0x4000450c +#define CYREG_PICU1_INTTYPE5 0x4000450d +#define CYREG_PICU1_INTTYPE6 0x4000450e +#define CYREG_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYREG_PICU2_INTTYPE0 0x40004510 +#define CYREG_PICU2_INTTYPE1 0x40004511 +#define CYREG_PICU2_INTTYPE2 0x40004512 +#define CYREG_PICU2_INTTYPE3 0x40004513 +#define CYREG_PICU2_INTTYPE4 0x40004514 +#define CYREG_PICU2_INTTYPE5 0x40004515 +#define CYREG_PICU2_INTTYPE6 0x40004516 +#define CYREG_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYREG_PICU3_INTTYPE0 0x40004518 +#define CYREG_PICU3_INTTYPE1 0x40004519 +#define CYREG_PICU3_INTTYPE2 0x4000451a +#define CYREG_PICU3_INTTYPE3 0x4000451b +#define CYREG_PICU3_INTTYPE4 0x4000451c +#define CYREG_PICU3_INTTYPE5 0x4000451d +#define CYREG_PICU3_INTTYPE6 0x4000451e +#define CYREG_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYREG_PICU4_INTTYPE0 0x40004520 +#define CYREG_PICU4_INTTYPE1 0x40004521 +#define CYREG_PICU4_INTTYPE2 0x40004522 +#define CYREG_PICU4_INTTYPE3 0x40004523 +#define CYREG_PICU4_INTTYPE4 0x40004524 +#define CYREG_PICU4_INTTYPE5 0x40004525 +#define CYREG_PICU4_INTTYPE6 0x40004526 +#define CYREG_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYREG_PICU5_INTTYPE0 0x40004528 +#define CYREG_PICU5_INTTYPE1 0x40004529 +#define CYREG_PICU5_INTTYPE2 0x4000452a +#define CYREG_PICU5_INTTYPE3 0x4000452b +#define CYREG_PICU5_INTTYPE4 0x4000452c +#define CYREG_PICU5_INTTYPE5 0x4000452d +#define CYREG_PICU5_INTTYPE6 0x4000452e +#define CYREG_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYREG_PICU6_INTTYPE0 0x40004530 +#define CYREG_PICU6_INTTYPE1 0x40004531 +#define CYREG_PICU6_INTTYPE2 0x40004532 +#define CYREG_PICU6_INTTYPE3 0x40004533 +#define CYREG_PICU6_INTTYPE4 0x40004534 +#define CYREG_PICU6_INTTYPE5 0x40004535 +#define CYREG_PICU6_INTTYPE6 0x40004536 +#define CYREG_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYREG_PICU12_INTTYPE0 0x40004560 +#define CYREG_PICU12_INTTYPE1 0x40004561 +#define CYREG_PICU12_INTTYPE2 0x40004562 +#define CYREG_PICU12_INTTYPE3 0x40004563 +#define CYREG_PICU12_INTTYPE4 0x40004564 +#define CYREG_PICU12_INTTYPE5 0x40004565 +#define CYREG_PICU12_INTTYPE6 0x40004566 +#define CYREG_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYREG_PICU15_INTTYPE0 0x40004578 +#define CYREG_PICU15_INTTYPE1 0x40004579 +#define CYREG_PICU15_INTTYPE2 0x4000457a +#define CYREG_PICU15_INTTYPE3 0x4000457b +#define CYREG_PICU15_INTTYPE4 0x4000457c +#define CYREG_PICU15_INTTYPE5 0x4000457d +#define CYREG_PICU15_INTTYPE6 0x4000457e +#define CYREG_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYREG_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYREG_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYREG_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYREG_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYREG_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYREG_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_TR0 0x40004620 +#define CYREG_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_TR0 0x40004622 +#define CYREG_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_TR0 0x40004624 +#define CYREG_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_TR0 0x40004626 +#define CYREG_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYREG_CMP0_TR0 0x40004630 +#define CYREG_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYREG_CMP1_TR0 0x40004632 +#define CYREG_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYREG_CMP2_TR0 0x40004634 +#define CYREG_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYREG_CMP3_TR0 0x40004636 +#define CYREG_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYREG_PWRSYS_HIB_TR0 0x40004680 +#define CYREG_PWRSYS_HIB_TR1 0x40004681 +#define CYREG_PWRSYS_I2C_TR 0x40004682 +#define CYREG_PWRSYS_SLP_TR 0x40004683 +#define CYREG_PWRSYS_BUZZ_TR 0x40004684 +#define CYREG_PWRSYS_WAKE_TR0 0x40004685 +#define CYREG_PWRSYS_WAKE_TR1 0x40004686 +#define CYREG_PWRSYS_BREF_TR 0x40004687 +#define CYREG_PWRSYS_BG_TR 0x40004688 +#define CYREG_PWRSYS_WAKE_TR2 0x40004689 +#define CYREG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYREG_ILO_TR0 0x40004690 +#define CYREG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYREG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYREG_IMO_TR0 0x400046a0 +#define CYREG_IMO_TR1 0x400046a1 +#define CYREG_IMO_GAIN 0x400046a2 +#define CYREG_IMO_C36M 0x400046a3 +#define CYREG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYREG_XMHZ_TR 0x400046a8 +#define CYREG_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYREG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYREG_MLOGIC_SEG_CR 0x400046e4 +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYREG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYREG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYREG_RESET_IPOR_CR0 0x400046f0 +#define CYREG_RESET_IPOR_CR1 0x400046f1 +#define CYREG_RESET_IPOR_CR2 0x400046f2 +#define CYREG_RESET_IPOR_CR3 0x400046f3 +#define CYREG_RESET_CR0 0x400046f4 +#define CYREG_RESET_CR1 0x400046f5 +#define CYREG_RESET_CR2 0x400046f6 +#define CYREG_RESET_CR3 0x400046f7 +#define CYREG_RESET_CR4 0x400046f8 +#define CYREG_RESET_CR5 0x400046f9 +#define CYREG_RESET_SR0 0x400046fa +#define CYREG_RESET_SR1 0x400046fb +#define CYREG_RESET_SR2 0x400046fc +#define CYREG_RESET_SR3 0x400046fd +#define CYREG_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYREG_SPC_FM_EE_CR 0x40004700 +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYREG_SPC_EE_SCR 0x40004702 +#define CYREG_SPC_EE_ERR 0x40004703 +#define CYREG_SPC_CPU_DATA 0x40004720 +#define CYREG_SPC_DMA_DATA 0x40004721 +#define CYREG_SPC_SR 0x40004722 +#define CYREG_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYREG_CACHE_CC_CTL 0x40004800 +#define CYREG_CACHE_ECC_CORR 0x40004880 +#define CYREG_CACHE_ECC_ERR 0x40004888 +#define CYREG_CACHE_FLASH_ERR 0x40004890 +#define CYREG_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYREG_I2C_XCFG 0x400049c8 +#define CYREG_I2C_ADR 0x400049ca +#define CYREG_I2C_CFG 0x400049d6 +#define CYREG_I2C_CSR 0x400049d7 +#define CYREG_I2C_D 0x400049d8 +#define CYREG_I2C_MCSR 0x400049d9 +#define CYREG_I2C_CLK_DIV1 0x400049db +#define CYREG_I2C_CLK_DIV2 0x400049dc +#define CYREG_I2C_TMOUT_CSR 0x400049dd +#define CYREG_I2C_TMOUT_SR 0x400049de +#define CYREG_I2C_TMOUT_CFG0 0x400049df +#define CYREG_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYREG_DEC_CR 0x40004e00 +#define CYREG_DEC_SR 0x40004e01 +#define CYREG_DEC_SHIFT1 0x40004e02 +#define CYREG_DEC_SHIFT2 0x40004e03 +#define CYREG_DEC_DR2 0x40004e04 +#define CYREG_DEC_DR2H 0x40004e05 +#define CYREG_DEC_DR1 0x40004e06 +#define CYREG_DEC_OCOR 0x40004e08 +#define CYREG_DEC_OCORM 0x40004e09 +#define CYREG_DEC_OCORH 0x40004e0a +#define CYREG_DEC_GCOR 0x40004e0c +#define CYREG_DEC_GCORH 0x40004e0d +#define CYREG_DEC_GVAL 0x40004e0e +#define CYREG_DEC_OUTSAMP 0x40004e10 +#define CYREG_DEC_OUTSAMPM 0x40004e11 +#define CYREG_DEC_OUTSAMPH 0x40004e12 +#define CYREG_DEC_OUTSAMPS 0x40004e13 +#define CYREG_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYREG_TMR0_CFG0 0x40004f00 +#define CYREG_TMR0_CFG1 0x40004f01 +#define CYREG_TMR0_CFG2 0x40004f02 +#define CYREG_TMR0_SR0 0x40004f03 +#define CYREG_TMR0_PER0 0x40004f04 +#define CYREG_TMR0_PER1 0x40004f05 +#define CYREG_TMR0_CNT_CMP0 0x40004f06 +#define CYREG_TMR0_CNT_CMP1 0x40004f07 +#define CYREG_TMR0_CAP0 0x40004f08 +#define CYREG_TMR0_CAP1 0x40004f09 +#define CYREG_TMR0_RT0 0x40004f0a +#define CYREG_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYREG_TMR1_CFG0 0x40004f0c +#define CYREG_TMR1_CFG1 0x40004f0d +#define CYREG_TMR1_CFG2 0x40004f0e +#define CYREG_TMR1_SR0 0x40004f0f +#define CYREG_TMR1_PER0 0x40004f10 +#define CYREG_TMR1_PER1 0x40004f11 +#define CYREG_TMR1_CNT_CMP0 0x40004f12 +#define CYREG_TMR1_CNT_CMP1 0x40004f13 +#define CYREG_TMR1_CAP0 0x40004f14 +#define CYREG_TMR1_CAP1 0x40004f15 +#define CYREG_TMR1_RT0 0x40004f16 +#define CYREG_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYREG_TMR2_CFG0 0x40004f18 +#define CYREG_TMR2_CFG1 0x40004f19 +#define CYREG_TMR2_CFG2 0x40004f1a +#define CYREG_TMR2_SR0 0x40004f1b +#define CYREG_TMR2_PER0 0x40004f1c +#define CYREG_TMR2_PER1 0x40004f1d +#define CYREG_TMR2_CNT_CMP0 0x40004f1e +#define CYREG_TMR2_CNT_CMP1 0x40004f1f +#define CYREG_TMR2_CAP0 0x40004f20 +#define CYREG_TMR2_CAP1 0x40004f21 +#define CYREG_TMR2_RT0 0x40004f22 +#define CYREG_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYREG_TMR3_CFG0 0x40004f24 +#define CYREG_TMR3_CFG1 0x40004f25 +#define CYREG_TMR3_CFG2 0x40004f26 +#define CYREG_TMR3_SR0 0x40004f27 +#define CYREG_TMR3_PER0 0x40004f28 +#define CYREG_TMR3_PER1 0x40004f29 +#define CYREG_TMR3_CNT_CMP0 0x40004f2a +#define CYREG_TMR3_CNT_CMP1 0x40004f2b +#define CYREG_TMR3_CAP0 0x40004f2c +#define CYREG_TMR3_CAP1 0x40004f2d +#define CYREG_TMR3_RT0 0x40004f2e +#define CYREG_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYREG_PRT0_PC0 0x40005000 +#define CYREG_PRT0_PC1 0x40005001 +#define CYREG_PRT0_PC2 0x40005002 +#define CYREG_PRT0_PC3 0x40005003 +#define CYREG_PRT0_PC4 0x40005004 +#define CYREG_PRT0_PC5 0x40005005 +#define CYREG_PRT0_PC6 0x40005006 +#define CYREG_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYREG_PRT1_PC0 0x40005008 +#define CYREG_PRT1_PC1 0x40005009 +#define CYREG_PRT1_PC2 0x4000500a +#define CYREG_PRT1_PC3 0x4000500b +#define CYREG_PRT1_PC4 0x4000500c +#define CYREG_PRT1_PC5 0x4000500d +#define CYREG_PRT1_PC6 0x4000500e +#define CYREG_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYREG_PRT2_PC0 0x40005010 +#define CYREG_PRT2_PC1 0x40005011 +#define CYREG_PRT2_PC2 0x40005012 +#define CYREG_PRT2_PC3 0x40005013 +#define CYREG_PRT2_PC4 0x40005014 +#define CYREG_PRT2_PC5 0x40005015 +#define CYREG_PRT2_PC6 0x40005016 +#define CYREG_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYREG_PRT3_PC0 0x40005018 +#define CYREG_PRT3_PC1 0x40005019 +#define CYREG_PRT3_PC2 0x4000501a +#define CYREG_PRT3_PC3 0x4000501b +#define CYREG_PRT3_PC4 0x4000501c +#define CYREG_PRT3_PC5 0x4000501d +#define CYREG_PRT3_PC6 0x4000501e +#define CYREG_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYREG_PRT4_PC0 0x40005020 +#define CYREG_PRT4_PC1 0x40005021 +#define CYREG_PRT4_PC2 0x40005022 +#define CYREG_PRT4_PC3 0x40005023 +#define CYREG_PRT4_PC4 0x40005024 +#define CYREG_PRT4_PC5 0x40005025 +#define CYREG_PRT4_PC6 0x40005026 +#define CYREG_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYREG_PRT5_PC0 0x40005028 +#define CYREG_PRT5_PC1 0x40005029 +#define CYREG_PRT5_PC2 0x4000502a +#define CYREG_PRT5_PC3 0x4000502b +#define CYREG_PRT5_PC4 0x4000502c +#define CYREG_PRT5_PC5 0x4000502d +#define CYREG_PRT5_PC6 0x4000502e +#define CYREG_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYREG_PRT6_PC0 0x40005030 +#define CYREG_PRT6_PC1 0x40005031 +#define CYREG_PRT6_PC2 0x40005032 +#define CYREG_PRT6_PC3 0x40005033 +#define CYREG_PRT6_PC4 0x40005034 +#define CYREG_PRT6_PC5 0x40005035 +#define CYREG_PRT6_PC6 0x40005036 +#define CYREG_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYREG_PRT12_PC0 0x40005060 +#define CYREG_PRT12_PC1 0x40005061 +#define CYREG_PRT12_PC2 0x40005062 +#define CYREG_PRT12_PC3 0x40005063 +#define CYREG_PRT12_PC4 0x40005064 +#define CYREG_PRT12_PC5 0x40005065 +#define CYREG_PRT12_PC6 0x40005066 +#define CYREG_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYREG_IO_PC_PRT15_PC0 0x40005078 +#define CYREG_IO_PC_PRT15_PC1 0x40005079 +#define CYREG_IO_PC_PRT15_PC2 0x4000507a +#define CYREG_IO_PC_PRT15_PC3 0x4000507b +#define CYREG_IO_PC_PRT15_PC4 0x4000507c +#define CYREG_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYREG_PRT0_DR 0x40005100 +#define CYREG_PRT0_PS 0x40005101 +#define CYREG_PRT0_DM0 0x40005102 +#define CYREG_PRT0_DM1 0x40005103 +#define CYREG_PRT0_DM2 0x40005104 +#define CYREG_PRT0_SLW 0x40005105 +#define CYREG_PRT0_BYP 0x40005106 +#define CYREG_PRT0_BIE 0x40005107 +#define CYREG_PRT0_INP_DIS 0x40005108 +#define CYREG_PRT0_CTL 0x40005109 +#define CYREG_PRT0_PRT 0x4000510a +#define CYREG_PRT0_BIT_MASK 0x4000510b +#define CYREG_PRT0_AMUX 0x4000510c +#define CYREG_PRT0_AG 0x4000510d +#define CYREG_PRT0_LCD_COM_SEG 0x4000510e +#define CYREG_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYREG_PRT1_DR 0x40005110 +#define CYREG_PRT1_PS 0x40005111 +#define CYREG_PRT1_DM0 0x40005112 +#define CYREG_PRT1_DM1 0x40005113 +#define CYREG_PRT1_DM2 0x40005114 +#define CYREG_PRT1_SLW 0x40005115 +#define CYREG_PRT1_BYP 0x40005116 +#define CYREG_PRT1_BIE 0x40005117 +#define CYREG_PRT1_INP_DIS 0x40005118 +#define CYREG_PRT1_CTL 0x40005119 +#define CYREG_PRT1_PRT 0x4000511a +#define CYREG_PRT1_BIT_MASK 0x4000511b +#define CYREG_PRT1_AMUX 0x4000511c +#define CYREG_PRT1_AG 0x4000511d +#define CYREG_PRT1_LCD_COM_SEG 0x4000511e +#define CYREG_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYREG_PRT2_DR 0x40005120 +#define CYREG_PRT2_PS 0x40005121 +#define CYREG_PRT2_DM0 0x40005122 +#define CYREG_PRT2_DM1 0x40005123 +#define CYREG_PRT2_DM2 0x40005124 +#define CYREG_PRT2_SLW 0x40005125 +#define CYREG_PRT2_BYP 0x40005126 +#define CYREG_PRT2_BIE 0x40005127 +#define CYREG_PRT2_INP_DIS 0x40005128 +#define CYREG_PRT2_CTL 0x40005129 +#define CYREG_PRT2_PRT 0x4000512a +#define CYREG_PRT2_BIT_MASK 0x4000512b +#define CYREG_PRT2_AMUX 0x4000512c +#define CYREG_PRT2_AG 0x4000512d +#define CYREG_PRT2_LCD_COM_SEG 0x4000512e +#define CYREG_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYREG_PRT3_DR 0x40005130 +#define CYREG_PRT3_PS 0x40005131 +#define CYREG_PRT3_DM0 0x40005132 +#define CYREG_PRT3_DM1 0x40005133 +#define CYREG_PRT3_DM2 0x40005134 +#define CYREG_PRT3_SLW 0x40005135 +#define CYREG_PRT3_BYP 0x40005136 +#define CYREG_PRT3_BIE 0x40005137 +#define CYREG_PRT3_INP_DIS 0x40005138 +#define CYREG_PRT3_CTL 0x40005139 +#define CYREG_PRT3_PRT 0x4000513a +#define CYREG_PRT3_BIT_MASK 0x4000513b +#define CYREG_PRT3_AMUX 0x4000513c +#define CYREG_PRT3_AG 0x4000513d +#define CYREG_PRT3_LCD_COM_SEG 0x4000513e +#define CYREG_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYREG_PRT4_DR 0x40005140 +#define CYREG_PRT4_PS 0x40005141 +#define CYREG_PRT4_DM0 0x40005142 +#define CYREG_PRT4_DM1 0x40005143 +#define CYREG_PRT4_DM2 0x40005144 +#define CYREG_PRT4_SLW 0x40005145 +#define CYREG_PRT4_BYP 0x40005146 +#define CYREG_PRT4_BIE 0x40005147 +#define CYREG_PRT4_INP_DIS 0x40005148 +#define CYREG_PRT4_CTL 0x40005149 +#define CYREG_PRT4_PRT 0x4000514a +#define CYREG_PRT4_BIT_MASK 0x4000514b +#define CYREG_PRT4_AMUX 0x4000514c +#define CYREG_PRT4_AG 0x4000514d +#define CYREG_PRT4_LCD_COM_SEG 0x4000514e +#define CYREG_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYREG_PRT5_DR 0x40005150 +#define CYREG_PRT5_PS 0x40005151 +#define CYREG_PRT5_DM0 0x40005152 +#define CYREG_PRT5_DM1 0x40005153 +#define CYREG_PRT5_DM2 0x40005154 +#define CYREG_PRT5_SLW 0x40005155 +#define CYREG_PRT5_BYP 0x40005156 +#define CYREG_PRT5_BIE 0x40005157 +#define CYREG_PRT5_INP_DIS 0x40005158 +#define CYREG_PRT5_CTL 0x40005159 +#define CYREG_PRT5_PRT 0x4000515a +#define CYREG_PRT5_BIT_MASK 0x4000515b +#define CYREG_PRT5_AMUX 0x4000515c +#define CYREG_PRT5_AG 0x4000515d +#define CYREG_PRT5_LCD_COM_SEG 0x4000515e +#define CYREG_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYREG_PRT6_DR 0x40005160 +#define CYREG_PRT6_PS 0x40005161 +#define CYREG_PRT6_DM0 0x40005162 +#define CYREG_PRT6_DM1 0x40005163 +#define CYREG_PRT6_DM2 0x40005164 +#define CYREG_PRT6_SLW 0x40005165 +#define CYREG_PRT6_BYP 0x40005166 +#define CYREG_PRT6_BIE 0x40005167 +#define CYREG_PRT6_INP_DIS 0x40005168 +#define CYREG_PRT6_CTL 0x40005169 +#define CYREG_PRT6_PRT 0x4000516a +#define CYREG_PRT6_BIT_MASK 0x4000516b +#define CYREG_PRT6_AMUX 0x4000516c +#define CYREG_PRT6_AG 0x4000516d +#define CYREG_PRT6_LCD_COM_SEG 0x4000516e +#define CYREG_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYREG_PRT12_DR 0x400051c0 +#define CYREG_PRT12_PS 0x400051c1 +#define CYREG_PRT12_DM0 0x400051c2 +#define CYREG_PRT12_DM1 0x400051c3 +#define CYREG_PRT12_DM2 0x400051c4 +#define CYREG_PRT12_SLW 0x400051c5 +#define CYREG_PRT12_BYP 0x400051c6 +#define CYREG_PRT12_BIE 0x400051c7 +#define CYREG_PRT12_INP_DIS 0x400051c8 +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9 +#define CYREG_PRT12_PRT 0x400051ca +#define CYREG_PRT12_BIT_MASK 0x400051cb +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYREG_PRT12_AG 0x400051cd +#define CYREG_PRT12_SIO_CFG 0x400051ce +#define CYREG_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYREG_PRT15_DR 0x400051f0 +#define CYREG_PRT15_PS 0x400051f1 +#define CYREG_PRT15_DM0 0x400051f2 +#define CYREG_PRT15_DM1 0x400051f3 +#define CYREG_PRT15_DM2 0x400051f4 +#define CYREG_PRT15_SLW 0x400051f5 +#define CYREG_PRT15_BYP 0x400051f6 +#define CYREG_PRT15_BIE 0x400051f7 +#define CYREG_PRT15_INP_DIS 0x400051f8 +#define CYREG_PRT15_CTL 0x400051f9 +#define CYREG_PRT15_PRT 0x400051fa +#define CYREG_PRT15_BIT_MASK 0x400051fb +#define CYREG_PRT15_AMUX 0x400051fc +#define CYREG_PRT15_AG 0x400051fd +#define CYREG_PRT15_LCD_COM_SEG 0x400051fe +#define CYREG_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYREG_PRT0_OUT_SEL0 0x40005200 +#define CYREG_PRT0_OUT_SEL1 0x40005201 +#define CYREG_PRT0_OE_SEL0 0x40005202 +#define CYREG_PRT0_OE_SEL1 0x40005203 +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204 +#define CYREG_PRT0_SYNC_OUT 0x40005205 +#define CYREG_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYREG_PRT1_OUT_SEL0 0x40005208 +#define CYREG_PRT1_OUT_SEL1 0x40005209 +#define CYREG_PRT1_OE_SEL0 0x4000520a +#define CYREG_PRT1_OE_SEL1 0x4000520b +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c +#define CYREG_PRT1_SYNC_OUT 0x4000520d +#define CYREG_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYREG_PRT2_OUT_SEL0 0x40005210 +#define CYREG_PRT2_OUT_SEL1 0x40005211 +#define CYREG_PRT2_OE_SEL0 0x40005212 +#define CYREG_PRT2_OE_SEL1 0x40005213 +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214 +#define CYREG_PRT2_SYNC_OUT 0x40005215 +#define CYREG_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYREG_PRT3_OUT_SEL0 0x40005218 +#define CYREG_PRT3_OUT_SEL1 0x40005219 +#define CYREG_PRT3_OE_SEL0 0x4000521a +#define CYREG_PRT3_OE_SEL1 0x4000521b +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c +#define CYREG_PRT3_SYNC_OUT 0x4000521d +#define CYREG_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYREG_PRT4_OUT_SEL0 0x40005220 +#define CYREG_PRT4_OUT_SEL1 0x40005221 +#define CYREG_PRT4_OE_SEL0 0x40005222 +#define CYREG_PRT4_OE_SEL1 0x40005223 +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224 +#define CYREG_PRT4_SYNC_OUT 0x40005225 +#define CYREG_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYREG_PRT5_OUT_SEL0 0x40005228 +#define CYREG_PRT5_OUT_SEL1 0x40005229 +#define CYREG_PRT5_OE_SEL0 0x4000522a +#define CYREG_PRT5_OE_SEL1 0x4000522b +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c +#define CYREG_PRT5_SYNC_OUT 0x4000522d +#define CYREG_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYREG_PRT6_OUT_SEL0 0x40005230 +#define CYREG_PRT6_OUT_SEL1 0x40005231 +#define CYREG_PRT6_OE_SEL0 0x40005232 +#define CYREG_PRT6_OE_SEL1 0x40005233 +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234 +#define CYREG_PRT6_SYNC_OUT 0x40005235 +#define CYREG_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYREG_PRT12_OUT_SEL0 0x40005260 +#define CYREG_PRT12_OUT_SEL1 0x40005261 +#define CYREG_PRT12_OE_SEL0 0x40005262 +#define CYREG_PRT12_OE_SEL1 0x40005263 +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264 +#define CYREG_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYREG_PRT15_OUT_SEL0 0x40005278 +#define CYREG_PRT15_OUT_SEL1 0x40005279 +#define CYREG_PRT15_OE_SEL0 0x4000527a +#define CYREG_PRT15_OE_SEL1 0x4000527b +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c +#define CYREG_PRT15_SYNC_OUT 0x4000527d +#define CYREG_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYREG_EMIF_NO_UDB 0x40005400 +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401 +#define CYREG_EMIF_MEM_DWN 0x40005402 +#define CYREG_EMIF_MEMCLK_DIV 0x40005403 +#define CYREG_EMIF_CLOCK_EN 0x40005404 +#define CYREG_EMIF_EM_TYPE 0x40005405 +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYREG_SC0_CR0 0x40005800 +#define CYREG_SC0_CR1 0x40005801 +#define CYREG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYREG_SC1_CR0 0x40005804 +#define CYREG_SC1_CR1 0x40005805 +#define CYREG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYREG_SC2_CR0 0x40005808 +#define CYREG_SC2_CR1 0x40005809 +#define CYREG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYREG_SC3_CR0 0x4000580c +#define CYREG_SC3_CR1 0x4000580d +#define CYREG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYREG_DAC0_CR0 0x40005820 +#define CYREG_DAC0_CR1 0x40005821 +#define CYREG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYREG_DAC1_CR0 0x40005824 +#define CYREG_DAC1_CR1 0x40005825 +#define CYREG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYREG_DAC2_CR0 0x40005828 +#define CYREG_DAC2_CR1 0x40005829 +#define CYREG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYREG_DAC3_CR0 0x4000582c +#define CYREG_DAC3_CR1 0x4000582d +#define CYREG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYREG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYREG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYREG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYREG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYREG_LUT0_CR 0x40005848 +#define CYREG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYREG_LUT1_CR 0x4000584a +#define CYREG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYREG_LUT2_CR 0x4000584c +#define CYREG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYREG_LUT3_CR 0x4000584e +#define CYREG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_CR 0x40005858 +#define CYREG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_CR 0x4000585a +#define CYREG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_CR 0x4000585c +#define CYREG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_CR 0x4000585e +#define CYREG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYREG_LCDDAC_CR0 0x40005868 +#define CYREG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYREG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYREG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYREG_BG_CR0 0x4000586c +#define CYREG_BG_RSVD 0x4000586d +#define CYREG_BG_DFT0 0x4000586e +#define CYREG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYREG_CAPSL_CFG0 0x40005870 +#define CYREG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYREG_CAPSR_CFG0 0x40005872 +#define CYREG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYREG_PUMP_CR0 0x40005876 +#define CYREG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYREG_LPF0_CR0 0x40005878 +#define CYREG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYREG_LPF1_CR0 0x4000587a +#define CYREG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYREG_DSM0_CR0 0x40005880 +#define CYREG_DSM0_CR1 0x40005881 +#define CYREG_DSM0_CR2 0x40005882 +#define CYREG_DSM0_CR3 0x40005883 +#define CYREG_DSM0_CR4 0x40005884 +#define CYREG_DSM0_CR5 0x40005885 +#define CYREG_DSM0_CR6 0x40005886 +#define CYREG_DSM0_CR7 0x40005887 +#define CYREG_DSM0_CR8 0x40005888 +#define CYREG_DSM0_CR9 0x40005889 +#define CYREG_DSM0_CR10 0x4000588a +#define CYREG_DSM0_CR11 0x4000588b +#define CYREG_DSM0_CR12 0x4000588c +#define CYREG_DSM0_CR13 0x4000588d +#define CYREG_DSM0_CR14 0x4000588e +#define CYREG_DSM0_CR15 0x4000588f +#define CYREG_DSM0_CR16 0x40005890 +#define CYREG_DSM0_CR17 0x40005891 +#define CYREG_DSM0_REF0 0x40005892 +#define CYREG_DSM0_REF1 0x40005893 +#define CYREG_DSM0_REF2 0x40005894 +#define CYREG_DSM0_REF3 0x40005895 +#define CYREG_DSM0_DEM0 0x40005896 +#define CYREG_DSM0_DEM1 0x40005897 +#define CYREG_DSM0_TST0 0x40005898 +#define CYREG_DSM0_TST1 0x40005899 +#define CYREG_DSM0_BUF0 0x4000589a +#define CYREG_DSM0_BUF1 0x4000589b +#define CYREG_DSM0_BUF2 0x4000589c +#define CYREG_DSM0_BUF3 0x4000589d +#define CYREG_DSM0_MISC 0x4000589e +#define CYREG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYREG_SAR0_CSR0 0x40005900 +#define CYREG_SAR0_CSR1 0x40005901 +#define CYREG_SAR0_CSR2 0x40005902 +#define CYREG_SAR0_CSR3 0x40005903 +#define CYREG_SAR0_CSR4 0x40005904 +#define CYREG_SAR0_CSR5 0x40005905 +#define CYREG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYREG_SAR1_CSR0 0x40005908 +#define CYREG_SAR1_CSR1 0x40005909 +#define CYREG_SAR1_CSR2 0x4000590a +#define CYREG_SAR1_CSR3 0x4000590b +#define CYREG_SAR1_CSR4 0x4000590c +#define CYREG_SAR1_CSR5 0x4000590d +#define CYREG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYREG_SC0_SW0 0x40005a00 +#define CYREG_SC0_SW2 0x40005a02 +#define CYREG_SC0_SW3 0x40005a03 +#define CYREG_SC0_SW4 0x40005a04 +#define CYREG_SC0_SW6 0x40005a06 +#define CYREG_SC0_SW7 0x40005a07 +#define CYREG_SC0_SW8 0x40005a08 +#define CYREG_SC0_SW10 0x40005a0a +#define CYREG_SC0_CLK 0x40005a0b +#define CYREG_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYREG_SC1_SW0 0x40005a10 +#define CYREG_SC1_SW2 0x40005a12 +#define CYREG_SC1_SW3 0x40005a13 +#define CYREG_SC1_SW4 0x40005a14 +#define CYREG_SC1_SW6 0x40005a16 +#define CYREG_SC1_SW7 0x40005a17 +#define CYREG_SC1_SW8 0x40005a18 +#define CYREG_SC1_SW10 0x40005a1a +#define CYREG_SC1_CLK 0x40005a1b +#define CYREG_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYREG_SC2_SW0 0x40005a20 +#define CYREG_SC2_SW2 0x40005a22 +#define CYREG_SC2_SW3 0x40005a23 +#define CYREG_SC2_SW4 0x40005a24 +#define CYREG_SC2_SW6 0x40005a26 +#define CYREG_SC2_SW7 0x40005a27 +#define CYREG_SC2_SW8 0x40005a28 +#define CYREG_SC2_SW10 0x40005a2a +#define CYREG_SC2_CLK 0x40005a2b +#define CYREG_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYREG_SC3_SW0 0x40005a30 +#define CYREG_SC3_SW2 0x40005a32 +#define CYREG_SC3_SW3 0x40005a33 +#define CYREG_SC3_SW4 0x40005a34 +#define CYREG_SC3_SW6 0x40005a36 +#define CYREG_SC3_SW7 0x40005a37 +#define CYREG_SC3_SW8 0x40005a38 +#define CYREG_SC3_SW10 0x40005a3a +#define CYREG_SC3_CLK 0x40005a3b +#define CYREG_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYREG_DAC0_SW0 0x40005a80 +#define CYREG_DAC0_SW2 0x40005a82 +#define CYREG_DAC0_SW3 0x40005a83 +#define CYREG_DAC0_SW4 0x40005a84 +#define CYREG_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYREG_DAC1_SW0 0x40005a88 +#define CYREG_DAC1_SW2 0x40005a8a +#define CYREG_DAC1_SW3 0x40005a8b +#define CYREG_DAC1_SW4 0x40005a8c +#define CYREG_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYREG_DAC2_SW0 0x40005a90 +#define CYREG_DAC2_SW2 0x40005a92 +#define CYREG_DAC2_SW3 0x40005a93 +#define CYREG_DAC2_SW4 0x40005a94 +#define CYREG_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYREG_DAC3_SW0 0x40005a98 +#define CYREG_DAC3_SW2 0x40005a9a +#define CYREG_DAC3_SW3 0x40005a9b +#define CYREG_DAC3_SW4 0x40005a9c +#define CYREG_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYREG_CMP0_SW0 0x40005ac0 +#define CYREG_CMP0_SW2 0x40005ac2 +#define CYREG_CMP0_SW3 0x40005ac3 +#define CYREG_CMP0_SW4 0x40005ac4 +#define CYREG_CMP0_SW6 0x40005ac6 +#define CYREG_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYREG_CMP1_SW0 0x40005ac8 +#define CYREG_CMP1_SW2 0x40005aca +#define CYREG_CMP1_SW3 0x40005acb +#define CYREG_CMP1_SW4 0x40005acc +#define CYREG_CMP1_SW6 0x40005ace +#define CYREG_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYREG_CMP2_SW0 0x40005ad0 +#define CYREG_CMP2_SW2 0x40005ad2 +#define CYREG_CMP2_SW3 0x40005ad3 +#define CYREG_CMP2_SW4 0x40005ad4 +#define CYREG_CMP2_SW6 0x40005ad6 +#define CYREG_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYREG_CMP3_SW0 0x40005ad8 +#define CYREG_CMP3_SW2 0x40005ada +#define CYREG_CMP3_SW3 0x40005adb +#define CYREG_CMP3_SW4 0x40005adc +#define CYREG_CMP3_SW6 0x40005ade +#define CYREG_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYREG_DSM0_SW0 0x40005b00 +#define CYREG_DSM0_SW2 0x40005b02 +#define CYREG_DSM0_SW3 0x40005b03 +#define CYREG_DSM0_SW4 0x40005b04 +#define CYREG_DSM0_SW6 0x40005b06 +#define CYREG_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYREG_SAR0_SW0 0x40005b20 +#define CYREG_SAR0_SW2 0x40005b22 +#define CYREG_SAR0_SW3 0x40005b23 +#define CYREG_SAR0_SW4 0x40005b24 +#define CYREG_SAR0_SW6 0x40005b26 +#define CYREG_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYREG_SAR1_SW0 0x40005b28 +#define CYREG_SAR1_SW2 0x40005b2a +#define CYREG_SAR1_SW3 0x40005b2b +#define CYREG_SAR1_SW4 0x40005b2c +#define CYREG_SAR1_SW6 0x40005b2e +#define CYREG_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_MX 0x40005b40 +#define CYREG_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_MX 0x40005b42 +#define CYREG_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_MX 0x40005b44 +#define CYREG_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_MX 0x40005b46 +#define CYREG_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYREG_LCDDAC_SW0 0x40005b50 +#define CYREG_LCDDAC_SW1 0x40005b51 +#define CYREG_LCDDAC_SW2 0x40005b52 +#define CYREG_LCDDAC_SW3 0x40005b53 +#define CYREG_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYREG_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYREG_BUS_SW0 0x40005b58 +#define CYREG_BUS_SW2 0x40005b5a +#define CYREG_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYREG_DFT_CR0 0x40005b5c +#define CYREG_DFT_CR1 0x40005b5d +#define CYREG_DFT_CR2 0x40005b5e +#define CYREG_DFT_CR3 0x40005b5f +#define CYREG_DFT_CR4 0x40005b60 +#define CYREG_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYREG_DSM0_OUT0 0x40005b88 +#define CYREG_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYREG_LUT_SR 0x40005b90 +#define CYREG_LUT_WRK1 0x40005b91 +#define CYREG_LUT_MSK 0x40005b92 +#define CYREG_LUT_CLK 0x40005b93 +#define CYREG_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYREG_CMP_WRK 0x40005b96 +#define CYREG_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYREG_SC_SR 0x40005b98 +#define CYREG_SC_WRK1 0x40005b99 +#define CYREG_SC_MSK 0x40005b9a +#define CYREG_SC_CMPINV 0x40005b9b +#define CYREG_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYREG_SAR0_WRK0 0x40005ba0 +#define CYREG_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYREG_SAR1_WRK0 0x40005ba2 +#define CYREG_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYREG_USB_EP0_DR0 0x40006000 +#define CYREG_USB_EP0_DR1 0x40006001 +#define CYREG_USB_EP0_DR2 0x40006002 +#define CYREG_USB_EP0_DR3 0x40006003 +#define CYREG_USB_EP0_DR4 0x40006004 +#define CYREG_USB_EP0_DR5 0x40006005 +#define CYREG_USB_EP0_DR6 0x40006006 +#define CYREG_USB_EP0_DR7 0x40006007 +#define CYREG_USB_CR0 0x40006008 +#define CYREG_USB_CR1 0x40006009 +#define CYREG_USB_SIE_EP_INT_EN 0x4000600a +#define CYREG_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYREG_USB_SIE_EP1_CNT0 0x4000600c +#define CYREG_USB_SIE_EP1_CNT1 0x4000600d +#define CYREG_USB_SIE_EP1_CR0 0x4000600e +#define CYREG_USB_USBIO_CR0 0x40006010 +#define CYREG_USB_USBIO_CR1 0x40006012 +#define CYREG_USB_DYN_RECONFIG 0x40006014 +#define CYREG_USB_SOF0 0x40006018 +#define CYREG_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYREG_USB_SIE_EP2_CNT0 0x4000601c +#define CYREG_USB_SIE_EP2_CNT1 0x4000601d +#define CYREG_USB_SIE_EP2_CR0 0x4000601e +#define CYREG_USB_EP0_CR 0x40006028 +#define CYREG_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYREG_USB_SIE_EP3_CNT0 0x4000602c +#define CYREG_USB_SIE_EP3_CNT1 0x4000602d +#define CYREG_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYREG_USB_SIE_EP4_CNT0 0x4000603c +#define CYREG_USB_SIE_EP4_CNT1 0x4000603d +#define CYREG_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYREG_USB_SIE_EP5_CNT0 0x4000604c +#define CYREG_USB_SIE_EP5_CNT1 0x4000604d +#define CYREG_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYREG_USB_SIE_EP6_CNT0 0x4000605c +#define CYREG_USB_SIE_EP6_CNT1 0x4000605d +#define CYREG_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYREG_USB_SIE_EP7_CNT0 0x4000606c +#define CYREG_USB_SIE_EP7_CNT1 0x4000606d +#define CYREG_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYREG_USB_SIE_EP8_CNT0 0x4000607c +#define CYREG_USB_SIE_EP8_CNT1 0x4000607d +#define CYREG_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYREG_USB_ARB_EP1_CFG 0x40006080 +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081 +#define CYREG_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYREG_USB_ARB_RW1_WA 0x40006084 +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYREG_USB_ARB_RW1_RA 0x40006086 +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYREG_USB_ARB_RW1_DR 0x40006088 +#define CYREG_USB_BUF_SIZE 0x4000608c +#define CYREG_USB_EP_ACTIVE 0x4000608e +#define CYREG_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYREG_USB_ARB_EP2_CFG 0x40006090 +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091 +#define CYREG_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYREG_USB_ARB_RW2_WA 0x40006094 +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYREG_USB_ARB_RW2_RA 0x40006096 +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYREG_USB_ARB_RW2_DR 0x40006098 +#define CYREG_USB_ARB_CFG 0x4000609c +#define CYREG_USB_USB_CLK_EN 0x4000609d +#define CYREG_USB_ARB_INT_EN 0x4000609e +#define CYREG_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYREG_USB_ARB_EP3_CFG 0x400060a0 +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYREG_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYREG_USB_ARB_RW3_WA 0x400060a4 +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYREG_USB_ARB_RW3_RA 0x400060a6 +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYREG_USB_ARB_RW3_DR 0x400060a8 +#define CYREG_USB_CWA 0x400060ac +#define CYREG_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYREG_USB_ARB_EP4_CFG 0x400060b0 +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYREG_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYREG_USB_ARB_RW4_WA 0x400060b4 +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYREG_USB_ARB_RW4_RA 0x400060b6 +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYREG_USB_ARB_RW4_DR 0x400060b8 +#define CYREG_USB_DMA_THRES 0x400060bc +#define CYREG_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYREG_USB_ARB_EP5_CFG 0x400060c0 +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYREG_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYREG_USB_ARB_RW5_WA 0x400060c4 +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYREG_USB_ARB_RW5_RA 0x400060c6 +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYREG_USB_ARB_RW5_DR 0x400060c8 +#define CYREG_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYREG_USB_ARB_EP6_CFG 0x400060d0 +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYREG_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYREG_USB_ARB_RW6_WA 0x400060d4 +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYREG_USB_ARB_RW6_RA 0x400060d6 +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYREG_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYREG_USB_ARB_EP7_CFG 0x400060e0 +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYREG_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYREG_USB_ARB_RW7_WA 0x400060e4 +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYREG_USB_ARB_RW7_RA 0x400060e6 +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYREG_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYREG_USB_ARB_EP8_CFG 0x400060f0 +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYREG_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYREG_USB_ARB_RW8_WA 0x400060f4 +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYREG_USB_ARB_RW8_RA 0x400060f6 +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYREG_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYREG_USB_MEM_DATA_MBASE 0x40006100 +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYREG_B0_UDB00_A0 0x40006400 +#define CYREG_B0_UDB01_A0 0x40006401 +#define CYREG_B0_UDB02_A0 0x40006402 +#define CYREG_B0_UDB03_A0 0x40006403 +#define CYREG_B0_UDB04_A0 0x40006404 +#define CYREG_B0_UDB05_A0 0x40006405 +#define CYREG_B0_UDB06_A0 0x40006406 +#define CYREG_B0_UDB07_A0 0x40006407 +#define CYREG_B0_UDB08_A0 0x40006408 +#define CYREG_B0_UDB09_A0 0x40006409 +#define CYREG_B0_UDB10_A0 0x4000640a +#define CYREG_B0_UDB11_A0 0x4000640b +#define CYREG_B0_UDB12_A0 0x4000640c +#define CYREG_B0_UDB13_A0 0x4000640d +#define CYREG_B0_UDB14_A0 0x4000640e +#define CYREG_B0_UDB15_A0 0x4000640f +#define CYREG_B0_UDB00_A1 0x40006410 +#define CYREG_B0_UDB01_A1 0x40006411 +#define CYREG_B0_UDB02_A1 0x40006412 +#define CYREG_B0_UDB03_A1 0x40006413 +#define CYREG_B0_UDB04_A1 0x40006414 +#define CYREG_B0_UDB05_A1 0x40006415 +#define CYREG_B0_UDB06_A1 0x40006416 +#define CYREG_B0_UDB07_A1 0x40006417 +#define CYREG_B0_UDB08_A1 0x40006418 +#define CYREG_B0_UDB09_A1 0x40006419 +#define CYREG_B0_UDB10_A1 0x4000641a +#define CYREG_B0_UDB11_A1 0x4000641b +#define CYREG_B0_UDB12_A1 0x4000641c +#define CYREG_B0_UDB13_A1 0x4000641d +#define CYREG_B0_UDB14_A1 0x4000641e +#define CYREG_B0_UDB15_A1 0x4000641f +#define CYREG_B0_UDB00_D0 0x40006420 +#define CYREG_B0_UDB01_D0 0x40006421 +#define CYREG_B0_UDB02_D0 0x40006422 +#define CYREG_B0_UDB03_D0 0x40006423 +#define CYREG_B0_UDB04_D0 0x40006424 +#define CYREG_B0_UDB05_D0 0x40006425 +#define CYREG_B0_UDB06_D0 0x40006426 +#define CYREG_B0_UDB07_D0 0x40006427 +#define CYREG_B0_UDB08_D0 0x40006428 +#define CYREG_B0_UDB09_D0 0x40006429 +#define CYREG_B0_UDB10_D0 0x4000642a +#define CYREG_B0_UDB11_D0 0x4000642b +#define CYREG_B0_UDB12_D0 0x4000642c +#define CYREG_B0_UDB13_D0 0x4000642d +#define CYREG_B0_UDB14_D0 0x4000642e +#define CYREG_B0_UDB15_D0 0x4000642f +#define CYREG_B0_UDB00_D1 0x40006430 +#define CYREG_B0_UDB01_D1 0x40006431 +#define CYREG_B0_UDB02_D1 0x40006432 +#define CYREG_B0_UDB03_D1 0x40006433 +#define CYREG_B0_UDB04_D1 0x40006434 +#define CYREG_B0_UDB05_D1 0x40006435 +#define CYREG_B0_UDB06_D1 0x40006436 +#define CYREG_B0_UDB07_D1 0x40006437 +#define CYREG_B0_UDB08_D1 0x40006438 +#define CYREG_B0_UDB09_D1 0x40006439 +#define CYREG_B0_UDB10_D1 0x4000643a +#define CYREG_B0_UDB11_D1 0x4000643b +#define CYREG_B0_UDB12_D1 0x4000643c +#define CYREG_B0_UDB13_D1 0x4000643d +#define CYREG_B0_UDB14_D1 0x4000643e +#define CYREG_B0_UDB15_D1 0x4000643f +#define CYREG_B0_UDB00_F0 0x40006440 +#define CYREG_B0_UDB01_F0 0x40006441 +#define CYREG_B0_UDB02_F0 0x40006442 +#define CYREG_B0_UDB03_F0 0x40006443 +#define CYREG_B0_UDB04_F0 0x40006444 +#define CYREG_B0_UDB05_F0 0x40006445 +#define CYREG_B0_UDB06_F0 0x40006446 +#define CYREG_B0_UDB07_F0 0x40006447 +#define CYREG_B0_UDB08_F0 0x40006448 +#define CYREG_B0_UDB09_F0 0x40006449 +#define CYREG_B0_UDB10_F0 0x4000644a +#define CYREG_B0_UDB11_F0 0x4000644b +#define CYREG_B0_UDB12_F0 0x4000644c +#define CYREG_B0_UDB13_F0 0x4000644d +#define CYREG_B0_UDB14_F0 0x4000644e +#define CYREG_B0_UDB15_F0 0x4000644f +#define CYREG_B0_UDB00_F1 0x40006450 +#define CYREG_B0_UDB01_F1 0x40006451 +#define CYREG_B0_UDB02_F1 0x40006452 +#define CYREG_B0_UDB03_F1 0x40006453 +#define CYREG_B0_UDB04_F1 0x40006454 +#define CYREG_B0_UDB05_F1 0x40006455 +#define CYREG_B0_UDB06_F1 0x40006456 +#define CYREG_B0_UDB07_F1 0x40006457 +#define CYREG_B0_UDB08_F1 0x40006458 +#define CYREG_B0_UDB09_F1 0x40006459 +#define CYREG_B0_UDB10_F1 0x4000645a +#define CYREG_B0_UDB11_F1 0x4000645b +#define CYREG_B0_UDB12_F1 0x4000645c +#define CYREG_B0_UDB13_F1 0x4000645d +#define CYREG_B0_UDB14_F1 0x4000645e +#define CYREG_B0_UDB15_F1 0x4000645f +#define CYREG_B0_UDB00_ST 0x40006460 +#define CYREG_B0_UDB01_ST 0x40006461 +#define CYREG_B0_UDB02_ST 0x40006462 +#define CYREG_B0_UDB03_ST 0x40006463 +#define CYREG_B0_UDB04_ST 0x40006464 +#define CYREG_B0_UDB05_ST 0x40006465 +#define CYREG_B0_UDB06_ST 0x40006466 +#define CYREG_B0_UDB07_ST 0x40006467 +#define CYREG_B0_UDB08_ST 0x40006468 +#define CYREG_B0_UDB09_ST 0x40006469 +#define CYREG_B0_UDB10_ST 0x4000646a +#define CYREG_B0_UDB11_ST 0x4000646b +#define CYREG_B0_UDB12_ST 0x4000646c +#define CYREG_B0_UDB13_ST 0x4000646d +#define CYREG_B0_UDB14_ST 0x4000646e +#define CYREG_B0_UDB15_ST 0x4000646f +#define CYREG_B0_UDB00_CTL 0x40006470 +#define CYREG_B0_UDB01_CTL 0x40006471 +#define CYREG_B0_UDB02_CTL 0x40006472 +#define CYREG_B0_UDB03_CTL 0x40006473 +#define CYREG_B0_UDB04_CTL 0x40006474 +#define CYREG_B0_UDB05_CTL 0x40006475 +#define CYREG_B0_UDB06_CTL 0x40006476 +#define CYREG_B0_UDB07_CTL 0x40006477 +#define CYREG_B0_UDB08_CTL 0x40006478 +#define CYREG_B0_UDB09_CTL 0x40006479 +#define CYREG_B0_UDB10_CTL 0x4000647a +#define CYREG_B0_UDB11_CTL 0x4000647b +#define CYREG_B0_UDB12_CTL 0x4000647c +#define CYREG_B0_UDB13_CTL 0x4000647d +#define CYREG_B0_UDB14_CTL 0x4000647e +#define CYREG_B0_UDB15_CTL 0x4000647f +#define CYREG_B0_UDB00_MSK 0x40006480 +#define CYREG_B0_UDB01_MSK 0x40006481 +#define CYREG_B0_UDB02_MSK 0x40006482 +#define CYREG_B0_UDB03_MSK 0x40006483 +#define CYREG_B0_UDB04_MSK 0x40006484 +#define CYREG_B0_UDB05_MSK 0x40006485 +#define CYREG_B0_UDB06_MSK 0x40006486 +#define CYREG_B0_UDB07_MSK 0x40006487 +#define CYREG_B0_UDB08_MSK 0x40006488 +#define CYREG_B0_UDB09_MSK 0x40006489 +#define CYREG_B0_UDB10_MSK 0x4000648a +#define CYREG_B0_UDB11_MSK 0x4000648b +#define CYREG_B0_UDB12_MSK 0x4000648c +#define CYREG_B0_UDB13_MSK 0x4000648d +#define CYREG_B0_UDB14_MSK 0x4000648e +#define CYREG_B0_UDB15_MSK 0x4000648f +#define CYREG_B0_UDB00_ACTL 0x40006490 +#define CYREG_B0_UDB01_ACTL 0x40006491 +#define CYREG_B0_UDB02_ACTL 0x40006492 +#define CYREG_B0_UDB03_ACTL 0x40006493 +#define CYREG_B0_UDB04_ACTL 0x40006494 +#define CYREG_B0_UDB05_ACTL 0x40006495 +#define CYREG_B0_UDB06_ACTL 0x40006496 +#define CYREG_B0_UDB07_ACTL 0x40006497 +#define CYREG_B0_UDB08_ACTL 0x40006498 +#define CYREG_B0_UDB09_ACTL 0x40006499 +#define CYREG_B0_UDB10_ACTL 0x4000649a +#define CYREG_B0_UDB11_ACTL 0x4000649b +#define CYREG_B0_UDB12_ACTL 0x4000649c +#define CYREG_B0_UDB13_ACTL 0x4000649d +#define CYREG_B0_UDB14_ACTL 0x4000649e +#define CYREG_B0_UDB15_ACTL 0x4000649f +#define CYREG_B0_UDB00_MC 0x400064a0 +#define CYREG_B0_UDB01_MC 0x400064a1 +#define CYREG_B0_UDB02_MC 0x400064a2 +#define CYREG_B0_UDB03_MC 0x400064a3 +#define CYREG_B0_UDB04_MC 0x400064a4 +#define CYREG_B0_UDB05_MC 0x400064a5 +#define CYREG_B0_UDB06_MC 0x400064a6 +#define CYREG_B0_UDB07_MC 0x400064a7 +#define CYREG_B0_UDB08_MC 0x400064a8 +#define CYREG_B0_UDB09_MC 0x400064a9 +#define CYREG_B0_UDB10_MC 0x400064aa +#define CYREG_B0_UDB11_MC 0x400064ab +#define CYREG_B0_UDB12_MC 0x400064ac +#define CYREG_B0_UDB13_MC 0x400064ad +#define CYREG_B0_UDB14_MC 0x400064ae +#define CYREG_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYREG_B1_UDB04_A0 0x40006504 +#define CYREG_B1_UDB05_A0 0x40006505 +#define CYREG_B1_UDB06_A0 0x40006506 +#define CYREG_B1_UDB07_A0 0x40006507 +#define CYREG_B1_UDB08_A0 0x40006508 +#define CYREG_B1_UDB09_A0 0x40006509 +#define CYREG_B1_UDB10_A0 0x4000650a +#define CYREG_B1_UDB11_A0 0x4000650b +#define CYREG_B1_UDB04_A1 0x40006514 +#define CYREG_B1_UDB05_A1 0x40006515 +#define CYREG_B1_UDB06_A1 0x40006516 +#define CYREG_B1_UDB07_A1 0x40006517 +#define CYREG_B1_UDB08_A1 0x40006518 +#define CYREG_B1_UDB09_A1 0x40006519 +#define CYREG_B1_UDB10_A1 0x4000651a +#define CYREG_B1_UDB11_A1 0x4000651b +#define CYREG_B1_UDB04_D0 0x40006524 +#define CYREG_B1_UDB05_D0 0x40006525 +#define CYREG_B1_UDB06_D0 0x40006526 +#define CYREG_B1_UDB07_D0 0x40006527 +#define CYREG_B1_UDB08_D0 0x40006528 +#define CYREG_B1_UDB09_D0 0x40006529 +#define CYREG_B1_UDB10_D0 0x4000652a +#define CYREG_B1_UDB11_D0 0x4000652b +#define CYREG_B1_UDB04_D1 0x40006534 +#define CYREG_B1_UDB05_D1 0x40006535 +#define CYREG_B1_UDB06_D1 0x40006536 +#define CYREG_B1_UDB07_D1 0x40006537 +#define CYREG_B1_UDB08_D1 0x40006538 +#define CYREG_B1_UDB09_D1 0x40006539 +#define CYREG_B1_UDB10_D1 0x4000653a +#define CYREG_B1_UDB11_D1 0x4000653b +#define CYREG_B1_UDB04_F0 0x40006544 +#define CYREG_B1_UDB05_F0 0x40006545 +#define CYREG_B1_UDB06_F0 0x40006546 +#define CYREG_B1_UDB07_F0 0x40006547 +#define CYREG_B1_UDB08_F0 0x40006548 +#define CYREG_B1_UDB09_F0 0x40006549 +#define CYREG_B1_UDB10_F0 0x4000654a +#define CYREG_B1_UDB11_F0 0x4000654b +#define CYREG_B1_UDB04_F1 0x40006554 +#define CYREG_B1_UDB05_F1 0x40006555 +#define CYREG_B1_UDB06_F1 0x40006556 +#define CYREG_B1_UDB07_F1 0x40006557 +#define CYREG_B1_UDB08_F1 0x40006558 +#define CYREG_B1_UDB09_F1 0x40006559 +#define CYREG_B1_UDB10_F1 0x4000655a +#define CYREG_B1_UDB11_F1 0x4000655b +#define CYREG_B1_UDB04_ST 0x40006564 +#define CYREG_B1_UDB05_ST 0x40006565 +#define CYREG_B1_UDB06_ST 0x40006566 +#define CYREG_B1_UDB07_ST 0x40006567 +#define CYREG_B1_UDB08_ST 0x40006568 +#define CYREG_B1_UDB09_ST 0x40006569 +#define CYREG_B1_UDB10_ST 0x4000656a +#define CYREG_B1_UDB11_ST 0x4000656b +#define CYREG_B1_UDB04_CTL 0x40006574 +#define CYREG_B1_UDB05_CTL 0x40006575 +#define CYREG_B1_UDB06_CTL 0x40006576 +#define CYREG_B1_UDB07_CTL 0x40006577 +#define CYREG_B1_UDB08_CTL 0x40006578 +#define CYREG_B1_UDB09_CTL 0x40006579 +#define CYREG_B1_UDB10_CTL 0x4000657a +#define CYREG_B1_UDB11_CTL 0x4000657b +#define CYREG_B1_UDB04_MSK 0x40006584 +#define CYREG_B1_UDB05_MSK 0x40006585 +#define CYREG_B1_UDB06_MSK 0x40006586 +#define CYREG_B1_UDB07_MSK 0x40006587 +#define CYREG_B1_UDB08_MSK 0x40006588 +#define CYREG_B1_UDB09_MSK 0x40006589 +#define CYREG_B1_UDB10_MSK 0x4000658a +#define CYREG_B1_UDB11_MSK 0x4000658b +#define CYREG_B1_UDB04_ACTL 0x40006594 +#define CYREG_B1_UDB05_ACTL 0x40006595 +#define CYREG_B1_UDB06_ACTL 0x40006596 +#define CYREG_B1_UDB07_ACTL 0x40006597 +#define CYREG_B1_UDB08_ACTL 0x40006598 +#define CYREG_B1_UDB09_ACTL 0x40006599 +#define CYREG_B1_UDB10_ACTL 0x4000659a +#define CYREG_B1_UDB11_ACTL 0x4000659b +#define CYREG_B1_UDB04_MC 0x400065a4 +#define CYREG_B1_UDB05_MC 0x400065a5 +#define CYREG_B1_UDB06_MC 0x400065a6 +#define CYREG_B1_UDB07_MC 0x400065a7 +#define CYREG_B1_UDB08_MC 0x400065a8 +#define CYREG_B1_UDB09_MC 0x400065a9 +#define CYREG_B1_UDB10_MC 0x400065aa +#define CYREG_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYREG_B0_UDB00_A0_A1 0x40006800 +#define CYREG_B0_UDB01_A0_A1 0x40006802 +#define CYREG_B0_UDB02_A0_A1 0x40006804 +#define CYREG_B0_UDB03_A0_A1 0x40006806 +#define CYREG_B0_UDB04_A0_A1 0x40006808 +#define CYREG_B0_UDB05_A0_A1 0x4000680a +#define CYREG_B0_UDB06_A0_A1 0x4000680c +#define CYREG_B0_UDB07_A0_A1 0x4000680e +#define CYREG_B0_UDB08_A0_A1 0x40006810 +#define CYREG_B0_UDB09_A0_A1 0x40006812 +#define CYREG_B0_UDB10_A0_A1 0x40006814 +#define CYREG_B0_UDB11_A0_A1 0x40006816 +#define CYREG_B0_UDB12_A0_A1 0x40006818 +#define CYREG_B0_UDB13_A0_A1 0x4000681a +#define CYREG_B0_UDB14_A0_A1 0x4000681c +#define CYREG_B0_UDB15_A0_A1 0x4000681e +#define CYREG_B0_UDB00_D0_D1 0x40006840 +#define CYREG_B0_UDB01_D0_D1 0x40006842 +#define CYREG_B0_UDB02_D0_D1 0x40006844 +#define CYREG_B0_UDB03_D0_D1 0x40006846 +#define CYREG_B0_UDB04_D0_D1 0x40006848 +#define CYREG_B0_UDB05_D0_D1 0x4000684a +#define CYREG_B0_UDB06_D0_D1 0x4000684c +#define CYREG_B0_UDB07_D0_D1 0x4000684e +#define CYREG_B0_UDB08_D0_D1 0x40006850 +#define CYREG_B0_UDB09_D0_D1 0x40006852 +#define CYREG_B0_UDB10_D0_D1 0x40006854 +#define CYREG_B0_UDB11_D0_D1 0x40006856 +#define CYREG_B0_UDB12_D0_D1 0x40006858 +#define CYREG_B0_UDB13_D0_D1 0x4000685a +#define CYREG_B0_UDB14_D0_D1 0x4000685c +#define CYREG_B0_UDB15_D0_D1 0x4000685e +#define CYREG_B0_UDB00_F0_F1 0x40006880 +#define CYREG_B0_UDB01_F0_F1 0x40006882 +#define CYREG_B0_UDB02_F0_F1 0x40006884 +#define CYREG_B0_UDB03_F0_F1 0x40006886 +#define CYREG_B0_UDB04_F0_F1 0x40006888 +#define CYREG_B0_UDB05_F0_F1 0x4000688a +#define CYREG_B0_UDB06_F0_F1 0x4000688c +#define CYREG_B0_UDB07_F0_F1 0x4000688e +#define CYREG_B0_UDB08_F0_F1 0x40006890 +#define CYREG_B0_UDB09_F0_F1 0x40006892 +#define CYREG_B0_UDB10_F0_F1 0x40006894 +#define CYREG_B0_UDB11_F0_F1 0x40006896 +#define CYREG_B0_UDB12_F0_F1 0x40006898 +#define CYREG_B0_UDB13_F0_F1 0x4000689a +#define CYREG_B0_UDB14_F0_F1 0x4000689c +#define CYREG_B0_UDB15_F0_F1 0x4000689e +#define CYREG_B0_UDB00_ST_CTL 0x400068c0 +#define CYREG_B0_UDB01_ST_CTL 0x400068c2 +#define CYREG_B0_UDB02_ST_CTL 0x400068c4 +#define CYREG_B0_UDB03_ST_CTL 0x400068c6 +#define CYREG_B0_UDB04_ST_CTL 0x400068c8 +#define CYREG_B0_UDB05_ST_CTL 0x400068ca +#define CYREG_B0_UDB06_ST_CTL 0x400068cc +#define CYREG_B0_UDB07_ST_CTL 0x400068ce +#define CYREG_B0_UDB08_ST_CTL 0x400068d0 +#define CYREG_B0_UDB09_ST_CTL 0x400068d2 +#define CYREG_B0_UDB10_ST_CTL 0x400068d4 +#define CYREG_B0_UDB11_ST_CTL 0x400068d6 +#define CYREG_B0_UDB12_ST_CTL 0x400068d8 +#define CYREG_B0_UDB13_ST_CTL 0x400068da +#define CYREG_B0_UDB14_ST_CTL 0x400068dc +#define CYREG_B0_UDB15_ST_CTL 0x400068de +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900 +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902 +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904 +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906 +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908 +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910 +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912 +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914 +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916 +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918 +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e +#define CYREG_B0_UDB00_MC_00 0x40006940 +#define CYREG_B0_UDB01_MC_00 0x40006942 +#define CYREG_B0_UDB02_MC_00 0x40006944 +#define CYREG_B0_UDB03_MC_00 0x40006946 +#define CYREG_B0_UDB04_MC_00 0x40006948 +#define CYREG_B0_UDB05_MC_00 0x4000694a +#define CYREG_B0_UDB06_MC_00 0x4000694c +#define CYREG_B0_UDB07_MC_00 0x4000694e +#define CYREG_B0_UDB08_MC_00 0x40006950 +#define CYREG_B0_UDB09_MC_00 0x40006952 +#define CYREG_B0_UDB10_MC_00 0x40006954 +#define CYREG_B0_UDB11_MC_00 0x40006956 +#define CYREG_B0_UDB12_MC_00 0x40006958 +#define CYREG_B0_UDB13_MC_00 0x4000695a +#define CYREG_B0_UDB14_MC_00 0x4000695c +#define CYREG_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYREG_B1_UDB04_A0_A1 0x40006a08 +#define CYREG_B1_UDB05_A0_A1 0x40006a0a +#define CYREG_B1_UDB06_A0_A1 0x40006a0c +#define CYREG_B1_UDB07_A0_A1 0x40006a0e +#define CYREG_B1_UDB08_A0_A1 0x40006a10 +#define CYREG_B1_UDB09_A0_A1 0x40006a12 +#define CYREG_B1_UDB10_A0_A1 0x40006a14 +#define CYREG_B1_UDB11_A0_A1 0x40006a16 +#define CYREG_B1_UDB04_D0_D1 0x40006a48 +#define CYREG_B1_UDB05_D0_D1 0x40006a4a +#define CYREG_B1_UDB06_D0_D1 0x40006a4c +#define CYREG_B1_UDB07_D0_D1 0x40006a4e +#define CYREG_B1_UDB08_D0_D1 0x40006a50 +#define CYREG_B1_UDB09_D0_D1 0x40006a52 +#define CYREG_B1_UDB10_D0_D1 0x40006a54 +#define CYREG_B1_UDB11_D0_D1 0x40006a56 +#define CYREG_B1_UDB04_F0_F1 0x40006a88 +#define CYREG_B1_UDB05_F0_F1 0x40006a8a +#define CYREG_B1_UDB06_F0_F1 0x40006a8c +#define CYREG_B1_UDB07_F0_F1 0x40006a8e +#define CYREG_B1_UDB08_F0_F1 0x40006a90 +#define CYREG_B1_UDB09_F0_F1 0x40006a92 +#define CYREG_B1_UDB10_F0_F1 0x40006a94 +#define CYREG_B1_UDB11_F0_F1 0x40006a96 +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8 +#define CYREG_B1_UDB05_ST_CTL 0x40006aca +#define CYREG_B1_UDB06_ST_CTL 0x40006acc +#define CYREG_B1_UDB07_ST_CTL 0x40006ace +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0 +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2 +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4 +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6 +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYREG_B1_UDB04_MC_00 0x40006b48 +#define CYREG_B1_UDB05_MC_00 0x40006b4a +#define CYREG_B1_UDB06_MC_00 0x40006b4c +#define CYREG_B1_UDB07_MC_00 0x40006b4e +#define CYREG_B1_UDB08_MC_00 0x40006b50 +#define CYREG_B1_UDB09_MC_00 0x40006b52 +#define CYREG_B1_UDB10_MC_00 0x40006b54 +#define CYREG_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYREG_B0_UDB00_01_A0 0x40006800 +#define CYREG_B0_UDB01_02_A0 0x40006802 +#define CYREG_B0_UDB02_03_A0 0x40006804 +#define CYREG_B0_UDB03_04_A0 0x40006806 +#define CYREG_B0_UDB04_05_A0 0x40006808 +#define CYREG_B0_UDB05_06_A0 0x4000680a +#define CYREG_B0_UDB06_07_A0 0x4000680c +#define CYREG_B0_UDB07_08_A0 0x4000680e +#define CYREG_B0_UDB08_09_A0 0x40006810 +#define CYREG_B0_UDB09_10_A0 0x40006812 +#define CYREG_B0_UDB10_11_A0 0x40006814 +#define CYREG_B0_UDB11_12_A0 0x40006816 +#define CYREG_B0_UDB12_13_A0 0x40006818 +#define CYREG_B0_UDB13_14_A0 0x4000681a +#define CYREG_B0_UDB14_15_A0 0x4000681c +#define CYREG_B0_UDB00_01_A1 0x40006820 +#define CYREG_B0_UDB01_02_A1 0x40006822 +#define CYREG_B0_UDB02_03_A1 0x40006824 +#define CYREG_B0_UDB03_04_A1 0x40006826 +#define CYREG_B0_UDB04_05_A1 0x40006828 +#define CYREG_B0_UDB05_06_A1 0x4000682a +#define CYREG_B0_UDB06_07_A1 0x4000682c +#define CYREG_B0_UDB07_08_A1 0x4000682e +#define CYREG_B0_UDB08_09_A1 0x40006830 +#define CYREG_B0_UDB09_10_A1 0x40006832 +#define CYREG_B0_UDB10_11_A1 0x40006834 +#define CYREG_B0_UDB11_12_A1 0x40006836 +#define CYREG_B0_UDB12_13_A1 0x40006838 +#define CYREG_B0_UDB13_14_A1 0x4000683a +#define CYREG_B0_UDB14_15_A1 0x4000683c +#define CYREG_B0_UDB00_01_D0 0x40006840 +#define CYREG_B0_UDB01_02_D0 0x40006842 +#define CYREG_B0_UDB02_03_D0 0x40006844 +#define CYREG_B0_UDB03_04_D0 0x40006846 +#define CYREG_B0_UDB04_05_D0 0x40006848 +#define CYREG_B0_UDB05_06_D0 0x4000684a +#define CYREG_B0_UDB06_07_D0 0x4000684c +#define CYREG_B0_UDB07_08_D0 0x4000684e +#define CYREG_B0_UDB08_09_D0 0x40006850 +#define CYREG_B0_UDB09_10_D0 0x40006852 +#define CYREG_B0_UDB10_11_D0 0x40006854 +#define CYREG_B0_UDB11_12_D0 0x40006856 +#define CYREG_B0_UDB12_13_D0 0x40006858 +#define CYREG_B0_UDB13_14_D0 0x4000685a +#define CYREG_B0_UDB14_15_D0 0x4000685c +#define CYREG_B0_UDB00_01_D1 0x40006860 +#define CYREG_B0_UDB01_02_D1 0x40006862 +#define CYREG_B0_UDB02_03_D1 0x40006864 +#define CYREG_B0_UDB03_04_D1 0x40006866 +#define CYREG_B0_UDB04_05_D1 0x40006868 +#define CYREG_B0_UDB05_06_D1 0x4000686a +#define CYREG_B0_UDB06_07_D1 0x4000686c +#define CYREG_B0_UDB07_08_D1 0x4000686e +#define CYREG_B0_UDB08_09_D1 0x40006870 +#define CYREG_B0_UDB09_10_D1 0x40006872 +#define CYREG_B0_UDB10_11_D1 0x40006874 +#define CYREG_B0_UDB11_12_D1 0x40006876 +#define CYREG_B0_UDB12_13_D1 0x40006878 +#define CYREG_B0_UDB13_14_D1 0x4000687a +#define CYREG_B0_UDB14_15_D1 0x4000687c +#define CYREG_B0_UDB00_01_F0 0x40006880 +#define CYREG_B0_UDB01_02_F0 0x40006882 +#define CYREG_B0_UDB02_03_F0 0x40006884 +#define CYREG_B0_UDB03_04_F0 0x40006886 +#define CYREG_B0_UDB04_05_F0 0x40006888 +#define CYREG_B0_UDB05_06_F0 0x4000688a +#define CYREG_B0_UDB06_07_F0 0x4000688c +#define CYREG_B0_UDB07_08_F0 0x4000688e +#define CYREG_B0_UDB08_09_F0 0x40006890 +#define CYREG_B0_UDB09_10_F0 0x40006892 +#define CYREG_B0_UDB10_11_F0 0x40006894 +#define CYREG_B0_UDB11_12_F0 0x40006896 +#define CYREG_B0_UDB12_13_F0 0x40006898 +#define CYREG_B0_UDB13_14_F0 0x4000689a +#define CYREG_B0_UDB14_15_F0 0x4000689c +#define CYREG_B0_UDB00_01_F1 0x400068a0 +#define CYREG_B0_UDB01_02_F1 0x400068a2 +#define CYREG_B0_UDB02_03_F1 0x400068a4 +#define CYREG_B0_UDB03_04_F1 0x400068a6 +#define CYREG_B0_UDB04_05_F1 0x400068a8 +#define CYREG_B0_UDB05_06_F1 0x400068aa +#define CYREG_B0_UDB06_07_F1 0x400068ac +#define CYREG_B0_UDB07_08_F1 0x400068ae +#define CYREG_B0_UDB08_09_F1 0x400068b0 +#define CYREG_B0_UDB09_10_F1 0x400068b2 +#define CYREG_B0_UDB10_11_F1 0x400068b4 +#define CYREG_B0_UDB11_12_F1 0x400068b6 +#define CYREG_B0_UDB12_13_F1 0x400068b8 +#define CYREG_B0_UDB13_14_F1 0x400068ba +#define CYREG_B0_UDB14_15_F1 0x400068bc +#define CYREG_B0_UDB00_01_ST 0x400068c0 +#define CYREG_B0_UDB01_02_ST 0x400068c2 +#define CYREG_B0_UDB02_03_ST 0x400068c4 +#define CYREG_B0_UDB03_04_ST 0x400068c6 +#define CYREG_B0_UDB04_05_ST 0x400068c8 +#define CYREG_B0_UDB05_06_ST 0x400068ca +#define CYREG_B0_UDB06_07_ST 0x400068cc +#define CYREG_B0_UDB07_08_ST 0x400068ce +#define CYREG_B0_UDB08_09_ST 0x400068d0 +#define CYREG_B0_UDB09_10_ST 0x400068d2 +#define CYREG_B0_UDB10_11_ST 0x400068d4 +#define CYREG_B0_UDB11_12_ST 0x400068d6 +#define CYREG_B0_UDB12_13_ST 0x400068d8 +#define CYREG_B0_UDB13_14_ST 0x400068da +#define CYREG_B0_UDB14_15_ST 0x400068dc +#define CYREG_B0_UDB00_01_CTL 0x400068e0 +#define CYREG_B0_UDB01_02_CTL 0x400068e2 +#define CYREG_B0_UDB02_03_CTL 0x400068e4 +#define CYREG_B0_UDB03_04_CTL 0x400068e6 +#define CYREG_B0_UDB04_05_CTL 0x400068e8 +#define CYREG_B0_UDB05_06_CTL 0x400068ea +#define CYREG_B0_UDB06_07_CTL 0x400068ec +#define CYREG_B0_UDB07_08_CTL 0x400068ee +#define CYREG_B0_UDB08_09_CTL 0x400068f0 +#define CYREG_B0_UDB09_10_CTL 0x400068f2 +#define CYREG_B0_UDB10_11_CTL 0x400068f4 +#define CYREG_B0_UDB11_12_CTL 0x400068f6 +#define CYREG_B0_UDB12_13_CTL 0x400068f8 +#define CYREG_B0_UDB13_14_CTL 0x400068fa +#define CYREG_B0_UDB14_15_CTL 0x400068fc +#define CYREG_B0_UDB00_01_MSK 0x40006900 +#define CYREG_B0_UDB01_02_MSK 0x40006902 +#define CYREG_B0_UDB02_03_MSK 0x40006904 +#define CYREG_B0_UDB03_04_MSK 0x40006906 +#define CYREG_B0_UDB04_05_MSK 0x40006908 +#define CYREG_B0_UDB05_06_MSK 0x4000690a +#define CYREG_B0_UDB06_07_MSK 0x4000690c +#define CYREG_B0_UDB07_08_MSK 0x4000690e +#define CYREG_B0_UDB08_09_MSK 0x40006910 +#define CYREG_B0_UDB09_10_MSK 0x40006912 +#define CYREG_B0_UDB10_11_MSK 0x40006914 +#define CYREG_B0_UDB11_12_MSK 0x40006916 +#define CYREG_B0_UDB12_13_MSK 0x40006918 +#define CYREG_B0_UDB13_14_MSK 0x4000691a +#define CYREG_B0_UDB14_15_MSK 0x4000691c +#define CYREG_B0_UDB00_01_ACTL 0x40006920 +#define CYREG_B0_UDB01_02_ACTL 0x40006922 +#define CYREG_B0_UDB02_03_ACTL 0x40006924 +#define CYREG_B0_UDB03_04_ACTL 0x40006926 +#define CYREG_B0_UDB04_05_ACTL 0x40006928 +#define CYREG_B0_UDB05_06_ACTL 0x4000692a +#define CYREG_B0_UDB06_07_ACTL 0x4000692c +#define CYREG_B0_UDB07_08_ACTL 0x4000692e +#define CYREG_B0_UDB08_09_ACTL 0x40006930 +#define CYREG_B0_UDB09_10_ACTL 0x40006932 +#define CYREG_B0_UDB10_11_ACTL 0x40006934 +#define CYREG_B0_UDB11_12_ACTL 0x40006936 +#define CYREG_B0_UDB12_13_ACTL 0x40006938 +#define CYREG_B0_UDB13_14_ACTL 0x4000693a +#define CYREG_B0_UDB14_15_ACTL 0x4000693c +#define CYREG_B0_UDB00_01_MC 0x40006940 +#define CYREG_B0_UDB01_02_MC 0x40006942 +#define CYREG_B0_UDB02_03_MC 0x40006944 +#define CYREG_B0_UDB03_04_MC 0x40006946 +#define CYREG_B0_UDB04_05_MC 0x40006948 +#define CYREG_B0_UDB05_06_MC 0x4000694a +#define CYREG_B0_UDB06_07_MC 0x4000694c +#define CYREG_B0_UDB07_08_MC 0x4000694e +#define CYREG_B0_UDB08_09_MC 0x40006950 +#define CYREG_B0_UDB09_10_MC 0x40006952 +#define CYREG_B0_UDB10_11_MC 0x40006954 +#define CYREG_B0_UDB11_12_MC 0x40006956 +#define CYREG_B0_UDB12_13_MC 0x40006958 +#define CYREG_B0_UDB13_14_MC 0x4000695a +#define CYREG_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYREG_B1_UDB04_05_A0 0x40006a08 +#define CYREG_B1_UDB05_06_A0 0x40006a0a +#define CYREG_B1_UDB06_07_A0 0x40006a0c +#define CYREG_B1_UDB07_08_A0 0x40006a0e +#define CYREG_B1_UDB08_09_A0 0x40006a10 +#define CYREG_B1_UDB09_10_A0 0x40006a12 +#define CYREG_B1_UDB10_11_A0 0x40006a14 +#define CYREG_B1_UDB11_12_A0 0x40006a16 +#define CYREG_B1_UDB04_05_A1 0x40006a28 +#define CYREG_B1_UDB05_06_A1 0x40006a2a +#define CYREG_B1_UDB06_07_A1 0x40006a2c +#define CYREG_B1_UDB07_08_A1 0x40006a2e +#define CYREG_B1_UDB08_09_A1 0x40006a30 +#define CYREG_B1_UDB09_10_A1 0x40006a32 +#define CYREG_B1_UDB10_11_A1 0x40006a34 +#define CYREG_B1_UDB11_12_A1 0x40006a36 +#define CYREG_B1_UDB04_05_D0 0x40006a48 +#define CYREG_B1_UDB05_06_D0 0x40006a4a +#define CYREG_B1_UDB06_07_D0 0x40006a4c +#define CYREG_B1_UDB07_08_D0 0x40006a4e +#define CYREG_B1_UDB08_09_D0 0x40006a50 +#define CYREG_B1_UDB09_10_D0 0x40006a52 +#define CYREG_B1_UDB10_11_D0 0x40006a54 +#define CYREG_B1_UDB11_12_D0 0x40006a56 +#define CYREG_B1_UDB04_05_D1 0x40006a68 +#define CYREG_B1_UDB05_06_D1 0x40006a6a +#define CYREG_B1_UDB06_07_D1 0x40006a6c +#define CYREG_B1_UDB07_08_D1 0x40006a6e +#define CYREG_B1_UDB08_09_D1 0x40006a70 +#define CYREG_B1_UDB09_10_D1 0x40006a72 +#define CYREG_B1_UDB10_11_D1 0x40006a74 +#define CYREG_B1_UDB11_12_D1 0x40006a76 +#define CYREG_B1_UDB04_05_F0 0x40006a88 +#define CYREG_B1_UDB05_06_F0 0x40006a8a +#define CYREG_B1_UDB06_07_F0 0x40006a8c +#define CYREG_B1_UDB07_08_F0 0x40006a8e +#define CYREG_B1_UDB08_09_F0 0x40006a90 +#define CYREG_B1_UDB09_10_F0 0x40006a92 +#define CYREG_B1_UDB10_11_F0 0x40006a94 +#define CYREG_B1_UDB11_12_F0 0x40006a96 +#define CYREG_B1_UDB04_05_F1 0x40006aa8 +#define CYREG_B1_UDB05_06_F1 0x40006aaa +#define CYREG_B1_UDB06_07_F1 0x40006aac +#define CYREG_B1_UDB07_08_F1 0x40006aae +#define CYREG_B1_UDB08_09_F1 0x40006ab0 +#define CYREG_B1_UDB09_10_F1 0x40006ab2 +#define CYREG_B1_UDB10_11_F1 0x40006ab4 +#define CYREG_B1_UDB11_12_F1 0x40006ab6 +#define CYREG_B1_UDB04_05_ST 0x40006ac8 +#define CYREG_B1_UDB05_06_ST 0x40006aca +#define CYREG_B1_UDB06_07_ST 0x40006acc +#define CYREG_B1_UDB07_08_ST 0x40006ace +#define CYREG_B1_UDB08_09_ST 0x40006ad0 +#define CYREG_B1_UDB09_10_ST 0x40006ad2 +#define CYREG_B1_UDB10_11_ST 0x40006ad4 +#define CYREG_B1_UDB11_12_ST 0x40006ad6 +#define CYREG_B1_UDB04_05_CTL 0x40006ae8 +#define CYREG_B1_UDB05_06_CTL 0x40006aea +#define CYREG_B1_UDB06_07_CTL 0x40006aec +#define CYREG_B1_UDB07_08_CTL 0x40006aee +#define CYREG_B1_UDB08_09_CTL 0x40006af0 +#define CYREG_B1_UDB09_10_CTL 0x40006af2 +#define CYREG_B1_UDB10_11_CTL 0x40006af4 +#define CYREG_B1_UDB11_12_CTL 0x40006af6 +#define CYREG_B1_UDB04_05_MSK 0x40006b08 +#define CYREG_B1_UDB05_06_MSK 0x40006b0a +#define CYREG_B1_UDB06_07_MSK 0x40006b0c +#define CYREG_B1_UDB07_08_MSK 0x40006b0e +#define CYREG_B1_UDB08_09_MSK 0x40006b10 +#define CYREG_B1_UDB09_10_MSK 0x40006b12 +#define CYREG_B1_UDB10_11_MSK 0x40006b14 +#define CYREG_B1_UDB11_12_MSK 0x40006b16 +#define CYREG_B1_UDB04_05_ACTL 0x40006b28 +#define CYREG_B1_UDB05_06_ACTL 0x40006b2a +#define CYREG_B1_UDB06_07_ACTL 0x40006b2c +#define CYREG_B1_UDB07_08_ACTL 0x40006b2e +#define CYREG_B1_UDB08_09_ACTL 0x40006b30 +#define CYREG_B1_UDB09_10_ACTL 0x40006b32 +#define CYREG_B1_UDB10_11_ACTL 0x40006b34 +#define CYREG_B1_UDB11_12_ACTL 0x40006b36 +#define CYREG_B1_UDB04_05_MC 0x40006b48 +#define CYREG_B1_UDB05_06_MC 0x40006b4a +#define CYREG_B1_UDB06_07_MC 0x40006b4c +#define CYREG_B1_UDB07_08_MC 0x40006b4e +#define CYREG_B1_UDB08_09_MC 0x40006b50 +#define CYREG_B1_UDB09_10_MC 0x40006b52 +#define CYREG_B1_UDB10_11_MC 0x40006b54 +#define CYREG_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYREG_PHUB_CFG 0x40007000 +#define CYREG_PHUB_ERR 0x40007004 +#define CYREG_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYREG_PHUB_CH0_ACTION 0x40007014 +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYREG_PHUB_CH1_ACTION 0x40007024 +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYREG_PHUB_CH2_ACTION 0x40007034 +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYREG_PHUB_CH3_ACTION 0x40007044 +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYREG_PHUB_CH4_ACTION 0x40007054 +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYREG_PHUB_CH5_ACTION 0x40007064 +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYREG_PHUB_CH6_ACTION 0x40007074 +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYREG_PHUB_CH7_ACTION 0x40007084 +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYREG_PHUB_CH8_ACTION 0x40007094 +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYREG_PHUB_CH9_ACTION 0x400070a4 +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYREG_PHUB_CH10_ACTION 0x400070b4 +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYREG_PHUB_CH11_ACTION 0x400070c4 +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYREG_PHUB_CH12_ACTION 0x400070d4 +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYREG_PHUB_CH13_ACTION 0x400070e4 +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYREG_PHUB_CH14_ACTION 0x400070f4 +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYREG_PHUB_CH15_ACTION 0x40007104 +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYREG_PHUB_CH16_ACTION 0x40007114 +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYREG_PHUB_CH17_ACTION 0x40007124 +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYREG_PHUB_CH18_ACTION 0x40007134 +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYREG_PHUB_CH19_ACTION 0x40007144 +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYREG_PHUB_CH20_ACTION 0x40007154 +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYREG_PHUB_CH21_ACTION 0x40007164 +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYREG_PHUB_CH22_ACTION 0x40007174 +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYREG_PHUB_CH23_ACTION 0x40007184 +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYREG_EE_DATA_MBASE 0x40008000 +#define CYREG_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYREG_CAN0_CSR_INT_SR 0x4000a000 +#define CYREG_CAN0_CSR_INT_EN 0x4000a004 +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008 +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c +#define CYREG_CAN0_CSR_CMD 0x4000a010 +#define CYREG_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYREG_CAN0_TX0_CMD 0x4000a020 +#define CYREG_CAN0_TX0_ID 0x4000a024 +#define CYREG_CAN0_TX0_DH 0x4000a028 +#define CYREG_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYREG_CAN0_TX1_CMD 0x4000a030 +#define CYREG_CAN0_TX1_ID 0x4000a034 +#define CYREG_CAN0_TX1_DH 0x4000a038 +#define CYREG_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYREG_CAN0_TX2_CMD 0x4000a040 +#define CYREG_CAN0_TX2_ID 0x4000a044 +#define CYREG_CAN0_TX2_DH 0x4000a048 +#define CYREG_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYREG_CAN0_TX3_CMD 0x4000a050 +#define CYREG_CAN0_TX3_ID 0x4000a054 +#define CYREG_CAN0_TX3_DH 0x4000a058 +#define CYREG_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYREG_CAN0_TX4_CMD 0x4000a060 +#define CYREG_CAN0_TX4_ID 0x4000a064 +#define CYREG_CAN0_TX4_DH 0x4000a068 +#define CYREG_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYREG_CAN0_TX5_CMD 0x4000a070 +#define CYREG_CAN0_TX5_ID 0x4000a074 +#define CYREG_CAN0_TX5_DH 0x4000a078 +#define CYREG_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYREG_CAN0_TX6_CMD 0x4000a080 +#define CYREG_CAN0_TX6_ID 0x4000a084 +#define CYREG_CAN0_TX6_DH 0x4000a088 +#define CYREG_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYREG_CAN0_TX7_CMD 0x4000a090 +#define CYREG_CAN0_TX7_ID 0x4000a094 +#define CYREG_CAN0_TX7_DH 0x4000a098 +#define CYREG_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYREG_CAN0_RX0_CMD 0x4000a0a0 +#define CYREG_CAN0_RX0_ID 0x4000a0a4 +#define CYREG_CAN0_RX0_DH 0x4000a0a8 +#define CYREG_CAN0_RX0_DL 0x4000a0ac +#define CYREG_CAN0_RX0_AMR 0x4000a0b0 +#define CYREG_CAN0_RX0_ACR 0x4000a0b4 +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8 +#define CYREG_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYREG_CAN0_RX1_CMD 0x4000a0c0 +#define CYREG_CAN0_RX1_ID 0x4000a0c4 +#define CYREG_CAN0_RX1_DH 0x4000a0c8 +#define CYREG_CAN0_RX1_DL 0x4000a0cc +#define CYREG_CAN0_RX1_AMR 0x4000a0d0 +#define CYREG_CAN0_RX1_ACR 0x4000a0d4 +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8 +#define CYREG_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYREG_CAN0_RX2_CMD 0x4000a0e0 +#define CYREG_CAN0_RX2_ID 0x4000a0e4 +#define CYREG_CAN0_RX2_DH 0x4000a0e8 +#define CYREG_CAN0_RX2_DL 0x4000a0ec +#define CYREG_CAN0_RX2_AMR 0x4000a0f0 +#define CYREG_CAN0_RX2_ACR 0x4000a0f4 +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8 +#define CYREG_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYREG_CAN0_RX3_CMD 0x4000a100 +#define CYREG_CAN0_RX3_ID 0x4000a104 +#define CYREG_CAN0_RX3_DH 0x4000a108 +#define CYREG_CAN0_RX3_DL 0x4000a10c +#define CYREG_CAN0_RX3_AMR 0x4000a110 +#define CYREG_CAN0_RX3_ACR 0x4000a114 +#define CYREG_CAN0_RX3_AMRD 0x4000a118 +#define CYREG_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYREG_CAN0_RX4_CMD 0x4000a120 +#define CYREG_CAN0_RX4_ID 0x4000a124 +#define CYREG_CAN0_RX4_DH 0x4000a128 +#define CYREG_CAN0_RX4_DL 0x4000a12c +#define CYREG_CAN0_RX4_AMR 0x4000a130 +#define CYREG_CAN0_RX4_ACR 0x4000a134 +#define CYREG_CAN0_RX4_AMRD 0x4000a138 +#define CYREG_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYREG_CAN0_RX5_CMD 0x4000a140 +#define CYREG_CAN0_RX5_ID 0x4000a144 +#define CYREG_CAN0_RX5_DH 0x4000a148 +#define CYREG_CAN0_RX5_DL 0x4000a14c +#define CYREG_CAN0_RX5_AMR 0x4000a150 +#define CYREG_CAN0_RX5_ACR 0x4000a154 +#define CYREG_CAN0_RX5_AMRD 0x4000a158 +#define CYREG_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYREG_CAN0_RX6_CMD 0x4000a160 +#define CYREG_CAN0_RX6_ID 0x4000a164 +#define CYREG_CAN0_RX6_DH 0x4000a168 +#define CYREG_CAN0_RX6_DL 0x4000a16c +#define CYREG_CAN0_RX6_AMR 0x4000a170 +#define CYREG_CAN0_RX6_ACR 0x4000a174 +#define CYREG_CAN0_RX6_AMRD 0x4000a178 +#define CYREG_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYREG_CAN0_RX7_CMD 0x4000a180 +#define CYREG_CAN0_RX7_ID 0x4000a184 +#define CYREG_CAN0_RX7_DH 0x4000a188 +#define CYREG_CAN0_RX7_DL 0x4000a18c +#define CYREG_CAN0_RX7_AMR 0x4000a190 +#define CYREG_CAN0_RX7_ACR 0x4000a194 +#define CYREG_CAN0_RX7_AMRD 0x4000a198 +#define CYREG_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYREG_CAN0_RX8_CMD 0x4000a1a0 +#define CYREG_CAN0_RX8_ID 0x4000a1a4 +#define CYREG_CAN0_RX8_DH 0x4000a1a8 +#define CYREG_CAN0_RX8_DL 0x4000a1ac +#define CYREG_CAN0_RX8_AMR 0x4000a1b0 +#define CYREG_CAN0_RX8_ACR 0x4000a1b4 +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8 +#define CYREG_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYREG_CAN0_RX9_CMD 0x4000a1c0 +#define CYREG_CAN0_RX9_ID 0x4000a1c4 +#define CYREG_CAN0_RX9_DH 0x4000a1c8 +#define CYREG_CAN0_RX9_DL 0x4000a1cc +#define CYREG_CAN0_RX9_AMR 0x4000a1d0 +#define CYREG_CAN0_RX9_ACR 0x4000a1d4 +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8 +#define CYREG_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYREG_CAN0_RX10_CMD 0x4000a1e0 +#define CYREG_CAN0_RX10_ID 0x4000a1e4 +#define CYREG_CAN0_RX10_DH 0x4000a1e8 +#define CYREG_CAN0_RX10_DL 0x4000a1ec +#define CYREG_CAN0_RX10_AMR 0x4000a1f0 +#define CYREG_CAN0_RX10_ACR 0x4000a1f4 +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8 +#define CYREG_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYREG_CAN0_RX11_CMD 0x4000a200 +#define CYREG_CAN0_RX11_ID 0x4000a204 +#define CYREG_CAN0_RX11_DH 0x4000a208 +#define CYREG_CAN0_RX11_DL 0x4000a20c +#define CYREG_CAN0_RX11_AMR 0x4000a210 +#define CYREG_CAN0_RX11_ACR 0x4000a214 +#define CYREG_CAN0_RX11_AMRD 0x4000a218 +#define CYREG_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYREG_CAN0_RX12_CMD 0x4000a220 +#define CYREG_CAN0_RX12_ID 0x4000a224 +#define CYREG_CAN0_RX12_DH 0x4000a228 +#define CYREG_CAN0_RX12_DL 0x4000a22c +#define CYREG_CAN0_RX12_AMR 0x4000a230 +#define CYREG_CAN0_RX12_ACR 0x4000a234 +#define CYREG_CAN0_RX12_AMRD 0x4000a238 +#define CYREG_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYREG_CAN0_RX13_CMD 0x4000a240 +#define CYREG_CAN0_RX13_ID 0x4000a244 +#define CYREG_CAN0_RX13_DH 0x4000a248 +#define CYREG_CAN0_RX13_DL 0x4000a24c +#define CYREG_CAN0_RX13_AMR 0x4000a250 +#define CYREG_CAN0_RX13_ACR 0x4000a254 +#define CYREG_CAN0_RX13_AMRD 0x4000a258 +#define CYREG_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYREG_CAN0_RX14_CMD 0x4000a260 +#define CYREG_CAN0_RX14_ID 0x4000a264 +#define CYREG_CAN0_RX14_DH 0x4000a268 +#define CYREG_CAN0_RX14_DL 0x4000a26c +#define CYREG_CAN0_RX14_AMR 0x4000a270 +#define CYREG_CAN0_RX14_ACR 0x4000a274 +#define CYREG_CAN0_RX14_AMRD 0x4000a278 +#define CYREG_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYREG_CAN0_RX15_CMD 0x4000a280 +#define CYREG_CAN0_RX15_ID 0x4000a284 +#define CYREG_CAN0_RX15_DH 0x4000a288 +#define CYREG_CAN0_RX15_DL 0x4000a28c +#define CYREG_CAN0_RX15_AMR 0x4000a290 +#define CYREG_CAN0_RX15_ACR 0x4000a294 +#define CYREG_CAN0_RX15_AMRD 0x4000a298 +#define CYREG_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYREG_DFB0_CR 0x4000c780 +#define CYREG_DFB0_SR 0x4000c784 +#define CYREG_DFB0_RAM_EN 0x4000c788 +#define CYREG_DFB0_RAM_DIR 0x4000c78c +#define CYREG_DFB0_SEMA 0x4000c790 +#define CYREG_DFB0_DSI_CTRL 0x4000c794 +#define CYREG_DFB0_INT_CTRL 0x4000c798 +#define CYREG_DFB0_DMA_CTRL 0x4000c79c +#define CYREG_DFB0_STAGEA 0x4000c7a0 +#define CYREG_DFB0_STAGEAM 0x4000c7a1 +#define CYREG_DFB0_STAGEAH 0x4000c7a2 +#define CYREG_DFB0_STAGEB 0x4000c7a4 +#define CYREG_DFB0_STAGEBM 0x4000c7a5 +#define CYREG_DFB0_STAGEBH 0x4000c7a6 +#define CYREG_DFB0_HOLDA 0x4000c7a8 +#define CYREG_DFB0_HOLDAM 0x4000c7a9 +#define CYREG_DFB0_HOLDAH 0x4000c7aa +#define CYREG_DFB0_HOLDAS 0x4000c7ab +#define CYREG_DFB0_HOLDB 0x4000c7ac +#define CYREG_DFB0_HOLDBM 0x4000c7ad +#define CYREG_DFB0_HOLDBH 0x4000c7ae +#define CYREG_DFB0_HOLDBS 0x4000c7af +#define CYREG_DFB0_COHER 0x4000c7b0 +#define CYREG_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYREG_B0_P0_U0_CFG0 0x40010040 +#define CYREG_B0_P0_U0_CFG1 0x40010041 +#define CYREG_B0_P0_U0_CFG2 0x40010042 +#define CYREG_B0_P0_U0_CFG3 0x40010043 +#define CYREG_B0_P0_U0_CFG4 0x40010044 +#define CYREG_B0_P0_U0_CFG5 0x40010045 +#define CYREG_B0_P0_U0_CFG6 0x40010046 +#define CYREG_B0_P0_U0_CFG7 0x40010047 +#define CYREG_B0_P0_U0_CFG8 0x40010048 +#define CYREG_B0_P0_U0_CFG9 0x40010049 +#define CYREG_B0_P0_U0_CFG10 0x4001004a +#define CYREG_B0_P0_U0_CFG11 0x4001004b +#define CYREG_B0_P0_U0_CFG12 0x4001004c +#define CYREG_B0_P0_U0_CFG13 0x4001004d +#define CYREG_B0_P0_U0_CFG14 0x4001004e +#define CYREG_B0_P0_U0_CFG15 0x4001004f +#define CYREG_B0_P0_U0_CFG16 0x40010050 +#define CYREG_B0_P0_U0_CFG17 0x40010051 +#define CYREG_B0_P0_U0_CFG18 0x40010052 +#define CYREG_B0_P0_U0_CFG19 0x40010053 +#define CYREG_B0_P0_U0_CFG20 0x40010054 +#define CYREG_B0_P0_U0_CFG21 0x40010055 +#define CYREG_B0_P0_U0_CFG22 0x40010056 +#define CYREG_B0_P0_U0_CFG23 0x40010057 +#define CYREG_B0_P0_U0_CFG24 0x40010058 +#define CYREG_B0_P0_U0_CFG25 0x40010059 +#define CYREG_B0_P0_U0_CFG26 0x4001005a +#define CYREG_B0_P0_U0_CFG27 0x4001005b +#define CYREG_B0_P0_U0_CFG28 0x4001005c +#define CYREG_B0_P0_U0_CFG29 0x4001005d +#define CYREG_B0_P0_U0_CFG30 0x4001005e +#define CYREG_B0_P0_U0_CFG31 0x4001005f +#define CYREG_B0_P0_U0_DCFG0 0x40010060 +#define CYREG_B0_P0_U0_DCFG1 0x40010062 +#define CYREG_B0_P0_U0_DCFG2 0x40010064 +#define CYREG_B0_P0_U0_DCFG3 0x40010066 +#define CYREG_B0_P0_U0_DCFG4 0x40010068 +#define CYREG_B0_P0_U0_DCFG5 0x4001006a +#define CYREG_B0_P0_U0_DCFG6 0x4001006c +#define CYREG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYREG_B0_P0_U1_CFG0 0x400100c0 +#define CYREG_B0_P0_U1_CFG1 0x400100c1 +#define CYREG_B0_P0_U1_CFG2 0x400100c2 +#define CYREG_B0_P0_U1_CFG3 0x400100c3 +#define CYREG_B0_P0_U1_CFG4 0x400100c4 +#define CYREG_B0_P0_U1_CFG5 0x400100c5 +#define CYREG_B0_P0_U1_CFG6 0x400100c6 +#define CYREG_B0_P0_U1_CFG7 0x400100c7 +#define CYREG_B0_P0_U1_CFG8 0x400100c8 +#define CYREG_B0_P0_U1_CFG9 0x400100c9 +#define CYREG_B0_P0_U1_CFG10 0x400100ca +#define CYREG_B0_P0_U1_CFG11 0x400100cb +#define CYREG_B0_P0_U1_CFG12 0x400100cc +#define CYREG_B0_P0_U1_CFG13 0x400100cd +#define CYREG_B0_P0_U1_CFG14 0x400100ce +#define CYREG_B0_P0_U1_CFG15 0x400100cf +#define CYREG_B0_P0_U1_CFG16 0x400100d0 +#define CYREG_B0_P0_U1_CFG17 0x400100d1 +#define CYREG_B0_P0_U1_CFG18 0x400100d2 +#define CYREG_B0_P0_U1_CFG19 0x400100d3 +#define CYREG_B0_P0_U1_CFG20 0x400100d4 +#define CYREG_B0_P0_U1_CFG21 0x400100d5 +#define CYREG_B0_P0_U1_CFG22 0x400100d6 +#define CYREG_B0_P0_U1_CFG23 0x400100d7 +#define CYREG_B0_P0_U1_CFG24 0x400100d8 +#define CYREG_B0_P0_U1_CFG25 0x400100d9 +#define CYREG_B0_P0_U1_CFG26 0x400100da +#define CYREG_B0_P0_U1_CFG27 0x400100db +#define CYREG_B0_P0_U1_CFG28 0x400100dc +#define CYREG_B0_P0_U1_CFG29 0x400100dd +#define CYREG_B0_P0_U1_CFG30 0x400100de +#define CYREG_B0_P0_U1_CFG31 0x400100df +#define CYREG_B0_P0_U1_DCFG0 0x400100e0 +#define CYREG_B0_P0_U1_DCFG1 0x400100e2 +#define CYREG_B0_P0_U1_DCFG2 0x400100e4 +#define CYREG_B0_P0_U1_DCFG3 0x400100e6 +#define CYREG_B0_P0_U1_DCFG4 0x400100e8 +#define CYREG_B0_P0_U1_DCFG5 0x400100ea +#define CYREG_B0_P0_U1_DCFG6 0x400100ec +#define CYREG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYREG_B0_P1_U0_CFG0 0x40010240 +#define CYREG_B0_P1_U0_CFG1 0x40010241 +#define CYREG_B0_P1_U0_CFG2 0x40010242 +#define CYREG_B0_P1_U0_CFG3 0x40010243 +#define CYREG_B0_P1_U0_CFG4 0x40010244 +#define CYREG_B0_P1_U0_CFG5 0x40010245 +#define CYREG_B0_P1_U0_CFG6 0x40010246 +#define CYREG_B0_P1_U0_CFG7 0x40010247 +#define CYREG_B0_P1_U0_CFG8 0x40010248 +#define CYREG_B0_P1_U0_CFG9 0x40010249 +#define CYREG_B0_P1_U0_CFG10 0x4001024a +#define CYREG_B0_P1_U0_CFG11 0x4001024b +#define CYREG_B0_P1_U0_CFG12 0x4001024c +#define CYREG_B0_P1_U0_CFG13 0x4001024d +#define CYREG_B0_P1_U0_CFG14 0x4001024e +#define CYREG_B0_P1_U0_CFG15 0x4001024f +#define CYREG_B0_P1_U0_CFG16 0x40010250 +#define CYREG_B0_P1_U0_CFG17 0x40010251 +#define CYREG_B0_P1_U0_CFG18 0x40010252 +#define CYREG_B0_P1_U0_CFG19 0x40010253 +#define CYREG_B0_P1_U0_CFG20 0x40010254 +#define CYREG_B0_P1_U0_CFG21 0x40010255 +#define CYREG_B0_P1_U0_CFG22 0x40010256 +#define CYREG_B0_P1_U0_CFG23 0x40010257 +#define CYREG_B0_P1_U0_CFG24 0x40010258 +#define CYREG_B0_P1_U0_CFG25 0x40010259 +#define CYREG_B0_P1_U0_CFG26 0x4001025a +#define CYREG_B0_P1_U0_CFG27 0x4001025b +#define CYREG_B0_P1_U0_CFG28 0x4001025c +#define CYREG_B0_P1_U0_CFG29 0x4001025d +#define CYREG_B0_P1_U0_CFG30 0x4001025e +#define CYREG_B0_P1_U0_CFG31 0x4001025f +#define CYREG_B0_P1_U0_DCFG0 0x40010260 +#define CYREG_B0_P1_U0_DCFG1 0x40010262 +#define CYREG_B0_P1_U0_DCFG2 0x40010264 +#define CYREG_B0_P1_U0_DCFG3 0x40010266 +#define CYREG_B0_P1_U0_DCFG4 0x40010268 +#define CYREG_B0_P1_U0_DCFG5 0x4001026a +#define CYREG_B0_P1_U0_DCFG6 0x4001026c +#define CYREG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYREG_B0_P1_U1_CFG0 0x400102c0 +#define CYREG_B0_P1_U1_CFG1 0x400102c1 +#define CYREG_B0_P1_U1_CFG2 0x400102c2 +#define CYREG_B0_P1_U1_CFG3 0x400102c3 +#define CYREG_B0_P1_U1_CFG4 0x400102c4 +#define CYREG_B0_P1_U1_CFG5 0x400102c5 +#define CYREG_B0_P1_U1_CFG6 0x400102c6 +#define CYREG_B0_P1_U1_CFG7 0x400102c7 +#define CYREG_B0_P1_U1_CFG8 0x400102c8 +#define CYREG_B0_P1_U1_CFG9 0x400102c9 +#define CYREG_B0_P1_U1_CFG10 0x400102ca +#define CYREG_B0_P1_U1_CFG11 0x400102cb +#define CYREG_B0_P1_U1_CFG12 0x400102cc +#define CYREG_B0_P1_U1_CFG13 0x400102cd +#define CYREG_B0_P1_U1_CFG14 0x400102ce +#define CYREG_B0_P1_U1_CFG15 0x400102cf +#define CYREG_B0_P1_U1_CFG16 0x400102d0 +#define CYREG_B0_P1_U1_CFG17 0x400102d1 +#define CYREG_B0_P1_U1_CFG18 0x400102d2 +#define CYREG_B0_P1_U1_CFG19 0x400102d3 +#define CYREG_B0_P1_U1_CFG20 0x400102d4 +#define CYREG_B0_P1_U1_CFG21 0x400102d5 +#define CYREG_B0_P1_U1_CFG22 0x400102d6 +#define CYREG_B0_P1_U1_CFG23 0x400102d7 +#define CYREG_B0_P1_U1_CFG24 0x400102d8 +#define CYREG_B0_P1_U1_CFG25 0x400102d9 +#define CYREG_B0_P1_U1_CFG26 0x400102da +#define CYREG_B0_P1_U1_CFG27 0x400102db +#define CYREG_B0_P1_U1_CFG28 0x400102dc +#define CYREG_B0_P1_U1_CFG29 0x400102dd +#define CYREG_B0_P1_U1_CFG30 0x400102de +#define CYREG_B0_P1_U1_CFG31 0x400102df +#define CYREG_B0_P1_U1_DCFG0 0x400102e0 +#define CYREG_B0_P1_U1_DCFG1 0x400102e2 +#define CYREG_B0_P1_U1_DCFG2 0x400102e4 +#define CYREG_B0_P1_U1_DCFG3 0x400102e6 +#define CYREG_B0_P1_U1_DCFG4 0x400102e8 +#define CYREG_B0_P1_U1_DCFG5 0x400102ea +#define CYREG_B0_P1_U1_DCFG6 0x400102ec +#define CYREG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYREG_B0_P2_U0_CFG0 0x40010440 +#define CYREG_B0_P2_U0_CFG1 0x40010441 +#define CYREG_B0_P2_U0_CFG2 0x40010442 +#define CYREG_B0_P2_U0_CFG3 0x40010443 +#define CYREG_B0_P2_U0_CFG4 0x40010444 +#define CYREG_B0_P2_U0_CFG5 0x40010445 +#define CYREG_B0_P2_U0_CFG6 0x40010446 +#define CYREG_B0_P2_U0_CFG7 0x40010447 +#define CYREG_B0_P2_U0_CFG8 0x40010448 +#define CYREG_B0_P2_U0_CFG9 0x40010449 +#define CYREG_B0_P2_U0_CFG10 0x4001044a +#define CYREG_B0_P2_U0_CFG11 0x4001044b +#define CYREG_B0_P2_U0_CFG12 0x4001044c +#define CYREG_B0_P2_U0_CFG13 0x4001044d +#define CYREG_B0_P2_U0_CFG14 0x4001044e +#define CYREG_B0_P2_U0_CFG15 0x4001044f +#define CYREG_B0_P2_U0_CFG16 0x40010450 +#define CYREG_B0_P2_U0_CFG17 0x40010451 +#define CYREG_B0_P2_U0_CFG18 0x40010452 +#define CYREG_B0_P2_U0_CFG19 0x40010453 +#define CYREG_B0_P2_U0_CFG20 0x40010454 +#define CYREG_B0_P2_U0_CFG21 0x40010455 +#define CYREG_B0_P2_U0_CFG22 0x40010456 +#define CYREG_B0_P2_U0_CFG23 0x40010457 +#define CYREG_B0_P2_U0_CFG24 0x40010458 +#define CYREG_B0_P2_U0_CFG25 0x40010459 +#define CYREG_B0_P2_U0_CFG26 0x4001045a +#define CYREG_B0_P2_U0_CFG27 0x4001045b +#define CYREG_B0_P2_U0_CFG28 0x4001045c +#define CYREG_B0_P2_U0_CFG29 0x4001045d +#define CYREG_B0_P2_U0_CFG30 0x4001045e +#define CYREG_B0_P2_U0_CFG31 0x4001045f +#define CYREG_B0_P2_U0_DCFG0 0x40010460 +#define CYREG_B0_P2_U0_DCFG1 0x40010462 +#define CYREG_B0_P2_U0_DCFG2 0x40010464 +#define CYREG_B0_P2_U0_DCFG3 0x40010466 +#define CYREG_B0_P2_U0_DCFG4 0x40010468 +#define CYREG_B0_P2_U0_DCFG5 0x4001046a +#define CYREG_B0_P2_U0_DCFG6 0x4001046c +#define CYREG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYREG_B0_P2_U1_CFG0 0x400104c0 +#define CYREG_B0_P2_U1_CFG1 0x400104c1 +#define CYREG_B0_P2_U1_CFG2 0x400104c2 +#define CYREG_B0_P2_U1_CFG3 0x400104c3 +#define CYREG_B0_P2_U1_CFG4 0x400104c4 +#define CYREG_B0_P2_U1_CFG5 0x400104c5 +#define CYREG_B0_P2_U1_CFG6 0x400104c6 +#define CYREG_B0_P2_U1_CFG7 0x400104c7 +#define CYREG_B0_P2_U1_CFG8 0x400104c8 +#define CYREG_B0_P2_U1_CFG9 0x400104c9 +#define CYREG_B0_P2_U1_CFG10 0x400104ca +#define CYREG_B0_P2_U1_CFG11 0x400104cb +#define CYREG_B0_P2_U1_CFG12 0x400104cc +#define CYREG_B0_P2_U1_CFG13 0x400104cd +#define CYREG_B0_P2_U1_CFG14 0x400104ce +#define CYREG_B0_P2_U1_CFG15 0x400104cf +#define CYREG_B0_P2_U1_CFG16 0x400104d0 +#define CYREG_B0_P2_U1_CFG17 0x400104d1 +#define CYREG_B0_P2_U1_CFG18 0x400104d2 +#define CYREG_B0_P2_U1_CFG19 0x400104d3 +#define CYREG_B0_P2_U1_CFG20 0x400104d4 +#define CYREG_B0_P2_U1_CFG21 0x400104d5 +#define CYREG_B0_P2_U1_CFG22 0x400104d6 +#define CYREG_B0_P2_U1_CFG23 0x400104d7 +#define CYREG_B0_P2_U1_CFG24 0x400104d8 +#define CYREG_B0_P2_U1_CFG25 0x400104d9 +#define CYREG_B0_P2_U1_CFG26 0x400104da +#define CYREG_B0_P2_U1_CFG27 0x400104db +#define CYREG_B0_P2_U1_CFG28 0x400104dc +#define CYREG_B0_P2_U1_CFG29 0x400104dd +#define CYREG_B0_P2_U1_CFG30 0x400104de +#define CYREG_B0_P2_U1_CFG31 0x400104df +#define CYREG_B0_P2_U1_DCFG0 0x400104e0 +#define CYREG_B0_P2_U1_DCFG1 0x400104e2 +#define CYREG_B0_P2_U1_DCFG2 0x400104e4 +#define CYREG_B0_P2_U1_DCFG3 0x400104e6 +#define CYREG_B0_P2_U1_DCFG4 0x400104e8 +#define CYREG_B0_P2_U1_DCFG5 0x400104ea +#define CYREG_B0_P2_U1_DCFG6 0x400104ec +#define CYREG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYREG_B0_P3_U0_CFG0 0x40010640 +#define CYREG_B0_P3_U0_CFG1 0x40010641 +#define CYREG_B0_P3_U0_CFG2 0x40010642 +#define CYREG_B0_P3_U0_CFG3 0x40010643 +#define CYREG_B0_P3_U0_CFG4 0x40010644 +#define CYREG_B0_P3_U0_CFG5 0x40010645 +#define CYREG_B0_P3_U0_CFG6 0x40010646 +#define CYREG_B0_P3_U0_CFG7 0x40010647 +#define CYREG_B0_P3_U0_CFG8 0x40010648 +#define CYREG_B0_P3_U0_CFG9 0x40010649 +#define CYREG_B0_P3_U0_CFG10 0x4001064a +#define CYREG_B0_P3_U0_CFG11 0x4001064b +#define CYREG_B0_P3_U0_CFG12 0x4001064c +#define CYREG_B0_P3_U0_CFG13 0x4001064d +#define CYREG_B0_P3_U0_CFG14 0x4001064e +#define CYREG_B0_P3_U0_CFG15 0x4001064f +#define CYREG_B0_P3_U0_CFG16 0x40010650 +#define CYREG_B0_P3_U0_CFG17 0x40010651 +#define CYREG_B0_P3_U0_CFG18 0x40010652 +#define CYREG_B0_P3_U0_CFG19 0x40010653 +#define CYREG_B0_P3_U0_CFG20 0x40010654 +#define CYREG_B0_P3_U0_CFG21 0x40010655 +#define CYREG_B0_P3_U0_CFG22 0x40010656 +#define CYREG_B0_P3_U0_CFG23 0x40010657 +#define CYREG_B0_P3_U0_CFG24 0x40010658 +#define CYREG_B0_P3_U0_CFG25 0x40010659 +#define CYREG_B0_P3_U0_CFG26 0x4001065a +#define CYREG_B0_P3_U0_CFG27 0x4001065b +#define CYREG_B0_P3_U0_CFG28 0x4001065c +#define CYREG_B0_P3_U0_CFG29 0x4001065d +#define CYREG_B0_P3_U0_CFG30 0x4001065e +#define CYREG_B0_P3_U0_CFG31 0x4001065f +#define CYREG_B0_P3_U0_DCFG0 0x40010660 +#define CYREG_B0_P3_U0_DCFG1 0x40010662 +#define CYREG_B0_P3_U0_DCFG2 0x40010664 +#define CYREG_B0_P3_U0_DCFG3 0x40010666 +#define CYREG_B0_P3_U0_DCFG4 0x40010668 +#define CYREG_B0_P3_U0_DCFG5 0x4001066a +#define CYREG_B0_P3_U0_DCFG6 0x4001066c +#define CYREG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYREG_B0_P3_U1_CFG0 0x400106c0 +#define CYREG_B0_P3_U1_CFG1 0x400106c1 +#define CYREG_B0_P3_U1_CFG2 0x400106c2 +#define CYREG_B0_P3_U1_CFG3 0x400106c3 +#define CYREG_B0_P3_U1_CFG4 0x400106c4 +#define CYREG_B0_P3_U1_CFG5 0x400106c5 +#define CYREG_B0_P3_U1_CFG6 0x400106c6 +#define CYREG_B0_P3_U1_CFG7 0x400106c7 +#define CYREG_B0_P3_U1_CFG8 0x400106c8 +#define CYREG_B0_P3_U1_CFG9 0x400106c9 +#define CYREG_B0_P3_U1_CFG10 0x400106ca +#define CYREG_B0_P3_U1_CFG11 0x400106cb +#define CYREG_B0_P3_U1_CFG12 0x400106cc +#define CYREG_B0_P3_U1_CFG13 0x400106cd +#define CYREG_B0_P3_U1_CFG14 0x400106ce +#define CYREG_B0_P3_U1_CFG15 0x400106cf +#define CYREG_B0_P3_U1_CFG16 0x400106d0 +#define CYREG_B0_P3_U1_CFG17 0x400106d1 +#define CYREG_B0_P3_U1_CFG18 0x400106d2 +#define CYREG_B0_P3_U1_CFG19 0x400106d3 +#define CYREG_B0_P3_U1_CFG20 0x400106d4 +#define CYREG_B0_P3_U1_CFG21 0x400106d5 +#define CYREG_B0_P3_U1_CFG22 0x400106d6 +#define CYREG_B0_P3_U1_CFG23 0x400106d7 +#define CYREG_B0_P3_U1_CFG24 0x400106d8 +#define CYREG_B0_P3_U1_CFG25 0x400106d9 +#define CYREG_B0_P3_U1_CFG26 0x400106da +#define CYREG_B0_P3_U1_CFG27 0x400106db +#define CYREG_B0_P3_U1_CFG28 0x400106dc +#define CYREG_B0_P3_U1_CFG29 0x400106dd +#define CYREG_B0_P3_U1_CFG30 0x400106de +#define CYREG_B0_P3_U1_CFG31 0x400106df +#define CYREG_B0_P3_U1_DCFG0 0x400106e0 +#define CYREG_B0_P3_U1_DCFG1 0x400106e2 +#define CYREG_B0_P3_U1_DCFG2 0x400106e4 +#define CYREG_B0_P3_U1_DCFG3 0x400106e6 +#define CYREG_B0_P3_U1_DCFG4 0x400106e8 +#define CYREG_B0_P3_U1_DCFG5 0x400106ea +#define CYREG_B0_P3_U1_DCFG6 0x400106ec +#define CYREG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYREG_B0_P4_U0_CFG0 0x40010840 +#define CYREG_B0_P4_U0_CFG1 0x40010841 +#define CYREG_B0_P4_U0_CFG2 0x40010842 +#define CYREG_B0_P4_U0_CFG3 0x40010843 +#define CYREG_B0_P4_U0_CFG4 0x40010844 +#define CYREG_B0_P4_U0_CFG5 0x40010845 +#define CYREG_B0_P4_U0_CFG6 0x40010846 +#define CYREG_B0_P4_U0_CFG7 0x40010847 +#define CYREG_B0_P4_U0_CFG8 0x40010848 +#define CYREG_B0_P4_U0_CFG9 0x40010849 +#define CYREG_B0_P4_U0_CFG10 0x4001084a +#define CYREG_B0_P4_U0_CFG11 0x4001084b +#define CYREG_B0_P4_U0_CFG12 0x4001084c +#define CYREG_B0_P4_U0_CFG13 0x4001084d +#define CYREG_B0_P4_U0_CFG14 0x4001084e +#define CYREG_B0_P4_U0_CFG15 0x4001084f +#define CYREG_B0_P4_U0_CFG16 0x40010850 +#define CYREG_B0_P4_U0_CFG17 0x40010851 +#define CYREG_B0_P4_U0_CFG18 0x40010852 +#define CYREG_B0_P4_U0_CFG19 0x40010853 +#define CYREG_B0_P4_U0_CFG20 0x40010854 +#define CYREG_B0_P4_U0_CFG21 0x40010855 +#define CYREG_B0_P4_U0_CFG22 0x40010856 +#define CYREG_B0_P4_U0_CFG23 0x40010857 +#define CYREG_B0_P4_U0_CFG24 0x40010858 +#define CYREG_B0_P4_U0_CFG25 0x40010859 +#define CYREG_B0_P4_U0_CFG26 0x4001085a +#define CYREG_B0_P4_U0_CFG27 0x4001085b +#define CYREG_B0_P4_U0_CFG28 0x4001085c +#define CYREG_B0_P4_U0_CFG29 0x4001085d +#define CYREG_B0_P4_U0_CFG30 0x4001085e +#define CYREG_B0_P4_U0_CFG31 0x4001085f +#define CYREG_B0_P4_U0_DCFG0 0x40010860 +#define CYREG_B0_P4_U0_DCFG1 0x40010862 +#define CYREG_B0_P4_U0_DCFG2 0x40010864 +#define CYREG_B0_P4_U0_DCFG3 0x40010866 +#define CYREG_B0_P4_U0_DCFG4 0x40010868 +#define CYREG_B0_P4_U0_DCFG5 0x4001086a +#define CYREG_B0_P4_U0_DCFG6 0x4001086c +#define CYREG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYREG_B0_P4_U1_CFG0 0x400108c0 +#define CYREG_B0_P4_U1_CFG1 0x400108c1 +#define CYREG_B0_P4_U1_CFG2 0x400108c2 +#define CYREG_B0_P4_U1_CFG3 0x400108c3 +#define CYREG_B0_P4_U1_CFG4 0x400108c4 +#define CYREG_B0_P4_U1_CFG5 0x400108c5 +#define CYREG_B0_P4_U1_CFG6 0x400108c6 +#define CYREG_B0_P4_U1_CFG7 0x400108c7 +#define CYREG_B0_P4_U1_CFG8 0x400108c8 +#define CYREG_B0_P4_U1_CFG9 0x400108c9 +#define CYREG_B0_P4_U1_CFG10 0x400108ca +#define CYREG_B0_P4_U1_CFG11 0x400108cb +#define CYREG_B0_P4_U1_CFG12 0x400108cc +#define CYREG_B0_P4_U1_CFG13 0x400108cd +#define CYREG_B0_P4_U1_CFG14 0x400108ce +#define CYREG_B0_P4_U1_CFG15 0x400108cf +#define CYREG_B0_P4_U1_CFG16 0x400108d0 +#define CYREG_B0_P4_U1_CFG17 0x400108d1 +#define CYREG_B0_P4_U1_CFG18 0x400108d2 +#define CYREG_B0_P4_U1_CFG19 0x400108d3 +#define CYREG_B0_P4_U1_CFG20 0x400108d4 +#define CYREG_B0_P4_U1_CFG21 0x400108d5 +#define CYREG_B0_P4_U1_CFG22 0x400108d6 +#define CYREG_B0_P4_U1_CFG23 0x400108d7 +#define CYREG_B0_P4_U1_CFG24 0x400108d8 +#define CYREG_B0_P4_U1_CFG25 0x400108d9 +#define CYREG_B0_P4_U1_CFG26 0x400108da +#define CYREG_B0_P4_U1_CFG27 0x400108db +#define CYREG_B0_P4_U1_CFG28 0x400108dc +#define CYREG_B0_P4_U1_CFG29 0x400108dd +#define CYREG_B0_P4_U1_CFG30 0x400108de +#define CYREG_B0_P4_U1_CFG31 0x400108df +#define CYREG_B0_P4_U1_DCFG0 0x400108e0 +#define CYREG_B0_P4_U1_DCFG1 0x400108e2 +#define CYREG_B0_P4_U1_DCFG2 0x400108e4 +#define CYREG_B0_P4_U1_DCFG3 0x400108e6 +#define CYREG_B0_P4_U1_DCFG4 0x400108e8 +#define CYREG_B0_P4_U1_DCFG5 0x400108ea +#define CYREG_B0_P4_U1_DCFG6 0x400108ec +#define CYREG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYREG_B0_P5_U0_CFG0 0x40010a40 +#define CYREG_B0_P5_U0_CFG1 0x40010a41 +#define CYREG_B0_P5_U0_CFG2 0x40010a42 +#define CYREG_B0_P5_U0_CFG3 0x40010a43 +#define CYREG_B0_P5_U0_CFG4 0x40010a44 +#define CYREG_B0_P5_U0_CFG5 0x40010a45 +#define CYREG_B0_P5_U0_CFG6 0x40010a46 +#define CYREG_B0_P5_U0_CFG7 0x40010a47 +#define CYREG_B0_P5_U0_CFG8 0x40010a48 +#define CYREG_B0_P5_U0_CFG9 0x40010a49 +#define CYREG_B0_P5_U0_CFG10 0x40010a4a +#define CYREG_B0_P5_U0_CFG11 0x40010a4b +#define CYREG_B0_P5_U0_CFG12 0x40010a4c +#define CYREG_B0_P5_U0_CFG13 0x40010a4d +#define CYREG_B0_P5_U0_CFG14 0x40010a4e +#define CYREG_B0_P5_U0_CFG15 0x40010a4f +#define CYREG_B0_P5_U0_CFG16 0x40010a50 +#define CYREG_B0_P5_U0_CFG17 0x40010a51 +#define CYREG_B0_P5_U0_CFG18 0x40010a52 +#define CYREG_B0_P5_U0_CFG19 0x40010a53 +#define CYREG_B0_P5_U0_CFG20 0x40010a54 +#define CYREG_B0_P5_U0_CFG21 0x40010a55 +#define CYREG_B0_P5_U0_CFG22 0x40010a56 +#define CYREG_B0_P5_U0_CFG23 0x40010a57 +#define CYREG_B0_P5_U0_CFG24 0x40010a58 +#define CYREG_B0_P5_U0_CFG25 0x40010a59 +#define CYREG_B0_P5_U0_CFG26 0x40010a5a +#define CYREG_B0_P5_U0_CFG27 0x40010a5b +#define CYREG_B0_P5_U0_CFG28 0x40010a5c +#define CYREG_B0_P5_U0_CFG29 0x40010a5d +#define CYREG_B0_P5_U0_CFG30 0x40010a5e +#define CYREG_B0_P5_U0_CFG31 0x40010a5f +#define CYREG_B0_P5_U0_DCFG0 0x40010a60 +#define CYREG_B0_P5_U0_DCFG1 0x40010a62 +#define CYREG_B0_P5_U0_DCFG2 0x40010a64 +#define CYREG_B0_P5_U0_DCFG3 0x40010a66 +#define CYREG_B0_P5_U0_DCFG4 0x40010a68 +#define CYREG_B0_P5_U0_DCFG5 0x40010a6a +#define CYREG_B0_P5_U0_DCFG6 0x40010a6c +#define CYREG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYREG_B0_P5_U1_CFG0 0x40010ac0 +#define CYREG_B0_P5_U1_CFG1 0x40010ac1 +#define CYREG_B0_P5_U1_CFG2 0x40010ac2 +#define CYREG_B0_P5_U1_CFG3 0x40010ac3 +#define CYREG_B0_P5_U1_CFG4 0x40010ac4 +#define CYREG_B0_P5_U1_CFG5 0x40010ac5 +#define CYREG_B0_P5_U1_CFG6 0x40010ac6 +#define CYREG_B0_P5_U1_CFG7 0x40010ac7 +#define CYREG_B0_P5_U1_CFG8 0x40010ac8 +#define CYREG_B0_P5_U1_CFG9 0x40010ac9 +#define CYREG_B0_P5_U1_CFG10 0x40010aca +#define CYREG_B0_P5_U1_CFG11 0x40010acb +#define CYREG_B0_P5_U1_CFG12 0x40010acc +#define CYREG_B0_P5_U1_CFG13 0x40010acd +#define CYREG_B0_P5_U1_CFG14 0x40010ace +#define CYREG_B0_P5_U1_CFG15 0x40010acf +#define CYREG_B0_P5_U1_CFG16 0x40010ad0 +#define CYREG_B0_P5_U1_CFG17 0x40010ad1 +#define CYREG_B0_P5_U1_CFG18 0x40010ad2 +#define CYREG_B0_P5_U1_CFG19 0x40010ad3 +#define CYREG_B0_P5_U1_CFG20 0x40010ad4 +#define CYREG_B0_P5_U1_CFG21 0x40010ad5 +#define CYREG_B0_P5_U1_CFG22 0x40010ad6 +#define CYREG_B0_P5_U1_CFG23 0x40010ad7 +#define CYREG_B0_P5_U1_CFG24 0x40010ad8 +#define CYREG_B0_P5_U1_CFG25 0x40010ad9 +#define CYREG_B0_P5_U1_CFG26 0x40010ada +#define CYREG_B0_P5_U1_CFG27 0x40010adb +#define CYREG_B0_P5_U1_CFG28 0x40010adc +#define CYREG_B0_P5_U1_CFG29 0x40010add +#define CYREG_B0_P5_U1_CFG30 0x40010ade +#define CYREG_B0_P5_U1_CFG31 0x40010adf +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYREG_B0_P5_U1_DCFG5 0x40010aea +#define CYREG_B0_P5_U1_DCFG6 0x40010aec +#define CYREG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYREG_B0_P6_U0_CFG0 0x40010c40 +#define CYREG_B0_P6_U0_CFG1 0x40010c41 +#define CYREG_B0_P6_U0_CFG2 0x40010c42 +#define CYREG_B0_P6_U0_CFG3 0x40010c43 +#define CYREG_B0_P6_U0_CFG4 0x40010c44 +#define CYREG_B0_P6_U0_CFG5 0x40010c45 +#define CYREG_B0_P6_U0_CFG6 0x40010c46 +#define CYREG_B0_P6_U0_CFG7 0x40010c47 +#define CYREG_B0_P6_U0_CFG8 0x40010c48 +#define CYREG_B0_P6_U0_CFG9 0x40010c49 +#define CYREG_B0_P6_U0_CFG10 0x40010c4a +#define CYREG_B0_P6_U0_CFG11 0x40010c4b +#define CYREG_B0_P6_U0_CFG12 0x40010c4c +#define CYREG_B0_P6_U0_CFG13 0x40010c4d +#define CYREG_B0_P6_U0_CFG14 0x40010c4e +#define CYREG_B0_P6_U0_CFG15 0x40010c4f +#define CYREG_B0_P6_U0_CFG16 0x40010c50 +#define CYREG_B0_P6_U0_CFG17 0x40010c51 +#define CYREG_B0_P6_U0_CFG18 0x40010c52 +#define CYREG_B0_P6_U0_CFG19 0x40010c53 +#define CYREG_B0_P6_U0_CFG20 0x40010c54 +#define CYREG_B0_P6_U0_CFG21 0x40010c55 +#define CYREG_B0_P6_U0_CFG22 0x40010c56 +#define CYREG_B0_P6_U0_CFG23 0x40010c57 +#define CYREG_B0_P6_U0_CFG24 0x40010c58 +#define CYREG_B0_P6_U0_CFG25 0x40010c59 +#define CYREG_B0_P6_U0_CFG26 0x40010c5a +#define CYREG_B0_P6_U0_CFG27 0x40010c5b +#define CYREG_B0_P6_U0_CFG28 0x40010c5c +#define CYREG_B0_P6_U0_CFG29 0x40010c5d +#define CYREG_B0_P6_U0_CFG30 0x40010c5e +#define CYREG_B0_P6_U0_CFG31 0x40010c5f +#define CYREG_B0_P6_U0_DCFG0 0x40010c60 +#define CYREG_B0_P6_U0_DCFG1 0x40010c62 +#define CYREG_B0_P6_U0_DCFG2 0x40010c64 +#define CYREG_B0_P6_U0_DCFG3 0x40010c66 +#define CYREG_B0_P6_U0_DCFG4 0x40010c68 +#define CYREG_B0_P6_U0_DCFG5 0x40010c6a +#define CYREG_B0_P6_U0_DCFG6 0x40010c6c +#define CYREG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYREG_B0_P6_U1_CFG0 0x40010cc0 +#define CYREG_B0_P6_U1_CFG1 0x40010cc1 +#define CYREG_B0_P6_U1_CFG2 0x40010cc2 +#define CYREG_B0_P6_U1_CFG3 0x40010cc3 +#define CYREG_B0_P6_U1_CFG4 0x40010cc4 +#define CYREG_B0_P6_U1_CFG5 0x40010cc5 +#define CYREG_B0_P6_U1_CFG6 0x40010cc6 +#define CYREG_B0_P6_U1_CFG7 0x40010cc7 +#define CYREG_B0_P6_U1_CFG8 0x40010cc8 +#define CYREG_B0_P6_U1_CFG9 0x40010cc9 +#define CYREG_B0_P6_U1_CFG10 0x40010cca +#define CYREG_B0_P6_U1_CFG11 0x40010ccb +#define CYREG_B0_P6_U1_CFG12 0x40010ccc +#define CYREG_B0_P6_U1_CFG13 0x40010ccd +#define CYREG_B0_P6_U1_CFG14 0x40010cce +#define CYREG_B0_P6_U1_CFG15 0x40010ccf +#define CYREG_B0_P6_U1_CFG16 0x40010cd0 +#define CYREG_B0_P6_U1_CFG17 0x40010cd1 +#define CYREG_B0_P6_U1_CFG18 0x40010cd2 +#define CYREG_B0_P6_U1_CFG19 0x40010cd3 +#define CYREG_B0_P6_U1_CFG20 0x40010cd4 +#define CYREG_B0_P6_U1_CFG21 0x40010cd5 +#define CYREG_B0_P6_U1_CFG22 0x40010cd6 +#define CYREG_B0_P6_U1_CFG23 0x40010cd7 +#define CYREG_B0_P6_U1_CFG24 0x40010cd8 +#define CYREG_B0_P6_U1_CFG25 0x40010cd9 +#define CYREG_B0_P6_U1_CFG26 0x40010cda +#define CYREG_B0_P6_U1_CFG27 0x40010cdb +#define CYREG_B0_P6_U1_CFG28 0x40010cdc +#define CYREG_B0_P6_U1_CFG29 0x40010cdd +#define CYREG_B0_P6_U1_CFG30 0x40010cde +#define CYREG_B0_P6_U1_CFG31 0x40010cdf +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYREG_B0_P6_U1_DCFG5 0x40010cea +#define CYREG_B0_P6_U1_DCFG6 0x40010cec +#define CYREG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYREG_B0_P7_U0_CFG0 0x40010e40 +#define CYREG_B0_P7_U0_CFG1 0x40010e41 +#define CYREG_B0_P7_U0_CFG2 0x40010e42 +#define CYREG_B0_P7_U0_CFG3 0x40010e43 +#define CYREG_B0_P7_U0_CFG4 0x40010e44 +#define CYREG_B0_P7_U0_CFG5 0x40010e45 +#define CYREG_B0_P7_U0_CFG6 0x40010e46 +#define CYREG_B0_P7_U0_CFG7 0x40010e47 +#define CYREG_B0_P7_U0_CFG8 0x40010e48 +#define CYREG_B0_P7_U0_CFG9 0x40010e49 +#define CYREG_B0_P7_U0_CFG10 0x40010e4a +#define CYREG_B0_P7_U0_CFG11 0x40010e4b +#define CYREG_B0_P7_U0_CFG12 0x40010e4c +#define CYREG_B0_P7_U0_CFG13 0x40010e4d +#define CYREG_B0_P7_U0_CFG14 0x40010e4e +#define CYREG_B0_P7_U0_CFG15 0x40010e4f +#define CYREG_B0_P7_U0_CFG16 0x40010e50 +#define CYREG_B0_P7_U0_CFG17 0x40010e51 +#define CYREG_B0_P7_U0_CFG18 0x40010e52 +#define CYREG_B0_P7_U0_CFG19 0x40010e53 +#define CYREG_B0_P7_U0_CFG20 0x40010e54 +#define CYREG_B0_P7_U0_CFG21 0x40010e55 +#define CYREG_B0_P7_U0_CFG22 0x40010e56 +#define CYREG_B0_P7_U0_CFG23 0x40010e57 +#define CYREG_B0_P7_U0_CFG24 0x40010e58 +#define CYREG_B0_P7_U0_CFG25 0x40010e59 +#define CYREG_B0_P7_U0_CFG26 0x40010e5a +#define CYREG_B0_P7_U0_CFG27 0x40010e5b +#define CYREG_B0_P7_U0_CFG28 0x40010e5c +#define CYREG_B0_P7_U0_CFG29 0x40010e5d +#define CYREG_B0_P7_U0_CFG30 0x40010e5e +#define CYREG_B0_P7_U0_CFG31 0x40010e5f +#define CYREG_B0_P7_U0_DCFG0 0x40010e60 +#define CYREG_B0_P7_U0_DCFG1 0x40010e62 +#define CYREG_B0_P7_U0_DCFG2 0x40010e64 +#define CYREG_B0_P7_U0_DCFG3 0x40010e66 +#define CYREG_B0_P7_U0_DCFG4 0x40010e68 +#define CYREG_B0_P7_U0_DCFG5 0x40010e6a +#define CYREG_B0_P7_U0_DCFG6 0x40010e6c +#define CYREG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYREG_B0_P7_U1_CFG0 0x40010ec0 +#define CYREG_B0_P7_U1_CFG1 0x40010ec1 +#define CYREG_B0_P7_U1_CFG2 0x40010ec2 +#define CYREG_B0_P7_U1_CFG3 0x40010ec3 +#define CYREG_B0_P7_U1_CFG4 0x40010ec4 +#define CYREG_B0_P7_U1_CFG5 0x40010ec5 +#define CYREG_B0_P7_U1_CFG6 0x40010ec6 +#define CYREG_B0_P7_U1_CFG7 0x40010ec7 +#define CYREG_B0_P7_U1_CFG8 0x40010ec8 +#define CYREG_B0_P7_U1_CFG9 0x40010ec9 +#define CYREG_B0_P7_U1_CFG10 0x40010eca +#define CYREG_B0_P7_U1_CFG11 0x40010ecb +#define CYREG_B0_P7_U1_CFG12 0x40010ecc +#define CYREG_B0_P7_U1_CFG13 0x40010ecd +#define CYREG_B0_P7_U1_CFG14 0x40010ece +#define CYREG_B0_P7_U1_CFG15 0x40010ecf +#define CYREG_B0_P7_U1_CFG16 0x40010ed0 +#define CYREG_B0_P7_U1_CFG17 0x40010ed1 +#define CYREG_B0_P7_U1_CFG18 0x40010ed2 +#define CYREG_B0_P7_U1_CFG19 0x40010ed3 +#define CYREG_B0_P7_U1_CFG20 0x40010ed4 +#define CYREG_B0_P7_U1_CFG21 0x40010ed5 +#define CYREG_B0_P7_U1_CFG22 0x40010ed6 +#define CYREG_B0_P7_U1_CFG23 0x40010ed7 +#define CYREG_B0_P7_U1_CFG24 0x40010ed8 +#define CYREG_B0_P7_U1_CFG25 0x40010ed9 +#define CYREG_B0_P7_U1_CFG26 0x40010eda +#define CYREG_B0_P7_U1_CFG27 0x40010edb +#define CYREG_B0_P7_U1_CFG28 0x40010edc +#define CYREG_B0_P7_U1_CFG29 0x40010edd +#define CYREG_B0_P7_U1_CFG30 0x40010ede +#define CYREG_B0_P7_U1_CFG31 0x40010edf +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYREG_B0_P7_U1_DCFG5 0x40010eea +#define CYREG_B0_P7_U1_DCFG6 0x40010eec +#define CYREG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYREG_B1_P2_U0_CFG0 0x40011440 +#define CYREG_B1_P2_U0_CFG1 0x40011441 +#define CYREG_B1_P2_U0_CFG2 0x40011442 +#define CYREG_B1_P2_U0_CFG3 0x40011443 +#define CYREG_B1_P2_U0_CFG4 0x40011444 +#define CYREG_B1_P2_U0_CFG5 0x40011445 +#define CYREG_B1_P2_U0_CFG6 0x40011446 +#define CYREG_B1_P2_U0_CFG7 0x40011447 +#define CYREG_B1_P2_U0_CFG8 0x40011448 +#define CYREG_B1_P2_U0_CFG9 0x40011449 +#define CYREG_B1_P2_U0_CFG10 0x4001144a +#define CYREG_B1_P2_U0_CFG11 0x4001144b +#define CYREG_B1_P2_U0_CFG12 0x4001144c +#define CYREG_B1_P2_U0_CFG13 0x4001144d +#define CYREG_B1_P2_U0_CFG14 0x4001144e +#define CYREG_B1_P2_U0_CFG15 0x4001144f +#define CYREG_B1_P2_U0_CFG16 0x40011450 +#define CYREG_B1_P2_U0_CFG17 0x40011451 +#define CYREG_B1_P2_U0_CFG18 0x40011452 +#define CYREG_B1_P2_U0_CFG19 0x40011453 +#define CYREG_B1_P2_U0_CFG20 0x40011454 +#define CYREG_B1_P2_U0_CFG21 0x40011455 +#define CYREG_B1_P2_U0_CFG22 0x40011456 +#define CYREG_B1_P2_U0_CFG23 0x40011457 +#define CYREG_B1_P2_U0_CFG24 0x40011458 +#define CYREG_B1_P2_U0_CFG25 0x40011459 +#define CYREG_B1_P2_U0_CFG26 0x4001145a +#define CYREG_B1_P2_U0_CFG27 0x4001145b +#define CYREG_B1_P2_U0_CFG28 0x4001145c +#define CYREG_B1_P2_U0_CFG29 0x4001145d +#define CYREG_B1_P2_U0_CFG30 0x4001145e +#define CYREG_B1_P2_U0_CFG31 0x4001145f +#define CYREG_B1_P2_U0_DCFG0 0x40011460 +#define CYREG_B1_P2_U0_DCFG1 0x40011462 +#define CYREG_B1_P2_U0_DCFG2 0x40011464 +#define CYREG_B1_P2_U0_DCFG3 0x40011466 +#define CYREG_B1_P2_U0_DCFG4 0x40011468 +#define CYREG_B1_P2_U0_DCFG5 0x4001146a +#define CYREG_B1_P2_U0_DCFG6 0x4001146c +#define CYREG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYREG_B1_P2_U1_CFG0 0x400114c0 +#define CYREG_B1_P2_U1_CFG1 0x400114c1 +#define CYREG_B1_P2_U1_CFG2 0x400114c2 +#define CYREG_B1_P2_U1_CFG3 0x400114c3 +#define CYREG_B1_P2_U1_CFG4 0x400114c4 +#define CYREG_B1_P2_U1_CFG5 0x400114c5 +#define CYREG_B1_P2_U1_CFG6 0x400114c6 +#define CYREG_B1_P2_U1_CFG7 0x400114c7 +#define CYREG_B1_P2_U1_CFG8 0x400114c8 +#define CYREG_B1_P2_U1_CFG9 0x400114c9 +#define CYREG_B1_P2_U1_CFG10 0x400114ca +#define CYREG_B1_P2_U1_CFG11 0x400114cb +#define CYREG_B1_P2_U1_CFG12 0x400114cc +#define CYREG_B1_P2_U1_CFG13 0x400114cd +#define CYREG_B1_P2_U1_CFG14 0x400114ce +#define CYREG_B1_P2_U1_CFG15 0x400114cf +#define CYREG_B1_P2_U1_CFG16 0x400114d0 +#define CYREG_B1_P2_U1_CFG17 0x400114d1 +#define CYREG_B1_P2_U1_CFG18 0x400114d2 +#define CYREG_B1_P2_U1_CFG19 0x400114d3 +#define CYREG_B1_P2_U1_CFG20 0x400114d4 +#define CYREG_B1_P2_U1_CFG21 0x400114d5 +#define CYREG_B1_P2_U1_CFG22 0x400114d6 +#define CYREG_B1_P2_U1_CFG23 0x400114d7 +#define CYREG_B1_P2_U1_CFG24 0x400114d8 +#define CYREG_B1_P2_U1_CFG25 0x400114d9 +#define CYREG_B1_P2_U1_CFG26 0x400114da +#define CYREG_B1_P2_U1_CFG27 0x400114db +#define CYREG_B1_P2_U1_CFG28 0x400114dc +#define CYREG_B1_P2_U1_CFG29 0x400114dd +#define CYREG_B1_P2_U1_CFG30 0x400114de +#define CYREG_B1_P2_U1_CFG31 0x400114df +#define CYREG_B1_P2_U1_DCFG0 0x400114e0 +#define CYREG_B1_P2_U1_DCFG1 0x400114e2 +#define CYREG_B1_P2_U1_DCFG2 0x400114e4 +#define CYREG_B1_P2_U1_DCFG3 0x400114e6 +#define CYREG_B1_P2_U1_DCFG4 0x400114e8 +#define CYREG_B1_P2_U1_DCFG5 0x400114ea +#define CYREG_B1_P2_U1_DCFG6 0x400114ec +#define CYREG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYREG_B1_P3_U0_CFG0 0x40011640 +#define CYREG_B1_P3_U0_CFG1 0x40011641 +#define CYREG_B1_P3_U0_CFG2 0x40011642 +#define CYREG_B1_P3_U0_CFG3 0x40011643 +#define CYREG_B1_P3_U0_CFG4 0x40011644 +#define CYREG_B1_P3_U0_CFG5 0x40011645 +#define CYREG_B1_P3_U0_CFG6 0x40011646 +#define CYREG_B1_P3_U0_CFG7 0x40011647 +#define CYREG_B1_P3_U0_CFG8 0x40011648 +#define CYREG_B1_P3_U0_CFG9 0x40011649 +#define CYREG_B1_P3_U0_CFG10 0x4001164a +#define CYREG_B1_P3_U0_CFG11 0x4001164b +#define CYREG_B1_P3_U0_CFG12 0x4001164c +#define CYREG_B1_P3_U0_CFG13 0x4001164d +#define CYREG_B1_P3_U0_CFG14 0x4001164e +#define CYREG_B1_P3_U0_CFG15 0x4001164f +#define CYREG_B1_P3_U0_CFG16 0x40011650 +#define CYREG_B1_P3_U0_CFG17 0x40011651 +#define CYREG_B1_P3_U0_CFG18 0x40011652 +#define CYREG_B1_P3_U0_CFG19 0x40011653 +#define CYREG_B1_P3_U0_CFG20 0x40011654 +#define CYREG_B1_P3_U0_CFG21 0x40011655 +#define CYREG_B1_P3_U0_CFG22 0x40011656 +#define CYREG_B1_P3_U0_CFG23 0x40011657 +#define CYREG_B1_P3_U0_CFG24 0x40011658 +#define CYREG_B1_P3_U0_CFG25 0x40011659 +#define CYREG_B1_P3_U0_CFG26 0x4001165a +#define CYREG_B1_P3_U0_CFG27 0x4001165b +#define CYREG_B1_P3_U0_CFG28 0x4001165c +#define CYREG_B1_P3_U0_CFG29 0x4001165d +#define CYREG_B1_P3_U0_CFG30 0x4001165e +#define CYREG_B1_P3_U0_CFG31 0x4001165f +#define CYREG_B1_P3_U0_DCFG0 0x40011660 +#define CYREG_B1_P3_U0_DCFG1 0x40011662 +#define CYREG_B1_P3_U0_DCFG2 0x40011664 +#define CYREG_B1_P3_U0_DCFG3 0x40011666 +#define CYREG_B1_P3_U0_DCFG4 0x40011668 +#define CYREG_B1_P3_U0_DCFG5 0x4001166a +#define CYREG_B1_P3_U0_DCFG6 0x4001166c +#define CYREG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYREG_B1_P3_U1_CFG0 0x400116c0 +#define CYREG_B1_P3_U1_CFG1 0x400116c1 +#define CYREG_B1_P3_U1_CFG2 0x400116c2 +#define CYREG_B1_P3_U1_CFG3 0x400116c3 +#define CYREG_B1_P3_U1_CFG4 0x400116c4 +#define CYREG_B1_P3_U1_CFG5 0x400116c5 +#define CYREG_B1_P3_U1_CFG6 0x400116c6 +#define CYREG_B1_P3_U1_CFG7 0x400116c7 +#define CYREG_B1_P3_U1_CFG8 0x400116c8 +#define CYREG_B1_P3_U1_CFG9 0x400116c9 +#define CYREG_B1_P3_U1_CFG10 0x400116ca +#define CYREG_B1_P3_U1_CFG11 0x400116cb +#define CYREG_B1_P3_U1_CFG12 0x400116cc +#define CYREG_B1_P3_U1_CFG13 0x400116cd +#define CYREG_B1_P3_U1_CFG14 0x400116ce +#define CYREG_B1_P3_U1_CFG15 0x400116cf +#define CYREG_B1_P3_U1_CFG16 0x400116d0 +#define CYREG_B1_P3_U1_CFG17 0x400116d1 +#define CYREG_B1_P3_U1_CFG18 0x400116d2 +#define CYREG_B1_P3_U1_CFG19 0x400116d3 +#define CYREG_B1_P3_U1_CFG20 0x400116d4 +#define CYREG_B1_P3_U1_CFG21 0x400116d5 +#define CYREG_B1_P3_U1_CFG22 0x400116d6 +#define CYREG_B1_P3_U1_CFG23 0x400116d7 +#define CYREG_B1_P3_U1_CFG24 0x400116d8 +#define CYREG_B1_P3_U1_CFG25 0x400116d9 +#define CYREG_B1_P3_U1_CFG26 0x400116da +#define CYREG_B1_P3_U1_CFG27 0x400116db +#define CYREG_B1_P3_U1_CFG28 0x400116dc +#define CYREG_B1_P3_U1_CFG29 0x400116dd +#define CYREG_B1_P3_U1_CFG30 0x400116de +#define CYREG_B1_P3_U1_CFG31 0x400116df +#define CYREG_B1_P3_U1_DCFG0 0x400116e0 +#define CYREG_B1_P3_U1_DCFG1 0x400116e2 +#define CYREG_B1_P3_U1_DCFG2 0x400116e4 +#define CYREG_B1_P3_U1_DCFG3 0x400116e6 +#define CYREG_B1_P3_U1_DCFG4 0x400116e8 +#define CYREG_B1_P3_U1_DCFG5 0x400116ea +#define CYREG_B1_P3_U1_DCFG6 0x400116ec +#define CYREG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYREG_B1_P4_U0_CFG0 0x40011840 +#define CYREG_B1_P4_U0_CFG1 0x40011841 +#define CYREG_B1_P4_U0_CFG2 0x40011842 +#define CYREG_B1_P4_U0_CFG3 0x40011843 +#define CYREG_B1_P4_U0_CFG4 0x40011844 +#define CYREG_B1_P4_U0_CFG5 0x40011845 +#define CYREG_B1_P4_U0_CFG6 0x40011846 +#define CYREG_B1_P4_U0_CFG7 0x40011847 +#define CYREG_B1_P4_U0_CFG8 0x40011848 +#define CYREG_B1_P4_U0_CFG9 0x40011849 +#define CYREG_B1_P4_U0_CFG10 0x4001184a +#define CYREG_B1_P4_U0_CFG11 0x4001184b +#define CYREG_B1_P4_U0_CFG12 0x4001184c +#define CYREG_B1_P4_U0_CFG13 0x4001184d +#define CYREG_B1_P4_U0_CFG14 0x4001184e +#define CYREG_B1_P4_U0_CFG15 0x4001184f +#define CYREG_B1_P4_U0_CFG16 0x40011850 +#define CYREG_B1_P4_U0_CFG17 0x40011851 +#define CYREG_B1_P4_U0_CFG18 0x40011852 +#define CYREG_B1_P4_U0_CFG19 0x40011853 +#define CYREG_B1_P4_U0_CFG20 0x40011854 +#define CYREG_B1_P4_U0_CFG21 0x40011855 +#define CYREG_B1_P4_U0_CFG22 0x40011856 +#define CYREG_B1_P4_U0_CFG23 0x40011857 +#define CYREG_B1_P4_U0_CFG24 0x40011858 +#define CYREG_B1_P4_U0_CFG25 0x40011859 +#define CYREG_B1_P4_U0_CFG26 0x4001185a +#define CYREG_B1_P4_U0_CFG27 0x4001185b +#define CYREG_B1_P4_U0_CFG28 0x4001185c +#define CYREG_B1_P4_U0_CFG29 0x4001185d +#define CYREG_B1_P4_U0_CFG30 0x4001185e +#define CYREG_B1_P4_U0_CFG31 0x4001185f +#define CYREG_B1_P4_U0_DCFG0 0x40011860 +#define CYREG_B1_P4_U0_DCFG1 0x40011862 +#define CYREG_B1_P4_U0_DCFG2 0x40011864 +#define CYREG_B1_P4_U0_DCFG3 0x40011866 +#define CYREG_B1_P4_U0_DCFG4 0x40011868 +#define CYREG_B1_P4_U0_DCFG5 0x4001186a +#define CYREG_B1_P4_U0_DCFG6 0x4001186c +#define CYREG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYREG_B1_P4_U1_CFG0 0x400118c0 +#define CYREG_B1_P4_U1_CFG1 0x400118c1 +#define CYREG_B1_P4_U1_CFG2 0x400118c2 +#define CYREG_B1_P4_U1_CFG3 0x400118c3 +#define CYREG_B1_P4_U1_CFG4 0x400118c4 +#define CYREG_B1_P4_U1_CFG5 0x400118c5 +#define CYREG_B1_P4_U1_CFG6 0x400118c6 +#define CYREG_B1_P4_U1_CFG7 0x400118c7 +#define CYREG_B1_P4_U1_CFG8 0x400118c8 +#define CYREG_B1_P4_U1_CFG9 0x400118c9 +#define CYREG_B1_P4_U1_CFG10 0x400118ca +#define CYREG_B1_P4_U1_CFG11 0x400118cb +#define CYREG_B1_P4_U1_CFG12 0x400118cc +#define CYREG_B1_P4_U1_CFG13 0x400118cd +#define CYREG_B1_P4_U1_CFG14 0x400118ce +#define CYREG_B1_P4_U1_CFG15 0x400118cf +#define CYREG_B1_P4_U1_CFG16 0x400118d0 +#define CYREG_B1_P4_U1_CFG17 0x400118d1 +#define CYREG_B1_P4_U1_CFG18 0x400118d2 +#define CYREG_B1_P4_U1_CFG19 0x400118d3 +#define CYREG_B1_P4_U1_CFG20 0x400118d4 +#define CYREG_B1_P4_U1_CFG21 0x400118d5 +#define CYREG_B1_P4_U1_CFG22 0x400118d6 +#define CYREG_B1_P4_U1_CFG23 0x400118d7 +#define CYREG_B1_P4_U1_CFG24 0x400118d8 +#define CYREG_B1_P4_U1_CFG25 0x400118d9 +#define CYREG_B1_P4_U1_CFG26 0x400118da +#define CYREG_B1_P4_U1_CFG27 0x400118db +#define CYREG_B1_P4_U1_CFG28 0x400118dc +#define CYREG_B1_P4_U1_CFG29 0x400118dd +#define CYREG_B1_P4_U1_CFG30 0x400118de +#define CYREG_B1_P4_U1_CFG31 0x400118df +#define CYREG_B1_P4_U1_DCFG0 0x400118e0 +#define CYREG_B1_P4_U1_DCFG1 0x400118e2 +#define CYREG_B1_P4_U1_DCFG2 0x400118e4 +#define CYREG_B1_P4_U1_DCFG3 0x400118e6 +#define CYREG_B1_P4_U1_DCFG4 0x400118e8 +#define CYREG_B1_P4_U1_DCFG5 0x400118ea +#define CYREG_B1_P4_U1_DCFG6 0x400118ec +#define CYREG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYREG_B1_P5_U0_CFG0 0x40011a40 +#define CYREG_B1_P5_U0_CFG1 0x40011a41 +#define CYREG_B1_P5_U0_CFG2 0x40011a42 +#define CYREG_B1_P5_U0_CFG3 0x40011a43 +#define CYREG_B1_P5_U0_CFG4 0x40011a44 +#define CYREG_B1_P5_U0_CFG5 0x40011a45 +#define CYREG_B1_P5_U0_CFG6 0x40011a46 +#define CYREG_B1_P5_U0_CFG7 0x40011a47 +#define CYREG_B1_P5_U0_CFG8 0x40011a48 +#define CYREG_B1_P5_U0_CFG9 0x40011a49 +#define CYREG_B1_P5_U0_CFG10 0x40011a4a +#define CYREG_B1_P5_U0_CFG11 0x40011a4b +#define CYREG_B1_P5_U0_CFG12 0x40011a4c +#define CYREG_B1_P5_U0_CFG13 0x40011a4d +#define CYREG_B1_P5_U0_CFG14 0x40011a4e +#define CYREG_B1_P5_U0_CFG15 0x40011a4f +#define CYREG_B1_P5_U0_CFG16 0x40011a50 +#define CYREG_B1_P5_U0_CFG17 0x40011a51 +#define CYREG_B1_P5_U0_CFG18 0x40011a52 +#define CYREG_B1_P5_U0_CFG19 0x40011a53 +#define CYREG_B1_P5_U0_CFG20 0x40011a54 +#define CYREG_B1_P5_U0_CFG21 0x40011a55 +#define CYREG_B1_P5_U0_CFG22 0x40011a56 +#define CYREG_B1_P5_U0_CFG23 0x40011a57 +#define CYREG_B1_P5_U0_CFG24 0x40011a58 +#define CYREG_B1_P5_U0_CFG25 0x40011a59 +#define CYREG_B1_P5_U0_CFG26 0x40011a5a +#define CYREG_B1_P5_U0_CFG27 0x40011a5b +#define CYREG_B1_P5_U0_CFG28 0x40011a5c +#define CYREG_B1_P5_U0_CFG29 0x40011a5d +#define CYREG_B1_P5_U0_CFG30 0x40011a5e +#define CYREG_B1_P5_U0_CFG31 0x40011a5f +#define CYREG_B1_P5_U0_DCFG0 0x40011a60 +#define CYREG_B1_P5_U0_DCFG1 0x40011a62 +#define CYREG_B1_P5_U0_DCFG2 0x40011a64 +#define CYREG_B1_P5_U0_DCFG3 0x40011a66 +#define CYREG_B1_P5_U0_DCFG4 0x40011a68 +#define CYREG_B1_P5_U0_DCFG5 0x40011a6a +#define CYREG_B1_P5_U0_DCFG6 0x40011a6c +#define CYREG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYREG_B1_P5_U1_CFG0 0x40011ac0 +#define CYREG_B1_P5_U1_CFG1 0x40011ac1 +#define CYREG_B1_P5_U1_CFG2 0x40011ac2 +#define CYREG_B1_P5_U1_CFG3 0x40011ac3 +#define CYREG_B1_P5_U1_CFG4 0x40011ac4 +#define CYREG_B1_P5_U1_CFG5 0x40011ac5 +#define CYREG_B1_P5_U1_CFG6 0x40011ac6 +#define CYREG_B1_P5_U1_CFG7 0x40011ac7 +#define CYREG_B1_P5_U1_CFG8 0x40011ac8 +#define CYREG_B1_P5_U1_CFG9 0x40011ac9 +#define CYREG_B1_P5_U1_CFG10 0x40011aca +#define CYREG_B1_P5_U1_CFG11 0x40011acb +#define CYREG_B1_P5_U1_CFG12 0x40011acc +#define CYREG_B1_P5_U1_CFG13 0x40011acd +#define CYREG_B1_P5_U1_CFG14 0x40011ace +#define CYREG_B1_P5_U1_CFG15 0x40011acf +#define CYREG_B1_P5_U1_CFG16 0x40011ad0 +#define CYREG_B1_P5_U1_CFG17 0x40011ad1 +#define CYREG_B1_P5_U1_CFG18 0x40011ad2 +#define CYREG_B1_P5_U1_CFG19 0x40011ad3 +#define CYREG_B1_P5_U1_CFG20 0x40011ad4 +#define CYREG_B1_P5_U1_CFG21 0x40011ad5 +#define CYREG_B1_P5_U1_CFG22 0x40011ad6 +#define CYREG_B1_P5_U1_CFG23 0x40011ad7 +#define CYREG_B1_P5_U1_CFG24 0x40011ad8 +#define CYREG_B1_P5_U1_CFG25 0x40011ad9 +#define CYREG_B1_P5_U1_CFG26 0x40011ada +#define CYREG_B1_P5_U1_CFG27 0x40011adb +#define CYREG_B1_P5_U1_CFG28 0x40011adc +#define CYREG_B1_P5_U1_CFG29 0x40011add +#define CYREG_B1_P5_U1_CFG30 0x40011ade +#define CYREG_B1_P5_U1_CFG31 0x40011adf +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYREG_B1_P5_U1_DCFG5 0x40011aea +#define CYREG_B1_P5_U1_DCFG6 0x40011aec +#define CYREG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYREG_BCTL0_MDCLK_EN 0x40015000 +#define CYREG_BCTL0_MBCLK_EN 0x40015001 +#define CYREG_BCTL0_WAIT_CFG 0x40015002 +#define CYREG_BCTL0_BANK_CTL 0x40015003 +#define CYREG_BCTL0_UDB_TEST_3 0x40015007 +#define CYREG_BCTL0_DCLK_EN0 0x40015008 +#define CYREG_BCTL0_BCLK_EN0 0x40015009 +#define CYREG_BCTL0_DCLK_EN1 0x4001500a +#define CYREG_BCTL0_BCLK_EN1 0x4001500b +#define CYREG_BCTL0_DCLK_EN2 0x4001500c +#define CYREG_BCTL0_BCLK_EN2 0x4001500d +#define CYREG_BCTL0_DCLK_EN3 0x4001500e +#define CYREG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYREG_BCTL1_MDCLK_EN 0x40015010 +#define CYREG_BCTL1_MBCLK_EN 0x40015011 +#define CYREG_BCTL1_WAIT_CFG 0x40015012 +#define CYREG_BCTL1_BANK_CTL 0x40015013 +#define CYREG_BCTL1_UDB_TEST_3 0x40015017 +#define CYREG_BCTL1_DCLK_EN0 0x40015018 +#define CYREG_BCTL1_BCLK_EN0 0x40015019 +#define CYREG_BCTL1_DCLK_EN1 0x4001501a +#define CYREG_BCTL1_BCLK_EN1 0x4001501b +#define CYREG_BCTL1_DCLK_EN2 0x4001501c +#define CYREG_BCTL1_BCLK_EN2 0x4001501d +#define CYREG_BCTL1_DCLK_EN3 0x4001501e +#define CYREG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYREG_IDMUX_IRQ_CTL0 0x40015100 +#define CYREG_IDMUX_IRQ_CTL1 0x40015101 +#define CYREG_IDMUX_IRQ_CTL2 0x40015102 +#define CYREG_IDMUX_IRQ_CTL3 0x40015103 +#define CYREG_IDMUX_IRQ_CTL4 0x40015104 +#define CYREG_IDMUX_IRQ_CTL5 0x40015105 +#define CYREG_IDMUX_IRQ_CTL6 0x40015106 +#define CYREG_IDMUX_IRQ_CTL7 0x40015107 +#define CYREG_IDMUX_DRQ_CTL0 0x40015110 +#define CYREG_IDMUX_DRQ_CTL1 0x40015111 +#define CYREG_IDMUX_DRQ_CTL2 0x40015112 +#define CYREG_IDMUX_DRQ_CTL3 0x40015113 +#define CYREG_IDMUX_DRQ_CTL4 0x40015114 +#define CYREG_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYREG_CACHERAM_DATA_MBASE 0x40030000 +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYREG_SFR_GPIO0 0x40050180 +#define CYREG_SFR_GPIRD0 0x40050189 +#define CYREG_SFR_GPIO0_SEL 0x4005018a +#define CYREG_SFR_GPIO1 0x40050190 +#define CYREG_SFR_GPIRD1 0x40050191 +#define CYREG_SFR_GPIO2 0x40050198 +#define CYREG_SFR_GPIRD2 0x40050199 +#define CYREG_SFR_GPIO2_SEL 0x4005019a +#define CYREG_SFR_GPIO1_SEL 0x400501a2 +#define CYREG_SFR_GPIO3 0x400501b0 +#define CYREG_SFR_GPIRD3 0x400501b1 +#define CYREG_SFR_GPIO3_SEL 0x400501b2 +#define CYREG_SFR_GPIO4 0x400501c0 +#define CYREG_SFR_GPIRD4 0x400501c1 +#define CYREG_SFR_GPIO4_SEL 0x400501c2 +#define CYREG_SFR_GPIO5 0x400501c8 +#define CYREG_SFR_GPIRD5 0x400501c9 +#define CYREG_SFR_GPIO5_SEL 0x400501ca +#define CYREG_SFR_GPIO6 0x400501d8 +#define CYREG_SFR_GPIRD6 0x400501d9 +#define CYREG_SFR_GPIO6_SEL 0x400501da +#define CYREG_SFR_GPIO12 0x400501e8 +#define CYREG_SFR_GPIRD12 0x400501e9 +#define CYREG_SFR_GPIO12_SEL 0x400501f2 +#define CYREG_SFR_GPIO15 0x400501f8 +#define CYREG_SFR_GPIRD15 0x400501f9 +#define CYREG_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYREG_P3BA_Y_START 0x40050300 +#define CYREG_P3BA_YROLL 0x40050301 +#define CYREG_P3BA_YCFG 0x40050302 +#define CYREG_P3BA_X_START1 0x40050303 +#define CYREG_P3BA_X_START2 0x40050304 +#define CYREG_P3BA_XROLL1 0x40050305 +#define CYREG_P3BA_XROLL2 0x40050306 +#define CYREG_P3BA_XINC 0x40050307 +#define CYREG_P3BA_XCFG 0x40050308 +#define CYREG_P3BA_OFFSETADDR1 0x40050309 +#define CYREG_P3BA_OFFSETADDR2 0x4005030a +#define CYREG_P3BA_OFFSETADDR3 0x4005030b +#define CYREG_P3BA_ABSADDR1 0x4005030c +#define CYREG_P3BA_ABSADDR2 0x4005030d +#define CYREG_P3BA_ABSADDR3 0x4005030e +#define CYREG_P3BA_ABSADDR4 0x4005030f +#define CYREG_P3BA_DATCFG1 0x40050310 +#define CYREG_P3BA_DATCFG2 0x40050311 +#define CYREG_P3BA_CMP_RSLT1 0x40050314 +#define CYREG_P3BA_CMP_RSLT2 0x40050315 +#define CYREG_P3BA_CMP_RSLT3 0x40050316 +#define CYREG_P3BA_CMP_RSLT4 0x40050317 +#define CYREG_P3BA_DATA_REG1 0x40050318 +#define CYREG_P3BA_DATA_REG2 0x40050319 +#define CYREG_P3BA_DATA_REG3 0x4005031a +#define CYREG_P3BA_DATA_REG4 0x4005031b +#define CYREG_P3BA_EXP_DATA1 0x4005031c +#define CYREG_P3BA_EXP_DATA2 0x4005031d +#define CYREG_P3BA_EXP_DATA3 0x4005031e +#define CYREG_P3BA_EXP_DATA4 0x4005031f +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320 +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321 +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322 +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323 +#define CYREG_P3BA_BIST_EN 0x40050324 +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYREG_P3BA_SEQCFG1 0x40050326 +#define CYREG_P3BA_SEQCFG2 0x40050327 +#define CYREG_P3BA_Y_CURR 0x40050328 +#define CYREG_P3BA_X_CURR1 0x40050329 +#define CYREG_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYREG_PANTHER_STCALIB_CFG 0x40080000 +#define CYREG_PANTHER_WAITPIPE 0x40080004 +#define CYREG_PANTHER_TRACE_CFG 0x40080008 +#define CYREG_PANTHER_DBG_CFG 0x4008000c +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYREG_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYREG_FLSECC_DATA_MBASE 0x48000000 +#define CYREG_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYREG_FLSHID_RSVD_MBASE 0x49000000 +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080 +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYREG_EXTMEM_DATA_MBASE 0x60000000 +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYREG_ITM_TRACE_EN 0xe0000e00 +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYREG_ITM_TRACE_CTRL 0xe0000e80 +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4 +#define CYREG_ITM_PID4 0xe0000fd0 +#define CYREG_ITM_PID5 0xe0000fd4 +#define CYREG_ITM_PID6 0xe0000fd8 +#define CYREG_ITM_PID7 0xe0000fdc +#define CYREG_ITM_PID0 0xe0000fe0 +#define CYREG_ITM_PID1 0xe0000fe4 +#define CYREG_ITM_PID2 0xe0000fe8 +#define CYREG_ITM_PID3 0xe0000fec +#define CYREG_ITM_CID0 0xe0000ff0 +#define CYREG_ITM_CID1 0xe0000ff4 +#define CYREG_ITM_CID2 0xe0000ff8 +#define CYREG_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYREG_DWT_CTRL 0xe0001000 +#define CYREG_DWT_CYCLE_COUNT 0xe0001004 +#define CYREG_DWT_CPI_COUNT 0xe0001008 +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYREG_DWT_SLEEP_COUNT 0xe0001010 +#define CYREG_DWT_LSU_COUNT 0xe0001014 +#define CYREG_DWT_FOLD_COUNT 0xe0001018 +#define CYREG_DWT_PC_SAMPLE 0xe000101c +#define CYREG_DWT_COMP_0 0xe0001020 +#define CYREG_DWT_MASK_0 0xe0001024 +#define CYREG_DWT_FUNCTION_0 0xe0001028 +#define CYREG_DWT_COMP_1 0xe0001030 +#define CYREG_DWT_MASK_1 0xe0001034 +#define CYREG_DWT_FUNCTION_1 0xe0001038 +#define CYREG_DWT_COMP_2 0xe0001040 +#define CYREG_DWT_MASK_2 0xe0001044 +#define CYREG_DWT_FUNCTION_2 0xe0001048 +#define CYREG_DWT_COMP_3 0xe0001050 +#define CYREG_DWT_MASK_3 0xe0001054 +#define CYREG_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYREG_FPB_CTRL 0xe0002000 +#define CYREG_FPB_REMAP 0xe0002004 +#define CYREG_FPB_FP_COMP_0 0xe0002008 +#define CYREG_FPB_FP_COMP_1 0xe000200c +#define CYREG_FPB_FP_COMP_2 0xe0002010 +#define CYREG_FPB_FP_COMP_3 0xe0002014 +#define CYREG_FPB_FP_COMP_4 0xe0002018 +#define CYREG_FPB_FP_COMP_5 0xe000201c +#define CYREG_FPB_FP_COMP_6 0xe0002020 +#define CYREG_FPB_FP_COMP_7 0xe0002024 +#define CYREG_FPB_PID4 0xe0002fd0 +#define CYREG_FPB_PID5 0xe0002fd4 +#define CYREG_FPB_PID6 0xe0002fd8 +#define CYREG_FPB_PID7 0xe0002fdc +#define CYREG_FPB_PID0 0xe0002fe0 +#define CYREG_FPB_PID1 0xe0002fe4 +#define CYREG_FPB_PID2 0xe0002fe8 +#define CYREG_FPB_PID3 0xe0002fec +#define CYREG_FPB_CID0 0xe0002ff0 +#define CYREG_FPB_CID1 0xe0002ff4 +#define CYREG_FPB_CID2 0xe0002ff8 +#define CYREG_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010 +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c +#define CYREG_NVIC_SETENA0 0xe000e100 +#define CYREG_NVIC_CLRENA0 0xe000e180 +#define CYREG_NVIC_SETPEND0 0xe000e200 +#define CYREG_NVIC_CLRPEND0 0xe000e280 +#define CYREG_NVIC_ACTIVE0 0xe000e300 +#define CYREG_NVIC_PRI_0 0xe000e400 +#define CYREG_NVIC_PRI_1 0xe000e401 +#define CYREG_NVIC_PRI_2 0xe000e402 +#define CYREG_NVIC_PRI_3 0xe000e403 +#define CYREG_NVIC_PRI_4 0xe000e404 +#define CYREG_NVIC_PRI_5 0xe000e405 +#define CYREG_NVIC_PRI_6 0xe000e406 +#define CYREG_NVIC_PRI_7 0xe000e407 +#define CYREG_NVIC_PRI_8 0xe000e408 +#define CYREG_NVIC_PRI_9 0xe000e409 +#define CYREG_NVIC_PRI_10 0xe000e40a +#define CYREG_NVIC_PRI_11 0xe000e40b +#define CYREG_NVIC_PRI_12 0xe000e40c +#define CYREG_NVIC_PRI_13 0xe000e40d +#define CYREG_NVIC_PRI_14 0xe000e40e +#define CYREG_NVIC_PRI_15 0xe000e40f +#define CYREG_NVIC_PRI_16 0xe000e410 +#define CYREG_NVIC_PRI_17 0xe000e411 +#define CYREG_NVIC_PRI_18 0xe000e412 +#define CYREG_NVIC_PRI_19 0xe000e413 +#define CYREG_NVIC_PRI_20 0xe000e414 +#define CYREG_NVIC_PRI_21 0xe000e415 +#define CYREG_NVIC_PRI_22 0xe000e416 +#define CYREG_NVIC_PRI_23 0xe000e417 +#define CYREG_NVIC_PRI_24 0xe000e418 +#define CYREG_NVIC_PRI_25 0xe000e419 +#define CYREG_NVIC_PRI_26 0xe000e41a +#define CYREG_NVIC_PRI_27 0xe000e41b +#define CYREG_NVIC_PRI_28 0xe000e41c +#define CYREG_NVIC_PRI_29 0xe000e41d +#define CYREG_NVIC_PRI_30 0xe000e41e +#define CYREG_NVIC_PRI_31 0xe000e41f +#define CYREG_NVIC_CPUID_BASE 0xe000ed00 +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08 +#define CYREG_NVIC_APPLN_INTR 0xe000ed0c +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14 +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYREG_TPIU_PROTOCOL 0xe00400f0 +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYREG_TPIU_TRIGGER 0xe0040ee8 +#define CYREG_TPIU_ITETMDATA 0xe0040eec +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0 +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8 +#define CYREG_TPIU_ITITMDATA 0xe0040efc +#define CYREG_TPIU_ITCTRL 0xe0040f00 +#define CYREG_TPIU_DEVID 0xe0040fc8 +#define CYREG_TPIU_DEVTYPE 0xe0040fcc +#define CYREG_TPIU_PID4 0xe0040fd0 +#define CYREG_TPIU_PID5 0xe0040fd4 +#define CYREG_TPIU_PID6 0xe0040fd8 +#define CYREG_TPIU_PID7 0xe0040fdc +#define CYREG_TPIU_PID0 0xe0040fe0 +#define CYREG_TPIU_PID1 0xe0040fe4 +#define CYREG_TPIU_PID2 0xe0040fe8 +#define CYREG_TPIU_PID3 0xe0040fec +#define CYREG_TPIU_CID0 0xe0040ff0 +#define CYREG_TPIU_CID1 0xe0040ff4 +#define CYREG_TPIU_CID2 0xe0040ff8 +#define CYREG_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYREG_ETM_CTL 0xe0041000 +#define CYREG_ETM_CFG_CODE 0xe0041004 +#define CYREG_ETM_TRIG_EVENT 0xe0041008 +#define CYREG_ETM_STATUS 0xe0041010 +#define CYREG_ETM_SYS_CFG 0xe0041014 +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYREG_ETM_SYNC_FREQ 0xe00411e0 +#define CYREG_ETM_ETM_ID 0xe00411e4 +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYREG_ETM_CS_TRACE_ID 0xe0041200 +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYREG_ETM_PDSR 0xe0041314 +#define CYREG_ETM_ITMISCIN 0xe0041ee0 +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8 +#define CYREG_ETM_ITATBCTR2 0xe0041ef0 +#define CYREG_ETM_ITATBCTR0 0xe0041ef8 +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4 +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8 +#define CYREG_ETM_DEV_TYPE 0xe0041fcc +#define CYREG_ETM_PID4 0xe0041fd0 +#define CYREG_ETM_PID5 0xe0041fd4 +#define CYREG_ETM_PID6 0xe0041fd8 +#define CYREG_ETM_PID7 0xe0041fdc +#define CYREG_ETM_PID0 0xe0041fe0 +#define CYREG_ETM_PID1 0xe0041fe4 +#define CYREG_ETM_PID2 0xe0041fe8 +#define CYREG_ETM_PID3 0xe0041fec +#define CYREG_ETM_CID0 0xe0041ff0 +#define CYREG_ETM_CID1 0xe0041ff4 +#define CYREG_ETM_CID2 0xe0041ff8 +#define CYREG_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYREG_ROM_TABLE_NVIC 0xe00ff000 +#define CYREG_ROM_TABLE_DWT 0xe00ff004 +#define CYREG_ROM_TABLE_FPB 0xe00ff008 +#define CYREG_ROM_TABLE_ITM 0xe00ff00c +#define CYREG_ROM_TABLE_TPIU 0xe00ff010 +#define CYREG_ROM_TABLE_ETM 0xe00ff014 +#define CYREG_ROM_TABLE_END 0xe00ff018 +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYREG_ROM_TABLE_PID4 0xe00fffd0 +#define CYREG_ROM_TABLE_PID5 0xe00fffd4 +#define CYREG_ROM_TABLE_PID6 0xe00fffd8 +#define CYREG_ROM_TABLE_PID7 0xe00fffdc +#define CYREG_ROM_TABLE_PID0 0xe00fffe0 +#define CYREG_ROM_TABLE_PID1 0xe00fffe4 +#define CYREG_ROM_TABLE_PID2 0xe00fffe8 +#define CYREG_ROM_TABLE_PID3 0xe00fffec +#define CYREG_ROM_TABLE_CID0 0xe00ffff0 +#define CYREG_ROM_TABLE_CID1 0xe00ffff4 +#define CYREG_ROM_TABLE_CID2 0xe00ffff8 +#define CYREG_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc new file mode 100644 index 0000000..cff336b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -0,0 +1,16039 @@ +; +; File Name: cydevicerv.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc new file mode 100644 index 0000000..fc79212 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -0,0 +1,16039 @@ +; +; File Name: cydevicerv_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h new file mode 100644 index 0000000..8178873 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h new file mode 100644 index 0000000..c917e54 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -0,0 +1,2858 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice.h" +#include "cydevice_trm.h" + +/* LED1 */ +#define LED1__0__INTTYPE CYREG_PICU12_INTTYPE2 +#define LED1__0__MASK 0x04u +#define LED1__0__PC CYREG_PRT12_PC2 +#define LED1__0__PORT 12u +#define LED1__0__SHIFT 2u +#define LED1__1__INTTYPE CYREG_PICU12_INTTYPE3 +#define LED1__1__MASK 0x08u +#define LED1__1__PC CYREG_PRT12_PC3 +#define LED1__1__PORT 12u +#define LED1__1__SHIFT 3u +#define LED1__AG CYREG_PRT12_AG +#define LED1__BIE CYREG_PRT12_BIE +#define LED1__BIT_MASK CYREG_PRT12_BIT_MASK +#define LED1__BYP CYREG_PRT12_BYP +#define LED1__DM0 CYREG_PRT12_DM0 +#define LED1__DM1 CYREG_PRT12_DM1 +#define LED1__DM2 CYREG_PRT12_DM2 +#define LED1__DR CYREG_PRT12_DR +#define LED1__INP_DIS CYREG_PRT12_INP_DIS +#define LED1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define LED1__MASK 0x0Cu +#define LED1__PORT 12u +#define LED1__PRT CYREG_PRT12_PRT +#define LED1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define LED1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define LED1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define LED1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define LED1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define LED1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define LED1__PS CYREG_PRT12_PS +#define LED1__SHIFT 2u +#define LED1__SIO_CFG CYREG_PRT12_SIO_CFG +#define LED1__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define LED1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define LED1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define LED1__SLW CYREG_PRT12_SLW + +/* SD_CS */ +#define SD_CS__0__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_CS__0__MASK 0x08u +#define SD_CS__0__PC CYREG_PRT3_PC3 +#define SD_CS__0__PORT 3u +#define SD_CS__0__SHIFT 3u +#define SD_CS__AG CYREG_PRT3_AG +#define SD_CS__AMUX CYREG_PRT3_AMUX +#define SD_CS__BIE CYREG_PRT3_BIE +#define SD_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_CS__BYP CYREG_PRT3_BYP +#define SD_CS__CTL CYREG_PRT3_CTL +#define SD_CS__DM0 CYREG_PRT3_DM0 +#define SD_CS__DM1 CYREG_PRT3_DM1 +#define SD_CS__DM2 CYREG_PRT3_DM2 +#define SD_CS__DR CYREG_PRT3_DR +#define SD_CS__INP_DIS CYREG_PRT3_INP_DIS +#define SD_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_CS__LCD_EN CYREG_PRT3_LCD_EN +#define SD_CS__MASK 0x08u +#define SD_CS__PORT 3u +#define SD_CS__PRT CYREG_PRT3_PRT +#define SD_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_CS__PS CYREG_PRT3_PS +#define SD_CS__SHIFT 3u +#define SD_CS__SLW CYREG_PRT3_SLW + +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 6u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x80u +#define USBFS_ep_1__INTC_NUMBER 7u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_7 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x100u +#define USBFS_ep_2__INTC_NUMBER 8u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_8 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_3__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_3__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_3__INTC_MASK 0x200u +#define USBFS_ep_3__INTC_NUMBER 9u +#define USBFS_ep_3__INTC_PRIOR_NUM 7u +#define USBFS_ep_3__INTC_PRIOR_REG CYREG_NVIC_PRI_9 +#define USBFS_ep_3__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_3__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_4__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_4__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_4__INTC_MASK 0x400u +#define USBFS_ep_4__INTC_NUMBER 10u +#define USBFS_ep_4__INTC_PRIOR_NUM 7u +#define USBFS_ep_4__INTC_PRIOR_REG CYREG_NVIC_PRI_10 +#define USBFS_ep_4__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_4__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 + +/* SDCard */ +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST +#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_RxStsReg__4__POS 4 +#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u +#define SDCard_BSPIM_RxStsReg__5__POS 5 +#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u +#define SDCard_BSPIM_RxStsReg__6__POS 6 +#define SDCard_BSPIM_RxStsReg__MASK 0x70u +#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB04_05_D1 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB04_05_F0 +#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB04_05_F1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB04_A0_A1 +#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB04_A0 +#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB04_A1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB04_D0_D1 +#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB04_D0 +#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB04_D1 +#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB04_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 +#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 +#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 +#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL +#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u +#define SDCard_BSPIM_TxStsReg__0__POS 0 +#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u +#define SDCard_BSPIM_TxStsReg__1__POS 1 +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u +#define SDCard_BSPIM_TxStsReg__2__POS 2 +#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u +#define SDCard_BSPIM_TxStsReg__3__POS 3 +#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u +#define SDCard_BSPIM_TxStsReg__4__POS 4 +#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST + +/* SD_SCK */ +#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_SCK__0__MASK 0x02u +#define SD_SCK__0__PC CYREG_PRT3_PC1 +#define SD_SCK__0__PORT 3u +#define SD_SCK__0__SHIFT 1u +#define SD_SCK__AG CYREG_PRT3_AG +#define SD_SCK__AMUX CYREG_PRT3_AMUX +#define SD_SCK__BIE CYREG_PRT3_BIE +#define SD_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_SCK__BYP CYREG_PRT3_BYP +#define SD_SCK__CTL CYREG_PRT3_CTL +#define SD_SCK__DM0 CYREG_PRT3_DM0 +#define SD_SCK__DM1 CYREG_PRT3_DM1 +#define SD_SCK__DM2 CYREG_PRT3_DM2 +#define SD_SCK__DR CYREG_PRT3_DR +#define SD_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define SD_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define SD_SCK__MASK 0x02u +#define SD_SCK__PORT 3u +#define SD_SCK__PRT CYREG_PRT3_PRT +#define SD_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_SCK__PS CYREG_PRT3_PS +#define SD_SCK__SHIFT 1u +#define SD_SCK__SLW CYREG_PRT3_SLW + +/* SCSI_In */ +#define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 +#define SCSI_In__0__MASK 0x02u +#define SCSI_In__0__PC CYREG_PRT6_PC1 +#define SCSI_In__0__PORT 6u +#define SCSI_In__0__SHIFT 1u +#define SCSI_In__AG CYREG_PRT6_AG +#define SCSI_In__AMUX CYREG_PRT6_AMUX +#define SCSI_In__BIE CYREG_PRT6_BIE +#define SCSI_In__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In__BYP CYREG_PRT6_BYP +#define SCSI_In__CTL CYREG_PRT6_CTL +#define SCSI_In__DBP__INTTYPE CYREG_PICU6_INTTYPE1 +#define SCSI_In__DBP__MASK 0x02u +#define SCSI_In__DBP__PC CYREG_PRT6_PC1 +#define SCSI_In__DBP__PORT 6u +#define SCSI_In__DBP__SHIFT 1u +#define SCSI_In__DM0 CYREG_PRT6_DM0 +#define SCSI_In__DM1 CYREG_PRT6_DM1 +#define SCSI_In__DM2 CYREG_PRT6_DM2 +#define SCSI_In__DR CYREG_PRT6_DR +#define SCSI_In__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU6_BASE +#define SCSI_In__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In__MASK 0x02u +#define SCSI_In__PORT 6u +#define SCSI_In__PRT CYREG_PRT6_PRT +#define SCSI_In__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In__PS CYREG_PRT6_PS +#define SCSI_In__SHIFT 1u +#define SCSI_In__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__0__AG CYREG_PRT6_AG +#define SCSI_In_DBx__0__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__0__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__0__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__0__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__0__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__0__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__0__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__0__DR CYREG_PRT6_DR +#define SCSI_In_DBx__0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__0__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_In_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__0__MASK 0x40u +#define SCSI_In_DBx__0__PC CYREG_PRT6_PC6 +#define SCSI_In_DBx__0__PORT 6u +#define SCSI_In_DBx__0__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__0__PS CYREG_PRT6_PS +#define SCSI_In_DBx__0__SHIFT 6u +#define SCSI_In_DBx__0__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__1__AG CYREG_PRT6_AG +#define SCSI_In_DBx__1__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__1__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__1__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__1__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__1__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__1__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__1__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__1__DR CYREG_PRT6_DR +#define SCSI_In_DBx__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__1__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_In_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__1__MASK 0x10u +#define SCSI_In_DBx__1__PC CYREG_PRT6_PC4 +#define SCSI_In_DBx__1__PORT 6u +#define SCSI_In_DBx__1__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__1__PS CYREG_PRT6_PS +#define SCSI_In_DBx__1__SHIFT 4u +#define SCSI_In_DBx__1__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__2__AG CYREG_PRT12_AG +#define SCSI_In_DBx__2__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__2__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__2__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__2__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__2__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__2__DR CYREG_PRT12_DR +#define SCSI_In_DBx__2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__2__INTTYPE CYREG_PICU12_INTTYPE4 +#define SCSI_In_DBx__2__MASK 0x10u +#define SCSI_In_DBx__2__PC CYREG_PRT12_PC4 +#define SCSI_In_DBx__2__PORT 12u +#define SCSI_In_DBx__2__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__2__PS CYREG_PRT12_PS +#define SCSI_In_DBx__2__SHIFT 4u +#define SCSI_In_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__2__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__3__AG CYREG_PRT2_AG +#define SCSI_In_DBx__3__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__3__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__3__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__3__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__3__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__3__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__3__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__3__DR CYREG_PRT2_DR +#define SCSI_In_DBx__3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__3__INTTYPE CYREG_PICU2_INTTYPE6 +#define SCSI_In_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__3__MASK 0x40u +#define SCSI_In_DBx__3__PC CYREG_PRT2_PC6 +#define SCSI_In_DBx__3__PORT 2u +#define SCSI_In_DBx__3__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__3__PS CYREG_PRT2_PS +#define SCSI_In_DBx__3__SHIFT 6u +#define SCSI_In_DBx__3__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__4__AG CYREG_PRT2_AG +#define SCSI_In_DBx__4__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__4__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__4__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__4__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__4__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__4__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__4__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__4__DR CYREG_PRT2_DR +#define SCSI_In_DBx__4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__4__INTTYPE CYREG_PICU2_INTTYPE4 +#define SCSI_In_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__4__MASK 0x10u +#define SCSI_In_DBx__4__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__4__PORT 2u +#define SCSI_In_DBx__4__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__4__PS CYREG_PRT2_PS +#define SCSI_In_DBx__4__SHIFT 4u +#define SCSI_In_DBx__4__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__5__AG CYREG_PRT2_AG +#define SCSI_In_DBx__5__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__5__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__5__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__5__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__5__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__5__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__5__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__5__DR CYREG_PRT2_DR +#define SCSI_In_DBx__5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__5__INTTYPE CYREG_PICU2_INTTYPE2 +#define SCSI_In_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__5__MASK 0x04u +#define SCSI_In_DBx__5__PC CYREG_PRT2_PC2 +#define SCSI_In_DBx__5__PORT 2u +#define SCSI_In_DBx__5__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__5__PS CYREG_PRT2_PS +#define SCSI_In_DBx__5__SHIFT 2u +#define SCSI_In_DBx__5__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__6__AG CYREG_PRT2_AG +#define SCSI_In_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__6__DR CYREG_PRT2_DR +#define SCSI_In_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__6__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_In_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__6__MASK 0x01u +#define SCSI_In_DBx__6__PC CYREG_PRT2_PC0 +#define SCSI_In_DBx__6__PORT 2u +#define SCSI_In_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__6__PS CYREG_PRT2_PS +#define SCSI_In_DBx__6__SHIFT 0u +#define SCSI_In_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__7__AG CYREG_PRT6_AG +#define SCSI_In_DBx__7__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__7__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__7__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__7__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__7__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__7__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__7__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__7__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__7__DR CYREG_PRT6_DR +#define SCSI_In_DBx__7__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__7__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_In_DBx__7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__7__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__7__MASK 0x08u +#define SCSI_In_DBx__7__PC CYREG_PRT6_PC3 +#define SCSI_In_DBx__7__PORT 6u +#define SCSI_In_DBx__7__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__7__PS CYREG_PRT6_PS +#define SCSI_In_DBx__7__SHIFT 3u +#define SCSI_In_DBx__7__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__DB0__AG CYREG_PRT6_AG +#define SCSI_In_DBx__DB0__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__DB0__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__DB0__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__DB0__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__DB0__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__DB0__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__DB0__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__DB0__DR CYREG_PRT6_DR +#define SCSI_In_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE6 +#define SCSI_In_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__DB0__MASK 0x40u +#define SCSI_In_DBx__DB0__PC CYREG_PRT6_PC6 +#define SCSI_In_DBx__DB0__PORT 6u +#define SCSI_In_DBx__DB0__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__DB0__PS CYREG_PRT6_PS +#define SCSI_In_DBx__DB0__SHIFT 6u +#define SCSI_In_DBx__DB0__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__DB1__AG CYREG_PRT6_AG +#define SCSI_In_DBx__DB1__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__DB1__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__DB1__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__DB1__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__DB1__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__DB1__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__DB1__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__DB1__DR CYREG_PRT6_DR +#define SCSI_In_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE4 +#define SCSI_In_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__DB1__MASK 0x10u +#define SCSI_In_DBx__DB1__PC CYREG_PRT6_PC4 +#define SCSI_In_DBx__DB1__PORT 6u +#define SCSI_In_DBx__DB1__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__DB1__PS CYREG_PRT6_PS +#define SCSI_In_DBx__DB1__SHIFT 4u +#define SCSI_In_DBx__DB1__SLW CYREG_PRT6_SLW +#define SCSI_In_DBx__DB2__AG CYREG_PRT12_AG +#define SCSI_In_DBx__DB2__BIE CYREG_PRT12_BIE +#define SCSI_In_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_In_DBx__DB2__BYP CYREG_PRT12_BYP +#define SCSI_In_DBx__DB2__DM0 CYREG_PRT12_DM0 +#define SCSI_In_DBx__DB2__DM1 CYREG_PRT12_DM1 +#define SCSI_In_DBx__DB2__DM2 CYREG_PRT12_DM2 +#define SCSI_In_DBx__DB2__DR CYREG_PRT12_DR +#define SCSI_In_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_In_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE4 +#define SCSI_In_DBx__DB2__MASK 0x10u +#define SCSI_In_DBx__DB2__PC CYREG_PRT12_PC4 +#define SCSI_In_DBx__DB2__PORT 12u +#define SCSI_In_DBx__DB2__PRT CYREG_PRT12_PRT +#define SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_In_DBx__DB2__PS CYREG_PRT12_PS +#define SCSI_In_DBx__DB2__SHIFT 4u +#define SCSI_In_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_In_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_In_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_In_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_In_DBx__DB2__SLW CYREG_PRT12_SLW +#define SCSI_In_DBx__DB3__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB3__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB3__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB3__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB3__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB3__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB3__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB3__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB3__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE6 +#define SCSI_In_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB3__MASK 0x40u +#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC6 +#define SCSI_In_DBx__DB3__PORT 2u +#define SCSI_In_DBx__DB3__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB3__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB3__SHIFT 6u +#define SCSI_In_DBx__DB3__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB4__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB4__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB4__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB4__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB4__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB4__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB4__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB4__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB4__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE4 +#define SCSI_In_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB4__MASK 0x10u +#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4 +#define SCSI_In_DBx__DB4__PORT 2u +#define SCSI_In_DBx__DB4__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB4__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB4__SHIFT 4u +#define SCSI_In_DBx__DB4__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB5__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB5__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB5__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB5__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB5__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB5__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB5__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB5__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB5__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE2 +#define SCSI_In_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB5__MASK 0x04u +#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC2 +#define SCSI_In_DBx__DB5__PORT 2u +#define SCSI_In_DBx__DB5__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB5__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB5__SHIFT 2u +#define SCSI_In_DBx__DB5__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_In_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_In_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_In_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_In_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_In_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_In_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_In_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_In_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_In_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_In_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_In_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE0 +#define SCSI_In_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_In_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_In_DBx__DB6__MASK 0x01u +#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC0 +#define SCSI_In_DBx__DB6__PORT 2u +#define SCSI_In_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_In_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_In_DBx__DB6__SHIFT 0u +#define SCSI_In_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_In_DBx__DB7__AG CYREG_PRT6_AG +#define SCSI_In_DBx__DB7__AMUX CYREG_PRT6_AMUX +#define SCSI_In_DBx__DB7__BIE CYREG_PRT6_BIE +#define SCSI_In_DBx__DB7__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_In_DBx__DB7__BYP CYREG_PRT6_BYP +#define SCSI_In_DBx__DB7__CTL CYREG_PRT6_CTL +#define SCSI_In_DBx__DB7__DM0 CYREG_PRT6_DM0 +#define SCSI_In_DBx__DB7__DM1 CYREG_PRT6_DM1 +#define SCSI_In_DBx__DB7__DM2 CYREG_PRT6_DM2 +#define SCSI_In_DBx__DB7__DR CYREG_PRT6_DR +#define SCSI_In_DBx__DB7__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_In_DBx__DB7__INTTYPE CYREG_PICU6_INTTYPE3 +#define SCSI_In_DBx__DB7__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_In_DBx__DB7__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_In_DBx__DB7__MASK 0x08u +#define SCSI_In_DBx__DB7__PC CYREG_PRT6_PC3 +#define SCSI_In_DBx__DB7__PORT 6u +#define SCSI_In_DBx__DB7__PRT CYREG_PRT6_PRT +#define SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_In_DBx__DB7__PS CYREG_PRT6_PS +#define SCSI_In_DBx__DB7__SHIFT 3u +#define SCSI_In_DBx__DB7__SLW CYREG_PRT6_SLW + +/* SD_MISO */ +#define SD_MISO__0__INTTYPE CYREG_PICU3_INTTYPE0 +#define SD_MISO__0__MASK 0x01u +#define SD_MISO__0__PC CYREG_PRT3_PC0 +#define SD_MISO__0__PORT 3u +#define SD_MISO__0__SHIFT 0u +#define SD_MISO__AG CYREG_PRT3_AG +#define SD_MISO__AMUX CYREG_PRT3_AMUX +#define SD_MISO__BIE CYREG_PRT3_BIE +#define SD_MISO__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MISO__BYP CYREG_PRT3_BYP +#define SD_MISO__CTL CYREG_PRT3_CTL +#define SD_MISO__DM0 CYREG_PRT3_DM0 +#define SD_MISO__DM1 CYREG_PRT3_DM1 +#define SD_MISO__DM2 CYREG_PRT3_DM2 +#define SD_MISO__DR CYREG_PRT3_DR +#define SD_MISO__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MISO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MISO__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MISO__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MISO__MASK 0x01u +#define SD_MISO__PORT 3u +#define SD_MISO__PRT CYREG_PRT3_PRT +#define SD_MISO__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MISO__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MISO__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MISO__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MISO__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MISO__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MISO__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MISO__PS CYREG_PRT3_PS +#define SD_MISO__SHIFT 0u +#define SD_MISO__SLW CYREG_PRT3_SLW + +/* SD_MOSI */ +#define SD_MOSI__0__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_MOSI__0__MASK 0x04u +#define SD_MOSI__0__PC CYREG_PRT3_PC2 +#define SD_MOSI__0__PORT 3u +#define SD_MOSI__0__SHIFT 2u +#define SD_MOSI__AG CYREG_PRT3_AG +#define SD_MOSI__AMUX CYREG_PRT3_AMUX +#define SD_MOSI__BIE CYREG_PRT3_BIE +#define SD_MOSI__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_MOSI__BYP CYREG_PRT3_BYP +#define SD_MOSI__CTL CYREG_PRT3_CTL +#define SD_MOSI__DM0 CYREG_PRT3_DM0 +#define SD_MOSI__DM1 CYREG_PRT3_DM1 +#define SD_MOSI__DM2 CYREG_PRT3_DM2 +#define SD_MOSI__DR CYREG_PRT3_DR +#define SD_MOSI__INP_DIS CYREG_PRT3_INP_DIS +#define SD_MOSI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_MOSI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_MOSI__LCD_EN CYREG_PRT3_LCD_EN +#define SD_MOSI__MASK 0x04u +#define SD_MOSI__PORT 3u +#define SD_MOSI__PRT CYREG_PRT3_PRT +#define SD_MOSI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_MOSI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_MOSI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_MOSI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_MOSI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_MOSI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_MOSI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_MOSI__PS CYREG_PRT3_PS +#define SD_MOSI__SHIFT 2u +#define SD_MOSI__SLW CYREG_PRT3_SLW + +/* TERM_EN */ +#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3 +#define TERM_EN__0__MASK 0x08u +#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3 +#define TERM_EN__0__PORT 15u +#define TERM_EN__0__SHIFT 3u +#define TERM_EN__AG CYREG_PRT15_AG +#define TERM_EN__AMUX CYREG_PRT15_AMUX +#define TERM_EN__BIE CYREG_PRT15_BIE +#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK +#define TERM_EN__BYP CYREG_PRT15_BYP +#define TERM_EN__CTL CYREG_PRT15_CTL +#define TERM_EN__DM0 CYREG_PRT15_DM0 +#define TERM_EN__DM1 CYREG_PRT15_DM1 +#define TERM_EN__DM2 CYREG_PRT15_DM2 +#define TERM_EN__DR CYREG_PRT15_DR +#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS +#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN +#define TERM_EN__MASK 0x08u +#define TERM_EN__PORT 15u +#define TERM_EN__PRT CYREG_PRT15_PRT +#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define TERM_EN__PS CYREG_PRT15_PS +#define TERM_EN__SHIFT 3u +#define TERM_EN__SLW CYREG_PRT15_SLW + +/* SCSI_CLK */ +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u +#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SCSI_CLK__PM_STBY_MSK 0x02u + +/* SCSI_Out */ +#define SCSI_Out__0__AG CYREG_PRT6_AG +#define SCSI_Out__0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__0__BIE CYREG_PRT6_BIE +#define SCSI_Out__0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__0__BYP CYREG_PRT6_BYP +#define SCSI_Out__0__CTL CYREG_PRT6_CTL +#define SCSI_Out__0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__0__DR CYREG_PRT6_DR +#define SCSI_Out__0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__0__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__0__MASK 0x04u +#define SCSI_Out__0__PC CYREG_PRT6_PC2 +#define SCSI_Out__0__PORT 6u +#define SCSI_Out__0__PRT CYREG_PRT6_PRT +#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__0__PS CYREG_PRT6_PS +#define SCSI_Out__0__SHIFT 2u +#define SCSI_Out__0__SLW CYREG_PRT6_SLW +#define SCSI_Out__1__AG CYREG_PRT4_AG +#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__1__BIE CYREG_PRT4_BIE +#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__1__BYP CYREG_PRT4_BYP +#define SCSI_Out__1__CTL CYREG_PRT4_CTL +#define SCSI_Out__1__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__1__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__1__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__1__DR CYREG_PRT4_DR +#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE6 +#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__1__MASK 0x40u +#define SCSI_Out__1__PC CYREG_PRT4_PC6 +#define SCSI_Out__1__PORT 4u +#define SCSI_Out__1__PRT CYREG_PRT4_PRT +#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__1__PS CYREG_PRT4_PS +#define SCSI_Out__1__SHIFT 6u +#define SCSI_Out__1__SLW CYREG_PRT4_SLW +#define SCSI_Out__2__AG CYREG_PRT0_AG +#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__2__BIE CYREG_PRT0_BIE +#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__2__BYP CYREG_PRT0_BYP +#define SCSI_Out__2__CTL CYREG_PRT0_CTL +#define SCSI_Out__2__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__2__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__2__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__2__DR CYREG_PRT0_DR +#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7 +#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__2__MASK 0x80u +#define SCSI_Out__2__PC CYREG_PRT0_PC7 +#define SCSI_Out__2__PORT 0u +#define SCSI_Out__2__PRT CYREG_PRT0_PRT +#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__2__PS CYREG_PRT0_PS +#define SCSI_Out__2__SHIFT 7u +#define SCSI_Out__2__SLW CYREG_PRT0_SLW +#define SCSI_Out__3__AG CYREG_PRT0_AG +#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__3__BIE CYREG_PRT0_BIE +#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__3__BYP CYREG_PRT0_BYP +#define SCSI_Out__3__CTL CYREG_PRT0_CTL +#define SCSI_Out__3__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__3__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__3__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__3__DR CYREG_PRT0_DR +#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE5 +#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__3__MASK 0x20u +#define SCSI_Out__3__PC CYREG_PRT0_PC5 +#define SCSI_Out__3__PORT 0u +#define SCSI_Out__3__PRT CYREG_PRT0_PRT +#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__3__PS CYREG_PRT0_PS +#define SCSI_Out__3__SHIFT 5u +#define SCSI_Out__3__SLW CYREG_PRT0_SLW +#define SCSI_Out__4__AG CYREG_PRT0_AG +#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__4__BIE CYREG_PRT0_BIE +#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__4__BYP CYREG_PRT0_BYP +#define SCSI_Out__4__CTL CYREG_PRT0_CTL +#define SCSI_Out__4__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__4__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__4__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__4__DR CYREG_PRT0_DR +#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE3 +#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__4__MASK 0x08u +#define SCSI_Out__4__PC CYREG_PRT0_PC3 +#define SCSI_Out__4__PORT 0u +#define SCSI_Out__4__PRT CYREG_PRT0_PRT +#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__4__PS CYREG_PRT0_PS +#define SCSI_Out__4__SHIFT 3u +#define SCSI_Out__4__SLW CYREG_PRT0_SLW +#define SCSI_Out__5__AG CYREG_PRT0_AG +#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__5__BIE CYREG_PRT0_BIE +#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__5__BYP CYREG_PRT0_BYP +#define SCSI_Out__5__CTL CYREG_PRT0_CTL +#define SCSI_Out__5__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__5__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__5__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__5__DR CYREG_PRT0_DR +#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE1 +#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__5__MASK 0x02u +#define SCSI_Out__5__PC CYREG_PRT0_PC1 +#define SCSI_Out__5__PORT 0u +#define SCSI_Out__5__PRT CYREG_PRT0_PRT +#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__5__PS CYREG_PRT0_PS +#define SCSI_Out__5__SHIFT 1u +#define SCSI_Out__5__SLW CYREG_PRT0_SLW +#define SCSI_Out__6__AG CYREG_PRT4_AG +#define SCSI_Out__6__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__6__BIE CYREG_PRT4_BIE +#define SCSI_Out__6__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__6__BYP CYREG_PRT4_BYP +#define SCSI_Out__6__CTL CYREG_PRT4_CTL +#define SCSI_Out__6__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__6__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__6__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__6__DR CYREG_PRT4_DR +#define SCSI_Out__6__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__6__INTTYPE CYREG_PICU4_INTTYPE1 +#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__6__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__6__MASK 0x02u +#define SCSI_Out__6__PC CYREG_PRT4_PC1 +#define SCSI_Out__6__PORT 4u +#define SCSI_Out__6__PRT CYREG_PRT4_PRT +#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__6__PS CYREG_PRT4_PS +#define SCSI_Out__6__SHIFT 1u +#define SCSI_Out__6__SLW CYREG_PRT4_SLW +#define SCSI_Out__7__AG CYREG_PRT4_AG +#define SCSI_Out__7__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__7__BIE CYREG_PRT4_BIE +#define SCSI_Out__7__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__7__BYP CYREG_PRT4_BYP +#define SCSI_Out__7__CTL CYREG_PRT4_CTL +#define SCSI_Out__7__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__7__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__7__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__7__DR CYREG_PRT4_DR +#define SCSI_Out__7__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__7__INTTYPE CYREG_PICU4_INTTYPE0 +#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__7__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__7__MASK 0x01u +#define SCSI_Out__7__PC CYREG_PRT4_PC0 +#define SCSI_Out__7__PORT 4u +#define SCSI_Out__7__PRT CYREG_PRT4_PRT +#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__7__PS CYREG_PRT4_PS +#define SCSI_Out__7__SHIFT 0u +#define SCSI_Out__7__SLW CYREG_PRT4_SLW +#define SCSI_Out__BSY__AG CYREG_PRT4_AG +#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE +#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP +#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL +#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__BSY__DR CYREG_PRT4_DR +#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__BSY__INTTYPE CYREG_PICU4_INTTYPE6 +#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__BSY__MASK 0x40u +#define SCSI_Out__BSY__PC CYREG_PRT4_PC6 +#define SCSI_Out__BSY__PORT 4u +#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT +#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__BSY__PS CYREG_PRT4_PS +#define SCSI_Out__BSY__SHIFT 6u +#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW +#define SCSI_Out__CD_raw__AG CYREG_PRT0_AG +#define SCSI_Out__CD_raw__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__CD_raw__BIE CYREG_PRT0_BIE +#define SCSI_Out__CD_raw__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__CD_raw__BYP CYREG_PRT0_BYP +#define SCSI_Out__CD_raw__CTL CYREG_PRT0_CTL +#define SCSI_Out__CD_raw__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__CD_raw__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__CD_raw__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__CD_raw__DR CYREG_PRT0_DR +#define SCSI_Out__CD_raw__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__CD_raw__INTTYPE CYREG_PICU0_INTTYPE1 +#define SCSI_Out__CD_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__CD_raw__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__CD_raw__MASK 0x02u +#define SCSI_Out__CD_raw__PC CYREG_PRT0_PC1 +#define SCSI_Out__CD_raw__PORT 0u +#define SCSI_Out__CD_raw__PRT CYREG_PRT0_PRT +#define SCSI_Out__CD_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__CD_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__CD_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__CD_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__CD_raw__PS CYREG_PRT0_PS +#define SCSI_Out__CD_raw__SHIFT 1u +#define SCSI_Out__CD_raw__SLW CYREG_PRT0_SLW +#define SCSI_Out__DBP_raw__AG CYREG_PRT6_AG +#define SCSI_Out__DBP_raw__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__DBP_raw__BIE CYREG_PRT6_BIE +#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__DBP_raw__BYP CYREG_PRT6_BYP +#define SCSI_Out__DBP_raw__CTL CYREG_PRT6_CTL +#define SCSI_Out__DBP_raw__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__DBP_raw__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__DBP_raw__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__DBP_raw__DR CYREG_PRT6_DR +#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__DBP_raw__MASK 0x04u +#define SCSI_Out__DBP_raw__PC CYREG_PRT6_PC2 +#define SCSI_Out__DBP_raw__PORT 6u +#define SCSI_Out__DBP_raw__PRT CYREG_PRT6_PRT +#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__DBP_raw__PS CYREG_PRT6_PS +#define SCSI_Out__DBP_raw__SHIFT 2u +#define SCSI_Out__DBP_raw__SLW CYREG_PRT6_SLW +#define SCSI_Out__IO_raw__AG CYREG_PRT4_AG +#define SCSI_Out__IO_raw__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__IO_raw__BIE CYREG_PRT4_BIE +#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__IO_raw__BYP CYREG_PRT4_BYP +#define SCSI_Out__IO_raw__CTL CYREG_PRT4_CTL +#define SCSI_Out__IO_raw__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__IO_raw__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__IO_raw__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__IO_raw__DR CYREG_PRT4_DR +#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU4_INTTYPE0 +#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__IO_raw__MASK 0x01u +#define SCSI_Out__IO_raw__PC CYREG_PRT4_PC0 +#define SCSI_Out__IO_raw__PORT 4u +#define SCSI_Out__IO_raw__PRT CYREG_PRT4_PRT +#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__IO_raw__PS CYREG_PRT4_PS +#define SCSI_Out__IO_raw__SHIFT 0u +#define SCSI_Out__IO_raw__SLW CYREG_PRT4_SLW +#define SCSI_Out__MSG_raw__AG CYREG_PRT0_AG +#define SCSI_Out__MSG_raw__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__MSG_raw__BIE CYREG_PRT0_BIE +#define SCSI_Out__MSG_raw__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__MSG_raw__BYP CYREG_PRT0_BYP +#define SCSI_Out__MSG_raw__CTL CYREG_PRT0_CTL +#define SCSI_Out__MSG_raw__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__MSG_raw__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__MSG_raw__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__MSG_raw__DR CYREG_PRT0_DR +#define SCSI_Out__MSG_raw__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__MSG_raw__INTTYPE CYREG_PICU0_INTTYPE5 +#define SCSI_Out__MSG_raw__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__MSG_raw__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__MSG_raw__MASK 0x20u +#define SCSI_Out__MSG_raw__PC CYREG_PRT0_PC5 +#define SCSI_Out__MSG_raw__PORT 0u +#define SCSI_Out__MSG_raw__PRT CYREG_PRT0_PRT +#define SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__MSG_raw__PS CYREG_PRT0_PS +#define SCSI_Out__MSG_raw__SHIFT 5u +#define SCSI_Out__MSG_raw__SLW CYREG_PRT0_SLW +#define SCSI_Out__REQ__AG CYREG_PRT4_AG +#define SCSI_Out__REQ__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__REQ__BIE CYREG_PRT4_BIE +#define SCSI_Out__REQ__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__REQ__BYP CYREG_PRT4_BYP +#define SCSI_Out__REQ__CTL CYREG_PRT4_CTL +#define SCSI_Out__REQ__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__REQ__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__REQ__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__REQ__DR CYREG_PRT4_DR +#define SCSI_Out__REQ__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__REQ__INTTYPE CYREG_PICU4_INTTYPE1 +#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__REQ__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__REQ__MASK 0x02u +#define SCSI_Out__REQ__PC CYREG_PRT4_PC1 +#define SCSI_Out__REQ__PORT 4u +#define SCSI_Out__REQ__PRT CYREG_PRT4_PRT +#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__REQ__PS CYREG_PRT4_PS +#define SCSI_Out__REQ__SHIFT 1u +#define SCSI_Out__REQ__SLW CYREG_PRT4_SLW +#define SCSI_Out__RST__AG CYREG_PRT0_AG +#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__RST__BIE CYREG_PRT0_BIE +#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__RST__BYP CYREG_PRT0_BYP +#define SCSI_Out__RST__CTL CYREG_PRT0_CTL +#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__RST__DR CYREG_PRT0_DR +#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE7 +#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__RST__MASK 0x80u +#define SCSI_Out__RST__PC CYREG_PRT0_PC7 +#define SCSI_Out__RST__PORT 0u +#define SCSI_Out__RST__PRT CYREG_PRT0_PRT +#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__RST__PS CYREG_PRT0_PS +#define SCSI_Out__RST__SHIFT 7u +#define SCSI_Out__RST__SLW CYREG_PRT0_SLW +#define SCSI_Out__SEL__AG CYREG_PRT0_AG +#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__SEL__DR CYREG_PRT0_DR +#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3 +#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__SEL__MASK 0x08u +#define SCSI_Out__SEL__PC CYREG_PRT0_PC3 +#define SCSI_Out__SEL__PORT 0u +#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__SEL__PS CYREG_PRT0_PS +#define SCSI_Out__SEL__SHIFT 3u +#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW +#define SCSI_Out_Bits_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 +#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 +#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u +#define SCSI_Out_Bits_Sync_ctrl_reg__3__POS 3 +#define SCSI_Out_Bits_Sync_ctrl_reg__4__MASK 0x10u +#define SCSI_Out_Bits_Sync_ctrl_reg__4__POS 4 +#define SCSI_Out_Bits_Sync_ctrl_reg__5__MASK 0x20u +#define SCSI_Out_Bits_Sync_ctrl_reg__5__POS 5 +#define SCSI_Out_Bits_Sync_ctrl_reg__6__MASK 0x40u +#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 +#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u +#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK +#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE7 +#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__0__MASK 0x80u +#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC7 +#define SCSI_Out_DBx__0__PORT 6u +#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__0__SHIFT 7u +#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__1__MASK 0x20u +#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__1__PORT 6u +#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__1__SHIFT 5u +#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__2__AG CYREG_PRT12_AG +#define SCSI_Out_DBx__2__BIE CYREG_PRT12_BIE +#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Out_DBx__2__BYP CYREG_PRT12_BYP +#define SCSI_Out_DBx__2__DM0 CYREG_PRT12_DM0 +#define SCSI_Out_DBx__2__DM1 CYREG_PRT12_DM1 +#define SCSI_Out_DBx__2__DM2 CYREG_PRT12_DM2 +#define SCSI_Out_DBx__2__DR CYREG_PRT12_DR +#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Out_DBx__2__MASK 0x20u +#define SCSI_Out_DBx__2__PC CYREG_PRT12_PC5 +#define SCSI_Out_DBx__2__PORT 12u +#define SCSI_Out_DBx__2__PRT CYREG_PRT12_PRT +#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Out_DBx__2__PS CYREG_PRT12_PS +#define SCSI_Out_DBx__2__SHIFT 5u +#define SCSI_Out_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Out_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Out_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Out_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Out_DBx__2__SLW CYREG_PRT12_SLW +#define SCSI_Out_DBx__3__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__3__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__3__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__3__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__3__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__3__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__3__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__3__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__3__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU2_INTTYPE7 +#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__3__MASK 0x80u +#define SCSI_Out_DBx__3__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__3__PORT 2u +#define SCSI_Out_DBx__3__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__3__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__3__SHIFT 7u +#define SCSI_Out_DBx__3__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE5 +#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__4__MASK 0x20u +#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC5 +#define SCSI_Out_DBx__4__PORT 2u +#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__4__SHIFT 5u +#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3 +#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__5__MASK 0x08u +#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__5__PORT 2u +#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__5__SHIFT 3u +#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE1 +#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__6__MASK 0x02u +#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC1 +#define SCSI_Out_DBx__6__PORT 2u +#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__6__SHIFT 1u +#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__7__AG CYREG_PRT15_AG +#define SCSI_Out_DBx__7__AMUX CYREG_PRT15_AMUX +#define SCSI_Out_DBx__7__BIE CYREG_PRT15_BIE +#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out_DBx__7__BYP CYREG_PRT15_BYP +#define SCSI_Out_DBx__7__CTL CYREG_PRT15_CTL +#define SCSI_Out_DBx__7__DM0 CYREG_PRT15_DM0 +#define SCSI_Out_DBx__7__DM1 CYREG_PRT15_DM1 +#define SCSI_Out_DBx__7__DM2 CYREG_PRT15_DM2 +#define SCSI_Out_DBx__7__DR CYREG_PRT15_DR +#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU15_INTTYPE5 +#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out_DBx__7__MASK 0x20u +#define SCSI_Out_DBx__7__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out_DBx__7__PORT 15u +#define SCSI_Out_DBx__7__PRT CYREG_PRT15_PRT +#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out_DBx__7__PS CYREG_PRT15_PS +#define SCSI_Out_DBx__7__SHIFT 5u +#define SCSI_Out_DBx__7__SLW CYREG_PRT15_SLW +#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE7 +#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB0__MASK 0x80u +#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC7 +#define SCSI_Out_DBx__DB0__PORT 6u +#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB0__SHIFT 7u +#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB1__MASK 0x20u +#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__DB1__PORT 6u +#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB1__SHIFT 5u +#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB2__AG CYREG_PRT12_AG +#define SCSI_Out_DBx__DB2__BIE CYREG_PRT12_BIE +#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Out_DBx__DB2__BYP CYREG_PRT12_BYP +#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT12_DM0 +#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT12_DM1 +#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT12_DM2 +#define SCSI_Out_DBx__DB2__DR CYREG_PRT12_DR +#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Out_DBx__DB2__MASK 0x20u +#define SCSI_Out_DBx__DB2__PC CYREG_PRT12_PC5 +#define SCSI_Out_DBx__DB2__PORT 12u +#define SCSI_Out_DBx__DB2__PRT CYREG_PRT12_PRT +#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Out_DBx__DB2__PS CYREG_PRT12_PS +#define SCSI_Out_DBx__DB2__SHIFT 5u +#define SCSI_Out_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Out_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Out_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Out_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Out_DBx__DB2__SLW CYREG_PRT12_SLW +#define SCSI_Out_DBx__DB3__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB3__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB3__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB3__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB3__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE7 +#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB3__MASK 0x80u +#define SCSI_Out_DBx__DB3__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__DB3__PORT 2u +#define SCSI_Out_DBx__DB3__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB3__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB3__SHIFT 7u +#define SCSI_Out_DBx__DB3__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE5 +#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB4__MASK 0x20u +#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC5 +#define SCSI_Out_DBx__DB4__PORT 2u +#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB4__SHIFT 5u +#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3 +#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB5__MASK 0x08u +#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__DB5__PORT 2u +#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB5__SHIFT 3u +#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE1 +#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB6__MASK 0x02u +#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC1 +#define SCSI_Out_DBx__DB6__PORT 2u +#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB6__SHIFT 1u +#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB7__AG CYREG_PRT15_AG +#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT15_AMUX +#define SCSI_Out_DBx__DB7__BIE CYREG_PRT15_BIE +#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out_DBx__DB7__BYP CYREG_PRT15_BYP +#define SCSI_Out_DBx__DB7__CTL CYREG_PRT15_CTL +#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT15_DM0 +#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT15_DM1 +#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT15_DM2 +#define SCSI_Out_DBx__DB7__DR CYREG_PRT15_DR +#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU15_INTTYPE5 +#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out_DBx__DB7__MASK 0x20u +#define SCSI_Out_DBx__DB7__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out_DBx__DB7__PORT 15u +#define SCSI_Out_DBx__DB7__PRT CYREG_PRT15_PRT +#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out_DBx__DB7__PS CYREG_PRT15_PS +#define SCSI_Out_DBx__DB7__SHIFT 5u +#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW + +/* SD_RX_DMA */ +#define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SD_RX_DMA__DRQ_NUMBER 2u +#define SD_RX_DMA__NUMBEROF_TDS 0u +#define SD_RX_DMA__PRIORITY 0u +#define SD_RX_DMA__TERMIN_EN 0u +#define SD_RX_DMA__TERMIN_SEL 0u +#define SD_RX_DMA__TERMOUT0_EN 1u +#define SD_RX_DMA__TERMOUT0_SEL 2u +#define SD_RX_DMA__TERMOUT1_EN 0u +#define SD_RX_DMA__TERMOUT1_SEL 0u +#define SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SD_RX_DMA_COMPLETE__INTC_MASK 0x20u +#define SD_RX_DMA_COMPLETE__INTC_NUMBER 5u +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SD_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_5 +#define SD_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SD_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA */ +#define SD_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SD_TX_DMA__DRQ_NUMBER 3u +#define SD_TX_DMA__NUMBEROF_TDS 0u +#define SD_TX_DMA__PRIORITY 1u +#define SD_TX_DMA__TERMIN_EN 0u +#define SD_TX_DMA__TERMIN_SEL 0u +#define SD_TX_DMA__TERMOUT0_EN 1u +#define SD_TX_DMA__TERMOUT0_SEL 3u +#define SD_TX_DMA__TERMOUT1_EN 0u +#define SD_TX_DMA__TERMOUT1_SEL 0u +#define SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SD_TX_DMA_COMPLETE__INTC_MASK 0x40u +#define SD_TX_DMA_COMPLETE__INTC_NUMBER 6u +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SD_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_6 +#define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Noise */ +#define SCSI_Noise__0__AG CYREG_PRT4_AG +#define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__0__BIE CYREG_PRT4_BIE +#define SCSI_Noise__0__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__0__BYP CYREG_PRT4_BYP +#define SCSI_Noise__0__CTL CYREG_PRT4_CTL +#define SCSI_Noise__0__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__0__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__0__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__0__DR CYREG_PRT4_DR +#define SCSI_Noise__0__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__0__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__0__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__0__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__0__MASK 0x80u +#define SCSI_Noise__0__PC CYREG_PRT4_PC7 +#define SCSI_Noise__0__PORT 4u +#define SCSI_Noise__0__PRT CYREG_PRT4_PRT +#define SCSI_Noise__0__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__0__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__0__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__0__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__0__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__0__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__0__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__0__PS CYREG_PRT4_PS +#define SCSI_Noise__0__SHIFT 7u +#define SCSI_Noise__0__SLW CYREG_PRT4_SLW +#define SCSI_Noise__1__AG CYREG_PRT4_AG +#define SCSI_Noise__1__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__1__BIE CYREG_PRT4_BIE +#define SCSI_Noise__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__1__BYP CYREG_PRT4_BYP +#define SCSI_Noise__1__CTL CYREG_PRT4_CTL +#define SCSI_Noise__1__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__1__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__1__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__1__DR CYREG_PRT4_DR +#define SCSI_Noise__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__1__INTTYPE CYREG_PICU4_INTTYPE5 +#define SCSI_Noise__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__1__MASK 0x20u +#define SCSI_Noise__1__PC CYREG_PRT4_PC5 +#define SCSI_Noise__1__PORT 4u +#define SCSI_Noise__1__PRT CYREG_PRT4_PRT +#define SCSI_Noise__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__1__PS CYREG_PRT4_PS +#define SCSI_Noise__1__SHIFT 5u +#define SCSI_Noise__1__SLW CYREG_PRT4_SLW +#define SCSI_Noise__2__AG CYREG_PRT0_AG +#define SCSI_Noise__2__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__2__BIE CYREG_PRT0_BIE +#define SCSI_Noise__2__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__2__BYP CYREG_PRT0_BYP +#define SCSI_Noise__2__CTL CYREG_PRT0_CTL +#define SCSI_Noise__2__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__2__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__2__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__2__DR CYREG_PRT0_DR +#define SCSI_Noise__2__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__2__INTTYPE CYREG_PICU0_INTTYPE2 +#define SCSI_Noise__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__2__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__2__MASK 0x04u +#define SCSI_Noise__2__PC CYREG_PRT0_PC2 +#define SCSI_Noise__2__PORT 0u +#define SCSI_Noise__2__PRT CYREG_PRT0_PRT +#define SCSI_Noise__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__2__PS CYREG_PRT0_PS +#define SCSI_Noise__2__SHIFT 2u +#define SCSI_Noise__2__SLW CYREG_PRT0_SLW +#define SCSI_Noise__3__AG CYREG_PRT0_AG +#define SCSI_Noise__3__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__3__BIE CYREG_PRT0_BIE +#define SCSI_Noise__3__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__3__BYP CYREG_PRT0_BYP +#define SCSI_Noise__3__CTL CYREG_PRT0_CTL +#define SCSI_Noise__3__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__3__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__3__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__3__DR CYREG_PRT0_DR +#define SCSI_Noise__3__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__3__INTTYPE CYREG_PICU0_INTTYPE6 +#define SCSI_Noise__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__3__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__3__MASK 0x40u +#define SCSI_Noise__3__PC CYREG_PRT0_PC6 +#define SCSI_Noise__3__PORT 0u +#define SCSI_Noise__3__PRT CYREG_PRT0_PRT +#define SCSI_Noise__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__3__PS CYREG_PRT0_PS +#define SCSI_Noise__3__SHIFT 6u +#define SCSI_Noise__3__SLW CYREG_PRT0_SLW +#define SCSI_Noise__4__AG CYREG_PRT4_AG +#define SCSI_Noise__4__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__4__BIE CYREG_PRT4_BIE +#define SCSI_Noise__4__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__4__BYP CYREG_PRT4_BYP +#define SCSI_Noise__4__CTL CYREG_PRT4_CTL +#define SCSI_Noise__4__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__4__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__4__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__4__DR CYREG_PRT4_DR +#define SCSI_Noise__4__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__4__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__4__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__4__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__4__MASK 0x08u +#define SCSI_Noise__4__PC CYREG_PRT4_PC3 +#define SCSI_Noise__4__PORT 4u +#define SCSI_Noise__4__PRT CYREG_PRT4_PRT +#define SCSI_Noise__4__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__4__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__4__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__4__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__4__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__4__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__4__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__4__PS CYREG_PRT4_PS +#define SCSI_Noise__4__SHIFT 3u +#define SCSI_Noise__4__SLW CYREG_PRT4_SLW +#define SCSI_Noise__ACK__AG CYREG_PRT4_AG +#define SCSI_Noise__ACK__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__ACK__BIE CYREG_PRT4_BIE +#define SCSI_Noise__ACK__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__ACK__BYP CYREG_PRT4_BYP +#define SCSI_Noise__ACK__CTL CYREG_PRT4_CTL +#define SCSI_Noise__ACK__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__ACK__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__ACK__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__ACK__DR CYREG_PRT4_DR +#define SCSI_Noise__ACK__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__ACK__INTTYPE CYREG_PICU4_INTTYPE3 +#define SCSI_Noise__ACK__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__ACK__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__ACK__MASK 0x08u +#define SCSI_Noise__ACK__PC CYREG_PRT4_PC3 +#define SCSI_Noise__ACK__PORT 4u +#define SCSI_Noise__ACK__PRT CYREG_PRT4_PRT +#define SCSI_Noise__ACK__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__ACK__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__ACK__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__ACK__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__ACK__PS CYREG_PRT4_PS +#define SCSI_Noise__ACK__SHIFT 3u +#define SCSI_Noise__ACK__SLW CYREG_PRT4_SLW +#define SCSI_Noise__ATN__AG CYREG_PRT4_AG +#define SCSI_Noise__ATN__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__ATN__BIE CYREG_PRT4_BIE +#define SCSI_Noise__ATN__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__ATN__BYP CYREG_PRT4_BYP +#define SCSI_Noise__ATN__CTL CYREG_PRT4_CTL +#define SCSI_Noise__ATN__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__ATN__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__ATN__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__ATN__DR CYREG_PRT4_DR +#define SCSI_Noise__ATN__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__ATN__INTTYPE CYREG_PICU4_INTTYPE7 +#define SCSI_Noise__ATN__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__ATN__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__ATN__MASK 0x80u +#define SCSI_Noise__ATN__PC CYREG_PRT4_PC7 +#define SCSI_Noise__ATN__PORT 4u +#define SCSI_Noise__ATN__PRT CYREG_PRT4_PRT +#define SCSI_Noise__ATN__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__ATN__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__ATN__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__ATN__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__ATN__PS CYREG_PRT4_PS +#define SCSI_Noise__ATN__SHIFT 7u +#define SCSI_Noise__ATN__SLW CYREG_PRT4_SLW +#define SCSI_Noise__BSY__AG CYREG_PRT4_AG +#define SCSI_Noise__BSY__AMUX CYREG_PRT4_AMUX +#define SCSI_Noise__BSY__BIE CYREG_PRT4_BIE +#define SCSI_Noise__BSY__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Noise__BSY__BYP CYREG_PRT4_BYP +#define SCSI_Noise__BSY__CTL CYREG_PRT4_CTL +#define SCSI_Noise__BSY__DM0 CYREG_PRT4_DM0 +#define SCSI_Noise__BSY__DM1 CYREG_PRT4_DM1 +#define SCSI_Noise__BSY__DM2 CYREG_PRT4_DM2 +#define SCSI_Noise__BSY__DR CYREG_PRT4_DR +#define SCSI_Noise__BSY__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Noise__BSY__INTTYPE CYREG_PICU4_INTTYPE5 +#define SCSI_Noise__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Noise__BSY__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Noise__BSY__MASK 0x20u +#define SCSI_Noise__BSY__PC CYREG_PRT4_PC5 +#define SCSI_Noise__BSY__PORT 4u +#define SCSI_Noise__BSY__PRT CYREG_PRT4_PRT +#define SCSI_Noise__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Noise__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Noise__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Noise__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Noise__BSY__PS CYREG_PRT4_PS +#define SCSI_Noise__BSY__SHIFT 5u +#define SCSI_Noise__BSY__SLW CYREG_PRT4_SLW +#define SCSI_Noise__RST__AG CYREG_PRT0_AG +#define SCSI_Noise__RST__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__RST__BIE CYREG_PRT0_BIE +#define SCSI_Noise__RST__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__RST__BYP CYREG_PRT0_BYP +#define SCSI_Noise__RST__CTL CYREG_PRT0_CTL +#define SCSI_Noise__RST__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__RST__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__RST__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__RST__DR CYREG_PRT0_DR +#define SCSI_Noise__RST__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__RST__INTTYPE CYREG_PICU0_INTTYPE6 +#define SCSI_Noise__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__RST__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__RST__MASK 0x40u +#define SCSI_Noise__RST__PC CYREG_PRT0_PC6 +#define SCSI_Noise__RST__PORT 0u +#define SCSI_Noise__RST__PRT CYREG_PRT0_PRT +#define SCSI_Noise__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__RST__PS CYREG_PRT0_PS +#define SCSI_Noise__RST__SHIFT 6u +#define SCSI_Noise__RST__SLW CYREG_PRT0_SLW +#define SCSI_Noise__SEL__AG CYREG_PRT0_AG +#define SCSI_Noise__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Noise__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Noise__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Noise__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Noise__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Noise__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Noise__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Noise__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Noise__SEL__DR CYREG_PRT0_DR +#define SCSI_Noise__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Noise__SEL__INTTYPE CYREG_PICU0_INTTYPE2 +#define SCSI_Noise__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Noise__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Noise__SEL__MASK 0x04u +#define SCSI_Noise__SEL__PC CYREG_PRT0_PC2 +#define SCSI_Noise__SEL__PORT 0u +#define SCSI_Noise__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Noise__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Noise__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Noise__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Noise__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Noise__SEL__PS CYREG_PRT0_PS +#define SCSI_Noise__SEL__SHIFT 2u +#define SCSI_Noise__SEL__SLW CYREG_PRT0_SLW + +/* scsiTarget */ +#define scsiTarget_datapath__16BIT_A0_REG CYREG_B0_UDB00_01_A0 +#define scsiTarget_datapath__16BIT_A1_REG CYREG_B0_UDB00_01_A1 +#define scsiTarget_datapath__16BIT_D0_REG CYREG_B0_UDB00_01_D0 +#define scsiTarget_datapath__16BIT_D1_REG CYREG_B0_UDB00_01_D1 +#define scsiTarget_datapath__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath__16BIT_F0_REG CYREG_B0_UDB00_01_F0 +#define scsiTarget_datapath__16BIT_F1_REG CYREG_B0_UDB00_01_F1 +#define scsiTarget_datapath__A0_A1_REG CYREG_B0_UDB00_A0_A1 +#define scsiTarget_datapath__A0_REG CYREG_B0_UDB00_A0 +#define scsiTarget_datapath__A1_REG CYREG_B0_UDB00_A1 +#define scsiTarget_datapath__D0_D1_REG CYREG_B0_UDB00_D0_D1 +#define scsiTarget_datapath__D0_REG CYREG_B0_UDB00_D0 +#define scsiTarget_datapath__D1_REG CYREG_B0_UDB00_D1 +#define scsiTarget_datapath__DP_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath__F0_F1_REG CYREG_B0_UDB00_F0_F1 +#define scsiTarget_datapath__F0_REG CYREG_B0_UDB00_F0 +#define scsiTarget_datapath__F1_REG CYREG_B0_UDB00_F1 +#define scsiTarget_datapath__MSK_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath__PER_DP_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PI__16BIT_STATUS_REG CYREG_B0_UDB00_01_ST +#define scsiTarget_datapath_PI__MASK_REG CYREG_B0_UDB00_MSK +#define scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PI__STATUS_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PI__STATUS_CNT_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_CONTROL_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PI__STATUS_REG CYREG_B0_UDB00_ST +#define scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB00_01_ACTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG CYREG_B0_UDB00_01_CTL +#define scsiTarget_datapath_PO__16BIT_MASK_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB00_01_MSK +#define scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG CYREG_B0_UDB00_ACTL +#define scsiTarget_datapath_PO__CONTROL_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__CONTROL_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__COUNT_REG CYREG_B0_UDB00_CTL +#define scsiTarget_datapath_PO__COUNT_ST_REG CYREG_B0_UDB00_ST_CTL +#define scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG CYREG_B0_UDB00_MSK_ACTL +#define scsiTarget_datapath_PO__PERIOD_REG CYREG_B0_UDB00_MSK +#define scsiTarget_StatusReg__0__MASK 0x01u +#define scsiTarget_StatusReg__0__POS 0 +#define scsiTarget_StatusReg__1__MASK 0x02u +#define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__2__MASK 0x04u +#define scsiTarget_StatusReg__2__POS 2 +#define scsiTarget_StatusReg__3__MASK 0x08u +#define scsiTarget_StatusReg__3__POS 3 +#define scsiTarget_StatusReg__4__MASK 0x10u +#define scsiTarget_StatusReg__4__POS 4 +#define scsiTarget_StatusReg__MASK 0x1Fu +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST + +/* Debug_Timer */ +#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define Debug_Timer_Interrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define Debug_Timer_Interrupt__INTC_MASK 0x01u +#define Debug_Timer_Interrupt__INTC_NUMBER 0u +#define Debug_Timer_Interrupt__INTC_PRIOR_NUM 7u +#define Debug_Timer_Interrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define Debug_Timer_Interrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define Debug_Timer_Interrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define Debug_Timer_TimerHW__CAP0 CYREG_TMR0_CAP0 +#define Debug_Timer_TimerHW__CAP1 CYREG_TMR0_CAP1 +#define Debug_Timer_TimerHW__CFG0 CYREG_TMR0_CFG0 +#define Debug_Timer_TimerHW__CFG1 CYREG_TMR0_CFG1 +#define Debug_Timer_TimerHW__CFG2 CYREG_TMR0_CFG2 +#define Debug_Timer_TimerHW__CNT_CMP0 CYREG_TMR0_CNT_CMP0 +#define Debug_Timer_TimerHW__CNT_CMP1 CYREG_TMR0_CNT_CMP1 +#define Debug_Timer_TimerHW__PER0 CYREG_TMR0_PER0 +#define Debug_Timer_TimerHW__PER1 CYREG_TMR0_PER1 +#define Debug_Timer_TimerHW__PM_ACT_CFG CYREG_PM_ACT_CFG3 +#define Debug_Timer_TimerHW__PM_ACT_MSK 0x01u +#define Debug_Timer_TimerHW__PM_STBY_CFG CYREG_PM_STBY_CFG3 +#define Debug_Timer_TimerHW__PM_STBY_MSK 0x01u +#define Debug_Timer_TimerHW__RT0 CYREG_TMR0_RT0 +#define Debug_Timer_TimerHW__RT1 CYREG_TMR0_RT1 +#define Debug_Timer_TimerHW__SR0 CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +#define SCSI_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_RX_DMA__DRQ_NUMBER 0u +#define SCSI_RX_DMA__NUMBEROF_TDS 0u +#define SCSI_RX_DMA__PRIORITY 2u +#define SCSI_RX_DMA__TERMIN_EN 0u +#define SCSI_RX_DMA__TERMIN_SEL 0u +#define SCSI_RX_DMA__TERMOUT0_EN 1u +#define SCSI_RX_DMA__TERMOUT0_SEL 0u +#define SCSI_RX_DMA__TERMOUT1_EN 0u +#define SCSI_RX_DMA__TERMOUT1_SEL 0u +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RX_DMA_COMPLETE__INTC_MASK 0x04u +#define SCSI_RX_DMA_COMPLETE__INTC_NUMBER 2u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_2 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +#define SCSI_TX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 +#define SCSI_TX_DMA__DRQ_NUMBER 1u +#define SCSI_TX_DMA__NUMBEROF_TDS 0u +#define SCSI_TX_DMA__PRIORITY 2u +#define SCSI_TX_DMA__TERMIN_EN 0u +#define SCSI_TX_DMA__TERMIN_SEL 0u +#define SCSI_TX_DMA__TERMOUT0_EN 1u +#define SCSI_TX_DMA__TERMOUT0_SEL 1u +#define SCSI_TX_DMA__TERMOUT1_EN 0u +#define SCSI_TX_DMA__TERMOUT1_SEL 0u +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_TX_DMA_COMPLETE__INTC_MASK 0x10u +#define SCSI_TX_DMA_COMPLETE__INTC_NUMBER 4u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM 7u +#define SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG CYREG_NVIC_PRI_4 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u +#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define SD_Data_Clk__PM_STBY_MSK 0x01u + +/* SPI_Pullups */ +#define SPI_Pullups__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SPI_Pullups__0__MASK 0x10u +#define SPI_Pullups__0__PC CYREG_PRT3_PC4 +#define SPI_Pullups__0__PORT 3u +#define SPI_Pullups__0__SHIFT 4u +#define SPI_Pullups__1__INTTYPE CYREG_PICU3_INTTYPE5 +#define SPI_Pullups__1__MASK 0x20u +#define SPI_Pullups__1__PC CYREG_PRT3_PC5 +#define SPI_Pullups__1__PORT 3u +#define SPI_Pullups__1__SHIFT 5u +#define SPI_Pullups__2__INTTYPE CYREG_PICU3_INTTYPE6 +#define SPI_Pullups__2__MASK 0x40u +#define SPI_Pullups__2__PC CYREG_PRT3_PC6 +#define SPI_Pullups__2__PORT 3u +#define SPI_Pullups__2__SHIFT 6u +#define SPI_Pullups__3__INTTYPE CYREG_PICU3_INTTYPE7 +#define SPI_Pullups__3__MASK 0x80u +#define SPI_Pullups__3__PC CYREG_PRT3_PC7 +#define SPI_Pullups__3__PORT 3u +#define SPI_Pullups__3__SHIFT 7u +#define SPI_Pullups__AG CYREG_PRT3_AG +#define SPI_Pullups__AMUX CYREG_PRT3_AMUX +#define SPI_Pullups__BIE CYREG_PRT3_BIE +#define SPI_Pullups__BIT_MASK CYREG_PRT3_BIT_MASK +#define SPI_Pullups__BYP CYREG_PRT3_BYP +#define SPI_Pullups__CTL CYREG_PRT3_CTL +#define SPI_Pullups__DM0 CYREG_PRT3_DM0 +#define SPI_Pullups__DM1 CYREG_PRT3_DM1 +#define SPI_Pullups__DM2 CYREG_PRT3_DM2 +#define SPI_Pullups__DR CYREG_PRT3_DR +#define SPI_Pullups__INP_DIS CYREG_PRT3_INP_DIS +#define SPI_Pullups__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SPI_Pullups__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SPI_Pullups__LCD_EN CYREG_PRT3_LCD_EN +#define SPI_Pullups__MASK 0xF0u +#define SPI_Pullups__PORT 3u +#define SPI_Pullups__PRT CYREG_PRT3_PRT +#define SPI_Pullups__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SPI_Pullups__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SPI_Pullups__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SPI_Pullups__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SPI_Pullups__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SPI_Pullups__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SPI_Pullups__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SPI_Pullups__PS CYREG_PRT3_PS +#define SPI_Pullups__SHIFT 4u +#define SPI_Pullups__SLW CYREG_PRT3_SLW +#define SPI_Pullups_1__0__INTTYPE CYREG_PICU12_INTTYPE0 +#define SPI_Pullups_1__0__MASK 0x01u +#define SPI_Pullups_1__0__PC CYREG_PRT12_PC0 +#define SPI_Pullups_1__0__PORT 12u +#define SPI_Pullups_1__0__SHIFT 0u +#define SPI_Pullups_1__1__INTTYPE CYREG_PICU12_INTTYPE1 +#define SPI_Pullups_1__1__MASK 0x02u +#define SPI_Pullups_1__1__PC CYREG_PRT12_PC1 +#define SPI_Pullups_1__1__PORT 12u +#define SPI_Pullups_1__1__SHIFT 1u +#define SPI_Pullups_1__AG CYREG_PRT12_AG +#define SPI_Pullups_1__BIE CYREG_PRT12_BIE +#define SPI_Pullups_1__BIT_MASK CYREG_PRT12_BIT_MASK +#define SPI_Pullups_1__BYP CYREG_PRT12_BYP +#define SPI_Pullups_1__DM0 CYREG_PRT12_DM0 +#define SPI_Pullups_1__DM1 CYREG_PRT12_DM1 +#define SPI_Pullups_1__DM2 CYREG_PRT12_DM2 +#define SPI_Pullups_1__DR CYREG_PRT12_DR +#define SPI_Pullups_1__INP_DIS CYREG_PRT12_INP_DIS +#define SPI_Pullups_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SPI_Pullups_1__MASK 0x03u +#define SPI_Pullups_1__PORT 12u +#define SPI_Pullups_1__PRT CYREG_PRT12_PRT +#define SPI_Pullups_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SPI_Pullups_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SPI_Pullups_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SPI_Pullups_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SPI_Pullups_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SPI_Pullups_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SPI_Pullups_1__PS CYREG_PRT12_PS +#define SPI_Pullups_1__SHIFT 0u +#define SPI_Pullups_1__SIO_CFG CYREG_PRT12_SIO_CFG +#define SPI_Pullups_1__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SPI_Pullups_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SPI_Pullups_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SPI_Pullups_1__SLW CYREG_PRT12_SLW + +/* timer_clock */ +#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 +#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 +#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2 +#define timer_clock__CFG2_SRC_SEL_MASK 0x07u +#define timer_clock__INDEX 0x02u +#define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define timer_clock__PM_ACT_MSK 0x04u +#define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define timer_clock__PM_STBY_MSK 0x04u + +/* SCSI_RST_ISR */ +#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_RST_ISR__INTC_MASK 0x02u +#define SCSI_RST_ISR__INTC_NUMBER 1u +#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u +#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +#define SCSI_SEL_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define SCSI_SEL_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define SCSI_SEL_ISR__INTC_MASK 0x08u +#define SCSI_SEL_ISR__INTC_NUMBER 3u +#define SCSI_SEL_ISR__INTC_PRIOR_NUM 7u +#define SCSI_SEL_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_3 +#define SCSI_SEL_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define SCSI_SEL_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +#define SCSI_Filtered_sts_sts_reg__0__MASK 0x01u +#define SCSI_Filtered_sts_sts_reg__0__POS 0 +#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u +#define SCSI_Filtered_sts_sts_reg__1__POS 1 +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u +#define SCSI_Filtered_sts_sts_reg__2__POS 2 +#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u +#define SCSI_Filtered_sts_sts_reg__3__POS 3 +#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u +#define SCSI_Filtered_sts_sts_reg__4__POS 4 +#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST + +/* SCSI_CTL_PHASE */ +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK + +/* SCSI_Glitch_Ctl */ +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__0__POS 0 +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST + +/* Miscellaneous */ +#define BCLK__BUS_CLK__HZ 50000000U +#define BCLK__BUS_CLK__KHZ 50000U +#define BCLK__BUS_CLK__MHZ 50U +#define CY_PROJECT_NAME "SCSI2SD" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E133069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 0 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x0400 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x0000007Fu +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 2 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x1000 +#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 3.3 +#define CYDEV_VDDIO3_MV 3300 +#define CYDEV_VIO0 5 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 3.3 +#define CYDEV_VIO3_MV 3300 +#define CYIPBLOCK_ARM_CM3_VERSION 0 +#define CYIPBLOCK_P3_ANAIF_VERSION 0 +#define CYIPBLOCK_P3_CAPSENSE_VERSION 0 +#define CYIPBLOCK_P3_COMP_VERSION 0 +#define CYIPBLOCK_P3_DMA_VERSION 0 +#define CYIPBLOCK_P3_DRQ_VERSION 0 +#define CYIPBLOCK_P3_EMIF_VERSION 0 +#define CYIPBLOCK_P3_I2C_VERSION 0 +#define CYIPBLOCK_P3_LCD_VERSION 0 +#define CYIPBLOCK_P3_LPF_VERSION 0 +#define CYIPBLOCK_P3_PM_VERSION 0 +#define CYIPBLOCK_P3_TIMER_VERSION 0 +#define CYIPBLOCK_P3_USB_VERSION 0 +#define CYIPBLOCK_P3_VIDAC_VERSION 0 +#define CYIPBLOCK_P3_VREF_VERSION 0 +#define CYIPBLOCK_S8_GPIO_VERSION 0 +#define CYIPBLOCK_S8_IRQ_VERSION 0 +#define CYIPBLOCK_S8_SAR_VERSION 0 +#define CYIPBLOCK_S8_SIO_VERSION 0 +#define CYIPBLOCK_S8_UDB_VERSION 0 +#define DMA_CHANNELS_USED__MASK0 0x0000000Fu +#define CYDEV_BOOTLOADER_ENABLE 0 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c new file mode 100644 index 0000000..d04b6a7 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -0,0 +1,2146 @@ + +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* PSoC Creator 4.2 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" +#include "cyfitter_cfg.h" + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* `#START CyClockStartupError` */ + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + + /* `#END` */ + + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + +#define CY_CFG_BASE_ADDR_COUNT 39u +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + uint32 timeout; + uint8 pllLock; + + + /* Configure Digital Clocks based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0B19u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) + { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + /* If we ran out of time the PLL didn't lock so go to the error function */ + if (timeout == 0u) + { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + + /* Configure USB Clock based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); + + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u))); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x00u; + } + else + { + regValue &= (uint8)~0x00u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + + + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ + /* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { + 0x44u, 0xAAu, 0xAAu, 0x00u, 0x22u, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_7_VAL[] = { + 0x05u, 0x00u, 0x13u, 0x20u, 0x2Cu, 0x0Cu, 0x20u, 0x00u, 0x00u, 0x0Cu}; + + /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */ + static const uint8 CYCODE BS_IOPINS1_7_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x10u}; + + /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { + 0x40u, 0x00u, 0x00u, 0x28u, 0x28u, 0x08u, 0x20u, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_1_VAL[] = { + 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { + 0x55u, 0xAAu, 0xAAu, 0x00u, 0xAAu, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x18u, 0x00u, 0xF1u, 0x0Eu, 0x0Eu, 0x02u, 0x06u, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { + 0xA8u, 0x43u, 0x43u, 0x00u, 0x03u, 0x00u, 0x00u, 0x01u}; + + /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { + 0x5Au, 0xA4u, 0xA4u, 0x00u, 0xA4u, 0x00u, 0x00u, 0x01u}; + + /* PHUB_CFGMEM1 Address: CYREG_PHUB_CFGMEM1_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM1_VAL[] = { + 0x00u, 0x01u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM2 Address: CYREG_PHUB_CFGMEM2_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM2_VAL[] = { + 0x00u, 0x02u, 0x00u, 0x00u}; + + /* PHUB_CFGMEM3 Address: CYREG_PHUB_CFGMEM3_CFG0 Size (bytes): 4 */ + static const uint8 CYCODE BS_PHUB_CFGMEM3_VAL[] = { + 0x00u, 0x03u, 0x00u, 0x00u}; + +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Set Flash Cycles based on newly configured 50.00MHz Bus Clock. */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0xC1u : 0xC0u)); + /* Enable/Disable Debug functionality based on settings from System DWR */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); + + { + static const uint32 CYCODE cy_cfg_addr_table[] = { + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ + 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ + 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ + 0x40006401u, /* Base address: 0x40006400 Count: 1 */ + 0x40006501u, /* Base address: 0x40006500 Count: 1 */ + 0x40010042u, /* Base address: 0x40010000 Count: 66 */ + 0x4001013Eu, /* Base address: 0x40010100 Count: 62 */ + 0x4001025Fu, /* Base address: 0x40010200 Count: 95 */ + 0x40010356u, /* Base address: 0x40010300 Count: 86 */ + 0x40010450u, /* Base address: 0x40010400 Count: 80 */ + 0x40010557u, /* Base address: 0x40010500 Count: 87 */ + 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ + 0x40010756u, /* Base address: 0x40010700 Count: 86 */ + 0x40010915u, /* Base address: 0x40010900 Count: 21 */ + 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */ + 0x40010B52u, /* Base address: 0x40010B00 Count: 82 */ + 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */ + 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */ + 0x40010E4Bu, /* Base address: 0x40010E00 Count: 75 */ + 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */ + 0x40011416u, /* Base address: 0x40011400 Count: 22 */ + 0x4001154Eu, /* Base address: 0x40011500 Count: 78 */ + 0x40011653u, /* Base address: 0x40011600 Count: 83 */ + 0x40011744u, /* Base address: 0x40011700 Count: 68 */ + 0x40011908u, /* Base address: 0x40011900 Count: 8 */ + 0x40011B08u, /* Base address: 0x40011B00 Count: 8 */ + 0x4001401Fu, /* Base address: 0x40014000 Count: 31 */ + 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ + 0x40014211u, /* Base address: 0x40014200 Count: 17 */ + 0x40014310u, /* Base address: 0x40014300 Count: 16 */ + 0x40014411u, /* Base address: 0x40014400 Count: 17 */ + 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */ + 0x40014613u, /* Base address: 0x40014600 Count: 19 */ + 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ + 0x40014807u, /* Base address: 0x40014800 Count: 7 */ + 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */ + 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ + 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40015104u, /* Base address: 0x40015100 Count: 4 */ + }; + + static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + {0x7Eu, 0x02u}, + {0x01u, 0x20u}, + {0x0Au, 0x27u}, + {0x01u, 0x22u}, + {0x10u, 0xAAu}, + {0x11u, 0x88u}, + {0x18u, 0x02u}, + {0x19u, 0x08u}, + {0x1Cu, 0x08u}, + {0x20u, 0x02u}, + {0x21u, 0x02u}, + {0x30u, 0x80u}, + {0x31u, 0x04u}, + {0x78u, 0x20u}, + {0x7Cu, 0x40u}, + {0x20u, 0x01u}, + {0x84u, 0x0Fu}, + {0x04u, 0xE0u}, + {0x05u, 0xFFu}, + {0x08u, 0x11u}, + {0x0Au, 0xECu}, + {0x0Bu, 0xFFu}, + {0x0Cu, 0x40u}, + {0x0Du, 0x69u}, + {0x0Eu, 0x80u}, + {0x0Fu, 0x96u}, + {0x10u, 0x0Bu}, + {0x11u, 0x0Fu}, + {0x12u, 0xF4u}, + {0x13u, 0xF0u}, + {0x16u, 0xFFu}, + {0x17u, 0xFFu}, + {0x18u, 0xCAu}, + {0x19u, 0x33u}, + {0x1Au, 0x15u}, + {0x1Bu, 0xCCu}, + {0x1Eu, 0x10u}, + {0x20u, 0x06u}, + {0x25u, 0xFFu}, + {0x28u, 0x40u}, + {0x29u, 0x55u}, + {0x2Au, 0x80u}, + {0x2Bu, 0xAAu}, + {0x2Cu, 0x01u}, + {0x2Fu, 0xFFu}, + {0x30u, 0xC0u}, + {0x31u, 0xFFu}, + {0x34u, 0x3Fu}, + {0x3Au, 0x02u}, + {0x3Bu, 0x02u}, + {0x40u, 0x52u}, + {0x41u, 0x04u}, + {0x42u, 0x30u}, + {0x45u, 0xC2u}, + {0x46u, 0xFDu}, + {0x47u, 0x0Eu}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Fu, 0x2Cu}, + {0x56u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x01u}, + {0x5Fu, 0x01u}, + {0x60u, 0x08u}, + {0x62u, 0xC8u}, + {0x66u, 0x80u}, + {0x68u, 0x40u}, + {0x69u, 0x40u}, + {0x6Eu, 0x08u}, + {0x9Du, 0x01u}, + {0xB1u, 0x01u}, + {0xBFu, 0x01u}, + {0xD6u, 0x08u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x20u}, + {0x03u, 0x26u}, + {0x09u, 0x80u}, + {0x0Au, 0x44u}, + {0x0Bu, 0x20u}, + {0x10u, 0x81u}, + {0x12u, 0x04u}, + {0x19u, 0x20u}, + {0x1Au, 0x84u}, + {0x1Bu, 0x02u}, + {0x20u, 0x40u}, + {0x21u, 0x02u}, + {0x24u, 0x80u}, + {0x2Au, 0xA0u}, + {0x2Bu, 0x20u}, + {0x30u, 0x10u}, + {0x31u, 0x02u}, + {0x33u, 0x04u}, + {0x35u, 0x40u}, + {0x3Au, 0x48u}, + {0x3Bu, 0x20u}, + {0x41u, 0x08u}, + {0x42u, 0xCCu}, + {0x48u, 0x80u}, + {0x4Au, 0x10u}, + {0x4Bu, 0x80u}, + {0x50u, 0x20u}, + {0x51u, 0xC0u}, + {0x52u, 0x08u}, + {0x59u, 0x10u}, + {0x5Au, 0x88u}, + {0x5Bu, 0x01u}, + {0x5Cu, 0x80u}, + {0x5Fu, 0x28u}, + {0x61u, 0x24u}, + {0x63u, 0x82u}, + {0x64u, 0x12u}, + {0x66u, 0x24u}, + {0x69u, 0x51u}, + {0x6Bu, 0x10u}, + {0x70u, 0x18u}, + {0x73u, 0x42u}, + {0x80u, 0x20u}, + {0x81u, 0x80u}, + {0x82u, 0x40u}, + {0x84u, 0x80u}, + {0x87u, 0x40u}, + {0x8Bu, 0x22u}, + {0x8Cu, 0xC0u}, + {0xC0u, 0x07u}, + {0xC2u, 0x0Fu}, + {0xC4u, 0x0Bu}, + {0xCAu, 0x0Eu}, + {0xCCu, 0x17u}, + {0xCEu, 0x0Eu}, + {0xD0u, 0x07u}, + {0xD2u, 0x08u}, + {0xD6u, 0x7Fu}, + {0xD8u, 0x7Fu}, + {0xE0u, 0x1Du}, + {0xE4u, 0x03u}, + {0xE6u, 0x10u}, + {0x00u, 0x88u}, + {0x01u, 0x04u}, + {0x02u, 0x77u}, + {0x03u, 0x08u}, + {0x04u, 0x34u}, + {0x05u, 0x40u}, + {0x06u, 0x40u}, + {0x08u, 0x10u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x3Fu}, + {0x0Cu, 0x03u}, + {0x0Du, 0x01u}, + {0x0Eu, 0x0Cu}, + {0x0Fu, 0x02u}, + {0x10u, 0x8Bu}, + {0x11u, 0x01u}, + {0x12u, 0x74u}, + {0x13u, 0x02u}, + {0x14u, 0x40u}, + {0x15u, 0x10u}, + {0x16u, 0x80u}, + {0x17u, 0x20u}, + {0x18u, 0x3Du}, + {0x19u, 0x10u}, + {0x1Au, 0x42u}, + {0x1Bu, 0x20u}, + {0x1Cu, 0x02u}, + {0x1Du, 0x3Fu}, + {0x23u, 0x3Fu}, + {0x24u, 0x10u}, + {0x26u, 0x20u}, + {0x27u, 0x3Fu}, + {0x29u, 0x3Fu}, + {0x2Au, 0x77u}, + {0x2Du, 0x04u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x08u}, + {0x31u, 0x0Cu}, + {0x32u, 0xC0u}, + {0x33u, 0x40u}, + {0x34u, 0x30u}, + {0x35u, 0x30u}, + {0x36u, 0x0Fu}, + {0x37u, 0x03u}, + {0x3Au, 0xA8u}, + {0x3Bu, 0xA2u}, + {0x3Fu, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x11u}, + {0x5Fu, 0x01u}, + {0x80u, 0x50u}, + {0x82u, 0x8Cu}, + {0x84u, 0x0Cu}, + {0x86u, 0x80u}, + {0x87u, 0x18u}, + {0x88u, 0x04u}, + {0x8Au, 0x08u}, + {0x8Bu, 0x20u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x24u}, + {0x92u, 0x02u}, + {0x94u, 0x20u}, + {0x96u, 0x0Cu}, + {0x97u, 0x04u}, + {0x98u, 0x4Cu}, + {0x9Au, 0x80u}, + {0x9Fu, 0x03u}, + {0xA0u, 0x01u}, + {0xA1u, 0x24u}, + {0xA2u, 0x02u}, + {0xA3u, 0x09u}, + {0xA4u, 0x10u}, + {0xA6u, 0x8Cu}, + {0xA8u, 0x04u}, + {0xA9u, 0x24u}, + {0xAAu, 0x08u}, + {0xABu, 0x12u}, + {0xAEu, 0x10u}, + {0xB0u, 0xF0u}, + {0xB2u, 0x0Cu}, + {0xB3u, 0x38u}, + {0xB4u, 0x03u}, + {0xB6u, 0x03u}, + {0xB7u, 0x07u}, + {0xB8u, 0x02u}, + {0xBAu, 0x08u}, + {0xBEu, 0x50u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x01u, 0x02u}, + {0x02u, 0x01u}, + {0x03u, 0x28u}, + {0x04u, 0x08u}, + {0x05u, 0x52u}, + {0x08u, 0x0Au}, + {0x0Au, 0x04u}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x48u}, + {0x0Eu, 0x04u}, + {0x10u, 0x05u}, + {0x13u, 0x0Au}, + {0x14u, 0x08u}, + {0x16u, 0x22u}, + {0x18u, 0x08u}, + {0x19u, 0x86u}, + {0x1Au, 0x40u}, + {0x1Bu, 0x28u}, + {0x1Du, 0x58u}, + {0x21u, 0x84u}, + {0x25u, 0x20u}, + {0x26u, 0x26u}, + {0x27u, 0x01u}, + {0x29u, 0x22u}, + {0x2Du, 0x22u}, + {0x2Fu, 0x11u}, + {0x30u, 0x08u}, + {0x31u, 0x80u}, + {0x35u, 0x80u}, + {0x36u, 0x28u}, + {0x37u, 0x01u}, + {0x38u, 0x20u}, + {0x39u, 0x08u}, + {0x3Bu, 0x80u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x08u}, + {0x3Eu, 0x80u}, + {0x3Fu, 0x02u}, + {0x58u, 0x40u}, + {0x62u, 0x40u}, + {0x6Bu, 0x02u}, + {0x7Au, 0x02u}, + {0x7Bu, 0x01u}, + {0x81u, 0x04u}, + {0x84u, 0x12u}, + {0x86u, 0x12u}, + {0x87u, 0x48u}, + {0x89u, 0x80u}, + {0x90u, 0x20u}, + {0x91u, 0xD1u}, + {0x92u, 0x04u}, + {0x96u, 0x48u}, + {0x97u, 0xA0u}, + {0x98u, 0x43u}, + {0x99u, 0x20u}, + {0x9Au, 0x31u}, + {0x9Bu, 0x10u}, + {0x9Du, 0x54u}, + {0x9Eu, 0x40u}, + {0x9Fu, 0x01u}, + {0xA0u, 0x08u}, + {0xA2u, 0x10u}, + {0xA3u, 0x04u}, + {0xA4u, 0x10u}, + {0xA5u, 0x28u}, + {0xA7u, 0x61u}, + {0xAAu, 0x01u}, + {0xABu, 0x04u}, + {0xAFu, 0x08u}, + {0xB0u, 0x43u}, + {0xB2u, 0x18u}, + {0xB4u, 0x40u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xFEu}, + {0xC4u, 0xEFu}, + {0xCAu, 0xF5u}, + {0xCCu, 0xFAu}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x08u}, + {0xE2u, 0x8Cu}, + {0xE4u, 0x08u}, + {0xE8u, 0x02u}, + {0xEAu, 0x0Du}, + {0xEEu, 0x84u}, + {0x00u, 0x04u}, + {0x02u, 0x79u}, + {0x04u, 0x78u}, + {0x05u, 0x44u}, + {0x07u, 0x88u}, + {0x0Bu, 0xFFu}, + {0x0Eu, 0x03u}, + {0x10u, 0x20u}, + {0x11u, 0x33u}, + {0x12u, 0x40u}, + {0x13u, 0xCCu}, + {0x15u, 0x21u}, + {0x16u, 0x78u}, + {0x17u, 0x12u}, + {0x18u, 0x7Cu}, + {0x1Au, 0x02u}, + {0x1Cu, 0x20u}, + {0x1Du, 0x0Fu}, + {0x1Eu, 0x40u}, + {0x1Fu, 0xF0u}, + {0x20u, 0x08u}, + {0x21u, 0x84u}, + {0x22u, 0x10u}, + {0x23u, 0x48u}, + {0x25u, 0xFFu}, + {0x26u, 0x7Cu}, + {0x28u, 0x08u}, + {0x2Au, 0x10u}, + {0x2Bu, 0xFFu}, + {0x2Du, 0x11u}, + {0x2Eu, 0x04u}, + {0x2Fu, 0x22u}, + {0x30u, 0x07u}, + {0x31u, 0xFFu}, + {0x34u, 0x18u}, + {0x36u, 0x60u}, + {0x3Au, 0xA0u}, + {0x3Fu, 0x01u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x80u, 0x10u}, + {0x82u, 0x08u}, + {0x83u, 0x40u}, + {0x85u, 0x48u}, + {0x87u, 0x24u}, + {0x88u, 0x10u}, + {0x8Au, 0x0Au}, + {0x8Bu, 0x08u}, + {0x93u, 0x30u}, + {0x94u, 0x10u}, + {0x96u, 0x09u}, + {0x97u, 0x48u}, + {0x98u, 0x10u}, + {0x9Au, 0x0Cu}, + {0x9Bu, 0x06u}, + {0x9Cu, 0x08u}, + {0x9Eu, 0x10u}, + {0xABu, 0x01u}, + {0xADu, 0x48u}, + {0xAFu, 0x12u}, + {0xB0u, 0x02u}, + {0xB2u, 0x04u}, + {0xB3u, 0x0Eu}, + {0xB4u, 0x01u}, + {0xB5u, 0x01u}, + {0xB6u, 0x18u}, + {0xB7u, 0x70u}, + {0xBAu, 0x80u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x40u}, + {0x01u, 0x02u}, + {0x03u, 0x20u}, + {0x05u, 0x11u}, + {0x08u, 0x02u}, + {0x0Au, 0x06u}, + {0x0Bu, 0x20u}, + {0x0Eu, 0x22u}, + {0x0Fu, 0x04u}, + {0x10u, 0x08u}, + {0x11u, 0x40u}, + {0x12u, 0x40u}, + {0x13u, 0x08u}, + {0x18u, 0x40u}, + {0x1Au, 0x0Au}, + {0x1Bu, 0x40u}, + {0x1Du, 0x11u}, + {0x1Eu, 0x22u}, + {0x1Fu, 0x40u}, + {0x20u, 0x80u}, + {0x25u, 0x08u}, + {0x27u, 0x26u}, + {0x29u, 0x40u}, + {0x2Au, 0x04u}, + {0x2Bu, 0x88u}, + {0x2Cu, 0x02u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x04u}, + {0x31u, 0x08u}, + {0x32u, 0x80u}, + {0x33u, 0x02u}, + {0x37u, 0x2Au}, + {0x3Au, 0x18u}, + {0x3Du, 0x11u}, + {0x3Eu, 0x04u}, + {0x4Cu, 0x08u}, + {0x4Eu, 0x04u}, + {0x58u, 0x10u}, + {0x59u, 0x08u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x20u}, + {0x5Fu, 0x80u}, + {0x60u, 0x0Au}, + {0x62u, 0x08u}, + {0x63u, 0x20u}, + {0x65u, 0x80u}, + {0x66u, 0x80u}, + {0x67u, 0x04u}, + {0x78u, 0x0Cu}, + {0x80u, 0xC0u}, + {0x83u, 0x40u}, + {0x87u, 0xC0u}, + {0x89u, 0x40u}, + {0x8Bu, 0x03u}, + {0x8Du, 0x20u}, + {0x91u, 0x51u}, + {0x92u, 0x44u}, + {0x96u, 0x08u}, + {0x97u, 0x22u}, + {0x98u, 0x10u}, + {0x99u, 0x0Au}, + {0x9Au, 0x51u}, + {0x9Bu, 0x18u}, + {0x9Cu, 0x04u}, + {0x9Eu, 0x80u}, + {0xA3u, 0x24u}, + {0xA6u, 0x08u}, + {0xA7u, 0x40u}, + {0xAAu, 0x04u}, + {0xACu, 0x10u}, + {0xB1u, 0x04u}, + {0xB2u, 0x04u}, + {0xB4u, 0x04u}, + {0xB5u, 0x08u}, + {0xC0u, 0x5Du}, + {0xC2u, 0xEFu}, + {0xC4u, 0x0Fu}, + {0xCAu, 0x3Fu}, + {0xCCu, 0xEBu}, + {0xCEu, 0xE6u}, + {0xD6u, 0x3Eu}, + {0xD8u, 0x3Eu}, + {0xE0u, 0x10u}, + {0xE2u, 0x06u}, + {0xE4u, 0x16u}, + {0xE6u, 0x01u}, + {0xEEu, 0x02u}, + {0x04u, 0x20u}, + {0x06u, 0x50u}, + {0x0Au, 0x04u}, + {0x0Eu, 0x03u}, + {0x10u, 0x20u}, + {0x12u, 0x18u}, + {0x14u, 0x20u}, + {0x16u, 0x10u}, + {0x18u, 0x04u}, + {0x19u, 0x02u}, + {0x1Au, 0x02u}, + {0x1Du, 0x04u}, + {0x20u, 0x10u}, + {0x21u, 0x01u}, + {0x22u, 0x20u}, + {0x24u, 0x20u}, + {0x25u, 0x08u}, + {0x26u, 0x10u}, + {0x2Au, 0x04u}, + {0x2Cu, 0x04u}, + {0x2Du, 0x02u}, + {0x2Eu, 0x01u}, + {0x2Fu, 0x04u}, + {0x30u, 0x40u}, + {0x32u, 0x08u}, + {0x33u, 0x08u}, + {0x34u, 0x30u}, + {0x35u, 0x01u}, + {0x36u, 0x07u}, + {0x37u, 0x06u}, + {0x3Au, 0x20u}, + {0x3Fu, 0x40u}, + {0x56u, 0x08u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x91u}, + {0x5Du, 0x90u}, + {0x5Fu, 0x01u}, + {0x82u, 0xFFu}, + {0x84u, 0xFFu}, + {0x87u, 0xFFu}, + {0x8Bu, 0xFFu}, + {0x90u, 0x55u}, + {0x91u, 0x33u}, + {0x92u, 0xAAu}, + {0x93u, 0xCCu}, + {0x94u, 0x33u}, + {0x95u, 0x21u}, + {0x96u, 0xCCu}, + {0x97u, 0x12u}, + {0x98u, 0xFFu}, + {0x9Du, 0x0Fu}, + {0x9Fu, 0xF0u}, + {0xA0u, 0x96u}, + {0xA1u, 0x84u}, + {0xA2u, 0x69u}, + {0xA3u, 0x48u}, + {0xA5u, 0x44u}, + {0xA6u, 0xFFu}, + {0xA7u, 0x88u}, + {0xA8u, 0x0Fu}, + {0xA9u, 0xFFu}, + {0xAAu, 0xF0u}, + {0xADu, 0x11u}, + {0xAEu, 0xFFu}, + {0xAFu, 0x22u}, + {0xB1u, 0xFFu}, + {0xB2u, 0xFFu}, + {0xB8u, 0x02u}, + {0xBAu, 0x08u}, + {0xBEu, 0x01u}, + {0xBFu, 0x01u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x01u}, + {0xDFu, 0x01u}, + {0x01u, 0x01u}, + {0x03u, 0x20u}, + {0x05u, 0x40u}, + {0x06u, 0x20u}, + {0x07u, 0x08u}, + {0x08u, 0x0Au}, + {0x0Au, 0x04u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x24u}, + {0x10u, 0x86u}, + {0x11u, 0xC0u}, + {0x13u, 0x08u}, + {0x15u, 0x41u}, + {0x17u, 0x16u}, + {0x19u, 0x08u}, + {0x1Au, 0x80u}, + {0x1Du, 0x42u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x14u}, + {0x23u, 0x40u}, + {0x24u, 0x08u}, + {0x26u, 0x08u}, + {0x27u, 0x01u}, + {0x28u, 0x40u}, + {0x29u, 0x40u}, + {0x2Au, 0x08u}, + {0x2Bu, 0x88u}, + {0x2Fu, 0x52u}, + {0x31u, 0x08u}, + {0x32u, 0x80u}, + {0x33u, 0x02u}, + {0x34u, 0x44u}, + {0x35u, 0x08u}, + {0x37u, 0x20u}, + {0x39u, 0x08u}, + {0x3Au, 0x14u}, + {0x45u, 0x80u}, + {0x46u, 0x01u}, + {0x59u, 0x04u}, + {0x5Au, 0x10u}, + {0x5Bu, 0x82u}, + {0x5Cu, 0x40u}, + {0x5Fu, 0x10u}, + {0x61u, 0x80u}, + {0x66u, 0x20u}, + {0x67u, 0x02u}, + {0x6Fu, 0x02u}, + {0x82u, 0x40u}, + {0x86u, 0x08u}, + {0x8Au, 0x8Au}, + {0x8Du, 0x04u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x80u}, + {0x92u, 0x04u}, + {0x93u, 0x80u}, + {0x97u, 0x6Au}, + {0x98u, 0x0Au}, + {0x99u, 0x80u}, + {0x9Au, 0x11u}, + {0x9Bu, 0x3Cu}, + {0x9Du, 0x40u}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0x01u}, + {0xA0u, 0x82u}, + {0xA1u, 0x08u}, + {0xA2u, 0x01u}, + {0xA3u, 0xBCu}, + {0xA6u, 0x80u}, + {0xA7u, 0x02u}, + {0xABu, 0x20u}, + {0xACu, 0x40u}, + {0xAFu, 0x80u}, + {0xB3u, 0x02u}, + {0xB7u, 0x08u}, + {0xC0u, 0xECu}, + {0xC2u, 0x7Eu}, + {0xC4u, 0xFFu}, + {0xCAu, 0xDFu}, + {0xCCu, 0x3Bu}, + {0xCEu, 0x06u}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x38u}, + {0xE2u, 0x09u}, + {0xE6u, 0xA2u}, + {0xE8u, 0x03u}, + {0xEEu, 0x08u}, + {0x85u, 0x04u}, + {0x88u, 0x01u}, + {0x8Du, 0x02u}, + {0x91u, 0x04u}, + {0x9Bu, 0x20u}, + {0x9Cu, 0xD1u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x01u}, + {0xA1u, 0x22u}, + {0xA5u, 0x08u}, + {0xAAu, 0x02u}, + {0xABu, 0x04u}, + {0xADu, 0x10u}, + {0xAEu, 0x10u}, + {0xB0u, 0x02u}, + {0xB1u, 0x04u}, + {0xB5u, 0x41u}, + {0xE2u, 0x89u}, + {0xE6u, 0x10u}, + {0xEAu, 0x10u}, + {0xECu, 0x80u}, + {0x00u, 0x0Fu}, + {0x02u, 0xF0u}, + {0x04u, 0x11u}, + {0x05u, 0x44u}, + {0x06u, 0x22u}, + {0x07u, 0x88u}, + {0x08u, 0x12u}, + {0x09u, 0x48u}, + {0x0Au, 0x21u}, + {0x0Bu, 0x84u}, + {0x0Du, 0x0Fu}, + {0x0Fu, 0xF0u}, + {0x11u, 0x12u}, + {0x12u, 0xFFu}, + {0x13u, 0x21u}, + {0x16u, 0xFFu}, + {0x19u, 0xFFu}, + {0x1Au, 0xFFu}, + {0x1Du, 0xFFu}, + {0x21u, 0x33u}, + {0x23u, 0xCCu}, + {0x24u, 0x44u}, + {0x25u, 0x11u}, + {0x26u, 0x88u}, + {0x27u, 0x22u}, + {0x28u, 0x48u}, + {0x2Au, 0x84u}, + {0x2Bu, 0xFFu}, + {0x2Cu, 0x33u}, + {0x2Eu, 0xCCu}, + {0x35u, 0xFFu}, + {0x36u, 0xFFu}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x01u}, + {0x81u, 0x02u}, + {0x82u, 0x02u}, + {0x83u, 0x05u}, + {0x84u, 0x04u}, + {0x85u, 0x02u}, + {0x87u, 0x21u}, + {0x88u, 0x04u}, + {0x89u, 0x02u}, + {0x8Bu, 0x01u}, + {0x8Cu, 0x02u}, + {0x8Du, 0x02u}, + {0x8Eu, 0x01u}, + {0x8Fu, 0x01u}, + {0x91u, 0x10u}, + {0x94u, 0x02u}, + {0x96u, 0x09u}, + {0x99u, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x04u}, + {0xA0u, 0x02u}, + {0xA2u, 0x01u}, + {0xA4u, 0x02u}, + {0xA5u, 0x08u}, + {0xA6u, 0x11u}, + {0xA8u, 0x04u}, + {0xADu, 0x08u}, + {0xAFu, 0x10u}, + {0xB0u, 0x03u}, + {0xB1u, 0x18u}, + {0xB2u, 0x10u}, + {0xB3u, 0x03u}, + {0xB4u, 0x04u}, + {0xB5u, 0x04u}, + {0xB6u, 0x08u}, + {0xB7u, 0x20u}, + {0xBAu, 0x02u}, + {0xBBu, 0x08u}, + {0xBEu, 0x10u}, + {0xBFu, 0x01u}, + {0xD6u, 0x08u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDDu, 0x90u}, + {0xDFu, 0x01u}, + {0x00u, 0x02u}, + {0x02u, 0x40u}, + {0x03u, 0x24u}, + {0x04u, 0x80u}, + {0x05u, 0x21u}, + {0x06u, 0x10u}, + {0x08u, 0x04u}, + {0x09u, 0x25u}, + {0x0Au, 0x80u}, + {0x0Eu, 0x21u}, + {0x10u, 0x02u}, + {0x11u, 0x14u}, + {0x12u, 0x01u}, + {0x15u, 0x21u}, + {0x16u, 0x20u}, + {0x1Au, 0x01u}, + {0x1Du, 0x13u}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x40u}, + {0x21u, 0x10u}, + {0x24u, 0x01u}, + {0x25u, 0x11u}, + {0x27u, 0x20u}, + {0x28u, 0x04u}, + {0x2Au, 0x01u}, + {0x2Bu, 0x20u}, + {0x2Cu, 0x02u}, + {0x2Du, 0x09u}, + {0x2Fu, 0x40u}, + {0x31u, 0x20u}, + {0x32u, 0x42u}, + {0x37u, 0x22u}, + {0x39u, 0x14u}, + {0x3Au, 0x40u}, + {0x3Cu, 0x01u}, + {0x3Du, 0xA0u}, + {0x3Eu, 0x08u}, + {0x5Du, 0x40u}, + {0x5Eu, 0x10u}, + {0x5Fu, 0x04u}, + {0x65u, 0x80u}, + {0x66u, 0x28u}, + {0x81u, 0x88u}, + {0x85u, 0x20u}, + {0x88u, 0x08u}, + {0x8Au, 0x01u}, + {0x8Bu, 0x20u}, + {0x8Du, 0x10u}, + {0x8Eu, 0x10u}, + {0x90u, 0x80u}, + {0x91u, 0x14u}, + {0x93u, 0x04u}, + {0x95u, 0x08u}, + {0x96u, 0x02u}, + {0x97u, 0x80u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0xD9u}, + {0x9Eu, 0x04u}, + {0xA0u, 0x01u}, + {0xA1u, 0x64u}, + {0xA5u, 0x19u}, + {0xAAu, 0x40u}, + {0xB0u, 0x04u}, + {0xB2u, 0x02u}, + {0xB4u, 0x04u}, + {0xB7u, 0x08u}, + {0xC0u, 0xFEu}, + {0xC2u, 0xAEu}, + {0xC4u, 0x77u}, + {0xCAu, 0x57u}, + {0xCCu, 0xADu}, + {0xCEu, 0xFEu}, + {0xD6u, 0x70u}, + {0xD8u, 0x70u}, + {0xE0u, 0xA0u}, + {0xE2u, 0x02u}, + {0xE4u, 0x30u}, + {0xE6u, 0x01u}, + {0xE8u, 0x10u}, + {0xEAu, 0x40u}, + {0xECu, 0xA1u}, + {0xEEu, 0x02u}, + {0x00u, 0x30u}, + {0x02u, 0xC0u}, + {0x03u, 0x08u}, + {0x04u, 0x50u}, + {0x05u, 0x40u}, + {0x06u, 0xA0u}, + {0x07u, 0x01u}, + {0x08u, 0x0Fu}, + {0x0Au, 0xF0u}, + {0x0Bu, 0x20u}, + {0x0Du, 0x01u}, + {0x0Fu, 0x0Eu}, + {0x11u, 0x18u}, + {0x13u, 0x03u}, + {0x14u, 0x06u}, + {0x15u, 0x03u}, + {0x16u, 0x09u}, + {0x17u, 0x14u}, + {0x18u, 0x60u}, + {0x19u, 0x02u}, + {0x1Au, 0x90u}, + {0x1Cu, 0x03u}, + {0x1Eu, 0x0Cu}, + {0x20u, 0x05u}, + {0x22u, 0x0Au}, + {0x23u, 0x80u}, + {0x27u, 0x1Fu}, + {0x29u, 0x04u}, + {0x31u, 0x80u}, + {0x33u, 0x1Fu}, + {0x35u, 0x40u}, + {0x36u, 0xFFu}, + {0x37u, 0x20u}, + {0x3Eu, 0x40u}, + {0x3Fu, 0x10u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x04u}, + {0x81u, 0x80u}, + {0x84u, 0x10u}, + {0x85u, 0x53u}, + {0x87u, 0xACu}, + {0x89u, 0x01u}, + {0x8Bu, 0x02u}, + {0x8Du, 0x40u}, + {0x91u, 0x12u}, + {0x93u, 0x01u}, + {0x94u, 0x01u}, + {0x98u, 0x15u}, + {0x9Au, 0x2Au}, + {0x9Cu, 0x20u}, + {0x9Du, 0x28u}, + {0x9Fu, 0x04u}, + {0xA1u, 0x04u}, + {0xA3u, 0x08u}, + {0xA4u, 0x02u}, + {0xA8u, 0x08u}, + {0xB0u, 0x0Cu}, + {0xB1u, 0xC0u}, + {0xB2u, 0x03u}, + {0xB3u, 0x30u}, + {0xB4u, 0x30u}, + {0xB5u, 0x0Fu}, + {0xBEu, 0x15u}, + {0xBFu, 0x15u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x02u, 0x50u}, + {0x04u, 0x02u}, + {0x05u, 0x04u}, + {0x06u, 0x08u}, + {0x08u, 0x04u}, + {0x09u, 0x80u}, + {0x0Bu, 0x08u}, + {0x0Cu, 0x24u}, + {0x0Du, 0x40u}, + {0x0Fu, 0x01u}, + {0x10u, 0x20u}, + {0x13u, 0x20u}, + {0x15u, 0x02u}, + {0x16u, 0x40u}, + {0x18u, 0x04u}, + {0x1Au, 0x90u}, + {0x1Cu, 0x02u}, + {0x20u, 0x90u}, + {0x21u, 0x20u}, + {0x24u, 0xA0u}, + {0x25u, 0x40u}, + {0x26u, 0x18u}, + {0x2Au, 0x02u}, + {0x2Cu, 0x10u}, + {0x2Fu, 0x48u}, + {0x32u, 0x01u}, + {0x33u, 0x40u}, + {0x35u, 0x20u}, + {0x36u, 0x0Au}, + {0x38u, 0x02u}, + {0x39u, 0x88u}, + {0x3Au, 0x18u}, + {0x3Bu, 0x08u}, + {0x3Du, 0x28u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x82u}, + {0x69u, 0x14u}, + {0x6Bu, 0x52u}, + {0x70u, 0x21u}, + {0x71u, 0x84u}, + {0x72u, 0x02u}, + {0x73u, 0x20u}, + {0x80u, 0x10u}, + {0x82u, 0x50u}, + {0x86u, 0x08u}, + {0x87u, 0x01u}, + {0x88u, 0x40u}, + {0x89u, 0x01u}, + {0x8Au, 0x10u}, + {0x8Du, 0x01u}, + {0x92u, 0x44u}, + {0x93u, 0x05u}, + {0x94u, 0x20u}, + {0x95u, 0x08u}, + {0x99u, 0x20u}, + {0x9Au, 0x10u}, + {0x9Cu, 0xC9u}, + {0x9Eu, 0x04u}, + {0x9Fu, 0x10u}, + {0xA3u, 0x40u}, + {0xA5u, 0x08u}, + {0xA6u, 0x0Au}, + {0xA8u, 0x04u}, + {0xAAu, 0xA0u}, + {0xABu, 0x04u}, + {0xAFu, 0x04u}, + {0xB0u, 0x04u}, + {0xB1u, 0x80u}, + {0xB2u, 0x04u}, + {0xB6u, 0x02u}, + {0xC0u, 0x7Cu}, + {0xC2u, 0xE7u}, + {0xC4u, 0x16u}, + {0xCAu, 0xE1u}, + {0xCCu, 0xE9u}, + {0xCEu, 0xFFu}, + {0xE0u, 0x21u}, + {0xE2u, 0x80u}, + {0xE4u, 0x01u}, + {0xE8u, 0x60u}, + {0xEAu, 0x88u}, + {0xECu, 0x81u}, + {0xEEu, 0x20u}, + {0x00u, 0x02u}, + {0x02u, 0x09u}, + {0x04u, 0x02u}, + {0x05u, 0x08u}, + {0x06u, 0x11u}, + {0x07u, 0x10u}, + {0x0Du, 0x04u}, + {0x0Fu, 0x03u}, + {0x11u, 0x01u}, + {0x13u, 0x06u}, + {0x14u, 0x02u}, + {0x15u, 0x03u}, + {0x16u, 0x01u}, + {0x17u, 0x04u}, + {0x18u, 0x01u}, + {0x19u, 0x10u}, + {0x1Au, 0x02u}, + {0x1Cu, 0x02u}, + {0x1Eu, 0x05u}, + {0x21u, 0x05u}, + {0x23u, 0x02u}, + {0x29u, 0x08u}, + {0x30u, 0x10u}, + {0x32u, 0x04u}, + {0x34u, 0x03u}, + {0x35u, 0x18u}, + {0x36u, 0x08u}, + {0x37u, 0x07u}, + {0x3Au, 0x20u}, + {0x3Bu, 0x80u}, + {0x3Fu, 0x10u}, + {0x54u, 0x01u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x01u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x83u, 0x18u}, + {0x84u, 0x90u}, + {0x86u, 0x2Fu}, + {0x87u, 0x20u}, + {0x88u, 0xC0u}, + {0x89u, 0x40u}, + {0x8Au, 0x1Fu}, + {0x8Cu, 0x03u}, + {0x8Eu, 0x0Cu}, + {0x8Fu, 0x04u}, + {0x91u, 0x24u}, + {0x93u, 0x12u}, + {0x96u, 0x70u}, + {0x97u, 0x24u}, + {0x98u, 0x0Fu}, + {0x9Eu, 0x80u}, + {0xA0u, 0x06u}, + {0xA2u, 0x09u}, + {0xA7u, 0x03u}, + {0xA8u, 0x05u}, + {0xA9u, 0x24u}, + {0xAAu, 0x0Au}, + {0xABu, 0x09u}, + {0xACu, 0xA0u}, + {0xAEu, 0x4Fu}, + {0xB0u, 0x80u}, + {0xB2u, 0x7Fu}, + {0xB3u, 0x07u}, + {0xB5u, 0x40u}, + {0xB7u, 0x38u}, + {0xBEu, 0x01u}, + {0xBFu, 0x10u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x11u}, + {0xDFu, 0x01u}, + {0x00u, 0x08u}, + {0x01u, 0x02u}, + {0x04u, 0x20u}, + {0x06u, 0x22u}, + {0x0Au, 0x2Au}, + {0x0Eu, 0x25u}, + {0x11u, 0x0Cu}, + {0x12u, 0x10u}, + {0x14u, 0x42u}, + {0x16u, 0x04u}, + {0x18u, 0x04u}, + {0x19u, 0x02u}, + {0x1Au, 0x2Au}, + {0x1Eu, 0x20u}, + {0x1Fu, 0x01u}, + {0x21u, 0x40u}, + {0x22u, 0xA0u}, + {0x24u, 0x01u}, + {0x25u, 0x04u}, + {0x27u, 0x04u}, + {0x28u, 0x88u}, + {0x2Du, 0x04u}, + {0x2Eu, 0x20u}, + {0x30u, 0x01u}, + {0x31u, 0x08u}, + {0x33u, 0x10u}, + {0x34u, 0x02u}, + {0x36u, 0x0Au}, + {0x39u, 0x88u}, + {0x3Cu, 0x01u}, + {0x3Du, 0x10u}, + {0x3Eu, 0x08u}, + {0x3Fu, 0x41u}, + {0x59u, 0x40u}, + {0x5Du, 0x80u}, + {0x5Fu, 0x2Au}, + {0x67u, 0x02u}, + {0x6Du, 0x10u}, + {0x6Eu, 0x44u}, + {0x81u, 0x20u}, + {0x82u, 0x20u}, + {0x83u, 0x62u}, + {0x85u, 0x40u}, + {0x86u, 0x19u}, + {0x87u, 0x08u}, + {0x8Bu, 0x40u}, + {0xC0u, 0xECu}, + {0xC2u, 0xE7u}, + {0xC4u, 0xD0u}, + {0xCAu, 0x65u}, + {0xCCu, 0xC7u}, + {0xCEu, 0xFAu}, + {0xD6u, 0xF8u}, + {0xD8u, 0x10u}, + {0xE0u, 0x20u}, + {0xE6u, 0x20u}, + {0x80u, 0x02u}, + {0x82u, 0x64u}, + {0x84u, 0x11u}, + {0x88u, 0xC4u}, + {0x8Au, 0x02u}, + {0x8Eu, 0x11u}, + {0x92u, 0x20u}, + {0x96u, 0x01u}, + {0x98u, 0x0Cu}, + {0x9Cu, 0x11u}, + {0xA0u, 0x11u}, + {0xA4u, 0x11u}, + {0xA8u, 0x02u}, + {0xAAu, 0xA8u}, + {0xB0u, 0xE0u}, + {0xB2u, 0x01u}, + {0xB4u, 0x0Eu}, + {0xB6u, 0x10u}, + {0xB8u, 0x20u}, + {0xBEu, 0x44u}, + {0xD8u, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x20u}, + {0x03u, 0x52u}, + {0x04u, 0x10u}, + {0x07u, 0x92u}, + {0x09u, 0x80u}, + {0x0Au, 0x80u}, + {0x0Bu, 0x14u}, + {0x0Cu, 0x90u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x48u}, + {0x10u, 0x08u}, + {0x12u, 0x40u}, + {0x13u, 0x40u}, + {0x15u, 0x02u}, + {0x17u, 0x28u}, + {0x18u, 0x80u}, + {0x19u, 0x20u}, + {0x1Bu, 0x03u}, + {0x1Du, 0x04u}, + {0x1Eu, 0x49u}, + {0x20u, 0x90u}, + {0x22u, 0x16u}, + {0x23u, 0xD4u}, + {0x2Bu, 0x81u}, + {0x32u, 0x16u}, + {0x33u, 0x40u}, + {0x39u, 0x54u}, + {0x3Au, 0x02u}, + {0x42u, 0x01u}, + {0x43u, 0x22u}, + {0x49u, 0x09u}, + {0x4Au, 0x80u}, + {0x4Bu, 0x50u}, + {0x51u, 0x08u}, + {0x52u, 0x50u}, + {0x53u, 0x80u}, + {0x63u, 0x08u}, + {0x68u, 0x08u}, + {0x69u, 0x56u}, + {0x6Au, 0x82u}, + {0x6Bu, 0x5Au}, + {0x70u, 0x80u}, + {0x71u, 0x80u}, + {0x72u, 0x02u}, + {0x80u, 0x40u}, + {0x83u, 0x20u}, + {0x84u, 0x60u}, + {0x87u, 0x80u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x20u}, + {0x95u, 0x40u}, + {0x96u, 0x83u}, + {0x97u, 0x54u}, + {0x9Cu, 0x30u}, + {0x9Du, 0x0Du}, + {0x9Eu, 0x12u}, + {0x9Fu, 0x10u}, + {0xA3u, 0x04u}, + {0xA4u, 0x88u}, + {0xA5u, 0x08u}, + {0xA6u, 0x80u}, + {0xA7u, 0x03u}, + {0xAFu, 0xC0u}, + {0xB0u, 0x01u}, + {0xB1u, 0x08u}, + {0xB7u, 0x04u}, + {0xC0u, 0xFFu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x7Bu}, + {0xCAu, 0x09u}, + {0xCCu, 0x0Fu}, + {0xCEu, 0x0Fu}, + {0xD0u, 0x0Du}, + {0xD2u, 0x0Cu}, + {0xD8u, 0x04u}, + {0xE0u, 0x43u}, + {0xE6u, 0x40u}, + {0x02u, 0x12u}, + {0x05u, 0xFFu}, + {0x09u, 0x69u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x96u}, + {0x0Fu, 0xFFu}, + {0x10u, 0x21u}, + {0x12u, 0x02u}, + {0x13u, 0xFFu}, + {0x14u, 0x88u}, + {0x16u, 0x03u}, + {0x17u, 0xFFu}, + {0x19u, 0x0Fu}, + {0x1Au, 0xECu}, + {0x1Bu, 0xF0u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x33u}, + {0x1Eu, 0x43u}, + {0x1Fu, 0xCCu}, + {0x24u, 0xE0u}, + {0x25u, 0xFFu}, + {0x2Du, 0x55u}, + {0x2Fu, 0xAAu}, + {0x32u, 0x10u}, + {0x34u, 0x0Fu}, + {0x35u, 0xFFu}, + {0x36u, 0xE0u}, + {0x3Bu, 0x20u}, + {0x3Eu, 0x40u}, + {0x54u, 0x40u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Fu, 0x01u}, + {0x80u, 0x10u}, + {0x81u, 0xC0u}, + {0x83u, 0x01u}, + {0x84u, 0x01u}, + {0x85u, 0x80u}, + {0x88u, 0x04u}, + {0x89u, 0x7Fu}, + {0x8Bu, 0x80u}, + {0x8Cu, 0x88u}, + {0x8Du, 0x1Fu}, + {0x8Eu, 0x21u}, + {0x8Fu, 0x20u}, + {0x90u, 0x87u}, + {0x91u, 0xC0u}, + {0x92u, 0x18u}, + {0x93u, 0x02u}, + {0x94u, 0x40u}, + {0x95u, 0xC0u}, + {0x97u, 0x08u}, + {0x98u, 0x40u}, + {0x99u, 0xC0u}, + {0x9Bu, 0x04u}, + {0x9Cu, 0x01u}, + {0x9Du, 0x90u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x01u}, + {0xA3u, 0x9Fu}, + {0xA4u, 0x01u}, + {0xA8u, 0xA2u}, + {0xAAu, 0x08u}, + {0xABu, 0x60u}, + {0xACu, 0x01u}, + {0xAFu, 0xFFu}, + {0xB0u, 0x08u}, + {0xB2u, 0x3Fu}, + {0xB4u, 0x40u}, + {0xB5u, 0xFFu}, + {0xB6u, 0x80u}, + {0xB8u, 0x28u}, + {0xBEu, 0x45u}, + {0xBFu, 0x10u}, + {0xD4u, 0x09u}, + {0xD6u, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x20u}, + {0x02u, 0x80u}, + {0x03u, 0x12u}, + {0x04u, 0x10u}, + {0x05u, 0x01u}, + {0x09u, 0x20u}, + {0x0Au, 0x22u}, + {0x0Bu, 0x40u}, + {0x0Eu, 0x08u}, + {0x0Fu, 0x52u}, + {0x10u, 0x80u}, + {0x11u, 0x40u}, + {0x13u, 0x14u}, + {0x14u, 0x10u}, + {0x19u, 0x70u}, + {0x1Au, 0x60u}, + {0x1Cu, 0x10u}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x80u}, + {0x21u, 0x20u}, + {0x26u, 0x20u}, + {0x27u, 0x04u}, + {0x29u, 0x11u}, + {0x2Bu, 0x02u}, + {0x2Fu, 0x21u}, + {0x30u, 0x08u}, + {0x32u, 0x41u}, + {0x33u, 0x10u}, + {0x35u, 0x80u}, + {0x36u, 0x20u}, + {0x37u, 0x0Au}, + {0x3Au, 0x02u}, + {0x3Bu, 0x54u}, + {0x3Du, 0x80u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x20u}, + {0x58u, 0x20u}, + {0x59u, 0x08u}, + {0x5Au, 0x41u}, + {0x61u, 0x40u}, + {0x62u, 0x02u}, + {0x64u, 0x01u}, + {0x65u, 0x04u}, + {0x66u, 0x10u}, + {0x67u, 0x80u}, + {0x92u, 0x04u}, + {0x93u, 0x02u}, + {0x99u, 0x80u}, + {0x9Bu, 0x0Au}, + {0xA1u, 0x40u}, + {0xA3u, 0x34u}, + {0xA6u, 0x02u}, + {0xA8u, 0x40u}, + {0xAAu, 0x10u}, + {0xAFu, 0x10u}, + {0xB1u, 0x0Cu}, + {0xB3u, 0x12u}, + {0xB4u, 0x04u}, + {0xC0u, 0x5Fu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x2Fu}, + {0xCAu, 0x5Du}, + {0xCCu, 0xFFu}, + {0xCEu, 0x7Fu}, + {0xD6u, 0x0Fu}, + {0xD8u, 0xF9u}, + {0xEAu, 0x11u}, + {0xEEu, 0x1Cu}, + {0x9Cu, 0x81u}, + {0x9Eu, 0x04u}, + {0xA5u, 0x08u}, + {0xABu, 0x20u}, + {0xB0u, 0x50u}, + {0xB1u, 0x20u}, + {0xE8u, 0xA0u}, + {0xEEu, 0x9Cu}, + {0x81u, 0x08u}, + {0x84u, 0x01u}, + {0x8Cu, 0x80u}, + {0x9Cu, 0x81u}, + {0xA5u, 0x08u}, + {0xB6u, 0x04u}, + {0xE0u, 0x10u}, + {0xECu, 0x10u}, + {0x04u, 0x10u}, + {0x0Cu, 0x20u}, + {0x0Du, 0x08u}, + {0x11u, 0x08u}, + {0x12u, 0x08u}, + {0x16u, 0x80u}, + {0x17u, 0x80u}, + {0x30u, 0x10u}, + {0x33u, 0x02u}, + {0x35u, 0x80u}, + {0x36u, 0x01u}, + {0x39u, 0x08u}, + {0x3Au, 0x80u}, + {0x3Du, 0x21u}, + {0x42u, 0x04u}, + {0x53u, 0x04u}, + {0x5Eu, 0x10u}, + {0x6Du, 0x08u}, + {0x6Fu, 0x02u}, + {0x81u, 0x10u}, + {0x8Cu, 0x10u}, + {0x8Eu, 0x10u}, + {0xC0u, 0x80u}, + {0xC2u, 0xA0u}, + {0xC4u, 0xF0u}, + {0xCCu, 0xF0u}, + {0xCEu, 0xF0u}, + {0xD0u, 0x10u}, + {0xD4u, 0x20u}, + {0xD6u, 0x20u}, + {0xE2u, 0x80u}, + {0x03u, 0x08u}, + {0x0Au, 0x01u}, + {0x30u, 0x04u}, + {0x33u, 0x10u}, + {0x37u, 0x84u}, + {0x39u, 0x80u}, + {0x52u, 0x02u}, + {0x63u, 0x08u}, + {0x8Bu, 0x04u}, + {0x95u, 0x01u}, + {0x96u, 0x04u}, + {0x97u, 0x08u}, + {0x9Bu, 0x90u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x80u}, + {0xA0u, 0x20u}, + {0xA2u, 0x02u}, + {0xA6u, 0x01u}, + {0xAAu, 0x0Au}, + {0xABu, 0x10u}, + {0xADu, 0x08u}, + {0xB1u, 0x04u}, + {0xC0u, 0x40u}, + {0xC2u, 0x40u}, + {0xCCu, 0xF0u}, + {0xCEu, 0x10u}, + {0xD4u, 0x80u}, + {0xD8u, 0x40u}, + {0xE8u, 0x40u}, + {0xEAu, 0x80u}, + {0x10u, 0x10u}, + {0x33u, 0x80u}, + {0x8Cu, 0x20u}, + {0x8Fu, 0x08u}, + {0x92u, 0x01u}, + {0x95u, 0x81u}, + {0x96u, 0x04u}, + {0x9Cu, 0x14u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x20u}, + {0xA3u, 0x08u}, + {0xA6u, 0x01u}, + {0xABu, 0x04u}, + {0xC4u, 0x10u}, + {0xCCu, 0x10u}, + {0xEEu, 0x20u}, + {0x6Bu, 0x40u}, + {0x83u, 0x44u}, + {0x84u, 0x04u}, + {0x89u, 0x80u}, + {0x8Au, 0x04u}, + {0x92u, 0x01u}, + {0x95u, 0x81u}, + {0x96u, 0x04u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x80u}, + {0x9Fu, 0x04u}, + {0xA6u, 0x01u}, + {0xA7u, 0x80u}, + {0xDCu, 0x20u}, + {0xE2u, 0x90u}, + {0xE6u, 0x80u}, + {0x04u, 0x10u}, + {0x05u, 0x02u}, + {0x09u, 0x02u}, + {0x0Au, 0x01u}, + {0x10u, 0x40u}, + {0x5Au, 0x20u}, + {0x5Bu, 0x01u}, + {0x5Eu, 0x02u}, + {0x78u, 0x80u}, + {0x89u, 0x02u}, + {0xC0u, 0x05u}, + {0xC2u, 0x0Au}, + {0xC4u, 0x08u}, + {0xD4u, 0x01u}, + {0xD6u, 0x03u}, + {0xDCu, 0x01u}, + {0xE6u, 0x04u}, + {0x01u, 0x44u}, + {0x08u, 0x08u}, + {0x09u, 0x40u}, + {0x57u, 0x08u}, + {0x5Fu, 0x20u}, + {0x65u, 0x80u}, + {0x66u, 0x08u}, + {0x82u, 0x08u}, + {0x83u, 0x20u}, + {0x89u, 0x08u}, + {0x8Eu, 0x01u}, + {0x90u, 0x10u}, + {0x96u, 0x20u}, + {0x99u, 0x02u}, + {0x9Fu, 0x01u}, + {0xA6u, 0x01u}, + {0xA8u, 0x80u}, + {0xAEu, 0x01u}, + {0xB0u, 0x40u}, + {0xC0u, 0x0Au}, + {0xC2u, 0x0Au}, + {0xD4u, 0x02u}, + {0xD6u, 0x05u}, + {0xD8u, 0x01u}, + {0xE0u, 0x08u}, + {0xE4u, 0x04u}, + {0xEAu, 0x01u}, + {0x55u, 0x08u}, + {0x80u, 0x10u}, + {0x85u, 0x40u}, + {0x8Bu, 0x01u}, + {0x8Eu, 0x10u}, + {0x90u, 0x10u}, + {0x96u, 0x20u}, + {0x98u, 0x08u}, + {0x99u, 0x02u}, + {0x9Fu, 0x01u}, + {0xA1u, 0x48u}, + {0xABu, 0x08u}, + {0xADu, 0x04u}, + {0xB5u, 0xC0u}, + {0xD4u, 0x02u}, + {0xE0u, 0x02u}, + {0xE4u, 0x04u}, + {0xEAu, 0x02u}, + {0xECu, 0x02u}, + {0x09u, 0x10u}, + {0x0Bu, 0x80u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x02u}, + {0x81u, 0x02u}, + {0x87u, 0x40u}, + {0x98u, 0x08u}, + {0xB5u, 0x02u}, + {0xC2u, 0x0Fu}, + {0xEAu, 0x02u}, + {0x95u, 0x01u}, + {0xAEu, 0x01u}, + {0xAFu, 0x80u}, + {0xB5u, 0x40u}, + {0xB6u, 0x01u}, + {0xE8u, 0x10u}, + {0xEEu, 0x10u}, + {0x03u, 0x80u}, + {0x52u, 0x80u}, + {0x56u, 0x20u}, + {0x8Eu, 0x20u}, + {0x8Fu, 0x80u}, + {0xA2u, 0x80u}, + {0xADu, 0x01u}, + {0xAEu, 0x80u}, + {0xC0u, 0x10u}, + {0xD4u, 0x60u}, + {0xEAu, 0x10u}, + {0xEEu, 0x10u}, + {0xA8u, 0x08u}, + {0xAFu, 0x01u}, + {0xB5u, 0x10u}, + {0xEEu, 0x08u}, + {0x10u, 0x03u}, + {0x1Au, 0x03u}, + {0x00u, 0xFFu}, + {0x01u, 0xBFu}, + {0x02u, 0x2Au}, + {0x10u, 0x95u}, + }; + + + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + + CYPACKED typedef struct { + void CYFAR *dest; + const void CYCODE *src; + uint16 size; + } CYPACKED_ATTR cfg_memcpy_t; + + static const cfg_memset_t CYCODE cfg_memset_list[] = { + /* address, size */ + {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, + {(void CYFAR *)(CYREG_PRT5_DR), 16u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, + }; + + /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { + 0xD6u, 0x6Cu, 0x00u, 0x00u, 0xD2u, 0x64u, 0x04u, 0x08u, 0x20u, 0x40u, 0xD0u, 0x2Cu, 0x29u, 0x2Cu, 0x46u, 0x40u, + 0xD6u, 0x71u, 0x00u, 0x82u, 0x21u, 0xC0u, 0x8Eu, 0x2Fu, 0x02u, 0xA4u, 0x00u, 0x40u, 0xD6u, 0x6Cu, 0x00u, 0x00u, + 0x04u, 0x08u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x00u, 0x06u, 0x00u, 0x17u, 0x91u, 0x28u, 0x4Eu, + 0x0Fu, 0x0Fu, 0x00u, 0x31u, 0xF0u, 0xC0u, 0x00u, 0x00u, 0x02u, 0x00u, 0x20u, 0x2Cu, 0x00u, 0x00u, 0x00u, 0x00u, + 0x46u, 0x05u, 0x10u, 0x00u, 0x02u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ + static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { + 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x00u}; + + static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { + /* dest, src, size */ + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + } + + /* Copy device configuration data into registers */ + for (i = 0u; i < (sizeof(cfg_memcpy_list)/sizeof(cfg_memcpy_list[0])); i++) + { + const cfg_memcpy_t CYCODE * CYDATA mc = &cfg_memcpy_list[i]; + void * CYDATA destPtr = mc->dest; + const void CYCODE * CYDATA srcPtr = mc->src; + uint16 CYDATA numBytes = mc->size; + CYCONFIGCPYCODE(destPtr, srcPtr, numBytes); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Perform normal device configuration. Order is not critical for these items. */ + CYMEMZERO((void CYFAR *)(CYREG_PHUB_CFGMEM0_CFG0), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM1_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM1_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM2_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM2_VAL), 4u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PHUB_CFGMEM3_CFG0), (const void CYCODE *)(BS_PHUB_CFGMEM3_VAL), 4u); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + + /* Enable UDB array */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG0) | 0x40u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2, CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_AVAIL_CR2) | 0x10u); + } + + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DM0), (const void CYCODE *)(BS_IOPINS0_0_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR + 0x0000000Bu), (const void CYCODE *)(BS_IOPINS1_7_VAL), 5u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DR), (const void CYCODE *)(BS_IOPINS0_3_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h new file mode 100644 index 0000000..eefc440 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc new file mode 100644 index 0000000..d6a1b5c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -0,0 +1,2853 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu.inc" +.include "cydevicegnu_trm.inc" + +/* LED1 */ +.set LED1__0__INTTYPE, CYREG_PICU12_INTTYPE2 +.set LED1__0__MASK, 0x04 +.set LED1__0__PC, CYREG_PRT12_PC2 +.set LED1__0__PORT, 12 +.set LED1__0__SHIFT, 2 +.set LED1__1__INTTYPE, CYREG_PICU12_INTTYPE3 +.set LED1__1__MASK, 0x08 +.set LED1__1__PC, CYREG_PRT12_PC3 +.set LED1__1__PORT, 12 +.set LED1__1__SHIFT, 3 +.set LED1__AG, CYREG_PRT12_AG +.set LED1__BIE, CYREG_PRT12_BIE +.set LED1__BIT_MASK, CYREG_PRT12_BIT_MASK +.set LED1__BYP, CYREG_PRT12_BYP +.set LED1__DM0, CYREG_PRT12_DM0 +.set LED1__DM1, CYREG_PRT12_DM1 +.set LED1__DM2, CYREG_PRT12_DM2 +.set LED1__DR, CYREG_PRT12_DR +.set LED1__INP_DIS, CYREG_PRT12_INP_DIS +.set LED1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE +.set LED1__MASK, 0x0C +.set LED1__PORT, 12 +.set LED1__PRT, CYREG_PRT12_PRT +.set LED1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set LED1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set LED1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set LED1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set LED1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set LED1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set LED1__PS, CYREG_PRT12_PS +.set LED1__SHIFT, 2 +.set LED1__SIO_CFG, CYREG_PRT12_SIO_CFG +.set LED1__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set LED1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set LED1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set LED1__SLW, CYREG_PRT12_SLW + +/* SD_CS */ +.set SD_CS__0__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_CS__0__MASK, 0x08 +.set SD_CS__0__PC, CYREG_PRT3_PC3 +.set SD_CS__0__PORT, 3 +.set SD_CS__0__SHIFT, 3 +.set SD_CS__AG, CYREG_PRT3_AG +.set SD_CS__AMUX, CYREG_PRT3_AMUX +.set SD_CS__BIE, CYREG_PRT3_BIE +.set SD_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_CS__BYP, CYREG_PRT3_BYP +.set SD_CS__CTL, CYREG_PRT3_CTL +.set SD_CS__DM0, CYREG_PRT3_DM0 +.set SD_CS__DM1, CYREG_PRT3_DM1 +.set SD_CS__DM2, CYREG_PRT3_DM2 +.set SD_CS__DR, CYREG_PRT3_DR +.set SD_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_CS__MASK, 0x08 +.set SD_CS__PORT, 3 +.set SD_CS__PRT, CYREG_PRT3_PRT +.set SD_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_CS__PS, CYREG_PRT3_PS +.set SD_CS__SHIFT, 3 +.set SD_CS__SLW, CYREG_PRT3_SLW + +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 6 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x80 +.set USBFS_ep_1__INTC_NUMBER, 7 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_7 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x100 +.set USBFS_ep_2__INTC_NUMBER, 8 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_8 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_3__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_3__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_3__INTC_MASK, 0x200 +.set USBFS_ep_3__INTC_NUMBER, 9 +.set USBFS_ep_3__INTC_PRIOR_NUM, 7 +.set USBFS_ep_3__INTC_PRIOR_REG, CYREG_NVIC_PRI_9 +.set USBFS_ep_3__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_3__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_4__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_4__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_4__INTC_MASK, 0x400 +.set USBFS_ep_4__INTC_NUMBER, 10 +.set USBFS_ep_4__INTC_PRIOR_NUM, 7 +.set USBFS_ep_4__INTC_PRIOR_REG, CYREG_NVIC_PRI_10 +.set USBFS_ep_4__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_4__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 + +/* SDCard */ +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST +.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_RxStsReg__4__POS, 4 +.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20 +.set SDCard_BSPIM_RxStsReg__5__POS, 5 +.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40 +.set SDCard_BSPIM_RxStsReg__6__POS, 6 +.set SDCard_BSPIM_RxStsReg__MASK, 0x70 +.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB04_05_D1 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB04_05_F0 +.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB04_05_F1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB04_A0_A1 +.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB04_A0 +.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB04_A1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB04_D0_D1 +.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB04_D0 +.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB04_D1 +.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB04_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 +.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 +.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 +.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL +.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 +.set SDCard_BSPIM_TxStsReg__0__POS, 0 +.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 +.set SDCard_BSPIM_TxStsReg__1__POS, 1 +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 +.set SDCard_BSPIM_TxStsReg__2__POS, 2 +.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 +.set SDCard_BSPIM_TxStsReg__3__POS, 3 +.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 +.set SDCard_BSPIM_TxStsReg__4__POS, 4 +.set SDCard_BSPIM_TxStsReg__MASK, 0x1F +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST + +/* SD_SCK */ +.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_SCK__0__MASK, 0x02 +.set SD_SCK__0__PC, CYREG_PRT3_PC1 +.set SD_SCK__0__PORT, 3 +.set SD_SCK__0__SHIFT, 1 +.set SD_SCK__AG, CYREG_PRT3_AG +.set SD_SCK__AMUX, CYREG_PRT3_AMUX +.set SD_SCK__BIE, CYREG_PRT3_BIE +.set SD_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_SCK__BYP, CYREG_PRT3_BYP +.set SD_SCK__CTL, CYREG_PRT3_CTL +.set SD_SCK__DM0, CYREG_PRT3_DM0 +.set SD_SCK__DM1, CYREG_PRT3_DM1 +.set SD_SCK__DM2, CYREG_PRT3_DM2 +.set SD_SCK__DR, CYREG_PRT3_DR +.set SD_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_SCK__MASK, 0x02 +.set SD_SCK__PORT, 3 +.set SD_SCK__PRT, CYREG_PRT3_PRT +.set SD_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_SCK__PS, CYREG_PRT3_PS +.set SD_SCK__SHIFT, 1 +.set SD_SCK__SLW, CYREG_PRT3_SLW + +/* SCSI_In */ +.set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 +.set SCSI_In__0__MASK, 0x02 +.set SCSI_In__0__PC, CYREG_PRT6_PC1 +.set SCSI_In__0__PORT, 6 +.set SCSI_In__0__SHIFT, 1 +.set SCSI_In__AG, CYREG_PRT6_AG +.set SCSI_In__AMUX, CYREG_PRT6_AMUX +.set SCSI_In__BIE, CYREG_PRT6_BIE +.set SCSI_In__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In__BYP, CYREG_PRT6_BYP +.set SCSI_In__CTL, CYREG_PRT6_CTL +.set SCSI_In__DBP__INTTYPE, CYREG_PICU6_INTTYPE1 +.set SCSI_In__DBP__MASK, 0x02 +.set SCSI_In__DBP__PC, CYREG_PRT6_PC1 +.set SCSI_In__DBP__PORT, 6 +.set SCSI_In__DBP__SHIFT, 1 +.set SCSI_In__DM0, CYREG_PRT6_DM0 +.set SCSI_In__DM1, CYREG_PRT6_DM1 +.set SCSI_In__DM2, CYREG_PRT6_DM2 +.set SCSI_In__DR, CYREG_PRT6_DR +.set SCSI_In__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU6_BASE +.set SCSI_In__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In__MASK, 0x02 +.set SCSI_In__PORT, 6 +.set SCSI_In__PRT, CYREG_PRT6_PRT +.set SCSI_In__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In__PS, CYREG_PRT6_PS +.set SCSI_In__SHIFT, 1 +.set SCSI_In__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__0__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__0__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__0__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__0__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__0__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__0__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__0__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__0__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__0__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_In_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__0__MASK, 0x40 +.set SCSI_In_DBx__0__PC, CYREG_PRT6_PC6 +.set SCSI_In_DBx__0__PORT, 6 +.set SCSI_In_DBx__0__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__0__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__0__SHIFT, 6 +.set SCSI_In_DBx__0__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__1__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__1__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__1__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__1__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__1__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__1__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__1__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__1__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_In_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__1__MASK, 0x10 +.set SCSI_In_DBx__1__PC, CYREG_PRT6_PC4 +.set SCSI_In_DBx__1__PORT, 6 +.set SCSI_In_DBx__1__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__1__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__1__SHIFT, 4 +.set SCSI_In_DBx__1__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__2__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__2__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__2__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__2__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__2__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__2__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__2__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE4 +.set SCSI_In_DBx__2__MASK, 0x10 +.set SCSI_In_DBx__2__PC, CYREG_PRT12_PC4 +.set SCSI_In_DBx__2__PORT, 12 +.set SCSI_In_DBx__2__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__2__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__2__SHIFT, 4 +.set SCSI_In_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__2__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__3__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__3__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__3__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__3__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__3__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__3__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__3__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__3__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__3__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE6 +.set SCSI_In_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__3__MASK, 0x40 +.set SCSI_In_DBx__3__PC, CYREG_PRT2_PC6 +.set SCSI_In_DBx__3__PORT, 2 +.set SCSI_In_DBx__3__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__3__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__3__SHIFT, 6 +.set SCSI_In_DBx__3__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__4__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__4__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__4__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__4__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__4__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__4__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__4__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__4__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__4__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE4 +.set SCSI_In_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__4__MASK, 0x10 +.set SCSI_In_DBx__4__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__4__PORT, 2 +.set SCSI_In_DBx__4__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__4__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__4__SHIFT, 4 +.set SCSI_In_DBx__4__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__5__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__5__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__5__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__5__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__5__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__5__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__5__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__5__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__5__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE2 +.set SCSI_In_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__5__MASK, 0x04 +.set SCSI_In_DBx__5__PC, CYREG_PRT2_PC2 +.set SCSI_In_DBx__5__PORT, 2 +.set SCSI_In_DBx__5__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__5__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__5__SHIFT, 2 +.set SCSI_In_DBx__5__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_In_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__6__MASK, 0x01 +.set SCSI_In_DBx__6__PC, CYREG_PRT2_PC0 +.set SCSI_In_DBx__6__PORT, 2 +.set SCSI_In_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__6__SHIFT, 0 +.set SCSI_In_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__7__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__7__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__7__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__7__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__7__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__7__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__7__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__7__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__7__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__7__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__7__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__7__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_In_DBx__7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__7__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__7__MASK, 0x08 +.set SCSI_In_DBx__7__PC, CYREG_PRT6_PC3 +.set SCSI_In_DBx__7__PORT, 6 +.set SCSI_In_DBx__7__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__7__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__7__SHIFT, 3 +.set SCSI_In_DBx__7__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__DB0__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__DB0__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__DB0__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__DB0__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__DB0__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__DB0__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__DB0__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__DB0__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__DB0__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE6 +.set SCSI_In_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__DB0__MASK, 0x40 +.set SCSI_In_DBx__DB0__PC, CYREG_PRT6_PC6 +.set SCSI_In_DBx__DB0__PORT, 6 +.set SCSI_In_DBx__DB0__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__DB0__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__DB0__SHIFT, 6 +.set SCSI_In_DBx__DB0__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__DB1__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__DB1__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__DB1__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__DB1__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__DB1__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__DB1__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__DB1__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__DB1__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__DB1__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE4 +.set SCSI_In_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__DB1__MASK, 0x10 +.set SCSI_In_DBx__DB1__PC, CYREG_PRT6_PC4 +.set SCSI_In_DBx__DB1__PORT, 6 +.set SCSI_In_DBx__DB1__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__DB1__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__DB1__SHIFT, 4 +.set SCSI_In_DBx__DB1__SLW, CYREG_PRT6_SLW +.set SCSI_In_DBx__DB2__AG, CYREG_PRT12_AG +.set SCSI_In_DBx__DB2__BIE, CYREG_PRT12_BIE +.set SCSI_In_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_In_DBx__DB2__BYP, CYREG_PRT12_BYP +.set SCSI_In_DBx__DB2__DM0, CYREG_PRT12_DM0 +.set SCSI_In_DBx__DB2__DM1, CYREG_PRT12_DM1 +.set SCSI_In_DBx__DB2__DM2, CYREG_PRT12_DM2 +.set SCSI_In_DBx__DB2__DR, CYREG_PRT12_DR +.set SCSI_In_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_In_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE4 +.set SCSI_In_DBx__DB2__MASK, 0x10 +.set SCSI_In_DBx__DB2__PC, CYREG_PRT12_PC4 +.set SCSI_In_DBx__DB2__PORT, 12 +.set SCSI_In_DBx__DB2__PRT, CYREG_PRT12_PRT +.set SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_In_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_In_DBx__DB2__PS, CYREG_PRT12_PS +.set SCSI_In_DBx__DB2__SHIFT, 4 +.set SCSI_In_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_In_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_In_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_In_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_In_DBx__DB2__SLW, CYREG_PRT12_SLW +.set SCSI_In_DBx__DB3__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB3__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB3__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB3__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB3__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB3__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB3__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB3__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB3__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE6 +.set SCSI_In_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB3__MASK, 0x40 +.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC6 +.set SCSI_In_DBx__DB3__PORT, 2 +.set SCSI_In_DBx__DB3__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB3__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB3__SHIFT, 6 +.set SCSI_In_DBx__DB3__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB4__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB4__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB4__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB4__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB4__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB4__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB4__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB4__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB4__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE4 +.set SCSI_In_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB4__MASK, 0x10 +.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4 +.set SCSI_In_DBx__DB4__PORT, 2 +.set SCSI_In_DBx__DB4__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB4__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB4__SHIFT, 4 +.set SCSI_In_DBx__DB4__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB5__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB5__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB5__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB5__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB5__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB5__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB5__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB5__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB5__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE2 +.set SCSI_In_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB5__MASK, 0x04 +.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC2 +.set SCSI_In_DBx__DB5__PORT, 2 +.set SCSI_In_DBx__DB5__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB5__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB5__SHIFT, 2 +.set SCSI_In_DBx__DB5__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_In_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_In_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_In_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_In_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_In_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_In_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_In_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_In_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_In_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_In_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_In_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE0 +.set SCSI_In_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_In_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_In_DBx__DB6__MASK, 0x01 +.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC0 +.set SCSI_In_DBx__DB6__PORT, 2 +.set SCSI_In_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_In_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_In_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_In_DBx__DB6__SHIFT, 0 +.set SCSI_In_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_In_DBx__DB7__AG, CYREG_PRT6_AG +.set SCSI_In_DBx__DB7__AMUX, CYREG_PRT6_AMUX +.set SCSI_In_DBx__DB7__BIE, CYREG_PRT6_BIE +.set SCSI_In_DBx__DB7__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_In_DBx__DB7__BYP, CYREG_PRT6_BYP +.set SCSI_In_DBx__DB7__CTL, CYREG_PRT6_CTL +.set SCSI_In_DBx__DB7__DM0, CYREG_PRT6_DM0 +.set SCSI_In_DBx__DB7__DM1, CYREG_PRT6_DM1 +.set SCSI_In_DBx__DB7__DM2, CYREG_PRT6_DM2 +.set SCSI_In_DBx__DB7__DR, CYREG_PRT6_DR +.set SCSI_In_DBx__DB7__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_In_DBx__DB7__INTTYPE, CYREG_PICU6_INTTYPE3 +.set SCSI_In_DBx__DB7__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_In_DBx__DB7__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_In_DBx__DB7__MASK, 0x08 +.set SCSI_In_DBx__DB7__PC, CYREG_PRT6_PC3 +.set SCSI_In_DBx__DB7__PORT, 6 +.set SCSI_In_DBx__DB7__PRT, CYREG_PRT6_PRT +.set SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_In_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_In_DBx__DB7__PS, CYREG_PRT6_PS +.set SCSI_In_DBx__DB7__SHIFT, 3 +.set SCSI_In_DBx__DB7__SLW, CYREG_PRT6_SLW + +/* SD_MISO */ +.set SD_MISO__0__INTTYPE, CYREG_PICU3_INTTYPE0 +.set SD_MISO__0__MASK, 0x01 +.set SD_MISO__0__PC, CYREG_PRT3_PC0 +.set SD_MISO__0__PORT, 3 +.set SD_MISO__0__SHIFT, 0 +.set SD_MISO__AG, CYREG_PRT3_AG +.set SD_MISO__AMUX, CYREG_PRT3_AMUX +.set SD_MISO__BIE, CYREG_PRT3_BIE +.set SD_MISO__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MISO__BYP, CYREG_PRT3_BYP +.set SD_MISO__CTL, CYREG_PRT3_CTL +.set SD_MISO__DM0, CYREG_PRT3_DM0 +.set SD_MISO__DM1, CYREG_PRT3_DM1 +.set SD_MISO__DM2, CYREG_PRT3_DM2 +.set SD_MISO__DR, CYREG_PRT3_DR +.set SD_MISO__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MISO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MISO__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MISO__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MISO__MASK, 0x01 +.set SD_MISO__PORT, 3 +.set SD_MISO__PRT, CYREG_PRT3_PRT +.set SD_MISO__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MISO__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MISO__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MISO__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MISO__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MISO__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MISO__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MISO__PS, CYREG_PRT3_PS +.set SD_MISO__SHIFT, 0 +.set SD_MISO__SLW, CYREG_PRT3_SLW + +/* SD_MOSI */ +.set SD_MOSI__0__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_MOSI__0__MASK, 0x04 +.set SD_MOSI__0__PC, CYREG_PRT3_PC2 +.set SD_MOSI__0__PORT, 3 +.set SD_MOSI__0__SHIFT, 2 +.set SD_MOSI__AG, CYREG_PRT3_AG +.set SD_MOSI__AMUX, CYREG_PRT3_AMUX +.set SD_MOSI__BIE, CYREG_PRT3_BIE +.set SD_MOSI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_MOSI__BYP, CYREG_PRT3_BYP +.set SD_MOSI__CTL, CYREG_PRT3_CTL +.set SD_MOSI__DM0, CYREG_PRT3_DM0 +.set SD_MOSI__DM1, CYREG_PRT3_DM1 +.set SD_MOSI__DM2, CYREG_PRT3_DM2 +.set SD_MOSI__DR, CYREG_PRT3_DR +.set SD_MOSI__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_MOSI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_MOSI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_MOSI__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_MOSI__MASK, 0x04 +.set SD_MOSI__PORT, 3 +.set SD_MOSI__PRT, CYREG_PRT3_PRT +.set SD_MOSI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_MOSI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_MOSI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_MOSI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_MOSI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_MOSI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_MOSI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_MOSI__PS, CYREG_PRT3_PS +.set SD_MOSI__SHIFT, 2 +.set SD_MOSI__SLW, CYREG_PRT3_SLW + +/* TERM_EN */ +.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3 +.set TERM_EN__0__MASK, 0x08 +.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3 +.set TERM_EN__0__PORT, 15 +.set TERM_EN__0__SHIFT, 3 +.set TERM_EN__AG, CYREG_PRT15_AG +.set TERM_EN__AMUX, CYREG_PRT15_AMUX +.set TERM_EN__BIE, CYREG_PRT15_BIE +.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK +.set TERM_EN__BYP, CYREG_PRT15_BYP +.set TERM_EN__CTL, CYREG_PRT15_CTL +.set TERM_EN__DM0, CYREG_PRT15_DM0 +.set TERM_EN__DM1, CYREG_PRT15_DM1 +.set TERM_EN__DM2, CYREG_PRT15_DM2 +.set TERM_EN__DR, CYREG_PRT15_DR +.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS +.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN +.set TERM_EN__MASK, 0x08 +.set TERM_EN__PORT, 15 +.set TERM_EN__PRT, CYREG_PRT15_PRT +.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set TERM_EN__PS, CYREG_PRT15_PS +.set TERM_EN__SHIFT, 3 +.set TERM_EN__SLW, CYREG_PRT15_SLW + +/* SCSI_CLK */ +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 +.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SCSI_CLK__PM_STBY_MSK, 0x02 + +/* SCSI_Out */ +.set SCSI_Out__0__AG, CYREG_PRT6_AG +.set SCSI_Out__0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__0__BIE, CYREG_PRT6_BIE +.set SCSI_Out__0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__0__BYP, CYREG_PRT6_BYP +.set SCSI_Out__0__CTL, CYREG_PRT6_CTL +.set SCSI_Out__0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__0__DR, CYREG_PRT6_DR +.set SCSI_Out__0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__0__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__0__MASK, 0x04 +.set SCSI_Out__0__PC, CYREG_PRT6_PC2 +.set SCSI_Out__0__PORT, 6 +.set SCSI_Out__0__PRT, CYREG_PRT6_PRT +.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__0__PS, CYREG_PRT6_PS +.set SCSI_Out__0__SHIFT, 2 +.set SCSI_Out__0__SLW, CYREG_PRT6_SLW +.set SCSI_Out__1__AG, CYREG_PRT4_AG +.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__1__BIE, CYREG_PRT4_BIE +.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__1__BYP, CYREG_PRT4_BYP +.set SCSI_Out__1__CTL, CYREG_PRT4_CTL +.set SCSI_Out__1__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__1__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__1__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__1__DR, CYREG_PRT4_DR +.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE6 +.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__1__MASK, 0x40 +.set SCSI_Out__1__PC, CYREG_PRT4_PC6 +.set SCSI_Out__1__PORT, 4 +.set SCSI_Out__1__PRT, CYREG_PRT4_PRT +.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__1__PS, CYREG_PRT4_PS +.set SCSI_Out__1__SHIFT, 6 +.set SCSI_Out__1__SLW, CYREG_PRT4_SLW +.set SCSI_Out__2__AG, CYREG_PRT0_AG +.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__2__BIE, CYREG_PRT0_BIE +.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__2__BYP, CYREG_PRT0_BYP +.set SCSI_Out__2__CTL, CYREG_PRT0_CTL +.set SCSI_Out__2__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__2__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__2__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__2__DR, CYREG_PRT0_DR +.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7 +.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__2__MASK, 0x80 +.set SCSI_Out__2__PC, CYREG_PRT0_PC7 +.set SCSI_Out__2__PORT, 0 +.set SCSI_Out__2__PRT, CYREG_PRT0_PRT +.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__2__PS, CYREG_PRT0_PS +.set SCSI_Out__2__SHIFT, 7 +.set SCSI_Out__2__SLW, CYREG_PRT0_SLW +.set SCSI_Out__3__AG, CYREG_PRT0_AG +.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__3__BIE, CYREG_PRT0_BIE +.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__3__BYP, CYREG_PRT0_BYP +.set SCSI_Out__3__CTL, CYREG_PRT0_CTL +.set SCSI_Out__3__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__3__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__3__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__3__DR, CYREG_PRT0_DR +.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE5 +.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__3__MASK, 0x20 +.set SCSI_Out__3__PC, CYREG_PRT0_PC5 +.set SCSI_Out__3__PORT, 0 +.set SCSI_Out__3__PRT, CYREG_PRT0_PRT +.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__3__PS, CYREG_PRT0_PS +.set SCSI_Out__3__SHIFT, 5 +.set SCSI_Out__3__SLW, CYREG_PRT0_SLW +.set SCSI_Out__4__AG, CYREG_PRT0_AG +.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__4__BIE, CYREG_PRT0_BIE +.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__4__BYP, CYREG_PRT0_BYP +.set SCSI_Out__4__CTL, CYREG_PRT0_CTL +.set SCSI_Out__4__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__4__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__4__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__4__DR, CYREG_PRT0_DR +.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE3 +.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__4__MASK, 0x08 +.set SCSI_Out__4__PC, CYREG_PRT0_PC3 +.set SCSI_Out__4__PORT, 0 +.set SCSI_Out__4__PRT, CYREG_PRT0_PRT +.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__4__PS, CYREG_PRT0_PS +.set SCSI_Out__4__SHIFT, 3 +.set SCSI_Out__4__SLW, CYREG_PRT0_SLW +.set SCSI_Out__5__AG, CYREG_PRT0_AG +.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__5__BIE, CYREG_PRT0_BIE +.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__5__BYP, CYREG_PRT0_BYP +.set SCSI_Out__5__CTL, CYREG_PRT0_CTL +.set SCSI_Out__5__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__5__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__5__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__5__DR, CYREG_PRT0_DR +.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE1 +.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__5__MASK, 0x02 +.set SCSI_Out__5__PC, CYREG_PRT0_PC1 +.set SCSI_Out__5__PORT, 0 +.set SCSI_Out__5__PRT, CYREG_PRT0_PRT +.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__5__PS, CYREG_PRT0_PS +.set SCSI_Out__5__SHIFT, 1 +.set SCSI_Out__5__SLW, CYREG_PRT0_SLW +.set SCSI_Out__6__AG, CYREG_PRT4_AG +.set SCSI_Out__6__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__6__BIE, CYREG_PRT4_BIE +.set SCSI_Out__6__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__6__BYP, CYREG_PRT4_BYP +.set SCSI_Out__6__CTL, CYREG_PRT4_CTL +.set SCSI_Out__6__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__6__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__6__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__6__DR, CYREG_PRT4_DR +.set SCSI_Out__6__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__6__INTTYPE, CYREG_PICU4_INTTYPE1 +.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__6__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__6__MASK, 0x02 +.set SCSI_Out__6__PC, CYREG_PRT4_PC1 +.set SCSI_Out__6__PORT, 4 +.set SCSI_Out__6__PRT, CYREG_PRT4_PRT +.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__6__PS, CYREG_PRT4_PS +.set SCSI_Out__6__SHIFT, 1 +.set SCSI_Out__6__SLW, CYREG_PRT4_SLW +.set SCSI_Out__7__AG, CYREG_PRT4_AG +.set SCSI_Out__7__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__7__BIE, CYREG_PRT4_BIE +.set SCSI_Out__7__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__7__BYP, CYREG_PRT4_BYP +.set SCSI_Out__7__CTL, CYREG_PRT4_CTL +.set SCSI_Out__7__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__7__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__7__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__7__DR, CYREG_PRT4_DR +.set SCSI_Out__7__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__7__INTTYPE, CYREG_PICU4_INTTYPE0 +.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__7__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__7__MASK, 0x01 +.set SCSI_Out__7__PC, CYREG_PRT4_PC0 +.set SCSI_Out__7__PORT, 4 +.set SCSI_Out__7__PRT, CYREG_PRT4_PRT +.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__7__PS, CYREG_PRT4_PS +.set SCSI_Out__7__SHIFT, 0 +.set SCSI_Out__7__SLW, CYREG_PRT4_SLW +.set SCSI_Out__BSY__AG, CYREG_PRT4_AG +.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE +.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP +.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL +.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__BSY__DR, CYREG_PRT4_DR +.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__BSY__INTTYPE, CYREG_PICU4_INTTYPE6 +.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__BSY__MASK, 0x40 +.set SCSI_Out__BSY__PC, CYREG_PRT4_PC6 +.set SCSI_Out__BSY__PORT, 4 +.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT +.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__BSY__PS, CYREG_PRT4_PS +.set SCSI_Out__BSY__SHIFT, 6 +.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW +.set SCSI_Out__CD_raw__AG, CYREG_PRT0_AG +.set SCSI_Out__CD_raw__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__CD_raw__BIE, CYREG_PRT0_BIE +.set SCSI_Out__CD_raw__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__CD_raw__BYP, CYREG_PRT0_BYP +.set SCSI_Out__CD_raw__CTL, CYREG_PRT0_CTL +.set SCSI_Out__CD_raw__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__CD_raw__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__CD_raw__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__CD_raw__DR, CYREG_PRT0_DR +.set SCSI_Out__CD_raw__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__CD_raw__INTTYPE, CYREG_PICU0_INTTYPE1 +.set SCSI_Out__CD_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__CD_raw__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__CD_raw__MASK, 0x02 +.set SCSI_Out__CD_raw__PC, CYREG_PRT0_PC1 +.set SCSI_Out__CD_raw__PORT, 0 +.set SCSI_Out__CD_raw__PRT, CYREG_PRT0_PRT +.set SCSI_Out__CD_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__CD_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__CD_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__CD_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__CD_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__CD_raw__PS, CYREG_PRT0_PS +.set SCSI_Out__CD_raw__SHIFT, 1 +.set SCSI_Out__CD_raw__SLW, CYREG_PRT0_SLW +.set SCSI_Out__DBP_raw__AG, CYREG_PRT6_AG +.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__DBP_raw__BIE, CYREG_PRT6_BIE +.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__DBP_raw__BYP, CYREG_PRT6_BYP +.set SCSI_Out__DBP_raw__CTL, CYREG_PRT6_CTL +.set SCSI_Out__DBP_raw__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__DBP_raw__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__DBP_raw__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__DBP_raw__DR, CYREG_PRT6_DR +.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__DBP_raw__MASK, 0x04 +.set SCSI_Out__DBP_raw__PC, CYREG_PRT6_PC2 +.set SCSI_Out__DBP_raw__PORT, 6 +.set SCSI_Out__DBP_raw__PRT, CYREG_PRT6_PRT +.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__DBP_raw__PS, CYREG_PRT6_PS +.set SCSI_Out__DBP_raw__SHIFT, 2 +.set SCSI_Out__DBP_raw__SLW, CYREG_PRT6_SLW +.set SCSI_Out__IO_raw__AG, CYREG_PRT4_AG +.set SCSI_Out__IO_raw__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__IO_raw__BIE, CYREG_PRT4_BIE +.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__IO_raw__BYP, CYREG_PRT4_BYP +.set SCSI_Out__IO_raw__CTL, CYREG_PRT4_CTL +.set SCSI_Out__IO_raw__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__IO_raw__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__IO_raw__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__IO_raw__DR, CYREG_PRT4_DR +.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU4_INTTYPE0 +.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__IO_raw__MASK, 0x01 +.set SCSI_Out__IO_raw__PC, CYREG_PRT4_PC0 +.set SCSI_Out__IO_raw__PORT, 4 +.set SCSI_Out__IO_raw__PRT, CYREG_PRT4_PRT +.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__IO_raw__PS, CYREG_PRT4_PS +.set SCSI_Out__IO_raw__SHIFT, 0 +.set SCSI_Out__IO_raw__SLW, CYREG_PRT4_SLW +.set SCSI_Out__MSG_raw__AG, CYREG_PRT0_AG +.set SCSI_Out__MSG_raw__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__MSG_raw__BIE, CYREG_PRT0_BIE +.set SCSI_Out__MSG_raw__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__MSG_raw__BYP, CYREG_PRT0_BYP +.set SCSI_Out__MSG_raw__CTL, CYREG_PRT0_CTL +.set SCSI_Out__MSG_raw__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__MSG_raw__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__MSG_raw__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__MSG_raw__DR, CYREG_PRT0_DR +.set SCSI_Out__MSG_raw__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__MSG_raw__INTTYPE, CYREG_PICU0_INTTYPE5 +.set SCSI_Out__MSG_raw__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__MSG_raw__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__MSG_raw__MASK, 0x20 +.set SCSI_Out__MSG_raw__PC, CYREG_PRT0_PC5 +.set SCSI_Out__MSG_raw__PORT, 0 +.set SCSI_Out__MSG_raw__PRT, CYREG_PRT0_PRT +.set SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__MSG_raw__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__MSG_raw__PS, CYREG_PRT0_PS +.set SCSI_Out__MSG_raw__SHIFT, 5 +.set SCSI_Out__MSG_raw__SLW, CYREG_PRT0_SLW +.set SCSI_Out__REQ__AG, CYREG_PRT4_AG +.set SCSI_Out__REQ__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__REQ__BIE, CYREG_PRT4_BIE +.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__REQ__BYP, CYREG_PRT4_BYP +.set SCSI_Out__REQ__CTL, CYREG_PRT4_CTL +.set SCSI_Out__REQ__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__REQ__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__REQ__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__REQ__DR, CYREG_PRT4_DR +.set SCSI_Out__REQ__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__REQ__INTTYPE, CYREG_PICU4_INTTYPE1 +.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__REQ__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__REQ__MASK, 0x02 +.set SCSI_Out__REQ__PC, CYREG_PRT4_PC1 +.set SCSI_Out__REQ__PORT, 4 +.set SCSI_Out__REQ__PRT, CYREG_PRT4_PRT +.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__REQ__PS, CYREG_PRT4_PS +.set SCSI_Out__REQ__SHIFT, 1 +.set SCSI_Out__REQ__SLW, CYREG_PRT4_SLW +.set SCSI_Out__RST__AG, CYREG_PRT0_AG +.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE +.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP +.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL +.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__RST__DR, CYREG_PRT0_DR +.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE7 +.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__RST__MASK, 0x80 +.set SCSI_Out__RST__PC, CYREG_PRT0_PC7 +.set SCSI_Out__RST__PORT, 0 +.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT +.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__RST__PS, CYREG_PRT0_PS +.set SCSI_Out__RST__SHIFT, 7 +.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW +.set SCSI_Out__SEL__AG, CYREG_PRT0_AG +.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__SEL__DR, CYREG_PRT0_DR +.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3 +.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__SEL__MASK, 0x08 +.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 +.set SCSI_Out__SEL__PORT, 0 +.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__SEL__PS, CYREG_PRT0_PS +.set SCSI_Out__SEL__SHIFT, 3 +.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW +.set SCSI_Out_Bits_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 +.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 +.set SCSI_Out_Bits_Sync_ctrl_reg__3__POS, 3 +.set SCSI_Out_Bits_Sync_ctrl_reg__4__MASK, 0x10 +.set SCSI_Out_Bits_Sync_ctrl_reg__4__POS, 4 +.set SCSI_Out_Bits_Sync_ctrl_reg__5__MASK, 0x20 +.set SCSI_Out_Bits_Sync_ctrl_reg__5__POS, 5 +.set SCSI_Out_Bits_Sync_ctrl_reg__6__MASK, 0x40 +.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 +.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 +.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK +.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE7 +.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__0__MASK, 0x80 +.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC7 +.set SCSI_Out_DBx__0__PORT, 6 +.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__0__SHIFT, 7 +.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__1__MASK, 0x20 +.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__1__PORT, 6 +.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__1__SHIFT, 5 +.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__2__AG, CYREG_PRT12_AG +.set SCSI_Out_DBx__2__BIE, CYREG_PRT12_BIE +.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Out_DBx__2__BYP, CYREG_PRT12_BYP +.set SCSI_Out_DBx__2__DM0, CYREG_PRT12_DM0 +.set SCSI_Out_DBx__2__DM1, CYREG_PRT12_DM1 +.set SCSI_Out_DBx__2__DM2, CYREG_PRT12_DM2 +.set SCSI_Out_DBx__2__DR, CYREG_PRT12_DR +.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Out_DBx__2__MASK, 0x20 +.set SCSI_Out_DBx__2__PC, CYREG_PRT12_PC5 +.set SCSI_Out_DBx__2__PORT, 12 +.set SCSI_Out_DBx__2__PRT, CYREG_PRT12_PRT +.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Out_DBx__2__PS, CYREG_PRT12_PS +.set SCSI_Out_DBx__2__SHIFT, 5 +.set SCSI_Out_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Out_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Out_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Out_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Out_DBx__2__SLW, CYREG_PRT12_SLW +.set SCSI_Out_DBx__3__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__3__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__3__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__3__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__3__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__3__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__3__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__3__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__3__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE7 +.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__3__MASK, 0x80 +.set SCSI_Out_DBx__3__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__3__PORT, 2 +.set SCSI_Out_DBx__3__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__3__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__3__SHIFT, 7 +.set SCSI_Out_DBx__3__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE5 +.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__4__MASK, 0x20 +.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC5 +.set SCSI_Out_DBx__4__PORT, 2 +.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__4__SHIFT, 5 +.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3 +.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__5__MASK, 0x08 +.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__5__PORT, 2 +.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__5__SHIFT, 3 +.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE1 +.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__6__MASK, 0x02 +.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC1 +.set SCSI_Out_DBx__6__PORT, 2 +.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__6__SHIFT, 1 +.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__7__AG, CYREG_PRT15_AG +.set SCSI_Out_DBx__7__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out_DBx__7__BIE, CYREG_PRT15_BIE +.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out_DBx__7__BYP, CYREG_PRT15_BYP +.set SCSI_Out_DBx__7__CTL, CYREG_PRT15_CTL +.set SCSI_Out_DBx__7__DM0, CYREG_PRT15_DM0 +.set SCSI_Out_DBx__7__DM1, CYREG_PRT15_DM1 +.set SCSI_Out_DBx__7__DM2, CYREG_PRT15_DM2 +.set SCSI_Out_DBx__7__DR, CYREG_PRT15_DR +.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU15_INTTYPE5 +.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out_DBx__7__MASK, 0x20 +.set SCSI_Out_DBx__7__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out_DBx__7__PORT, 15 +.set SCSI_Out_DBx__7__PRT, CYREG_PRT15_PRT +.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out_DBx__7__PS, CYREG_PRT15_PS +.set SCSI_Out_DBx__7__SHIFT, 5 +.set SCSI_Out_DBx__7__SLW, CYREG_PRT15_SLW +.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE7 +.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB0__MASK, 0x80 +.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC7 +.set SCSI_Out_DBx__DB0__PORT, 6 +.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB0__SHIFT, 7 +.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB1__MASK, 0x20 +.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__DB1__PORT, 6 +.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB1__SHIFT, 5 +.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB2__AG, CYREG_PRT12_AG +.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT12_BIE +.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT12_BYP +.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT12_DM0 +.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT12_DM1 +.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT12_DM2 +.set SCSI_Out_DBx__DB2__DR, CYREG_PRT12_DR +.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Out_DBx__DB2__MASK, 0x20 +.set SCSI_Out_DBx__DB2__PC, CYREG_PRT12_PC5 +.set SCSI_Out_DBx__DB2__PORT, 12 +.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT12_PRT +.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Out_DBx__DB2__PS, CYREG_PRT12_PS +.set SCSI_Out_DBx__DB2__SHIFT, 5 +.set SCSI_Out_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Out_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Out_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Out_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT12_SLW +.set SCSI_Out_DBx__DB3__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB3__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE7 +.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB3__MASK, 0x80 +.set SCSI_Out_DBx__DB3__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__DB3__PORT, 2 +.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB3__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB3__SHIFT, 7 +.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE5 +.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB4__MASK, 0x20 +.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC5 +.set SCSI_Out_DBx__DB4__PORT, 2 +.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB4__SHIFT, 5 +.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3 +.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB5__MASK, 0x08 +.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__DB5__PORT, 2 +.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB5__SHIFT, 3 +.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE1 +.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB6__MASK, 0x02 +.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC1 +.set SCSI_Out_DBx__DB6__PORT, 2 +.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB6__SHIFT, 1 +.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB7__AG, CYREG_PRT15_AG +.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT15_BIE +.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT15_BYP +.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT15_CTL +.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT15_DM0 +.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT15_DM1 +.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT15_DM2 +.set SCSI_Out_DBx__DB7__DR, CYREG_PRT15_DR +.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU15_INTTYPE5 +.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out_DBx__DB7__MASK, 0x20 +.set SCSI_Out_DBx__DB7__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out_DBx__DB7__PORT, 15 +.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT15_PRT +.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out_DBx__DB7__PS, CYREG_PRT15_PS +.set SCSI_Out_DBx__DB7__SHIFT, 5 +.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW + +/* SD_RX_DMA */ +.set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SD_RX_DMA__DRQ_NUMBER, 2 +.set SD_RX_DMA__NUMBEROF_TDS, 0 +.set SD_RX_DMA__PRIORITY, 0 +.set SD_RX_DMA__TERMIN_EN, 0 +.set SD_RX_DMA__TERMIN_SEL, 0 +.set SD_RX_DMA__TERMOUT0_EN, 1 +.set SD_RX_DMA__TERMOUT0_SEL, 2 +.set SD_RX_DMA__TERMOUT1_EN, 0 +.set SD_RX_DMA__TERMOUT1_SEL, 0 +.set SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SD_RX_DMA_COMPLETE__INTC_MASK, 0x20 +.set SD_RX_DMA_COMPLETE__INTC_NUMBER, 5 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SD_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_5 +.set SD_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SD_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA */ +.set SD_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SD_TX_DMA__DRQ_NUMBER, 3 +.set SD_TX_DMA__NUMBEROF_TDS, 0 +.set SD_TX_DMA__PRIORITY, 1 +.set SD_TX_DMA__TERMIN_EN, 0 +.set SD_TX_DMA__TERMIN_SEL, 0 +.set SD_TX_DMA__TERMOUT0_EN, 1 +.set SD_TX_DMA__TERMOUT0_SEL, 3 +.set SD_TX_DMA__TERMOUT1_EN, 0 +.set SD_TX_DMA__TERMOUT1_SEL, 0 +.set SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SD_TX_DMA_COMPLETE__INTC_MASK, 0x40 +.set SD_TX_DMA_COMPLETE__INTC_NUMBER, 6 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SD_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_6 +.set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Noise */ +.set SCSI_Noise__0__AG, CYREG_PRT4_AG +.set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__0__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__0__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__0__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__0__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__0__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__0__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__0__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__0__DR, CYREG_PRT4_DR +.set SCSI_Noise__0__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__0__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__0__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__0__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__0__MASK, 0x80 +.set SCSI_Noise__0__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__0__PORT, 4 +.set SCSI_Noise__0__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__0__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__0__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__0__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__0__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__0__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__0__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__0__PS, CYREG_PRT4_PS +.set SCSI_Noise__0__SHIFT, 7 +.set SCSI_Noise__0__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__1__AG, CYREG_PRT4_AG +.set SCSI_Noise__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__1__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__1__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__1__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__1__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__1__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__1__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__1__DR, CYREG_PRT4_DR +.set SCSI_Noise__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__1__INTTYPE, CYREG_PICU4_INTTYPE5 +.set SCSI_Noise__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__1__MASK, 0x20 +.set SCSI_Noise__1__PC, CYREG_PRT4_PC5 +.set SCSI_Noise__1__PORT, 4 +.set SCSI_Noise__1__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__1__PS, CYREG_PRT4_PS +.set SCSI_Noise__1__SHIFT, 5 +.set SCSI_Noise__1__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__2__AG, CYREG_PRT0_AG +.set SCSI_Noise__2__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__2__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__2__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__2__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__2__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__2__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__2__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__2__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__2__DR, CYREG_PRT0_DR +.set SCSI_Noise__2__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__2__INTTYPE, CYREG_PICU0_INTTYPE2 +.set SCSI_Noise__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__2__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__2__MASK, 0x04 +.set SCSI_Noise__2__PC, CYREG_PRT0_PC2 +.set SCSI_Noise__2__PORT, 0 +.set SCSI_Noise__2__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__2__PS, CYREG_PRT0_PS +.set SCSI_Noise__2__SHIFT, 2 +.set SCSI_Noise__2__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__3__AG, CYREG_PRT0_AG +.set SCSI_Noise__3__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__3__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__3__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__3__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__3__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__3__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__3__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__3__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__3__DR, CYREG_PRT0_DR +.set SCSI_Noise__3__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__3__INTTYPE, CYREG_PICU0_INTTYPE6 +.set SCSI_Noise__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__3__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__3__MASK, 0x40 +.set SCSI_Noise__3__PC, CYREG_PRT0_PC6 +.set SCSI_Noise__3__PORT, 0 +.set SCSI_Noise__3__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__3__PS, CYREG_PRT0_PS +.set SCSI_Noise__3__SHIFT, 6 +.set SCSI_Noise__3__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__4__AG, CYREG_PRT4_AG +.set SCSI_Noise__4__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__4__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__4__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__4__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__4__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__4__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__4__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__4__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__4__DR, CYREG_PRT4_DR +.set SCSI_Noise__4__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__4__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__4__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__4__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__4__MASK, 0x08 +.set SCSI_Noise__4__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__4__PORT, 4 +.set SCSI_Noise__4__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__4__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__4__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__4__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__4__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__4__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__4__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__4__PS, CYREG_PRT4_PS +.set SCSI_Noise__4__SHIFT, 3 +.set SCSI_Noise__4__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__ACK__AG, CYREG_PRT4_AG +.set SCSI_Noise__ACK__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__ACK__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__ACK__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__ACK__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__ACK__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__ACK__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__ACK__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__ACK__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__ACK__DR, CYREG_PRT4_DR +.set SCSI_Noise__ACK__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__ACK__INTTYPE, CYREG_PICU4_INTTYPE3 +.set SCSI_Noise__ACK__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__ACK__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__ACK__MASK, 0x08 +.set SCSI_Noise__ACK__PC, CYREG_PRT4_PC3 +.set SCSI_Noise__ACK__PORT, 4 +.set SCSI_Noise__ACK__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__ACK__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__ACK__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__ACK__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__ACK__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__ACK__PS, CYREG_PRT4_PS +.set SCSI_Noise__ACK__SHIFT, 3 +.set SCSI_Noise__ACK__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__ATN__AG, CYREG_PRT4_AG +.set SCSI_Noise__ATN__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__ATN__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__ATN__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__ATN__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__ATN__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__ATN__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__ATN__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__ATN__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__ATN__DR, CYREG_PRT4_DR +.set SCSI_Noise__ATN__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__ATN__INTTYPE, CYREG_PICU4_INTTYPE7 +.set SCSI_Noise__ATN__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__ATN__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__ATN__MASK, 0x80 +.set SCSI_Noise__ATN__PC, CYREG_PRT4_PC7 +.set SCSI_Noise__ATN__PORT, 4 +.set SCSI_Noise__ATN__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__ATN__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__ATN__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__ATN__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__ATN__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__ATN__PS, CYREG_PRT4_PS +.set SCSI_Noise__ATN__SHIFT, 7 +.set SCSI_Noise__ATN__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__BSY__AG, CYREG_PRT4_AG +.set SCSI_Noise__BSY__AMUX, CYREG_PRT4_AMUX +.set SCSI_Noise__BSY__BIE, CYREG_PRT4_BIE +.set SCSI_Noise__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Noise__BSY__BYP, CYREG_PRT4_BYP +.set SCSI_Noise__BSY__CTL, CYREG_PRT4_CTL +.set SCSI_Noise__BSY__DM0, CYREG_PRT4_DM0 +.set SCSI_Noise__BSY__DM1, CYREG_PRT4_DM1 +.set SCSI_Noise__BSY__DM2, CYREG_PRT4_DM2 +.set SCSI_Noise__BSY__DR, CYREG_PRT4_DR +.set SCSI_Noise__BSY__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Noise__BSY__INTTYPE, CYREG_PICU4_INTTYPE5 +.set SCSI_Noise__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Noise__BSY__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Noise__BSY__MASK, 0x20 +.set SCSI_Noise__BSY__PC, CYREG_PRT4_PC5 +.set SCSI_Noise__BSY__PORT, 4 +.set SCSI_Noise__BSY__PRT, CYREG_PRT4_PRT +.set SCSI_Noise__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Noise__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Noise__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Noise__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Noise__BSY__PS, CYREG_PRT4_PS +.set SCSI_Noise__BSY__SHIFT, 5 +.set SCSI_Noise__BSY__SLW, CYREG_PRT4_SLW +.set SCSI_Noise__RST__AG, CYREG_PRT0_AG +.set SCSI_Noise__RST__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__RST__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__RST__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__RST__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__RST__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__RST__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__RST__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__RST__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__RST__DR, CYREG_PRT0_DR +.set SCSI_Noise__RST__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__RST__INTTYPE, CYREG_PICU0_INTTYPE6 +.set SCSI_Noise__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__RST__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__RST__MASK, 0x40 +.set SCSI_Noise__RST__PC, CYREG_PRT0_PC6 +.set SCSI_Noise__RST__PORT, 0 +.set SCSI_Noise__RST__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__RST__PS, CYREG_PRT0_PS +.set SCSI_Noise__RST__SHIFT, 6 +.set SCSI_Noise__RST__SLW, CYREG_PRT0_SLW +.set SCSI_Noise__SEL__AG, CYREG_PRT0_AG +.set SCSI_Noise__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Noise__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Noise__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Noise__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Noise__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Noise__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Noise__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Noise__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Noise__SEL__DR, CYREG_PRT0_DR +.set SCSI_Noise__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Noise__SEL__INTTYPE, CYREG_PICU0_INTTYPE2 +.set SCSI_Noise__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Noise__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Noise__SEL__MASK, 0x04 +.set SCSI_Noise__SEL__PC, CYREG_PRT0_PC2 +.set SCSI_Noise__SEL__PORT, 0 +.set SCSI_Noise__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Noise__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Noise__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Noise__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Noise__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Noise__SEL__PS, CYREG_PRT0_PS +.set SCSI_Noise__SEL__SHIFT, 2 +.set SCSI_Noise__SEL__SLW, CYREG_PRT0_SLW + +/* scsiTarget */ +.set scsiTarget_datapath__16BIT_A0_REG, CYREG_B0_UDB00_01_A0 +.set scsiTarget_datapath__16BIT_A1_REG, CYREG_B0_UDB00_01_A1 +.set scsiTarget_datapath__16BIT_D0_REG, CYREG_B0_UDB00_01_D0 +.set scsiTarget_datapath__16BIT_D1_REG, CYREG_B0_UDB00_01_D1 +.set scsiTarget_datapath__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath__16BIT_F0_REG, CYREG_B0_UDB00_01_F0 +.set scsiTarget_datapath__16BIT_F1_REG, CYREG_B0_UDB00_01_F1 +.set scsiTarget_datapath__A0_A1_REG, CYREG_B0_UDB00_A0_A1 +.set scsiTarget_datapath__A0_REG, CYREG_B0_UDB00_A0 +.set scsiTarget_datapath__A1_REG, CYREG_B0_UDB00_A1 +.set scsiTarget_datapath__D0_D1_REG, CYREG_B0_UDB00_D0_D1 +.set scsiTarget_datapath__D0_REG, CYREG_B0_UDB00_D0 +.set scsiTarget_datapath__D1_REG, CYREG_B0_UDB00_D1 +.set scsiTarget_datapath__DP_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath__F0_F1_REG, CYREG_B0_UDB00_F0_F1 +.set scsiTarget_datapath__F0_REG, CYREG_B0_UDB00_F0 +.set scsiTarget_datapath__F1_REG, CYREG_B0_UDB00_F1 +.set scsiTarget_datapath__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath__PER_DP_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PI__16BIT_STATUS_REG, CYREG_B0_UDB00_01_ST +.set scsiTarget_datapath_PI__MASK_REG, CYREG_B0_UDB00_MSK +.set scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PI__STATUS_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PI__STATUS_CNT_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_CONTROL_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PI__STATUS_REG, CYREG_B0_UDB00_ST +.set scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_01_ACTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB00_01_CTL +.set scsiTarget_datapath_PO__16BIT_MASK_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB00_01_MSK +.set scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG, CYREG_B0_UDB00_ACTL +.set scsiTarget_datapath_PO__CONTROL_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__CONTROL_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__COUNT_REG, CYREG_B0_UDB00_CTL +.set scsiTarget_datapath_PO__COUNT_ST_REG, CYREG_B0_UDB00_ST_CTL +.set scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB00_MSK_ACTL +.set scsiTarget_datapath_PO__PERIOD_REG, CYREG_B0_UDB00_MSK +.set scsiTarget_StatusReg__0__MASK, 0x01 +.set scsiTarget_StatusReg__0__POS, 0 +.set scsiTarget_StatusReg__1__MASK, 0x02 +.set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__2__MASK, 0x04 +.set scsiTarget_StatusReg__2__POS, 2 +.set scsiTarget_StatusReg__3__MASK, 0x08 +.set scsiTarget_StatusReg__3__POS, 3 +.set scsiTarget_StatusReg__4__MASK, 0x10 +.set scsiTarget_StatusReg__4__POS, 4 +.set scsiTarget_StatusReg__MASK, 0x1F +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST + +/* Debug_Timer */ +.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set Debug_Timer_Interrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set Debug_Timer_Interrupt__INTC_MASK, 0x01 +.set Debug_Timer_Interrupt__INTC_NUMBER, 0 +.set Debug_Timer_Interrupt__INTC_PRIOR_NUM, 7 +.set Debug_Timer_Interrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set Debug_Timer_Interrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set Debug_Timer_Interrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set Debug_Timer_TimerHW__CAP0, CYREG_TMR0_CAP0 +.set Debug_Timer_TimerHW__CAP1, CYREG_TMR0_CAP1 +.set Debug_Timer_TimerHW__CFG0, CYREG_TMR0_CFG0 +.set Debug_Timer_TimerHW__CFG1, CYREG_TMR0_CFG1 +.set Debug_Timer_TimerHW__CFG2, CYREG_TMR0_CFG2 +.set Debug_Timer_TimerHW__CNT_CMP0, CYREG_TMR0_CNT_CMP0 +.set Debug_Timer_TimerHW__CNT_CMP1, CYREG_TMR0_CNT_CMP1 +.set Debug_Timer_TimerHW__PER0, CYREG_TMR0_PER0 +.set Debug_Timer_TimerHW__PER1, CYREG_TMR0_PER1 +.set Debug_Timer_TimerHW__PM_ACT_CFG, CYREG_PM_ACT_CFG3 +.set Debug_Timer_TimerHW__PM_ACT_MSK, 0x01 +.set Debug_Timer_TimerHW__PM_STBY_CFG, CYREG_PM_STBY_CFG3 +.set Debug_Timer_TimerHW__PM_STBY_MSK, 0x01 +.set Debug_Timer_TimerHW__RT0, CYREG_TMR0_RT0 +.set Debug_Timer_TimerHW__RT1, CYREG_TMR0_RT1 +.set Debug_Timer_TimerHW__SR0, CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +.set SCSI_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_RX_DMA__DRQ_NUMBER, 0 +.set SCSI_RX_DMA__NUMBEROF_TDS, 0 +.set SCSI_RX_DMA__PRIORITY, 2 +.set SCSI_RX_DMA__TERMIN_EN, 0 +.set SCSI_RX_DMA__TERMIN_SEL, 0 +.set SCSI_RX_DMA__TERMOUT0_EN, 1 +.set SCSI_RX_DMA__TERMOUT0_SEL, 0 +.set SCSI_RX_DMA__TERMOUT1_EN, 0 +.set SCSI_RX_DMA__TERMOUT1_SEL, 0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RX_DMA_COMPLETE__INTC_MASK, 0x04 +.set SCSI_RX_DMA_COMPLETE__INTC_NUMBER, 2 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_2 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +.set SCSI_TX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 +.set SCSI_TX_DMA__DRQ_NUMBER, 1 +.set SCSI_TX_DMA__NUMBEROF_TDS, 0 +.set SCSI_TX_DMA__PRIORITY, 2 +.set SCSI_TX_DMA__TERMIN_EN, 0 +.set SCSI_TX_DMA__TERMIN_SEL, 0 +.set SCSI_TX_DMA__TERMOUT0_EN, 1 +.set SCSI_TX_DMA__TERMOUT0_SEL, 1 +.set SCSI_TX_DMA__TERMOUT1_EN, 0 +.set SCSI_TX_DMA__TERMOUT1_SEL, 0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_TX_DMA_COMPLETE__INTC_MASK, 0x10 +.set SCSI_TX_DMA_COMPLETE__INTC_NUMBER, 4 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM, 7 +.set SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG, CYREG_NVIC_PRI_4 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 +.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set SD_Data_Clk__PM_STBY_MSK, 0x01 + +/* SPI_Pullups */ +.set SPI_Pullups__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SPI_Pullups__0__MASK, 0x10 +.set SPI_Pullups__0__PC, CYREG_PRT3_PC4 +.set SPI_Pullups__0__PORT, 3 +.set SPI_Pullups__0__SHIFT, 4 +.set SPI_Pullups__1__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SPI_Pullups__1__MASK, 0x20 +.set SPI_Pullups__1__PC, CYREG_PRT3_PC5 +.set SPI_Pullups__1__PORT, 3 +.set SPI_Pullups__1__SHIFT, 5 +.set SPI_Pullups__2__INTTYPE, CYREG_PICU3_INTTYPE6 +.set SPI_Pullups__2__MASK, 0x40 +.set SPI_Pullups__2__PC, CYREG_PRT3_PC6 +.set SPI_Pullups__2__PORT, 3 +.set SPI_Pullups__2__SHIFT, 6 +.set SPI_Pullups__3__INTTYPE, CYREG_PICU3_INTTYPE7 +.set SPI_Pullups__3__MASK, 0x80 +.set SPI_Pullups__3__PC, CYREG_PRT3_PC7 +.set SPI_Pullups__3__PORT, 3 +.set SPI_Pullups__3__SHIFT, 7 +.set SPI_Pullups__AG, CYREG_PRT3_AG +.set SPI_Pullups__AMUX, CYREG_PRT3_AMUX +.set SPI_Pullups__BIE, CYREG_PRT3_BIE +.set SPI_Pullups__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SPI_Pullups__BYP, CYREG_PRT3_BYP +.set SPI_Pullups__CTL, CYREG_PRT3_CTL +.set SPI_Pullups__DM0, CYREG_PRT3_DM0 +.set SPI_Pullups__DM1, CYREG_PRT3_DM1 +.set SPI_Pullups__DM2, CYREG_PRT3_DM2 +.set SPI_Pullups__DR, CYREG_PRT3_DR +.set SPI_Pullups__INP_DIS, CYREG_PRT3_INP_DIS +.set SPI_Pullups__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SPI_Pullups__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SPI_Pullups__LCD_EN, CYREG_PRT3_LCD_EN +.set SPI_Pullups__MASK, 0xF0 +.set SPI_Pullups__PORT, 3 +.set SPI_Pullups__PRT, CYREG_PRT3_PRT +.set SPI_Pullups__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SPI_Pullups__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SPI_Pullups__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SPI_Pullups__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SPI_Pullups__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SPI_Pullups__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SPI_Pullups__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SPI_Pullups__PS, CYREG_PRT3_PS +.set SPI_Pullups__SHIFT, 4 +.set SPI_Pullups__SLW, CYREG_PRT3_SLW +.set SPI_Pullups_1__0__INTTYPE, CYREG_PICU12_INTTYPE0 +.set SPI_Pullups_1__0__MASK, 0x01 +.set SPI_Pullups_1__0__PC, CYREG_PRT12_PC0 +.set SPI_Pullups_1__0__PORT, 12 +.set SPI_Pullups_1__0__SHIFT, 0 +.set SPI_Pullups_1__1__INTTYPE, CYREG_PICU12_INTTYPE1 +.set SPI_Pullups_1__1__MASK, 0x02 +.set SPI_Pullups_1__1__PC, CYREG_PRT12_PC1 +.set SPI_Pullups_1__1__PORT, 12 +.set SPI_Pullups_1__1__SHIFT, 1 +.set SPI_Pullups_1__AG, CYREG_PRT12_AG +.set SPI_Pullups_1__BIE, CYREG_PRT12_BIE +.set SPI_Pullups_1__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SPI_Pullups_1__BYP, CYREG_PRT12_BYP +.set SPI_Pullups_1__DM0, CYREG_PRT12_DM0 +.set SPI_Pullups_1__DM1, CYREG_PRT12_DM1 +.set SPI_Pullups_1__DM2, CYREG_PRT12_DM2 +.set SPI_Pullups_1__DR, CYREG_PRT12_DR +.set SPI_Pullups_1__INP_DIS, CYREG_PRT12_INP_DIS +.set SPI_Pullups_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE +.set SPI_Pullups_1__MASK, 0x03 +.set SPI_Pullups_1__PORT, 12 +.set SPI_Pullups_1__PRT, CYREG_PRT12_PRT +.set SPI_Pullups_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SPI_Pullups_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SPI_Pullups_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SPI_Pullups_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SPI_Pullups_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SPI_Pullups_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SPI_Pullups_1__PS, CYREG_PRT12_PS +.set SPI_Pullups_1__SHIFT, 0 +.set SPI_Pullups_1__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SPI_Pullups_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SPI_Pullups_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SPI_Pullups_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SPI_Pullups_1__SLW, CYREG_PRT12_SLW + +/* timer_clock */ +.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 +.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 +.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2 +.set timer_clock__CFG2_SRC_SEL_MASK, 0x07 +.set timer_clock__INDEX, 0x02 +.set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set timer_clock__PM_ACT_MSK, 0x04 +.set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set timer_clock__PM_STBY_MSK, 0x04 + +/* SCSI_RST_ISR */ +.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_RST_ISR__INTC_MASK, 0x02 +.set SCSI_RST_ISR__INTC_NUMBER, 1 +.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +.set SCSI_SEL_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set SCSI_SEL_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set SCSI_SEL_ISR__INTC_MASK, 0x08 +.set SCSI_SEL_ISR__INTC_NUMBER, 3 +.set SCSI_SEL_ISR__INTC_PRIOR_NUM, 7 +.set SCSI_SEL_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_3 +.set SCSI_SEL_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set SCSI_SEL_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +.set SCSI_Filtered_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Filtered_sts_sts_reg__0__POS, 0 +.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 +.set SCSI_Filtered_sts_sts_reg__1__POS, 1 +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 +.set SCSI_Filtered_sts_sts_reg__2__POS, 2 +.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 +.set SCSI_Filtered_sts_sts_reg__3__POS, 3 +.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 +.set SCSI_Filtered_sts_sts_reg__4__POS, 4 +.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST + +/* SCSI_CTL_PHASE */ +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK + +/* SCSI_Glitch_Ctl */ +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST + +/* Miscellaneous */ +.set BCLK__BUS_CLK__HZ, 50000000 +.set BCLK__BUS_CLK__KHZ, 50000 +.set BCLK__BUS_CLK__MHZ, 50 +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 +.set CYDEV_CHIP_JTAG_ID, 0x2E133069 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 +.set CYDEV_CHIP_REV_TMA4_ES, 17 +.set CYDEV_CHIP_REV_TMA4_ES2, 33 +.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 +.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 +.set CYDEV_CHIP_REVISION_4G_ES, 17 +.set CYDEV_CHIP_REVISION_4G_ES2, 33 +.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED +.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_DMA, 0 +.set CYDEV_CONFIGURATION_ECC, 0 +.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_DEBUG_ENABLE_MASK, 0x20 +.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DEBUGGING_XRES, 0 +.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 +.set CYDEV_ECC_ENABLE, 0 +.set CYDEV_HEAP_SIZE, 0x0400 +.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 +.set CYDEV_INTR_RISING, 0x0000007F +.set CYDEV_IS_EXPORTING_CODE, 0 +.set CYDEV_IS_IMPORTING_CODE, 0 +.set CYDEV_PROJ_TYPE, 2 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LAUNCHER, 5 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_PROTECTION_ENABLE, 0 +.set CYDEV_STACK_SIZE, 0x1000 +.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA, 5 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD, 5 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_VDDIO0, 5 +.set CYDEV_VDDIO0_MV, 5000 +.set CYDEV_VDDIO1, 5 +.set CYDEV_VDDIO1_MV, 5000 +.set CYDEV_VDDIO2, 5 +.set CYDEV_VDDIO2_MV, 5000 +.set CYDEV_VDDIO3_MV, 3300 +.set CYDEV_VIO0, 5 +.set CYDEV_VIO0_MV, 5000 +.set CYDEV_VIO1, 5 +.set CYDEV_VIO1_MV, 5000 +.set CYDEV_VIO2, 5 +.set CYDEV_VIO2_MV, 5000 +.set CYDEV_VIO3_MV, 3300 +.set CYIPBLOCK_ARM_CM3_VERSION, 0 +.set CYIPBLOCK_P3_ANAIF_VERSION, 0 +.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0 +.set CYIPBLOCK_P3_COMP_VERSION, 0 +.set CYIPBLOCK_P3_DMA_VERSION, 0 +.set CYIPBLOCK_P3_DRQ_VERSION, 0 +.set CYIPBLOCK_P3_EMIF_VERSION, 0 +.set CYIPBLOCK_P3_I2C_VERSION, 0 +.set CYIPBLOCK_P3_LCD_VERSION, 0 +.set CYIPBLOCK_P3_LPF_VERSION, 0 +.set CYIPBLOCK_P3_PM_VERSION, 0 +.set CYIPBLOCK_P3_TIMER_VERSION, 0 +.set CYIPBLOCK_P3_USB_VERSION, 0 +.set CYIPBLOCK_P3_VIDAC_VERSION, 0 +.set CYIPBLOCK_P3_VREF_VERSION, 0 +.set CYIPBLOCK_S8_GPIO_VERSION, 0 +.set CYIPBLOCK_S8_IRQ_VERSION, 0 +.set CYIPBLOCK_S8_SAR_VERSION, 0 +.set CYIPBLOCK_S8_SIO_VERSION, 0 +.set CYIPBLOCK_S8_UDB_VERSION, 0 +.set DMA_CHANNELS_USED__MASK0, 0x0000000F +.set CYDEV_BOOTLOADER_ENABLE, 0 +.endif diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc new file mode 100644 index 0000000..1fab3ec --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -0,0 +1,2853 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar.inc + INCLUDE cydeviceiar_trm.inc + +/* LED1 */ +LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE2 +LED1__0__MASK EQU 0x04 +LED1__0__PC EQU CYREG_PRT12_PC2 +LED1__0__PORT EQU 12 +LED1__0__SHIFT EQU 2 +LED1__1__INTTYPE EQU CYREG_PICU12_INTTYPE3 +LED1__1__MASK EQU 0x08 +LED1__1__PC EQU CYREG_PRT12_PC3 +LED1__1__PORT EQU 12 +LED1__1__SHIFT EQU 3 +LED1__AG EQU CYREG_PRT12_AG +LED1__BIE EQU CYREG_PRT12_BIE +LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +LED1__BYP EQU CYREG_PRT12_BYP +LED1__DM0 EQU CYREG_PRT12_DM0 +LED1__DM1 EQU CYREG_PRT12_DM1 +LED1__DM2 EQU CYREG_PRT12_DM2 +LED1__DR EQU CYREG_PRT12_DR +LED1__INP_DIS EQU CYREG_PRT12_INP_DIS +LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +LED1__MASK EQU 0x0C +LED1__PORT EQU 12 +LED1__PRT EQU CYREG_PRT12_PRT +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +LED1__PS EQU CYREG_PRT12_PS +LED1__SHIFT EQU 2 +LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +LED1__SLW EQU CYREG_PRT12_SLW + +/* SD_CS */ +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_CS__0__MASK EQU 0x08 +SD_CS__0__PC EQU CYREG_PRT3_PC3 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 3 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x08 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 3 +SD_CS__SLW EQU CYREG_PRT3_SLW + +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 + +/* SDCard */ +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +/* SD_SCK */ +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_SCK__0__MASK EQU 0x02 +SD_SCK__0__PC EQU CYREG_PRT3_PC1 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 1 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x02 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 1 +SD_SCK__SLW EQU CYREG_PRT3_SLW + +/* SCSI_In */ +SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 +SCSI_In__0__MASK EQU 0x02 +SCSI_In__0__PC EQU CYREG_PRT6_PC1 +SCSI_In__0__PORT EQU 6 +SCSI_In__0__SHIFT EQU 1 +SCSI_In__AG EQU CYREG_PRT6_AG +SCSI_In__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__BIE EQU CYREG_PRT6_BIE +SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__BYP EQU CYREG_PRT6_BYP +SCSI_In__CTL EQU CYREG_PRT6_CTL +SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1 +SCSI_In__DBP__MASK EQU 0x02 +SCSI_In__DBP__PC EQU CYREG_PRT6_PC1 +SCSI_In__DBP__PORT EQU 6 +SCSI_In__DBP__SHIFT EQU 1 +SCSI_In__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__DR EQU CYREG_PRT6_DR +SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE +SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__MASK EQU 0x02 +SCSI_In__PORT EQU 6 +SCSI_In__PRT EQU CYREG_PRT6_PRT +SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__PS EQU CYREG_PRT6_PS +SCSI_In__SHIFT EQU 1 +SCSI_In__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__0__MASK EQU 0x40 +SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__0__PORT EQU 6 +SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__0__SHIFT EQU 6 +SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__1__MASK EQU 0x10 +SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4 +SCSI_In_DBx__1__PORT EQU 6 +SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__1__SHIFT EQU 4 +SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4 +SCSI_In_DBx__2__MASK EQU 0x10 +SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__2__PORT EQU 12 +SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__2__SHIFT EQU 4 +SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6 +SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__3__MASK EQU 0x40 +SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__3__PORT EQU 2 +SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__3__SHIFT EQU 6 +SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4 +SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__4__MASK EQU 0x10 +SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__4__PORT EQU 2 +SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__4__SHIFT EQU 4 +SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2 +SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__5__MASK EQU 0x04 +SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__5__PORT EQU 2 +SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__5__SHIFT EQU 2 +SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__6__MASK EQU 0x01 +SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__6__PORT EQU 2 +SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__6__SHIFT EQU 0 +SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__7__MASK EQU 0x08 +SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3 +SCSI_In_DBx__7__PORT EQU 6 +SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__7__SHIFT EQU 3 +SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB0__MASK EQU 0x40 +SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__DB0__PORT EQU 6 +SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB0__SHIFT EQU 6 +SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB1__MASK EQU 0x10 +SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4 +SCSI_In_DBx__DB1__PORT EQU 6 +SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB1__SHIFT EQU 4 +SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4 +SCSI_In_DBx__DB2__MASK EQU 0x10 +SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__DB2__PORT EQU 12 +SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB2__SHIFT EQU 4 +SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6 +SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB3__MASK EQU 0x40 +SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__DB3__PORT EQU 2 +SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB3__SHIFT EQU 6 +SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4 +SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB4__MASK EQU 0x10 +SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__DB4__PORT EQU 2 +SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB4__SHIFT EQU 4 +SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2 +SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB5__MASK EQU 0x04 +SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__DB5__PORT EQU 2 +SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB5__SHIFT EQU 2 +SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB6__MASK EQU 0x01 +SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__DB6__PORT EQU 2 +SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB6__SHIFT EQU 0 +SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB7__MASK EQU 0x08 +SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3 +SCSI_In_DBx__DB7__PORT EQU 6 +SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB7__SHIFT EQU 3 +SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW + +/* SD_MISO */ +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_MISO__0__MASK EQU 0x01 +SD_MISO__0__PC EQU CYREG_PRT3_PC0 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 0 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x01 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 0 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +/* SD_MOSI */ +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_MOSI__0__MASK EQU 0x04 +SD_MOSI__0__PC EQU CYREG_PRT3_PC2 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 2 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x04 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 2 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +/* TERM_EN */ +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +/* SCSI_CLK */ +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + +/* SCSI_Out */ +SCSI_Out__0__AG EQU CYREG_PRT6_AG +SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__0__DR EQU CYREG_PRT6_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__0__MASK EQU 0x04 +SCSI_Out__0__PC EQU CYREG_PRT6_PC2 +SCSI_Out__0__PORT EQU 6 +SCSI_Out__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT6_PS +SCSI_Out__0__SHIFT EQU 2 +SCSI_Out__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out__1__AG EQU CYREG_PRT4_AG +SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT4_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT4_BYP +SCSI_Out__1__CTL EQU CYREG_PRT4_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__1__DR EQU CYREG_PRT4_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__1__MASK EQU 0x40 +SCSI_Out__1__PC EQU CYREG_PRT4_PC6 +SCSI_Out__1__PORT EQU 4 +SCSI_Out__1__PRT EQU CYREG_PRT4_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT4_PS +SCSI_Out__1__SHIFT EQU 6 +SCSI_Out__1__SLW EQU CYREG_PRT4_SLW +SCSI_Out__2__AG EQU CYREG_PRT0_AG +SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT0_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT0_BYP +SCSI_Out__2__CTL EQU CYREG_PRT0_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__2__DR EQU CYREG_PRT0_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__2__MASK EQU 0x80 +SCSI_Out__2__PC EQU CYREG_PRT0_PC7 +SCSI_Out__2__PORT EQU 0 +SCSI_Out__2__PRT EQU CYREG_PRT0_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT0_PS +SCSI_Out__2__SHIFT EQU 7 +SCSI_Out__2__SLW EQU CYREG_PRT0_SLW +SCSI_Out__3__AG EQU CYREG_PRT0_AG +SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT0_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT0_BYP +SCSI_Out__3__CTL EQU CYREG_PRT0_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__3__DR EQU CYREG_PRT0_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__3__MASK EQU 0x20 +SCSI_Out__3__PC EQU CYREG_PRT0_PC5 +SCSI_Out__3__PORT EQU 0 +SCSI_Out__3__PRT EQU CYREG_PRT0_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT0_PS +SCSI_Out__3__SHIFT EQU 5 +SCSI_Out__3__SLW EQU CYREG_PRT0_SLW +SCSI_Out__4__AG EQU CYREG_PRT0_AG +SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT0_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT0_BYP +SCSI_Out__4__CTL EQU CYREG_PRT0_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__4__DR EQU CYREG_PRT0_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__4__MASK EQU 0x08 +SCSI_Out__4__PC EQU CYREG_PRT0_PC3 +SCSI_Out__4__PORT EQU 0 +SCSI_Out__4__PRT EQU CYREG_PRT0_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT0_PS +SCSI_Out__4__SHIFT EQU 3 +SCSI_Out__4__SLW EQU CYREG_PRT0_SLW +SCSI_Out__5__AG EQU CYREG_PRT0_AG +SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT0_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT0_BYP +SCSI_Out__5__CTL EQU CYREG_PRT0_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__5__DR EQU CYREG_PRT0_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__5__MASK EQU 0x02 +SCSI_Out__5__PC EQU CYREG_PRT0_PC1 +SCSI_Out__5__PORT EQU 0 +SCSI_Out__5__PRT EQU CYREG_PRT0_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT0_PS +SCSI_Out__5__SHIFT EQU 1 +SCSI_Out__5__SLW EQU CYREG_PRT0_SLW +SCSI_Out__6__AG EQU CYREG_PRT4_AG +SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT4_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT4_BYP +SCSI_Out__6__CTL EQU CYREG_PRT4_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__6__DR EQU CYREG_PRT4_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__6__MASK EQU 0x02 +SCSI_Out__6__PC EQU CYREG_PRT4_PC1 +SCSI_Out__6__PORT EQU 4 +SCSI_Out__6__PRT EQU CYREG_PRT4_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT4_PS +SCSI_Out__6__SHIFT EQU 1 +SCSI_Out__6__SLW EQU CYREG_PRT4_SLW +SCSI_Out__7__AG EQU CYREG_PRT4_AG +SCSI_Out__7__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT4_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT4_BYP +SCSI_Out__7__CTL EQU CYREG_PRT4_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__7__DR EQU CYREG_PRT4_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__7__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__7__MASK EQU 0x01 +SCSI_Out__7__PC EQU CYREG_PRT4_PC0 +SCSI_Out__7__PORT EQU 4 +SCSI_Out__7__PRT EQU CYREG_PRT4_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT4_PS +SCSI_Out__7__SHIFT EQU 0 +SCSI_Out__7__SLW EQU CYREG_PRT4_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT4_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT4_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__BSY__MASK EQU 0x40 +SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6 +SCSI_Out__BSY__PORT EQU 4 +SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT4_PS +SCSI_Out__BSY__SHIFT EQU 6 +SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD_raw__MASK EQU 0x02 +SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1 +SCSI_Out__CD_raw__PORT EQU 0 +SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__CD_raw__SHIFT EQU 1 +SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x04 +SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2 +SCSI_Out__DBP_raw__PORT EQU 6 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS +SCSI_Out__DBP_raw__SHIFT EQU 2 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT4_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT4_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT4_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT4_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT4_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x01 +SCSI_Out__IO_raw__PC EQU CYREG_PRT4_PC0 +SCSI_Out__IO_raw__PORT EQU 4 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT4_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT4_PS +SCSI_Out__IO_raw__SHIFT EQU 0 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT4_SLW +SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__MSG_raw__MASK EQU 0x20 +SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5 +SCSI_Out__MSG_raw__PORT EQU 0 +SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__MSG_raw__SHIFT EQU 5 +SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT4_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT4_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__REQ__MASK EQU 0x02 +SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1 +SCSI_Out__REQ__PORT EQU 4 +SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT4_PS +SCSI_Out__REQ__SHIFT EQU 1 +SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW +SCSI_Out__RST__AG EQU CYREG_PRT0_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT0_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__RST__MASK EQU 0x80 +SCSI_Out__RST__PC EQU CYREG_PRT0_PC7 +SCSI_Out__RST__PORT EQU 0 +SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT0_PS +SCSI_Out__RST__SHIFT EQU 7 +SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x08 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 3 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW +SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 +SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 +SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3 +SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10 +SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4 +SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20 +SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5 +SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 +SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 +SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 +SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x80 +SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__0__PORT EQU 6 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__0__SHIFT EQU 7 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x20 +SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__1__PORT EQU 6 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__1__SHIFT EQU 5 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__2__PORT EQU 12 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x80 +SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__3__PORT EQU 2 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__3__SHIFT EQU 7 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x20 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 5 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x08 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 3 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x02 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 1 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x20 +SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__7__PORT EQU 15 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__7__SHIFT EQU 5 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x80 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__DB0__PORT EQU 6 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB0__SHIFT EQU 7 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x20 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB1__PORT EQU 6 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB1__SHIFT EQU 5 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__DB2__PORT EQU 12 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x80 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB3__PORT EQU 2 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB3__SHIFT EQU 7 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x20 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 5 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x08 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 3 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x02 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 1 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x20 +SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__DB7__PORT EQU 15 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__DB7__SHIFT EQU 5 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW + +/* SD_RX_DMA */ +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__NUMBEROF_TDS EQU 0 +SD_RX_DMA__PRIORITY EQU 0 +SD_RX_DMA__TERMIN_EN EQU 0 +SD_RX_DMA__TERMIN_SEL EQU 0 +SD_RX_DMA__TERMOUT0_EN EQU 1 +SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT1_EN EQU 0 +SD_RX_DMA__TERMOUT1_SEL EQU 0 +SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_TX_DMA */ +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__NUMBEROF_TDS EQU 0 +SD_TX_DMA__PRIORITY EQU 1 +SD_TX_DMA__TERMIN_EN EQU 0 +SD_TX_DMA__TERMIN_SEL EQU 0 +SD_TX_DMA__TERMOUT0_EN EQU 1 +SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT1_EN EQU 0 +SD_TX_DMA__TERMOUT1_SEL EQU 0 +SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Noise */ +SCSI_Noise__0__AG EQU CYREG_PRT4_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT4_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__0__MASK EQU 0x80 +SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__0__PORT EQU 4 +SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT4_PS +SCSI_Noise__0__SHIFT EQU 7 +SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__1__AG EQU CYREG_PRT4_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT4_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__1__MASK EQU 0x20 +SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__1__PORT EQU 4 +SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT4_PS +SCSI_Noise__1__SHIFT EQU 5 +SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__2__AG EQU CYREG_PRT0_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT0_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__2__MASK EQU 0x04 +SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__2__PORT EQU 0 +SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT0_PS +SCSI_Noise__2__SHIFT EQU 2 +SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__3__AG EQU CYREG_PRT0_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT0_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__3__PORT EQU 0 +SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT0_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__4__AG EQU CYREG_PRT4_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT4_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__4__MASK EQU 0x08 +SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__4__PORT EQU 4 +SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT4_PS +SCSI_Noise__4__SHIFT EQU 3 +SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x08 +SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__ACK__PORT EQU 4 +SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS +SCSI_Noise__ACK__SHIFT EQU 3 +SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x80 +SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__ATN__PORT EQU 4 +SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS +SCSI_Noise__ATN__SHIFT EQU 7 +SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x20 +SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__BSY__PORT EQU 4 +SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS +SCSI_Noise__BSY__SHIFT EQU 5 +SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT0_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT0_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__RST__PORT EQU 0 +SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT0_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x04 +SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__SEL__PORT EQU 0 +SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS +SCSI_Noise__SEL__SHIFT EQU 2 +SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW + +/* scsiTarget */ +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_StatusReg__0__MASK EQU 0x01 +scsiTarget_StatusReg__0__POS EQU 0 +scsiTarget_StatusReg__1__MASK EQU 0x02 +scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__2__MASK EQU 0x04 +scsiTarget_StatusReg__2__POS EQU 2 +scsiTarget_StatusReg__3__MASK EQU 0x08 +scsiTarget_StatusReg__3__POS EQU 3 +scsiTarget_StatusReg__4__MASK EQU 0x10 +scsiTarget_StatusReg__4__POS EQU 4 +scsiTarget_StatusReg__MASK EQU 0x1F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST + +/* Debug_Timer */ +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +/* SCSI_RX_DMA */ +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_TX_DMA */ +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SD_Data_Clk */ +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +/* SPI_Pullups */ +SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SPI_Pullups__0__MASK EQU 0x10 +SPI_Pullups__0__PC EQU CYREG_PRT3_PC4 +SPI_Pullups__0__PORT EQU 3 +SPI_Pullups__0__SHIFT EQU 4 +SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SPI_Pullups__1__MASK EQU 0x20 +SPI_Pullups__1__PC EQU CYREG_PRT3_PC5 +SPI_Pullups__1__PORT EQU 3 +SPI_Pullups__1__SHIFT EQU 5 +SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SPI_Pullups__2__MASK EQU 0x40 +SPI_Pullups__2__PC EQU CYREG_PRT3_PC6 +SPI_Pullups__2__PORT EQU 3 +SPI_Pullups__2__SHIFT EQU 6 +SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 +SPI_Pullups__3__MASK EQU 0x80 +SPI_Pullups__3__PC EQU CYREG_PRT3_PC7 +SPI_Pullups__3__PORT EQU 3 +SPI_Pullups__3__SHIFT EQU 7 +SPI_Pullups__AG EQU CYREG_PRT3_AG +SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX +SPI_Pullups__BIE EQU CYREG_PRT3_BIE +SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_Pullups__BYP EQU CYREG_PRT3_BYP +SPI_Pullups__CTL EQU CYREG_PRT3_CTL +SPI_Pullups__DM0 EQU CYREG_PRT3_DM0 +SPI_Pullups__DM1 EQU CYREG_PRT3_DM1 +SPI_Pullups__DM2 EQU CYREG_PRT3_DM2 +SPI_Pullups__DR EQU CYREG_PRT3_DR +SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_Pullups__MASK EQU 0xF0 +SPI_Pullups__PORT EQU 3 +SPI_Pullups__PRT EQU CYREG_PRT3_PRT +SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_Pullups__PS EQU CYREG_PRT3_PS +SPI_Pullups__SHIFT EQU 4 +SPI_Pullups__SLW EQU CYREG_PRT3_SLW +SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 +SPI_Pullups_1__0__MASK EQU 0x01 +SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0 +SPI_Pullups_1__0__PORT EQU 12 +SPI_Pullups_1__0__SHIFT EQU 0 +SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 +SPI_Pullups_1__1__MASK EQU 0x02 +SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1 +SPI_Pullups_1__1__PORT EQU 12 +SPI_Pullups_1__1__SHIFT EQU 1 +SPI_Pullups_1__AG EQU CYREG_PRT12_AG +SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE +SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP +SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0 +SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1 +SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2 +SPI_Pullups_1__DR EQU CYREG_PRT12_DR +SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS +SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SPI_Pullups_1__MASK EQU 0x03 +SPI_Pullups_1__PORT EQU 12 +SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT +SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SPI_Pullups_1__PS EQU CYREG_PRT12_PS +SPI_Pullups_1__SHIFT EQU 0 +SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW + +/* timer_clock */ +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 +timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 +timer_clock__INDEX EQU 0x02 +timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +timer_clock__PM_ACT_MSK EQU 0x04 +timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +timer_clock__PM_STBY_MSK EQU 0x04 + +/* SCSI_RST_ISR */ +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_SEL_ISR */ +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +/* SCSI_Filtered */ +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST + +/* SCSI_CTL_PHASE */ +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK + +/* SCSI_Glitch_Ctl */ +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK + +/* SCSI_Parity_Error */ +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST + +/* Miscellaneous */ +BCLK__BUS_CLK__HZ EQU 50000000 +BCLK__BUS_CLK__KHZ EQU 50000 +BCLK__BUS_CLK__MHZ EQU 50 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0400 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x1000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA EQU 5 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD EQU 5 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0 EQU 5 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1 EQU 5 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2 EQU 5 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3300 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3300 +CYIPBLOCK_ARM_CM3_VERSION EQU 0 +CYIPBLOCK_P3_ANAIF_VERSION EQU 0 +CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0 +CYIPBLOCK_P3_COMP_VERSION EQU 0 +CYIPBLOCK_P3_DMA_VERSION EQU 0 +CYIPBLOCK_P3_DRQ_VERSION EQU 0 +CYIPBLOCK_P3_EMIF_VERSION EQU 0 +CYIPBLOCK_P3_I2C_VERSION EQU 0 +CYIPBLOCK_P3_LCD_VERSION EQU 0 +CYIPBLOCK_P3_LPF_VERSION EQU 0 +CYIPBLOCK_P3_PM_VERSION EQU 0 +CYIPBLOCK_P3_TIMER_VERSION EQU 0 +CYIPBLOCK_P3_USB_VERSION EQU 0 +CYIPBLOCK_P3_VIDAC_VERSION EQU 0 +CYIPBLOCK_P3_VREF_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 0 +CYIPBLOCK_S8_IRQ_VERSION EQU 0 +CYIPBLOCK_S8_SAR_VERSION EQU 0 +CYIPBLOCK_S8_SIO_VERSION EQU 0 +CYIPBLOCK_S8_UDB_VERSION EQU 0 +DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +CYDEV_BOOTLOADER_ENABLE EQU 0 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc new file mode 100644 index 0000000..cd3a5eb --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -0,0 +1,2853 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; LED1 +LED1__0__INTTYPE EQU CYREG_PICU12_INTTYPE2 +LED1__0__MASK EQU 0x04 +LED1__0__PC EQU CYREG_PRT12_PC2 +LED1__0__PORT EQU 12 +LED1__0__SHIFT EQU 2 +LED1__1__INTTYPE EQU CYREG_PICU12_INTTYPE3 +LED1__1__MASK EQU 0x08 +LED1__1__PC EQU CYREG_PRT12_PC3 +LED1__1__PORT EQU 12 +LED1__1__SHIFT EQU 3 +LED1__AG EQU CYREG_PRT12_AG +LED1__BIE EQU CYREG_PRT12_BIE +LED1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +LED1__BYP EQU CYREG_PRT12_BYP +LED1__DM0 EQU CYREG_PRT12_DM0 +LED1__DM1 EQU CYREG_PRT12_DM1 +LED1__DM2 EQU CYREG_PRT12_DM2 +LED1__DR EQU CYREG_PRT12_DR +LED1__INP_DIS EQU CYREG_PRT12_INP_DIS +LED1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +LED1__MASK EQU 0x0C +LED1__PORT EQU 12 +LED1__PRT EQU CYREG_PRT12_PRT +LED1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +LED1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +LED1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +LED1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +LED1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +LED1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +LED1__PS EQU CYREG_PRT12_PS +LED1__SHIFT EQU 2 +LED1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +LED1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +LED1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +LED1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +LED1__SLW EQU CYREG_PRT12_SLW + +; SD_CS +SD_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_CS__0__MASK EQU 0x08 +SD_CS__0__PC EQU CYREG_PRT3_PC3 +SD_CS__0__PORT EQU 3 +SD_CS__0__SHIFT EQU 3 +SD_CS__AG EQU CYREG_PRT3_AG +SD_CS__AMUX EQU CYREG_PRT3_AMUX +SD_CS__BIE EQU CYREG_PRT3_BIE +SD_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_CS__BYP EQU CYREG_PRT3_BYP +SD_CS__CTL EQU CYREG_PRT3_CTL +SD_CS__DM0 EQU CYREG_PRT3_DM0 +SD_CS__DM1 EQU CYREG_PRT3_DM1 +SD_CS__DM2 EQU CYREG_PRT3_DM2 +SD_CS__DR EQU CYREG_PRT3_DR +SD_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_CS__MASK EQU 0x08 +SD_CS__PORT EQU 3 +SD_CS__PRT EQU CYREG_PRT3_PRT +SD_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_CS__PS EQU CYREG_PRT3_PS +SD_CS__SHIFT EQU 3 +SD_CS__SLW EQU CYREG_PRT3_SLW + +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 6 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x80 +USBFS_ep_1__INTC_NUMBER EQU 7 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_7 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x100 +USBFS_ep_2__INTC_NUMBER EQU 8 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_8 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_3__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_3__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_3__INTC_MASK EQU 0x200 +USBFS_ep_3__INTC_NUMBER EQU 9 +USBFS_ep_3__INTC_PRIOR_NUM EQU 7 +USBFS_ep_3__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_9 +USBFS_ep_3__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_3__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_4__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_4__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_4__INTC_MASK EQU 0x400 +USBFS_ep_4__INTC_NUMBER EQU 10 +USBFS_ep_4__INTC_PRIOR_NUM EQU 7 +USBFS_ep_4__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10 +USBFS_ep_4__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_4__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 + +; SDCard +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST +SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_RxStsReg__4__POS EQU 4 +SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20 +SDCard_BSPIM_RxStsReg__5__POS EQU 5 +SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 +SDCard_BSPIM_RxStsReg__6__POS EQU 6 +SDCard_BSPIM_RxStsReg__MASK EQU 0x70 +SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST +SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB04_05_D1 +SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL +SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB04_05_F0 +SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB04_05_F1 +SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB04_A0_A1 +SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB04_A0 +SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB04_A1 +SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB04_D0_D1 +SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB04_D0 +SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB04_D1 +SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL +SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 +SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 +SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 +SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL +SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 +SDCard_BSPIM_TxStsReg__0__POS EQU 0 +SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 +SDCard_BSPIM_TxStsReg__1__POS EQU 1 +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 +SDCard_BSPIM_TxStsReg__2__POS EQU 2 +SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 +SDCard_BSPIM_TxStsReg__3__POS EQU 3 +SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 +SDCard_BSPIM_TxStsReg__4__POS EQU 4 +SDCard_BSPIM_TxStsReg__MASK EQU 0x1F +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST + +; SD_SCK +SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_SCK__0__MASK EQU 0x02 +SD_SCK__0__PC EQU CYREG_PRT3_PC1 +SD_SCK__0__PORT EQU 3 +SD_SCK__0__SHIFT EQU 1 +SD_SCK__AG EQU CYREG_PRT3_AG +SD_SCK__AMUX EQU CYREG_PRT3_AMUX +SD_SCK__BIE EQU CYREG_PRT3_BIE +SD_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_SCK__BYP EQU CYREG_PRT3_BYP +SD_SCK__CTL EQU CYREG_PRT3_CTL +SD_SCK__DM0 EQU CYREG_PRT3_DM0 +SD_SCK__DM1 EQU CYREG_PRT3_DM1 +SD_SCK__DM2 EQU CYREG_PRT3_DM2 +SD_SCK__DR EQU CYREG_PRT3_DR +SD_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_SCK__MASK EQU 0x02 +SD_SCK__PORT EQU 3 +SD_SCK__PRT EQU CYREG_PRT3_PRT +SD_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_SCK__PS EQU CYREG_PRT3_PS +SD_SCK__SHIFT EQU 1 +SD_SCK__SLW EQU CYREG_PRT3_SLW + +; SCSI_In +SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 +SCSI_In__0__MASK EQU 0x02 +SCSI_In__0__PC EQU CYREG_PRT6_PC1 +SCSI_In__0__PORT EQU 6 +SCSI_In__0__SHIFT EQU 1 +SCSI_In__AG EQU CYREG_PRT6_AG +SCSI_In__AMUX EQU CYREG_PRT6_AMUX +SCSI_In__BIE EQU CYREG_PRT6_BIE +SCSI_In__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In__BYP EQU CYREG_PRT6_BYP +SCSI_In__CTL EQU CYREG_PRT6_CTL +SCSI_In__DBP__INTTYPE EQU CYREG_PICU6_INTTYPE1 +SCSI_In__DBP__MASK EQU 0x02 +SCSI_In__DBP__PC EQU CYREG_PRT6_PC1 +SCSI_In__DBP__PORT EQU 6 +SCSI_In__DBP__SHIFT EQU 1 +SCSI_In__DM0 EQU CYREG_PRT6_DM0 +SCSI_In__DM1 EQU CYREG_PRT6_DM1 +SCSI_In__DM2 EQU CYREG_PRT6_DM2 +SCSI_In__DR EQU CYREG_PRT6_DR +SCSI_In__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU6_BASE +SCSI_In__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In__MASK EQU 0x02 +SCSI_In__PORT EQU 6 +SCSI_In__PRT EQU CYREG_PRT6_PRT +SCSI_In__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In__PS EQU CYREG_PRT6_PS +SCSI_In__SHIFT EQU 1 +SCSI_In__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_In_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__0__MASK EQU 0x40 +SCSI_In_DBx__0__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__0__PORT EQU 6 +SCSI_In_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__0__SHIFT EQU 6 +SCSI_In_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_In_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__1__MASK EQU 0x10 +SCSI_In_DBx__1__PC EQU CYREG_PRT6_PC4 +SCSI_In_DBx__1__PORT EQU 6 +SCSI_In_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__1__SHIFT EQU 4 +SCSI_In_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE4 +SCSI_In_DBx__2__MASK EQU 0x10 +SCSI_In_DBx__2__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__2__PORT EQU 12 +SCSI_In_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__2__SHIFT EQU 4 +SCSI_In_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE6 +SCSI_In_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__3__MASK EQU 0x40 +SCSI_In_DBx__3__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__3__PORT EQU 2 +SCSI_In_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__3__SHIFT EQU 6 +SCSI_In_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE4 +SCSI_In_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__4__MASK EQU 0x10 +SCSI_In_DBx__4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__4__PORT EQU 2 +SCSI_In_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__4__SHIFT EQU 4 +SCSI_In_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE2 +SCSI_In_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__5__MASK EQU 0x04 +SCSI_In_DBx__5__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__5__PORT EQU 2 +SCSI_In_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__5__SHIFT EQU 2 +SCSI_In_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_In_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__6__MASK EQU 0x01 +SCSI_In_DBx__6__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__6__PORT EQU 2 +SCSI_In_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__6__SHIFT EQU 0 +SCSI_In_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__7__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__7__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__7__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__7__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__7__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__7__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__7__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__7__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__7__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__7__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__7__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__7__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_In_DBx__7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__7__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__7__MASK EQU 0x08 +SCSI_In_DBx__7__PC EQU CYREG_PRT6_PC3 +SCSI_In_DBx__7__PORT EQU 6 +SCSI_In_DBx__7__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__7__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__7__SHIFT EQU 3 +SCSI_In_DBx__7__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE6 +SCSI_In_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB0__MASK EQU 0x40 +SCSI_In_DBx__DB0__PC EQU CYREG_PRT6_PC6 +SCSI_In_DBx__DB0__PORT EQU 6 +SCSI_In_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB0__SHIFT EQU 6 +SCSI_In_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE4 +SCSI_In_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB1__MASK EQU 0x10 +SCSI_In_DBx__DB1__PC EQU CYREG_PRT6_PC4 +SCSI_In_DBx__DB1__PORT EQU 6 +SCSI_In_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB1__SHIFT EQU 4 +SCSI_In_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_In_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_In_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_In_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_In_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_In_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_In_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_In_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_In_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_In_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_In_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE4 +SCSI_In_DBx__DB2__MASK EQU 0x10 +SCSI_In_DBx__DB2__PC EQU CYREG_PRT12_PC4 +SCSI_In_DBx__DB2__PORT EQU 12 +SCSI_In_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_In_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_In_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_In_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_In_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_In_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_In_DBx__DB2__SHIFT EQU 4 +SCSI_In_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_In_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_In_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_In_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_In_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_In_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE6 +SCSI_In_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB3__MASK EQU 0x40 +SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC6 +SCSI_In_DBx__DB3__PORT EQU 2 +SCSI_In_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB3__SHIFT EQU 6 +SCSI_In_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE4 +SCSI_In_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB4__MASK EQU 0x10 +SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4 +SCSI_In_DBx__DB4__PORT EQU 2 +SCSI_In_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB4__SHIFT EQU 4 +SCSI_In_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE2 +SCSI_In_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB5__MASK EQU 0x04 +SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC2 +SCSI_In_DBx__DB5__PORT EQU 2 +SCSI_In_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB5__SHIFT EQU 2 +SCSI_In_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_In_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_In_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_In_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_In_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_In_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_In_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_In_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_In_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_In_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_In_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_In_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE0 +SCSI_In_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_In_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_In_DBx__DB6__MASK EQU 0x01 +SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC0 +SCSI_In_DBx__DB6__PORT EQU 2 +SCSI_In_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_In_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_In_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_In_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_In_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_In_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_In_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_In_DBx__DB6__SHIFT EQU 0 +SCSI_In_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_In_DBx__DB7__AG EQU CYREG_PRT6_AG +SCSI_In_DBx__DB7__AMUX EQU CYREG_PRT6_AMUX +SCSI_In_DBx__DB7__BIE EQU CYREG_PRT6_BIE +SCSI_In_DBx__DB7__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_In_DBx__DB7__BYP EQU CYREG_PRT6_BYP +SCSI_In_DBx__DB7__CTL EQU CYREG_PRT6_CTL +SCSI_In_DBx__DB7__DM0 EQU CYREG_PRT6_DM0 +SCSI_In_DBx__DB7__DM1 EQU CYREG_PRT6_DM1 +SCSI_In_DBx__DB7__DM2 EQU CYREG_PRT6_DM2 +SCSI_In_DBx__DB7__DR EQU CYREG_PRT6_DR +SCSI_In_DBx__DB7__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_In_DBx__DB7__INTTYPE EQU CYREG_PICU6_INTTYPE3 +SCSI_In_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_In_DBx__DB7__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_In_DBx__DB7__MASK EQU 0x08 +SCSI_In_DBx__DB7__PC EQU CYREG_PRT6_PC3 +SCSI_In_DBx__DB7__PORT EQU 6 +SCSI_In_DBx__DB7__PRT EQU CYREG_PRT6_PRT +SCSI_In_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_In_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_In_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_In_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_In_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_In_DBx__DB7__PS EQU CYREG_PRT6_PS +SCSI_In_DBx__DB7__SHIFT EQU 3 +SCSI_In_DBx__DB7__SLW EQU CYREG_PRT6_SLW + +; SD_MISO +SD_MISO__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_MISO__0__MASK EQU 0x01 +SD_MISO__0__PC EQU CYREG_PRT3_PC0 +SD_MISO__0__PORT EQU 3 +SD_MISO__0__SHIFT EQU 0 +SD_MISO__AG EQU CYREG_PRT3_AG +SD_MISO__AMUX EQU CYREG_PRT3_AMUX +SD_MISO__BIE EQU CYREG_PRT3_BIE +SD_MISO__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MISO__BYP EQU CYREG_PRT3_BYP +SD_MISO__CTL EQU CYREG_PRT3_CTL +SD_MISO__DM0 EQU CYREG_PRT3_DM0 +SD_MISO__DM1 EQU CYREG_PRT3_DM1 +SD_MISO__DM2 EQU CYREG_PRT3_DM2 +SD_MISO__DR EQU CYREG_PRT3_DR +SD_MISO__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MISO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MISO__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MISO__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MISO__MASK EQU 0x01 +SD_MISO__PORT EQU 3 +SD_MISO__PRT EQU CYREG_PRT3_PRT +SD_MISO__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MISO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MISO__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MISO__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MISO__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MISO__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MISO__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MISO__PS EQU CYREG_PRT3_PS +SD_MISO__SHIFT EQU 0 +SD_MISO__SLW EQU CYREG_PRT3_SLW + +; SD_MOSI +SD_MOSI__0__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_MOSI__0__MASK EQU 0x04 +SD_MOSI__0__PC EQU CYREG_PRT3_PC2 +SD_MOSI__0__PORT EQU 3 +SD_MOSI__0__SHIFT EQU 2 +SD_MOSI__AG EQU CYREG_PRT3_AG +SD_MOSI__AMUX EQU CYREG_PRT3_AMUX +SD_MOSI__BIE EQU CYREG_PRT3_BIE +SD_MOSI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_MOSI__BYP EQU CYREG_PRT3_BYP +SD_MOSI__CTL EQU CYREG_PRT3_CTL +SD_MOSI__DM0 EQU CYREG_PRT3_DM0 +SD_MOSI__DM1 EQU CYREG_PRT3_DM1 +SD_MOSI__DM2 EQU CYREG_PRT3_DM2 +SD_MOSI__DR EQU CYREG_PRT3_DR +SD_MOSI__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_MOSI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_MOSI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_MOSI__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_MOSI__MASK EQU 0x04 +SD_MOSI__PORT EQU 3 +SD_MOSI__PRT EQU CYREG_PRT3_PRT +SD_MOSI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_MOSI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_MOSI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_MOSI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_MOSI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_MOSI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_MOSI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_MOSI__PS EQU CYREG_PRT3_PS +SD_MOSI__SHIFT EQU 2 +SD_MOSI__SLW EQU CYREG_PRT3_SLW + +; TERM_EN +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +; SCSI_CLK +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 +SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SCSI_CLK__PM_STBY_MSK EQU 0x02 + +; SCSI_Out +SCSI_Out__0__AG EQU CYREG_PRT6_AG +SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__0__DR EQU CYREG_PRT6_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__0__MASK EQU 0x04 +SCSI_Out__0__PC EQU CYREG_PRT6_PC2 +SCSI_Out__0__PORT EQU 6 +SCSI_Out__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT6_PS +SCSI_Out__0__SHIFT EQU 2 +SCSI_Out__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out__1__AG EQU CYREG_PRT4_AG +SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT4_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT4_BYP +SCSI_Out__1__CTL EQU CYREG_PRT4_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__1__DR EQU CYREG_PRT4_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__1__MASK EQU 0x40 +SCSI_Out__1__PC EQU CYREG_PRT4_PC6 +SCSI_Out__1__PORT EQU 4 +SCSI_Out__1__PRT EQU CYREG_PRT4_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT4_PS +SCSI_Out__1__SHIFT EQU 6 +SCSI_Out__1__SLW EQU CYREG_PRT4_SLW +SCSI_Out__2__AG EQU CYREG_PRT0_AG +SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT0_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT0_BYP +SCSI_Out__2__CTL EQU CYREG_PRT0_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__2__DR EQU CYREG_PRT0_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__2__MASK EQU 0x80 +SCSI_Out__2__PC EQU CYREG_PRT0_PC7 +SCSI_Out__2__PORT EQU 0 +SCSI_Out__2__PRT EQU CYREG_PRT0_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT0_PS +SCSI_Out__2__SHIFT EQU 7 +SCSI_Out__2__SLW EQU CYREG_PRT0_SLW +SCSI_Out__3__AG EQU CYREG_PRT0_AG +SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT0_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT0_BYP +SCSI_Out__3__CTL EQU CYREG_PRT0_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__3__DR EQU CYREG_PRT0_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__3__MASK EQU 0x20 +SCSI_Out__3__PC EQU CYREG_PRT0_PC5 +SCSI_Out__3__PORT EQU 0 +SCSI_Out__3__PRT EQU CYREG_PRT0_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT0_PS +SCSI_Out__3__SHIFT EQU 5 +SCSI_Out__3__SLW EQU CYREG_PRT0_SLW +SCSI_Out__4__AG EQU CYREG_PRT0_AG +SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT0_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT0_BYP +SCSI_Out__4__CTL EQU CYREG_PRT0_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__4__DR EQU CYREG_PRT0_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__4__MASK EQU 0x08 +SCSI_Out__4__PC EQU CYREG_PRT0_PC3 +SCSI_Out__4__PORT EQU 0 +SCSI_Out__4__PRT EQU CYREG_PRT0_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT0_PS +SCSI_Out__4__SHIFT EQU 3 +SCSI_Out__4__SLW EQU CYREG_PRT0_SLW +SCSI_Out__5__AG EQU CYREG_PRT0_AG +SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT0_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT0_BYP +SCSI_Out__5__CTL EQU CYREG_PRT0_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__5__DR EQU CYREG_PRT0_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__5__MASK EQU 0x02 +SCSI_Out__5__PC EQU CYREG_PRT0_PC1 +SCSI_Out__5__PORT EQU 0 +SCSI_Out__5__PRT EQU CYREG_PRT0_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT0_PS +SCSI_Out__5__SHIFT EQU 1 +SCSI_Out__5__SLW EQU CYREG_PRT0_SLW +SCSI_Out__6__AG EQU CYREG_PRT4_AG +SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT4_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT4_BYP +SCSI_Out__6__CTL EQU CYREG_PRT4_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__6__DR EQU CYREG_PRT4_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__6__MASK EQU 0x02 +SCSI_Out__6__PC EQU CYREG_PRT4_PC1 +SCSI_Out__6__PORT EQU 4 +SCSI_Out__6__PRT EQU CYREG_PRT4_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT4_PS +SCSI_Out__6__SHIFT EQU 1 +SCSI_Out__6__SLW EQU CYREG_PRT4_SLW +SCSI_Out__7__AG EQU CYREG_PRT4_AG +SCSI_Out__7__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT4_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT4_BYP +SCSI_Out__7__CTL EQU CYREG_PRT4_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__7__DR EQU CYREG_PRT4_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__7__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__7__MASK EQU 0x01 +SCSI_Out__7__PC EQU CYREG_PRT4_PC0 +SCSI_Out__7__PORT EQU 4 +SCSI_Out__7__PRT EQU CYREG_PRT4_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT4_PS +SCSI_Out__7__SHIFT EQU 0 +SCSI_Out__7__SLW EQU CYREG_PRT4_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT4_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT4_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__BSY__MASK EQU 0x40 +SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6 +SCSI_Out__BSY__PORT EQU 4 +SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT4_PS +SCSI_Out__BSY__SHIFT EQU 6 +SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Out__CD_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__CD_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__CD_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD_raw__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__CD_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD_raw__MASK EQU 0x02 +SCSI_Out__CD_raw__PC EQU CYREG_PRT0_PC1 +SCSI_Out__CD_raw__PORT EQU 0 +SCSI_Out__CD_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__CD_raw__SHIFT EQU 1 +SCSI_Out__CD_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x04 +SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2 +SCSI_Out__DBP_raw__PORT EQU 6 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS +SCSI_Out__DBP_raw__SHIFT EQU 2 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT4_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT4_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT4_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT4_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT4_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x01 +SCSI_Out__IO_raw__PC EQU CYREG_PRT4_PC0 +SCSI_Out__IO_raw__PORT EQU 4 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT4_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT4_PS +SCSI_Out__IO_raw__SHIFT EQU 0 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT4_SLW +SCSI_Out__MSG_raw__AG EQU CYREG_PRT0_AG +SCSI_Out__MSG_raw__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__MSG_raw__BIE EQU CYREG_PRT0_BIE +SCSI_Out__MSG_raw__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__MSG_raw__BYP EQU CYREG_PRT0_BYP +SCSI_Out__MSG_raw__CTL EQU CYREG_PRT0_CTL +SCSI_Out__MSG_raw__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__MSG_raw__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__MSG_raw__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__MSG_raw__DR EQU CYREG_PRT0_DR +SCSI_Out__MSG_raw__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__MSG_raw__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__MSG_raw__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__MSG_raw__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__MSG_raw__MASK EQU 0x20 +SCSI_Out__MSG_raw__PC EQU CYREG_PRT0_PC5 +SCSI_Out__MSG_raw__PORT EQU 0 +SCSI_Out__MSG_raw__PRT EQU CYREG_PRT0_PRT +SCSI_Out__MSG_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__MSG_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__MSG_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__MSG_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__MSG_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__MSG_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__MSG_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__MSG_raw__PS EQU CYREG_PRT0_PS +SCSI_Out__MSG_raw__SHIFT EQU 5 +SCSI_Out__MSG_raw__SLW EQU CYREG_PRT0_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT4_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT4_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__REQ__MASK EQU 0x02 +SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1 +SCSI_Out__REQ__PORT EQU 4 +SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT4_PS +SCSI_Out__REQ__SHIFT EQU 1 +SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW +SCSI_Out__RST__AG EQU CYREG_PRT0_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT0_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__RST__MASK EQU 0x80 +SCSI_Out__RST__PC EQU CYREG_PRT0_PC7 +SCSI_Out__RST__PORT EQU 0 +SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT0_PS +SCSI_Out__RST__SHIFT EQU 7 +SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x08 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 3 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW +SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 +SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 +SCSI_Out_Bits_Sync_ctrl_reg__3__POS EQU 3 +SCSI_Out_Bits_Sync_ctrl_reg__4__MASK EQU 0x10 +SCSI_Out_Bits_Sync_ctrl_reg__4__POS EQU 4 +SCSI_Out_Bits_Sync_ctrl_reg__5__MASK EQU 0x20 +SCSI_Out_Bits_Sync_ctrl_reg__5__POS EQU 5 +SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 +SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 +SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 +SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x80 +SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__0__PORT EQU 6 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__0__SHIFT EQU 7 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x20 +SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__1__PORT EQU 6 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__1__SHIFT EQU 5 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__2__PORT EQU 12 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x80 +SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__3__PORT EQU 2 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__3__SHIFT EQU 7 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x20 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 5 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x08 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 3 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x02 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 1 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x20 +SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__7__PORT EQU 15 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__7__SHIFT EQU 5 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x80 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__DB0__PORT EQU 6 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB0__SHIFT EQU 7 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x20 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB1__PORT EQU 6 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB1__SHIFT EQU 5 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__DB2__PORT EQU 12 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x80 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB3__PORT EQU 2 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB3__SHIFT EQU 7 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x20 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 5 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x08 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 3 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x02 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 1 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x20 +SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__DB7__PORT EQU 15 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__DB7__SHIFT EQU 5 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW + +; SD_RX_DMA +SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_RX_DMA__DRQ_NUMBER EQU 2 +SD_RX_DMA__NUMBEROF_TDS EQU 0 +SD_RX_DMA__PRIORITY EQU 0 +SD_RX_DMA__TERMIN_EN EQU 0 +SD_RX_DMA__TERMIN_SEL EQU 0 +SD_RX_DMA__TERMOUT0_EN EQU 1 +SD_RX_DMA__TERMOUT0_SEL EQU 2 +SD_RX_DMA__TERMOUT1_EN EQU 0 +SD_RX_DMA__TERMOUT1_SEL EQU 0 +SD_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_RX_DMA_COMPLETE__INTC_MASK EQU 0x20 +SD_RX_DMA_COMPLETE__INTC_NUMBER EQU 5 +SD_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_5 +SD_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_TX_DMA +SD_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SD_TX_DMA__DRQ_NUMBER EQU 3 +SD_TX_DMA__NUMBEROF_TDS EQU 0 +SD_TX_DMA__PRIORITY EQU 1 +SD_TX_DMA__TERMIN_EN EQU 0 +SD_TX_DMA__TERMIN_SEL EQU 0 +SD_TX_DMA__TERMOUT0_EN EQU 1 +SD_TX_DMA__TERMOUT0_SEL EQU 3 +SD_TX_DMA__TERMOUT1_EN EQU 0 +SD_TX_DMA__TERMOUT1_SEL EQU 0 +SD_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SD_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SD_TX_DMA_COMPLETE__INTC_MASK EQU 0x40 +SD_TX_DMA_COMPLETE__INTC_NUMBER EQU 6 +SD_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 +SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Noise +SCSI_Noise__0__AG EQU CYREG_PRT4_AG +SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__0__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__0__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__0__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__0__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__0__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__0__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__0__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__0__DR EQU CYREG_PRT4_DR +SCSI_Noise__0__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__0__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__0__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__0__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__0__MASK EQU 0x80 +SCSI_Noise__0__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__0__PORT EQU 4 +SCSI_Noise__0__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__0__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__0__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__0__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__0__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__0__PS EQU CYREG_PRT4_PS +SCSI_Noise__0__SHIFT EQU 7 +SCSI_Noise__0__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__1__AG EQU CYREG_PRT4_AG +SCSI_Noise__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__1__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__1__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__1__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__1__DR EQU CYREG_PRT4_DR +SCSI_Noise__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__1__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__1__MASK EQU 0x20 +SCSI_Noise__1__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__1__PORT EQU 4 +SCSI_Noise__1__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__1__PS EQU CYREG_PRT4_PS +SCSI_Noise__1__SHIFT EQU 5 +SCSI_Noise__1__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__2__AG EQU CYREG_PRT0_AG +SCSI_Noise__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__2__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__2__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__2__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__2__DR EQU CYREG_PRT0_DR +SCSI_Noise__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__2__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__2__MASK EQU 0x04 +SCSI_Noise__2__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__2__PORT EQU 0 +SCSI_Noise__2__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__2__PS EQU CYREG_PRT0_PS +SCSI_Noise__2__SHIFT EQU 2 +SCSI_Noise__2__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__3__AG EQU CYREG_PRT0_AG +SCSI_Noise__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__3__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__3__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__3__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__3__DR EQU CYREG_PRT0_DR +SCSI_Noise__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__3__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__3__MASK EQU 0x40 +SCSI_Noise__3__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__3__PORT EQU 0 +SCSI_Noise__3__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__3__PS EQU CYREG_PRT0_PS +SCSI_Noise__3__SHIFT EQU 6 +SCSI_Noise__3__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__4__AG EQU CYREG_PRT4_AG +SCSI_Noise__4__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__4__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__4__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__4__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__4__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__4__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__4__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__4__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__4__DR EQU CYREG_PRT4_DR +SCSI_Noise__4__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__4__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__4__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__4__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__4__MASK EQU 0x08 +SCSI_Noise__4__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__4__PORT EQU 4 +SCSI_Noise__4__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__4__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__4__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__4__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__4__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__4__PS EQU CYREG_PRT4_PS +SCSI_Noise__4__SHIFT EQU 3 +SCSI_Noise__4__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ACK__AG EQU CYREG_PRT4_AG +SCSI_Noise__ACK__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ACK__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ACK__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ACK__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ACK__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ACK__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ACK__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ACK__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ACK__DR EQU CYREG_PRT4_DR +SCSI_Noise__ACK__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ACK__INTTYPE EQU CYREG_PICU4_INTTYPE3 +SCSI_Noise__ACK__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ACK__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ACK__MASK EQU 0x08 +SCSI_Noise__ACK__PC EQU CYREG_PRT4_PC3 +SCSI_Noise__ACK__PORT EQU 4 +SCSI_Noise__ACK__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ACK__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ACK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ACK__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ACK__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ACK__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ACK__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ACK__PS EQU CYREG_PRT4_PS +SCSI_Noise__ACK__SHIFT EQU 3 +SCSI_Noise__ACK__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__ATN__AG EQU CYREG_PRT4_AG +SCSI_Noise__ATN__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__ATN__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__ATN__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__ATN__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__ATN__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__ATN__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__ATN__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__ATN__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__ATN__DR EQU CYREG_PRT4_DR +SCSI_Noise__ATN__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__ATN__INTTYPE EQU CYREG_PICU4_INTTYPE7 +SCSI_Noise__ATN__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__ATN__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__ATN__MASK EQU 0x80 +SCSI_Noise__ATN__PC EQU CYREG_PRT4_PC7 +SCSI_Noise__ATN__PORT EQU 4 +SCSI_Noise__ATN__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__ATN__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__ATN__PS EQU CYREG_PRT4_PS +SCSI_Noise__ATN__SHIFT EQU 7 +SCSI_Noise__ATN__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__BSY__AG EQU CYREG_PRT4_AG +SCSI_Noise__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Noise__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Noise__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Noise__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Noise__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Noise__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Noise__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Noise__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Noise__BSY__DR EQU CYREG_PRT4_DR +SCSI_Noise__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Noise__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE5 +SCSI_Noise__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Noise__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Noise__BSY__MASK EQU 0x20 +SCSI_Noise__BSY__PC EQU CYREG_PRT4_PC5 +SCSI_Noise__BSY__PORT EQU 4 +SCSI_Noise__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Noise__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Noise__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Noise__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Noise__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Noise__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Noise__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Noise__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Noise__BSY__PS EQU CYREG_PRT4_PS +SCSI_Noise__BSY__SHIFT EQU 5 +SCSI_Noise__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Noise__RST__AG EQU CYREG_PRT0_AG +SCSI_Noise__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__RST__DR EQU CYREG_PRT0_DR +SCSI_Noise__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__RST__INTTYPE EQU CYREG_PICU0_INTTYPE6 +SCSI_Noise__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__RST__MASK EQU 0x40 +SCSI_Noise__RST__PC EQU CYREG_PRT0_PC6 +SCSI_Noise__RST__PORT EQU 0 +SCSI_Noise__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__RST__PS EQU CYREG_PRT0_PS +SCSI_Noise__RST__SHIFT EQU 6 +SCSI_Noise__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Noise__SEL__AG EQU CYREG_PRT0_AG +SCSI_Noise__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Noise__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Noise__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Noise__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Noise__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Noise__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Noise__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Noise__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Noise__SEL__DR EQU CYREG_PRT0_DR +SCSI_Noise__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Noise__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE2 +SCSI_Noise__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Noise__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Noise__SEL__MASK EQU 0x04 +SCSI_Noise__SEL__PC EQU CYREG_PRT0_PC2 +SCSI_Noise__SEL__PORT EQU 0 +SCSI_Noise__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Noise__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Noise__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Noise__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Noise__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Noise__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Noise__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Noise__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Noise__SEL__PS EQU CYREG_PRT0_PS +SCSI_Noise__SEL__SHIFT EQU 2 +SCSI_Noise__SEL__SLW EQU CYREG_PRT0_SLW + +; scsiTarget +scsiTarget_datapath__16BIT_A0_REG EQU CYREG_B0_UDB00_01_A0 +scsiTarget_datapath__16BIT_A1_REG EQU CYREG_B0_UDB00_01_A1 +scsiTarget_datapath__16BIT_D0_REG EQU CYREG_B0_UDB00_01_D0 +scsiTarget_datapath__16BIT_D1_REG EQU CYREG_B0_UDB00_01_D1 +scsiTarget_datapath__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath__16BIT_F0_REG EQU CYREG_B0_UDB00_01_F0 +scsiTarget_datapath__16BIT_F1_REG EQU CYREG_B0_UDB00_01_F1 +scsiTarget_datapath__A0_A1_REG EQU CYREG_B0_UDB00_A0_A1 +scsiTarget_datapath__A0_REG EQU CYREG_B0_UDB00_A0 +scsiTarget_datapath__A1_REG EQU CYREG_B0_UDB00_A1 +scsiTarget_datapath__D0_D1_REG EQU CYREG_B0_UDB00_D0_D1 +scsiTarget_datapath__D0_REG EQU CYREG_B0_UDB00_D0 +scsiTarget_datapath__D1_REG EQU CYREG_B0_UDB00_D1 +scsiTarget_datapath__DP_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath__F0_F1_REG EQU CYREG_B0_UDB00_F0_F1 +scsiTarget_datapath__F0_REG EQU CYREG_B0_UDB00_F0 +scsiTarget_datapath__F1_REG EQU CYREG_B0_UDB00_F1 +scsiTarget_datapath__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PI__16BIT_STATUS_REG EQU CYREG_B0_UDB00_01_ST +scsiTarget_datapath_PI__MASK_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_datapath_PI__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PI__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PI__STATUS_CNT_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_CONTROL_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PI__STATUS_REG EQU CYREG_B0_UDB00_ST +scsiTarget_datapath_PO__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_01_ACTL +scsiTarget_datapath_PO__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB00_01_CTL +scsiTarget_datapath_PO__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB00_01_MSK +scsiTarget_datapath_PO__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB00_ACTL +scsiTarget_datapath_PO__CONTROL_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__CONTROL_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__COUNT_REG EQU CYREG_B0_UDB00_CTL +scsiTarget_datapath_PO__COUNT_ST_REG EQU CYREG_B0_UDB00_ST_CTL +scsiTarget_datapath_PO__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB00_MSK_ACTL +scsiTarget_datapath_PO__PERIOD_REG EQU CYREG_B0_UDB00_MSK +scsiTarget_StatusReg__0__MASK EQU 0x01 +scsiTarget_StatusReg__0__POS EQU 0 +scsiTarget_StatusReg__1__MASK EQU 0x02 +scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__2__MASK EQU 0x04 +scsiTarget_StatusReg__2__POS EQU 2 +scsiTarget_StatusReg__3__MASK EQU 0x08 +scsiTarget_StatusReg__3__POS EQU 3 +scsiTarget_StatusReg__4__MASK EQU 0x10 +scsiTarget_StatusReg__4__POS EQU 4 +scsiTarget_StatusReg__MASK EQU 0x1F +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST + +; Debug_Timer +Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +Debug_Timer_Interrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +Debug_Timer_Interrupt__INTC_MASK EQU 0x01 +Debug_Timer_Interrupt__INTC_NUMBER EQU 0 +Debug_Timer_Interrupt__INTC_PRIOR_NUM EQU 7 +Debug_Timer_Interrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +Debug_Timer_Interrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +Debug_Timer_Interrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +Debug_Timer_TimerHW__CAP0 EQU CYREG_TMR0_CAP0 +Debug_Timer_TimerHW__CAP1 EQU CYREG_TMR0_CAP1 +Debug_Timer_TimerHW__CFG0 EQU CYREG_TMR0_CFG0 +Debug_Timer_TimerHW__CFG1 EQU CYREG_TMR0_CFG1 +Debug_Timer_TimerHW__CFG2 EQU CYREG_TMR0_CFG2 +Debug_Timer_TimerHW__CNT_CMP0 EQU CYREG_TMR0_CNT_CMP0 +Debug_Timer_TimerHW__CNT_CMP1 EQU CYREG_TMR0_CNT_CMP1 +Debug_Timer_TimerHW__PER0 EQU CYREG_TMR0_PER0 +Debug_Timer_TimerHW__PER1 EQU CYREG_TMR0_PER1 +Debug_Timer_TimerHW__PM_ACT_CFG EQU CYREG_PM_ACT_CFG3 +Debug_Timer_TimerHW__PM_ACT_MSK EQU 0x01 +Debug_Timer_TimerHW__PM_STBY_CFG EQU CYREG_PM_STBY_CFG3 +Debug_Timer_TimerHW__PM_STBY_MSK EQU 0x01 +Debug_Timer_TimerHW__RT0 EQU CYREG_TMR0_RT0 +Debug_Timer_TimerHW__RT1 EQU CYREG_TMR0_RT1 +Debug_Timer_TimerHW__SR0 EQU CYREG_TMR0_SR0 + +; SCSI_RX_DMA +SCSI_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_RX_DMA__DRQ_NUMBER EQU 0 +SCSI_RX_DMA__NUMBEROF_TDS EQU 0 +SCSI_RX_DMA__PRIORITY EQU 2 +SCSI_RX_DMA__TERMIN_EN EQU 0 +SCSI_RX_DMA__TERMIN_SEL EQU 0 +SCSI_RX_DMA__TERMOUT0_EN EQU 1 +SCSI_RX_DMA__TERMOUT0_SEL EQU 0 +SCSI_RX_DMA__TERMOUT1_EN EQU 0 +SCSI_RX_DMA__TERMOUT1_SEL EQU 0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RX_DMA_COMPLETE__INTC_MASK EQU 0x04 +SCSI_RX_DMA_COMPLETE__INTC_NUMBER EQU 2 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_RX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_2 +SCSI_RX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_TX_DMA +SCSI_TX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 +SCSI_TX_DMA__DRQ_NUMBER EQU 1 +SCSI_TX_DMA__NUMBEROF_TDS EQU 0 +SCSI_TX_DMA__PRIORITY EQU 2 +SCSI_TX_DMA__TERMIN_EN EQU 0 +SCSI_TX_DMA__TERMIN_SEL EQU 0 +SCSI_TX_DMA__TERMOUT0_EN EQU 1 +SCSI_TX_DMA__TERMOUT0_SEL EQU 1 +SCSI_TX_DMA__TERMOUT1_EN EQU 0 +SCSI_TX_DMA__TERMOUT1_SEL EQU 0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_TX_DMA_COMPLETE__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_TX_DMA_COMPLETE__INTC_MASK EQU 0x10 +SCSI_TX_DMA_COMPLETE__INTC_NUMBER EQU 4 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_NUM EQU 7 +SCSI_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_4 +SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SD_Data_Clk +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 +SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +SD_Data_Clk__PM_STBY_MSK EQU 0x01 + +; SPI_Pullups +SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SPI_Pullups__0__MASK EQU 0x10 +SPI_Pullups__0__PC EQU CYREG_PRT3_PC4 +SPI_Pullups__0__PORT EQU 3 +SPI_Pullups__0__SHIFT EQU 4 +SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SPI_Pullups__1__MASK EQU 0x20 +SPI_Pullups__1__PC EQU CYREG_PRT3_PC5 +SPI_Pullups__1__PORT EQU 3 +SPI_Pullups__1__SHIFT EQU 5 +SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SPI_Pullups__2__MASK EQU 0x40 +SPI_Pullups__2__PC EQU CYREG_PRT3_PC6 +SPI_Pullups__2__PORT EQU 3 +SPI_Pullups__2__SHIFT EQU 6 +SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 +SPI_Pullups__3__MASK EQU 0x80 +SPI_Pullups__3__PC EQU CYREG_PRT3_PC7 +SPI_Pullups__3__PORT EQU 3 +SPI_Pullups__3__SHIFT EQU 7 +SPI_Pullups__AG EQU CYREG_PRT3_AG +SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX +SPI_Pullups__BIE EQU CYREG_PRT3_BIE +SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_Pullups__BYP EQU CYREG_PRT3_BYP +SPI_Pullups__CTL EQU CYREG_PRT3_CTL +SPI_Pullups__DM0 EQU CYREG_PRT3_DM0 +SPI_Pullups__DM1 EQU CYREG_PRT3_DM1 +SPI_Pullups__DM2 EQU CYREG_PRT3_DM2 +SPI_Pullups__DR EQU CYREG_PRT3_DR +SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_Pullups__MASK EQU 0xF0 +SPI_Pullups__PORT EQU 3 +SPI_Pullups__PRT EQU CYREG_PRT3_PRT +SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_Pullups__PS EQU CYREG_PRT3_PS +SPI_Pullups__SHIFT EQU 4 +SPI_Pullups__SLW EQU CYREG_PRT3_SLW +SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 +SPI_Pullups_1__0__MASK EQU 0x01 +SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0 +SPI_Pullups_1__0__PORT EQU 12 +SPI_Pullups_1__0__SHIFT EQU 0 +SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 +SPI_Pullups_1__1__MASK EQU 0x02 +SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1 +SPI_Pullups_1__1__PORT EQU 12 +SPI_Pullups_1__1__SHIFT EQU 1 +SPI_Pullups_1__AG EQU CYREG_PRT12_AG +SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE +SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP +SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0 +SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1 +SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2 +SPI_Pullups_1__DR EQU CYREG_PRT12_DR +SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS +SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SPI_Pullups_1__MASK EQU 0x03 +SPI_Pullups_1__PORT EQU 12 +SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT +SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SPI_Pullups_1__PS EQU CYREG_PRT12_PS +SPI_Pullups_1__SHIFT EQU 0 +SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW + +; timer_clock +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 +timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 +timer_clock__INDEX EQU 0x02 +timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +timer_clock__PM_ACT_MSK EQU 0x04 +timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +timer_clock__PM_STBY_MSK EQU 0x04 + +; SCSI_RST_ISR +SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_RST_ISR__INTC_MASK EQU 0x02 +SCSI_RST_ISR__INTC_NUMBER EQU 1 +SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_SEL_ISR +SCSI_SEL_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +SCSI_SEL_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +SCSI_SEL_ISR__INTC_MASK EQU 0x08 +SCSI_SEL_ISR__INTC_NUMBER EQU 3 +SCSI_SEL_ISR__INTC_PRIOR_NUM EQU 7 +SCSI_SEL_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_3 +SCSI_SEL_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +SCSI_SEL_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 + +; SCSI_Filtered +SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Filtered_sts_sts_reg__0__POS EQU 0 +SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 +SCSI_Filtered_sts_sts_reg__1__POS EQU 1 +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 +SCSI_Filtered_sts_sts_reg__2__POS EQU 2 +SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 +SCSI_Filtered_sts_sts_reg__3__POS EQU 3 +SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 +SCSI_Filtered_sts_sts_reg__4__POS EQU 4 +SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST + +; SCSI_CTL_PHASE +SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 +SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 +SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK + +; SCSI_Glitch_Ctl +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK + +; SCSI_Parity_Error +SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST + +; Miscellaneous +BCLK__BUS_CLK__HZ EQU 50000000 +BCLK__BUS_CLK__KHZ EQU 50000 +BCLK__BUS_CLK__MHZ EQU 50 +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 0 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0400 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x0000007F +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 2 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x1000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA EQU 5 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD EQU 5 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0 EQU 5 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1 EQU 5 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2 EQU 5 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3300 +CYDEV_VIO0 EQU 5 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1 EQU 5 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2 EQU 5 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3300 +CYIPBLOCK_ARM_CM3_VERSION EQU 0 +CYIPBLOCK_P3_ANAIF_VERSION EQU 0 +CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0 +CYIPBLOCK_P3_COMP_VERSION EQU 0 +CYIPBLOCK_P3_DMA_VERSION EQU 0 +CYIPBLOCK_P3_DRQ_VERSION EQU 0 +CYIPBLOCK_P3_EMIF_VERSION EQU 0 +CYIPBLOCK_P3_I2C_VERSION EQU 0 +CYIPBLOCK_P3_LCD_VERSION EQU 0 +CYIPBLOCK_P3_LPF_VERSION EQU 0 +CYIPBLOCK_P3_PM_VERSION EQU 0 +CYIPBLOCK_P3_TIMER_VERSION EQU 0 +CYIPBLOCK_P3_USB_VERSION EQU 0 +CYIPBLOCK_P3_VIDAC_VERSION EQU 0 +CYIPBLOCK_P3_VREF_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 0 +CYIPBLOCK_S8_IRQ_VERSION EQU 0 +CYIPBLOCK_S8_SAR_VERSION EQU 0 +CYIPBLOCK_S8_SIO_VERSION EQU 0 +CYIPBLOCK_S8_UDB_VERSION EQU 0 +DMA_CHANNELS_USED__MASK0 EQU 0x0000000F +CYDEV_BOOTLOADER_ENABLE EQU 0 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c new file mode 100644 index 0000000..82ddcb0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.2 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_LOADABLE_META_SECTION +#define CY_LOADABLE_META_SECTION __attribute__ ((__section__(".cyloadablemeta"), used)) +#endif +CY_LOADABLE_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyloadablemeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_loadable[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x5Cu, 0xD1u, 0x20u, 0x05u, + 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CONFIG_ECC_SECTION +#define CY_CONFIG_ECC_SECTION __attribute__ ((__section__(".cyconfigecc"), used)) +#endif +CY_CONFIG_ECC_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyconfigecc" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_configecc[] = { + 0x00u +}; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h new file mode 100644 index 0000000..17f1452 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h @@ -0,0 +1,311 @@ +/***************************************************************************//** +* \file cypins.h +* \version 5.50 +* +* \brief This file contains the function prototypes and constants used for a +* port/pin in access and control. +* +* \note Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +****************************************************************************//** +* +* Reads the current value on the pin (pin state, PS). +* +* \param pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* \return +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +****************************************************************************//** +* +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +****************************************************************************//** +* +* This macro sets the state of the specified pin to 0. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +****************************************************************************//** +* +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* \param mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +****************************************************************************//** +* +* Reads the drive mode for the pin (DM). +* +* \param pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* \return +* mode: The current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +****************************************************************************//** +* +* Set the slew rate for the pin to fast the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +****************************************************************************//** +* +* Set the slew rate for the pin to slow the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* \param pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* \param in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h new file mode 100644 index 0000000..3207d1a --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h @@ -0,0 +1,1414 @@ +/***************************************************************************//** +* \file cytypes.h +* \version 5.50 +* +* \brief CyTypes provides register access macros and approved types for use in +* firmware. +* +* \note Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + +#ifdef CYDEV_CHIP_MEMBER_4M + #define CY_PSOC4_4100M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) + #define CY_PSOC4_4200M (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4M) +#else + #define CY_PSOC4_4100M (0u != 0u) + #define CY_PSOC4_4200M (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4M */ + +#ifdef CYDEV_CHIP_MEMBER_4H + #define CY_PSOC4_4200D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4H) +#else + #define CY_PSOC4_4200D (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4H */ + +#ifdef CYDEV_CHIP_MEMBER_4L + #define CY_PSOC4_4200L (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4L) +#else + #define CY_PSOC4_4200L (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4L */ + +#ifdef CYDEV_CHIP_MEMBER_4U + #define CY_PSOC4_4000U (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4U) +#else + #define CY_PSOC4_4000U (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4U */ + +#ifdef CYDEV_CHIP_MEMBER_4J + #define CY_PSOC4_4000S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4J) +#else + #define CY_PSOC4_4000S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4J */ + +#ifdef CYDEV_CHIP_MEMBER_4K + #define CY_PSOC4_4100S (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4K) +#else + #define CY_PSOC4_4100S (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4K */ + + +#define CY_IP_HOBTO_DEVICE (!(0 == 1)) + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_SRSSV2 (0 != 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0 == 0) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSSV3 (0 == 1) + #define CY_IP_CPUSSV2 (0 == 1) + #define CY_IP_CPUSS (0 == 1) + #else + #define CY_IP_CPUSSV3 (0 != 0) + #define CY_IP_CPUSSV2 (0 != 0) + #define CY_IP_CPUSS (0 == 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* CM0 present or CM0+ present (1=CM0, 0=CM0+) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_CPUSS_CM0 (0 == 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_CPUSS_CM0 (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #define CY_IP_CPUSS_CM0PLUS (!CY_IP_CPUSS_CM0) + #else + #define CY_IP_CPUSS_CM0 (0 == 0) + #define CY_IP_CPUSS_CM0PLUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash memory present or not (1=Flash present, 0=Flash not present) */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_CPUSS_FLASHC_PRESENT (0 == 0) + #else + #define CY_IP_CPUSS_FLASHC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FM (-1 == 0) + #define CY_IP_FMLT (-1 == 1) + #define CY_IP_FS (-1 == 2) + #define CY_IP_FSLT (-1 == 3) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #define CY_IP_FMLT (0 != 0) /* FLASH-Lite */ + #define CY_IP_FS (0 != 0) /* FS */ + #define CY_IP_FSLT (0 != 0) /* FSLT */ + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Enable simultaneous execution/programming in multi-macro devices */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_PARALLEL_PGM_EN (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_PARALLEL_PGM_EN (0u != 0u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_FLASH_MACROS (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_FLASH_MACROS (1u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_INT_NR (-1u) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_INT_NR (-1u) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_INT_NR (32u) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Presence of the BLESS IP block */ + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_BLESS (0 != 0) + #else + #define CY_IP_BLESS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_USBDEV (0 != 0) + #else + #define CY_IP_USBDEV (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /*************************************************************************** + * Devices with the SPCIF_SYNCHRONOUS parameter set to one will not use + * the 36MHz Oscillator for Flash operation. Instead, flash write function + * ensures that the charge pump clock and the higher frequency clock (HFCLK) + * are set to the IMO at 48MHz prior to writing the flash. + ***************************************************************************/ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #else /* CY_IP_CPUSSV3 */ + #define CY_IP_SPCIF_SYNCHRONOUS (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SPCIF_SYNCHRONOUS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_WCO_BLESS (0 == 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 == 1) + #define CY_IP_WCO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_WCO_BLESS (0 != 0) + #define CY_IP_WCO_WCO (0 != 0) + #define CY_IP_WCO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_WCO (CY_IP_WCO_BLESS || CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + + + /* PLL is present */ + #if (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) + #define CY_IP_PLL ((-1 != 0) || \ + (-1 != 0)) + + #define CY_IP_PLL_NR (-1u + \ + -1u) + #else + #define CY_IP_PLL (0 != 0) + #define CY_IP_PLL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE && CY_IP_SRSSV2) */ + + + /* External Crystal Oscillator is present (high frequency) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_BLESS) + #define CY_IP_ECO_BLESS (0 == 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_SRSSV2 (-1 == 1) + #endif /* (CY_IP_BLESS) */ + #else + #define CY_IP_ECO_BLESS (0 != 0) + #define CY_IP_ECO_SRSSV2 (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #define CY_IP_ECO (CY_IP_ECO_BLESS || CY_IP_ECO_SRSSV2) + + + /* Clock Source clk_lf implemented in SysTick Counter. When 0, not implemented, 1=implemented */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #else /* CY_IP_CPUSSV3 */ + #define CY_SYSTICK_LFCLK_SOURCE (-1 != 0) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + /* Flash Macro 0 has extra rows */ + #if (CY_IP_HOBTO_DEVICE) + #ifdef CYREG_SFLASH_MACRO_0_FREE_SFLASH0 + #define CY_SFLASH_XTRA_ROWS (0 == 0) + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* CYREG_SFLASH_MACRO_0_FREE_SFLASH0 */ + + #else + #define CY_SFLASH_XTRA_ROWS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + #if (CY_IP_USBDEV) + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_USB (0 != 0) + #endif /* (CY_IP_USBDEV) */ + + + #if (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 == 0) + #else + #define CY_IP_IMO_TRIMMABLE_BY_WCO (0 != 0) + #endif /* (CY_IP_WCO_WCO || CY_IP_WCO_SRSSV2) */ + + + /* DW/DMA Controller present (0=No, 1=Yes) */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_DMAC_PRESENT (-1 == 1) + #else + #define CY_IP_DMAC_PRESENT (-1 == 1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_DMAC_PRESENT (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + #if (CY_IP_HOBTO_DEVICE) + #define CY_IP_PASS (0 == 1) + #else + #define CY_IP_PASS (0 != 0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + + + + /* Number of external slave ports on System Interconnect */ + #if (CY_IP_HOBTO_DEVICE) + #if (CY_IP_CPUSSV2) + #define CY_IP_SL_NR (-1) + #else + #define CY_IP_SL_NR (-1) + #endif /* (CY_IP_CPUSSV2) */ + #else + #define CY_IP_SL_NR (0) + #endif /* (CY_IP_HOBTO_DEVICE) */ + +#else + + #if (CY_PSOC3) + #define CY_SYSTICK_LFCLK_SOURCE (0 != 0) + #else /* PSoC 5LP */ + #define CY_SYSTICK_LFCLK_SOURCE (0 == 0) + #endif /* (CY_PSOC3) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_5_0 (500u) +#define CY_BOOT_5_10 (510u) +#define CY_BOOT_5_20 (520u) +#define CY_BOOT_5_30 (530u) +#define CY_BOOT_5_40 (540u) +#define CY_BOOT_VERSION (CY_BOOT_5_40) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +#define CY_M_PI (3.14159265358979323846264338327) + + +/** +* \addtogroup group_register_access +A library of macros provides read and write access to the registers of the device. These macros are used with the +defined values made available in the generated cydevice_trm.h and cyfitter.h files. Access to registers should be made +using these macros and not the functions that are used to implement the macros. This allows for device independent code +generation. + +The PSoC 4 processor architecture use little endian ordering. + +SRAM and Flash storage in all architectures is done using the endianness of the architecture and compilers. However, +the registers in all these chips are laid out in little endian order. These macros allow register accesses to match this +little endian ordering. If you perform operations on multi-byte registers without using these macros, you must consider +the byte ordering of the specific architecture. Examples include usage of DMA to transfer between memory and registers, +as well as function calls that are passed an array of bytes in memory. + +The PSoC 4 requires these accesses to be aligned to the width of the transaction. + +The PSoC 4 requires peripheral register accesses to match the hardware register size. Otherwise, the peripheral might +ignore the transfer and Hard Fault exception will be generated. + +*/ + +/** @} group_register_access */ + + +/** +* \addtogroup group_register_access_macros Register Access +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC3) + /******************************************************************************* + * Macro Name: CY_GET_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG8(addr) + ****************************************************************************//** + * + * Reads the 8-bit value from the specified register. + * Identical to \ref CY_GET_REG8 for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG8(addr, value) + ****************************************************************************//** + * + * Writes the 8-bit value to the specified register. + * Identical to \ref CY_SET_REG8 for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG16(addr) + ****************************************************************************//** + * + * Reads the 16-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG16(addr, value) + ****************************************************************************//** + * + * Writes the 16-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG16 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG24(addr) + ****************************************************************************//** + * + * Reads the 24-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG24(addr, value) + ****************************************************************************//** + * + * Writes the 24-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG24 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + + /******************************************************************************* + * Macro Name: CY_GET_XTND_REG32(addr) + ****************************************************************************//** + * + * Reads the 32-bit value from the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_GET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * + * \return Read value. + * + *******************************************************************************/ + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + + + /******************************************************************************* + * Macro Name: CY_SET_XTND_REG32(addr, value) + ****************************************************************************//** + * + * Writes the 32-bit value to the specified register. This macro implements the + * byte swapping required for proper operation. Identical to \ref CY_SET_REG32 + * for PSoC 4. + * + * \param reg Register address. + * \param value Value to write. + * + *******************************************************************************/ + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ +/** @} group_register_access_macros */ + + +/** +* \addtogroup group_register_access_bits Bit Manipulation +* \ingroup group_register_access +* @{ +*/ + +#if(CY_PSOC4) + + /******************************************************************************* + * Macro Name: CY_GET_FIELD_MASK(regSize, bitFieldName) + ****************************************************************************//** + * + * Returns the bit field mask for the specified register size and bit field + * name. + * + * \param regSize Size of the register in bits. + * \param bitFieldName Fully qualified name of the bit field. The biFieldName + * is automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * \return Returns the bit mask. + * + *******************************************************************************/ + #define CY_GET_FIELD_MASK(regSize, bitFieldName) \ + ((((uint ## regSize) 0xFFFFFFFFu << ((uint32)(regSize) - bitFieldName ## __SIZE - bitFieldName ## __OFFSET)) >>\ + ((uint32)(regSize) - bitFieldName ## __SIZE)) << bitFieldName ## __OFFSET) + + + /******************************************************************************* + * Macro Name: CY_GET_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register will remain uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on 32-bit and 16-bit width registers will generate a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG8_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG8((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG8_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 8-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers, generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG8_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG8((registerName), \ + ((CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)) | \ + (((uint8)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG8_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 8-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hard fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG8_FIELD(registerName, bitFieldName) \ + (CY_SET_REG8((registerName), (CY_GET_REG8((registerName)) & ~CY_GET_FIELD_MASK(8, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write + * operation performed by two threads (main and interrupt threads). To + * guarantee data integrity in such cases, the macro should be invoked while + * the specific interrupt is disabled or within a critical section (all + * interrupts are disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a + * hardfault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the + * possible values the field can take, please, refer to a respective PSoC + * family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG16_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG16((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG16_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 16-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerNam The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family + * register TRM. + * + *******************************************************************************/ + #define CY_SET_REG16_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG16((registerName), \ + ((CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)) | \ + (((uint16)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG16_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 16-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 32-bit and 16-bit width registers generates a hard + * fault exception. Examples of 8-bit registers are the UDB registers. + * + * \param registerName: The fully qualified name of the PSoC 4 device register. + * \param bitFieldName: fully qualified name of the bit field. The biFieldName is + * automatically appended with __OFFSET and __SIZE by the macro for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG16_FIELD(registerName, bitFieldName)\ + (CY_SET_REG16((registerName), (CY_GET_REG16((registerName)) & ~CY_GET_FIELD_MASK(16, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The Fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields, please, refer to + * a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, otherwise. + * The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_REG32_FIELD(registerName, bitFieldName) \ + ((CY_GET_REG32((registerName)) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_REG32_FIELD(registerName, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value of the specified 32-bit register to the + * required value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_SET_REG32_FIELD(registerName, bitFieldName, value) \ + CY_SET_REG32((registerName), \ + ((CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)) | \ + (((uint32)(value) << bitFieldName ## __OFFSET) & CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_CLEAR_REG32_FIELD(registerName, bitFieldName) + ****************************************************************************//** + * + * Clears the specified bit field of the specified 32-bit register. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * Using this macro on the 16-bit and 8-bit width registers generates a hard + * fault exception. + * + * \param registerName The fully qualified name of the PSoC 4 device register. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the register and bit fields and the possible + * values the field can take, please, refer to a respective PSoC family register + * TRM. + * + *******************************************************************************/ + #define CY_CLEAR_REG32_FIELD(registerName, bitFieldName) \ + (CY_SET_REG32((registerName), (CY_GET_REG32((registerName)) & ~CY_GET_FIELD_MASK(32, bitFieldName)))) + + + /******************************************************************************* + * Macro Name: CY_GET_FIELD(regValue, bitFieldName) + ****************************************************************************//** + * + * Reads the specified bit field value from the given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to a respective PSoC family register TRM. + * + * \return Zero if the specified bit field is zero, and a non-zero value, + * otherwise. The return value is of type uint32. + * + *******************************************************************************/ + #define CY_GET_FIELD(regValue, bitFieldName) \ + (((regValue) >> bitFieldName ## __OFFSET) & (~(0xFFFFFFFFu << bitFieldName ## __SIZE))) + + + /******************************************************************************* + * Macro Name: CY_SET_FIELD(regValue, bitFieldName, value) + ****************************************************************************//** + * + * Sets the specified bit field value within a given 32-bit value. + * + * The macro operation is not atomic. It is not guaranteed that the shared + * register remains uncorrupted during simultaneous read-modify-write operation + * performed by two threads (main and interrupt threads). To guarantee data + * integrity in such cases, the macro should be invoked while the specific + * interrupt is disabled or within a critical section (all interrupts are + * disabled). + * + * This macro has to be used in conjunction with \ref CY_GET_REG32 for atomic + * reads and \ref CY_SET_REG32 for atomic writes. + * + * \param regValue The value as read by \ref CY_GET_REG32. + * \param bitFieldName The fully qualified name of the bit field. The + * biFieldName is automatically appended with __OFFSET and __SIZE by the macro + * for usage. + * \param value The value that the field must be configured for. + * + * For fully qualified names of the bit field and the possible values the field + * can take, please, refer to the respective PSoC family register TRM. + * + *******************************************************************************/ + #define CY_SET_FIELD(regValue, bitFieldName, value) \ + ((regValue) = \ + ((((uint32)(value) & (~(0xFFFFFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET)) | \ + ((uint32)(regValue) & (((~(0xFFu << bitFieldName ## __SIZE))) << bitFieldName ## __OFFSET))) + +#endif /* (CY_PSOC4) */ + +/** @} group_register_access_bits */ + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)((((x) >> 24) & 0x000000FFu) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | (((x) >> 8) & 0x00FFu))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 5.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_IP_S8FS CY_IP_FS + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c new file mode 100644 index 0000000..21c2b8b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c @@ -0,0 +1,77 @@ +/***************************************************************************//** +* \file cyutils.c +* \version 5.50 +* +* \brief Provides a function to handle 24-bit value writes. +* +******************************************************************************** +* \copyright +* Copyright 2008-2016, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + ************************************************************************//** + * + * Writes a 24-bit value to the specified register. + * + * \param add The address where data must be written. + * \param value The data that must be written. + * + * Reentrant: + * No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + ************************************************************************//** + * + * Reads the 24-bit value from the specified register. + * + * \param addr : the address where data must be read. + * + * Reentrant: + * No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/exported_symbols.txt b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/exported_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h new file mode 100644 index 0000000..e00c8c0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -0,0 +1,92 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.2 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "cyfitter_cfg.h" +#include "cydevice.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cydisabledsheets.h" +#include "SCSI_In_DBx_aliases.h" +#include "SCSI_Out_DBx_aliases.h" +#include "SD_Data_Clk.h" +#include "SCSI_CTL_PHASE.h" +#include "SCSI_In_aliases.h" +#include "SCSI_In.h" +#include "SCSI_Out_aliases.h" +#include "CFG_EEPROM.h" +#include "SD_CS_aliases.h" +#include "SD_CS.h" +#include "SD_SCK_aliases.h" +#include "SD_SCK.h" +#include "SD_MOSI_aliases.h" +#include "SD_MOSI.h" +#include "SCSI_CLK.h" +#include "SCSI_Noise_aliases.h" +#include "SCSI_RST_ISR.h" +#include "LED1_aliases.h" +#include "LED1.h" +#include "SDCard.h" +#include "SDCard_PVT.h" +#include "SD_MISO_aliases.h" +#include "SD_MISO.h" +#include "USBFS.h" +#include "USBFS_audio.h" +#include "USBFS_cdc.h" +#include "USBFS_hid.h" +#include "USBFS_midi.h" +#include "USBFS_pvt.h" +#include "USBFS_cydmac.h" +#include "USBFS_msc.h" +#include "Bootloadable_1.h" +#include "SCSI_Out_Bits.h" +#include "SCSI_Out_Ctl.h" +#include "Debug_Timer.h" +#include "timer_clock.h" +#include "Debug_Timer_Interrupt.h" +#include "SCSI_TX_DMA_dma.h" +#include "SCSI_TX_DMA_COMPLETE.h" +#include "SD_RX_DMA_dma.h" +#include "SD_TX_DMA_dma.h" +#include "SD_RX_DMA_COMPLETE.h" +#include "SD_TX_DMA_COMPLETE.h" +#include "SCSI_RX_DMA_dma.h" +#include "SCSI_RX_DMA_COMPLETE.h" +#include "SCSI_Parity_Error.h" +#include "SCSI_Filtered.h" +#include "SCSI_SEL_ISR.h" +#include "SCSI_Glitch_Ctl.h" +#include "TERM_EN_aliases.h" +#include "TERM_EN.h" +#include "SPI_Pullups_aliases.h" +#include "SPI_Pullups.h" +#include "SPI_Pullups_1_aliases.h" +#include "SPI_Pullups_1.h" +#include "USBFS_Dm_aliases.h" +#include "USBFS_Dm.h" +#include "USBFS_Dp_aliases.h" +#include "USBFS_Dp.h" +#include "core_cm3_psoc5.h" +#include "CyDmac.h" +#include "CyFlash.h" +#include "CyLib.h" +#include "cypins.h" +#include "cyPm.h" +#include "CySpc.h" +#include "cytypes.h" +#include "cy_em_eeprom.h" + +/*[]*/ + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex new file mode 100644 index 0000000..deab42f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/protect.hex @@ -0,0 +1,3 @@ +:4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0 +:400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080 +:00000001FF diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/renamed_symbols.txt b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/renamed_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c new file mode 100644 index 0000000..8172794 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: timer_clock.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "timer_clock.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: timer_clock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_Start(void) +{ + /* Set the bit to enable the clock. */ + timer_clock_CLKEN |= timer_clock_CLKEN_MASK; + timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: timer_clock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_Stop(void) +{ + /* Clear the bit to disable the clock. */ + timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK); + timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: timer_clock_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_StopBlock(void) +{ + if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(timer_clock__CFG3) + CLK_DIST_AMASK = timer_clock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = timer_clock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* timer_clock__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(timer_clock_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK); + timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(timer_clock_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: timer_clock_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_StandbyPower(uint8 state) +{ + if(state == 0u) + { + timer_clock_CLKSTBY &= (uint8)(~timer_clock_CLKSTBY_MASK); + } + else + { + timer_clock_CLKSTBY |= timer_clock_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: timer_clock_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = timer_clock_GetSourceRegister(); + uint16 oldDivider = timer_clock_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = timer_clock_CLKEN & timer_clock_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(timer_clock_DIV_PTR, clkDivider); + timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + timer_clock_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(timer_clock_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(timer_clock__CFG3) + CLK_DIST_AMASK = timer_clock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = timer_clock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* timer_clock__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((timer_clock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + timer_clock_CLKEN &= (uint8)(~timer_clock_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((timer_clock_CLKEN & timer_clock_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(timer_clock_DIV_PTR, clkDivider); + timer_clock_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: timer_clock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 timer_clock_GetDividerRegister(void) +{ + return CY_GET_REG16(timer_clock_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: timer_clock_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_SetModeRegister(uint8 modeBitMask) +{ + timer_clock_MOD_SRC |= modeBitMask & (uint8)timer_clock_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: timer_clock_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_ClearModeRegister(uint8 modeBitMask) +{ + timer_clock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(timer_clock_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: timer_clock_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 timer_clock_GetModeRegister(void) +{ + return timer_clock_MOD_SRC & (uint8)(timer_clock_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: timer_clock_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = timer_clock_GetDividerRegister(); + uint8 oldSrc = timer_clock_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + timer_clock_MOD_SRC |= CYCLK_SSS; + timer_clock_MOD_SRC = + (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + timer_clock_MOD_SRC = + (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource; + timer_clock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + timer_clock_MOD_SRC = + (timer_clock_MOD_SRC & (uint8)(~timer_clock_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: timer_clock_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 timer_clock_GetSourceRegister(void) +{ + return timer_clock_MOD_SRC & timer_clock_SRC_SEL_MSK; +} + + +#if defined(timer_clock__CFG3) + + +/******************************************************************************* +* Function Name: timer_clock_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void timer_clock_SetPhaseRegister(uint8 clkPhase) +{ + timer_clock_PHASE = clkPhase & timer_clock_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: timer_clock_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 timer_clock_GetPhaseRegister(void) +{ + return timer_clock_PHASE & timer_clock_PHASE_MASK; +} + +#endif /* timer_clock__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h new file mode 100644 index 0000000..7fbbb4c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/timer_clock.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: timer_clock.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_timer_clock_H) +#define CY_CLOCK_timer_clock_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void timer_clock_Start(void) ; +void timer_clock_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void timer_clock_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void timer_clock_StandbyPower(uint8 state) ; +void timer_clock_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 timer_clock_GetDividerRegister(void) ; +void timer_clock_SetModeRegister(uint8 modeBitMask) ; +void timer_clock_ClearModeRegister(uint8 modeBitMask) ; +uint8 timer_clock_GetModeRegister(void) ; +void timer_clock_SetSourceRegister(uint8 clkSource) ; +uint8 timer_clock_GetSourceRegister(void) ; +#if defined(timer_clock__CFG3) +void timer_clock_SetPhaseRegister(uint8 clkPhase) ; +uint8 timer_clock_GetPhaseRegister(void) ; +#endif /* defined(timer_clock__CFG3) */ + +#define timer_clock_Enable() timer_clock_Start() +#define timer_clock_Disable() timer_clock_Stop() +#define timer_clock_SetDivider(clkDivider) timer_clock_SetDividerRegister(clkDivider, 1u) +#define timer_clock_SetDividerValue(clkDivider) timer_clock_SetDividerRegister((clkDivider) - 1u, 1u) +#define timer_clock_SetMode(clkMode) timer_clock_SetModeRegister(clkMode) +#define timer_clock_SetSource(clkSource) timer_clock_SetSourceRegister(clkSource) +#if defined(timer_clock__CFG3) +#define timer_clock_SetPhase(clkPhase) timer_clock_SetPhaseRegister(clkPhase) +#define timer_clock_SetPhaseValue(clkPhase) timer_clock_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(timer_clock__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define timer_clock_CLKEN (* (reg8 *) timer_clock__PM_ACT_CFG) +#define timer_clock_CLKEN_PTR ((reg8 *) timer_clock__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define timer_clock_CLKSTBY (* (reg8 *) timer_clock__PM_STBY_CFG) +#define timer_clock_CLKSTBY_PTR ((reg8 *) timer_clock__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define timer_clock_DIV_LSB (* (reg8 *) timer_clock__CFG0) +#define timer_clock_DIV_LSB_PTR ((reg8 *) timer_clock__CFG0) +#define timer_clock_DIV_PTR ((reg16 *) timer_clock__CFG0) + +/* Clock MSB divider configuration register. */ +#define timer_clock_DIV_MSB (* (reg8 *) timer_clock__CFG1) +#define timer_clock_DIV_MSB_PTR ((reg8 *) timer_clock__CFG1) + +/* Mode and source configuration register */ +#define timer_clock_MOD_SRC (* (reg8 *) timer_clock__CFG2) +#define timer_clock_MOD_SRC_PTR ((reg8 *) timer_clock__CFG2) + +#if defined(timer_clock__CFG3) +/* Analog clock phase configuration register */ +#define timer_clock_PHASE (* (reg8 *) timer_clock__CFG3) +#define timer_clock_PHASE_PTR ((reg8 *) timer_clock__CFG3) +#endif /* defined(timer_clock__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define timer_clock_CLKEN_MASK timer_clock__PM_ACT_MSK +#define timer_clock_CLKSTBY_MASK timer_clock__PM_STBY_MSK + +/* CFG2 field masks */ +#define timer_clock_SRC_SEL_MSK timer_clock__CFG2_SRC_SEL_MASK +#define timer_clock_MODE_MASK (~(timer_clock_SRC_SEL_MSK)) + +#if defined(timer_clock__CFG3) +/* CFG3 phase mask */ +#define timer_clock_PHASE_MASK timer_clock__CFG3_PHASE_DLY_MASK +#endif /* defined(timer_clock__CFG3) */ + +#endif /* CY_CLOCK_timer_clock_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml new file mode 100644 index 0000000..5cdfca1 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -0,0 +1,258 @@ + + + + + + + + + + + + + + + + + + + + + + SCSI2SD.svd + + + .\Generated_Source\PSoC5\cm3gcc.ld + .\Generated_Source\PSoC5\Cm3RealView.scat + .\Generated_Source\PSoC5\Cm3Iar.icf + + + + + ..\..\src\main.c + ..\..\src\diagnostic.c + ..\..\src\disk.c + ..\..\src\geometry.c + ..\..\src\inquiry.c + ..\..\src\mode.c + ..\..\src\scsi.c + ..\..\src\scsiPhy.c + ..\..\src\bits.c + ..\..\src\sd.c + ..\..\src\config.c + ..\..\src\led.c + ..\..\src\time.c + ..\..\src\hidpacket.c + ..\..\src\cdrom.c + ..\..\src\diagnostic.h + ..\..\src\disk.h + ..\..\src\geometry.h + ..\..\src\inquiry.h + ..\..\src\led.h + ..\..\src\mode.h + ..\..\src\scsi.h + ..\..\src\scsiPhy.h + ..\..\src\sense.h + ..\..\src\bits.h + ..\..\src\sd.h + ..\..\src\config.h + ..\..\src\time.h + ..\..\src\cdrom.h + + + + + .\device.h + + + + + ..\..\..\include\scsi2sd.h + ..\..\..\include\hidpacket.h + + + + + .\Generated_Source\PSoC5\cyfitter_cfg.h + .\Generated_Source\PSoC5\cyfitter_cfg.c + .\Generated_Source\PSoC5\cybootloader.c + .\Generated_Source\PSoC5\cymetadata.c + .\Generated_Source\PSoC5\cydevice.h + .\Generated_Source\PSoC5\cydevicegnu.inc + .\Generated_Source\PSoC5\cydevicerv.inc + .\Generated_Source\PSoC5\cydeviceiar.inc + .\Generated_Source\PSoC5\cydevice_trm.h + .\Generated_Source\PSoC5\cydevicegnu_trm.inc + .\Generated_Source\PSoC5\cydevicerv_trm.inc + .\Generated_Source\PSoC5\cydeviceiar_trm.inc + .\Generated_Source\PSoC5\cyfittergnu.inc + .\Generated_Source\PSoC5\cyfitterrv.inc + .\Generated_Source\PSoC5\cyfitteriar.inc + .\Generated_Source\PSoC5\cyfitter.h + .\Generated_Source\PSoC5\cydisabledsheets.h + .\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h + .\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h + .\Generated_Source\PSoC5\SD_Data_Clk.c + .\Generated_Source\PSoC5\SD_Data_Clk.h + .\Generated_Source\PSoC5\SD_CD_aliases.h + .\Generated_Source\PSoC5\SD_CD.c + .\Generated_Source\PSoC5\SD_CD.h + .\Generated_Source\PSoC5\SCSI_In_aliases.h + .\Generated_Source\PSoC5\SCSI_Out_aliases.h + .\Generated_Source\PSoC5\CFG_EEPROM.c + .\Generated_Source\PSoC5\CFG_EEPROM.h + .\Generated_Source\PSoC5\SD_CS_aliases.h + .\Generated_Source\PSoC5\SD_CS.c + .\Generated_Source\PSoC5\SD_CS.h + .\Generated_Source\PSoC5\SD_SCK_aliases.h + .\Generated_Source\PSoC5\SD_SCK.c + .\Generated_Source\PSoC5\SD_SCK.h + .\Generated_Source\PSoC5\SD_MOSI_aliases.h + .\Generated_Source\PSoC5\SD_MOSI.c + .\Generated_Source\PSoC5\SD_MOSI.h + .\Generated_Source\PSoC5\SCSI_RST_ISR.c + .\Generated_Source\PSoC5\SCSI_RST_ISR.h + .\Generated_Source\PSoC5\LED1_aliases.h + .\Generated_Source\PSoC5\LED1.c + .\Generated_Source\PSoC5\LED1.h + .\Generated_Source\PSoC5\SDCard.c + .\Generated_Source\PSoC5\SDCard.h + .\Generated_Source\PSoC5\SDCard_PM.c + .\Generated_Source\PSoC5\SDCard_INT.c + .\Generated_Source\PSoC5\SDCard_PVT.h + .\Generated_Source\PSoC5\SD_MISO_aliases.h + .\Generated_Source\PSoC5\SD_MISO.c + .\Generated_Source\PSoC5\SD_MISO.h + .\Generated_Source\PSoC5\USBFS.c + .\Generated_Source\PSoC5\USBFS.h + .\Generated_Source\PSoC5\USBFS_audio.c + .\Generated_Source\PSoC5\USBFS_audio.h + .\Generated_Source\PSoC5\USBFS_boot.c + .\Generated_Source\PSoC5\USBFS_cdc.c + .\Generated_Source\PSoC5\USBFS_cdc.h + .\Generated_Source\PSoC5\USBFS_cls.c + .\Generated_Source\PSoC5\USBFS_descr.c + .\Generated_Source\PSoC5\USBFS_drv.c + .\Generated_Source\PSoC5\USBFS_episr.c + .\Generated_Source\PSoC5\USBFS_hid.c + .\Generated_Source\PSoC5\USBFS_hid.h + .\Generated_Source\PSoC5\USBFS_pm.c + .\Generated_Source\PSoC5\USBFS_std.c + .\Generated_Source\PSoC5\USBFS_vnd.c + .\Generated_Source\PSoC5\USBFS_midi.c + .\Generated_Source\PSoC5\USBFS_midi.h + .\Generated_Source\PSoC5\USBFS_pvt.h + .\Generated_Source\PSoC5\Bootloadable_1.c + .\Generated_Source\PSoC5\Bootloadable_1.h + .\Generated_Source\PSoC5\USBFS_Dm_aliases.h + .\Generated_Source\PSoC5\USBFS_Dm.c + .\Generated_Source\PSoC5\USBFS_Dm.h + .\Generated_Source\PSoC5\USBFS_Dp_aliases.h + .\Generated_Source\PSoC5\USBFS_Dp.c + .\Generated_Source\PSoC5\USBFS_Dp.h + .\Generated_Source\PSoC5\Cm3Start.c + .\Generated_Source\PSoC5\core_cm3_psoc5.h + .\Generated_Source\PSoC5\core_cm3.h + .\Generated_Source\PSoC5\CyBootAsmGnu.s + .\Generated_Source\PSoC5\CyBootAsmRv.s + .\Generated_Source\PSoC5\CyDmac.c + .\Generated_Source\PSoC5\CyDmac.h + .\Generated_Source\PSoC5\CyFlash.c + .\Generated_Source\PSoC5\CyFlash.h + .\Generated_Source\PSoC5\CyLib.c + .\Generated_Source\PSoC5\CyLib.h + .\Generated_Source\PSoC5\cypins.h + .\Generated_Source\PSoC5\cyPm.c + .\Generated_Source\PSoC5\cyPm.h + .\Generated_Source\PSoC5\CySpc.c + .\Generated_Source\PSoC5\CySpc.h + .\Generated_Source\PSoC5\cytypes.h + .\Generated_Source\PSoC5\cyutils.c + .\Generated_Source\PSoC5\core_cmFunc.h + .\Generated_Source\PSoC5\core_cmInstr.h + .\Generated_Source\PSoC5\CyBootAsmIar.s + .\Generated_Source\PSoC5\project.h + .\Generated_Source\PSoC5\SD_TX_DMA_dma.c + .\Generated_Source\PSoC5\SD_TX_DMA_dma.h + .\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SD_RX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SD_RX_DMA_dma.c + .\Generated_Source\PSoC5\SD_RX_DMA_dma.h + .\Generated_Source\PSoC5\SCSI_CTL_PHASE.c + .\Generated_Source\PSoC5\SCSI_CTL_PHASE.h + .\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SD_TX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SCSI_TX_DMA_dma.c + .\Generated_Source\PSoC5\SCSI_TX_DMA_dma.h + .\Generated_Source\PSoC5\SCSI_RX_DMA_dma.c + .\Generated_Source\PSoC5\SCSI_RX_DMA_dma.h + .\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SCSI_TX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.c + .\Generated_Source\PSoC5\SCSI_RX_DMA_COMPLETE.h + .\Generated_Source\PSoC5\SCSI_Out_Bits.c + .\Generated_Source\PSoC5\SCSI_Out_Bits.h + .\Generated_Source\PSoC5\SCSI_Out_Ctl.c + .\Generated_Source\PSoC5\SCSI_Out_Ctl.h + .\Generated_Source\PSoC5\Debug_Timer.c + .\Generated_Source\PSoC5\Debug_Timer.h + .\Generated_Source\PSoC5\Debug_Timer_PM.c + .\Generated_Source\PSoC5\timer_clock.c + .\Generated_Source\PSoC5\timer_clock.h + .\Generated_Source\PSoC5\Debug_Timer_Interrupt.c + .\Generated_Source\PSoC5\Debug_Timer_Interrupt.h + .\Generated_Source\PSoC5\EXTLED_aliases.h + .\Generated_Source\PSoC5\EXTLED.c + .\Generated_Source\PSoC5\EXTLED.h + .\Generated_Source\PSoC5\SCSI_Parity_Error.c + .\Generated_Source\PSoC5\SCSI_Parity_Error.h + .\Generated_Source\PSoC5\SCSI_CLK.c + .\Generated_Source\PSoC5\SCSI_CLK.h + .\Generated_Source\PSoC5\SCSI_Noise_aliases.h + .\Generated_Source\PSoC5\SCSI_Filtered.c + .\Generated_Source\PSoC5\SCSI_Filtered.h + .\Generated_Source\PSoC5\prebuild.bat + .\Generated_Source\PSoC5\postbuild.bat + .\Generated_Source\PSoC5\CyElfTool.exe + .\Generated_Source\PSoC5\libelf.dll + + + + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.cysym b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.cysym new file mode 100644 index 0000000..b715b18 Binary files /dev/null and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.cysym differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.v b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.v new file mode 100644 index 0000000..a260222 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/OddParityGen/OddParityGen.v @@ -0,0 +1,44 @@ + +//`#start header` -- edit after this line, do not edit this line +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +`include "cypress.v" +//`#end` -- edit above this line, do not edit this line +// Generated on 10/15/2013 at 22:01 +// Component: OddParityGen +module OddParityGen ( + output DBP, + input [7:0] DBx, + input EN +); + +//`#start body` -- edit after this line, do not edit this line + + // For some reason the "simple" implementation uses up about 34% of all + // PLD resources on a PSoC 5LP + // 1 ^ DBx[0] ^ DBx[1] ^ DBx[2] ^ DBx[3] ^ DBx[4] ^ DBx[5] ^ DBx[6] ^ DBx[7] + + // Breaking the expression up into parts seems to use much less resources. + wire tmp = 1 ^ DBx[0]; + wire tmpa = DBx[1] ^ DBx[2]; + wire tmpb = DBx[3] ^ DBx[4]; + wire tmpc = DBx[5] ^ DBx[6] ^ DBx[7]; + assign DBP = EN ? tmp ^ tmpa ^ tmpb ^ tmpc : 0; +//`#end` -- edit above this line, do not edit this line +endmodule +//`#start footer` -- edit after this line, do not edit this line +//`#end` -- edit above this line, do not edit this line diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx new file mode 100644 index 0000000..0fb7619 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -0,0 +1,1047 @@ + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr new file mode 100644 index 0000000..47e0e7f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr @@ -0,0 +1,3951 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + SCSI_Parity_Error + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Parity_Error_STATUS_REG + No description available + 0x4000646E + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_MASK_REG + No description available + 0x4000648E + 8 + read-write + 0 + 0 + + + SCSI_Parity_Error_STATUS_AUX_CTL_REG + No description available + 0x4000649E + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + SCSI_Glitch_Ctl + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Glitch_Ctl_CONTROL_REG + No description available + 0x40006473 + 8 + read-write + 0 + 0 + + + + + SCSI_CTL_PHASE + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_CTL_PHASE_CONTROL_REG + No description available + 0x4000647F + 8 + read-write + 0 + 0 + + + + + Debug_Timer + No description available + 0x0 + + 0 + 0x0 + registers + + + + Debug_Timer_GLOBAL_ENABLE + PM.ACT.CFG + 0x400043A3 + 8 + read-write + 0 + 0 + + + en_timer + Enable timer/counters. + 0 + 3 + read-write + + + + + Debug_Timer_CONTROL + TMRx.CFG0 + 0x40004F00 + 8 + read-write + 0 + 0 + + + EN + Enables timer/comparator. + 0 + 0 + read-write + + + MODE + Mode. (0 = Timer; 1 = Comparator) + 1 + 1 + read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + + + + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. + 2 + 2 + read-write + + + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. + 3 + 3 + read-write + + + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write + + + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 + read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + + + + DEADBAND_PERIOD + Deadband Period + 6 + 7 + read-write + + + + + Debug_Timer_CONTROL2 + TMRx.CFG1 + 0x40004F01 + 8 + read-write + 0 + 0 + + + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) + 0 + 0 + read-write + + + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 + read-write + + + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 + 6 + read-write + + + BUS_CLK_SEL + Bus Clock selection. + 7 + 7 + read-write + + + + + Debug_Timer_CONTROL3_ + TMRx.CFG2 + 0x40004F02 + 8 + read-write + 0 + 0 + + + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + 0 + 1 + read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + + + + COD + Clear On Disable (COD). Clears or gates outputs to zero. + 2 + 2 + read-write + + + ROD + Reset On Disable (ROD). Resets internal state of output logic + 3 + 3 + read-write + + + CMP_CFG + Comparator configurations + 4 + 6 + read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + + + + HW_EN + When set Timer Enable controls counting. + 7 + 7 + read-write + + + + + Debug_Timer_PERIOD + TMRx.PER0 - Assigned Period + 0x40004F04 + 16 + read-write + 0 + 0 + + + Debug_Timer_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0x40004F06 + 16 + read-write + 0 + 0 + + + + + SCSI_Out_Ctl + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x40006476 + 8 + read-write + 0 + 0 + + + + + SCSI_Out_Bits + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Bits_CONTROL_REG + No description available + 0x4000647D + 8 + read-write + 0 + 0 + + + + + USBFS + USBFS + 0x0 + + 0 + 0x0 + registers + + + + CR0 + USB Control 0 Register + 0x40006008 + 8 + read-write + 0 + 0 + + + DEVICE_ADDRESS + These bits specify the USB device address to which the SIE will respond. This address must be set by firmware and is specified by the USB Host with a SET ADDRESS command during USB enumeration. This value must be programmed by firmware when assigned during enumeration. It is not set automatically by the hardware. + 0 + 6 + read-only + + + USB_ENABLE + This bit enables the device to respond to USB traffic. + 7 + 7 + read-write + + + Disabled + Block responds to USB traffic. + 0 + + + Enabled + Block does not respond to USB traffic. + 1 + + + + + + + CR1 + USB Control 1 Register + 0x40006009 + 8 + read-write + 0 + 0 + + + REG_ENABLE + This bit controls the operation of the internal USB regulator. For applications with supply voltages in the 5V range this bit is set high to enable the internal regulator. For device supply voltage in the 3.3V range this bit is cleared to connect the transceiver directly to the supply. + 0 + 0 + read-only + + + Disabled + Regulator for 5V is disabled. + 0 + + + Enabled + Regulator for 5V is enabled. + 1 + + + + + ENABLE_LOCK + This bit is set to turn on the automatic frequency locking of the internal oscillator to USB traffic. Unless an external clock is being provided this bit should remain set for proper USB operation. + 1 + 1 + read-write + + + BUS_ACTIVITY + The Bus Activity bit is a stickybit that detects any non-idle USB event that has occurred on the USB bus. Once set to High by the SIE to indicate the bus activity this bit retains its logical High value until firmware clears it. + 2 + 2 + read-write + + + TRIM_OFFSET_MSB + This bit enables trim bit[7]. + 3 + 3 + read-write + + + + + SIE_EP_INT_EN + USB SIE Data Endpoints Interrupt Enable Register + 0x4000600A + 8 + read-write + 0 + 0 + + + EP1_INTR_EN + Enables interrupt for EP1. + 0 + 0 + read-write + + + EP2_INTR_EN + Enables interrupt for EP2. + 1 + 1 + read-write + + + EP3_INTR_EN + Enables interrupt for EP3. + 2 + 2 + read-write + + + EP4_INTR_EN + Enables interrupt for EP4. + 3 + 3 + read-write + + + EP5_INTR_EN + Enables interrupt for EP5. + 4 + 4 + read-write + + + EP6_INTR_EN + Enables interrupt for EP6. + 5 + 5 + read-write + + + EP7_INTR_EN + Enables interrupt for EP7. + 6 + 6 + read-write + + + EP8_INTR_EN + Enables interrupt for EP8. + 7 + 7 + read-write + + + + + SIE_EP_INT_SR + SIE Data Endpoint Interrupt Status Register + 0x4000600B + 8 + read-write + 0 + 0 + + + EP1_INTR + Interrupt status for EP1. + 0 + 0 + read-write + + + EP2_INTR + Interrupt status for EP2. + 1 + 1 + read-write + + + EP3_INTR + Interrupt status for EP3. + 2 + 2 + read-write + + + EP4_INTR + Interrupt status for EP4. + 3 + 3 + read-write + + + EP5_INTR + Interrupt status for EP5. + 4 + 4 + read-write + + + EP6_INTR + Interrupt status for EP6. + 5 + 5 + read-write + + + EP7_INTR + Interrupt status for EP7. + 6 + 6 + read-write + + + EP8_INTR + Interrupt status for EP8. + 7 + 7 + read-write + + + + + SIE_EP1_CNT0 + SIE Endpoint 1 Count0 Register + 0x4000600C + 8 + read-write + 0 + 0 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + 0 + 2 + read-write + + + DATA_VALID + DATA_ERROR - 0, DATA_VALID - 1. + 4 + 4 + read-write + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + 7 + 7 + read-write + + + + + SIE_EP1_CNT1 + SIE Endpoint 1 Count1 Register + 0x4000600D + 8 + read-write + 0 + 0 + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + 0 + 7 + read-write + + + + + SIE_EP1_CR0 + SIE Endpoint 1 Control Register + 0x4000600E + 8 + read-write + 0 + 0 + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + 0 + 3 + read-write + + + DISABLE + Ignore all USB traffic to this endpoint. + 0 + + + NAK_INOUT + SETUP: Accept, IN: NAK, OUT: NAK. + 1 + + + STATUS_OUT_ONLY + SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others. + 2 + + + STALL_INOUT + SETUP: Accept, IN: STALL, OUT: STALL. + 3 + + + ISO_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token. + 5 + + + STATUS_IN_ONLY + SETUP: Accept, IN: Respond with 0B data, OUT: Stall. + 6 + + + ISO_IN + SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore. + 7 + + + NAK_OUT + SETUP: Ignore, IN: Ignore, OUT: NAK. + 8 + + + ACK_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept, IN: Respond with 0B data, OUT: Accept data. + 11 + + + NAK_IN + SETUP: Ignore, IN: NAK, OUT: Ignore. + 12 + + + ACK_IN + SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others. + 15 + + + + + ACKED_TXN + ACKED_NO - 0, ACKED_YES - 1. + 4 + 4 + read-write + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + 5 + 5 + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. + 6 + 6 + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + 7 + 7 + read-write + + + + + USBIO_CR0 + USBIO Control 0 Register + 0x40006010 + 8 + read-write + 0 + 0 + + + RD + Received Data. This read only bit gives the state of the USB differential receiver. + 0 + 0 + read-only + + + DIFF_LOW + D+ less than D- (K state), or D+=D-=0 (SE0). + 0 + + + DIFF_HIGH + D+ greater than D- (J state). + 1 + + + + + TD + Transmit Data. Transmit a USB J or K state on the USB bus. No effect if TEN=0 or TSE0=1. + 5 + 5 + read-write + + + DIFF_K + Force USB K state (D+ is low D- is high). + 0 + + + DIFF_J + Force USB J state (D+ is high D- is low). + 1 + + + + + TSE0 + Transmit Single-Ended Zero. SE0: both D+ and D- low. No effect if TEN=0. + 6 + 6 + read-write + + + TEN + USB Transmit Enable. This is used to manually transmit on the D+ and D- pins. Normally this bit should be cleared to allow the internal SIE to drive the pins. The most common reason for manually transmitting is to force a resume state on the bus. + 7 + 7 + read-write + + + + + USBIO_CR1 + USBIO Control 1 Register + 0x40006012 + 8 + read-write + 0 + 0 + + + DMO + This read only bit gives the state of the D- pin. + 0 + 0 + read-only + + + DPO + This read only bit gives the state of the D+ pin. + 1 + 1 + read-only + + + USBPUEN + This bit enables the connection of the internal 1.5 k pull up resistor on the D+ pin. + 2 + 2 + read-write + + + IOMODE + This bit allows the D+ and D- pins to be configured for either USB mode or bit-banged modes. If this bit is set the DMI and DPI bits are used to drive the D- and D+ pins. + 5 + 5 + read-write + + + Bit_banged + Bit-banged mode for Dm and Dp. + 0 + + + USB + USB block controls Dm and Dp. + 1 + + + + + + + SIE_EP2_CNT0 + SIE Endpoint 1 Count0 Register + 0x4000601C + 8 + read-write + 0 + 0 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + 0 + 2 + read-write + + + DATA_VALID + DATA_ERROR - 0, DATA_VALID - 1. + 4 + 4 + read-write + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + 7 + 7 + read-write + + + + + SIE_EP2_CNT1 + SIE Endpoint 1 Count1 Register + 0x4000601D + 8 + read-write + 0 + 0 + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + 0 + 7 + read-write + + + + + SIE_EP2_CR0 + SIE Endpoint 1 Control Register + 0x4000601E + 8 + read-write + 0 + 0 + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + 0 + 3 + read-write + + + DISABLE + Ignore all USB traffic to this endpoint. + 0 + + + NAK_INOUT + SETUP: Accept, IN: NAK, OUT: NAK. + 1 + + + STATUS_OUT_ONLY + SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others. + 2 + + + STALL_INOUT + SETUP: Accept, IN: STALL, OUT: STALL. + 3 + + + ISO_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token. + 5 + + + STATUS_IN_ONLY + SETUP: Accept, IN: Respond with 0B data, OUT: Stall. + 6 + + + ISO_IN + SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore. + 7 + + + NAK_OUT + SETUP: Ignore, IN: Ignore, OUT: NAK. + 8 + + + ACK_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept, IN: Respond with 0B data, OUT: Accept data. + 11 + + + NAK_IN + SETUP: Ignore, IN: NAK, OUT: Ignore. + 12 + + + ACK_IN + SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others. + 15 + + + + + ACKED_TXN + ACKED_NO - 0, ACKED_YES - 1. + 4 + 4 + read-write + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + 5 + 5 + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. + 6 + 6 + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + 7 + 7 + read-write + + + + + EP0_CR + Endpoint0 control Register + 0x40006028 + 8 + read-write + 0 + 0 + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + 0 + 3 + read-write + + + DISABLE + Ignore all USB traffic to this endpoint. + 0 + + + NAK_INOUT + SETUP: Accept, IN: NAK, OUT: NAK. + 1 + + + STATUS_OUT_ONLY + SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others. + 2 + + + STALL_INOUT + SETUP: Accept, IN: STALL, OUT: STALL. + 3 + + + ISO_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token. + 5 + + + STATUS_IN_ONLY + SETUP: Accept, IN: Respond with 0B data, OUT: Stall. + 6 + + + ISO_IN + SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore. + 7 + + + NAK_OUT + SETUP: Ignore, IN: Ignore, OUT: NAK. + 8 + + + ACK_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept, IN: Respond with 0B data, OUT: Accept data. + 11 + + + NAK_IN + SETUP: Ignore, IN: NAK, OUT: Ignore. + 12 + + + ACK_IN + SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others. + 15 + + + + + ACKED_TXN + ACKED_NO - 0, ACKED_YES - 1. + 4 + 4 + read-write + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + 5 + 5 + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. + 6 + 6 + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + 7 + 7 + read-write + + + + + EP0_CNT + Endpoint0 control Register + 0x40006029 + 8 + read-write + 0 + 0 + + + BYTE_COUNT + These bits indicate the number of data bytes in a transaction. For IN transactions firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 8. For OUT or SETUP transactions the count is updated by hardware to the number of data bytes received plus two for the CRC bytes. Valid values are 2 to 10. + 0 + 3 + read-write + + + DATA_VALID + This bit is used for OUT/SETUP transactions only and is read only. It is cleared to '0' if CRC bit stuffing errors or PID errors occur. This bit does not update for some endpoint mode settings. + 4 + 4 + read-write + + + DATA_ERROR + No ACK'd transactions since bit was last cleared. + 0 + + + DATA_VALID + Indicates a transaction ended with an ACK. + 1 + + + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + 5 + 5 + read-write + + + + + SIE_EP3_CNT0 + SIE Endpoint 1 Count0 Register + 0x4000602C + 8 + read-write + 0 + 0 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + 0 + 2 + read-write + + + DATA_VALID + DATA_ERROR - 0, DATA_VALID - 1. + 4 + 4 + read-write + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + 7 + 7 + read-write + + + + + SIE_EP3_CNT1 + SIE Endpoint 1 Count1 Register + 0x4000602D + 8 + read-write + 0 + 0 + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + 0 + 7 + read-write + + + + + SIE_EP3_CR0 + SIE Endpoint 1 Control Register + 0x4000602E + 8 + read-write + 0 + 0 + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + 0 + 3 + read-write + + + DISABLE + Ignore all USB traffic to this endpoint. + 0 + + + NAK_INOUT + SETUP: Accept, IN: NAK, OUT: NAK. + 1 + + + STATUS_OUT_ONLY + SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others. + 2 + + + STALL_INOUT + SETUP: Accept, IN: STALL, OUT: STALL. + 3 + + + ISO_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token. + 5 + + + STATUS_IN_ONLY + SETUP: Accept, IN: Respond with 0B data, OUT: Stall. + 6 + + + ISO_IN + SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore. + 7 + + + NAK_OUT + SETUP: Ignore, IN: Ignore, OUT: NAK. + 8 + + + ACK_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept, IN: Respond with 0B data, OUT: Accept data. + 11 + + + NAK_IN + SETUP: Ignore, IN: NAK, OUT: Ignore. + 12 + + + ACK_IN + SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others. + 15 + + + + + ACKED_TXN + ACKED_NO - 0, ACKED_YES - 1. + 4 + 4 + read-write + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + 5 + 5 + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. + 6 + 6 + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + 7 + 7 + read-write + + + + + SIE_EP4_CNT0 + SIE Endpoint 1 Count0 Register + 0x4000603C + 8 + read-write + 0 + 0 + + + DATA_COUNT_MSB + These bits are the 3 MSb bits of an 11-bit counter. The LSb are the Data Count[7:0] bits of the CNT1 register. Refer to the CNT1 register for more information. + 0 + 2 + read-write + + + DATA_VALID + DATA_ERROR - 0, DATA_VALID - 1. + 4 + 4 + read-write + + + DATA_TOGGLE + This bit selects the DATA packet's toggle state. For IN transactions firmware must set this bit to the expected state. For OUT transactions the hardware sets this bit to the state of the received Data Toggle bit. + 7 + 7 + read-write + + + + + SIE_EP4_CNT1 + SIE Endpoint 1 Count1 Register + 0x4000603D + 8 + read-write + 0 + 0 + + + DATA_COUNT + These bits are the 8 LSb of a 11-bit counter. The 3 MSb bits are in the CNT0 register. The 11-bit count indicates the number of data bytes in a transaction. + 0 + 7 + read-write + + + + + SIE_EP4_CR0 + SIE Endpoint 1 Control Register + 0x4000603E + 8 + read-write + 0 + 0 + + + MODE + The mode controls how the USB SIE responds to traffic and how the USB SIE changes the mode of that endpoint as a result of host packets to the endpoint. + 0 + 3 + read-write + + + DISABLE + Ignore all USB traffic to this endpoint. + 0 + + + NAK_INOUT + SETUP: Accept, IN: NAK, OUT: NAK. + 1 + + + STATUS_OUT_ONLY + SETUP: Accept, IN: STALL, OUT: ACK 0B tokens, NAK others. + 2 + + + STALL_INOUT + SETUP: Accept, IN: STALL, OUT: STALL. + 3 + + + ISO_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept Isochronous OUT token. + 5 + + + STATUS_IN_ONLY + SETUP: Accept, IN: Respond with 0B data, OUT: Stall. + 6 + + + ISO_IN + SETUP: Ignore, IN: Accept Isochronous IN token, OUT: Ignore. + 7 + + + NAK_OUT + SETUP: Ignore, IN: Ignore, OUT: NAK. + 8 + + + ACK_OUT + SETUP: Ignore, IN: Ignore, OUT: Accept data and ACK if STALL = 0, STALL otherwise. Change to MODE=8 after one succesfull OUT token. + 9 + + + ACK_OUT_STATUS_IN + SETUP: Accept, IN: Respond with 0B data, OUT: Accept data. + 11 + + + NAK_IN + SETUP: Ignore, IN: NAK, OUT: Ignore. + 12 + + + ACK_IN + SETUP: Ignore, IN: Respond to IN with data if STALL=0, STALL otherwise, OUT: Ignore + 13 + + + ACK_IN_STATUS_OUT + SETUP: Accept, IN: Respond to IN with data, OUT: ACK 0B tokens, NAK others. + 15 + + + + + ACKED_TXN + ACKED_NO - 0, ACKED_YES - 1. + 4 + 4 + read-write + + + NAK_INT_EN + When set this bit causes an endpoint interrupt to be generated even when a transfer completes with a NAK. + 5 + 5 + read-write + + + ERR_IN_TXN + The Error in transaction bit is set whenever an error is detected. + 6 + 6 + read-write + + + STALL + When this bit is set the SIE stalls an OUT packet if the Mode bits are set to ACK-OUT. The SIE stalls an IN packet if the mode bits are set to ACK-IN. This bit must be clear for all other modes. + 7 + 7 + read-write + + + + + ARB_EP1_CFG + Arbiter Endpoint 1 Configuration Register + 0x40006080 + 8 + read-write + 0 + 0 + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + 0 + 0 + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + 1 + 1 + read-write + + + CRC_BYPASS + CRC_NORMAL - 0, CRC_BYPASS - 1 + 2 + 2 + read-write + + + RESET_PTR + RESET_KRYPTON - 0, RESET_NORMAL - 1 + 3 + 3 + read-write + + + + + ARB_EP1_INT_EN + Arbiter Endpoint 1 Interrupt Enable Register + 0x40006081 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_EP1_INT_SR + Arbiter Endpoint 1 Interrupt Status Register + 0x40006082 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_RW1_WA + Arbiter Endpoint 1 Write Address LSB Register + 0x40006084 + 8 + read-write + 0 + 0 + + + WA8 + Write Address for EP. + 0 + 7 + read-write + + + + + ARB_RW1_WA_MSB + Arbiter Endpoint 1 Write Address MSB Register + 0x40006085 + 8 + read-write + 0 + 0 + + + WA9 + Write Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_RW1_RA + Arbiter Endpoint 1 Read Address LSB Register + 0x40006086 + 8 + read-write + 0 + 0 + + + RA8 + Read Address for EP MSB. + 0 + 7 + read-write + + + + + ARB_RW1_RA_MSB + Arbiter Endpoint 1 Read Address MSB Register + 0x40006087 + 8 + read-write + 0 + 0 + + + RA9 + Read Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_EP2_CFG + Arbiter Endpoint 1 Configuration Register + 0x40006090 + 8 + read-write + 0 + 0 + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + 0 + 0 + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + 1 + 1 + read-write + + + CRC_BYPASS + CRC_NORMAL - 0, CRC_BYPASS - 1 + 2 + 2 + read-write + + + RESET_PTR + RESET_KRYPTON - 0, RESET_NORMAL - 1 + 3 + 3 + read-write + + + + + ARB_EP2_INT_EN + Arbiter Endpoint 1 Interrupt Enable Register + 0x40006091 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_EP2_INT_SR + Arbiter Endpoint 1 Interrupt Status Register + 0x40006092 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_RW2_WA + Arbiter Endpoint 1 Write Address LSB Register + 0x40006094 + 8 + read-write + 0 + 0 + + + WA8 + Write Address for EP. + 0 + 7 + read-write + + + + + ARB_RW2_WA_MSB + Arbiter Endpoint 1 Write Address MSB Register + 0x40006095 + 8 + read-write + 0 + 0 + + + WA9 + Write Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_RW2_RA + Arbiter Endpoint 1 Read Address LSB Register + 0x40006096 + 8 + read-write + 0 + 0 + + + RA8 + Read Address for EP MSB. + 0 + 7 + read-write + + + + + ARB_RW2_RA_MSB + Arbiter Endpoint 1 Read Address MSB Register + 0x40006097 + 8 + read-write + 0 + 0 + + + RA9 + Read Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_CFG + Arbiter configuration register + 0x4000609C + 8 + read-write + 0 + 0 + + + AUTO_MEM + Enables Auto Memory Configuration. Manual memory configuration by default. + 4 + 4 + read-write + + + DMA_CFG + DMA Access Configuration. + 5 + 6 + read-write + + + DMA_NONE + No DMA. + 0 + + + DMA_MANUAL + Manual DMA. + 1 + + + DMA_AUTO + Auto DMA. + 2 + + + + + CFG_CMP + Register Configuration Complete Indication. Posedge is detected on this bit. Hence a 0 to 1 transition is required. + 7 + 7 + read-write + + + + + USB_CLK_EN + USB Control 0 Register + 0x4000609D + 8 + read-write + 0 + 0 + + + CSR_CLK_EN + Clock Enable for Core Logic clocked by AHB bus clock. + 7 + 7 + read-write + + + Disabled + Disables clock to UBS block. + 0 + + + Enabled + Enables clock to UBS block. + 1 + + + + + + + ARB_INT_EN + Arbiter Interrupt Enable Register + 0x4000609E + 8 + read-write + 0 + 0 + + + EP1_INTR_EN + Enables interrupt for EP1. + 0 + 0 + read-write + + + EP2_INTR_EN + Enables interrupt for EP2. + 1 + 1 + read-write + + + EP3_INTR_EN + Enables interrupt for EP3. + 2 + 2 + read-write + + + EP4_INTR_EN + Enables interrupt for EP4. + 3 + 3 + read-write + + + EP5_INTR_EN + Enables interrupt for EP5. + 4 + 4 + read-write + + + EP6_INTR_EN + Enables interrupt for EP6. + 5 + 5 + read-write + + + EP7_INTR_EN + Enables interrupt for EP7. + 6 + 6 + read-write + + + EP8_INTR_EN + Enables interrupt for EP8. + 7 + 7 + read-write + + + + + ARB_INT_SR + Arbiter Interrupt Status + 0x4000609F + 8 + read-write + 0 + 0 + + + EP1_INTR + Interrupt status for EP1. + 0 + 0 + read-only + + + EP2_INTR + Interrupt status for EP2. + 1 + 1 + read-only + + + EP3_INTR + Interrupt status for EP3. + 2 + 2 + read-only + + + EP4_INTR + Interrupt status for EP4. + 3 + 3 + read-only + + + EP5_INTR + Interrupt status for EP5. + 4 + 4 + read-only + + + EP6_INTR + Interrupt status for EP6. + 5 + 5 + read-only + + + EP7_INTR + Interrupt status for EP7. + 6 + 6 + read-only + + + EP8_INTR + Interrupt status for EP8. + 7 + 7 + read-only + + + + + ARB_EP3_CFG + Arbiter Endpoint 1 Configuration Register + 0x400060A0 + 8 + read-write + 0 + 0 + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + 0 + 0 + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + 1 + 1 + read-write + + + CRC_BYPASS + CRC_NORMAL - 0, CRC_BYPASS - 1 + 2 + 2 + read-write + + + RESET_PTR + RESET_KRYPTON - 0, RESET_NORMAL - 1 + 3 + 3 + read-write + + + + + ARB_EP3_INT_EN + Arbiter Endpoint 1 Interrupt Enable Register + 0x400060A1 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_EP3_INT_SR + Arbiter Endpoint 1 Interrupt Status Register + 0x400060A2 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_RW3_WA + Arbiter Endpoint 1 Write Address LSB Register + 0x400060A4 + 8 + read-write + 0 + 0 + + + WA8 + Write Address for EP. + 0 + 7 + read-write + + + + + ARB_RW3_WA_MSB + Arbiter Endpoint 1 Write Address MSB Register + 0x400060A5 + 8 + read-write + 0 + 0 + + + WA9 + Write Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_RW3_RA + Arbiter Endpoint 1 Read Address LSB Register + 0x400060A6 + 8 + read-write + 0 + 0 + + + RA8 + Read Address for EP MSB. + 0 + 7 + read-write + + + + + ARB_RW3_RA_MSB + Arbiter Endpoint 1 Read Address MSB Register + 0x400060A7 + 8 + read-write + 0 + 0 + + + RA9 + Read Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_EP4_CFG + Arbiter Endpoint 1 Configuration Register + 0x400060B0 + 8 + read-write + 0 + 0 + + + IN_DATA_RDY + Indication that Endpoint Packet Data is Ready in Main memory + 0 + 0 + read-write + + + DMA_REQ + Manual DMA Request for a particular (1 to 8) endpoint; changing this field from 0 to 1 causes a DMA request to be generated. + 1 + 1 + read-write + + + CRC_BYPASS + CRC_NORMAL - 0, CRC_BYPASS - 1 + 2 + 2 + read-write + + + RESET_PTR + RESET_KRYPTON - 0, RESET_NORMAL - 1 + 3 + 3 + read-write + + + + + ARB_EP4_INT_EN + Arbiter Endpoint 1 Interrupt Enable Register + 0x400060B1 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_EP4_INT_SR + Arbiter Endpoint 1 Interrupt Status Register + 0x400060B2 + 8 + read-write + 0 + 0 + + + IN_BUF_FULL_EN + IN Endpoint Local Buffer Full + 0 + 0 + read-write + + + DMA_GNT_EN + Endpoint DMA Grant + 1 + 1 + read-write + + + BUF_OVER_EN + Endpoint Buffer Overflow + 2 + 2 + read-write + + + BUF_UNDER_EN + Endpoint Buffer Underflow + 3 + 3 + read-write + + + ERR_INT_EN + Endpoint Error in Transaction Interrupt + 4 + 4 + read-write + + + DMA_TERMIN_EN + Endpoint DMA Terminated Enable + 5 + 5 + read-write + + + + + ARB_RW4_WA + Arbiter Endpoint 1 Write Address LSB Register + 0x400060B4 + 8 + read-write + 0 + 0 + + + WA8 + Write Address for EP. + 0 + 7 + read-write + + + + + ARB_RW4_WA_MSB + Arbiter Endpoint 1 Write Address MSB Register + 0x400060B5 + 8 + read-write + 0 + 0 + + + WA9 + Write Address for EP MSB. + 0 + 0 + read-write + + + + + ARB_RW4_RA + Arbiter Endpoint 1 Read Address LSB Register + 0x400060B6 + 8 + read-write + 0 + 0 + + + RA8 + Read Address for EP MSB. + 0 + 7 + read-write + + + + + ARB_RW4_RA_MSB + Arbiter Endpoint 1 Read Address MSB Register + 0x400060B7 + 8 + read-write + 0 + 0 + + + RA9 + Read Address for EP MSB. + 0 + 0 + read-write + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch new file mode 100644 index 0000000..aec23a1 Binary files /dev/null and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/device.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/device.h new file mode 100644 index 0000000..af016c3 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/device.h @@ -0,0 +1,18 @@ +/******************************************************************************* +* This file is automatically generated by PSoC Creator +* and should not be edited by hand. +* +* This file is necessary for your project to build. +* Please do not delete it. +******************************************************************************** +* Copyright 2008-2011, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ +#ifndef DEVICE_H +#define DEVICE_H +#include + +#endif +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym new file mode 100644 index 0000000..a0321ce Binary files /dev/null and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.cysym differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.v b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.v new file mode 100644 index 0000000..3fb7a3c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/scsiTarget/scsiTarget.v @@ -0,0 +1,402 @@ + +//`#start header` -- edit after this line, do not edit this line +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +`include "cypress.v" +//`#end` -- edit above this line, do not edit this line +// Generated on 10/16/2013 at 00:01 +// Component: scsiTarget +module scsiTarget ( + output [7:0] DBx_out, // Active High, connected to SCSI bus via inverter + output REQ, // Active High, connected to SCSI bus via inverter + input nACK, // Active LOW, connected directly to SCSI bus. + input [7:0] nDBx_in, // Active LOW, connected directly to SCSI bus. + input nDBP, // Active LOW, connected directly to SCSI bus + input IO, // Active High, set by CPU via status register. + input nRST, // Active LOW, connected directly to SCSI bus. + input clk, + output tx_intr, + output rx_intr, + output parityErr +); + + +//`#start body` -- edit after this line, do not edit this line + +///////////////////////////////////////////////////////////////////////////// +// Force Clock Sync +///////////////////////////////////////////////////////////////////////////// +// The udb_clock_enable primitive component is used to indicate that the input +// clock must always be synchronous and if not implement synchronizers to make +// it synchronous. +wire op_clk; +cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`TRUE)) ClkSync +( + .clock_in(clk), + .enable(1'b1), + .clock_out(op_clk) +); + +///////////////////////////////////////////////////////////////////////////// +// CONSTANTS +///////////////////////////////////////////////////////////////////////////// +localparam IO_WRITE = 1'b1; +localparam IO_READ = 1'b0; + + +///////////////////////////////////////////////////////////////////////////// +// STATE MACHINE +///////////////////////////////////////////////////////////////////////////// +// TX States: +// IDLE +// Wait for an entry in the input FIFO +// FIFOLOAD +// Load F0 into A0. Feed (old) A0 into the ALU SRCA. +// TX +// Load data register from PO. PO is fed by A0 going into the ALU via SRCA +// A0 must remain unchanged. +// DESKEW_INIT +// DBx output signals will be output in this state +// Load deskew clock count into A0 from D0 +// DESKEW +// DBx output signals will be output in this state +// Wait for the SCSI deskew time of 55ns. (DEC A0). +// A1 must be fed into SRCA, so PO is now useless. +// READY +// REQ and DBx output signals will be output in this state +// Wait for acknowledgement from the SCSI initiator +// RX +// Wait for the initiator to release he ACK signal. Once released, +// PI enabled for input into ALU "PASS" operation, storing into F1 in the +// next state, either IDLE or FIFOLOAD. +// +// RX States: +// IDLE +// Wait for a dummy "enabling" entry in the input FIFO +// FIFOLOAD +// Load F0 into A0. +// The input FIFO is used to control the number of bytes we attempt to +// read from the SCSI bus. +// WAIT_TIL_READY +// Wait for space in output fifo +// +// READY +// REQ signal will be output in this state +// Wait for the initiator to send a byte on the SCSI bus. +// RX +// Wait for the initiator to release he ACK signal. Once released, +// PI enabled for input into ALU "PASS" operation, storing into F1 in the +// next state, either IDLE or FIFOLOAD. + + +localparam STATE_IDLE = 3'b000; +localparam STATE_FIFOLOAD = 3'b001; +localparam STATE_TX = 3'b010; +localparam STATE_DESKEW_INIT = 3'b011; +localparam STATE_DESKEW = 3'b100; +localparam STATE_WAIT_TIL_READY = 3'b101; +localparam STATE_READY = 3'b110; +localparam STATE_RX = 3'b111; + +// state selects the datapath register. +reg[2:0] state; + +// Data being read/written from/to the SCSI bus +reg[7:0] data; + +// Set by the datapath zero detector (z1). High when A1 counts down to zero. +wire deskewComplete; + +// Parallel input to the datapath SRCA. +// Selected for input through to the ALU if CFB EN bit set for the datapath +// state and enabled by PI DYN bit in CFG15-14 +wire[7:0] pi; + +// Parallel output from the selected SRCA value (A0 or A1) to the ALU. +wire[7:0] po; + +// Set true to trigger storing A1 into F1. Set while in STATE_RX +reg fifoStore; + +// Set to true on detecting a parity input while reading +reg parityErrReg; +// Temp values in parity calcs. We need to do it in 2 steps to avoid +// timing issues and running-out-of resources +reg[2:0] genParity; + +reg REQReg; +reg[7:0] dbxInReg; + +// Set Output Pins +assign REQ = REQReg; // STATE_READY & STATE_RX +assign DBx_out[7:0] = data; +assign pi[7:0] = dbxInReg[7:0]; +assign parityErr = parityErrReg; + + +///////////////////////////////////////////////////////////////////////////// +// FIFO Status Register +///////////////////////////////////////////////////////////////////////////// +// Status Register: scsiTarget_StatusReg__STATUS_REG +// Bit 0: Tx FIFO not full +// Bit 1: Rx FIFO not empty +// Bit 2: Tx FIFO empty +// Bit 3: Rx FIFO full +// Bit 4: TX Complete. Fifos empty and idle. +// +// TX FIFO Register: scsiTarget_scsiTarget_u0__F0_REG +// RX FIFO Register: scsiTarget_scsiTarget_u0__F1_REG +// Use with CY_GET_REG8 and CY_SET_REG8 +wire f0_bus_stat; // Tx FIFO not full +wire f0_blk_stat; // Tx FIFO empty +wire f1_bus_stat; // Rx FIFO not empty +wire f1_blk_stat; // Rx FIFO full +wire txComplete = f0_blk_stat && (state == STATE_IDLE); +cy_psoc3_status #(.cy_force_order(1), .cy_md_select(8'h00)) StatusReg +( + .clock(op_clk), + .status({3'b0, txComplete, f1_blk_stat, f0_blk_stat, f1_bus_stat, f0_bus_stat}) +); + +// DMA outputs +assign tx_intr = f0_bus_stat; +//assign tx_intr = f0_blk_stat; +assign rx_intr = f1_bus_stat; +//assign rx_intr = f1_blk_stat; + +///////////////////////////////////////////////////////////////////////////// +// State machine +///////////////////////////////////////////////////////////////////////////// +always @(posedge op_clk) begin + case (state) + STATE_IDLE: + begin + if (!nRST) state <= STATE_IDLE; + else if (!f0_blk_stat) // Input FIFO has some data + state <= STATE_FIFOLOAD; + else + state <= STATE_IDLE; + + // Clear our output pins + data <= 8'b0; + + REQReg <= 1'b0; + fifoStore <= 1'b0; + parityErrReg <= 1'b0; + end + + STATE_FIFOLOAD: + begin + fifoStore <= 1'b0; + + if (!nRST) state <= STATE_IDLE; + else if (IO == IO_WRITE) + state <= STATE_TX; + + // Note: Cannot check whether the output FIFO is not full + // because we haven't finished writing to it yet. + // causes a rare race condition issue on fast SCSI hosts + + else begin + state <= STATE_WAIT_TIL_READY; + end + end + + STATE_TX: + begin + if (!nRST) state <= STATE_IDLE; + else state <= STATE_DESKEW_INIT; + data <= po; + end + + STATE_DESKEW_INIT: + if (!nRST) state <= STATE_IDLE; + else state <= STATE_DESKEW; + + STATE_DESKEW: + if (!nRST) state <= STATE_IDLE; + else if(deskewComplete) begin + state <= STATE_READY; + REQReg <= 1'b1; + end else state <= STATE_DESKEW; + + STATE_WAIT_TIL_READY: // IO == IO_READ only + if (!nRST) state <= STATE_IDLE; + + // Wait until the output FIFO is not full. + else if (!f1_blk_stat) begin + state <= STATE_READY; + REQReg <= 1'b1; + end else begin + state <= STATE_WAIT_TIL_READY; + end + + STATE_READY: + if (!nRST) state <= STATE_IDLE; + else if (~nACK) begin + REQReg <= 1'b0; + state <= STATE_RX; + dbxInReg[7:0] = ~nDBx_in[7:0]; // Invert active low scsi bus + + genParity[0] <= (~nDBP) ^ 1'b1 ^ ~nDBx_in[7] ^ ~nDBx_in[6]; + genParity[1] <= ~nDBx_in[5] ^ ~nDBx_in[4] ^ ~nDBx_in[3]; + genParity[2] <= ~nDBx_in[2] ^ ~nDBx_in[1] ^ ~nDBx_in[0]; + end else state <= STATE_READY; + + STATE_RX: + begin + // Wait for this transfer to complete. + // We need to wait at the end, because some hosts will set ACK + // before REQ for the first byte of a phase. + if (!nRST) state <= STATE_IDLE; + else if (nACK && !f0_blk_stat) + begin // Next byte is ready, skip IDLE. + fifoStore <= 1'b1; + state <= STATE_FIFOLOAD; + end + else if (nACK) + begin + fifoStore <= 1'b1; + state <= STATE_IDLE; + end + else + state <= STATE_RX; + + parityErrReg <= 1'b0; + if (IO == IO_READ) begin + parityErrReg <= ^genParity[2:0]; + end + end + + default: state <= STATE_IDLE; + endcase +end + +// D0 is used for the deskew count. +// The data output is valid during the DESKEW_INIT phase as well, +// so we subtract 1. +// SCSI-1 deskew + cable skew = 55ns +// D0 = [0.000000055 / (1 / clk)] - 1 = 1 (clk = 25MHz) +// SCSI-2 FAST deskew + cable skew = 25ns +// D0 = [0.000000025 / (1 / clk)] - 1 = 0 (clk = 25MHz) +cy_psoc3_dp #(.d0_init(1), +.cy_dpconfig( +{ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, + `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM0: IDLE*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC___F0, `CS_A1_SRC_NONE, + `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM1: FIFO Load*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, + `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM2: TX*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC___D0, `CS_A1_SRC_NONE, + `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM3: DESKEW INIT*/ + `CS_ALU_OP__DEC, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC__ALU, `CS_A1_SRC_NONE, + `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM4: DESKEW*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, + `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM5: WAIT TIL READY*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, + `CS_FEEDBACK_DSBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM6: READY*/ + `CS_ALU_OP_PASS, `CS_SRCA_A0, `CS_SRCB_D0, + `CS_SHFT_OP_PASS, `CS_A0_SRC_NONE, `CS_A1_SRC_NONE, + `CS_FEEDBACK_ENBL, `CS_CI_SEL_CFGA, `CS_SI_SEL_CFGA, + `CS_CMP_SEL_CFGA, /*CFGRAM7: RX*/ + 8'hFF, 8'h00, /*CFG9: */ + 8'hFF, 8'hFF, /*CFG11-10: */ + `SC_CMPB_A1_D1, `SC_CMPA_A1_D1, `SC_CI_B_ARITH, + `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, + `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_DEFSI, + `SC_SI_A_DEFSI, /*CFG13-12: */ + `SC_A0_SRC_ACC, `SC_SHIFT_SL, `SC_PI_DYN_EN, + 1'h0, `SC_FIFO1_ALU, `SC_FIFO0_BUS, + `SC_MSB_DSBL, `SC_MSB_BIT0, `SC_MSB_NOCHN, + `SC_FB_NOCHN, `SC_CMP1_NOCHN, + `SC_CMP0_NOCHN, /*CFG15-14: */ + 10'h00, `SC_FIFO_CLK__DP,`SC_FIFO_CAP_AX, + `SC_FIFO_LEVEL,`SC_FIFO__SYNC,`SC_EXTCRC_DSBL, + `SC_WRK16CAT_DSBL /*CFG17-16: */ +} +)) datapath( + /* input */ .reset(1'b0), + /* input */ .clk(op_clk), + /* input [02:00] */ .cs_addr(state), + /* input */ .route_si(1'b0), + /* input */ .route_ci(1'b0), + /* input */ .f0_load(1'b0), + /* input */ .f1_load(fifoStore), + /* input */ .d0_load(1'b0), + /* input */ .d1_load(1'b0), + /* output */ .ce0(), + /* output */ .cl0(), + /* output */ .z0(deskewComplete), + /* output */ .ff0(), + /* output */ .ce1(), + /* output */ .cl1(), + /* output */ .z1(), + /* output */ .ff1(), + /* output */ .ov_msb(), + /* output */ .co_msb(), + /* output */ .cmsb(), + /* output */ .so(), + /* output */ .f0_bus_stat(f0_bus_stat), + /* output */ .f0_blk_stat(f0_blk_stat), + /* output */ .f1_bus_stat(f1_bus_stat), + /* output */ .f1_blk_stat(f1_blk_stat), + + /* input */ .ci(1'b0), // Carry in from previous stage + /* output */ .co(), // Carry out to next stage + /* input */ .sir(1'b0), // Shift in from right side + /* output */ .sor(), // Shift out to right side + /* input */ .sil(1'b0), // Shift in from left side + /* output */ .sol(), // Shift out to left side + /* input */ .msbi(1'b0), // MSB chain in + /* output */ .msbo(), // MSB chain out + /* input [01:00] */ .cei(2'b0), // Compare equal in from prev stage + /* output [01:00] */ .ceo(), // Compare equal out to next stage + /* input [01:00] */ .cli(2'b0), // Compare less than in from prv stage + /* output [01:00] */ .clo(), // Compare less than out to next stage + /* input [01:00] */ .zi(2'b0), // Zero detect in from previous stage + /* output [01:00] */ .zo(), // Zero detect out to next stage + /* input [01:00] */ .fi(2'b0), // 0xFF detect in from previous stage + /* output [01:00] */ .fo(), // 0xFF detect out to next stage + /* input [01:00] */ .capi(2'b0), // Software capture from previous stage + /* output [01:00] */ .capo(), // Software capture to next stage + /* input */ .cfbi(1'b0), // CRC Feedback in from previous stage + /* output */ .cfbo(), // CRC Feedback out to next stage + /* input [07:00] */ .pi(pi), // Parallel data port + /* output [07:00] */ .po(po) // Parallel data port +); +//`#end` -- edit above this line, do not edit this line +endmodule +//`#start footer` -- edit after this line, do not edit this line +//`#end` -- edit above this line, do not edit this line + + + diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c new file mode 100644 index 0000000..a013f3f --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.c @@ -0,0 +1,1863 @@ +/******************************************************************************* +* File Name: BL.c +* Version 1.30 +* +* Description: +* Provides an API for the Bootloader component. The API includes functions +* for starting boot loading operations, validating the application and +* jumping to the application. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "BL_PVT.h" + +#include "project.h" +#include + + +/******************************************************************************* +* The Checksum and SizeBytes are forcefully set in code. We then post process +* the hex file from the linker and inject their values then. When the hex file +* is loaded onto the device these two variables should have valid values. +* Because the compiler can do optimizations to remove the constant +* accesses, these should not be accessed directly. Instead, the variables +* CyBtldr_ChecksumAccess & CyBtldr_SizeBytesAccess should be used to get the +* proper values at runtime. +*******************************************************************************/ +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"), used)) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) + const uint8 CYCODE BL_Checksum = 0u; +#elif defined (__ICCARM__) + __root const uint8 CYCODE BL_Checksum = 0u; +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) || defined (__C51__) */ +const uint8 CYCODE *BL_ChecksumAccess = (const uint8 CYCODE *)(&BL_Checksum); + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"), used)) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ + +const uint32 CYCODE BL_SizeBytes = 0xFFFFFFFFu; +const uint32 CYCODE *BL_SizeBytesAccess = (const uint32 CYCODE *)(&BL_SizeBytes); + + +#if(0u != BL_DUAL_APP_BOOTLOADER) + uint8 BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; +#else + #define BL_activeApp (BL_MD_BTLDB_ACTIVE_0) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/*************************************** +* Function Prototypes +***************************************/ +static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ + ; + +static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) CYSMALL \ + ; + +static void BL_HostLink(uint8 timeOut) \ + ; + +static void BL_LaunchApplication(void) CYSMALL \ + ; + +#if(!CY_PSOC3) + /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ + static void BL_LaunchBootloadable(uint32 appAddr); +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: BL_CalcPacketChecksum +******************************************************************************** +* +* Summary: +* This computes the 16 bit checksum for the provided number of bytes contained +* in the provided buffer +* +* Parameters: +* buffer: +* The buffer containing the data to compute the checksum for +* size: +* The number of bytes in the buffer to compute the checksum for +* +* Returns: +* 16 bit checksum for the provided data +* +*******************************************************************************/ +static uint16 BL_CalcPacketChecksum(const uint8 buffer[], uint16 size) \ + CYSMALL +{ + #if(0u != BL_PACKET_CHECKSUM_CRC) + + uint16 CYDATA crc = BL_CRC_CCITT_INITIAL_VALUE; + uint16 CYDATA tmp; + uint8 CYDATA i; + uint16 CYDATA tmpIndex = size; + + if(0u == size) + { + crc = ~crc; + } + else + { + do + { + tmp = buffer[tmpIndex - size]; + + for (i = 0u; i < 8u; i++) + { + if (0u != ((crc & 0x0001u) ^ (tmp & 0x0001u))) + { + crc = (crc >> 1u) ^ BL_CRC_CCITT_POLYNOMIAL; + } + else + { + crc >>= 1u; + } + + tmp >>= 1u; + } + + size--; + } + while(0u != size); + + crc = ~crc; + tmp = crc; + crc = ( uint16 )(crc << 8u) | (tmp >> 8u); + } + + return(crc); + + #else + + uint16 CYDATA sum = 0u; + + while (size > 0u) + { + sum += buffer[size - 1u]; + size--; + } + + return(( uint16 )1u + ( uint16 )(~sum)); + + #endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ +} + + +/******************************************************************************* +* Function Name: BL_Calc8BitSum +******************************************************************************** +* +* Summary: +* This computes the 8 bit sum for the provided number of bytes contained in +* FLASH (if baseAddr equals CY_FLASH_BASE) or EEPROM (if baseAddr equals +* CY_EEPROM_BASE). +* +* Parameters: +* baseAddr: +* CY_FLASH_BASE +* CY_EEPROM_BASE - applicable only for PSoC 3 / PSoC 5LP devices. +* +* start: +* The starting address to start summing data for +* size: +* The number of bytes to read and compute the sum for +* +* Returns: +* 8 bit sum for the provided data +* +*******************************************************************************/ +uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) \ + CYSMALL +{ + uint8 CYDATA sum = 0u; + + #if(!CY_PSOC4) + CYASSERT((baseAddr == CY_EEPROM_BASE) || (baseAddr == CY_FLASH_BASE)); + #else + CYASSERT(baseAddr == CY_FLASH_BASE); + #endif /* (!CY_PSOC4) */ + + while (size > 0u) + { + size--; + sum += (*((uint8 *)(baseAddr + start + size))); + } + + return(sum); +} + + +/******************************************************************************* +* Function Name: BL_Start +******************************************************************************** +* Summary: +* This function is called in order to execute the following algorithm: +* +* - Identify the active bootloadable application (applicable only to +* the Multi-application bootloader) +* +* - Validate the bootloader application (design-time configurable, Bootloader +* application validation option of the component customizer) +* +* - Validate the active bootloadable application. If active bootloadable +* application is not valid, and the other bootloadable application (inactive) +* is valid, the last one is started. +* +* - Run a communication subroutine (design-time configurable, Wait for command +* option of the component customizer) +* +* - Schedule the bootloadable and reset the device +* +* Parameters: +* None +* +* Return: +* This method will never return. It will either load a new application and +* reset the device or jump directly to the existing application. The CPU is +* halted, if validation failed when "Bootloader application validation" option +* is enabled. +* PSoC 3/PSoC 5: The CPU is halted if Flash initialization fails. +* +* Side Effects: +* If Bootloader application validation option is enabled and this method +* determines that the bootloader application itself is corrupt, this method +* will not return, instead it will simply hang the application. +* +*******************************************************************************/ +void BL_Start(void) CYSMALL +{ + #if(0u != BL_BOOTLOADER_APP_VALIDATION) + uint8 CYDATA calcedChecksum; + #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ + + #if(!CY_PSOC4) + #if(0u != BL_FAST_APP_VALIDATION) + #if !defined(CY_BOOT_VERSION) + + /* Not required starting from cy_boot 4.20 */ + uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE]; + + #endif /* !defined(CY_BOOT_VERSION) */ + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + #endif /* (!CY_PSOC4) */ + + cystatus validApp = CYRET_BAD_DATA; + + + /* Identify active bootloadable application */ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + /* Assumes no active bootloadable application. Bootloader is active. */ + BL_activeApp = BL_MD_BTLDB_ACTIVE_NONE; + + /* Bootloadable # A is active */ + if(BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 0u) == BL_MD_BTLDB_IS_ACTIVE) + { + /******************************************************************* + * ----------------------------------------------------------- + * | | Bootloadable A | Bootloadable B | | + * | Case |---------------------------------| Action | + * | | Active | Valid | Active | Valid | | + * |------|--------------------------------------------------| + * | 9 | 1 | 0 | 0 | 0 | Bootloader | + * | 10 | 1 | 0 | 0 | 1 | Bootloadable B | + * | 11 | 1 | 0 | 1 | 0 | Bootloader | + * | 12 | 1 | 0 | 1 | 1 | Bootloadable B | + * | 13 | 1 | 1 | 0 | 0 | Bootloadable A | + * | 14 | 1 | 1 | 0 | 1 | Bootloadable A | + * | 15 | 1 | 1 | 1 | 0 | Bootloadable A | + * | 16 | 1 | 1 | 1 | 1 | Bootloadable A | + * ----------------------------------------------------------- + *******************************************************************/ + if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)) + { + /* Cases # 13, 14, 15, and 16 */ + BL_activeApp = BL_MD_BTLDB_ACTIVE_0; + validApp = CYRET_SUCCESS; + } + else + { + if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1)) + { + /* Cases # 10 and 12 */ + BL_activeApp = BL_MD_BTLDB_ACTIVE_1; + validApp = CYRET_SUCCESS; + } + } + } + + /* Active bootloadable application is not identified */ + if(BL_activeApp == BL_MD_BTLDB_ACTIVE_NONE) + { + /******************************************************************* + * ----------------------------------------------------------- + * | | Bootloadable A | Bootloadable B | | + * | Case |---------------------------------| Action | + * | | Active | Valid | Active | Valid | | + * |------|--------------------------------------------------| + * | 1 | 0 | 0 | 0 | 0 | Bootloader | + * | 2 | 0 | 0 | 0 | 1 | Bootloader | + * | 3 | 0 | 0 | 1 | 0 | Bootloader | + * | 4 | 0 | 0 | 1 | 1 | Bootloadable B | + * | 5 | 0 | 1 | 0 | 0 | Bootloader | + * | 6 | 0 | 1 | 0 | 1 | Bootloader | + * | 7 | 0 | 1 | 1 | 0 | Bootloadable A | + * | 8 | 0 | 1 | 1 | 1 | Bootloadable B | + * ----------------------------------------------------------- + *******************************************************************/ + if (BL_GetMetadata(BL_GET_BTLDB_ACTIVE, 1u) == + BL_MD_BTLDB_IS_ACTIVE) + { + /* Cases # 3, 4, 7, and 8 */ + if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_1)) + { + /* Cases # 4 and 8 */ + BL_activeApp = BL_MD_BTLDB_ACTIVE_1; + validApp = CYRET_SUCCESS; + } + else + { + if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)) + { + /* Cases # 7 */ + BL_activeApp = BL_MD_BTLDB_ACTIVE_0; + validApp = CYRET_SUCCESS; + } + } + } + } + #else + if (CYRET_SUCCESS == BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0)) + { + validApp = CYRET_SUCCESS; + } + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /* Initialize Flash subsystem for non-PSoC 4 devices */ + #if(!CY_PSOC4) + #if(0u != BL_FAST_APP_VALIDATION) + + if (CYRET_SUCCESS != CySetTemp()) + { + CyHalt(0x00u); + } + + #if !defined(CY_BOOT_VERSION) + + /* Not required with cy_boot 4.20 */ + if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) + { + CyHalt(0x00u); + } + + #endif /* !defined(CY_BOOT_VERSION) */ + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + #endif /* (CY_PSOC4) */ + + + /*********************************************************************** + * Bootloader Application Validation + * + * Halt the device if: + * - A calculated checksum does not match the one stored in the metadata + * section. + * - There is an invalid pointer to the place where the bootloader + * application ends. + * - Flash subsystem was not initialized correctly + ***********************************************************************/ + #if(0u != BL_BOOTLOADER_APP_VALIDATION) + + /* Calculate Bootloader application checksum */ + calcedChecksum = BL_Calc8BitSum(CY_FLASH_BASE, + BL_MD_BTLDR_ADDR_PTR, + *BL_SizeBytesAccess - BL_MD_BTLDR_ADDR_PTR); + + /* we included checksum, so remove it */ + calcedChecksum -= *BL_ChecksumAccess; + calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); + + /* Checksum and pointer to bootloader verification */ + if((calcedChecksum != *BL_ChecksumAccess) || + (0u == *BL_SizeBytesAccess)) + { + CyHalt(0x00u); + } + + #endif /* (0u != BL_BOOTLOADER_APP_VALIDATION) */ + + + /*********************************************************************** + * If the active bootloadable application is invalid or a bootloader + * application is scheduled - do the following: + * - schedule the bootloader application to be run after software reset + * - Go to the communication subroutine. The HostLink() will wait for + * the commands forever. + ***********************************************************************/ + if ((BL_GET_RUN_TYPE == BL_START_BTLDR) || + (CYRET_SUCCESS != validApp)) + { + BL_SET_RUN_TYPE(0u); + + BL_HostLink(BL_WAIT_FOR_COMMAND_FOREVER); + } + + + /* Go to communication subroutine. Will wait for commands for specifed time */ + #if(0u != BL_WAIT_FOR_COMMAND) + + /* Timeout is in 100s of milliseconds */ + BL_HostLink(BL_WAIT_FOR_COMMAND_TIME); + + #endif /* (0u != BL_WAIT_FOR_COMMAND) */ + + + /* Schedule bootloadable application and perform software reset */ + BL_LaunchApplication(); +} + + +/******************************************************************************* +* Function Name: BL_LaunchApplication +******************************************************************************** +* +* Summary: +* Schedules bootloadable application and resets device +* +* Parameters: +* None +* +* Returns: +* This method will never return. +* +*******************************************************************************/ +static void BL_LaunchApplication(void) CYSMALL +{ + /* Schedule Bootloadable to start after reset */ + BL_SET_RUN_TYPE(BL_START_APP); + + CySoftwareReset(); +} + + +/******************************************************************************* +* Function Name: BL_Exit +******************************************************************************** +* +* Summary: +* Schedules the specified application and performs software reset to launch +* a specified application. +* +* If the specified application is not valid, the Bootloader (the result of the +* ValidateBootloadable() function execution returns other than CYRET_SUCCESS, +* the bootloader application is launched. +* +* Parameters: +* appId: application to be started: +* BL_EXIT_TO_BTLDR - Bootloader application will be started on +* software reset. +* BL_EXIT_TO_BTLDB, +* BL_EXIT_TO_BTLDB_1 - Bootloadable application # 1 will be +* started on software reset. +* BL_EXIT_TO_BTLDB_2 - Bootloadable application # 2 will be +* started on software reset. Available only +* if Multi-Application option is enabled in +* the component customizer. +* Returns: +* This function never returns. +* +*******************************************************************************/ +void BL_Exit(uint8 appId) CYSMALL +{ + if(BL_EXIT_TO_BTLDR == appId) + { + BL_SET_RUN_TYPE(0x0u); + } + else + { + if(CYRET_SUCCESS == BL_ValidateBootloadable(appId)) + { + /* Set active application in metadata */ + uint8 CYDATA idx; + for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++) + { + BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx), + (uint8 )(idx == appId)); + } + + #if(0u != BL_DUAL_APP_BOOTLOADER) + BL_activeApp = appId; + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB); + } + else + { + BL_SET_RUN_TYPE(0u); + } + } + + CySoftwareReset(); +} + + +/******************************************************************************* +* Function Name: CyBtldr_CheckLaunch +******************************************************************************** +* +* Summary: +* This routine checks if the bootloader or the bootloadable application has to +* be run. If the application has to be run, it will start executing. +* If the bootloader is to be run, it will return, so the bootloader can +* continue starting up. +* +* Parameters: +* None +* +* Returns: +* It will not return if it determines that the bootloadable application should +* be run. +* +*******************************************************************************/ +void CyBtldr_CheckLaunch(void) CYSMALL +{ + +#if(CY_PSOC4) + + /******************************************************************************* + * Set cyBtldrRunType to zero in case of non-software reset occurred. This means + * that bootloader application is scheduled - that is initial clean state. The + * value of cyBtldrRunType is valid only in case of software reset. + *******************************************************************************/ + if (0u == (BL_RES_CAUSE_REG & BL_RES_CAUSE_RESET_SOFT)) + { + cyBtldrRunType = 0u; + } + +#endif /* (CY_PSOC4) */ + + + if (BL_GET_RUN_TYPE == BL_START_APP) + { + BL_SET_RUN_TYPE(0u); + + /******************************************************************************* + * Indicates that we have told ourselves to jump to the application since we have + * already told ourselves to jump, we do not do any expensive verification of the + * application. We just check to make sure that the value at CY_APP_ADDR_ADDRESS + * is something other than 0. + *******************************************************************************/ + if(0u != BL_GetMetadata(BL_GET_BTLDB_ADDR, BL_activeApp)) + { + /* Never return from this method */ + BL_LaunchBootloadable(BL_GetMetadata(BL_GET_BTLDB_ADDR, + BL_activeApp)); + } + } +} + + +/* Moves argument appAddr (RO) into PC, moving execution to appAddr */ +#if defined (__ARMCC_VERSION) + + __asm static void BL_LaunchBootloadable(uint32 appAddr) + { + BX R0 + ALIGN + } + +#elif defined(__GNUC__) + + __attribute__((noinline)) /* Workaround for GCC toolchain bug with inlining */ + __attribute__((naked)) + static void BL_LaunchBootloadable(uint32 appAddr) + { + __asm volatile(" BX R0\n"); + } + +#elif defined (__ICCARM__) + + static void BL_LaunchBootloadable(uint32 appAddr) + { + __asm volatile(" BX R0\n"); + } + +#endif /* (__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: BL_ValidateBootloadable +******************************************************************************** +* Summary: +* Performs the bootloadable application validation by calculating the +* application image checksum and comparing it with the checksum value stored +* in the Bootloadable Application Checksum field of the metadata section. +* +* If the Fast bootloadable application validation option is enabled in the +* component customizer and bootloadable application successfully passes +* validation, the Bootloadable Application Verification Status field of the +* metadata section is updated. Refer to the Metadata Layout section for the +* details. +* +* If the Fast bootloadable application validation option is enabled and +* Bootloadable Application Verification Status field of the metadata section +* claims that bootloadable application is valid, the function returns +* CYRET_SUCCESS without further checksum calculation. +* +* Parameters: +* appId: +* The number of the bootloadable application should be 0 for the normal +* bootloader and 0 or 1 for the Multi-Application bootloader. +* +* Returns: +* Returns CYRET_SUCCESS if the specified bootloadable application is valid. +* +*******************************************************************************/ +cystatus BL_ValidateBootloadable(uint8 appId) CYSMALL \ + + { + uint32 CYDATA idx; + + uint32 CYDATA end = BL_FIRST_APP_BYTE(appId) + + BL_GetMetadata(BL_GET_BTLDB_LENGTH, + appId); + + CYBIT valid = 0u; /* Assume bad flash image */ + uint8 CYDATA calcedChecksum = 0u; + + + #if(0u != BL_DUAL_APP_BOOTLOADER) + + if(appId > 1u) + { + return(CYRET_BAD_DATA); + } + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + #if(0u != BL_FAST_APP_VALIDATION) + + + if(BL_GetMetadata(BL_GET_BTLDB_STATUS, appId) == + BL_MD_BTLDB_IS_VERIFIED) + { + return(CYRET_SUCCESS); + } + + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + + /* Calculate checksum of bootloadable image */ + for(idx = BL_FIRST_APP_BYTE(appId); idx < end; ++idx) + { + uint8 CYDATA curByte = BL_GET_CODE_BYTE(idx); + + if((curByte != 0u) && (curByte != 0xFFu)) + { + valid = 1u; + } + + calcedChecksum += curByte; + } + + + /*************************************************************************** + * We do not compute checksum over the meta data section, so no need to + * subtract off App Verified or App Active information here like we do when + * verifying a row. + ***************************************************************************/ + + + #if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) + + /* Add ECC data to checksum */ + idx = ((BL_FIRST_APP_BYTE(appId)) >> 3u); + + /* Flash may run into meta data, so ECC does not use full row */ + end = (end == (CY_FLASH_SIZE - BL_MD_SIZEOF)) + ? (CY_FLASH_SIZE >> 3u) + : (end >> 3u); + + for (; idx < end; ++idx) + { + calcedChecksum += CY_GET_XTND_REG8((volatile uint8 *)(CYDEV_ECC_BASE + idx)); + } + + #endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u)) */ + + + calcedChecksum = ( uint8 )1u + ( uint8 )(~calcedChecksum); + + + if((calcedChecksum != BL_GetMetadata(BL_GET_BTLDB_CHECKSUM, appId)) || + (0u == valid)) + { + return(CYRET_BAD_DATA); + } + + + #if(0u != BL_FAST_APP_VALIDATION) + BL_SetFlashByte((uint32) BL_MD_BTLDB_VERIFIED_OFFSET(appId), + BL_MD_BTLDB_IS_VERIFIED); + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + + return(CYRET_SUCCESS); +} + + +/******************************************************************************* +* Function Name: BL_HostLink +******************************************************************************** +* +* Summary: +* Causes the bootloader to attempt to read data being transmitted by the +* host application. If data is sent from the host, this establishes the +* communication interface to process all requests. +* +* Parameters: +* timeOut: +* The amount of time to listen for data before giving up. Timeout is +* measured in 10s of ms. Use 0 for an infinite wait. +* +* Return: +* None +* +*******************************************************************************/ +static void BL_HostLink(uint8 timeOut) +{ + uint16 CYDATA numberRead; + uint16 CYDATA rspSize; + uint8 CYDATA ackCode; + uint16 CYDATA pktChecksum; + cystatus CYDATA readStat; + uint16 CYDATA pktSize = 0u; + uint16 CYDATA dataOffset = 0u; + uint8 CYDATA timeOutCnt = 10u; + + #if(0u != BL_FAST_APP_VALIDATION) + uint8 CYDATA clearedMetaData = 0u; + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + CYBIT communicationState = BL_COMMUNICATION_STATE_IDLE; + + uint8 packetBuffer[BL_SIZEOF_COMMAND_BUFFER]; + uint8 dataBuffer [BL_SIZEOF_COMMAND_BUFFER]; + + + #if(!CY_PSOC4) + #if(0u == BL_FAST_APP_VALIDATION) + #if !defined(CY_BOOT_VERSION) + + /* Not required with cy_boot 4.20 */ + uint8 CYXDATA BL_flashBuffer[BL_FROW_SIZE]; + + #endif /* !defined(CY_BOOT_VERSION) */ + #endif /* (0u == BL_FAST_APP_VALIDATION) */ + #endif /* (CY_PSOC4) */ + + + + #if(!CY_PSOC4) + #if(0u == BL_FAST_APP_VALIDATION) + + /* Initialize Flash subsystem for non-PSoC 4 devices */ + if (CYRET_SUCCESS != CySetTemp()) + { + CyHalt(0x00u); + } + + #if !defined(CY_BOOT_VERSION) + + /* Not required with cy_boot 4.20 */ + if (CYRET_SUCCESS != CySetFlashEEBuffer(BL_flashBuffer)) + { + CyHalt(0x00u); + } + + #endif /* !defined(CY_BOOT_VERSION) */ + #endif /* (0u == BL_FAST_APP_VALIDATION) */ + #endif /* (CY_PSOC4) */ + + /* Initialize communications channel. */ + CyBtldrCommStart(); + + /* Enable global interrupts */ + CyGlobalIntEnable; + + do + { + ackCode = CYRET_SUCCESS; + + do + { + readStat = CyBtldrCommRead(packetBuffer, + BL_SIZEOF_COMMAND_BUFFER, + &numberRead, + (0u == timeOut) ? 0xFFu : timeOut); + if (0u != timeOut) + { + timeOutCnt--; + } + + } while ( (0u != timeOutCnt) && (readStat != CYRET_SUCCESS) ); + + + if( readStat != CYRET_SUCCESS ) + { + continue; + } + + if((numberRead < BL_MIN_PKT_SIZE) || + (packetBuffer[BL_SOP_ADDR] != BL_SOP)) + { + ackCode = BL_ERR_DATA; + } + else + { + pktSize = ((uint16)((uint16)packetBuffer[BL_SIZE_ADDR + 1u] << 8u)) | + packetBuffer[BL_SIZE_ADDR]; + + pktChecksum = ((uint16)((uint16)packetBuffer[BL_CHK_ADDR(pktSize) + 1u] << 8u)) | + packetBuffer[BL_CHK_ADDR(pktSize)]; + + if((pktSize + BL_MIN_PKT_SIZE) > numberRead) + { + ackCode = BL_ERR_LENGTH; + } + else if(packetBuffer[BL_EOP_ADDR(pktSize)] != BL_EOP) + { + ackCode = BL_ERR_DATA; + } + else if(pktChecksum != BL_CalcPacketChecksum(packetBuffer, + pktSize + BL_DATA_ADDR)) + { + ackCode = BL_ERR_CHECKSUM; + } + else + { + /* Empty section */ + } + } + + rspSize = 0u; + if(ackCode == CYRET_SUCCESS) + { + uint8 CYDATA btldrData = packetBuffer[BL_DATA_ADDR]; + + ackCode = BL_ERR_DATA; + switch(packetBuffer[BL_CMD_ADDR]) + { + + + /*************************************************************************** + * Get metadata + ***************************************************************************/ + #if(0u != BL_CMD_GET_METADATA) + + case BL_COMMAND_GET_METADATA: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + if (btldrData >= BL_MAX_NUM_OF_BTLDB) + { + ackCode = BL_ERR_APP; + } + else if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) + { + #if(CY_PSOC3) + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + ((uint8 CYCODE *) (BL_META_BASE(btldrData))), + BL_GET_METADATA_RESPONSE_SIZE); + #else + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + (uint8 *) BL_META_BASE(btldrData), + BL_GET_METADATA_RESPONSE_SIZE); + #endif /* (CY_PSOC3) */ + + rspSize = 56u; + ackCode = CYRET_SUCCESS; + } + else + { + ackCode = BL_ERR_APP; + } + } + break; + + #endif /* (0u != BL_CMD_GET_METADATA) */ + + + /*************************************************************************** + * Verify checksum + ***************************************************************************/ + case BL_COMMAND_CHECKSUM: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 0u)) + { + packetBuffer[BL_DATA_ADDR] = + (uint8)(BL_ValidateBootloadable(BL_activeApp) == CYRET_SUCCESS); + + rspSize = 1u; + ackCode = CYRET_SUCCESS; + } + break; + + + /*************************************************************************** + * Get flash size + ***************************************************************************/ + + /* Replace BL_NUM_OF_FLASH_ARRAYS with CY_FLASH_NUMBER_ARRAYS */ + + + #if(0u != BL_CMD_GET_FLASH_SIZE_AVAIL) + + case BL_COMMAND_REPORT_SIZE: + + /* btldrData - holds flash array ID sent by host */ + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + if(btldrData < CY_FLASH_NUMBER_ARRAYS) + { + uint16 CYDATA startRow; + uint8 CYDATA ArrayIdBtlderEnds; + + + /******************************************************************************* + * - For the flash array where bootloader application ends, return the first + * full row after the bootloader application. + * + * - For the fully occupied flash array, the number of rows in array is returned. + * As there is no space for the bootloadable application in this array. + * + * - For the arrays next to the occupied array, zero is returned. + * The bootloadable application can written from the their beginning. + * + *******************************************************************************/ + ArrayIdBtlderEnds = (uint8) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ARRAY); + + if (btldrData == ArrayIdBtlderEnds) + { + startRow = (uint16) (*BL_SizeBytesAccess / CY_FLASH_SIZEOF_ROW) % + BL_NUMBER_OF_ROWS_IN_ARRAY; + } + else if (btldrData > ArrayIdBtlderEnds) + { + startRow = BL_FIRST_ROW_IN_ARRAY; + } + else /* (btldrData < ArrayIdBtlderEnds) */ + { + startRow = BL_NUMBER_OF_ROWS_IN_ARRAY; + } + + packetBuffer[BL_DATA_ADDR] = LO8(startRow); + packetBuffer[BL_DATA_ADDR + 1u] = HI8(startRow); + + packetBuffer[BL_DATA_ADDR + 2u] = + LO8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u); + + packetBuffer[BL_DATA_ADDR + 3u] = + HI8(BL_NUMBER_OF_ROWS_IN_ARRAY - 1u); + + rspSize = 4u; + ackCode = CYRET_SUCCESS; + } + + } + break; + + #endif /* (0u != BL_CMD_GET_FLASH_SIZE_AVAIL) */ + + + /*************************************************************************** + * Get application status + ***************************************************************************/ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + #if(0u != BL_CMD_GET_APP_STATUS_AVAIL) + + case BL_COMMAND_APP_STATUS: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + + packetBuffer[BL_DATA_ADDR] = + (uint8)BL_ValidateBootloadable(btldrData); + + packetBuffer[BL_DATA_ADDR + 1u] = + (uint8) BL_GetMetadata(BL_GET_BTLDB_ACTIVE, btldrData); + + rspSize = 2u; + ackCode = CYRET_SUCCESS; + } + break; + + #endif /* (0u != BL_CMD_GET_APP_STATUS_AVAIL) */ + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /*************************************************************************** + * Program / Erase row + ***************************************************************************/ + case BL_COMMAND_PROGRAM: + + /* The btldrData variable holds Flash Array ID */ + + #if (0u != BL_CMD_ERASE_ROW_AVAIL) + + case BL_COMMAND_ERASE: + if (BL_COMMAND_ERASE == packetBuffer[BL_CMD_ADDR]) + { + if ((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) + { + #if(!CY_PSOC4) + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + /* Size of EEPROM row */ + dataOffset = CY_EEPROM_SIZEOF_ROW; + } + else + { + /* Size of FLASH row (depends on ECC configuration) */ + dataOffset = BL_FROW_SIZE; + } + #else + /* Size of FLASH row (no ECC available) */ + dataOffset = BL_FROW_SIZE; + #endif /* (!CY_PSOC4) */ + + #if(CY_PSOC3) + (void) memset(dataBuffer, (char8) 0, (int16) dataOffset); + #else + (void) memset(dataBuffer, 0, (uint32) dataOffset); + #endif /* (CY_PSOC3) */ + } + else + { + break; + } + } + + #endif /* (0u != BL_CMD_ERASE_ROW_AVAIL) */ + + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize >= 3u)) + { + + /* The command may be sent along with the last block of data, to program the row. */ + #if(CY_PSOC3) + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR + 3u], + (int16) pktSize - 3); + #else + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR + 3u], + (uint32) pktSize - 3u); + #endif /* (CY_PSOC3) */ + + dataOffset += (pktSize - 3u); + + #if(!CY_PSOC4) + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + + CyEEPROM_Start(); + + /* Size of EEPROM row */ + pktSize = CY_EEPROM_SIZEOF_ROW; + } + else + { + /* Size of FLASH row (depends on ECC configuration) */ + pktSize = BL_FROW_SIZE; + } + #else + /* Size of FLASH row (no ECC available) */ + pktSize = BL_FROW_SIZE; + #endif /* (!CY_PSOC4) */ + + + /* Check if we have all data to program */ + if(dataOffset == pktSize) + { + uint16 row; + uint16 firstRow; + + /* Get FLASH/EEPROM row number inside of the array */ + dataOffset = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | + packetBuffer[BL_DATA_ADDR + 1u]; + + + /* Metadata section resides in Flash (cannot be in EEPROM). */ + #if(!CY_PSOC4) + if(btldrData <= BL_LAST_FLASH_ARRAYID) + { + #endif /* (!CY_PSOC4) */ + + + /* btldrData - holds flash array Id sent by host */ + /* dataOffset - holds flash row Id sent by host */ + row = (uint16)(btldrData * BL_NUMBER_OF_ROWS_IN_ARRAY) + dataOffset; + + + /******************************************************************************* + * Refuse to write to the row within range of the bootloader application + *******************************************************************************/ + + /* First empty flash row after bootloader application */ + firstRow = (uint16) (*BL_SizeBytesAccess / CYDEV_FLS_ROW_SIZE); + if ((*BL_SizeBytesAccess % CYDEV_FLS_ROW_SIZE) != 0u) + { + firstRow++; + } + + /* Check to see if the row to program will not corrupt the bootloader application */ + if(row < firstRow) + { + ackCode = BL_ERR_ROW; + dataOffset = 0u; + break; + } + + + #if(0u != BL_DUAL_APP_BOOTLOADER) + + if(BL_activeApp < BL_MD_BTLDB_ACTIVE_NONE) + { + uint16 lastRow; + + + /******************************************************************************* + * For the first bootloadable application gets the last flash row occupied by + * the bootloader application image: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<--firstRow---|> + * + * For the second bootloadable application gets the last flash row occupied by + * the first bootloadable application: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<-------------firstRow-----------------|> + * + * Incremented by 1 to get the first available row. + * + * Note: M1 and M2 stands for the metadata # 1 and metadata # 2, metadata + * sections for the 1st and 2nd bootloadable applications. + *******************************************************************************/ + firstRow = (uint16) 1u + + (uint16) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, + BL_activeApp); + + + /******************************************************************************* + * The number of flash rows available for the both bootloadable applications: + * + * First bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<-------------------lastRow -------------------->| + * + * Second bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<-------lastRow-------->| + *******************************************************************************/ + lastRow = (uint16)(CY_FLASH_NUMBER_ROWS - + BL_NUMBER_OF_METADATA_ROWS - + firstRow); + + + /******************************************************************************* + * The number of flash rows available for the active bootloadable application: + * + * First bootloadable application is active: the number of flash rows available + * for the both bootloadable applications should be divided by 2 - 2 bootloadable + * applications should fit there. + * + * Second bootloadable application is active: the number of flash rows available + * for the both bootloadable applications should be divided by 1 - 1 bootloadable + * application should fit there. + *******************************************************************************/ + lastRow = lastRow / (BL_NUMBER_OF_BTLDBLE_APPS - + BL_activeApp); + + + /******************************************************************************* + * The last row equals to the first row plus the number of rows available for + * the each bootloadable application. That gives the flash row number right + * beyond the valid range, so we subtract 1. + * + * First bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<----------------lastRow ------------->| + * + * Second bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<-----------------------------lastRow-------------------------->| + *******************************************************************************/ + lastRow = (firstRow + lastRow) - 1u; + + + /******************************************************************************* + * 1. Refuse to write row within the range of the active application + * + * First bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<----------------lastRow ------------->| + * |<--firstRow---|> + * |<-------protected------>| + * + * Second bootloadable application is active: + * --------------------------------------------------------------------------- + * | Bootloader | Bootloadable # 1 | | Bootloadable # 2 | | M2 | M1 | + * --------------------------------------------------------------------------- + * |<-------------firstRow-----------------|> + * |<-----------------------------lastRow-------------------------->| + * |<-------protected------>| + * + * 2. Refuse to write to the row that contains metadata of the active + * bootloadable application. + * + *******************************************************************************/ + if(((row >= firstRow) && (row <= lastRow)) || + ((btldrData == BL_MD_FLASH_ARRAY_NUM) && + (dataOffset == BL_MD_ROW_NUM(BL_activeApp)))) + { + ackCode = BL_ERR_ACTIVE; + dataOffset = 0u; + break; + } + } + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + + /******************************************************************************* + * Clear row that contains the metadata, when 'Fast bootloadable application + * validation' option is enabled. + * + * If 'Fast bootloadable application validation' option is enabled, the + * bootloader only computes the checksum the first time and assumes that it + * remains valid in each future startup. The metadata row is cleared because the + * bootloadable application might become corrupted during update, while + * 'Bootloadable Application Verification Status' field will still report that + * application is valid. + *******************************************************************************/ + #if(0u != BL_FAST_APP_VALIDATION) + + if(0u == clearedMetaData) + { + /* Metadata section must be filled with zeros */ + + uint8 erase[BL_FROW_SIZE]; + uint8 BL_notActiveApp; + + + #if(CY_PSOC3) + (void) memset(erase, (char8) 0, (int16) BL_FROW_SIZE); + #else + (void) memset(erase, 0, BL_FROW_SIZE); + #endif /* (CY_PSOC3) */ + + + #if(0u != BL_DUAL_APP_BOOTLOADER) + if (BL_MD_BTLDB_ACTIVE_0 == BL_activeApp) + { + BL_notActiveApp = BL_MD_BTLDB_ACTIVE_1; + } + else + { + BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0; + } + #else + BL_notActiveApp = BL_MD_BTLDB_ACTIVE_0; + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + #if(CY_PSOC4) + (void) CySysFlashWriteRow( + BL_MD_ROW_NUM(BL_notActiveApp), + erase); + #else + (void) CyWriteRowFull( + (uint8) BL_MD_FLASH_ARRAY_NUM, + (uint16) BL_MD_ROW_NUM(BL_notActiveApp), + erase, + BL_FROW_SIZE); + #endif /* (CY_PSOC4) */ + + /* PSoC 5: Do not care about flushing the cache as flash row has been erased. */ + + /* Set up flag that metadata was cleared */ + clearedMetaData = 1u; + } + + #endif /* (0u != BL_FAST_APP_VALIDATION) */ + + + #if(!CY_PSOC4) + } /* (btldrData <= BL_LAST_FLASH_ARRAYID) */ + #endif /* (!CY_PSOC4) */ + + + #if(CY_PSOC4) + ackCode = (CYRET_SUCCESS != CySysFlashWriteRow((uint32) row, dataBuffer)) \ + ? BL_ERR_ROW \ + : CYRET_SUCCESS; + #else + ackCode = (CYRET_SUCCESS != CyWriteRowFull(btldrData, dataOffset, dataBuffer, pktSize)) \ + ? BL_ERR_ROW \ + : CYRET_SUCCESS; + #endif /* (CY_PSOC4) */ + + + #if(CY_PSOC5) + /*************************************************************************** + * When writing Flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * Flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from Flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ + + } + else + { + ackCode = BL_ERR_LENGTH; + } + + dataOffset = 0u; + } + break; + + + /*************************************************************************** + * Sync bootloader + ***************************************************************************/ + #if(0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) + + case BL_COMMAND_SYNC: + + if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) + { + /* If something failed the host would send this command to reset the bootloader. */ + dataOffset = 0u; + + /* Don't acknowledge the packet, just get ready to accept the next one */ + continue; + } + break; + + #endif /* (0u != BL_CMD_SYNC_BOOTLOADER_AVAIL) */ + + + /*************************************************************************** + * Set an active application + ***************************************************************************/ + #if(0u != BL_DUAL_APP_BOOTLOADER) + + case BL_COMMAND_APP_ACTIVE: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 1u)) + { + if(CYRET_SUCCESS == BL_ValidateBootloadable(btldrData)) + { + uint8 CYDATA idx; + + for(idx = 0u; idx < BL_MAX_NUM_OF_BTLDB; idx++) + { + BL_SetFlashByte((uint32) BL_MD_BTLDB_ACTIVE_OFFSET(idx), + (uint8 )(idx == btldrData)); + } + BL_activeApp = btldrData; + ackCode = CYRET_SUCCESS; + } + else + { + ackCode = BL_ERR_APP; + } + } + break; + + #endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + + /*************************************************************************** + * Send data + ***************************************************************************/ + #if (0u != BL_CMD_SEND_DATA_AVAIL) + + case BL_COMMAND_DATA: + + if(BL_COMMUNICATION_STATE_ACTIVE == communicationState) + { + /* Make sure that dataOffset is valid before copying the data */ + if((dataOffset + pktSize) <= BL_SIZEOF_COMMAND_BUFFER) + { + ackCode = CYRET_SUCCESS; + + #if(CY_PSOC3) + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR], + ( int16 )pktSize); + #else + (void) memcpy(&dataBuffer[dataOffset], + &packetBuffer[BL_DATA_ADDR], + (uint32) pktSize); + #endif /* (CY_PSOC3) */ + + dataOffset += pktSize; + } + else + { + ackCode = BL_ERR_LENGTH; + } + } + + break; + + #endif /* (0u != BL_CMD_SEND_DATA_AVAIL) */ + + + /*************************************************************************** + * Enter bootloader + ***************************************************************************/ + case BL_COMMAND_ENTER: + + if(pktSize == 0u) + { + #if(CY_PSOC3) + + BL_ENTER CYDATA BtldrVersion = + {CYSWAP_ENDIAN32(CYDEV_CHIP_JTAG_ID), CYDEV_CHIP_REV_EXPECT, BL_VERSION}; + + #else + + BL_ENTER CYDATA BtldrVersion = + {CYDEV_CHIP_JTAG_ID, CYDEV_CHIP_REV_EXPECT, BL_VERSION}; + + #endif /* (CY_PSOC3) */ + + communicationState = BL_COMMUNICATION_STATE_ACTIVE; + + rspSize = sizeof(BL_ENTER); + + #if(CY_PSOC3) + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + &BtldrVersion, + ( int16 )rspSize); + #else + (void) memcpy(&packetBuffer[BL_DATA_ADDR], + &BtldrVersion, + (uint32) rspSize); + #endif /* (CY_PSOC3) */ + + ackCode = CYRET_SUCCESS; + } + break; + + + /*************************************************************************** + * Verify row + ***************************************************************************/ + #if (0u != BL_CMD_VERIFY_ROW_AVAIL) + + case BL_COMMAND_VERIFY: + + if((BL_COMMUNICATION_STATE_ACTIVE == communicationState) && (pktSize == 3u)) + { + /* Get FLASH/EEPROM row number */ + uint16 CYDATA rowNum = ((uint16)((uint16)packetBuffer[BL_DATA_ADDR + 2u] << 8u)) | + packetBuffer[BL_DATA_ADDR + 1u]; + + #if(!CY_PSOC4) + + uint32 CYDATA rowAddr; + uint8 CYDATA checksum; + + if((btldrData >= BL_FIRST_EE_ARRAYID) && + (btldrData <= BL_LAST_EE_ARRAYID)) + { + /* EEPROM */ + /* Both PSoC 3 and PSoC 5LP architectures have one EEPROM array. */ + rowAddr = (uint32)rowNum * CYDEV_EEPROM_ROW_SIZE; + + checksum = BL_Calc8BitSum(CY_EEPROM_BASE, rowAddr, CYDEV_EEPROM_ROW_SIZE); + } + else + { + /* FLASH */ + rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); + + checksum = BL_Calc8BitSum(CY_FLASH_BASE, rowAddr, CYDEV_FLS_ROW_SIZE); + } + + #else + + uint32 CYDATA rowAddr = ((uint32)btldrData * CYDEV_FLS_SECTOR_SIZE) + + ((uint32)rowNum * CYDEV_FLS_ROW_SIZE); + + uint8 CYDATA checksum = BL_Calc8BitSum(CY_FLASH_BASE, + rowAddr, + CYDEV_FLS_ROW_SIZE); + + #endif /* (!CY_PSOC4) */ + + + /* Calculate checksum on data from ECC */ + #if(!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) + + if(btldrData <= BL_LAST_FLASH_ARRAYID) + { + uint16 CYDATA tmpIndex; + + rowAddr = CYDEV_ECC_BASE + ((uint32)btldrData * (CYDEV_FLS_SECTOR_SIZE / 8u)) + + ((uint32)rowNum * CYDEV_ECC_ROW_SIZE); + + for(tmpIndex = 0u; tmpIndex < CYDEV_ECC_ROW_SIZE; tmpIndex++) + { + checksum += CY_GET_XTND_REG8((uint8 CYFAR *)(rowAddr + tmpIndex)); + } + } + + #endif /* (!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0u) */ + + + /******************************************************************************* + * App Verified & App Active are information that is updated in Flash at runtime. + * Remove these items from the checksum to allow the host to verify everything is + * correct. + ******************************************************************************/ + if((BL_MD_FLASH_ARRAY_NUM == btldrData) && + (BL_CONTAIN_METADATA(rowNum))) + { + + checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_ACTIVE, + BL_GET_APP_ID(rowNum)); + + checksum -= (uint8)BL_GetMetadata(BL_GET_BTLDB_STATUS, + BL_GET_APP_ID(rowNum)); + } + + packetBuffer[BL_DATA_ADDR] = (uint8)1u + (uint8)(~checksum); + ackCode = CYRET_SUCCESS; + rspSize = 1u; + } + break; + + #endif /* (0u != BL_CMD_VERIFY_ROW_AVAIL) */ + + + /*************************************************************************** + * Exit bootloader + ***************************************************************************/ + case BL_COMMAND_EXIT: + + if(CYRET_SUCCESS == BL_ValidateBootloadable(BL_activeApp)) + { + BL_SET_RUN_TYPE(BL_SCHEDULE_BTLDB); + } + + CySoftwareReset(); + + /* Will never get here */ + break; + + + /*************************************************************************** + * Unsupported command + ***************************************************************************/ + default: + ackCode = BL_ERR_CMD; + break; + } + } + + /* Reply with acknowledge or not acknowledge packet */ + (void) BL_WritePacket(ackCode, packetBuffer, rspSize); + + } while ((0u == timeOut) || (BL_COMMUNICATION_STATE_ACTIVE == communicationState)); +} + + +/******************************************************************************* +* Function Name: BL_WritePacket +******************************************************************************** +* +* Summary: +* Creates a bootloader response packet and transmits it back to the bootloader +* host application over the already established communications protocol. +* +* Parameters: +* status: +* The status code to pass back as the second byte of the packet +* buffer: +* The buffer containing the data portion of the packet +* size: +* The number of bytes contained within the buffer to pass back +* +* Return: +* CYRET_SUCCESS if successful. Any other non-zero value if failure occurred. +* +*******************************************************************************/ +static cystatus BL_WritePacket(uint8 status, uint8 buffer[], uint16 size) CYSMALL \ + +{ + uint16 CYDATA checksum; + + /* Start of packet. */ + buffer[BL_SOP_ADDR] = BL_SOP; + buffer[BL_CMD_ADDR] = status; + buffer[BL_SIZE_ADDR] = LO8(size); + buffer[BL_SIZE_ADDR + 1u] = HI8(size); + + /* Compute checksum. */ + checksum = BL_CalcPacketChecksum(buffer, size + BL_DATA_ADDR); + + buffer[BL_CHK_ADDR(size)] = LO8(checksum); + buffer[BL_CHK_ADDR(1u + size)] = HI8(checksum); + buffer[BL_EOP_ADDR(size)] = BL_EOP; + + /* Start packet transmit. */ + return(CyBtldrCommWrite(buffer, size + BL_MIN_PKT_SIZE, &size, 150u)); +} + + +/******************************************************************************* +* Function Name: BL_SetFlashByte +******************************************************************************** +* +* Summary: +* Writes a byte to the specified Flash memory location. +* +* Parameters: +* address: +* The address in Flash memory where data will be written +* +* runType: +* Byte to be written +* +* Return: +* None +* +*******************************************************************************/ +void BL_SetFlashByte(uint32 address, uint8 runType) +{ + uint32 flsAddr = address - CYDEV_FLASH_BASE; + uint8 rowData[CYDEV_FLS_ROW_SIZE]; + + #if !(CY_PSOC4) + uint8 arrayId = ( uint8 )(flsAddr / CYDEV_FLS_SECTOR_SIZE); + #endif /* !(CY_PSOC4) */ + + #if (CY_PSOC4) + uint16 rowNum = ( uint16 )(flsAddr / CYDEV_FLS_ROW_SIZE); + #else + uint16 rowNum = ( uint16 )((flsAddr % CYDEV_FLS_SECTOR_SIZE) / CYDEV_FLS_ROW_SIZE); + #endif /* (CY_PSOC4) */ + + uint32 baseAddr = address - (address % CYDEV_FLS_ROW_SIZE); + uint16 idx; + + for(idx = 0u; idx < CYDEV_FLS_ROW_SIZE; idx++) + { + rowData[idx] = BL_GET_CODE_BYTE(baseAddr + idx); + } + + rowData[address % CYDEV_FLS_ROW_SIZE] = runType; + + #if(CY_PSOC4) + (void) CySysFlashWriteRow((uint32) rowNum, rowData); + #else + (void) CyWriteRowData(arrayId, rowNum, rowData); + #endif /* (CY_PSOC4) */ + + #if(CY_PSOC5) + /*************************************************************************** + * When writing Flash, data in the instruction cache can become stale. + * Therefore, the cache data does not correlate to the data just written to + * Flash. A call to CyFlushCache() is required to invalidate the data in the + * cache and force fresh information to be loaded from Flash. + ***************************************************************************/ + CyFlushCache(); + #endif /* (CY_PSOC5) */ +} + + +/******************************************************************************* +* Function Name: BL_GetMetadata +******************************************************************************** +* +* Summary: +* Returns the value of the specified field of the metadata section. +* +* Parameters: +* field: +* The field to get data from: +* BL_GET_BTLDB_CHECKSUM - Bootloadable Application Checksum +* BL_GET_BTLDB_ADDR - Bootloadable Application Start +* Routine Address +* BL_GET_BTLDR_LAST_ROW - Bootloader Last Flash Row +* BL_GET_BTLDB_LENGTH - Bootloadable Application Length +* BL_GET_BTLDB_ACTIVE - Active Bootloadable Application +* BL_GET_BTLDB_STATUS - Bootloadable Application +* Verification Status +* BL_GET_BTLDR_APP_VERSION - Bootloader Application Version +* BL_GET_BTLDB_APP_VERSION - Bootloadable Application Version +* BL_GET_BTLDB_APP_ID - Bootloadable Application ID +* BL_GET_BTLDB_APP_CUST_ID - Bootloadable Application Custom ID +* +* appId: +* Number of the bootlodable application. Should be 0 for the normal +* bootloader and 0 or 1 for the Multi-Application bootloader. +* +* Return: +* The value of the specified field of the specified application. +* +*******************************************************************************/ +uint32 BL_GetMetadata(uint8 field, uint8 appId) +{ + uint32 fieldPtr; + uint8 fieldSize = 2u; + uint32 result = 0u; + + switch (field) + { + case BL_GET_BTLDB_CHECKSUM: + fieldPtr = BL_MD_BTLDB_CHECKSUM_OFFSET(appId); + fieldSize = 1u; + break; + + case BL_GET_BTLDB_ADDR: + fieldPtr = BL_MD_BTLDB_ADDR_OFFSET(appId); + #if(!CY_PSOC3) + fieldSize = 4u; + #endif /* (!CY_PSOC3) */ + break; + + case BL_GET_BTLDR_LAST_ROW: + fieldPtr = BL_MD_BTLDR_LAST_ROW_OFFSET(appId); + break; + + case BL_GET_BTLDB_LENGTH: + fieldPtr = BL_MD_BTLDB_LENGTH_OFFSET(appId); + #if(!CY_PSOC3) + fieldSize = 4u; + #endif /* (!CY_PSOC3) */ + break; + + case BL_GET_BTLDB_ACTIVE: + fieldPtr = BL_MD_BTLDB_ACTIVE_OFFSET(appId); + fieldSize = 1u; + break; + + case BL_GET_BTLDB_STATUS: + fieldPtr = BL_MD_BTLDB_VERIFIED_OFFSET(appId); + fieldSize = 1u; + break; + + case BL_GET_BTLDB_APP_VERSION: + fieldPtr = BL_MD_BTLDB_APP_VERSION_OFFSET(appId); + break; + + case BL_GET_BTLDR_APP_VERSION: + fieldPtr = BL_MD_BTLDR_APP_VERSION_OFFSET(appId); + break; + + case BL_GET_BTLDB_APP_ID: + fieldPtr = BL_MD_BTLDB_APP_ID_OFFSET(appId); + break; + + case BL_GET_BTLDB_APP_CUST_ID: + fieldPtr = BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId); + fieldSize = 4u; + break; + + default: + /* Should never be here */ + CYASSERT(0u != 0u); + fieldPtr = 0u; + break; + } + + + if (1u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)fieldPtr); + } + + #if(CY_PSOC3) /* Big-endian */ + + if (2u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 8u; + } + + if (4u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 8u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 16u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )) << 24u; + } + + #else /* PSoC 4 and PSoC 5: Little-endian */ + + if (2u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr )); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *) (fieldPtr + 1u)) << 8u; + } + + if (4u == fieldSize) + { + result = (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr )); + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 1u)) << 8u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 2u)) << 16u; + result |= (uint32) CY_GET_XTND_REG8((volatile uint8 *)(fieldPtr + 3u)) << 24u; + } + + #endif /* (CY_PSOC3) */ + + return (result); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h new file mode 100644 index 0000000..ece5988 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL.h @@ -0,0 +1,355 @@ +/******************************************************************************* +* File Name: BL.h +* Version 1.30 +* +* Description: +* Provides an API for the Bootloader. The API includes functions for starting +* boot loading operations, validating the application and jumping to the +* application. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOTLOADER_BL_H) +#define CY_BOOTLOADER_BL_H + +#include "cytypes.h" +#include "CyFlash.h" + +#define BL_DUAL_APP_BOOTLOADER (0u) +#define BL_BOOTLOADER_APP_VERSION (20736u) +#define BL_FAST_APP_VALIDATION (1u) +#define BL_PACKET_CHECKSUM_CRC (0u) +#define BL_WAIT_FOR_COMMAND (0u) +#define BL_WAIT_FOR_COMMAND_TIME (20u) +#define BL_BOOTLOADER_APP_VALIDATION (1u) + +#define BL_CMD_GET_FLASH_SIZE_AVAIL (1u) +#define BL_CMD_ERASE_ROW_AVAIL (1u) +#define BL_CMD_VERIFY_ROW_AVAIL (1u) +#define BL_CMD_SYNC_BOOTLOADER_AVAIL (1u) +#define BL_CMD_SEND_DATA_AVAIL (1u) +#define BL_CMD_GET_METADATA (0u) + +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_CMD_GET_APP_STATUS_AVAIL (1u) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Bootloadable applications identification +*******************************************************************************/ +#define BL_MD_BTLDB_ACTIVE_0 (0x00u) +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_MD_BTLDB_ACTIVE_1 (0x01u) + #define BL_MD_BTLDB_ACTIVE_NONE (0x02u) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/* Mask used to indicate starting application */ +#define BL_SCHEDULE_BTLDB (0x80u) +#define BL_SCHEDULE_BTLDR (0x40u) +#define BL_SCHEDULE_MASK (0xC0u) + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ +extern const uint8 CYCODE BL_Checksum; +extern const uint8 CYCODE *BL_ChecksumAccess; + + +#if defined(__ARMCC_VERSION) || defined (__GNUC__) + __attribute__((section (".bootloader"))) +#elif defined (__ICCARM__) + #pragma location=".bootloader" +#endif /* defined(__ARMCC_VERSION) || defined (__GNUC__) */ +extern const uint32 CYCODE BL_SizeBytes; +extern const uint32 CYCODE *BL_SizeBytesAccess; + + +/******************************************************************************* +* This variable is used by Bootloader/Bootloadable components to schedule what +* application will be started after software reset. +*******************************************************************************/ +#if (CY_PSOC4) + #if defined(__ARMCC_VERSION) + __attribute__ ((section(".bootloaderruntype"), zero_init)) + #elif defined (__GNUC__) + __attribute__ ((section(".bootloaderruntype"))) + #elif defined (__ICCARM__) + #pragma location=".bootloaderruntype" + #endif /* defined(__ARMCC_VERSION) */ + extern volatile uint32 cyBtldrRunType; +#endif /* (CY_PSOC4) */ + + +#if(0u != BL_DUAL_APP_BOOTLOADER) + extern uint8 BL_activeApp; +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +#if(CY_PSOC4) + /* Reset Cause Observation Register */ + #define BL_RES_CAUSE_REG (* (reg32 *) CYREG_RES_CAUSE) + #define BL_RES_CAUSE_PTR ( (reg32 *) CYREG_RES_CAUSE) +#else + #define BL_RESET_SR0_REG (* (reg8 *) CYREG_RESET_SR0) + #define BL_RESET_SR0_PTR ( (reg8 *) CYREG_RESET_SR0) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Get the reason of the device reset +* Return cyBtldrRunType in the case if software reset was the reset reason and +* set cyBtldrRunType to zero (bootloader application is scheduled - that is +* the initial clean state) and return zero. +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_GET_RUN_TYPE (cyBtldrRunType) +#else + #define BL_GET_RUN_TYPE (BL_RESET_SR0_REG & BL_SCHEDULE_MASK) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* Schedule Bootloader/Bootloadable to be run after software reset +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_SET_RUN_TYPE(x) (cyBtldrRunType = (x)) +#else + #define BL_SET_RUN_TYPE(x) (BL_RESET_SR0_REG = (x)) +#endif /* (CY_PSOC4) */ + + +/* Returns the number of Flash arrays available in the device */ +#ifndef CY_FLASH_NUMBER_ARRAYS + #define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) +#endif /* CY_FLASH_NUMBER_ARRAYS */ + + +/******************************************************************************* +* External References +*******************************************************************************/ +void BL_SetFlashByte(uint32 address, uint8 runType); +void CyBtldr_CheckLaunch(void) CYSMALL ; +void BL_Start(void) CYSMALL ; +cystatus BL_ValidateBootloadable(uint8 appId) \ + CYSMALL ; +uint8 BL_Calc8BitSum(uint32 baseAddr, uint32 start, uint32 size) CYSMALL \ + ; +uint32 BL_GetMetadata(uint8 field, uint8 appId) \ + ; +void BL_Exit(uint8 appId) CYSMALL ; + +#if(CY_PSOC3) + /* Implementation for the PSoC 3 resides in a BL_psoc3.a51 file. */ + void BL_LaunchBootloadable(uint32 appAddr); +#endif /* (CY_PSOC3) */ + +/* When using a custom interface as the IO Component, the user must provide these functions */ +#if defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) + + extern void CyBtldrCommStart(void); + extern void CyBtldrCommStop (void); + extern void CyBtldrCommReset(void); + extern cystatus CyBtldrCommWrite(uint8* buffer, uint16 size, uint16* count, uint8 timeOut); + extern cystatus CyBtldrCommRead (uint8* buffer, uint16 size, uint16* count, uint8 timeOut); + +#endif /* defined(CYDEV_BOOTLOADER_IO_COMP) && (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface) */ + + +/******************************************************************************* +* BL_GetMetadata() +*******************************************************************************/ +#define BL_GET_BTLDB_CHECKSUM (1u) +#define BL_GET_BTLDB_ADDR (2u) +#define BL_GET_BTLDR_LAST_ROW (3u) +#define BL_GET_BTLDB_LENGTH (4u) +#define BL_GET_BTLDB_ACTIVE (5u) +#define BL_GET_BTLDB_STATUS (6u) +#define BL_GET_BTLDR_APP_VERSION (7u) +#define BL_GET_BTLDB_APP_VERSION (8u) +#define BL_GET_BTLDB_APP_ID (9u) +#define BL_GET_BTLDB_APP_CUST_ID (10u) + +#define BL_GET_METADATA_RESPONSE_SIZE (56u) + +/******************************************************************************* +* BL_Exit() +*******************************************************************************/ +#define BL_EXIT_TO_BTLDR (2u) +#define BL_EXIT_TO_BTLDB (0u) +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_EXIT_TO_BTLDB_1 (0u) + #define BL_EXIT_TO_BTLDB_2 (1u) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Kept for backward compatibility. +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) + #define BL_ValidateApplication() \ + BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) +#else + #define BL_ValidateApplication() \ + BL_ValidateBootloadable(BL_MD_BTLDB_ACTIVE_0) + #define BL_ValidateApp(x) BL_ValidateBootloadable((x)) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ +#define BL_Calc8BitFlashSum(start, size) BL_Calc8BitSum(CY_FLASH_BASE, (start), (size)) + + +/******************************************************************************* +* The following code is DEPRECATED and must not be used. +*******************************************************************************/ +#define BL_BOOTLOADABLE_APP_VALID (BL_BOOTLOADER_APP_VALIDATION) +#define CyBtldr_Start BL_Start + +#define BL_NUM_OF_FLASH_ARRAYS (CYDEV_FLASH_SIZE / CYDEV_FLS_SECTOR_SIZE) +#define BL_META_BASE(x) (CYDEV_FLASH_BASE + \ + (CYDEV_FLASH_SIZE - (( uint32 )(x) * CYDEV_FLS_ROW_SIZE) - \ + BL_META_DATA_SIZE)) +#define BL_META_ARRAY (BL_NUM_OF_FLASH_ARRAYS - 1u) +#define BL_META_APP_ENTRY_POINT_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ADDR_OFFSET) +#define BL_META_APP_BYTE_LEN(x) (BL_META_BASE(x) + \ + BL_META_APP_BYTE_LEN_OFFSET) +#define BL_META_APP_RUN_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_RUN_TYPE_OFFSET) +#define BL_META_APP_ACTIVE_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ACTIVE_OFFSET) +#define BL_META_APP_VERIFIED_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_VERIFIED_OFFSET) +#define BL_META_APP_BLDBL_VER_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_BL_BUILD_VER_OFFSET) +#define BL_META_APP_VER_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_VER_OFFSET) +#define BL_META_APP_ID_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_ID_OFFSET) +#define BL_META_APP_CUST_ID_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_CUST_ID_OFFSET) +#define BL_META_LAST_BLDR_ROW_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_BL_LAST_ROW_OFFSET) +#define BL_META_CHECKSUM_ADDR(x) (BL_META_BASE(x) + \ + BL_META_APP_CHECKSUM_OFFSET) +#if(0u == BL_DUAL_APP_BOOTLOADER) + #define BL_MD_BASE BL_META_BASE(0u) + + #if(!CY_PSOC4) + #define BL_MD_ROW ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ + - 1u) + #else + #define BL_MD_ROW (CY_FLASH_NUMBER_ROWS - 1u) + #endif /* (CY_PSOC4) */ + + #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(0u) + #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(0u) + #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(0u) + #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(0u) + #define BL_MD_APP_ENTRY_POINT_ADDR BL_META_APP_ENTRY_POINT_ADDR(0u) + #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(0u) +#else + #if(!CY_PSOC4) + #define BL_MD_ROW(x) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) \ + - 1u - ( uint32 )(x)) + #else + #define BL_MD_ROW(x) (CY_FLASH_NUMBER_ROWS - 1u - ( uint32 )(x)) + #endif /* (CY_PSOC4) */ + + #define BL_MD_CHECKSUM_ADDR BL_META_CHECKSUM_ADDR(appId) + #define BL_MD_LAST_BLDR_ROW_ADDR BL_META_LAST_BLDR_ROW_ADDR(appId) + #define BL_MD_APP_BYTE_LEN BL_META_APP_BYTE_LEN(appId) + #define BL_MD_APP_VERIFIED_ADDR BL_META_APP_VERIFIED_ADDR(appId) + #define BL_MD_APP_ENTRY_POINT_ADDR \ + BL_META_APP_ENTRY_POINT_ADDR(BL_activeApp) + #define BL_MD_APP_RUN_ADDR BL_META_APP_RUN_ADDR(BL_activeApp) +#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + +#define BL_P_APP_ACTIVE(x) ((uint8 CYCODE *) BL_META_APP_ACTIVE_ADDR(x)) +#define BL_MD_PTR_CHECKSUM ((uint8 CYCODE *) BL_MD_CHECKSUM_ADDR) +#define BL_MD_PTR_APP_ENTRY_POINT ((BL_APP_ADDRESS CYCODE *) \ + BL_MD_APP_ENTRY_POINT_ADDR) +#define BL_MD_PTR_LAST_BLDR_ROW ((uint16 CYCODE *) BL_MD_LAST_BLDR_ROW_ADDR) +#define BL_MD_PTR_APP_BYTE_LEN ((BL_APP_ADDRESS CYCODE *) \ + BL_MD_APP_BYTE_LEN) +#define BL_MD_PTR_APP_RUN_ADDR ((uint8 CYCODE *) BL_MD_APP_RUN_ADDR) +#define BL_MD_PTR_APP_VERIFIED ((uint8 CYCODE *) BL_MD_APP_VERIFIED_ADDR) +#define BL_MD_PTR_APP_BLD_BL_VER ((uint16 CYCODE *) BL_MD_APP_BLDBL_VER_ADDR) +#define BL_MD_PTR_APP_VER ((uint16 CYCODE *) BL_MD_APP_VER_ADDR) +#define BL_MD_PTR_APP_ID ((uint16 CYCODE *) BL_MD_APP_ID_ADDR) +#define BL_MD_PTR_APP_CUST_ID ((uint32 CYCODE *) BL_MD_APP_CUST_ID_ADDR) +#if(CY_PSOC3) + #define BL_APP_ADDRESS uint16 + #define BL_GET_CODE_DATA(idx) (*((uint8 CYCODE *) (idx))) + #define BL_GET_CODE_WORD(idx) (*((uint32 CYCODE *) (idx))) + #define BL_META_APP_ADDR_OFFSET (3u) + #define BL_META_APP_BL_LAST_ROW_OFFSET (7u) + #define BL_META_APP_BYTE_LEN_OFFSET (11u) + #define BL_META_APP_RUN_TYPE_OFFSET (15u) +#else + #define BL_APP_ADDRESS uint32 + #define BL_GET_CODE_DATA(idx) (*((uint8 *)(CYDEV_FLASH_BASE + (idx)))) + #define BL_GET_CODE_WORD(idx) (*((uint32 *)(CYDEV_FLASH_BASE + (idx)))) + #define BL_META_APP_ADDR_OFFSET (1u) + #define BL_META_APP_BL_LAST_ROW_OFFSET (5u) + #define BL_META_APP_BYTE_LEN_OFFSET (9u) + #define BL_META_APP_RUN_TYPE_OFFSET (13u) +#endif /* (CY_PSOC3) */ +#define BL_META_APP_ACTIVE_OFFSET (16u) +#define BL_META_APP_VERIFIED_OFFSET (17u) +#define BL_META_APP_BL_BUILD_VER_OFFSET (18u) +#define BL_META_APP_ID_OFFSET (20u) +#define BL_META_APP_VER_OFFSET (22u) +#define BL_META_APP_CUST_ID_OFFSET (24u) +#if (CY_PSOC4) + #define BL_GET_REG16(x) ((uint16)( \ + (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) ) )) | \ + (( uint16 )(( uint16 )CY_GET_XTND_REG8((x) + 1u) << 8u)) \ + )) + + #define BL_GET_REG32(x) ( \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) ) )) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 1u) << 8u)) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 2u) << 16u)) | \ + (( uint32 )(( uint32 ) CY_GET_XTND_REG8((x) + 3u) << 24u)) \ + ) +#endif /* (CY_PSOC4) */ +#define BL_META_APP_CHECKSUM_OFFSET (0u) +#define BL_META_DATA_SIZE (64u) +#if(CY_PSOC4) + extern uint8 appRunType; +#endif /* (CY_PSOC4) */ + +#if(CY_PSOC4) + #define BL_SOFTWARE_RESET CY_SET_REG32(CYREG_CM0_AIRCR, 0x05FA0004u) +#else + #define BL_SOFTWARE_RESET CY_SET_REG8(CYREG_RESET_CR2, 0x01u) +#endif /* (CY_PSOC4) */ + +#define BL_SetFlashRunType(runType) BL_SetFlashByte( \ + BL_MD_APP_RUN_ADDR(0), (runType)) + +#define BL_START_APP (BL_SCHEDULE_BTLDB) +#define BL_START_BTLDR (BL_SCHEDULE_BTLDR) + +/* Some PSoC Creator versions are used to generate only one name types */ +#if !defined (CYDEV_FLASH_BASE) + #define CYDEV_FLASH_BASE (CYDEV_FLS_BASE) +#endif /* !defined (CYDEV_FLASH_BASE) */ + +#if !defined (CYDEV_FLASH_SIZE) + #define CYDEV_FLASH_SIZE (CYDEV_FLS_SIZE) +#endif /* CYDEV_FLASH_SIZE */ + + +#endif /* CY_BOOTLOADER_BL_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h new file mode 100644 index 0000000..015f378 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BL_PVT.h @@ -0,0 +1,288 @@ +/******************************************************************************* +* File Name: BL_PVT.h +* Version 1.30 +* +* Description: +* Provides an API for the Bootloader. +* +******************************************************************************** +* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOTLOADER_BL_PVT_H) +#define CY_BOOTLOADER_BL_PVT_H + +#include "BL.h" + + +typedef struct +{ + uint32 SiliconId; + uint8 Revision; + uint8 BootLoaderVersion[3u]; + +} BL_ENTER; + + +#define BL_VERSION {\ + (uint8)30, \ + (uint8)1, \ + (uint8)0x01u \ + } + +/* Packet framing constants. */ +#define BL_SOP (0x01u) /* Start of Packet */ +#define BL_EOP (0x17u) /* End of Packet */ + + +/* Bootloader command responses */ +#define BL_ERR_KEY (0x01u) /* The provided key does not match the expected value */ +#define BL_ERR_VERIFY (0x02u) /* The verification of flash failed */ +#define BL_ERR_LENGTH (0x03u) /* The amount of data available is outside the expected range */ +#define BL_ERR_DATA (0x04u) /* The data is not of the proper form */ +#define BL_ERR_CMD (0x05u) /* The command is not recognized */ +#define BL_ERR_DEVICE (0x06u) /* The expected device does not match the detected device */ +#define BL_ERR_VERSION (0x07u) /* The bootloader version detected is not supported */ +#define BL_ERR_CHECKSUM (0x08u) /* The checksum does not match the expected value */ +#define BL_ERR_ARRAY (0x09u) /* The flash array is not valid */ +#define BL_ERR_ROW (0x0Au) /* The flash row is not valid */ +#define BL_ERR_PROTECT (0x0Bu) /* The flash row is protected and can not be programmed */ +#define BL_ERR_APP (0x0Cu) /* The application is not valid and cannot be set as active */ +#define BL_ERR_ACTIVE (0x0Du) /* The application is currently marked as active */ +#define BL_ERR_UNK (0x0Fu) /* An unknown error occurred */ + + +/* Bootloader command definitions. */ +#define BL_COMMAND_CHECKSUM (0x31u) /* Verify the checksum for the bootloadable project */ +#define BL_COMMAND_REPORT_SIZE (0x32u) /* Report the programmable portions of flash */ +#define BL_COMMAND_APP_STATUS (0x33u) /* Gets status info about the provided app status */ +#define BL_COMMAND_ERASE (0x34u) /* Erase the specified flash row */ +#define BL_COMMAND_SYNC (0x35u) /* Sync the bootloader and host application */ +#define BL_COMMAND_APP_ACTIVE (0x36u) /* Sets the active application */ +#define BL_COMMAND_DATA (0x37u) /* Queue up a block of data for programming */ +#define BL_COMMAND_ENTER (0x38u) /* Enter the bootloader */ +#define BL_COMMAND_PROGRAM (0x39u) /* Program the specified row */ +#define BL_COMMAND_VERIFY (0x3Au) /* Compute flash row checksum for verification */ +#define BL_COMMAND_EXIT (0x3Bu) /* Exits the bootloader & resets the chip */ +#define BL_COMMAND_GET_METADATA (0x3Cu) /* Reports the metadata for a selected application */ + + +/******************************************************************************* +* Bootloader packet byte addresses: +* [1-byte] [1-byte ] [2-byte] [n-byte] [ 2-byte ] [1-byte] +* [ SOP ] [Command] [ Size ] [ Data ] [Checksum] [ EOP ] +*******************************************************************************/ +#define BL_SOP_ADDR (0x00u) /* Start of packet offset from beginning */ +#define BL_CMD_ADDR (0x01u) /* Command offset from beginning */ +#define BL_SIZE_ADDR (0x02u) /* Packet size offset from beginning */ +#define BL_DATA_ADDR (0x04u) /* Packet data offset from beginning */ +#define BL_CHK_ADDR(x) (0x04u + (x)) /* Packet checksum offset from end */ +#define BL_EOP_ADDR(x) (0x06u + (x)) /* End of packet offset from end */ +#define BL_MIN_PKT_SIZE (7u) /* The minimum number of bytes in a packet */ + + +/******************************************************************************* +BL_ValidateBootloadable() +*******************************************************************************/ +#define BL_FIRST_APP_BYTE(appId) ((uint32)CYDEV_FLS_ROW_SIZE * \ + ((uint32) BL_GetMetadata(BL_GET_BTLDR_LAST_ROW, appId) + \ + (uint32) 1u)) + +#define BL_MD_BTLDB_IS_VERIFIED (0x01u) + + +/******************************************************************************* +* BL_Start() +*******************************************************************************/ +#define BL_MD_BTLDB_IS_ACTIVE (0x01u) +#define BL_WAIT_FOR_COMMAND_FOREVER (0x00u) + + + /* The maximum number of bytes accepted in a packet plus some */ +#define BL_SIZEOF_COMMAND_BUFFER (300u) + + +/******************************************************************************* +* BL_HostLink() +*******************************************************************************/ +#define BL_COMMUNICATION_STATE_IDLE (0u) +#define BL_COMMUNICATION_STATE_ACTIVE (1u) + +#if(!CY_PSOC4) + + /******************************************************************************* + * The Array ID indicates the unique ID of the SONOS array being accessed: + * - 0x00-0x3E : Flash Arrays + * - 0x3F : Selects all Flash arrays simultaneously + * - 0x40-0x7F : Embedded EEPROM Arrays + *******************************************************************************/ + #define BL_FIRST_FLASH_ARRAYID (0x00u) + #define BL_LAST_FLASH_ARRAYID (0x3Fu) + #define BL_FIRST_EE_ARRAYID (0x40u) + #define BL_LAST_EE_ARRAYID (0x7Fu) + +#endif /* (!CY_PSOC4) */ + + +/******************************************************************************* +* BL_CalcPacketChecksum() +*******************************************************************************/ +#if(0u != BL_PACKET_CHECKSUM_CRC) + #define BL_CRC_CCITT_POLYNOMIAL (0x8408u) /* x^16 + x^12 + x^5 + 1 */ + #define BL_CRC_CCITT_INITIAL_VALUE (0xffffu) +#endif /* (0u != BL_PACKET_CHECKSUM_CRC) */ + + +/******************************************************************************* +* CyBtldr_CheckLaunch() +*******************************************************************************/ +#define BL_RES_CAUSE_RESET_SOFT (0x10u) + + +/******************************************************************************* +* Metadata addresses and pointer defines +*******************************************************************************/ +#define BL_MD_SIZEOF (64u) + + +/******************************************************************************* +* The Metadata base address. In the case of the bootloader application, the +* metadata is placed at row N-1; in the case of the multi-application +* bootloader, the bootloadable application number 1 will use row N-1, and +* application number 2 will use row N-2 to store its metadata, where N is the +* total number of the rows for the selected device. +*******************************************************************************/ +#define BL_MD_BASE_ADDR(appId) (CYDEV_FLASH_BASE + \ + (CYDEV_FLASH_SIZE - ((uint32)(appId) * CYDEV_FLS_ROW_SIZE) - \ + BL_MD_SIZEOF)) + +#define BL_MD_FLASH_ARRAY_NUM (BL_NUM_OF_FLASH_ARRAYS - 1u) + +#if(!CY_PSOC4) + #define BL_MD_ROW_NUM(appId) ((CY_FLASH_NUMBER_ROWS / BL_NUM_OF_FLASH_ARRAYS) - \ + 1u - (uint32)(appId)) +#else + #define BL_MD_ROW_NUM(appId) (CY_FLASH_NUMBER_ROWS - 1u - (uint32)(appId)) +#endif /* (!CY_PSOC4) */ + + +#define BL_MD_BTLDB_CHECKSUM_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 0u) +#if(CY_PSOC3) + #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 3u) + #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 7u) + #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 11u) +#else + #define BL_MD_BTLDB_ADDR_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 1u) + #define BL_MD_BTLDR_LAST_ROW_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 5u) + #define BL_MD_BTLDB_LENGTH_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 9u) +#endif /* (CY_PSOC3) */ +#define BL_MD_BTLDB_ACTIVE_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 16u) +#define BL_MD_BTLDB_VERIFIED_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 17u) +#define BL_MD_BTLDR_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 18u) +#define BL_MD_BTLDB_APP_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 20u) +#define BL_MD_BTLDB_APP_VERSION_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 22u) +#define BL_MD_BTLDB_APP_CUST_ID_OFFSET(appId) (BL_MD_BASE_ADDR(appId) + 24u) + + +/******************************************************************************* +* Get data byte from FLASH +*******************************************************************************/ +#if(CY_PSOC3) + #define BL_GET_CODE_BYTE(addr) (*((uint8 CYCODE *) (addr))) +#else + #define BL_GET_CODE_BYTE(addr) (*((uint8 *)(CYDEV_FLASH_BASE + (addr)))) +#endif /* (CY_PSOC3) */ + + +#if(!CY_PSOC4) + #define BL_GET_EEPROM_BYTE(addr) (*((uint8 *)(CYDEV_EE_BASE + (addr)))) +#endif /* (CY_PSOC3) */ + + +/* Our definition of a row size. */ +#if((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) + #define BL_FROW_SIZE ((CYDEV_FLS_ROW_SIZE) + (CYDEV_ECC_ROW_SIZE)) +#else + #define BL_FROW_SIZE CYDEV_FLS_ROW_SIZE +#endif /* ((!CY_PSOC4) && (CYDEV_ECC_ENABLE == 0)) */ + + +/******************************************************************************* +* Number of addresses remapped from Flash to RAM, when interrupt vectors are +* configured to be stored in RAM (default setting, configured by cy_boot). +*******************************************************************************/ +#if(CY_PSOC4) + #define BL_MD_BTLDR_ADDR_PTR (0xC0u) /* Exclude the vector */ +#else + #define BL_MD_BTLDR_ADDR_PTR (0x00u) +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The maximum number of Bootloadable applications +*******************************************************************************/ +#if(1u == BL_DUAL_APP_BOOTLOADER) + #define BL_MAX_NUM_OF_BTLDB (0x02u) +#else + #define BL_MAX_NUM_OF_BTLDB (0x01u) +#endif /* (1u == BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Returns TRUE if the row specified as a parameter contains a metadata section +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_CONTAIN_METADATA(row) \ + ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) || \ + (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_1) == (row))) +#else + #define BL_CONTAIN_METADATA(row) \ + (BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* The Metadata section is located in the last flash row for the Boootloader, for +* the Multi-Application Bootloader, the metadata section of the Bootloadable +* application # 0 is located in the last flash row, and the metadata section of +* the Bootloadable application # 1 is located in the flash row before last. +*******************************************************************************/ +#if(0u != BL_DUAL_APP_BOOTLOADER) + #define BL_GET_APP_ID(row) \ + ((BL_MD_ROW_NUM(BL_MD_BTLDB_ACTIVE_0) == (row)) ? \ + BL_MD_BTLDB_ACTIVE_0 : \ + BL_MD_BTLDB_ACTIVE_1) +#else + #define BL_GET_APP_ID(row) (BL_MD_BTLDB_ACTIVE_0) +#endif /* (0u != BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Defines the number of flash rows reserved for the metadata section +*******************************************************************************/ +#if(0u == BL_DUAL_APP_BOOTLOADER) + #define BL_NUMBER_OF_METADATA_ROWS (1u) +#else + #define BL_NUMBER_OF_METADATA_ROWS (2u) +#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + + +/******************************************************************************* +* Defines the number of possible bootloadable applications +*******************************************************************************/ +#if(0u == BL_DUAL_APP_BOOTLOADER) + #define BL_NUMBER_OF_BTLDBLE_APPS (1u) +#else + #define BL_NUMBER_OF_BTLDBLE_APPS (2u) +#endif /* (0u == BL_DUAL_APP_BOOTLOADER) */ + +#define BL_NUMBER_OF_ROWS_IN_ARRAY ((uint16)(CY_FLASH_SIZEOF_ARRAY/CY_FLASH_SIZEOF_ROW)) +#define BL_FIRST_ROW_IN_ARRAY (0u) + +#endif /* CY_BOOTLOADER_BL_PVT_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.c new file mode 100644 index 0000000..a38a767 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: BOOTLDR.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "BOOTLDR.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + BOOTLDR__PORT == 15 && ((BOOTLDR__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: BOOTLDR_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet BOOTLDR_SUT.c usage_BOOTLDR_Write +*******************************************************************************/ +void BOOTLDR_Write(uint8 value) +{ + uint8 staticBits = (BOOTLDR_DR & (uint8)(~BOOTLDR_MASK)); + BOOTLDR_DR = staticBits | ((uint8)(value << BOOTLDR_SHIFT) & BOOTLDR_MASK); +} + + +/******************************************************************************* +* Function Name: BOOTLDR_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet BOOTLDR_SUT.c usage_BOOTLDR_SetDriveMode +*******************************************************************************/ +void BOOTLDR_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(BOOTLDR_0, mode); +} + + +/******************************************************************************* +* Function Name: BOOTLDR_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet BOOTLDR_SUT.c usage_BOOTLDR_Read +*******************************************************************************/ +uint8 BOOTLDR_Read(void) +{ + return (BOOTLDR_PS & BOOTLDR_MASK) >> BOOTLDR_SHIFT; +} + + +/******************************************************************************* +* Function Name: BOOTLDR_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred BOOTLDR_Read() API because the +* BOOTLDR_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet BOOTLDR_SUT.c usage_BOOTLDR_ReadDataReg +*******************************************************************************/ +uint8 BOOTLDR_ReadDataReg(void) +{ + return (BOOTLDR_DR & BOOTLDR_MASK) >> BOOTLDR_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(BOOTLDR_INTSTAT) + + /******************************************************************************* + * Function Name: BOOTLDR_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use BOOTLDR_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - BOOTLDR_0_INTR (First pin in the list) + * - BOOTLDR_1_INTR (Second pin in the list) + * - ... + * - BOOTLDR_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet BOOTLDR_SUT.c usage_BOOTLDR_SetInterruptMode + *******************************************************************************/ + void BOOTLDR_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & BOOTLDR_0_INTR) != 0u) + { + BOOTLDR_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: BOOTLDR_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet BOOTLDR_SUT.c usage_BOOTLDR_ClearInterrupt + *******************************************************************************/ + uint8 BOOTLDR_ClearInterrupt(void) + { + return (BOOTLDR_INTSTAT & BOOTLDR_MASK) >> BOOTLDR_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.h new file mode 100644 index 0000000..f42e794 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: BOOTLDR.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_BOOTLDR_H) /* Pins BOOTLDR_H */ +#define CY_PINS_BOOTLDR_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "BOOTLDR_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + BOOTLDR__PORT == 15 && ((BOOTLDR__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void BOOTLDR_Write(uint8 value); +void BOOTLDR_SetDriveMode(uint8 mode); +uint8 BOOTLDR_ReadDataReg(void); +uint8 BOOTLDR_Read(void); +void BOOTLDR_SetInterruptMode(uint16 position, uint16 mode); +uint8 BOOTLDR_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the BOOTLDR_SetDriveMode() function. + * @{ + */ + #define BOOTLDR_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define BOOTLDR_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define BOOTLDR_DM_RES_UP PIN_DM_RES_UP + #define BOOTLDR_DM_RES_DWN PIN_DM_RES_DWN + #define BOOTLDR_DM_OD_LO PIN_DM_OD_LO + #define BOOTLDR_DM_OD_HI PIN_DM_OD_HI + #define BOOTLDR_DM_STRONG PIN_DM_STRONG + #define BOOTLDR_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define BOOTLDR_MASK BOOTLDR__MASK +#define BOOTLDR_SHIFT BOOTLDR__SHIFT +#define BOOTLDR_WIDTH 1u + +/* Interrupt constants */ +#if defined(BOOTLDR__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in BOOTLDR_SetInterruptMode() function. + * @{ + */ + #define BOOTLDR_INTR_NONE (uint16)(0x0000u) + #define BOOTLDR_INTR_RISING (uint16)(0x0001u) + #define BOOTLDR_INTR_FALLING (uint16)(0x0002u) + #define BOOTLDR_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define BOOTLDR_INTR_MASK (0x01u) +#endif /* (BOOTLDR__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define BOOTLDR_PS (* (reg8 *) BOOTLDR__PS) +/* Data Register */ +#define BOOTLDR_DR (* (reg8 *) BOOTLDR__DR) +/* Port Number */ +#define BOOTLDR_PRT_NUM (* (reg8 *) BOOTLDR__PRT) +/* Connect to Analog Globals */ +#define BOOTLDR_AG (* (reg8 *) BOOTLDR__AG) +/* Analog MUX bux enable */ +#define BOOTLDR_AMUX (* (reg8 *) BOOTLDR__AMUX) +/* Bidirectional Enable */ +#define BOOTLDR_BIE (* (reg8 *) BOOTLDR__BIE) +/* Bit-mask for Aliased Register Access */ +#define BOOTLDR_BIT_MASK (* (reg8 *) BOOTLDR__BIT_MASK) +/* Bypass Enable */ +#define BOOTLDR_BYP (* (reg8 *) BOOTLDR__BYP) +/* Port wide control signals */ +#define BOOTLDR_CTL (* (reg8 *) BOOTLDR__CTL) +/* Drive Modes */ +#define BOOTLDR_DM0 (* (reg8 *) BOOTLDR__DM0) +#define BOOTLDR_DM1 (* (reg8 *) BOOTLDR__DM1) +#define BOOTLDR_DM2 (* (reg8 *) BOOTLDR__DM2) +/* Input Buffer Disable Override */ +#define BOOTLDR_INP_DIS (* (reg8 *) BOOTLDR__INP_DIS) +/* LCD Common or Segment Drive */ +#define BOOTLDR_LCD_COM_SEG (* (reg8 *) BOOTLDR__LCD_COM_SEG) +/* Enable Segment LCD */ +#define BOOTLDR_LCD_EN (* (reg8 *) BOOTLDR__LCD_EN) +/* Slew Rate Control */ +#define BOOTLDR_SLW (* (reg8 *) BOOTLDR__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define BOOTLDR_PRTDSI__CAPS_SEL (* (reg8 *) BOOTLDR__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define BOOTLDR_PRTDSI__DBL_SYNC_IN (* (reg8 *) BOOTLDR__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define BOOTLDR_PRTDSI__OE_SEL0 (* (reg8 *) BOOTLDR__PRTDSI__OE_SEL0) +#define BOOTLDR_PRTDSI__OE_SEL1 (* (reg8 *) BOOTLDR__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define BOOTLDR_PRTDSI__OUT_SEL0 (* (reg8 *) BOOTLDR__PRTDSI__OUT_SEL0) +#define BOOTLDR_PRTDSI__OUT_SEL1 (* (reg8 *) BOOTLDR__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define BOOTLDR_PRTDSI__SYNC_OUT (* (reg8 *) BOOTLDR__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(BOOTLDR__SIO_CFG) + #define BOOTLDR_SIO_HYST_EN (* (reg8 *) BOOTLDR__SIO_HYST_EN) + #define BOOTLDR_SIO_REG_HIFREQ (* (reg8 *) BOOTLDR__SIO_REG_HIFREQ) + #define BOOTLDR_SIO_CFG (* (reg8 *) BOOTLDR__SIO_CFG) + #define BOOTLDR_SIO_DIFF (* (reg8 *) BOOTLDR__SIO_DIFF) +#endif /* (BOOTLDR__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(BOOTLDR__INTSTAT) + #define BOOTLDR_INTSTAT (* (reg8 *) BOOTLDR__INTSTAT) + #define BOOTLDR_SNAP (* (reg8 *) BOOTLDR__SNAP) + + #define BOOTLDR_0_INTTYPE_REG (* (reg8 *) BOOTLDR__0__INTTYPE) +#endif /* (BOOTLDR__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_BOOTLDR_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h new file mode 100644 index 0000000..7b8c969 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/BOOTLDR_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: BOOTLDR.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_BOOTLDR_ALIASES_H) /* Pins BOOTLDR_ALIASES_H */ +#define CY_PINS_BOOTLDR_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define BOOTLDR_0 (BOOTLDR__0__PC) +#define BOOTLDR_0_INTR ((uint16)((uint16)0x0001u << BOOTLDR__0__SHIFT)) + +#define BOOTLDR_INTR_ALL ((uint16)(BOOTLDR_0_INTR)) + +#endif /* End Pins BOOTLDR_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf new file mode 100644 index 0000000..5d23335 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Iar.icf @@ -0,0 +1,123 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_ROM_start__ = 0x0; +define symbol __ICFEDIT_region_ROM_end__ = 131072 - 1; +define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (32768 / 2); +define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (32768 / 2) - 1; +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_heap__ = 0x0800; +/**** End of ICF editor section. ###ICF###*/ + + +/******** Definitions ********/ +define symbol CY_APPL_LOADABLE = 0; +define symbol CY_APPL_LOADER = 1; +define symbol CY_APPL_NUM = 1; +define symbol CY_APPL_MAX = 1; +define symbol CY_METADATA_SIZE = 64; +define symbol CY_EE_IN_BTLDR = 0x0; +define symbol CY_EE_SIZE = 2048; + +if (!CY_APPL_LOADABLE) { + define symbol CYDEV_BTLDR_SIZE = 0; +} + +define symbol CY_FLASH_SIZE = 131072; +define symbol CY_APPL_ORIGIN = 0; +define symbol CY_FLASH_ROW_SIZE = 256; +define symbol CY_ECC_ROW_SIZE = 32; + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; +define block HSTACK {block HEAP, last block CSTACK}; + +if (CY_APPL_LOADABLE) +{ +define block LOADER { readonly section .cybootloader }; +} +define block APPL with fixed order {readonly section .romvectors, readonly}; + +/* The address of Flash row next after Bootloader image */ +define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE + + ((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ? + (CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0); + +/* The start address of Standard/Loader/Loadable#1 image */ +define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END; + +/* The number of metadata records located at the end of Flash */ +define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0); + +/* The application area size measured in rows */ +define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT; + +/* The start address of Loadable#2 image if any */ +define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE; + +/* The current image (Standard/Loader/Loadable) start address */ +define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START; + +/* The ECC data placement address */ +define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + +/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */ +define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; +define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + +/* Define EEPROM region */ +define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE]; + +/* Define APPL region that will limit application size */ +define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE]; + + +/****** Initializations ******/ +initialize by copy { readwrite }; +do not initialize { section .noinit }; +do not initialize { readwrite section .ramvectors }; + +/******** Placements *********/ +if (CY_APPL_LOADABLE) +{ +".cybootloader" : place at start of ROM_region {block LOADER}; +} + +"APPL" : place at start of APPL_region {block APPL}; + +"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors }; +"readwrite" : place in RAM_region { readwrite }; +"HSTACK" : place at end of RAM_region { block HSTACK}; + +keep { section .cybootloader, + section .cyloadermeta, + section .cyloadablemeta, + section .cyconfigecc, + section .cycustnvl, + section .cywolatch, + section .cyeeprom, + section .cyflashprotect, + section .cymeta }; + +".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta }; +if (CY_APPL_LOADABLE) +{ +".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta }; +} +".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc }; +".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl }; +".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch }; +".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom }; +".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect }; +".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta }; + + +/* EOF */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat new file mode 100644 index 0000000..951d2af --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3RealView.scat @@ -0,0 +1,190 @@ +#! armcc -E +; The first line specifies a preprocessor command that the linker invokes +; to pass a scatter file through a C preprocessor. + +;******************************************************************************** +;* File Name: Cm3RealView.scat +;* Version 4.20 +;* +;* Description: +;* This Linker Descriptor file describes the memory layout of the PSoC5 +;* device. The memory layout of the final binary and hex images as well as +;* the placement in PSoC5 memory is described. +;* +;* +;* Note: +;* +;* romvectors: Cypress default Interrupt service routine vector table. +;* +;* This is the ISR vector table at bootup. Used only for the reset vector. +;* +;* +;* ramvectors: Cypress ram interrupt service routine vector table. +;* +;* This is the ISR vector table used by the application. +;* +;* +;******************************************************************************** +;* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +;* You may use this file only in accordance with the license, terms, conditions, +;* disclaimers, and limitations in the end user license agreement accompanying +;* the software package with which this file was provided. +;********************************************************************************/ +#include "cyfitter.h" + +#define CY_FLASH_SIZE 131072 +#define CY_APPL_ORIGIN 0 +#define CY_FLASH_ROW_SIZE 256 +#define CY_ECC_ROW_SIZE 32 +#define CY_EE_SIZE 2048 +#define CY_METADATA_SIZE 64 + + +; Define application base address +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + #define CY_APPL_NUM 1 + #define CY_APPL_MAX 1 + #define CY_EE_IN_BTLDR + + #if CY_APPL_ORIGIN + #define APPL1_START CY_APPL_ORIGIN + #else + #define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE) + #endif + + #define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE)) + #define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE) + #define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) + #define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX)) + +#else + + #define APPL_START 0 + #define ECC_OFFSET 0 + #define EE_OFFSET 0 + #define EE_SIZE CY_EE_SIZE + +#endif + + +; Place Bootloader at the beginning of Flash +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYBOOTLOADER 0 + { + .cybootloader +0 + { + * (.cybootloader) + } + } + + #if CY_APPL_ORIGIN + ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER)) + #endif + +#endif + + +APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START) +{ + VECTORS +0 + { + * (.romvectors) + } + + CODE +0 + { + * (+RO) + } + + ISRVECTORS (0x20000000 - (32768 / 2)) UNINIT + { + * (.ramvectors) + } + + NOINIT_DATA +0 UNINIT + { + * (.noinit) + } + + DATA +0 + { + .ANY (+RW, +ZI) + } + + ARM_LIB_HEAP (0x20000000 + (32768 / 2) - 0x0800 - 0x2000) EMPTY 0x0800 + { + } + + ARM_LIB_STACK (0x20000000 + (32768 / 2)) EMPTY -0x2000 + { + } +} + + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER) + + CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE) + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#else + + #if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) + { + .cyloadablemeta +0 { * (.cyloadablemeta) } + } + + #endif + +#endif + +#if (CYDEV_ECC_ENABLE == 0) + + CYCONFIGECC (0x80000000 + ECC_OFFSET) + { + .cyconfigecc +0 { * (.cyconfigecc) } + } + +#endif + +CYCUSTNVL 0x90000000 +{ + .cycustnvl +0 { * (.cycustnvl) } +} + +CYWOLATCH 0x90100000 +{ + .cywolatch +0 { * (.cywolatch) } +} + +#if defined(CYDEV_ALLOCATE_EEPROM) + + CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE) + { + .cyeeprom +0 { * (.cyeeprom) } + } + +#endif + +CYFLASHPROTECT 0x90400000 +{ + .cyflashprotect +0 { * (.cyflashprotect) } +} + +CYMETA 0x90500000 +{ + .cymeta +0 { * (.cymeta) } +} + +#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE) + + CYLOADERMETA +0 + { + .cyloadermeta +0 { * (.cyloadermeta) } + } + +#endif diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c new file mode 100644 index 0000000..55a20e2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/Cm3Start.c @@ -0,0 +1,539 @@ +/******************************************************************************* +* File Name: Cm3Start.c +* Version 4.20 +* +* Description: +* Startup code for the ARM CM3. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "cydevice_trm.h" +#include "cytypes.h" +#include "cyfitter_cfg.h" +#include "CyLib.h" +#include "CyDmac.h" +#include "cyfitter.h" + +#define CY_NUM_INTERRUPTS (32u) +#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS) +#define CY_NUM_ROM_VECTORS (4u) +#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR) +#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL) +#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */ +#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */ +#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */ + + +/* Extern functions */ +extern void CyBtldr_CheckLaunch(void); + +/* Function prototypes */ +void initialize_psoc(void); +CY_ISR(IntDefaultHandler); +void Reset(void); +CY_ISR(IntDefaultHandler); + +#if defined(__ARMCC_VERSION) + #define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit) +#elif defined (__GNUC__) + #define INITIAL_STACK_POINTER (&__cy_stack) +#elif defined (__ICCARM__) + #pragma language=extended + #pragma segment="CSTACK" + #define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) } + + extern void __iar_program_start( void ); + extern void __iar_data_init3 (void); +#endif /* (__ARMCC_VERSION) */ + +#if defined(__GNUC__) + #include + extern int errno; + extern int end; +#endif /* defined(__GNUC__) */ + +/* Global variables */ +#if !defined (__ICCARM__) + CY_NOINIT static uint32 cySysNoInitDataValid; +#endif /* !defined (__ICCARM__) */ + + +/******************************************************************************* +* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned. +*******************************************************************************/ +#if defined (__ICCARM__) + #pragma location=".ramvectors" + #pragma data_alignment=256 +#else + CY_SECTION(".ramvectors") + CY_ALIGN(256) +#endif /* defined (__ICCARM__) */ +cyisraddress CyRamVectors[CY_NUM_VECTORS]; + + +/******************************************************************************* +* Function Name: IntDefaultHandler +******************************************************************************** +* +* Summary: +* This function is called for all interrupts, other than a reset that gets +* called before the system is setup. +* +* Parameters: +* None +* +* Return: +* None +* +* Theory: +* Any value other than zero is acceptable. +* +*******************************************************************************/ +CY_ISR(IntDefaultHandler) +{ + + while(1) + { + /*********************************************************************** + * We must not get here. If we do, a serious problem occurs, so go + * into an infinite loop. + ***********************************************************************/ + } +} + + +#if defined(__ARMCC_VERSION) + +/* Local function for device reset. */ +extern void Reset(void); + +/* Application entry point. */ +extern void $Super$$main(void); + +/* Linker-generated Stack Base addresses, Two Region and One Region */ +extern uint32 Image$$ARM_LIB_STACK$$ZI$$Limit; + +/* RealView C Library initialization. */ +extern int __main(void); + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the RVDS/MDK toolchains. +* This is the first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + __main(); +} + + +/******************************************************************************* +* Function Name: $Sub$$main +******************************************************************************** +* +* Summary: +* This function is called immediately before the users main +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void $Sub$$main(void) +{ + initialize_psoc(); + + /* Call original main */ + $Super$$main(); + + while (1) + { + /* If main returns, it is undefined what we should do. */ + } +} + +#elif defined(__GNUC__) + +void Start_c(void); + +/* Stack Base address */ +extern void __cy_stack(void); + +/* Application entry point. */ +extern int main(void); + +/* Static objects constructors initializer */ +extern void __libc_init_array(void); + +typedef unsigned char __cy_byte_align8 __attribute ((aligned (8))); + +struct __cy_region +{ + __cy_byte_align8 *init; /* Initial contents of this region. */ + __cy_byte_align8 *data; /* Start address of region. */ + size_t init_size; /* Size of initial data. */ + size_t zero_size; /* Additional size to be zeroed. */ +}; + +extern const struct __cy_region __cy_regions[]; +extern const char __cy_region_num __attribute__((weak)); +#define __cy_region_num ((size_t)&__cy_region_num) + + +/******************************************************************************* +* System Calls of the Red Hat newlib C Library +*******************************************************************************/ + + +/******************************************************************************* +* Function Name: _exit +******************************************************************************** +* +* Summary: +* Exit a program without cleaning up files. If your system doesn't provide +* this, it is best to avoid linking with subroutines that require it (exit, +* system). +* +* Parameters: +* status: Status caused program exit. +* +* Return: +* None +* +*******************************************************************************/ +__attribute__((weak)) +void _exit(int status) +{ + /* Cause divide by 0 exception */ + int x = status / (int) INT_MAX; + x = 4 / x; + + while(1) + { + + } +} + + +/******************************************************************************* +* Function Name: _sbrk +******************************************************************************** +* +* Summary: +* Increase program data space. As malloc and related functions depend on this, +* it is useful to have a working implementation. The following suffices for a +* standalone system; it exploits the symbol end automatically defined by the +* GNU linker. +* +* Parameters: +* nbytes: The number of bytes requested (if the parameter value is positive) +* from the heap or returned back to the heap (if the parameter value is +* negative). +* +* Return: +* None +* +*******************************************************************************/ +__attribute__((weak)) +void * _sbrk (int nbytes) +{ + extern int end; /* Symbol defined by linker map. Start of free memory (as symbol). */ + void * returnValue; + + /* The statically held previous end of the heap, with its initialization. */ + static void *heapPointer = (void *) &end; /* Previous end */ + + if (((heapPointer + nbytes) - (void *) &end) <= CYDEV_HEAP_SIZE) + { + returnValue = heapPointer; + heapPointer += nbytes; + } + else + { + errno = ENOMEM; + returnValue = (void *) -1; + } + + return (returnValue); +} + + +/******************************************************************************* +* Function Name: Reset +******************************************************************************** +* +* Summary: +* This function handles the reset interrupt for the GCC toolchain. This is the +* first bit of code that is executed at startup. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Reset(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if(CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* (CYDEV_BOOTLOADER_ENABLE) */ + + Start_c(); +} + + +/******************************************************************************* +* Function Name: Start_c +******************************************************************************** +* +* Summary: +* This function handles initializing the .data and .bss sections in +* preparation for running the standard C code. Once initialization is complete +* it will call main(). This function will never return. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void Start_c(void) __attribute__ ((noreturn)); +void Start_c(void) +{ + unsigned regions = __cy_region_num; + const struct __cy_region *rptr = __cy_regions; + + /* Initialize memory */ + for (regions = __cy_region_num; regions != 0u; regions--) + { + uint32 *src = (uint32 *)rptr->init; + uint32 *dst = (uint32 *)rptr->data; + unsigned limit = rptr->init_size; + unsigned count; + + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = *src; + dst++; + src++; + } + limit = rptr->zero_size; + for (count = 0u; count != limit; count += sizeof (uint32)) + { + *dst = 0u; + dst++; + } + + rptr++; + } + + /* Invoke static objects constructors */ + __libc_init_array(); + (void) main(); + + while (1) + { + /* If main returns, make sure we don't return. */ + } +} + + +#elif defined (__ICCARM__) + +/******************************************************************************* +* Function Name: __low_level_init +******************************************************************************** +* +* Summary: +* This function performs early initializations for the IAR Embedded +* Workbench IDE. It is executed in the context of a reset interrupt handler +* before the data sections are initialized. +* +* Parameters: +* None +* +* Return: +* The value that determines whether or not data sections should be initialized +* by the system startup code: +* 0 - skip data sections initialization; +* 1 - initialize data sections; +* +*******************************************************************************/ +int __low_level_init(void) +{ + #if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) + + /* For PSoC 5LP, debugging is enabled by default */ + #if(CYDEV_DEBUGGING_ENABLE == 0) + *(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK; + #endif /* (CYDEV_DEBUGGING_ENABLE) */ + + /* Reset Status Register has Read-to-clear SW access mode. + * Preserve current RESET_SR0 state to make it available for next reading. + */ + *(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0); + + #endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */ + + #if (CYDEV_BOOTLOADER_ENABLE) + CyBtldr_CheckLaunch(); + #endif /* CYDEV_BOOTLOADER_ENABLE */ + + /* Initialize data sections */ + __iar_data_init3(); + + initialize_psoc(); + + return 0; +} + +#endif /* __GNUC__ */ + + +/******************************************************************************* +* +* Default Rom Interrupt Vector table. +* +*******************************************************************************/ +#if defined(__ARMCC_VERSION) + /* Suppress diagnostic message 1296-D: extended constant initialiser used */ + #pragma diag_suppress 1296 +#endif /* defined(__ARMCC_VERSION) */ + +#if defined (__ICCARM__) + #pragma location=".romvectors" + const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] = +#else + CY_SECTION(".romvectors") + const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] = +#endif /* defined (__ICCARM__) */ +{ + INITIAL_STACK_POINTER, /* Initial stack pointer 0 */ + #if defined (__ICCARM__) /* Reset handler 1 */ + __iar_program_start, + #else + (cyisraddress)&Reset, + #endif /* defined (__ICCARM__) */ + &IntDefaultHandler, /* NMI handler 2 */ + &IntDefaultHandler, /* Hard fault handler 3 */ +}; + +#if defined(__ARMCC_VERSION) + #pragma diag_default 1296 +#endif /* defined(__ARMCC_VERSION) */ + + +/******************************************************************************* +* Function Name: initialize_psoc +******************************************************************************** +* +* Summary: +* This function used to initialize the PSoC chip before calling main. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) +__attribute__ ((constructor(101))) +#endif +void initialize_psoc(void) +{ + uint32 i; + + /* Set Priority group 5. */ + + /* Writes to NVIC_APINT register require the VECTKEY in the upper half */ + *CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5; + *CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN; + + /* Set Ram interrupt vectors to default functions. */ + for (i = 0u; i < CY_NUM_VECTORS; i++) + { + #if defined (__ICCARM__) + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler; + #else + CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler; + #endif /* defined (__ICCARM__) */ + } + + /* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */ + CyResetStatus = CY_GET_REG8(CYREG_PHUB_CFGMEM23_CFG1); + + /* Point NVIC at RAM vector table. */ + *CYINT_VECT_TABLE = CyRamVectors; + + /* Initialize the configuration registers. */ + cyfitter_cfg(); + + #if(0u != DMA_CHANNELS_USED__MASK0) + + /* Setup DMA - only necessary if design contains DMA component. */ + CyDmacConfigure(); + + #endif /* (0u != DMA_CHANNELS_USED__MASK0) */ + + #if !defined (__ICCARM__) + /* Actually, no need to clean this variable, just to make compiler happy. */ + cySysNoInitDataValid = 0u; + #endif /* !defined (__ICCARM__) */ +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s new file mode 100644 index 0000000..f72c255 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s @@ -0,0 +1,174 @@ +/******************************************************************************* +* File Name: CyBootAsmGnu.s +* Version 4.20 +* +* Description: +* Assembly routines for GNU as. +* +******************************************************************************** +* Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +.include "cyfittergnu.inc" + +.syntax unified +.text +.thumb + + +/******************************************************************************* +* Function Name: CyDelayCycles +******************************************************************************** +* +* Summary: +* Delays for the specified number of cycles. +* +* Parameters: +* uint32 cycles: number of cycles to delay. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyDelayCycles(uint32 cycles) */ +.align 3 /* Align to 8 byte boundary (2^n) */ +.global CyDelayCycles +.func CyDelayCycles, CyDelayCycles +.type CyDelayCycles, %function +.thumb_func +CyDelayCycles: /* cycles bytes */ +/* If ICache is enabled */ +.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1 + + ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */ + LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */ + BEQ CyDelayCycles_done /* 2 2 Skip if 0 */ + NOP /* 1 2 Loop alignment padding */ + +CyDelayCycles_loop: + SUBS r0, r0, #1 /* 1 2 */ + MOV r0, r0 /* 1 2 Pad loop to power of two cycles */ + BNE CyDelayCycles_loop /* 2 2 */ + +CyDelayCycles_done: + BX lr /* 3 2 */ + +.else + + CMP r0, #20 /* 1 2 If delay is short - jump to cycle */ + BLS CyDelayCycles_short /* 1 2 */ + PUSH {r1} /* 2 2 PUSH r1 to stack */ + MOVS r1, #1 /* 1 2 */ + + SUBS r0, r0, #20 /* 1 2 Subtract overhead */ + LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */ + LDRB r1, [r1, #0] /* 2 2 */ + ANDS r1, #0xC0 /* 1 2 */ + + LSRS r1, r1, #6 /* 1 2 */ + PUSH {r2} /* 1 2 PUSH r2 to stack */ + LDR r2, =cy_flash_cycles /* 2 2 */ + LDRB r1, [r2, r1] /* 2 2 */ + + POP {r2} /* 2 2 POP r2 from stack */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_loop: + SBCS r0, r0, r1 /* 1 2 */ + BPL CyDelayCycles_loop /* 3 2 */ + NOP /* 1 2 Loop alignment padding */ + NOP /* 1 2 Loop alignment padding */ + + POP {r1} /* 2 2 POP r1 from stack */ +CyDelayCycles_done: + BX lr /* 3 2 */ + NOP /* 1 2 Alignment padding */ + NOP /* 1 2 Alignment padding */ + +CyDelayCycles_short: + SBCS r0, r0, #4 /* 1 2 */ + BPL CyDelayCycles_short /* 3 2 */ + BX lr /* 3 2 */ + +cy_flash_cycles: +.byte 0x0B +.byte 0x05 +.byte 0x07 +.byte 0x09 +.endif + +.endfunc + + +/******************************************************************************* +* Function Name: CyEnterCriticalSection +******************************************************************************** +* +* Summary: +* CyEnterCriticalSection disables interrupts and returns a value indicating +* whether interrupts were previously enabled (the actual value depends on +* whether the device is PSoC 3 or PSoC 5). +* +* Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +* with interrupts still enabled. The test and set of the interrupt bits is not +* atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid +* corrupting processor state, it must be the policy that all interrupt routines +* restore the interrupt enable bits as they were found on entry. +* +* Parameters: +* None +* +* Return: +* uint8 +* Returns 0 if interrupts were previously enabled or 1 if interrupts +* were previously disabled. +* +*******************************************************************************/ +/* uint8 CyEnterCriticalSection(void) */ +.global CyEnterCriticalSection +.func CyEnterCriticalSection, CyEnterCriticalSection +.type CyEnterCriticalSection, %function +.thumb_func +CyEnterCriticalSection: + MRS r0, PRIMASK /* Save and return interrupt state */ + CPSID I /* Disable interrupts */ + BX lr +.endfunc + + +/******************************************************************************* +* Function Name: CyExitCriticalSection +******************************************************************************** +* +* Summary: +* CyExitCriticalSection re-enables interrupts if they were enabled before +* CyEnterCriticalSection was called. The argument should be the value returned +* from CyEnterCriticalSection. +* +* Parameters: +* uint8 savedIntrStatus: +* Saved interrupt status returned by the CyEnterCriticalSection function. +* +* Return: +* None +* +*******************************************************************************/ +/* void CyExitCriticalSection(uint8 savedIntrStatus) */ +.global CyExitCriticalSection +.func CyExitCriticalSection, CyExitCriticalSection +.type CyExitCriticalSection, %function +.thumb_func +CyExitCriticalSection: + MSR PRIMASK, r0 /* Restore interrupt state */ + BX lr +.endfunc + +.end + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s new file mode 100644 index 0000000..2c356b3 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s @@ -0,0 +1,156 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmIar.s +; Version 4.20 +; +; DESCRIPTION: +; Assembly routines for IAR Embedded Workbench IDE. +; +;------------------------------------------------------------------------------- +; Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + SECTION .text:CODE:ROOT(4) + PUBLIC CyDelayCycles + PUBLIC CyEnterCriticalSection + PUBLIC CyExitCriticalSection + INCLUDE cyfitteriar.inc + THUMB + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled. +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic. Therefore, to avoid a corrupting processor state, it must be the policy +; that all interrupt routines restore the interrupt enable bits as they were +; found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) + +CyEnterCriticalSection: + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) + +CyExitCriticalSection: + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + +CyDelayCycles: + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop: + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 +CyDelayCycles_done: + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop: + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done: + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding +CyDelayCycles_short: + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + NOP ; 1 2 Loop alignment padding + + DATA +cy_flash_cycles: +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + + END diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s new file mode 100644 index 0000000..8753fe1 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s @@ -0,0 +1,161 @@ +;------------------------------------------------------------------------------- +; FILENAME: CyBootAsmRv.s +; Version 4.20 +; +; DESCRIPTION: +; Assembly routines for RealView. +; +;------------------------------------------------------------------------------- +; Copyright 2010-2014, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + AREA |.text|,CODE,ALIGN=3 + THUMB + EXTERN Reset + + GET cyfitterrv.inc + +;------------------------------------------------------------------------------- +; Function Name: CyDelayCycles +;------------------------------------------------------------------------------- +; +; Summary: +; Delays for the specified number of cycles. +; +; Parameters: +; uint32 cycles: number of cycles to delay. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyDelayCycles(uint32 cycles) + ALIGN 8 +CyDelayCycles FUNCTION + EXPORT CyDelayCycles + IF CYDEV_INSTRUCT_CACHE_ENABLED == 1 + ; cycles bytes + ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4 + LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags + BEQ CyDelayCycles_done ; 2 2 Skip if 0 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_loop + SUBS r0, r0, #1 ; 1 2 + MOV r0, r0 ; 1 2 Pad loop to power of two cycles + BNE CyDelayCycles_loop ; 2 2 + NOP ; 1 2 Loop alignment padding +CyDelayCycles_done + BX lr ; 3 2 + + ELSE + + CMP r0, #20 ; 1 2 If delay is short - jump to cycle + BLS CyDelayCycles_short ; 1 2 + PUSH {r1} ; 2 2 PUSH r1 to stack + MOVS r1, #1 ; 1 2 + + SUBS r0, r0, #20 ; 1 2 Subtract overhead + LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value + LDRB r1, [r1, #0] ; 2 2 + ANDS r1, #0xC0 ; 1 2 + + LSRS r1, r1, #6 ; 1 2 + PUSH {r2} ; 1 2 PUSH r2 to stack + LDR r2, =cy_flash_cycles ; 2 2 + LDRB r1, [r2, r1] ; 2 2 + + POP {r2} ; 2 2 POP r2 from stack + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_loop + SBCS r0, r0, r1 ; 1 2 + BPL CyDelayCycles_loop ; 3 2 + NOP ; 1 2 Loop alignment padding + NOP ; 1 2 Loop alignment padding + + POP {r1} ; 2 2 POP r1 from stack +CyDelayCycles_done + BX lr ; 3 2 + NOP ; 1 2 Alignment padding + NOP ; 1 2 Alignment padding + +CyDelayCycles_short + SBCS r0, r0, #4 ; 1 2 + BPL CyDelayCycles_short ; 3 2 + BX lr ; 3 2 + +cy_flash_cycles +byte_1 DCB 0x0B +byte_2 DCB 0x05 +byte_3 DCB 0x07 +byte_4 DCB 0x09 + + ENDIF + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyEnterCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyEnterCriticalSection disables interrupts and returns a value indicating +; whether interrupts were previously enabled (the actual value depends on +; whether the device is PSoC 3 or PSoC 5). +; +; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit +; with interrupts still enabled. The test and set of the interrupt bits is not +; atomic; this is true for both PSoC 3 and PSoC 5. Therefore, to avoid a +; corrupting processor state, it must be the policy that all interrupt routines +; restore the interrupt enable bits as they were found on entry. +; +; Parameters: +; None +; +; Return: +; uint8 +; Returns 0 if interrupts were previously enabled or 1 if interrupts +; were previously disabled. +; +;------------------------------------------------------------------------------- +; uint8 CyEnterCriticalSection(void) +CyEnterCriticalSection FUNCTION + EXPORT CyEnterCriticalSection + MRS r0, PRIMASK ; Save and return interrupt state + CPSID I ; Disable interrupts + BX lr + ENDFUNC + + +;------------------------------------------------------------------------------- +; Function Name: CyExitCriticalSection +;------------------------------------------------------------------------------- +; +; Summary: +; CyExitCriticalSection re-enables interrupts if they were enabled before +; CyEnterCriticalSection was called. The argument should be the value returned +; from CyEnterCriticalSection. +; +; Parameters: +; uint8 savedIntrStatus: +; Saved interrupt status returned by the CyEnterCriticalSection function. +; +; Return: +; None +; +;------------------------------------------------------------------------------- +; void CyExitCriticalSection(uint8 savedIntrStatus) +CyExitCriticalSection FUNCTION + EXPORT CyExitCriticalSection + MSR PRIMASK, r0 ; Restore interrupt state + BX lr + ENDFUNC + + END + +; [] END OF FILE diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c new file mode 100644 index 0000000..c41fea0 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.c @@ -0,0 +1,1131 @@ +/******************************************************************************* +* File Name: CyDmac.c +* Version 4.20 +* +* Description: +* Provides an API for the DMAC component. The API includes functions for the +* DMA controller, DMA channels and Transfer Descriptors. +* +* This API is the library version not the auto generated code that gets +* generated when the user places a DMA component on the schematic. +* +* The auto generated code would use the APi's in this module. +* +* Note: +* This code is endian agnostic. +* +* The Transfer Descriptor memory can be used as regular memory if the TD's are +* not being used. +* +* This code uses the first byte of each TD to manage the free list of TD's. +* The user can overwrite this once the TD is allocated. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyDmac.h" + + +/******************************************************************************* +* The following variables are initialized from CyDmacConfigure() function that +* is executed from initialize_psoc() at the early initialization stage. +* In case of IAR EW IDE, initialize_psoc() is executed before the data sections +* are initialized. To avoid zeroing, these variables should be initialized +* properly during segments initialization as well. +*******************************************************************************/ +static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements on list */ +static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of first available TD */ +static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */ + + +/******************************************************************************* +* Function Name: CyDmacConfigure +******************************************************************************** +* +* Summary: +* Creates a linked list of all the TDs to be allocated. This function is called +* by the startup code; you do not normally need to call it. You can call this +* function if all of the DMA channels are inactive. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyDmacConfigure(void) +{ + uint8 dmaIndex; + + /* Set TD list variables. */ + CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); + CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; + + /* Make TD free list. */ + for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--) + { + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u); + } + + /* Make last one point to zero. */ + CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = 0u; +} + + +/******************************************************************************* +* Function Name: CyDmacError +******************************************************************************** +* +* Summary: +* Returns errors of the last failed DMA transaction. +* +* Parameters: +* None +* +* Return: +* Errors of the last failed DMA transaction. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing a 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by +* writing 1 to the error register. +* +*******************************************************************************/ +uint8 CyDmacError(void) +{ + return((uint8)(((uint32) 0x0Fu) & *CY_DMA_ERR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmacClearError +******************************************************************************** +* +* Summary: +* Clears the error bits in the error register of the DMAC. +* +* Parameters: +* error: +* Clears the error bits in the DMAC error register. +* +* DMAC_PERIPH_ERR: +* Set to 1 when a peripheral responds to a bus transaction with an error +* response. +* +* DMAC_UNPOP_ACC: +* Set to 1 when an access is attempted to an invalid address. +* +* DMAC_BUS_TIMEOUT: +* Set to 1 when a bus timeout occurs. Cleared by writing 1. Timeout values +* are determined by the BUS_TIMEOUT field in the PHUBCFG register. +* +* Return: +* None +* +* Theory: +* Once an error occurs the error bits are sticky and are only cleared by +* writing 1 to the error register. +* +*******************************************************************************/ +void CyDmacClearError(uint8 error) +{ + *CY_DMA_ERR_PTR = (((uint32)0x0Fu) & ((uint32)error)); +} + + +/******************************************************************************* +* Function Name: CyDmacErrorAddress +******************************************************************************** +* +* Summary: +* When DMAC_BUS_TIMEOUT, DMAC_UNPOP_ACC, and DMAC_PERIPH_ERR occur the +* address of the error is written to the error address register and can be read +* with this function. +* +* If there are multiple errors, only the address of the first is saved. +* +* Parameters: +* None +* +* Return: +* The address that caused the error. +* +*******************************************************************************/ +uint32 CyDmacErrorAddress(void) +{ + return(CY_GET_REG32(CY_DMA_ERR_ADR_PTR)); +} + + +/******************************************************************************* +* Function Name: CyDmaChAlloc +******************************************************************************** +* +* Summary: +* Allocates a channel from the DMAC to be used in all functions that require a +* channel handle. +* +* Parameters: +* None +* +* Return: +* The allocated channel number. Zero is a valid channel number. +* DMA_INVALID_CHANNEL is returned if there are no channels available. +* +*******************************************************************************/ +uint8 CyDmaChAlloc(void) +{ + uint8 interruptState; + uint8 dmaIndex; + uint32 channel = 1u; + + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + /* Look for free channel. */ + for(dmaIndex = 0u; dmaIndex < CY_DMA_NUMBEROF_CHANNELS; dmaIndex++) + { + if(0uL == (CyDmaChannels & channel)) + { + /* Mark channel as used. */ + CyDmaChannels |= channel; + break; + } + + channel <<= 1u; + } + + if(dmaIndex >= CY_DMA_NUMBEROF_CHANNELS) + { + dmaIndex = CY_DMA_INVALID_CHANNEL; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(dmaIndex); +} + + +/******************************************************************************* +* Function Name: CyDmaChFree +******************************************************************************** +* +* Summary: +* Frees a channel allocated by DmaChAlloc(). +* +* Parameters: +* uint8 chHandle: +* The handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChFree(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + uint8 interruptState; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Clear bit mask that keeps track of ownership. */ + CyDmaChannels &= ~(((uint32) 1u) << chHandle); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChEnable +******************************************************************************** +* +* Summary: +* Enables the DMA channel. A software or hardware request still must happen +* before the channel is executed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 preserveTds: +* Preserves the original TD state when the TD has completed. This parameter +* applies to all TDs in the channel. +* +* 0 - When TD is completed, the DMAC leaves the TD configuration values in +* their current state, and does not restore them to their original state. +* +* 1 - When TD is completed, the DMAC restores the original configuration +* values of the TD. +* +* When preserveTds is set, the TD slot that equals the channel number becomes +* RESERVED and that becomes where the working registers exist. So, for example, +* if you are using CH06 and preserveTds is set, you are not allowed to use TD +* slot 6. That is reclaimed by the DMA engine for its private use. +* +* Note Do not chain back to a completed TD if the preserveTds for the channel +* is set to 0. When a TD has completed preserveTds for the channel set to 0, +* the transfer count will be at 0. If a TD with a transfer count of 0 is +* started, the TD will transfer an indefinite amount of data. +* +* Take extra precautions when using the hardware request (DRQ) option when the +* preserveTds is set to 0, as you might be requesting the wrong data. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != preserveTds) + { + /* Store intermediate TD states separately in CHn_SEP_TD0/1 to + * preserve original TD chain + */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP; + } + else + { + /* Store intermediate and final TD states on top of original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP); + } + + /* Enable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChDisable +******************************************************************************** +* +* Summary: +* Disables the DMA channel. Once this function is called, CyDmaChStatus() may +* be called to determine when the channel is disabled and which TDs were being +* executed. +* +* If it is currently executing it will allow the current burst to finish +* naturally. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChDisable(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /*********************************************************************** + * Should not change configuration information of a DMA channel when it + * is active (or vulnerable to becoming active). + ***********************************************************************/ + + /* Disable channel */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN)); + + /* Store intermediate and final TD states on top of original TD chain */ + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaClearPendingDrq +******************************************************************************** +* +* Summary: +* Clears pending the DMA data request. +* +* Parameters: +* uint8 chHandle: +* Handle to the dma channel. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaClearPendingDrq(uint8 chHandle) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0] |= CY_DMA_CPU_TERM_CHAIN; + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] |= 0x01u; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChPriority +******************************************************************************** +* +* Summary: +* Sets the priority of a DMA channel. You can use this function when you want +* to change the priority at run time. If the priority remains the same for a +* DMA channel, then you can configure the priority in the .cydwr file. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 priority: +* Priority to set the channel to, 0 - 7. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) +{ + uint8 value; + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + value = CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~(0x0Eu))); + + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] = value | ((uint8) ((priority & 0x7u) << 0x01u)); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetExtendedAddress +******************************************************************************** +* +* Summary: +* Sets the high 16 bits of the source and destination addresses for the DMA +* channel (valid for all TDs in the chain). +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint16 source: +* Upper 16 bit address of the DMA transfer source. +* +* uint16 destination: +* Upper 16 bit address of the DMA transfer destination. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination) \ + +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + #if(CY_PSOC5) + + /* 0x1FFF8000-0x1FFFFFFF needs to use alias at 0x20008000-0x2000FFFF */ + if(source == 0x1FFFu) + { + source = 0x2000u; + } + + if(destination == 0x1FFFu) + { + destination = 0x2000u; + } + + #endif /* (CY_PSOC5) */ + + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u]; + CY_SET_REG16(convert, destination); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetInitialTd +******************************************************************************** +* +* Summary: +* Sets the initial TD to be executed for the channel when the CyDmaChEnable() +* function is called. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 startTd: +* Set the TD index as the first TD associated with the channel. Zero is +* a valid TD index. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1u] = startTd; + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetRequest +******************************************************************************** +* +* Summary: +* Allows the caller to terminate a chain of TDs, terminate one TD, or create a +* direct request to start the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 request: +* One of the following constants. Each of the constants is a three-bit value. +* +* CPU_REQ - Create a direct request to start the DMA channel +* CPU_TERM_TD - Terminate one TD +* CPU_TERM_CHAIN - Terminate a chain of TDs +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] |= (request & (CPU_REQ | CPU_TERM_TD | CPU_TERM_CHAIN)); + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChGetRequest +******************************************************************************** +* +* Summary: +* This function allows the caller of CyDmaChSetRequest() to determine if the +* request was completed. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* Return: +* Returns a three-bit field, corresponding to the three bits of the request, +* which describes the state of the previously posted request. If the value is +* zero, the request was completed. CY_DMA_INVALID_CHANNEL if the handle is +* invalid. +* +*******************************************************************************/ +cystatus CyDmaChGetRequest(uint8 chHandle) +{ + cystatus status = CY_DMA_INVALID_CHANNEL; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] & + (uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN)); + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChStatus +******************************************************************************** +* +* Summary: +* Determines the status of the DMA channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitalize(). +* +* uint8 * currentTd: +* The address to store the index of the current TD. Can be NULL if the value +* is not needed. +* +* uint8 * state: +* The address to store the state of the channel. Can be NULL if the value is +* not needed. +* +* STATUS_TD_ACTIVE +* 0: Channel is not currently being serviced by DMAC +* 1: Channel is currently being serviced by DMAC +* +* STATUS_CHAIN_ACTIVE +* 0: TD chain is inactive; either no DMA requests have triggered a new chain +* or the previous chain has completed. +* 1: TD chain has been triggered by a DMA request +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +* Theory: +* The caller can check on the activity of the Current TD and the Chain. +* +*******************************************************************************/ +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if(NULL != currentTd) + { + *currentTd = CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[1] & 0x7Fu; + } + + if(NULL != state) + { + *state= CY_DMA_CH_STRUCT_PTR[chHandle].basic_status[0]; + } + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaChSetConfiguration +******************************************************************************** +* +* Summary: +* Sets configuration information of the channel. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or DMA_DmaInitialize(). +* +* uint8 burstCount: +* Specifies the size of bursts (1 to 127) the data transfer should be divided +* into. If this value is zero then the whole transfer is done in one burst. +* +* uint8 requestPerBurst: +* The whole of the data can be split into multiple bursts, if this is +* required to complete the transaction: +* 0: All subsequent bursts after the first burst will be automatically +* requested and carried out +* 1: All subsequent bursts after the first burst must also be individually +* requested. +* +* uint8 tdDone0: +* Selects one of the TERMOUT0 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT0_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdDone1: +* Selects one of the TERMOUT1 interrupt lines to signal completion. The line +* connected to the nrq terminal will determine the TERMOUT1_SEL definition and +* should be used as supplied by cyfitter.h +* +* uint8 tdStop: +* Selects one of the TERMIN interrupt lines to signal to the DMAC that the TD +* should terminate. The signal connected to the trq terminal will determine +* which TERMIN (termination request) is used. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, + uint8 tdDone0, uint8 tdDone1, uint8 tdStop) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[0] = (burstCount & 0x7Fu) | ((uint8)((requestPerBurst & 0x1u) << 7u)); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[1] = ((uint8)((tdDone1 & 0xFu) << 4u)) | (tdDone0 & 0xFu); + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[2] = 0x0Fu & tdStop; + CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG0[3] = 0u; /* burstcount_remain. */ + + status = CYRET_SUCCESS; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdAllocate +******************************************************************************** +* +* Summary: +* Allocates a TD for use with an allocated DMA channel. +* +* Parameters: +* None +* +* Return: +* Zero-based index of the TD to be used by the caller. Since there are 128 TDs +* minus the reserved TDs (0 to 23), the value returned would range from 24 to +* 127 not 24 to 128. DMA_INVALID_TD is returned if there are no free TDs +* available. +* +*******************************************************************************/ +uint8 CyDmaTdAllocate(void) +{ + uint8 interruptState; + uint8 element = CY_DMA_INVALID_TD; + + /* Enter critical section! */ + interruptState = CyEnterCriticalSection(); + + if(CyDmaTdCurrentNumber > NUMBEROF_CHANNELS) + { + /* Get pointer to Next available. */ + element = CyDmaTdFreeIndex; + + /* Decrement the count. */ + CyDmaTdCurrentNumber--; + + /* Update next available pointer. */ + CyDmaTdFreeIndex = CY_DMA_TDMEM_STRUCT_PTR[element].TD0[0]; + } + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + + return(element); +} + + +/******************************************************************************* +* Function Name: CyDmaTdFree +******************************************************************************** +* +* Summary: +* Returns a TD to the free list. +* +* Parameters: +* uint8 tdHandle: +* The TD handle returned by the CyDmaTdAllocate(). +* +* Return: +* None +* +*******************************************************************************/ +void CyDmaTdFree(uint8 tdHandle) +{ + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Enter critical section! */ + uint8 interruptState = CyEnterCriticalSection(); + + /* Get pointer to Next available. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u] = CyDmaTdFreeIndex; + + /* Set new Next Available. */ + CyDmaTdFreeIndex = tdHandle; + + /* Keep track of how many left. */ + CyDmaTdCurrentNumber++; + + /* Exit critical section! */ + CyExitCriticalSection(interruptState); + } +} + + +/******************************************************************************* +* Function Name: CyDmaTdFreeCount +******************************************************************************** +* +* Summary: +* Returns the number of free TDs available to be allocated. +* +* Parameters: +* None +* +* Return: +* The number of free TDs. +* +*******************************************************************************/ +uint8 CyDmaTdFreeCount(void) +{ + return(CyDmaTdCurrentNumber - CY_DMA_NUMBEROF_CHANNELS); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetConfiguration +******************************************************************************** +* +* Summary: +* Configures the TD. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 transferCount: +* The size of the data transfer (in bytes) for this TD. A size of zero will +* cause the transfer to continue indefinitely. This parameter is limited to +* 4095 bytes; the TD is not initialized at all when a higher value is passed. +* +* uint8 nextTd: +* Zero based index of the next Transfer Descriptor in the TD chain. Zero is a +* valid pointer to the next TD; DMA_END_CHAIN_TD is the end of the chain. +* DMA_DISABLE_TD indicates an end to the chain and the DMA is disabled. No +* further TDs are fetched. DMA_DISABLE_TD is only supported on PSoC3 and +* PSoC 5LP silicons. +* +* uint8 configuration: +* Stores the Bit field of configuration bits. +* +* CY_DMA_TD_SWAP_EN - Perform endian swap +* +* CY_DMA_TD_SWAP_SIZE4 - Swap size = 4 bytes +* +* CY_DMA_TD_AUTO_EXEC_NEXT - The next TD in the chain will trigger +* automatically when the current TD completes. +* +* CY_DMA_TD_TERMIN_EN - Terminate this TD if a positive edge on the trq +* input line occurs. The positive edge must occur +* during a burst. That is the only time the DMAC +* will listen for it. +* +* DMA__TD_TERMOUT_EN - When this TD completes, the TERMOUT signal will +* generate a pulse. Note that this option is +* instance specific with the instance name followed +* by two underscores. In this example, the instance +* name is DMA. +* +* CY_DMA_TD_INC_DST_ADR - Increment DST_ADR according to the size of each +* data transaction in the burst. +* +* CY_DMA_TD_INC_SRC_ADR - Increment SRC_ADR according to the size of each +* data transaction in the burst. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle or transferCount is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if((tdHandle < CY_DMA_NUMBEROF_TDS) && (0u == (0xF000u & transferCount))) + { + /* Set 12 bits transfer count. */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0u]; + CY_SET_REG16(convert, transferCount); + + /* Set Next TD pointer. */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u] = nextTd; + + /* Configure the TD */ + CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u] = configuration; + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetConfiguration +******************************************************************************** +* +* Summary: +* Retrieves the configuration of the TD. If a NULL pointer is passed as a +* parameter, that parameter is skipped. You may request only the values you are +* interested in. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * transferCount: +* The address to store the size of the data transfer (in bytes) for this TD. +* A size of zero could indicate that the TD has completed its transfer, or +* that the TD is doing an indefinite transfer. +* +* uint8 * nextTd: +* The address to store the index of the next TD in the TD chain. +* +* uint8 * configuration: +* The address to store the Bit field of configuration bits. +* See CyDmaTdSetConfiguration() function description. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +* Side Effects: +* If TD has a transfer count of N and is executed, the transfer count becomes +* 0. If it is reexecuted, the Transfer count of zero will be interpreted as a +* request for indefinite transfer. Be careful when requesting TD with a +* transfer count of zero. +* +*******************************************************************************/ +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) \ + +{ + cystatus status = CYRET_BAD_PARAM; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have pointer */ + if(NULL != transferCount) + { + /* Get 12 bits of transfer count */ + reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[0]; + *transferCount = 0x0FFFu & CY_GET_REG16(convert); + } + + /* If we have pointer */ + if(NULL != nextTd) + { + /* Get Next TD pointer */ + *nextTd = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[2u]; + } + + /* If we have pointer */ + if(NULL != configuration) + { + /* Get configuration TD */ + *configuration = CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD0[3u]; + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdSetAddress +******************************************************************************** +* +* Summary: +* Sets the lower 16 bits of the source and destination addresses for this TD +* only. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 source: +* The lower 16 address bits of the source of the data transfer. +* +* uint16 destination: +* The lower 16 address bits of the destination of the data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* Set source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + CY_SET_REG16(convert, source); + + /* Set destination address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + CY_SET_REG16(convert, destination); + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaTdGetAddress +******************************************************************************** +* +* Summary: +* Retrieves the lower 16 bits of the source and/or destination addresses for +* this TD only. If NULL is passed for a pointer parameter, that value is +* skipped. You may request only the values of interest. +* +* Parameters: +* uint8 tdHandle: +* A handle previously returned by CyDmaTdAlloc(). +* +* uint16 * source: +* The address to store the lower 16 address bits of the source of the data +* transfer. +* +* uint16 * destination: +* The address to store the lower 16 address bits of the destination of the +* data transfer. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if tdHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) +{ + cystatus status = CYRET_BAD_PARAM; + reg16 *convert; + + if(tdHandle < CY_DMA_NUMBEROF_TDS) + { + /* If we have a pointer. */ + if(NULL != source) + { + /* Get source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u]; + *source = CY_GET_REG16(convert); + } + + /* If we have a pointer. */ + if(NULL != destination) + { + /* Get Destination address. */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u]; + *destination = CY_GET_REG16(convert); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyDmaChRoundRobin +******************************************************************************** +* +* Summary: +* Either enables or disables the Round-Robin scheduling enforcement algorithm. +* Within a priority level a Round-Robin fairness algorithm is enforced. +* +* Parameters: +* uint8 chHandle: +* A handle previously returned by CyDmaChAlloc() or Dma_DmaInitialize(). +* +* uint8 enableRR: +* 0: Disable Round-Robin fairness algorithm +* 1: Enable Round-Robin fairness algorithm +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if chHandle is invalid. +* +*******************************************************************************/ +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) +{ + cystatus status = CYRET_BAD_PARAM; + + if(chHandle < CY_DMA_NUMBEROF_CHANNELS) + { + if (0u != enableRR) + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE; + } + else + { + CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE); + } + + status = CYRET_SUCCESS; + } + + return(status); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h new file mode 100644 index 0000000..f78f3e3 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyDmac.h @@ -0,0 +1,229 @@ +/******************************************************************************* +* File Name: CyDmac.h +* Version 4.20 +* +* Description: +* Provides the function definitions for the DMA Controller. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYDMAC_H) +#define CY_BOOT_CYDMAC_H + + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "CyLib.h" + + +/*************************************** +* Function Prototypes +***************************************/ + +/* DMA Controller functions. */ +void CyDmacConfigure(void) ; +uint8 CyDmacError(void) ; +void CyDmacClearError(uint8 error) ; +uint32 CyDmacErrorAddress(void) ; + +/* Channel specific functions. */ +uint8 CyDmaChAlloc(void) ; +cystatus CyDmaChFree(uint8 chHandle) ; +cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ; +cystatus CyDmaChDisable(uint8 chHandle) ; +cystatus CyDmaClearPendingDrq(uint8 chHandle) ; +cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ; +cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\ +; +cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ; +cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ; +cystatus CyDmaChGetRequest(uint8 chHandle) ; +cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ; +cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, + uint8 tdDone1, uint8 tdStop) ; +cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ; + +/* Transfer Descriptor functions. */ +uint8 CyDmaTdAllocate(void) ; +void CyDmaTdFree(uint8 tdHandle) ; +uint8 CyDmaTdFreeCount(void) ; +cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\ +; +cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\ +; +cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ; +cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ; + + +/*************************************** +* Data Struct Definitions +***************************************/ + +typedef struct dmac_ch_struct +{ + volatile uint8 basic_cfg[4]; + volatile uint8 action[4]; + volatile uint8 basic_status[4]; + volatile uint8 reserved[4]; + +} dmac_ch; + + +typedef struct dmac_cfgmem_struct +{ + volatile uint8 CFG0[4]; + volatile uint8 CFG1[4]; + +} dmac_cfgmem; + + +typedef struct dmac_tdmem_struct +{ + volatile uint8 TD0[4]; + volatile uint8 TD1[4]; + +} dmac_tdmem; + + +typedef struct dmac_tdmem2_struct +{ + volatile uint16 xfercnt; + volatile uint8 next_td_ptr; + volatile uint8 flags; + volatile uint16 src_adr; + volatile uint16 dst_adr; +} dmac_tdmem2; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */ +#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */ +#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */ +#define CY_DMA_DISABLE_TD 0xFEu + +#define CY_DMA_TD_SIZE 0x08u + +/* "u" was removed as workaround for Keil compiler bug */ +#define CY_DMA_TD_SWAP_EN 0x80 +#define CY_DMA_TD_SWAP_SIZE4 0x40 +#define CY_DMA_TD_AUTO_EXEC_NEXT 0x20 +#define CY_DMA_TD_TERMIN_EN 0x10 +#define CY_DMA_TD_TERMOUT1_EN 0x08 +#define CY_DMA_TD_TERMOUT0_EN 0x04 +#define CY_DMA_TD_INC_DST_ADR 0x02 +#define CY_DMA_TD_INC_SRC_ADR 0x01 + +#define CY_DMA_NUMBEROF_TDS 128u +#define CY_DMA_NUMBEROF_CHANNELS ((uint8)(CYDEV_DMA_CHANNELS_AVAILABLE)) + +/* Action register bits */ +#define CY_DMA_CPU_REQ ((uint8)(1u << 0u)) +#define CY_DMA_CPU_TERM_TD ((uint8)(1u << 1u)) +#define CY_DMA_CPU_TERM_CHAIN ((uint8)(1u << 2u)) + +/* Basic Status register bits */ +#define CY_DMA_STATUS_CHAIN_ACTIVE ((uint8)(1u << 0u)) +#define CY_DMA_STATUS_TD_ACTIVE ((uint8)(1u << 1u)) + +/* DMA controller register error bits */ +#define CY_DMA_BUS_TIMEOUT (1u << 1u) +#define CY_DMA_UNPOP_ACC (1u << 2u) +#define CY_DMA_PERIPH_ERR (1u << 3u) + +/* Round robin bits */ +#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u)) + + +/******************************************************************************* +* CyDmaChEnable() / CyDmaChDisable() API constants +*******************************************************************************/ +#define CY_DMA_CH_BASIC_CFG_EN (0x01u) +#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u) + + +/*************************************** +* Registers +***************************************/ + +#define CY_DMA_CFG_REG (*(reg32 *) CYREG_PHUB_CFG) +#define CY_DMA_CFG_PTR ( (reg32 *) CYREG_PHUB_CFG) + +#define CY_DMA_ERR_REG (*(reg32 *) CYREG_PHUB_ERR) +#define CY_DMA_ERR_PTR ( (reg32 *) CYREG_PHUB_ERR) + +#define CY_DMA_ERR_ADR_REG (*(reg32 *) CYREG_PHUB_ERR_ADR) +#define CY_DMA_ERR_ADR_PTR ( (reg32 *) CYREG_PHUB_ERR_ADR) + +#define CY_DMA_CH_STRUCT_REG (*(dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) +#define CY_DMA_CH_STRUCT_PTR ( (dmac_ch CYXDATA *) CYDEV_PHUB_CH0_BASE) + +#define CY_DMA_CFGMEM_STRUCT_REG (*(dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) +#define CY_DMA_CFGMEM_STRUCT_PTR ( (dmac_cfgmem CYXDATA *) CYDEV_PHUB_CFGMEM0_BASE) + +#define CY_DMA_TDMEM_STRUCT_REG (*(dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) +#define CY_DMA_TDMEM_STRUCT_PTR ( (dmac_tdmem CYXDATA *) CYDEV_PHUB_TDMEM0_BASE) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define DMA_INVALID_CHANNEL (CY_DMA_INVALID_CHANNEL) +#define DMA_INVALID_TD (CY_DMA_INVALID_TD) +#define DMA_END_CHAIN_TD (CY_DMA_END_CHAIN_TD) +#define DMAC_TD_SIZE (CY_DMA_TD_SIZE) +#define TD_SWAP_EN (CY_DMA_TD_SWAP_EN) +#define TD_SWAP_SIZE4 (CY_DMA_TD_SWAP_SIZE4) +#define TD_AUTO_EXEC_NEXT (CY_DMA_TD_AUTO_EXEC_NEXT) +#define TD_TERMIN_EN (CY_DMA_TD_TERMIN_EN) +#define TD_TERMOUT1_EN (CY_DMA_TD_TERMOUT1_EN) +#define TD_TERMOUT0_EN (CY_DMA_TD_TERMOUT0_EN) +#define TD_INC_DST_ADR (CY_DMA_TD_INC_DST_ADR) +#define TD_INC_SRC_ADR (CY_DMA_TD_INC_SRC_ADR) +#define NUMBEROF_TDS (CY_DMA_NUMBEROF_TDS) +#define NUMBEROF_CHANNELS (CY_DMA_NUMBEROF_CHANNELS) +#define CPU_REQ (CY_DMA_CPU_REQ) +#define CPU_TERM_TD (CY_DMA_CPU_TERM_TD) +#define CPU_TERM_CHAIN (CY_DMA_CPU_TERM_CHAIN) +#define STATUS_CHAIN_ACTIVE (CY_DMA_STATUS_CHAIN_ACTIVE) +#define STATUS_TD_ACTIVE (CY_DMA_STATUS_TD_ACTIVE) +#define DMAC_BUS_TIMEOUT (CY_DMA_BUS_TIMEOUT) +#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC) +#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR) +#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE) +#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD) + +#define DMAC_CFG (CY_DMA_CFG_PTR) +#define DMAC_ERR (CY_DMA_ERR_PTR) +#define DMAC_ERR_ADR (CY_DMA_ERR_ADR_PTR) +#define DMAC_CH (CY_DMA_CH_STRUCT_PTR) +#define DMAC_CFGMEM (CY_DMA_CFGMEM_STRUCT_PTR) +#define DMAC_TDMEM (CY_DMA_TDMEM_STRUCT_PTR) + +#endif /* (CY_BOOT_CYDMAC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c new file mode 100644 index 0000000..fc1eee3 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.c @@ -0,0 +1,753 @@ +/******************************************************************************* +* File Name: CyFlash.c +* Version 4.20 +* +* Description: +* Provides an API for the FLASH/EEPROM. +* +* Note: +* This code is endian agnostic. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyFlash.h" + +/* The number of EEPROM arrays */ +#define CY_FLASH_EEPROM_NUMBER_ARRAYS (1u) + + +/******************************************************************************* +* Holds the die temperature, updated by CySetTemp(). Used for flash writing. +* The first byte is the sign of the temperature (0 = negative, 1 = positive). +* The second byte is the magnitude. +*******************************************************************************/ +uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + +#if(CYDEV_ECC_ENABLE == 0) + static uint8 * rowBuffer = 0; +#endif /* (CYDEV_ECC_ENABLE == 0) */ + + +static cystatus CySetTempInt(void); +static cystatus CyFlashGetSpcAlgorithm(void); + + +/******************************************************************************* +* Function Name: CyFlash_Start +******************************************************************************** +* +* Summary: +* Enable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or eeprom to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable flash. Active flash macros consume current, but re-enabling a + * disabled flash macro takes 5us. If the CPU attempts to fetch out of the + * macro during that time, it will be stalled. This bit allows the flash to + * be enabled even if the CPU is disabled, which allows a quicker return to + * code execution. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_FM; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_FM; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyFlash_Stop +******************************************************************************** +* +* Summary: +* Disable the Flash. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* This setting is ignored as long as the CPU is currently running. This will +* only take effect when the CPU is later disabled. +* +*******************************************************************************/ +void CyFlash_Stop(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_FM)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_FM)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySetTempInt +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to read the die temperature. Sets a global value +* used by the Write function. This function must be called once before +* executing a series of Flash writing functions. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CySetTempInt(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + /* Plan for failure. */ + status = CYRET_UNKNOWN; + + if(CySpcLock() == CYRET_SUCCESS) + { + /* Write the command. */ + if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES)) + { + do + { + if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE) + { + status = CYRET_SUCCESS; + + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + break; + } + + } while(CY_SPC_BUSY); + } + + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CyFlashGetSpcAlgorithm +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to download code into RAM. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS - if successful +* CYRET_LOCKED - if Flash writing already in use +* CYRET_UNKNOWN - if there was an SPC error +* +*******************************************************************************/ +static cystatus CyFlashGetSpcAlgorithm(void) +{ + cystatus status; + + /* Make sure SPC is powered */ + CySpcStart(); + + if(CySpcLock() == CYRET_SUCCESS) + { + status = CySpcGetAlgorithm(); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Spin until idle. */ + CyDelayUs(1u); + } + + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + } + CySpcUnlock(); + } + else + { + status = CYRET_LOCKED; + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetTemp +******************************************************************************** +* +* Summary: +* This is a wraparound for CySetTempInt(). It is used to return the second +* successful read of the temperature value. +* +* Parameters: +* None +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if Flash writing already in use +* CYRET_UNKNOWN if there was an SPC error. +* +* uint8 dieTemperature[2]: +* Holds the die temperature for the flash writing algorithm. The first byte is +* the sign of the temperature (0 = negative, 1 = positive). The second byte is +* the magnitude. +* +*******************************************************************************/ +cystatus CySetTemp(void) +{ + cystatus status = CyFlashGetSpcAlgorithm(); + + if(status == CYRET_SUCCESS) + { + status = CySetTempInt(); + } + + return (status); +} + + +/******************************************************************************* +* Function Name: CySetFlashEEBuffer +******************************************************************************** +* +* Summary: +* Sets the user supplied temporary buffer to store SPC data while performing +* Flash and EEPROM commands. This buffer is only necessary when the Flash ECC is +* disabled. +* +* Parameters: +* buffer: +* The address of a block of memory to store temporary memory. The size of the block +* of memory is CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE. +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_BAD_PARAM if the buffer is NULL +* +*******************************************************************************/ +cystatus CySetFlashEEBuffer(uint8 * buffer) +{ + cystatus status = CYRET_SUCCESS; + + CySpcStart(); + + #if(CYDEV_ECC_ENABLE == 0) + + if(NULL == buffer) + { + rowBuffer = rowBuffer; + status = CYRET_BAD_PARAM; + } + else if(CySpcLock() != CYRET_SUCCESS) + { + rowBuffer = rowBuffer; + status = CYRET_LOCKED; + } + else + { + rowBuffer = buffer; + CySpcUnlock(); + } + + #else + + /* To suppress warning */ + buffer = buffer; + + #endif /* (CYDEV_ECC_ENABLE == 0u) */ + + return(status); +} + + +/******************************************************************************* +* Function Name: CyWriteRowData +******************************************************************************** +* +* Summary: +* Sends a command to the SPC to load and program a row of data in +* Flash or EEPROM. +* +* Parameters: +* arrayID: ID of the array to write. +* The type of write, Flash or EEPROM, is determined from the array ID. +* The arrays in the part are sequential starting at the first ID for the +* specific memory type. The array ID for the Flash memory lasts from 0x00 to +* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F. +* rowAddress: rowAddress of flash row to program. +* rowData: Array of bytes to write. +* +* Return: +* status: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData) +{ + uint16 rowSize; + cystatus status; + + rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? CYDEV_EEPROM_ROW_SIZE : CYDEV_FLS_ROW_SIZE; + status = CyWriteRowFull(arrayId, rowAddress, rowData, rowSize); + + return(status); +} + + +/******************************************************************* +* If "Enable Error Correcting Code (ECC)" and "Store Configuration +* Data in ECC" DWR options are disabled, ECC section is available +* for user data. +*******************************************************************/ +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************************* + * Function Name: CyWriteRowConfig + ******************************************************************************** + * + * Summary: + * Sends a command to the SPC to load and program a row of config data in the Flash. + * This function is only valid for Flash array IDs (not for EEPROM). + * + * Parameters: + * arrayId: ID of the array to write + * The arrays in the part are sequential starting at the first ID for the + * specific memory type. The array ID for the Flash memory lasts + * from 0x00 to 0x3F. + * rowAddress: The address of the sector to erase. + * rowECC: The array of bytes to write. + * + * Return: + * status: + * CYRET_SUCCESS if successful. + * CYRET_LOCKED if the SPC is already in use. + * CYRET_CANCELED if command not accepted + * CYRET_UNKNOWN if there was an SPC error. + * + *******************************************************************************/ + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\ + + { + cystatus status; + + status = CyWriteRowFull(arrayId, rowAddress, rowECC, CYDEV_ECC_ROW_SIZE); + + return (status); + } + +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + +/******************************************************************************* +* Function Name: CyWriteRowFull +******************************************************************************** +* Summary: +* Sends a command to the SPC to load and program a row of data in the Flash. +* rowData array is expected to contain Flash and ECC data if needed. +* +* Parameters: +* arrayId: FLASH or EEPROM array id. +* rowData: Pointer to a row of data to write. +* rowNumber: Zero based number of the row. +* rowSize: Size of the row. +* +* Return: +* CYRET_SUCCESS if successful. +* CYRET_LOCKED if the SPC is already in use. +* CYRET_CANCELED if command not accepted +* CYRET_UNKNOWN if there was an SPC error. +* +*******************************************************************************/ +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \ + +{ + cystatus status = CYRET_SUCCESS; + + if((arrayId <= CY_SPC_LAST_FLASH_ARRAYID) && (arrayId > (CY_FLASH_NUMBER_ARRAYS + CY_SPC_FIRST_FLASH_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId > CY_SPC_LAST_EE_ARRAYID) + { + status = CYRET_BAD_PARAM; + } + + if((arrayId >= CY_SPC_FIRST_EE_ARRAYID) && (arrayId > (CY_FLASH_EEPROM_NUMBER_ARRAYS + CY_SPC_FIRST_EE_ARRAYID))) + { + status = CYRET_BAD_PARAM; + } + + if(arrayId <= CY_SPC_LAST_FLASH_ARRAYID) + { + /* Flash */ + if(rowNumber > (CY_FLASH_NUMBER_ROWS/CY_FLASH_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + } + else + { + /* EEPROM */ + if(rowNumber > (CY_EEPROM_NUMBER_ROWS/CY_FLASH_EEPROM_NUMBER_ARRAYS)) + { + status = CYRET_BAD_PARAM; + } + + if(CY_EEPROM_SIZEOF_ROW != rowSize) + { + status = CYRET_BAD_PARAM; + } + } + + if(rowData == NULL) + { + status = CYRET_BAD_PARAM; + } + + + if(status == CYRET_SUCCESS) + { + if(CySpcLock() == CYRET_SUCCESS) + { + /* Load row data into SPC internal latch */ + status = CySpcLoadRowFull(arrayId, rowNumber, rowData, rowSize); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + + if(CYRET_SUCCESS == status) + { + /* Erase and program flash with data from SPC interval latch */ + status = CySpcWriteRow(arrayId, rowNumber, dieTemperature[0u], dieTemperature[1u]); + + if(CYRET_STARTED == status) + { + while(CY_SPC_BUSY) + { + /* Wait for SPC to finish and get SPC status */ + CyDelayUs(1u); + } + + /* Hide SPC status */ + if(CY_SPC_STATUS_SUCCESS == CY_SPC_READ_STATUS) + { + status = CYRET_SUCCESS; + } + else + { + status = CYRET_UNKNOWN; + } + } + } + } + CySpcUnlock(); + } /* if(CySpcLock() == CYRET_SUCCESS) */ + else + { + status = CYRET_LOCKED; + } + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyFlash_SetWaitCycles +******************************************************************************** +* +* Summary: +* Sets the number of clock cycles the cache will wait before it samples data +* coming back from the Flash. This function must be called before increasing the CPU +* clock frequency. It can optionally be called after lowering the CPU clock +* frequency in order to improve the CPU performance. +* +* Parameters: +* uint8 freq: +* Frequency of operation in Megahertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyFlash_SetWaitCycles(uint8 freq) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*************************************************************************** + * The number of clock cycles the cache will wait before it samples data + * coming back from the Flash must be equal or greater to to the CPU frequency + * outlined in clock cycles. + ***************************************************************************/ + + if (freq < CY_FLASH_CACHE_WS_1_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_1_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_2_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_2_VALUE_MASK; + } + else if (freq < CY_FLASH_CACHE_WS_3_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_3_VALUE_MASK; + } +#if (CY_PSOC5) + else if (freq < CY_FLASH_CACHE_WS_4_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_4_VALUE_MASK; + } + else if (freq <= CY_FLASH_CACHE_WS_5_FREQ_MAX) + { + CY_FLASH_CONTROL_REG = (CY_FLASH_CONTROL_REG & (uint8)(~CY_FLASH_CACHE_WS_VALUE_MASK)) | + CY_FLASH_CACHE_WS_5_VALUE_MASK; + } +#endif /* (CY_PSOC5) */ + else + { + /* Halt CPU in debug mode if frequency is invalid */ + CYASSERT(0u != 0u); + } + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Start +******************************************************************************** +* +* Summary: +* Enable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Start(void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + + /*************************************************************************** + * Enable SPC clock. This also internally enables the 36MHz IMO, since this + * is required for the SPC to function. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG0_REG |= CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC; + CY_FLASH_PM_ALTACT_CFG0_REG |= CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC; + + + /*************************************************************************** + * The wake count defines the number of Bus Clock cycles it takes for the + * flash or EEPROM to wake up from a low power mode independent of the chip + * power mode. Wake up time for these blocks is 5 us. + * The granularity of this register is 2 Bus Clock cycles, so a value of 0x1E + * (30d) defines the wake up time as 60 cycles of the Bus Clock. + * This register needs to be written with a value dependent on the Bus Clock + * frequency so that the duration of the cycles is equal to or greater than + * the 5 us delay required. + ***************************************************************************/ + CY_FLASH_SPC_FM_EE_WAKE_CNT_REG = CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ; + + + /*************************************************************************** + * Enable EEPROM. Re-enabling an EEPROM macro takes 5us. During this time, + * the EE will not acknowledge a PHUB request. + ***************************************************************************/ + CY_FLASH_PM_ACT_CFG12_REG |= CY_FLASH_PM_ACT_CFG12_EN_EE; + CY_FLASH_PM_ALTACT_CFG12_REG |= CY_FLASH_PM_ALTACT_CFG12_EN_EE; + + while(0u == (CY_FLASH_SPC_FM_EE_CR_REG & CY_FLASH_EE_EE_AWAKE)) + { + /* Non-zero status denotes that the EEPROM/Flash is awake & powered. */ + } + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_Stop +******************************************************************************** +* +* Summary: +* Disable the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_Stop (void) +{ + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + CY_FLASH_PM_ACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ACT_CFG12_EN_EE)); + CY_FLASH_PM_ALTACT_CFG12_REG &= ((uint8)(~CY_FLASH_PM_ALTACT_CFG12_EN_EE)); + + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadReserve +******************************************************************************** +* +* Summary: +* Request access to the EEPROM for reading and wait until access is available. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadReserve(void) +{ + /* Make request for PHUB to have access */ + CY_FLASH_EE_SCR_REG |= CY_FLASH_EE_SCR_AHB_EE_REQ; + + while (0u == (CY_FLASH_EE_SCR_REG & CY_FLASH_EE_SCR_AHB_EE_ACK)) + { + /* Wait for acknowledgment from PHUB */ + } +} + + +/******************************************************************************* +* Function Name: CyEEPROM_ReadRelease +******************************************************************************** +* +* Summary: +* Release the read reservation of the EEPROM. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyEEPROM_ReadRelease(void) +{ + CY_FLASH_EE_SCR_REG &= (uint8)(~CY_FLASH_EE_SCR_AHB_EE_REQ); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h new file mode 100644 index 0000000..b8a18c2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyFlash.h @@ -0,0 +1,323 @@ +/******************************************************************************* +* File Name: CyFlash.h +* Version 4.20 +* +* Description: +* Provides the function definitions for the FLASH/EEPROM. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYFLASH_H) +#define CY_BOOT_CYFLASH_H + +#include "cydevice_trm.h" +#include "cytypes.h" +#include "CyLib.h" +#include "CySpc.h" + +#define CY_FLASH_DIE_TEMP_DATA_SIZE (2u) /* Die temperature data size */ + +extern uint8 dieTemperature[CY_FLASH_DIE_TEMP_DATA_SIZE]; + + +/*************************************** +* API Constants +***************************************/ + +#define CY_FLASH_BASE (CYDEV_FLASH_BASE) +#define CY_FLASH_SIZE (CYDEV_FLS_SIZE) +#define CY_FLASH_SIZEOF_ARRAY (CYDEV_FLS_SECTOR_SIZE) +#define CY_FLASH_SIZEOF_ROW (CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define CY_FLASH_NUMBER_ROWS (CYDEV_FLS_SIZE / CYDEV_FLS_ROW_SIZE) +#define CY_FLASH_NUMBER_ARRAYS (CYDEV_FLS_SIZE / CYDEV_FLS_SECTOR_SIZE) + +#if(CYDEV_ECC_ENABLE == 0) + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW + CY_FLASH_SIZEOF_ECC_ROW) +#else + #define CY_FLASH_SIZEOF_FULL_ROW (CY_FLASH_SIZEOF_ROW) +#endif /* (CYDEV_ECC_ENABLE == 0) */ +#define CY_EEPROM_BASE (CYDEV_EE_BASE) +#define CY_EEPROM_SIZE (CYDEV_EE_SIZE) +#define CY_EEPROM_SIZEOF_ARRAY (CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_ROW (CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ROWS (CYDEV_EE_SIZE / CYDEV_EEPROM_ROW_SIZE) +#define CY_EEPROM_NUMBER_ARRAYS (CYDEV_EE_SIZE / CY_EEPROM_SIZEOF_ARRAY) +#define CY_EEPROM_NUMBER_SECTORS (CYDEV_EE_SIZE / CYDEV_EEPROM_SECTOR_SIZE) +#define CY_EEPROM_SIZEOF_SECTOR (CYDEV_EEPROM_SECTOR_SIZE) + +#if !defined(CYDEV_FLS_BASE) + #define CYDEV_FLS_BASE CYDEV_FLASH_BASE +#endif /* !defined(CYDEV_FLS_BASE) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/* Flash Functions */ +void CyFlash_Start(void); +void CyFlash_Stop(void); +cystatus CySetTemp(void); +cystatus CySetFlashEEBuffer(uint8 * buffer); +cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8 * rowData, uint16 rowSize) \ + ; +cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData); + +#if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC) \ + ; +#endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + +void CyFlash_SetWaitCycles(uint8 freq) ; + +/* EEPROM Functions */ +void CyEEPROM_Start(void) ; +void CyEEPROM_Stop(void) ; + +void CyEEPROM_ReadReserve(void) ; +void CyEEPROM_ReadRelease(void) ; + + +/*************************************** +* Registers +***************************************/ +/* Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0) +#define CY_FLASH_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Alternate Active Power Mode Configuration Register 0 */ +#define CY_FLASH_PM_ALTACT_CFG0_REG (* (reg8 *) CYREG_PM_STBY_CFG0) +#define CY_FLASH_PM_ALTACT_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ACT_CFG12_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_CFG12_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) + +/* Alternate Active Power Mode Configuration Register 12 */ +#define CY_FLASH_PM_ALTACT_CFG12_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_CFG12_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) + +/* Wake count (BUS_CLK cycles) it takes for the Flash and EEPROM to wake up */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_REG (* (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_PTR ( (reg8 *) CYREG_SPC_FM_EE_WAKE_CNT) + +/* Flash macro control register */ +#define CY_FLASH_SPC_FM_EE_CR_REG (* (reg8 *) CYREG_SPC_FM_EE_CR) +#define CY_FLASH_SPC_FM_EE_CR_PTR ( (reg8 *) CYREG_SPC_FM_EE_CR) + + +/* Cache Control Register */ +#if (CY_PSOC3) + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else + + #define CY_FLASH_CONTROL_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_FLASH_CONTROL_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* EEPROM Status & Control Register */ +#define CY_FLASH_EE_SCR_REG (* (reg8 *) CYREG_SPC_EE_SCR) +#define CY_FLASH_EE_SCR_PTR ( (reg8 *) CYREG_SPC_EE_SCR) + + + +/*************************************** +* Register Constants +***************************************/ + +/* Power Mode Masks */ + +/* Enable EEPROM */ +#define CY_FLASH_PM_ACT_CFG12_EN_EE (0x10u) +#define CY_FLASH_PM_ALTACT_CFG12_EN_EE (0x10u) + +/* Enable Flash */ +#if (CY_PSOC3) + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x01u) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x01u) +#else + #define CY_FLASH_PM_ACT_CFG12_EN_FM (0x0Fu) + #define CY_FLASH_PM_ALTACT_CFG12_EN_FM (0x0Fu) +#endif /* (CY_PSOC3) */ + + + +/* Frequency Constants */ +#if (CY_PSOC3) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (22u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (44u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (67u) +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + #define CY_FLASH_CACHE_WS_VALUE_MASK (0xE0u) + #define CY_FLASH_CACHE_WS_1_VALUE_MASK (0x40u) + #define CY_FLASH_CACHE_WS_2_VALUE_MASK (0x80u) + #define CY_FLASH_CACHE_WS_3_VALUE_MASK (0xC0u) + #define CY_FLASH_CACHE_WS_4_VALUE_MASK (0x00u) + #define CY_FLASH_CACHE_WS_5_VALUE_MASK (0x20u) + + #define CY_FLASH_CACHE_WS_1_FREQ_MAX (16u) + #define CY_FLASH_CACHE_WS_2_FREQ_MAX (33u) + #define CY_FLASH_CACHE_WS_3_FREQ_MAX (50u) + #define CY_FLASH_CACHE_WS_4_FREQ_MAX (67u) + #define CY_FLASH_CACHE_WS_5_FREQ_MAX (83u) +#endif /* (CY_PSOC5) */ + +#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u) +#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT))) + +#define CY_FLASH_EE_SCR_AHB_EE_REQ (0x01u) +#define CY_FLASH_EE_SCR_AHB_EE_ACK (0x02u) + + +#define CY_FLASH_EE_EE_AWAKE (0x20u) + +/* 5(us) * BUS_CLK(80 MHz) / granularity(2) */ +#define CY_FLASH_SPC_FM_EE_WAKE_CNT_80MHZ (0xC8u) + +/* Enable clk_spc. This also internally enables the 36MHz IMO. */ +#define CY_FLASH_PM_ACT_CFG0_EN_CLK_SPC (0x08u) +#define CY_FLASH_PM_ALTACT_CFG0_EN_CLK_SPC (0x08u) + +/* Default values for getting temperature. */ + +#define CY_TEMP_NUMBER_OF_SAMPLES (0x1u) +#define CY_TEMP_TIMER_PERIOD (0xFFFu) +#define CY_TEMP_CLK_DIV_SELECT (0x4u) +#define CY_TEMP_NUM_SAMPLES (1 << (CY_TEMP_NUMBER_OF_SAMPLES)) +#define CY_SPC_CLK_PERIOD (120u) /* nS */ +#define CY_SYS_ns_PER_TICK (1000u) +#define CY_FRM_EXEC_TIME (1000u) /* nS */ + +#define CY_GET_TEMP_TIME ((1 << (CY_TEMP_NUM_SAMPLES + 1)) * \ + (CY_SPC_CLK_PERIOD * CY_TEMP_CLK_DIV_SELECT) * \ + CY_TEMP_TIMER_PERIOD + CY_FRM_EXEC_TIME) + +#define CY_TEMP_MAX_WAIT ((CY_GET_TEMP_TIME) / CY_SYS_ns_PER_TICK) /* In system ticks. */ + + +/******************************************************************************* +* Thne following code is OBSOLETE and must not be used starting with cy_boot +* 4.20. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if (CY_PSOC5) + #define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u) + #define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u) + #define CY_FLASH_GREATER_51MHz (0x00u) +#endif /* (CY_PSOC5) */ + +#if (CY_PSOC3) + #define CY_FLASH_LESSER_OR_EQUAL_22MHz (0x01u) + #define CY_FLASH_LESSER_OR_EQUAL_44MHz (0x02u) + #define CY_FLASH_GREATER_44MHz (0x03u) +#endif /* (CY_PSOC3) */ + +#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12) +#define CY_FLASH_PM_EE_MASK (0x10u) +#define CY_FLASH_PM_FLASH_MASK (0x01u) + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.0 +*******************************************************************************/ +#define FLASH_SIZE (CY_FLASH_SIZE) +#define FLASH_SIZEOF_SECTOR (CY_FLASH_SIZEOF_ARRAY) +#define FLASH_NUMBER_ROWS (CY_FLASH_NUMBER_ROWS) +#define FLASH_NUMBER_SECTORS (CY_FLASH_NUMBER_ARRAYS) +#define EEPROM_SIZE (CY_EEPROM_SIZE) +#define EEPROM_SIZEOF_SECTOR (CY_EEPROM_SIZEOF_ARRAY) +#define EEPROM_NUMBER_ROWS (CY_EEPROM_NUMBER_ROWS) +#define EEPROM_NUMBER_SECTORS (CY_EEPROM_NUMBER_ARRAYS) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +*******************************************************************************/ +#define FLASH_CYCLES_PTR (CY_FLASH_CONTROL_PTR) + +#define TEMP_NUMBER_OF_SAMPLES (CY_TEMP_NUMBER_OF_SAMPLES) +#define TEMP_TIMER_PERIOD (CY_TEMP_TIMER_PERIOD) +#define TEMP_CLK_DIV_SELECT (CY_TEMP_CLK_DIV_SELECT) +#define NUM_SAMPLES (CY_TEMP_NUM_SAMPLES) +#define SPC_CLK_PERIOD (CY_SPC_CLK_PERIOD) +#define FRM_EXEC_TIME (CY_FRM_EXEC_TIME) +#define GET_TEMP_TIME (CY_GET_TEMP_TIME) +#define TEMP_MAX_WAIT (CY_TEMP_MAX_WAIT) + +#define ECC_ADDR (0x80u) + + +#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) +#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR) + +#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) +#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR) + +#define PM_EE_MASK (CY_FLASH_PM_EE_MASK) +#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK) + +#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT) +#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK) + + +#if (CY_PSOC3) + + #define LESSER_OR_EQUAL_22MHz (CY_FLASH_LESSER_OR_EQUAL_22MHz) + #define LESSER_OR_EQUAL_44MHz (CY_FLASH_LESSER_OR_EQUAL_44MHz) + #define GREATER_44MHz (CY_FLASH_GREATER_44MHz) + +#endif /* (CY_PSOC3) */ + +#if (CY_PSOC5) + + #define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz) + #define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz) + #define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz) + #define LESSER_OR_EQUAL_67MHz (CY_FLASH_LESSER_OR_EQUAL_67MHz) + #define GREATER_67MHz (CY_FLASH_GREATER_67MHz) + #define GREATER_51MHz (CY_FLASH_GREATER_51MHz) + +#endif /* (CY_PSOC5) */ + +#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR) + + +#endif /* (CY_BOOT_CYFLASH_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c new file mode 100644 index 0000000..8d3c1c4 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.c @@ -0,0 +1,3105 @@ +/******************************************************************************* +* File Name: CyLib.c +* Version 4.20 +* +* Description: +* Provides a system API for the clocking, interrupts and watchdog timer. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CyLib.h" + + +/******************************************************************************* +* The CyResetStatus variable is used to obtain value of RESET_SR0 register after +* a device reset. It is set from initialize_psoc() at the early initialization +* stage. In case of IAR EW IDE, initialize_psoc() is executed before the data +* sections are initialized. To avoid zeroing, CyResetStatus should be placed +* to the .noinit section. +*******************************************************************************/ +CY_NOINIT uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + uint8 CyScPumpEnabled = (uint8)(CYDEV_VDDA_MV < 2700); + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +uint32 cydelay_freq_hz = BCLK__BUS_CLK__HZ; +uint32 cydelay_freq_khz = (BCLK__BUS_CLK__HZ + 999u) / 1000u; +uint8 cydelay_freq_mhz = (uint8)((BCLK__BUS_CLK__HZ + 999999u) / 1000000u); +uint32 cydelay_32k_ms = 32768u * ((BCLK__BUS_CLK__HZ + 999u) / 1000u); + + +/* Function Prototypes */ +static uint8 CyUSB_PowerOnCheck(void) ; +static void CyIMO_SetTrimValue(uint8 freq) ; +static void CyBusClk_Internal_SetDivider(uint16 divider); + +#if(CY_PSOC5) + static cySysTickCallback CySysTickCallbacks[CY_SYS_SYST_NUM_OF_CALLBACKS]; + static void CySysTickServiceCallbacks(void); + uint32 CySysTickInitVar = 0u; +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Start +******************************************************************************** +* +* Summary: +* Enables the PLL. Optionally waits for it to become stable. +* Waits at least 250 us or until it is detected that the PLL is stable. +* +* Parameters: +* wait: +* 0: Return immediately after configuration +* 1: Wait for PLL lock or timeout. +* +* Return: +* Status +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a stable clock. +* If the input source of the clock is jittery, then the lock indication +* may not occur. However, after the timeout has expired the generated PLL +* clock can still be used. +* +* Side Effects: +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + + uint8 iloEnableState; + uint8 pmTwCfg0State; + uint8 pmTwCfg2State; + + + /* Enables PLL circuit */ + CY_CLK_PLL_CFG0_REG |= CY_CLK_PLL_ENABLE; + + if(wait != 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmTwCfg0State = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2State = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_CLK_PLL_FTW_INTERVAL); + + status = CYRET_TIMEOUT; + + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + if(0u != (CY_CLK_PLL_SR_REG & CY_CLK_PLL_LOCK_STATUS)) + { + status = CYRET_SUCCESS; + break; + } + } + } + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == iloEnableState) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0State; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2State; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_Stop +******************************************************************************** +* +* Summary: +* Disables the PLL. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPLL_OUT_Stop(void) +{ + CY_CLK_PLL_CFG0_REG &= ((uint8)(~CY_CLK_PLL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetPQ +******************************************************************************** +* +* Summary: +* Sets the P and Q dividers and the charge pump current. +* The Frequency Out will be P/Q * Frequency In. +* The PLL must be disabled before calling this function. +* +* Parameters: +* uint8 pDiv: +* Valid range [8 - 255]. +* +* uint8 qDiv: +* Valid range [1 - 16]. Input Frequency / Q must be in range of 1 to 3 MHz. + +* uint8 current: +* Valid range [1 - 7]. Charge pump current in uA. Refer to the device TRM and +* datasheet for more information. +* +* Return: +* None +* +* Side Effects: +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + if((pDiv >= CY_CLK_PLL_MIN_P_VALUE ) && + (qDiv <= CY_CLK_PLL_MAX_Q_VALUE ) && (qDiv >= CY_CLK_PLL_MIN_Q_VALUE ) && + (current >= CY_CLK_PLL_MIN_CUR_VALUE) && (current <= CY_CLK_PLL_MAX_CUR_VALUE)) + { + /* Set new values */ + CY_CLK_PLL_P_REG = pDiv; + CY_CLK_PLL_Q_REG = ((uint8)(qDiv - 1u)); + CY_CLK_PLL_CFG1_REG = (CY_CLK_PLL_CFG1_REG & CY_CLK_PLL_CURRENT_MASK) | + ((uint8)(((uint8)(current - 1u)) << CY_CLK_PLL_CURRENT_POSITION)); + } + else + { + /*********************************************************************** + * Halt CPU in debug mode if: + * - P divider is less than required + * - Q divider is out of range + * - pump current is out of range + ***********************************************************************/ + CYASSERT(0u != 0u); + } + +} + + +/******************************************************************************* +* Function Name: CyPLL_OUT_SetSource +******************************************************************************** +* +* Summary: +* Sets the input clock source to the PLL. The PLL must be disabled before +* calling this function. +* +* Parameters: +* source: One of the three available PLL clock sources +* CY_PLL_SOURCE_IMO : IMO +* CY_PLL_SOURCE_XTAL : MHz Crystal +* CY_PLL_SOURCE_DSI : DSI +* +* Return: +* None +* +* Side Effects: +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the3 Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyPLL_OUT_SetSource(uint8 source) +{ + /* Halt CPU in debug mode if PLL is enabled */ + CYASSERT(0u == (CY_CLK_PLL_CFG0_REG & CY_CLK_PLL_ENABLE)); + + switch(source) + { + case CY_PLL_SOURCE_IMO: + case CY_PLL_SOURCE_XTAL: + case CY_PLL_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG = ((CY_LIB_CLKDIST_CR_REG & CY_LIB_CLKDIST_CR_PLL_SCR_MASK) | source); + break; + + default: + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Start +******************************************************************************** +* +* Summary: +* Enables the IMO. Optionally waits at least 6 us for it to settle. +* +* Parameters: +* uint8 wait: +* 0: Return immediately after configuration +* 1: Wait for at least 6 us for the IMO to settle. +* +* Return: +* None +* +* Side Effects: +* If wait is enabled: This function uses the Fast Time Wheel to time the wait. +* Any other use of the Fast Time Wheel will be stopped during the period of +* this function and then restored. This function also uses the 100 KHz ILO. +* If not enabled, this function will enable the 100 KHz ILO for the period of +* this function. +* +* No changes to the setup of the ILO, Fast Time Wheel, Central Time Wheel or +* Once Per Second interrupt may be made by interrupt routines during the period +* of this function execution. The current operation of the ILO, Central Time +* Wheel and Once Per Second interrupt are maintained during the operation of +* this function provided the reading of the Power Manager Interrupt Status +* Register is only done using the CyPmReadStatus() function. +* +*******************************************************************************/ +void CyIMO_Start(uint8 wait) +{ + uint8 pmFtwCfg2Reg; + uint8 pmFtwCfg0Reg; + uint8 ilo100KhzEnable; + + + CY_LIB_PM_ACT_CFG0_REG |= CY_LIB_PM_ACT_CFG0_IMO_EN; + CY_LIB_PM_STBY_CFG0_REG |= CY_LIB_PM_STBY_CFG0_IMO_EN; + + if(0u != wait) + { + /* Need to turn on 100KHz ILO if it happens to not already be running.*/ + ilo100KhzEnable = CY_LIB_SLOWCLK_ILO_CR0_REG & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; + pmFtwCfg0Reg = CY_LIB_PM_TW_CFG0_REG; + pmFtwCfg2Reg = CY_LIB_PM_TW_CFG2_REG; + + CyPmFtwSetInterval(CY_LIB_CLK_IMO_FTW_TIMEOUT); + + while (0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for interrupt status */ + } + + if(0u == ilo100KhzEnable) + { + CyILO_Stop100K(); + } + + CY_LIB_PM_TW_CFG0_REG = pmFtwCfg0Reg; + CY_LIB_PM_TW_CFG2_REG = pmFtwCfg2Reg; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_Stop +******************************************************************************** +* +* Summary: +* Disables the IMO. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_Stop(void) +{ + CY_LIB_PM_ACT_CFG0_REG &= ((uint8) (~CY_LIB_PM_ACT_CFG0_IMO_EN)); + CY_LIB_PM_STBY_CFG0_REG &= ((uint8) (~CY_LIB_PM_STBY_CFG0_IMO_EN)); +} + + +/******************************************************************************* +* Function Name: CyUSB_PowerOnCheck +******************************************************************************** +* +* Summary: +* Returns the USB power status value. A private function to cy_boot. +* +* Parameters: +* None +* +* Return: +* uint8: one if the USB is enabled, 0 if not enabled. +* +*******************************************************************************/ +static uint8 CyUSB_PowerOnCheck(void) +{ + uint8 poweredOn = 0u; + + /* Check whether device is in Active or AltActiv and if USB is powered on */ + if((((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ACTIVE ) && + (0u != (CY_LIB_PM_ACT_CFG5_REG & CY_ACT_USB_ENABLED ))) || + (((CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_MASK) == CY_PM_MODE_CSR_ALT_ACT) && + (0u != (CY_LIB_PM_STBY_CFG5_REG & CY_ALT_ACT_USB_ENABLED)))) + { + poweredOn = 1u; + } + + return (poweredOn); +} + + +/******************************************************************************* +* Function Name: CyIMO_SetTrimValue +******************************************************************************** +* +* Summary: +* Sets the IMO factory trim values. +* +* Parameters: +* uint8 freq - frequency for which trims must be set +* +* Return: +* None +* +*******************************************************************************/ +static void CyIMO_SetTrimValue(uint8 freq) +{ + uint8 usbPowerOn = CyUSB_PowerOnCheck(); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Unlock USB write */ + CY_LIB_USB_CR1_REG &= ((uint8)(~CY_LIB_USB_CLK_EN)); + } + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_3MHZ_PTR); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_6MHZ_PTR); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_12MHZ_PTR); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_24MHZ_PTR); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_TR1_PTR); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_67MHZ_PTR); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_80MHZ_PTR); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_IMO_TR1_REG = CY_GET_XTND_REG8(CY_LIB_TRIM_IMO_USB_PTR); + + /* If USB is powered */ + if(usbPowerOn == 1u) + { + /* Lock USB Oscillator */ + CY_LIB_USB_CR1_REG |= CY_LIB_USB_CLK_EN; + } + break; + + default: + CYASSERT(0u != 0u); + break; + } + +} + + +/******************************************************************************* +* Function Name: CyIMO_SetFreq +******************************************************************************** +* +* Summary: +* Sets the frequency of the IMO. Changes may be made while the IMO is running. +* +* Parameters: +* freq: Frequency of IMO operation +* CY_IMO_FREQ_3MHZ to set 3 MHz +* CY_IMO_FREQ_6MHZ to set 6 MHz +* CY_IMO_FREQ_12MHZ to set 12 MHz +* CY_IMO_FREQ_24MHZ to set 24 MHz +* CY_IMO_FREQ_48MHZ to set 48 MHz +* CY_IMO_FREQ_62MHZ to set 62.6 MHz +* CY_IMO_FREQ_74MHZ to set 74.7 MHz (not applicable for PSoC 3) +* CY_IMO_FREQ_USB to set 24 MHz (Trimmed for USB operation) +* +* Return: +* None +* +* Side Effects: +* If this function execution results in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When the USB setting is chosen, the USB clock locking circuit is enabled. +* Otherwise this circuit is disabled. The USB block must be powered before +* selecting the USB setting. +* +*******************************************************************************/ +void CyIMO_SetFreq(uint8 freq) +{ + uint8 currentFreq; + uint8 nextFreq; + + /*************************************************************************** + * If the IMO frequency is changed,the Trim values must also be set + * accordingly.This requires reading the current frequency. If the new + * frequency is faster, then set a new trim and then change the frequency, + * otherwise change the frequency and then set new trim values. + ***************************************************************************/ + + currentFreq = CY_LIB_FASTCLK_IMO_CR_REG & ((uint8)(~CY_LIB_FASTCLK_IMO_CR_RANGE_MASK)); + + /* Check if requested frequency is USB. */ + nextFreq = (freq == CY_IMO_FREQ_USB) ? CY_IMO_FREQ_24MHZ : freq; + + switch (currentFreq) + { + case 0u: + currentFreq = CY_IMO_FREQ_12MHZ; + break; + + case 1u: + currentFreq = CY_IMO_FREQ_6MHZ; + break; + + case 2u: + currentFreq = CY_IMO_FREQ_24MHZ; + break; + + case 3u: + currentFreq = CY_IMO_FREQ_3MHZ; + break; + + case 4u: + currentFreq = CY_IMO_FREQ_48MHZ; + break; + + case 5u: + currentFreq = CY_IMO_FREQ_62MHZ; + break; + +#if(CY_PSOC5) + case 6u: + currentFreq = CY_IMO_FREQ_74MHZ; + break; +#endif /* (CY_PSOC5) */ + + default: + CYASSERT(0u != 0u); + break; + } + + if (nextFreq >= currentFreq) + { + /* Set new trim first */ + CyIMO_SetTrimValue(freq); + } + + /* Set usbclk_on bit when using CY_IMO_FREQ_USB, if not clear it */ + switch(freq) + { + case CY_IMO_FREQ_3MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_3MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_6MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_6MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_12MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_12MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_24MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_48MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_48MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + + case CY_IMO_FREQ_62MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_62MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; + +#if(CY_PSOC5) + case CY_IMO_FREQ_74MHZ: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_74MHZ_VALUE) & ((uint8)(~CY_LIB_IMO_USBCLK_ON_SET)); + break; +#endif /* (CY_PSOC5) */ + + case CY_IMO_FREQ_USB: + CY_LIB_FASTCLK_IMO_CR_REG = ((CY_LIB_FASTCLK_IMO_CR_REG & CY_LIB_FASTCLK_IMO_CR_RANGE_MASK) | + CY_LIB_IMO_24MHZ_VALUE) | CY_LIB_IMO_USBCLK_ON_SET; + break; + + default: + CYASSERT(0u != 0u); + break; + } + + /* Tu rn onIMO Doubler, if switching to CY_IMO_FREQ_USB */ + if (freq == CY_IMO_FREQ_USB) + { + CyIMO_EnableDoubler(); + } + else + { + CyIMO_DisableDoubler(); + } + + if (nextFreq < currentFreq) + { + /* Set the trim after setting frequency */ + CyIMO_SetTrimValue(freq); + } +} + + +/******************************************************************************* +* Function Name: CyIMO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the IMO block. +* +* The output from the IMO is by default the IMO itself. Optionally the MHz +* Crystal or DSI input can be the source of the IMO output instead. +* +* Parameters: +* source: CY_IMO_SOURCE_DSI to set the DSI as source. +* CY_IMO_SOURCE_XTAL to set the MHz as source. +* CY_IMO_SOURCE_IMO to set the IMO itself. +* +* Return: +* None +* +* Side Effects: +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyIMO_SetSource(uint8 source) +{ + switch(source) + { + case CY_IMO_SOURCE_DSI: + CY_LIB_CLKDIST_CR_REG &= ((uint8)(~CY_LIB_CLKDIST_CR_IMO2X)); + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_XTAL: + CY_LIB_CLKDIST_CR_REG |= CY_LIB_CLKDIST_CR_IMO2X; + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_IMO; + break; + + case CY_IMO_SOURCE_IMO: + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_IMO)); + break; + + default: + /* Incorrect source value */ + CYASSERT(0u != 0u); + break; + } +} + + +/******************************************************************************* +* Function Name: CyIMO_EnableDoubler +******************************************************************************** +* +* Summary: +* Enables the IMO doubler. The 2x frequency clock is used to convert a 24 MHz +* input to a 48 MHz output for use by the USB block. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_EnableDoubler(void) +{ + /* Set FASTCLK_IMO_CR_PTR regigster's 4th bit */ + CY_LIB_FASTCLK_IMO_CR_REG |= CY_LIB_FASTCLK_IMO_DOUBLER; +} + + +/******************************************************************************* +* Function Name: CyIMO_DisableDoubler +******************************************************************************** +* +* Summary: +* Disables the IMO doubler. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyIMO_DisableDoubler(void) +{ + CY_LIB_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_LIB_FASTCLK_IMO_DOUBLER)); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the master clock. +* +* Parameters: +* source: One of the four available Master clock sources. +* CY_MASTER_SOURCE_IMO +* CY_MASTER_SOURCE_PLL +* CY_MASTER_SOURCE_XTAL +* CY_MASTER_SOURCE_DSI +* +* Return: +* None +* +* Side Effects: +* The current source and the new source must both be running and stable before +* calling this function. +* +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyMasterClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & MASTER_CLK_SRC_CLEAR) | + (source & ((uint8)(~MASTER_CLK_SRC_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyMasterClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate Master Clock. +* +* Parameters: +* uint8 divider: +* The valid range is [0-255]. The clock will be divided by this value + 1. +* For example to divide this parameter by two should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +* When changing the Master or Bus clock divider value from div-by-n to div-by-1 +* the first clock cycle output after the div-by-1 can be up to 4 ns shorter +* than the final/expected div-by-1 period. +* +*******************************************************************************/ +void CyMasterClk_SetDivider(uint8 divider) +{ + CY_LIB_CLKDIST_MSTR0_REG = divider; +} + + +/******************************************************************************* +* Function Name: CyBusClk_Internal_SetDivider +******************************************************************************** +* +* Summary: +* The function used by CyBusClk_SetDivider(). For internal use only. +* +* Parameters: +* divider: Valid range [0-65535]. +* The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +* Return: +* None +* +*******************************************************************************/ +static void CyBusClk_Internal_SetDivider(uint16 divider) +{ + /* Mask bits to enable shadow loads */ + CY_LIB_CLKDIST_AMASK_REG &= CY_LIB_CLKDIST_AMASK_MASK; + CY_LIB_CLKDIST_DMASK_REG = CY_LIB_CLKDIST_DMASK_MASK; + + /* Enable mask bits to enable shadow loads */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_MASK; + + /* Update Shadow Divider Value Register with new divider */ + CY_LIB_CLKDIST_WRK_LSB_REG = LO8(divider); + CY_LIB_CLKDIST_WRK_MSB_REG = HI8(divider); + + + /*************************************************************************** + * Copy shadow value defined in Shadow Divider Value Register + * (CY_LIB_CLKDIST_WRK_LSB_REG and CY_LIB_CLKDIST_WRK_MSB_REG) to all + * dividers selected in Analog and Digital Clock Mask Registers + * (CY_LIB_CLKDIST_AMASK_REG and CY_LIB_CLKDIST_DMASK_REG). + ***************************************************************************/ + CY_LIB_CLKDIST_LD_REG |= CY_LIB_CLKDIST_LD_LOAD; +} + + +/******************************************************************************* +* Function Name: CyBusClk_SetDivider +******************************************************************************** +* +* Summary: +* Sets the divider value used to generate the Bus Clock. +* +* Parameters: +* divider: Valid range [0-65535]. The clock will be divided by this value + 1. +* For example, to divide this parameter by two should be set to 1. +* +* Return: +* None +* +* Side Effects: +* If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. +* See CyFlash_SetWaitCycles() description for more information. +* +*******************************************************************************/ +void CyBusClk_SetDivider(uint16 divider) +{ + uint8 masterClkDiv; + uint16 busClkDiv; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + /* Work around to set bus clock divider value */ + busClkDiv = (uint16)((uint16)CY_LIB_CLKDIST_BCFG_MSB_REG << 8u); + busClkDiv |= CY_LIB_CLKDIST_BCFG_LSB_REG; + + if ((divider == 0u) || (busClkDiv == 0u)) + { + /* Save away master clock divider value */ + masterClkDiv = CY_LIB_CLKDIST_MSTR0_REG; + + if (masterClkDiv < CY_LIB_CLKDIST_MASTERCLK_DIV) + { + /* Set master clock divider to 7 */ + CyMasterClk_SetDivider(CY_LIB_CLKDIST_MASTERCLK_DIV); + } + + if (divider == 0u) + { + /* Set SSS bit and divider register desired value */ + CY_LIB_CLKDIST_BCFG2_REG |= CY_LIB_CLKDIST_BCFG2_SSS; + CyBusClk_Internal_SetDivider(divider); + } + else + { + CyBusClk_Internal_SetDivider(divider); + CY_LIB_CLKDIST_BCFG2_REG &= ((uint8)(~CY_LIB_CLKDIST_BCFG2_SSS)); + } + + /* Restore master clock */ + CyMasterClk_SetDivider(masterClkDiv); + } + else + { + CyBusClk_Internal_SetDivider(divider); + } + + CyExitCriticalSection(interruptState); +} + + +#if(CY_PSOC3) + + /******************************************************************************* + * Function Name: CyCpuClk_SetDivider + ******************************************************************************** + * + * Summary: + * Sets the divider value used to generate the CPU Clock. Only applicable for + * PSoC 3 parts. + * + * Parameters: + * divider: Valid range [0-15]. The clock will be divided by this value + 1. + * For example, to divide this parameter by two should be set to 1. + * + * Return: + * None + * + * Side Effects: + * If this function execution resulted in the CPU clock frequency increasing, +* then the number of clock cycles the cache will wait before it samples data +* coming back from the Flash must be adjusted by calling CyFlash_SetWaitCycles() +* with an appropriate parameter. It can be optionally called if the CPU clock +* frequency is lowered in order to improve the CPU performance. + * See CyFlash_SetWaitCycles() description for more information. + * + *******************************************************************************/ + void CyCpuClk_SetDivider(uint8 divider) + { + CY_LIB_CLKDIST_MSTR1_REG = (CY_LIB_CLKDIST_MSTR1_REG & CY_LIB_CLKDIST_MSTR1_DIV_MASK) | + ((uint8)(divider << CY_LIB_CLKDIST_DIV_POSITION)); + } + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyUsbClk_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the USB clock. +* +* Parameters: +* source: One of the four available USB clock sources +* CY_LIB_USB_CLK_IMO2X - IMO 2x +* CY_LIB_USB_CLK_IMO - IMO +* CY_LIB_USB_CLK_PLL - PLL +* CY_LIB_USB_CLK_DSI - DSI +* +* Return: +* None +* +*******************************************************************************/ +void CyUsbClk_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_UCFG_REG = (CY_LIB_CLKDIST_UCFG_REG & ((uint8)(~CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK))) | + (CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK & source); +} + + +/******************************************************************************* +* Function Name: CyILO_Start1K +******************************************************************************** +* +* Summary: +* Enables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator is always enabled by default, regardless of the +* selection in the Clock Editor. Therefore, this API is only needed if the +* oscillator was turned off manually. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start1K(void) +{ + /* Set bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop1K +******************************************************************************** +* +* Summary: +* Disables the ILO 1 KHz oscillator. +* +* Note The ILO 1 KHz oscillator must be enabled if the Sleep or Hibernate low power +* mode APIs are expected to be used. For more information, refer to the Power +* Management section of this document. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* PSoC5: Stopping the ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyILO_Stop1K(void) +{ + /* Clear bit 1 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Start100K +******************************************************************************** +* +* Summary: +* Enables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Start100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Stop100K +******************************************************************************** +* +* Summary: +* Disables the ILO 100 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Stop100K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_Enable33K +******************************************************************************** +* +* Summary: +* Enables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, +* so it must also be running in order to generate the 33 KHz output. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Enable33K(void) +{ + /* Set bit 5 of ILO RS */ + CY_LIB_SLOWCLK_ILO_CR0_REG |= CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ; +} + + +/******************************************************************************* +* Function Name: CyILO_Disable33K +******************************************************************************** +* +* Summary: +* Disables the ILO 33 KHz divider. +* +* Note that the 33 KHz clock is generated from the 100 KHz oscillator, but this +* API does not disable the 100 KHz clock. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_Disable33K(void) +{ + CY_LIB_SLOWCLK_ILO_CR0_REG &= ((uint8)(~CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ)); +} + + +/******************************************************************************* +* Function Name: CyILO_SetSource +******************************************************************************** +* +* Summary: +* Sets the source of the clock output from the ILO block. +* +* Parameters: +* source: One of the three available ILO output sources +* Value Define Source +* 0 CY_ILO_SOURCE_100K ILO 100 KHz +* 1 CY_ILO_SOURCE_33K ILO 33 KHz +* 2 CY_ILO_SOURCE_1K ILO 1 KHz +* +* Return: +* None +* +*******************************************************************************/ +void CyILO_SetSource(uint8 source) +{ + CY_LIB_CLKDIST_CR_REG = (CY_LIB_CLKDIST_CR_REG & CY_ILO_SOURCE_BITS_CLEAR) | + (((uint8) (source << 2u)) & ((uint8)(~CY_ILO_SOURCE_BITS_CLEAR))); +} + + +/******************************************************************************* +* Function Name: CyILO_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode used by the ILO during power down. Allows for lower power +* down power usage resulting in a slower startup time. +* +* Parameters: +* uint8 mode +* CY_ILO_FAST_START - Faster start-up, internal bias left on when powered down +* CY_ILO_SLOW_START - Slower start-up, internal bias off when powered down +* +* Return: +* Prevous power mode state. +* +*******************************************************************************/ +uint8 CyILO_SetPowerMode(uint8 mode) +{ + uint8 state; + + /* Get current state. */ + state = CY_LIB_SLOWCLK_ILO_CR0_REG; + + /* Set the oscillator power mode. */ + if(mode != CY_ILO_FAST_START) + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state | CY_ILO_CONTROL_PD_MODE); + } + else + { + CY_LIB_SLOWCLK_ILO_CR0_REG = (state & ((uint8)(~CY_ILO_CONTROL_PD_MODE))); + } + + /* Return old mode. */ + return ((state & CY_ILO_CONTROL_PD_MODE) >> CY_ILO_CONTROL_PD_POSITION); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Start +******************************************************************************** +* +* Summary: +* Enables the 32 KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Start(void) +{ + volatile uint16 i; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_STARTUP; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_PDBEN; + #endif /* (CY_PSOC3) */ + + /* Enable operation of 32K Crystal Oscillator */ + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_EN; + + for (i = 1000u; i > 0u; i--) + { + if(0u != (CyXTAL_32KHZ_ReadStatus() & CY_XTAL32K_ANA_STAT)) + { + /* Ready - switch to high power mode */ + (void) CyXTAL_32KHZ_SetPowerMode(0u); + + break; + } + CyDelayUs(1u); + } +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_Stop +******************************************************************************** +* +* Summary: +* Disables the 32KHz Crystal Oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_32KHZ_Stop(void) +{ + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_POWERDOWN; + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~(CY_CLK_XTAL32_CR_EN | CY_CLK_XTAL32_CR_LPM))); + + #if(CY_PSOC3) + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_PDBEN)); + #endif /* (CY_PSOC3) */ +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_ReadStatus +******************************************************************************** +* +* Summary: +* Returns status of the 32 KHz oscillator. +* +* Parameters: +* None +* +* Return: +* Value Define Source +* 20 CY_XTAL32K_ANA_STAT Analog measurement +* 1: Stable +* 0: Not stable +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_ReadStatus(void) +{ + return(CY_CLK_XTAL32_CR_REG & CY_XTAL32K_ANA_STAT); +} + + +/******************************************************************************* +* Function Name: CyXTAL_32KHZ_SetPowerMode +******************************************************************************** +* +* Summary: +* Sets the power mode for the 32 KHz oscillator used during the sleep mode. +* Allows for lower power during sleep when there are fewer sources of noise. +* During the active mode the oscillator is always run in the high power mode. +* +* Parameters: +* uint8 mode +* 0: High power mode +* 1: Low power mode during sleep +* +* Return: +* Previous power mode. +* +*******************************************************************************/ +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) +{ + uint8 state = (0u != (CY_CLK_XTAL32_CR_REG & CY_CLK_XTAL32_CR_LPM)) ? 1u : 0u; + + CY_CLK_XTAL32_TST_REG = CY_CLK_XTAL32_TST_DEFAULT; + + if(1u == mode) + { + /* Low power mode during Sleep */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_LOW_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_LOWPOWER; + CyDelayUs(20u); + CY_CLK_XTAL32_CR_REG |= CY_CLK_XTAL32_CR_LPM; + } + else + { + /* High power mode */ + CY_CLK_XTAL32_TR_REG = CY_CLK_XTAL32_TR_HIGH_POWER; + CyDelayUs(10u); + CY_CLK_XTAL32_CFG_REG = (CY_CLK_XTAL32_CFG_REG & ((uint8)(~CY_CLK_XTAL32_CFG_LP_MASK))) | + CY_CLK_XTAL32_CFG_LP_DEFAULT; + CY_CLK_XTAL32_CR_REG &= ((uint8)(~CY_CLK_XTAL32_CR_LPM)); + } + + return(state); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Start +******************************************************************************** +* +* Summary: +* Enables the megahertz crystal. +* +* PSoC 3: +* Waits until the XERR bit is low (no error) for a millisecond or until the +* number of milliseconds specified by the wait parameter has expired. +* +* Parameters: +* wait: Valid range [0-255]. +* This is the timeout value in milliseconds. +* The appropriate value is crystal specific. +* +* Return: +* CYRET_SUCCESS - Completed successfully +* CYRET_TIMEOUT - Timeout occurred without detecting a low value on XERR. +* +* Side Effects and Restrictions: +* If wait is enabled (non-zero wait). Uses the Fast Timewheel to time the wait. +* Any other use of the Fast Timewheel (FTW) will be stopped during the period +* of this function and then restored. +* +* Uses the 100KHz ILO. If not enabled, this function will enable the 100KHz +* ILO for the period of this function. No changes to the setup of the ILO, +* Fast Timewheel, Central Timewheel or Once Per Second interrupt may be made +* by interrupt routines during the period of this function. +* +* The current operation of the ILO, Central Timewheel and Once Per Second +* interrupt are maintained during the operation of this function provided the +* reading of the Power Manager Interrupt Status Register is only done using the +* CyPmReadStatus() function. +* +*******************************************************************************/ +cystatus CyXTAL_Start(uint8 wait) +{ + cystatus status = CYRET_SUCCESS; + volatile uint8 timeout = wait; + volatile uint8 count; + uint8 iloEnableState; + uint8 pmTwCfg0Tmp; + uint8 pmTwCfg2Tmp; + + + /* Enables MHz crystal oscillator circuit */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_ENABLE; + + + if(wait > 0u) + { + /* Save 100 KHz ILO, FTW interval, enable and interrupt enable */ + iloEnableState = CY_LIB_SLOWCLK_ILO_CR0_REG; + pmTwCfg0Tmp = CY_LIB_PM_TW_CFG0_REG; + pmTwCfg2Tmp = CY_LIB_PM_TW_CFG2_REG; + + /* Set 250 us interval */ + CyPmFtwSetInterval(CY_CLK_XMHZ_FTW_INTERVAL); + status = CYRET_TIMEOUT; + + + for( ; timeout > 0u; timeout--) + { + /* Read XERR bit to clear it */ + (void) CY_CLK_XMHZ_CSR_REG; + + /* Wait for 1 millisecond - 4 x 250 us */ + for(count = 4u; count > 0u; count--) + { + while(0u == (CY_PM_FTW_INT & CyPmReadStatus(CY_PM_FTW_INT))) + { + /* Wait for FTW interrupt event */ + } + } + + + /******************************************************************* + * High output indicates an oscillator failure. + * Only can be used after a start-up interval (1 ms) is completed. + *******************************************************************/ + if(0u == (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + + /* Restore 100 KHz ILO, FTW interval, enable and interrupt enable */ + if(0u == (iloEnableState & CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ)) + { + CyILO_Stop100K(); + } + CY_LIB_PM_TW_CFG0_REG = pmTwCfg0Tmp; + CY_LIB_PM_TW_CFG2_REG = pmTwCfg2Tmp; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CyXTAL_Stop +******************************************************************************** +* +* Summary: +* Disables the megahertz crystal oscillator. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_Stop(void) +{ + /* Disable oscillator. */ + FASTCLK_XMHZ_CSR &= ((uint8)(~XMHZ_CONTROL_ENABLE)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableErrStatus +******************************************************************************** +* +* Summary: +* Enables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XFB)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableErrStatus +******************************************************************************** +* +* Summary: +* Disables the generation of the XERR status bit for the megahertz crystal. +* This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableErrStatus(void) +{ + /* If oscillator has insufficient amplitude, XERR bit will be high. */ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XFB; +} + + +/******************************************************************************* +* Function Name: CyXTAL_ReadStatus +******************************************************************************** +* +* Summary: +* Reads the XERR status bit for the megahertz crystal. This status bit is a +* sticky, clear on read. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* Status +* 0: No error +* 1: Error +* +*******************************************************************************/ +uint8 CyXTAL_ReadStatus(void) +{ + /*************************************************************************** + * High output indicates an oscillator failure. Only use this after a start-up + * interval is completed. This can be used for the status and failure recovery. + ***************************************************************************/ + return((0u != (CY_CLK_XMHZ_CSR_REG & CY_CLK_XMHZ_CSR_XERR)) ? 1u : 0u); +} + + +/******************************************************************************* +* Function Name: CyXTAL_EnableFaultRecovery +******************************************************************************** +* +* Summary: +* Enables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. The crystal must be up and +* running with the XERR bit at 0, before calling this function to prevent +* an immediate fault switchover. This function is not available for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_EnableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG |= CY_CLK_XMHZ_CSR_XPROT; +} + + +/******************************************************************************* +* Function Name: CyXTAL_DisableFaultRecovery +******************************************************************************** +* +* Summary: +* Disables the fault recovery circuit which will switch to the IMO in the case +* of a fault in the megahertz crystal circuit. This function is not available +* for PSoC5. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_DisableFaultRecovery(void) +{ + CY_CLK_XMHZ_CSR_REG &= ((uint8)(~CY_CLK_XMHZ_CSR_XPROT)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetStartup +******************************************************************************** +* +* Summary: +* Sets the startup settings for the crystal. The logic model outputs a frequency +* (setting + 4) MHz when enabled. +* +* This is artificial as the actual frequency is determined by an attached +* external crystal. +* +* Parameters: +* setting: Valid range [0-31]. +* The value is dependent on the frequency and quality of the crystal being used. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetStartup(uint8 setting) +{ + CY_CLK_XMHZ_CFG0_REG = (CY_CLK_XMHZ_CFG0_REG & ((uint8)(~CY_CLK_XMHZ_CFG0_XCFG_MASK))) | + (setting & CY_CLK_XMHZ_CFG0_XCFG_MASK); +} + + + +/******************************************************************************* +* Function Name: CyXTAL_SetFbVoltage +******************************************************************************** +* +* Summary: +* Sets the feedback reference voltage to use for the crystal circuit. +* This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-15]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetFbVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_FB_MASK))) | + (setting & CY_CLK_XMHZ_CFG1_VREF_FB_MASK)); +} + + +/******************************************************************************* +* Function Name: CyXTAL_SetWdVoltage +******************************************************************************** +* +* Summary: +* Sets the reference voltage used by the watchdog to detect a failure in the +* crystal circuit. This function is only available for PSoC3 and PSoC 5LP. +* +* Parameters: +* setting: Valid range [0-7]. +* Refer to the device TRM and datasheet for more information. +* +* Return: +* None +* +*******************************************************************************/ +void CyXTAL_SetWdVoltage(uint8 setting) +{ + CY_CLK_XMHZ_CFG1_REG = ((CY_CLK_XMHZ_CFG1_REG & ((uint8)(~CY_CLK_XMHZ_CFG1_VREF_WD_MASK))) | + (((uint8)(setting << 4u)) & CY_CLK_XMHZ_CFG1_VREF_WD_MASK)); +} + + +/******************************************************************************* +* Function Name: CyHalt +******************************************************************************** +* +* Summary: +* Halts the CPU. +* +* Parameters: +* uint8 reason: Value to be used during debugging. +* +* Return: +* None +* +*******************************************************************************/ +void CyHalt(uint8 reason) CYREENTRANT +{ + if(0u != reason) + { + /* To remove unreferenced local variable warning */ + } + + #if defined (__ARMCC_VERSION) + __breakpoint(0x0); + #elif defined(__GNUC__) || defined (__ICCARM__) + __asm(" bkpt 1"); + #elif defined(__C51__) + CYDEV_HALT_CPU; + #endif /* (__ARMCC_VERSION) */ +} + + +/******************************************************************************* +* Function Name: CySoftwareReset +******************************************************************************** +* +* Summary: +* Forces a device software reset. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySoftwareReset(void) +{ + CY_LIB_RESET_CR2_REG |= CY_LIB_RESET_CR2_RESET; +} + + +/******************************************************************************* +* Function Name: CyDelay +******************************************************************************** +* +* Summary: +* Blocks for milliseconds. +* +* Note: +* CyDelay has been implemented with the instruction cache assumed enabled. When +* the instruction cache is disabled on PSoC5, CyDelay will be two times larger. +* For example, with instruction cache disabled CyDelay(100) would result in +* about 200 ms delay instead of 100 ms. +* +* Parameters: +* milliseconds: number of milliseconds to delay. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelay(uint32 milliseconds) CYREENTRANT +{ + while (milliseconds > 32768u) + { + /*********************************************************************** + * This loop prevents overflow.At 100MHz, milliseconds * delay_freq_khz + * overflows at about 42 seconds. + ***********************************************************************/ + CyDelayCycles(cydelay_32k_ms); + milliseconds = ((uint32)(milliseconds - 32768u)); + } + + CyDelayCycles(milliseconds * cydelay_freq_khz); +} + + +#if(!CY_PSOC3) + + /* For PSoC3 devices function is defined in CyBootAsmKeil.a51 file */ + + /******************************************************************************* + * Function Name: CyDelayUs + ******************************************************************************** + * + * Summary: + * Blocks for microseconds. + * + * Note: + * CyDelay has been implemented with the instruction cache assumed enabled. + * When instruction cache is disabled on PSoC5, CyDelayUs will be two times + * larger. Ex: With instruction cache disabled CyDelayUs(100) would result + * in about 200us delay instead of 100us. + * + * Parameters: + * uint16 microseconds: number of microseconds to delay. + * + * Return: + * None + * + * Side Effects: + * CyDelayUS has been implemented with the instruction cache assumed enabled. + * When the instruction cache is disabled on PSoC 5, CyDelayUs will be two times + * larger. For example, with the instruction cache disabled CyDelayUs(100) would + * result in about 200 us delay instead of 100 us. + * + * If the bus clock frequency is a small non-integer number, the actual delay + * can be up to twice as long as the nominal value. The actual delay cannot be + * shorter than the nominal one. + *******************************************************************************/ + void CyDelayUs(uint16 microseconds) CYREENTRANT + { + CyDelayCycles((uint32)microseconds * cydelay_freq_mhz); + } + +#endif /* (!CY_PSOC3) */ + + +/******************************************************************************* +* Function Name: CyDelayFreq +******************************************************************************** +* +* Summary: +* Sets the clock frequency for CyDelay. +* +* Parameters: +* freq: The frequency of the bus clock in Hertz. +* +* Return: +* None +* +*******************************************************************************/ +void CyDelayFreq(uint32 freq) CYREENTRANT +{ + if (freq != 0u) + { + cydelay_freq_hz = freq; + } + else + { + cydelay_freq_hz = BCLK__BUS_CLK__HZ; + } + + cydelay_freq_mhz = (uint8)((cydelay_freq_hz + 999999u) / 1000000u); + cydelay_freq_khz = (cydelay_freq_hz + 999u) / 1000u; + cydelay_32k_ms = 32768u * cydelay_freq_khz; +} + + +/******************************************************************************* +* Function Name: CyWdtStart +******************************************************************************** +* +* Summary: +* Enables the watchdog timer. +* +* The timer is configured for the specified count interval, the central +* timewheel is cleared, the setting for the low power mode is configured and the +* watchdog timer is enabled. +* +* Once enabled the watchdog cannot be disabled. The watchdog counts each time +* the Central Time Wheel (CTW) reaches the period specified. The watchdog must +* be cleared using the CyWdtClear() function before three ticks of the watchdog +* timer occur. The CTW is free running, so this will occur after between 2 and +* 3 timer periods elapse. +* +* PSoC5: The watchdog timer should not be used during sleep modes. Since the +* WDT cannot be disabled after it is enabled, the WDT timeout period can be +* set to be greater than the sleep wakeup period, then feed the dog on each +* wakeup from Sleep. +* +* Parameters: +* ticks: One of the four available timer periods. Once WDT enabled, the + interval cannot be changed. +* CYWDT_2_TICKS - 4 - 6 ms +* CYWDT_16_TICKS - 32 - 48 ms +* CYWDT_128_TICKS - 256 - 384 ms +* CYWDT_1024_TICKS - 2.048 - 3.072 s +* +* lpMode: Low power mode configuration. This parameter is ignored for PSoC 5. +* The WDT always acts as if CYWDT_LPMODE_NOCHANGE is passed. +* +* CYWDT_LPMODE_NOCHANGE - No Change +* CYWDT_LPMODE_MAXINTER - Switch to longest timer mode during low power +* mode +* CYWDT_LPMODE_DISABLED - Disable WDT during low power mode +* +* Return: +* None +* +* Side Effects: +* PSoC5: The ILO 1 KHz must be enabled for proper WDT operation. Stopping the +* ILO 1 kHz could break the active WDT functionality. +* +*******************************************************************************/ +void CyWdtStart(uint8 ticks, uint8 lpMode) +{ + /* Set WDT interval */ + CY_WDT_CFG_REG = (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_INTERVAL_MASK))) | (ticks & CY_WDT_CFG_INTERVAL_MASK); + + /* Reset CTW to ensure that first watchdog period is full */ + CY_WDT_CFG_REG |= CY_WDT_CFG_CTW_RESET; + CY_WDT_CFG_REG &= ((uint8)(~CY_WDT_CFG_CTW_RESET)); + + /* Setting low power mode */ + CY_WDT_CFG_REG = (((uint8)(lpMode << CY_WDT_CFG_LPMODE_SHIFT)) & CY_WDT_CFG_LPMODE_MASK) | + (CY_WDT_CFG_REG & ((uint8)(~CY_WDT_CFG_LPMODE_MASK))); + + /* Enables watchdog reset */ + CY_WDT_CFG_REG |= CY_WDT_CFG_WDR_EN; +} + + +/******************************************************************************* +* Function Name: CyWdtClear +******************************************************************************** +* +* Summary: +* Clears (feeds) the watchdog timer. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyWdtClear(void) +{ + CY_WDT_CR_REG = CY_WDT_CR_FEED; +} + + + +/******************************************************************************* +* Function Name: CyVdLvDigitEnable +******************************************************************************** +* +* Summary: +* Enables the digital low voltage monitors to generate interrupt on Vddd +* archives specified threshold and optionally resets the device. +* +* Parameters: +* reset: The option to reset the device at a specified Vddd threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with an interval of approximately +* 250 mV. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + CY_VD_LVI_TRIP_REG = (threshold & CY_VD_LVI_TRIP_LVID_MASK) | + (CY_VD_LVI_TRIP_REG & ((uint8)(~CY_VD_LVI_TRIP_LVID_MASK))); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVID_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESD_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog low voltage monitors to generate interrupt on Vdda +* archives specified threshold and optionally resets the device. +* +* Parameters: +* reset: The option to reset the device at a specified Vdda threshold: +* 0 - Device is not reset. +* 1 - Device is reset. +* +* threshold: Sets the trip level for the voltage monitor. +* Values from 1.70 V to 5.45 V are accepted with the approximately 250 mV +* interval. +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_TRIP_REG = ((uint8)(threshold << 4u)) | (CY_VD_LVI_TRIP_REG & 0x0Fu); + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_LVIA_EN; + + /* Timeout to eliminate glitches on LVI/HVI when enabling */ + CyDelayUs(1u); + + (void)CY_VD_PERSISTENT_STATUS_REG; + + if(0u != reset) + { + CY_VD_PRES_CONTROL_REG |= CY_VD_PRESA_EN; + } + else + { + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + } + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdLvDigitDisable +******************************************************************************** +* +* Summary: +* Disables the digital low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvDigitDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVID_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESD_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdLvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor (interrupt and device reset are +* disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdLvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_LVIA_EN)); + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + while(0u != (CY_VD_PERSISTENT_STATUS_REG & 0x07u)) + { + + } +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogEnable +******************************************************************************** +* +* Summary: +* Enables the analog high voltage monitors to generate interrupt on +* Vdda archives 5.75 V threshold and optionally resets device. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogEnable(void) +{ + *CY_INT_CLEAR_PTR = 0x01u; + + CY_VD_PRES_CONTROL_REG &= ((uint8)(~CY_VD_PRESA_EN)); + + CY_VD_LVI_HVI_CONTROL_REG |= CY_VD_HVIA_EN; + + /* Timeout to eliminate glitches on the LVI/HVI when enabling */ + CyDelayUs(1u); + + (void) CY_VD_PERSISTENT_STATUS_REG; + + *CY_INT_CLR_PEND_PTR = 0x01u; + *CY_INT_ENABLE_PTR = 0x01u; +} + + +/******************************************************************************* +* Function Name: CyVdHvAnalogDisable +******************************************************************************** +* +* Summary: +* Disables the analog low voltage monitor +* (interrupt and device reset are disabled). +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyVdHvAnalogDisable(void) +{ + CY_VD_LVI_HVI_CONTROL_REG &= ((uint8)(~CY_VD_HVIA_EN)); +} + + +/******************************************************************************* +* Function Name: CyVdStickyStatus +******************************************************************************** +* +* Summary: +* Manages the Reset and Voltage Detection Status Register 0. +* This register has the interrupt status for the HVIA, LVID and LVIA. +* This hardware register clears on read. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +* Return: +* Status. Same enumerated bit values as used for the mask parameter. +* +*******************************************************************************/ +uint8 CyVdStickyStatus(uint8 mask) +{ + uint8 status; + + status = CY_VD_PERSISTENT_STATUS_REG; + CY_VD_PERSISTENT_STATUS_REG &= ((uint8)(~mask)); + + return(status); +} + + +/******************************************************************************* +* Function Name: CyVdRealTimeStatus +******************************************************************************** +* +* Summary: +* Returns the real time voltage detection status. +* +* Parameters: +* None +* +* Return: +* Status: +* Define Definition +* CY_VD_LVID Persistent status of digital LVI. +* CY_VD_LVIA Persistent status of analog LVI. +* CY_VD_HVIA Persistent status of analog HVI. +* +*******************************************************************************/ +uint8 CyVdRealTimeStatus(void) +{ + uint8 interruptState; + uint8 vdFlagsState; + + interruptState = CyEnterCriticalSection(); + vdFlagsState = CY_VD_RT_STATUS_REG; + CyExitCriticalSection(interruptState); + + return(vdFlagsState); +} + + +/******************************************************************************* +* Function Name: CyDisableInts +******************************************************************************** +* +* Summary: +* Disables the interrupt enable for each interrupt. +* +* Parameters: +* None +* +* Return: +* 32 bit mask of previously enabled interrupts. +* +*******************************************************************************/ +uint32 CyDisableInts(void) +{ + uint32 intState; + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Get the current interrupt state. */ + intState = ((uint32) CY_GET_REG8(CY_INT_CLR_EN0_PTR)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN1_PTR)) << 8u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN2_PTR)) << 16u)); + intState |= ((uint32) (((uint32) CY_GET_REG8(CY_INT_CLR_EN3_PTR)) << 24u)); + + + /* Disable all of the interrupts. */ + CY_SET_REG8(CY_INT_CLR_EN0_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN1_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN2_PTR, 0xFFu); + CY_SET_REG8(CY_INT_CLR_EN3_PTR, 0xFFu); + + #else + + /* Get the current interrupt state. */ + intState = CY_GET_REG32(CY_INT_CLEAR_PTR); + + /* Disable all of the interrupts. */ + CY_SET_REG32(CY_INT_CLEAR_PTR, 0xFFFFFFFFu); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + + return (intState); +} + + +/******************************************************************************* +* Function Name: CyEnableInts +******************************************************************************** +* +* Summary: +* Enables interrupts to a given state. +* +* Parameters: +* uint32 mask: 32 bit mask of interrupts to enable. +* +* Return: +* None +* +*******************************************************************************/ +void CyEnableInts(uint32 mask) +{ + + uint8 interruptState; + + interruptState = CyEnterCriticalSection(); + + #if(CY_PSOC3) + + /* Set interrupts as enabled. */ + CY_SET_REG8(CY_INT_SET_EN3_PTR, ((uint8) (mask >> 24u))); + CY_SET_REG8(CY_INT_SET_EN2_PTR, ((uint8) (mask >> 16u))); + CY_SET_REG8(CY_INT_SET_EN1_PTR, ((uint8) (mask >> 8u ))); + CY_SET_REG8(CY_INT_SET_EN0_PTR, ((uint8) (mask ))); + + #else + + CY_SET_REG32(CY_INT_ENABLE_PTR, mask); + + #endif /* (CY_PSOC3) */ + + CyExitCriticalSection(interruptState); + +} + +#if(CY_PSOC5) + + /******************************************************************************* + * Function Name: CyFlushCache + ******************************************************************************** + * Summary: + * Flushes the PSoC 5/5LP cache by invalidating all entries. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CyFlushCache(void) + { + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /* Fill instruction prefectch unit to insure data integrity */ + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + CY_NOP; + + /* All entries in cache are invalidated on next clock cycle. */ + CY_CACHE_CONTROL_REG |= CY_CACHE_CONTROL_FLUSH; + + /* Once this is executed it's guaranteed the cache has been flushed */ + (void) CY_CACHE_CONTROL_REG; + + /* Flush the pipeline */ + CY_SYS_ISB; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + } + + + /******************************************************************************* + * Function Name: CyIntSetSysVector + ******************************************************************************** + * Summary: + * Sets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEM_MANAGE_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * address: Pointer to an interrupt service routine. + * + * Return: + * The old ISR vector at this location. + * + *******************************************************************************/ + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + + /* Set new Interrupt service routine. */ + ramVectorTable[number & CY_INT_SYS_NUMBER_MASK] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetSysVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified system interrupt number. System + * interrupts are present only for the ARM platform. These interrupts are for + * SysTick, PendSV and others. + * + * Parameters: + * number: System interrupt number: + * CY_INT_NMI_IRQN - Non Maskable Interrupt + * CY_INT_HARD_FAULT_IRQN - Hard Fault Interrupt + * CY_INT_MEMORY_MANAGEMENT_IRQN - Memory Management Interrupt + * CY_INT_BUS_FAULT_IRQN - Bus Fault Interrupt + * CY_INT_USAGE_FAULT_IRQN - Usage Fault Interrupt + * CY_INT_SVCALL_IRQN - SV Call Interrupt + * CY_INT_DEBUG_MONITOR_IRQN - Debug Monitor Interrupt + * CY_INT_PEND_SV_IRQN - Pend SV Interrupt + * CY_INT_SYSTICK_IRQN - System Tick Interrupt + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetSysVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_SYS_NUMBER_MAX); + + return ramVectorTable[number & CY_INT_SYS_NUMBER_MASK]; + } + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]; + + /* Set new Interrupt service routine. */ + ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)] = address; + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * The address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + cyisraddress *ramVectorTable = *CY_INT_VECT_TABLE; + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return (ramVectorTable[CY_INT_IRQ_BASE + (number & CY_INT_NUMBER_MASK)]); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + CYASSERT(number <= CY_INT_NUMBER_MAX); + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = (priority & CY_INT_PRIORITY_MASK)<< 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg32 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR; + + /* Get state of interrupt. */ + return (0u != (*stateReg & (((uint32) 1u) << (0x1Fu & number)))) ? ((uint8)(1u)) : ((uint8)(0u)); + } + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Function Name: CyIntSetVector + ******************************************************************************** + * + * Summary: + * Sets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * address: Pointer to an interrupt service routine + * + * Return: + * Previous interrupt vector value. + * + *******************************************************************************/ + cyisraddress CyIntSetVector(uint8 number, cyisraddress address) + { + cyisraddress oldIsr; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Save old Interrupt service routine. */ + oldIsr = (cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK]); + + /* Set new Interrupt service routine. */ + CY_SET_REG16(&CY_INT_VECT_TABLE[number], (uint16) address); + + return (oldIsr); + } + + + /******************************************************************************* + * Function Name: CyIntGetVector + ******************************************************************************** + * + * Summary: + * Gets the interrupt vector of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * Address of the ISR in the interrupt vector table. + * + *******************************************************************************/ + cyisraddress CyIntGetVector(uint8 number) + { + CYASSERT(number <= CY_INT_NUMBER_MAX); + + return ((cyisraddress) \ + CY_GET_REG16(&CY_INT_VECT_TABLE[number & CY_INT_NUMBER_MASK])); + } + + + /******************************************************************************* + * Function Name: CyIntSetPriority + ******************************************************************************** + * + * Summary: + * Sets the Priority of the Interrupt. + * + * Parameters: + * priority: Priority of the interrupt. 0 - 7, 0 being the highest. + * number: The number of the interrupt, 0 - 31. + * + * Return: + * None + * + *******************************************************************************/ + void CyIntSetPriority(uint8 number, uint8 priority) + { + CYASSERT(priority <= CY_INT_PRIORITY_MAX); + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] = + (priority & CY_INT_PRIORITY_MASK) << 5; + } + + + /******************************************************************************* + * Function Name: CyIntGetPriority + ******************************************************************************** + * + * Summary: + * Gets the Priority of the Interrupt. + * + * Parameters: + * number: The number of the interrupt, 0 - 31. + * + * Return: + * Priority of the interrupt. 0 - 7, 0 being the highest. + * + *******************************************************************************/ + uint8 CyIntGetPriority(uint8 number) + { + uint8 priority; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + priority = CY_INT_PRIORITY_PTR[number & CY_INT_NUMBER_MASK] >> 5; + + return (priority); + } + + + /******************************************************************************* + * Function Name: CyIntGetState + ******************************************************************************** + * + * Summary: + * Gets the enable state of the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * Enable status: 1 if enabled, 0 if disabled + * + *******************************************************************************/ + uint8 CyIntGetState(uint8 number) + { + reg8 * stateReg; + + CYASSERT(number <= CY_INT_NUMBER_MAX); + + /* Get pointer to Interrupt enable register. */ + stateReg = CY_INT_ENABLE_PTR + ((number & CY_INT_NUMBER_MASK) >> 3u); + + /* Get state of interrupt. */ + return ((0u != (*stateReg & ((uint8)(1u << (0x07u & number))))) ? ((uint8)(1u)) : ((uint8)(0u))); + } + + +#endif /* (CY_PSOC5) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + /******************************************************************************* + * Function Name: CySetScPumps + ******************************************************************************** + * + * Summary: + * If 1 is passed as a parameter: + * - if any of the SC blocks are used - enable pumps for the SC blocks and + * start boost clock. + * - For each enabled SC block set a boost clock index and enable the boost + * clock. + * + * If non-1 value is passed as a parameter: + * - If all SC blocks are not used - disable pumps for the SC blocks and + * stop the boost clock. + * - For each enabled SC block clear the boost clock index and disable the boost + * clock. + * + * The global variable CyScPumpEnabled is updated to be equal to passed the + * parameter. + * + * Parameters: + * uint8 enable: Enable/disable SC pumps and the boost clock for the enabled SC block. + * 1 - Enable + * 0 - Disable + * + * Return: + * None + * + *******************************************************************************/ + void CySetScPumps(uint8 enable) + { + if(1u == enable) + { + /* The SC pumps should be enabled */ + CyScPumpEnabled = 1u; + /* Enable pumps if any of SC blocks are used */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAPS_MASK)) + { + CY_LIB_SC_MISC_REG |= CY_LIB_SC_MISC_PUMP_FORCE; + CyScBoostClk_Start(); + } + /* Set positive pump for each enabled SC block: set clock index and enable it */ + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP0_EN)) + { + CY_LIB_SC0_BST_REG = (CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC0_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP1_EN)) + { + CY_LIB_SC1_BST_REG = (CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC1_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP2_EN)) + { + CY_LIB_SC2_BST_REG = (CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC2_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + if(0u != (CY_LIB_ACT_CFG9_REG & CY_LIB_ACT_CFG9_SWCAP3_EN)) + { + CY_LIB_SC3_BST_REG = (CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK) | CyScBoostClk__INDEX; + CY_LIB_SC3_BST_REG |= CY_LIB_SC_BST_CLK_EN; + } + } + else + { + /* The SC pumps should be disabled */ + CyScPumpEnabled = 0u; + /* Disable pumps for all SC blocks and stop boost clock */ + CY_LIB_SC_MISC_REG &= ((uint8)(~CY_LIB_SC_MISC_PUMP_FORCE)); + CyScBoostClk_Stop(); + /* Disable boost clock and clear clock index for each SC block */ + CY_LIB_SC0_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC0_BST_REG = CY_LIB_SC0_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC1_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC1_BST_REG = CY_LIB_SC1_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC2_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC2_BST_REG = CY_LIB_SC2_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + CY_LIB_SC3_BST_REG &= ((uint8)(~CY_LIB_SC_BST_CLK_EN)); + CY_LIB_SC3_BST_REG = CY_LIB_SC3_BST_REG & CY_LIB_SC_BST_CLK_INDEX_MASK; + } + } + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +#if(CY_PSOC5) + /******************************************************************************* + * Function Name: CySysTickStart + ******************************************************************************** + * + * Summary: + * Configures the SysTick timer to generate interrupt every 1 ms by call to the + * CySysTickInit() function and starts it by calling CySysTickEnable() function. + * Refer to the corresponding function description for the details. + + * Parameters: + * None + * + * Return: + * None + * + * Side Effects: + * Clears SysTick count flag if it was set + * + *******************************************************************************/ + void CySysTickStart(void) + { + if (0u == CySysTickInitVar) + { + CySysTickInit(); + CySysTickInitVar = 1u; + } + + CySysTickEnable(); + } + + + /******************************************************************************* + * Function Name: CySysTickInit + ******************************************************************************** + * + * Summary: + * Initializes the callback addresses with pointers to NULL, associates the + * SysTick system vector with the function that is responsible for calling + * registered callback functions, configures SysTick timer to generate interrupt + * every 1 ms. + * + * Parameters: + * None + * + * Return: + * None + * + * Side Effects: + * Clears SysTick count flag if it was set. + * + * The 1 ms interrupt interval is configured based on the frequency determined + * by PSoC Creator at build time. If System clock frequency is changed in + * runtime, the CyDelayFreq() with the appropriate parameter should be called. + * + *******************************************************************************/ + void CySysTickInit(void) + { + uint32 i; + + for (i = 0u; i>CY_SYS_SYST_CSR_COUNTFLAG_SHIFT) & 0x01u); + } + + + /******************************************************************************* + * Function Name: CySysTickClear + ******************************************************************************** + * + * Summary: + * Clears the SysTick counter for well-defined startup. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + void CySysTickClear(void) + { + CY_SYS_SYST_CVR_REG = 0u; + } + + + /******************************************************************************* + * Function Name: CySysTickSetCallback + ******************************************************************************** + * + * Summary: + * The function set the pointers to the functions that will be called on + * SysTick interrupt. + * + * Parameters: + * number: The number of callback function address to be set. + * The valid range is from 0 to 4. + * CallbackFunction: Function address. + * + * Return: + * Returns the address of the previous callback function. + * The NULL is returned if the specified address in not set. + * + *******************************************************************************/ + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function) + { + cySysTickCallback retVal; + + retVal = CySysTickCallbacks[number]; + CySysTickCallbacks[number] = function; + return (retVal); + } + + + /******************************************************************************* + * Function Name: CySysTickGetCallback + ******************************************************************************** + * + * Summary: + * The function get the specified callback pointer. + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + cySysTickCallback CySysTickGetCallback(uint32 number) + { + return ((cySysTickCallback) CySysTickCallbacks[number]); + } + + + /******************************************************************************* + * Function Name: CySysTickServiceCallbacks + ******************************************************************************** + * + * Summary: + * System Tick timer interrupt routine + * + * Parameters: + * None + * + * Return: + * None + * + *******************************************************************************/ + static void CySysTickServiceCallbacks(void) + { + uint32 i; + + /* Verify that tick timer flag was set */ + if (1u == CySysTickGetCountFlag()) + { + for (i=0u; i < CY_SYS_SYST_NUM_OF_CALLBACKS; i++) + { + if (CySysTickCallbacks[i] != (void *) 0) + { + (void)(CySysTickCallbacks[i])(); + } + } + } + } +#endif /* (CY_PSOC5) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h new file mode 100644 index 0000000..2e2c66a --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CyLib.h @@ -0,0 +1,1361 @@ +/******************************************************************************* +* File Name: CyLib.h +* Version 4.20 +* +* Description: +* Provides the function definitions for the system, clocking, interrupts and +* watchdog timer API. +* +* Note: +* Documentation of the API's in this file is located in the System Reference +* Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYLIB_H) +#define CY_BOOT_CYLIB_H + +#include +#include +#include + +#include "cytypes.h" +#include "cyfitter.h" +#include "cydevice_trm.h" +#include "cyPm.h" + +#if(CY_PSOC3) + #include +#endif /* (CY_PSOC3) */ + + +#if(CYDEV_VARIABLE_VDDA == 1) + + #include "CyScBoostClk.h" + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Global variable with preserved reset status */ +extern uint8 CYXDATA CyResetStatus; + + +/* Variable Vdda */ +#if(CYDEV_VARIABLE_VDDA == 1) + + extern uint8 CyScPumpEnabled; + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/* Do not use these definitions directly in your application */ +extern uint32 cydelay_freq_hz; +extern uint32 cydelay_freq_khz; +extern uint8 cydelay_freq_mhz; +extern uint32 cydelay_32k_ms; + + +/*************************************** +* Function Prototypes +***************************************/ +cystatus CyPLL_OUT_Start(uint8 wait) ; +void CyPLL_OUT_Stop(void) ; +void CyPLL_OUT_SetPQ(uint8 pDiv, uint8 qDiv, uint8 current) ; +void CyPLL_OUT_SetSource(uint8 source) ; + +void CyIMO_Start(uint8 wait) ; +void CyIMO_Stop(void) ; +void CyIMO_SetFreq(uint8 freq) ; +void CyIMO_SetSource(uint8 source) ; +void CyIMO_EnableDoubler(void) ; +void CyIMO_DisableDoubler(void) ; + +void CyMasterClk_SetSource(uint8 source) ; +void CyMasterClk_SetDivider(uint8 divider) ; +void CyBusClk_SetDivider(uint16 divider) ; + +#if(CY_PSOC3) + void CyCpuClk_SetDivider(uint8 divider) ; +#endif /* (CY_PSOC3) */ + +void CyUsbClk_SetSource(uint8 source) ; + +void CyILO_Start1K(void) ; +void CyILO_Stop1K(void) ; +void CyILO_Start100K(void) ; +void CyILO_Stop100K(void) ; +void CyILO_Enable33K(void) ; +void CyILO_Disable33K(void) ; +void CyILO_SetSource(uint8 source) ; +uint8 CyILO_SetPowerMode(uint8 mode) ; + +uint8 CyXTAL_32KHZ_ReadStatus(void) ; +uint8 CyXTAL_32KHZ_SetPowerMode(uint8 mode) ; +void CyXTAL_32KHZ_Start(void) ; +void CyXTAL_32KHZ_Stop(void) ; + +cystatus CyXTAL_Start(uint8 wait) ; +void CyXTAL_Stop(void) ; +void CyXTAL_SetStartup(uint8 setting) ; + +void CyXTAL_EnableErrStatus(void) ; +void CyXTAL_DisableErrStatus(void) ; +uint8 CyXTAL_ReadStatus(void) ; +void CyXTAL_EnableFaultRecovery(void) ; +void CyXTAL_DisableFaultRecovery(void) ; + +void CyXTAL_SetFbVoltage(uint8 setting) ; +void CyXTAL_SetWdVoltage(uint8 setting) ; + +void CyWdtStart(uint8 ticks, uint8 lpMode) ; +void CyWdtClear(void) ; + +/* System Function Prototypes */ +void CyDelay(uint32 milliseconds) CYREENTRANT; +void CyDelayUs(uint16 microseconds); +void CyDelayFreq(uint32 freq) CYREENTRANT; +void CyDelayCycles(uint32 cycles); + +void CySoftwareReset(void) ; + +uint8 CyEnterCriticalSection(void); +void CyExitCriticalSection(uint8 savedIntrStatus); +void CyHalt(uint8 reason) CYREENTRANT; + + +/* Interrupt Function Prototypes */ +#if(CY_PSOC5) + cyisraddress CyIntSetSysVector(uint8 number, cyisraddress address) ; + cyisraddress CyIntGetSysVector(uint8 number) ; +#endif /* (CY_PSOC5) */ + +cyisraddress CyIntSetVector(uint8 number, cyisraddress address) ; +cyisraddress CyIntGetVector(uint8 number) ; + +void CyIntSetPriority(uint8 number, uint8 priority) ; +uint8 CyIntGetPriority(uint8 number) ; + +uint8 CyIntGetState(uint8 number) ; + +uint32 CyDisableInts(void) ; +void CyEnableInts(uint32 mask) ; + + +#if(CY_PSOC5) + void CyFlushCache(void); +#endif /* (CY_PSOC5) */ + + +/* Voltage Detection Function Prototypes */ +void CyVdLvDigitEnable(uint8 reset, uint8 threshold) ; +void CyVdLvAnalogEnable(uint8 reset, uint8 threshold) ; +void CyVdLvDigitDisable(void) ; +void CyVdLvAnalogDisable(void) ; +void CyVdHvAnalogEnable(void) ; +void CyVdHvAnalogDisable(void) ; +uint8 CyVdStickyStatus(uint8 mask) ; +uint8 CyVdRealTimeStatus(void) ; + +void CySetScPumps(uint8 enable) ; + +#if(CY_PSOC5) + /* Default interrupt handler */ + CY_ISR_PROTO(IntDefaultHandler); +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC5) + /* System tick timer APIs */ + typedef void (*cySysTickCallback)(void); + + void CySysTickStart(void); + void CySysTickInit(void); + void CySysTickEnable(void); + void CySysTickStop(void); + void CySysTickEnableInterrupt(void); + void CySysTickDisableInterrupt(void); + void CySysTickSetReload(uint32 value); + uint32 CySysTickGetReload(void); + uint32 CySysTickGetValue(void); + cySysTickCallback CySysTickSetCallback(uint32 number, cySysTickCallback function); + cySysTickCallback CySysTickGetCallback(uint32 number); + void CySysTickSetClockSource(uint32 clockSource); + uint32 CySysTickGetCountFlag(void); + void CySysTickClear(void); +#endif /* (CY_PSOC5) */ + +/*************************************** +* API Constants +***************************************/ + + +/******************************************************************************* +* PLL API Constants +*******************************************************************************/ +#define CY_CLK_PLL_ENABLE (0x01u) +#define CY_CLK_PLL_LOCK_STATUS (0x01u) + +#define CY_CLK_PLL_FTW_INTERVAL (24u) + +#define CY_CLK_PLL_MAX_Q_VALUE (16u) +#define CY_CLK_PLL_MIN_Q_VALUE (1u) +#define CY_CLK_PLL_MIN_P_VALUE (8u) +#define CY_CLK_PLL_MIN_CUR_VALUE (1u) +#define CY_CLK_PLL_MAX_CUR_VALUE (7u) + +#define CY_CLK_PLL_CURRENT_POSITION (4u) +#define CY_CLK_PLL_CURRENT_MASK (0x8Fu) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_XTAL32K_ANA_STAT (0x20u) + +#define CY_CLK_XTAL32_CR_LPM (0x02u) +#define CY_CLK_XTAL32_CR_EN (0x01u) +#if(CY_PSOC3) + #define CY_CLK_XTAL32_CR_PDBEN (0x04u) +#endif /* (CY_PSOC3) */ + +#define CY_CLK_XTAL32_TR_MASK (0x07u) +#define CY_CLK_XTAL32_TR_STARTUP (0x03u) +#define CY_CLK_XTAL32_TR_HIGH_POWER (0x06u) +#define CY_CLK_XTAL32_TR_LOW_POWER (0x01u) +#define CY_CLK_XTAL32_TR_POWERDOWN (0x00u) + +#define CY_CLK_XTAL32_TST_DEFAULT (0xF3u) + +#define CY_CLK_XTAL32_CFG_LP_DEFAULT (0x04u) +#define CY_CLK_XTAL32_CFG_LP_LOWPOWER (0x08u) +#define CY_CLK_XTAL32_CFG_LP_MASK (0x0Cu) + +#define CY_CLK_XTAL32_CFG_LP_ALLOW (0x80u) + + +/******************************************************************************* +* External MHz Crystal Oscillator API Constants +*******************************************************************************/ +#define CY_CLK_XMHZ_FTW_INTERVAL (24u) +#define CY_CLK_XMHZ_MIN_TIMEOUT (130u) + +#define CY_CLK_XMHZ_CSR_ENABLE (0x01u) +#define CY_CLK_XMHZ_CSR_XERR (0x80u) +#define CY_CLK_XMHZ_CSR_XFB (0x04u) +#define CY_CLK_XMHZ_CSR_XPROT (0x40u) + +#define CY_CLK_XMHZ_CFG0_XCFG_MASK (0x1Fu) +#define CY_CLK_XMHZ_CFG1_VREF_FB_MASK (0x0Fu) +#define CY_CLK_XMHZ_CFG1_VREF_WD_MASK (0x70u) + + +/******************************************************************************* +* Watchdog Timer API Constants +*******************************************************************************/ +#define CYWDT_2_TICKS (0x0u) /* 4 - 6 ms */ +#define CYWDT_16_TICKS (0x1u) /* 32 - 48 ms */ +#define CYWDT_128_TICKS (0x2u) /* 256 - 384 ms */ +#define CYWDT_1024_TICKS (0x3u) /* 2048 - 3072 ms */ + +#define CYWDT_LPMODE_NOCHANGE (0x00u) +#define CYWDT_LPMODE_MAXINTER (0x01u) +#define CYWDT_LPMODE_DISABLED (0x03u) + +#define CY_WDT_CFG_INTERVAL_MASK (0x03u) +#define CY_WDT_CFG_CTW_RESET (0x80u) +#define CY_WDT_CFG_LPMODE_SHIFT (5u) +#define CY_WDT_CFG_LPMODE_MASK (0x60u) +#define CY_WDT_CFG_WDR_EN (0x10u) +#define CY_WDT_CFG_CLEAR_ALL (0x00u) +#define CY_WDT_CR_FEED (0x01u) + + +/******************************************************************************* +* Voltage Detection API Constants +*******************************************************************************/ + +#define CY_VD_LVID_EN (0x01u) +#define CY_VD_LVIA_EN (0x02u) +#define CY_VD_HVIA_EN (0x04u) + +#define CY_VD_PRESD_EN (0x40u) +#define CY_VD_PRESA_EN (0x80u) + +#define CY_VD_LVID (0x01u) +#define CY_VD_LVIA (0x02u) +#define CY_VD_HVIA (0x04u) + +#define CY_VD_LVI_TRIP_LVID_MASK (0x0Fu) + + +/******************************************************************************* +* Variable VDDA API Constants +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u) + #define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u) + #define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u) + #define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u) + #define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_PUMP_FORCE (0x20u) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC_BST_CLK_EN (0x08u) + #define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution API Constants +*******************************************************************************/ +#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u) +#define CY_LIB_CLKDIST_DMASK_MASK (0x00u) +#define CY_LIB_CLKDIST_LD_LOAD (0x01u) +#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) +#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u) +#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) +#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu) +#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u) +#define CY_LIB_FASTCLK_IMO_IMO (0x20u) +#define CY_LIB_CLKDIST_CR_IMO2X (0x40u) +#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u) + +#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu) + + +/* CyILO_SetPowerMode() */ +#define CY_ILO_CONTROL_PD_MODE (0x10u) +#define CY_ILO_CONTROL_PD_POSITION (4u) + +#define CY_ILO_SOURCE_100K (0u) +#define CY_ILO_SOURCE_33K (1u) +#define CY_ILO_SOURCE_1K (2u) + +#define CY_ILO_FAST_START (0u) +#define CY_ILO_SLOW_START (1u) + +#define CY_ILO_SOURCE_BITS_CLEAR (0xF3u) +#define CY_ILO_SOURCE_1K_SET (0x08u) +#define CY_ILO_SOURCE_33K_SET (0x04u) +#define CY_ILO_SOURCE_100K_SET (0x00u) + +#define CY_MASTER_SOURCE_IMO (0u) +#define CY_MASTER_SOURCE_PLL (1u) +#define CY_MASTER_SOURCE_XTAL (2u) +#define CY_MASTER_SOURCE_DSI (3u) + +#define CY_IMO_SOURCE_IMO (0u) +#define CY_IMO_SOURCE_XTAL (1u) +#define CY_IMO_SOURCE_DSI (2u) + + +/* CyIMO_Start() */ +#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u) +#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u) +#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u) + +#define CY_LIB_IMO_3MHZ_VALUE (0x03u) +#define CY_LIB_IMO_6MHZ_VALUE (0x01u) +#define CY_LIB_IMO_12MHZ_VALUE (0x00u) +#define CY_LIB_IMO_24MHZ_VALUE (0x02u) +#define CY_LIB_IMO_48MHZ_VALUE (0x04u) +#define CY_LIB_IMO_62MHZ_VALUE (0x05u) +#define CY_LIB_IMO_74MHZ_VALUE (0x06u) + + +/* CyIMO_SetFreq() */ +#define CY_IMO_FREQ_3MHZ (0u) +#define CY_IMO_FREQ_6MHZ (1u) +#define CY_IMO_FREQ_12MHZ (2u) +#define CY_IMO_FREQ_24MHZ (3u) +#define CY_IMO_FREQ_48MHZ (4u) +#define CY_IMO_FREQ_62MHZ (5u) +#if(CY_PSOC5) + #define CY_IMO_FREQ_74MHZ (6u) +#endif /* (CY_PSOC5) */ +#define CY_IMO_FREQ_USB (8u) + +#define CY_LIB_IMO_USBCLK_ON_SET (0x40u) + + +/* CyCpuClk_SetDivider() */ +#define CY_LIB_CLKDIST_DIV_POSITION (4u) +#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu) + + +/* CyIMO_SetTrimValue() */ +#define CY_LIB_USB_CLK_EN (0x02u) + + +/* CyPLL_OUT_SetSource() - parameters */ +#define CY_PLL_SOURCE_IMO (0u) +#define CY_PLL_SOURCE_XTAL (1u) +#define CY_PLL_SOURCE_DSI (2u) + + +/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */ +#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u) +#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u) + + +/* CyUsbClk_SetSource() */ +#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u) + + +/* CyUsbClk_SetSource() - parameters */ +#define CY_LIB_USB_CLK_IMO2X (0x00u) +#define CY_LIB_USB_CLK_IMO (0x01u) +#define CY_LIB_USB_CLK_PLL (0x02u) +#define CY_LIB_USB_CLK_DSI (0x03u) + + +/* CyUSB_PowerOnCheck() */ +#define CY_ACT_USB_ENABLED (0x01u) +#define CY_ALT_ACT_USB_ENABLED (0x01u) + + +#if(CY_PSOC5) + + /*************************************************************************** + * Instruction Synchronization Barrier flushes the pipeline in the processor, + * so that all instructions following the ISB are fetched from cache or + * memory, after the instruction has been completed. + ***************************************************************************/ + + #if defined(__ARMCC_VERSION) + #define CY_SYS_ISB __isb(0x0f) + #else /* ASM for GCC & IAR */ + #define CY_SYS_ISB asm volatile ("isb \n") + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + + +/******************************************************************************* +* System Registers +*******************************************************************************/ + +/* Software Reset Control Register */ +#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2) +#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2) + +/* Timewheel Configuration Register 0 */ +#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0) +#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) + +/* Timewheel Configuration Register 2 */ +#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2) +#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) + +/* USB Configuration Register */ +#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) + +/* Internal Main Oscillator Trim Register 1 */ +#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1) +#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) + +/* USB control 1 Register */ +#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 ) +#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0) +#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0) +#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) + +/* Active Power Mode Configuration Register 5 */ +#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) + +/* Standby Power Mode Configuration Register 5 */ +#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) + +/* CyIMO_SetTrimValue() */ +#if(CY_PSOC3) + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* PLL Registers +*******************************************************************************/ + +/* PLL Configuration Register 0 */ +#define CY_CLK_PLL_CFG0_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG0) +#define CY_CLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0) + +/* PLL Configuration Register 1 */ +#define CY_CLK_PLL_CFG1_REG (*(reg8 *) CYREG_FASTCLK_PLL_CFG1) +#define CY_CLK_PLL_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG1) + +/* PLL Status Register */ +#define CY_CLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR) +#define CY_CLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR) + +/* PLL Q-Counter Configuration Register */ +#define CY_CLK_PLL_Q_REG (*(reg8 *) CYREG_FASTCLK_PLL_Q) +#define CY_CLK_PLL_Q_PTR ( (reg8 *) CYREG_FASTCLK_PLL_Q) + +/* PLL P-Counter Configuration Register */ +#define CY_CLK_PLL_P_REG (*(reg8 *) CYREG_FASTCLK_PLL_P) +#define CY_CLK_PLL_P_PTR ( (reg8 *) CYREG_FASTCLK_PLL_P) + + +/******************************************************************************* +* External MHz Crystal Oscillator Registers +*******************************************************************************/ + +/* External MHz Crystal Oscillator Status and Control Register */ +#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR) +#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR) + +/* External MHz Crystal Oscillator Configuration Register 0 */ +#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0) +#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0) + +/* External MHz Crystal Oscillator Configuration Register 1 */ +#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1) +#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1) + + +/******************************************************************************* +* External 32kHz Crystal Oscillator Registers +*******************************************************************************/ + +/* 32 kHz Watch Crystal Oscillator Trim Register */ +#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR) +#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR) + +/* External 32kHz Crystal Oscillator Test Register */ +#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST) +#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR) +#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR) + +/* External 32kHz Crystal Oscillator Configuration Register */ +#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG) +#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG) + + +/******************************************************************************* +* Watchdog Timer Registers +*******************************************************************************/ + +/* Watchdog Timer Configuration Register */ +#define CY_WDT_CFG_REG (*(reg8 *) CYREG_PM_WDT_CFG) +#define CY_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG) + +/* Watchdog Timer Control Register */ +#define CY_WDT_CR_REG (*(reg8 *) CYREG_PM_WDT_CR) +#define CY_WDT_CR_PTR ( (reg8 *) CYREG_PM_WDT_CR) + + +/******************************************************************************* +* LVI/HVI Registers +*******************************************************************************/ + +#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0) +#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0) + +#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1) +#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1) + +#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3) +#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3) + +#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0) +#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0) + +#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2) +#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2) + + +/******************************************************************************* +* Variable VDDA +*******************************************************************************/ +#if(CYDEV_VARIABLE_VDDA == 1) + + /* Active Power Mode Configuration Register 9 */ + #define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 ) + #define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 ) + + /* Switched Capacitor 0 Boost Clock Selection Register */ + #define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST ) + #define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST ) + + /* Switched Capacitor 1 Boost Clock Selection Register */ + #define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST ) + #define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST ) + + /* Switched Capacitor 2 Boost Clock Selection Register */ + #define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST ) + #define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST ) + + /* Switched Capacitor 3 Boost Clock Selection Register */ + #define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST ) + #define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST ) + + /* Switched Cap Miscellaneous Control Register */ + #define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC ) + #define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC ) + +#endif /* (CYDEV_VARIABLE_VDDA == 1) */ + + +/******************************************************************************* +* Clock Distribution Registers +*******************************************************************************/ + +/* Analog Clock Mask Register */ +#define CY_LIB_CLKDIST_AMASK_REG (* (reg8 *) CYREG_CLKDIST_AMASK ) +#define CY_LIB_CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK ) + +/* Digital Clock Mask Register */ +#define CY_LIB_CLKDIST_DMASK_REG (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CY_LIB_CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) + +/* CLK_BUS Configuration Register */ +#define CY_LIB_CLKDIST_BCFG2_REG (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CY_LIB_CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) + +/* LSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_LSB_REG (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CY_LIB_CLKDIST_WRK_LSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) + +/* MSB Shadow Divider Value Register */ +#define CY_LIB_CLKDIST_WRK_MSB_REG (*(reg8 *) CYREG_CLKDIST_WRK1) +#define CY_LIB_CLKDIST_WRK_MSB_PTR ( (reg8 *) CYREG_CLKDIST_WRK1) + +/* LOAD Register */ +#define CY_LIB_CLKDIST_LD_REG (*(reg8 *) CYREG_CLKDIST_LD) +#define CY_LIB_CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_LSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CY_LIB_CLKDIST_BCFG_LSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_LIB_CLKDIST_BCFG_MSB_REG (*(reg8 *) CYREG_CLKDIST_BCFG1) +#define CY_LIB_CLKDIST_BCFG_MSB_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1) + +/* Master clock (clk_sync_d) Divider Value Register */ +#define CY_LIB_CLKDIST_MSTR0_REG (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define CY_LIB_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) + +/* Master (clk_sync_d) Configuration Register/CPU Divider Value */ +#define CY_LIB_CLKDIST_MSTR1_REG (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define CY_LIB_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) + +/* Internal Main Oscillator Control Register */ +#define CY_LIB_FASTCLK_IMO_CR_REG (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CY_LIB_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) + +/* Configuration Register CR */ +#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR) +#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) + + +/******************************************************************************* +* Interrupt Registers +*******************************************************************************/ + +#if(CY_PSOC5) + + /* Interrupt Vector Table Offset */ + #define CY_INT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET) + + /* Interrupt Priority 0-31 */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_NVIC_PRI_0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_NVIC_PRI_0) + + /* Interrupt Enable Set 0-31 */ + #define CY_INT_ENABLE_REG (* (reg32 *) CYREG_NVIC_SETENA0) + #define CY_INT_ENABLE_PTR ( (reg32 *) CYREG_NVIC_SETENA0) + + /* Interrupt Enable Clear 0-31 */ + #define CY_INT_CLEAR_REG (* (reg32 *) CYREG_NVIC_CLRENA0) + #define CY_INT_CLEAR_PTR ( (reg32 *) CYREG_NVIC_CLRENA0) + + /* Interrupt Pending Set 0-31 */ + #define CY_INT_SET_PEND_REG (* (reg32 *) CYREG_NVIC_SETPEND0) + #define CY_INT_SET_PEND_PTR ( (reg32 *) CYREG_NVIC_SETPEND0) + + /* Interrupt Pending Clear 0-31 */ + #define CY_INT_CLR_PEND_REG (* (reg32 *) CYREG_NVIC_CLRPEND0) + #define CY_INT_CLR_PEND_PTR ( (reg32 *) CYREG_NVIC_CLRPEND0) + + /* Cache Control Register */ + #define CY_CACHE_CONTROL_REG (* (reg16 *) CYREG_CACHE_CC_CTL ) + #define CY_CACHE_CONTROL_PTR ( (reg16 *) CYREG_CACHE_CC_CTL ) + + /* System tick registers */ + #define CY_SYS_SYST_CSR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CTL) + #define CY_SYS_SYST_CSR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CTL) + + #define CY_SYS_SYST_RVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + #define CY_SYS_SYST_RVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_RELOAD) + + #define CY_SYS_SYST_CVR_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + #define CY_SYS_SYST_CVR_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CURRENT) + + #define CY_SYS_SYST_CALIB_REG (*(reg32 *) CYREG_NVIC_SYSTICK_CAL) + #define CY_SYS_SYST_CALIB_PTR ( (reg32 *) CYREG_NVIC_SYSTICK_CAL) + +#elif (CY_PSOC3) + + /* Interrupt Address Vector registers */ + #define CY_INT_VECT_TABLE ((cyisraddress CYXDATA *) CYREG_INTC_VECT_MBASE) + + /* Interrupt Controller Priority Registers */ + #define CY_INT_PRIORITY_REG (* (reg8 *) CYREG_INTC_PRIOR0) + #define CY_INT_PRIORITY_PTR ( (reg8 *) CYREG_INTC_PRIOR0) + + /* Interrupt Controller Set Enable Registers */ + #define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0) + #define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0) + + #define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1) + #define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1) + + #define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2) + #define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2) + + #define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3) + #define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3) + + /* Interrupt Controller Clear Enable Registers */ + #define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0) + #define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0) + + #define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1) + #define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1) + + #define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2) + #define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2) + + #define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3) + #define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3) + + + /* Interrupt Controller Set Pend Registers */ + #define CY_INT_SET_PEND_REG (* (reg8 *) CYREG_INTC_SET_PD0) + #define CY_INT_SET_PEND_PTR ( (reg8 *) CYREG_INTC_SET_PD0) + + /* Interrupt Controller Clear Pend Registers */ + #define CY_INT_CLR_PEND_REG (* (reg8 *) CYREG_INTC_CLR_PD0) + #define CY_INT_CLR_PEND_PTR ( (reg8 *) CYREG_INTC_CLR_PD0) + + + /* Access Interrupt Controller Registers based on interrupt number */ + #define CY_INT_SET_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_EN_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_EN0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_CLR_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_CLR_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + #define CY_INT_SET_PEND_INDX_PTR(number) ((reg8 *) (CYREG_INTC_SET_PD0 + (((number) & CY_INT_NUMBER_MASK) >> 3u))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro Name: CyAssert +******************************************************************************** +* Summary: +* The macro that evaluates the expression and if it is false (evaluates to 0) +* then the processor is halted. +* +* This macro is evaluated unless NDEBUG is defined. +* +* If NDEBUG is defined, then no code is generated for this macro. NDEBUG is +* defined by default for a Release build setting and not defined for a Debug +* build setting. +* +* Parameters: +* expr: Logical expression. Asserts if false. +* +* Return: +* None +* +*******************************************************************************/ +#if !defined(NDEBUG) + #define CYASSERT(x) { \ + if(!(x)) \ + { \ + CyHalt((uint8) 0u); \ + } \ + } +#else + #define CYASSERT(x) +#endif /* !defined(NDEBUG) */ + + +/* Reset register fields of RESET_SR0 (CyResetStatus) */ +#define CY_RESET_LVID (0x01u) +#define CY_RESET_LVIA (0x02u) +#define CY_RESET_HVIA (0x04u) +#define CY_RESET_WD (0x08u) +#define CY_RESET_SW (0x20u) +#define CY_RESET_GPIO0 (0x40u) +#define CY_RESET_GPIO1 (0x80u) + + +/* Interrupt Controller Configuration and Status Register */ +#if(CY_PSOC3) + #define INTERRUPT_CSR ((reg8 *) CYREG_INTC_CSR_EN) + #define DISABLE_IRQ_SET ((uint8)(0x01u << 1u)) /* INTC_CSR_EN */ + #define INTERRUPT_DISABLE_IRQ {*INTERRUPT_CSR |= DISABLE_IRQ_SET;} + #define INTERRUPT_ENABLE_IRQ {*INTERRUPT_CSR = (uint8)(~DISABLE_IRQ_SET);} +#endif /* (CY_PSOC3) */ + + +#if defined(__ARMCC_VERSION) + #define CyGlobalIntEnable {__enable_irq();} + #define CyGlobalIntDisable {__disable_irq();} +#elif defined(__GNUC__) || defined (__ICCARM__) + #define CyGlobalIntEnable {__asm("CPSIE i");} + #define CyGlobalIntDisable {__asm("CPSID i");} +#elif defined(__C51__) + #define CyGlobalIntEnable {\ + EA = 1u; \ + INTERRUPT_ENABLE_IRQ\ + } + + #define CyGlobalIntDisable {\ + INTERRUPT_DISABLE_IRQ; \ + CY_NOP; \ + EA = 0u;\ + } +#else + #error No compiler toolchain defined + #define CyGlobalIntEnable + #define CyGlobalIntDisable +#endif /* (__ARMCC_VERSION) */ + + +#ifdef CYREG_MLOGIC_CPU_SCR_CPU_SCR + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x01u) +#else + #define CYDEV_HALT_CPU CY_SET_REG8(CYREG_MLOGIC_CPU_SCR, 0x01u) +#endif /* (CYREG_MLOGIC_CPU_SCR_CPU_SCR) */ + + +#ifdef CYREG_MLOGIC_REV_ID_REV_ID + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID_REV_ID)) +#else + #define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID)) +#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */ + + +/******************************************************************************* +* System API constants +*******************************************************************************/ +#define CY_CACHE_CONTROL_FLUSH (0x0004u) +#define CY_LIB_RESET_CR2_RESET (0x01u) + +#if(CY_PSOC5) + /* System tick API constants */ + #define CY_SYS_SYST_CSR_ENABLE ((uint32) (0x01u)) + #define CY_SYS_SYST_CSR_ENABLE_INT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_CLK_SOURCE_SHIFT ((uint32) (0x02u)) + #define CY_SYS_SYST_CSR_COUNTFLAG_SHIFT ((uint32) (16u)) + #define CY_SYS_SYST_CSR_CLK_SRC_SYSCLK ((uint32) (1u)) + #define CY_SYS_SYST_CSR_CLK_SRC_LFCLK ((uint32) (0u)) + #define CY_SYS_SYST_RVR_CNT_MASK ((uint32) (0x00FFFFFFu)) + #define CY_SYS_SYST_NUM_OF_CALLBACKS ((uint32) (5u)) +#endif /* (CY_PSOC5) */ + + + +/******************************************************************************* +* Interrupt API constants +*******************************************************************************/ +#if(CY_PSOC5) + + #define CY_INT_IRQ_BASE (16u) + +#elif (CY_PSOC3) + + #define CY_INT_IRQ_BASE (0u) + +#endif /* (CY_PSOC5) */ + +/* Valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MAX (31u) + +/* Valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MAX (15u) + +/* Valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MAX (7u) + +/* Mask to get valid range of interrupt 0-31 */ +#define CY_INT_NUMBER_MASK (0x1Fu) + +/* Mask to get valid range of system priority 0-7 */ +#define CY_INT_PRIORITY_MASK (0x7u) + +/* Mask to get valid range of system interrupt 0-15 */ +#define CY_INT_SYS_NUMBER_MASK (0xFu) + +#if(CY_PSOC5) + + /* CyIntSetSysVector()/CyIntGetSysVector() - parameter definitions */ + #define CY_INT_NMI_IRQN ( 2u) /* Non Maskable Interrupt */ + #define CY_INT_HARD_FAULT_IRQN ( 3u) /* Hard Fault Interrupt */ + #define CY_INT_MEM_MANAGE_IRQN ( 4u) /* Memory Management Interrupt */ + #define CY_INT_BUS_FAULT_IRQN ( 5u) /* Bus Fault Interrupt */ + #define CY_INT_USAGE_FAULT_IRQN ( 6u) /* Usage Fault Interrupt */ + #define CY_INT_SVCALL_IRQN (11u) /* SV Call Interrupt */ + #define CY_INT_DEBUG_MONITOR_IRQN (12u) /* Debug Monitor Interrupt */ + #define CY_INT_PEND_SV_IRQN (14u) /* Pend SV Interrupt */ + #define CY_INT_SYSTICK_IRQN (15u) /* System Tick Interrupt */ + +#endif /* (CY_PSOC5) */ + +/******************************************************************************* +* Interrupt Macros +*******************************************************************************/ + +#if(CY_PSOC5) + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG32(CY_INT_ENABLE_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG32(CY_INT_CLEAR_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG32(CY_INT_SET_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG32(CY_INT_CLR_PEND_PTR, ((uint32)((uint32)1u << (0x1Fu & (number))))) + + +#else /* PSoC3 */ + + + /******************************************************************************* + * Macro Name: CyIntEnable + ******************************************************************************** + * + * Summary: + * Enables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntEnable(number) CY_SET_REG8(CY_INT_SET_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntDisable + ******************************************************************************** + * + * Summary: + * Disables the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntDisable(number) CY_SET_REG8(CY_INT_CLR_EN_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntSetPending + ******************************************************************************** + * + * Summary: + * Forces the specified interrupt number to be pending. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntSetPending(number) CY_SET_REG8(CY_INT_SET_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + + + /******************************************************************************* + * Macro Name: CyIntClearPending + ******************************************************************************** + * Summary: + * Clears any pending interrupt for the specified interrupt number. + * + * Parameters: + * number: Valid range [0-31]. Interrupt number. + * + * Return: + * None + * + *******************************************************************************/ + #define CyIntClearPending(number) CY_SET_REG8(CY_INT_CLR_PEND_INDX_PTR((number)), \ + ((uint8)(1u << (0x07u & (number))))) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ + +#define CYGlobalIntEnable CyGlobalIntEnable +#define CYGlobalIntDisable CyGlobalIntDisable + +#define cymemset(s,c,n) memset((s),(c),(n)) +#define cymemcpy(d,s,n) memcpy((d),(s),(n)) + +#define MFGCFG_X32_TR_PTR (CY_CLK_XTAL32_TR_PTR) +#define MFGCFG_X32_TR (CY_CLK_XTAL32_TR_REG) +#define SLOWCLK_X32_TST_PTR (CY_CLK_XTAL32_TST_PTR) +#define SLOWCLK_X32_TST (CY_CLK_XTAL32_TST_REG) +#define SLOWCLK_X32_CR_PTR (CY_CLK_XTAL32_CR_PTR) +#define SLOWCLK_X32_CR (CY_CLK_XTAL32_CR_REG) +#define SLOWCLK_X32_CFG_PTR (CY_CLK_XTAL32_CFG_PTR) +#define SLOWCLK_X32_CFG (CY_CLK_XTAL32_CFG_REG) + +#define X32_CONTROL_ANA_STAT (CY_CLK_XTAL32_CR_ANA_STAT) +#define X32_CONTROL_DIG_STAT (0x10u) +#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM) +#define X32_CONTROL_LPM_POSITION (1u) +#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN) +#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN) +#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP) +#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN) +#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER) +#define X32_TR_LPMODE (CY_CLK_XTAL32_TR_LOW_POWER) +#define X32_TST_SETALL (CY_CLK_XTAL32_TST_DEFAULT) +#define X32_CFG_LP_BITS_MASK (CY_CLK_XTAL32_CFG_LP_MASK) +#define X32_CFG_LP_DEFAULT (CY_CLK_XTAL32_CFG_LP_DEFAULT) +#define X32_CFG_LOWPOWERMODE (0x80u) +#define X32_CFG_LP_LOWPOWER (0x8u) +#define CY_X32_HIGHPOWER_MODE (0u) +#define CY_X32_LOWPOWER_MODE (1u) +#define CY_XTAL32K_DIG_STAT (0x10u) +#define CY_XTAL32K_STAT_FIELDS (0x30u) +#define CY_XTAL32K_DIG_STAT_UNSTABLE (0u) +#define CY_XTAL32K_ANA_STAT_UNSTABLE (0x0u) +#define CY_XTAL32K_STATUS (0x20u) + +#define FASTCLK_XMHZ_CSR_PTR (CY_CLK_XMHZ_CSR_PTR) +#define FASTCLK_XMHZ_CSR (CY_CLK_XMHZ_CSR_REG) +#define FASTCLK_XMHZ_CFG0_PTR (CY_CLK_XMHZ_CFG0_PTR) +#define FASTCLK_XMHZ_CFG0 (CY_CLK_XMHZ_CFG0_REG) +#define FASTCLK_XMHZ_CFG1_PTR (CY_CLK_XMHZ_CFG1_PTR) +#define FASTCLK_XMHZ_CFG1 (CY_CLK_XMHZ_CFG1_REG) +#define FASTCLK_XMHZ_GAINMASK (CY_CLK_XMHZ_CFG0_XCFG_MASK) +#define FASTCLK_XMHZ_VREFMASK (CY_CLK_XMHZ_CFG1_VREF_FB_MASK) +#define FASTCLK_XMHZ_VREF_WD_MASK (CY_CLK_XMHZ_CFG1_VREF_WD_MASK) +#define XMHZ_CONTROL_ENABLE (CY_CLK_XMHZ_CSR_ENABLE) +#define X32_CONTROL_XERR_MASK (CY_CLK_XMHZ_CSR_XERR) +#define X32_CONTROL_XERR_DIS (CY_CLK_XMHZ_CSR_XFB) +#define X32_CONTROL_XERR_POSITION (7u) +#define X32_CONTROL_FAULT_RECOVER (CY_CLK_XMHZ_CSR_XPROT) + +#define CYWDT_CFG (CY_WDT_CFG_PTR) +#define CYWDT_CR (CY_WDT_CR_PTR) + +#define CYWDT_TICKS_MASK (CY_WDT_CFG_INTERVAL_MASK) +#define CYWDT_RESET (CY_WDT_CFG_CTW_RESET) +#define CYWDT_LPMODE_SHIFT (CY_WDT_CFG_LPMODE_SHIFT) +#define CYWDT_LPMODE_MASK (CY_WDT_CFG_LPMODE_MASK) +#define CYWDT_ENABLE_BIT (CY_WDT_CFG_WDR_EN) + +#define FASTCLK_PLL_CFG0_PTR (CY_CLK_PLL_CFG0_PTR) +#define FASTCLK_PLL_CFG0 (CY_CLK_PLL_CFG0_REG) +#define FASTCLK_PLL_SR_PTR (CY_CLK_PLL_SR_PTR) +#define FASTCLK_PLL_SR (CY_CLK_PLL_SR_REG) + +#define MAX_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MAX_Q_VALUE) +#define MIN_FASTCLK_PLL_Q_VALUE (CY_CLK_PLL_MIN_Q_VALUE) +#define MIN_FASTCLK_PLL_P_VALUE (CY_CLK_PLL_MIN_P_VALUE) +#define MIN_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MIN_CUR_VALUE) +#define MAX_FASTCLK_PLL_CUR_VALUE (CY_CLK_PLL_MAX_CUR_VALUE) + +#define PLL_CONTROL_ENABLE (CY_CLK_PLL_ENABLE) +#define PLL_STATUS_LOCK (CY_CLK_PLL_LOCK_STATUS) +#define PLL_STATUS_ENABLED (CY_CLK_PLL_ENABLE) +#define PLL_CURRENT_POSITION (CY_CLK_PLL_CURRENT_POSITION) +#define PLL_VCO_GAIN_2 (2u) + +#define FASTCLK_PLL_Q_PTR (CY_CLK_PLL_Q_PTR) +#define FASTCLK_PLL_Q (CY_CLK_PLL_Q_REG) +#define FASTCLK_PLL_P_PTR (CY_CLK_PLL_P_PTR) +#define FASTCLK_PLL_P (CY_CLK_PLL_P_REG) +#define FASTCLK_PLL_CFG1_PTR (CY_CLK_PLL_CFG1_REG) +#define FASTCLK_PLL_CFG1 (CY_CLK_PLL_CFG1_REG) + +#define CY_VD_PRESISTENT_STATUS_REG (CY_VD_PERSISTENT_STATUS_REG) +#define CY_VD_PRESISTENT_STATUS_PTR (CY_VD_PERSISTENT_STATUS_PTR) + + +#if(CY_PSOC5) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + #define CACHE_CC_CTL (CY_CACHE_CONTROL_PTR) + +#elif (CY_PSOC3) + + #define CYINT_IRQ_BASE (CY_INT_IRQ_BASE) + + #define CYINT_VECT_TABLE (CY_INT_VECT_TABLE) + #define CYINT_PRIORITY (CY_INT_PRIORITY_PTR) + #define CYINT_ENABLE (CY_INT_ENABLE_PTR) + #define CYINT_CLEAR (CY_INT_CLEAR_PTR) + #define CYINT_SET_PEND (CY_INT_SET_PEND_PTR) + #define CYINT_CLR_PEND (CY_INT_CLR_PEND_PTR) + +#endif /* (CY_PSOC5) */ + + + +#define BUS_AMASK_CLEAR (0xF0u) +#define BUS_DMASK_CLEAR (0x00u) +#define CLKDIST_LD_LOAD_SET (0x01u) +#define CLKDIST_WRK0_MASK_SET (0x80u) /* Enable shadow loads */ +#define MASTERCLK_DIVIDER_VALUE (7u) +#define CLKDIST_BCFG2_SSS_SET (0x40u) /* Sync source is same frequency */ +#define MASTER_CLK_SRC_CLEAR (0xFCu) +#define IMO_DOUBLER_ENABLE (0x10u) +#define CLOCK_IMO_IMO (0x20u) +#define CLOCK_IMO2X_XTAL (0x40u) +#define CLOCK_IMO_RANGE_CLEAR (0xF8u) +#define CLOCK_CONTROL_DIST_MASK (0xFCu) + + +#define CLKDIST_AMASK (*(reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_AMASK_PTR ( (reg8 *) CYREG_CLKDIST_AMASK) +#define CLKDIST_DMASK_PTR ( (reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_DMASK (*(reg8 *) CYREG_CLKDIST_DMASK) +#define CLKDIST_BCFG2_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_BCFG2 (*(reg8 *) CYREG_CLKDIST_BCFG2) +#define CLKDIST_WRK0_PTR ( (reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_WRK0 (*(reg8 *) CYREG_CLKDIST_WRK0) +#define CLKDIST_LD_PTR ( (reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_LD (*(reg8 *) CYREG_CLKDIST_LD) +#define CLKDIST_BCFG0_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_BCFG0 (*(reg8 *) CYREG_CLKDIST_BCFG0) +#define CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0) +#define CLKDIST_MSTR0 (*(reg8 *) CYREG_CLKDIST_MSTR0) +#define FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR) +#define FASTCLK_IMO_CR (*(reg8 *) CYREG_FASTCLK_IMO_CR) +#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR) +#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR) + + +#define IMO_PM_ENABLE (0x10u) +#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0) +#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0) +#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0) +#define ILO_CONTROL_PD_MODE (0x10u) +#define ILO_CONTROL_PD_POSITION (4u) +#define ILO_CONTROL_1KHZ_ON (0x02u) +#define ILO_CONTROL_100KHZ_ON (0x04u) +#define ILO_CONTROL_33KHZ_ON (0x20u) +#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0) +#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2) +#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2) +#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2) +#define FASTCLK_IMO_USBCLK_ON_SET (0x40u) +#define CLOCK_IMO_3MHZ_VALUE (0x03u) +#define CLOCK_IMO_6MHZ_VALUE (0x01u) +#define CLOCK_IMO_12MHZ_VALUE (0x00u) +#define CLOCK_IMO_24MHZ_VALUE (0x02u) +#define CLOCK_IMO_48MHZ_VALUE (0x04u) +#define CLOCK_IMO_62MHZ_VALUE (0x05u) +#define CLOCK_IMO_74MHZ_VALUE (0x06u) +#define CLKDIST_DIV_POSITION (4u) +#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu) +#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu) +#define CLOCK_USB_ENABLE (0x02u) +#define CLOCK_IMO_OUT_X2 (0x10u) +#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2)) +#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI)) +#define USB_CLKDIST_CONFIG_MASK (0x03u) +#define USB_CLK_IMO2X (0x00u) +#define USB_CLK_IMO (0x01u) +#define USB_CLK_PLL (0x02u) +#define USB_CLK_DSI (0x03u) +#define USB_CLK_DIV2_ON (0x04u) +#define USB_CLK_STOP_FLAG (0x00u) +#define USB_CLK_START_FLAG (0x01u) +#define FTW_CLEAR_ALL_BITS (0x00u) +#define FTW_CLEAR_FTW_BITS (0xFCu) +#define FTW_ENABLE (0x01u) +#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0) +#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0) +#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2) +#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2) +#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1) +#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1) +#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV) +#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1) +#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1) +#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR) +#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 ) +#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 ) +#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG) +#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG) +#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 ) +#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 ) +#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 ) +#if(CY_PSOC3) + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) + #else + #define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ) + #define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ) + #define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ) + #define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ) + #define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ) + #define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ) + #define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB) + #define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u)) +#endif /* (CY_PSOC3) */ + + +#endif /* (CY_BOOT_CYLIB_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c new file mode 100644 index 0000000..949b675 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.c @@ -0,0 +1,736 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.20 +* +* Description: +* Provides an API for the System Performance Component. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "CySpc.h" + +#define CY_SPC_KEY_ONE (0xB6u) +#define CY_SPC_KEY_TWO(x) ((uint8) (((uint16) 0xD3u) + ((uint16) (x)))) + +/* Command Codes */ +#define CY_SPC_CMD_LD_BYTE (0x00u) +#define CY_SPC_CMD_LD_MULTI_BYTE (0x01u) +#define CY_SPC_CMD_LD_ROW (0x02u) +#define CY_SPC_CMD_RD_BYTE (0x03u) +#define CY_SPC_CMD_RD_MULTI_BYTE (0x04u) +#define CY_SPC_CMD_WR_ROW (0x05u) +#define CY_SPC_CMD_WR_USER_NVL (0x06u) +#define CY_SPC_CMD_PRG_ROW (0x07u) +#define CY_SPC_CMD_ER_SECTOR (0x08u) +#define CY_SPC_CMD_ER_ALL (0x09u) +#define CY_SPC_CMD_RD_HIDDEN (0x0Au) +#define CY_SPC_CMD_PRG_PROTECT (0x0Bu) +#define CY_SPC_CMD_CHECKSUM (0x0Cu) +#define CY_SPC_CMD_DWNLD_ALGORITHM (0x0Du) +#define CY_SPC_CMD_GET_TEMP (0x0Eu) +#define CY_SPC_CMD_GET_ADC (0x0Fu) +#define CY_SPC_CMD_RD_NVL_VOLATILE (0x10u) +#define CY_SPC_CMD_SETUP_TS (0x11u) +#define CY_SPC_CMD_DISABLE_TS (0x12u) +#define CY_SPC_CMD_ER_ROW (0x13u) + +/* Enable bit in Active and Alternate Active mode templates */ +#define PM_SPC_PM_EN (0x08u) + +/* Gate calls to the SPC. */ +uint8 SpcLockState = CY_SPC_UNLOCKED; + + +#if(CY_PSOC5) + + /*************************************************************************** + * The wait-state pipeline must be enabled prior to accessing the SPC + * register interface regardless of CPU frequency. The CySpcLock() saves + * current wait-state pipeline state and enables it. The CySpcUnlock() + * function, which must be called after SPC transaction, restores original + * state. + ***************************************************************************/ + static uint32 spcWaitPipeBypass = 0u; + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Function Name: CySpcStart +******************************************************************************** +* Summary: +* Starts the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStart(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG |= PM_SPC_PM_EN; + CY_SPC_PM_STBY_REG |= PM_SPC_PM_EN; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcStop +******************************************************************************** +* Summary: +* Stops the SPC. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcStop(void) +{ + /* Save current global interrupt enable and disable it */ + uint8 interruptState = CyEnterCriticalSection(); + + CY_SPC_PM_ACT_REG &= ((uint8)(~PM_SPC_PM_EN)); + CY_SPC_PM_STBY_REG &= ((uint8)(~PM_SPC_PM_EN)); + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcReadData +******************************************************************************** +* Summary: +* Reads data from the SPC. +* +* Parameters: +* uint8 buffer: +* Address to store data read. +* +* uint8 size: +* Number of bytes to read from the SPC. +* +* Return: +* uint8: +* The number of bytes read from the SPC. +* +*******************************************************************************/ +uint8 CySpcReadData(uint8 buffer[], uint8 size) +{ + uint8 i; + + for(i = 0u; i < size; i++) + { + while(!CY_SPC_DATA_READY) + { + CyDelayUs(1u); + } + buffer[i] = CY_SPC_CPU_DATA_REG; + } + + return(i); +} + + +/******************************************************************************* +* Function Name: CySpcLoadMultiByte +******************************************************************************** +* Summary: +* Loads 1 to 32 bytes of data into the row latch of a Flash/EEPROM array. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* Flash/eeprom addrress +* +* uint8* buffer: +* Data to load to the row latch +* +* uint16 number: +* Number bytes to load. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* CYRET_BAD_PARAM +* +*******************************************************************************/ +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ + +{ + cystatus status = CYRET_STARTED; + uint8 i; + + /*************************************************************************** + * Check if number is correct for array. Number must be less than + * 32 for Flash or less than 16 for EEPROM. + ***************************************************************************/ + if(((array < CY_SPC_LAST_FLASH_ARRAYID) && (size < 32u)) || + ((array > CY_SPC_LAST_FLASH_ARRAYID) && (size < 16u))) + { + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_MULTI_BYTE); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_MULTI_BYTE; + + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = 1u & HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = ((uint8)(size - 1u)); + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + } + else + { + status = CYRET_BAD_PARAM; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRow +******************************************************************************** +* Summary: +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The buffer pointer should point to the data that should be written to the +* flash row directly (no data in ECC/flash will be preserved). It is Flash API +* responsibility to prepare data: the preserved data are copied from flash into +* array with the modified data. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8* buffer: +* Data to be loaded to the row latch +* +* uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size) +{ + cystatus status = CYRET_STARTED; + uint16 i; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLoadRowFull +******************************************************************************** +* Summary: +* Loads a row of data into the row latch of a Flash/EEPROM array. +* +* The only data that are going to be changed should be passed. The function +* will handle unmodified data preservation based on DWR settings and input +* parameters. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 row: +* Flash row number to be loaded. +* +* uint8* buffer: +* Data to be loaded to the row latch +* +* uint8 size: +* The number of data bytes that the SPC expects to be written. Depends on the +* type of the array and, if the array is Flash, whether ECC is being enabled +* or not. There are following values: flash row latch size with ECC enabled, +* flash row latch size with ECC disabled and EEPROM row latch size. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ + +{ + cystatus status = CYRET_STARTED; + uint16 i; + + #if (CYDEV_ECC_ENABLE == 0) + uint32 offset; + #endif /* (CYDEV_ECC_ENABLE == 0) */ + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_LD_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_LD_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" and "Store Configuration + * Data in ECC" DWR options are disabled, ECC section is available + * for user data. + *******************************************************************/ + #if ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) + + /******************************************************************* + * If size parameter equals size of the ECC row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the ECC section. + * In this case flash data must be preserved. The flash data copied + * from flash data section to the SPC data register. + *******************************************************************/ + if ((size == CYDEV_ECC_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_FLS_BASE + + ((uint32) array * CYDEV_FLS_SECTOR_SIZE) + + ((uint32) row * CYDEV_FLS_ROW_SIZE ); + + for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #endif /* ((CYDEV_ECC_ENABLE == 0u) && (CYDEV_CONFIGURATION_ECC == 0u)) */ + + + for(i = 0u; i < size; i++) + { + CY_SPC_CPU_DATA_REG = buffer[i]; + } + + + /******************************************************************* + * If "Enable Error Correcting Code (ECC)" DWR option is disabled, + * ECC section can be used for storing device configuration data + * ("Store Configuration Data in ECC" DWR option is enabled) or for + * storing user data in the ECC section ("Store Configuration Data in + * ECC" DWR option is enabled). In both cases, the data in the ECC + * section must be preserved if flash data is written. + *******************************************************************/ + #if (CYDEV_ECC_ENABLE == 0) + + + /******************************************************************* + * If size parameter equals size of the flash row and selected array + * identification corresponds to the flash array (but not to EEPROM + * array) then data are going to be written to the flash data + * section. In this case, ECC section data must be preserved. + * The ECC section data copied from ECC section to the SPC data + * register. + *******************************************************************/ + if ((size == CYDEV_FLS_ROW_SIZE) && (array <= CY_SPC_LAST_FLASH_ARRAYID)) + { + offset = CYDEV_ECC_BASE + + ((uint32) array * CYDEV_ECC_SECTOR_SIZE) + + ((uint32) row * CYDEV_ECC_ROW_SIZE ); + + for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++) + { + CY_SPC_CPU_DATA_REG = CY_GET_XTND_REG8((void CYFAR *)(offset + i)); + } + } + + #else + + if(0u != row) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CYDEV_ECC_ENABLE == 0) */ + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcWriteRow +******************************************************************************** +* Summary: +* Erases then programs a row in Flash/EEPROM with data in row latch. +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint16 address: +* flash/eeprom addrress +* +* uint8 tempPolarity: +* temperature polarity. +* 1: the Temp Magnitude is interpreted as a positive value +* 0: the Temp Magnitude is interpreted as a negative value +* +* uint8 tempMagnitude: +* temperature magnitude. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ + +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_WR_ROW); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_WR_ROW; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = HI8(address); + CY_SPC_CPU_DATA_REG = LO8(address); + CY_SPC_CPU_DATA_REG = tempPolarity; + CY_SPC_CPU_DATA_REG = tempMagnitude; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcEraseSector +******************************************************************************** +* Summary: +* Erases all data in the addressed sector (block of 64 rows). +* +* Parameters: +* uint8 array: +* Id of the array. +* +* uint8 sectorNumber: +* Zero based sector number within Flash/EEPROM array +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_ER_SECTOR); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_ER_SECTOR; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = array; + CY_SPC_CPU_DATA_REG = sectorNumber; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcGetTemp +******************************************************************************** +* Summary: +* Returns the internal die temperature +* +* Parameters: +* uint8 numSamples: +* Number of samples. Valid values are 1-5, resulting in 2 - 32 samples +* respectively. +* +* uint16 timerPeriod: +* Number of ADC ACLK cycles. A valid 14 bit value is accepted, higher 2 bits +* of 16 bit values are ignored. +* +* uint8 clkDivSelect: +* ADC ACLK clock divide value. Valid values are 2 - 225. +* +* Return: +* CYRET_STARTED +* CYRET_CANCELED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetTemp(uint8 numSamples) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_GET_TEMP); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_GET_TEMP; + + /* Make sure the command was accepted */ + if(CY_SPC_BUSY) + { + CY_SPC_CPU_DATA_REG = numSamples; + } + else + { + status = CYRET_CANCELED; + } + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcLock +******************************************************************************** +* Summary: +* Locks the SPC so it can not be used by someone else: +* - Saves wait-pipeline enable state and enable pipeline (PSoC5) +* +* Parameters: +* Note +* +* Return: +* CYRET_SUCCESS - if the resource was free. +* CYRET_LOCKED - if the SPC is in use. +* +*******************************************************************************/ +cystatus CySpcLock(void) +{ + cystatus status = CYRET_LOCKED; + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + if(CY_SPC_UNLOCKED == SpcLockState) + { + SpcLockState = CY_SPC_LOCKED; + status = CYRET_SUCCESS; + + #if(CY_PSOC5) + + if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS)) + { + /* Enable pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG &= ((uint32)(~CY_SPC_CPU_WAITPIPE_BYPASS)); + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS; + } + + #endif /* (CY_PSOC5) */ + } + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(status); +} + + +/******************************************************************************* +* Function Name: CySpcUnlock +******************************************************************************** +* Summary: +* Unlocks the SPC so it can be used by someone else: +* - Restores wait-pipeline enable state (PSoC5) +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CySpcUnlock(void) +{ + uint8 interruptState; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Release the SPC object */ + SpcLockState = CY_SPC_UNLOCKED; + + #if(CY_PSOC5) + + if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass) + { + /* Force to bypass pipeline registers */ + CY_SPC_CPU_WAITPIPE_REG |= CY_SPC_CPU_WAITPIPE_BYPASS; + + /* At least 2 NOP instructions are recommended */ + CY_NOP; + CY_NOP; + CY_NOP; + + spcWaitPipeBypass = 0u; + } + + #endif /* (CY_PSOC5) */ + + /* Exit critical section */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CySpcGetAlgorithm +******************************************************************************** +* Summary: +* Downloads SPC algorithm from SPC SROM into SRAM. +* +* Parameters: +* None +* +* Return: +* CYRET_STARTED +* CYRET_LOCKED +* +*******************************************************************************/ +cystatus CySpcGetAlgorithm(void) +{ + cystatus status = CYRET_STARTED; + + /* Make sure the SPC is ready to accept command */ + if(CY_SPC_IDLE) + { + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_ONE; + CY_SPC_CPU_DATA_REG = CY_SPC_KEY_TWO(CY_SPC_CMD_DWNLD_ALGORITHM); + CY_SPC_CPU_DATA_REG = CY_SPC_CMD_DWNLD_ALGORITHM; + } + else + { + status = CYRET_LOCKED; + } + + return(status); +} + +/* [] END OF FILE */ + diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h new file mode 100644 index 0000000..2282713 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/CySpc.h @@ -0,0 +1,168 @@ +/******************************************************************************* +* File Name: CySpc.c +* Version 4.20 +* +* Description: +* Provides definitions for the System Performance Component API. +* The SPC functions are not meant to be called directly by the user +* application. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYSPC_H) +#define CY_BOOT_CYSPC_H + +#include "cytypes.h" +#include "CyLib.h" +#include "cydevice_trm.h" + + +/*************************************** +* Global Variables +***************************************/ +extern uint8 SpcLockState; + + +/*************************************** +* Function Prototypes +***************************************/ +void CySpcStart(void); +void CySpcStop(void); +uint8 CySpcReadData(uint8 buffer[], uint8 size); +cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\ +; +cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size); +cystatus CySpcLoadRowFull(uint8 array, uint16 row, const uint8 buffer[], uint16 size)\ +; +cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\ +; +cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber); +cystatus CySpcGetTemp(uint8 numSamples); +cystatus CySpcGetAlgorithm(void); +cystatus CySpcLock(void); +void CySpcUnlock(void); + + +/*************************************** +* API Constants +***************************************/ + +#define CY_SPC_LOCKED (0x01u) +#define CY_SPC_UNLOCKED (0x00u) + +/******************************************************************************* +* The Array ID indicates the unique ID of the SONOS array being accessed: +* - 0x00-0x3E : Flash Arrays +* - 0x3F : Selects all Flash arrays simultaneously +* - 0x40-0x7F : Embedded EEPROM Arrays +*******************************************************************************/ +#define CY_SPC_FIRST_FLASH_ARRAYID (0x00u) +#define CY_SPC_LAST_FLASH_ARRAYID (0x3Fu) +#define CY_SPC_FIRST_EE_ARRAYID (0x40u) +#define CY_SPC_LAST_EE_ARRAYID (0x7Fu) + + +#define CY_SPC_STATUS_DATA_READY_MASK (0x01u) +#define CY_SPC_STATUS_IDLE_MASK (0x02u) +#define CY_SPC_STATUS_CODE_MASK (0xFCu) +#define CY_SPC_STATUS_CODE_SHIFT (0x02u) + +/* Status codes for SPC. */ +#define CY_SPC_STATUS_SUCCESS (0x00u) /* Operation Successful */ +#define CY_SPC_STATUS_INVALID_ARRAY_ID (0x01u) /* Invalid Array ID for given command */ +#define CY_SPC_STATUS_INVALID_2BYTEKEY (0x02u) /* Invalid 2-byte key */ +#define CY_SPC_STATUS_ARRAY_ASLEEP (0x03u) /* Addressed Array is Asleep */ +#define CY_SPC_STATUS_EXTERN_ACCESS (0x04u) /* External Access Failure (SPC is not in external access mode) */ +#define CY_SPC_STATUS_INVALID_NUMBER (0x05u) /* Invalid 'N' Value for given command */ +#define CY_SPC_STATUS_TEST_MODE (0x06u) /* Test Mode Failure (SPC is not in test mode) */ +#define CY_SPC_STATUS_ALG_CSUM (0x07u) /* Smart Write Algorithm Checksum Failure */ +#define CY_SPC_STATUS_PARAM_CSUM (0x08u) /* Smart Write Parameter Checksum Failure */ +#define CY_SPC_STATUS_PROTECTION (0x09u) /* Protection Check Failure */ +#define CY_SPC_STATUS_ADDRESS_PARAM (0x0Au) /* Invalid Address parameter for the given command */ +#define CY_SPC_STATUS_COMMAND_CODE (0x0Bu) /* Invalid Command Code */ +#define CY_SPC_STATUS_ROW_ID (0x0Cu) /* Invalid Row ID parameter for given command */ +#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */ +#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */ + +#if(CY_PSOC5) + + /* Wait-state pipeline */ + #define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Registers +***************************************/ + +/* SPC CPU Data Register */ +#define CY_SPC_CPU_DATA_REG (* (reg8 *) CYREG_SPC_CPU_DATA ) +#define CY_SPC_CPU_DATA_PTR ( (reg8 *) CYREG_SPC_CPU_DATA ) + +/* SPC Status Register */ +#define CY_SPC_STATUS_REG (* (reg8 *) CYREG_SPC_SR ) +#define CY_SPC_STATUS_PTR ( (reg8 *) CYREG_SPC_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_SPC_PM_ACT_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_SPC_PM_ACT_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Standby Power Mode Configuration Register 0 */ +#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 ) +#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 ) + +#if(CY_PSOC5) + + /* Wait State Pipeline */ + #define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE ) + #define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE ) + +#endif /* (CY_PSOC5) */ + + +/*************************************** +* Macros +***************************************/ +#define CY_SPC_IDLE (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_BUSY (0u == (CY_SPC_STATUS_REG & CY_SPC_STATUS_IDLE_MASK)) +#define CY_SPC_DATA_READY (0u != (CY_SPC_STATUS_REG & CY_SPC_STATUS_DATA_READY_MASK)) + +/* SPC must be in idle state in order to obtain correct status */ +#define CY_SPC_READ_STATUS (CY_SPC_IDLE ? \ + ((uint8)(CY_SPC_STATUS_REG >> CY_SPC_STATUS_CODE_SHIFT)) : \ + ((uint8) CY_SPC_STATUS_BUSY)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define FIRST_FLASH_ARRAYID (CY_SPC_FIRST_FLASH_ARRAYID) +#define LAST_FLASH_ARRAYID (CY_SPC_LAST_FLASH_ARRAYID) +#define FIRST_EE_ARRAYID (CY_SPC_FIRST_EE_ARRAYID) +#define LAST_EE_ARRAYID (CY_SPC_LAST_EE_ARRAYID) +#define SIZEOF_ECC_ROW (CYDEV_ECC_ROW_SIZE) +#define SIZEOF_FLASH_ROW (CYDEV_FLS_ROW_SIZE) +#define SIZEOF_EEPROM_ROW (CYDEV_EEPROM_ROW_SIZE) + + +#endif /* (CY_BOOT_CYSPC_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c new file mode 100644 index 0000000..76594e2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.c @@ -0,0 +1,147 @@ +/******************************************************************************* +* File Name: LED.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "LED.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + LED__PORT == 15 && ((LED__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: LED_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void LED_Write(uint8 value) +{ + uint8 staticBits = (LED_DR & (uint8)(~LED_MASK)); + LED_DR = staticBits | ((uint8)(value << LED_SHIFT) & LED_MASK); +} + + +/******************************************************************************* +* Function Name: LED_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* LED_DM_STRONG Strong Drive +* LED_DM_OD_HI Open Drain, Drives High +* LED_DM_OD_LO Open Drain, Drives Low +* LED_DM_RES_UP Resistive Pull Up +* LED_DM_RES_DWN Resistive Pull Down +* LED_DM_RES_UPDWN Resistive Pull Up/Down +* LED_DM_DIG_HIZ High Impedance Digital +* LED_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void LED_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(LED_0, mode); + CyPins_SetPinDriveMode(LED_1, mode); +} + + +/******************************************************************************* +* Function Name: LED_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro LED_ReadPS calls this function. +* +*******************************************************************************/ +uint8 LED_Read(void) +{ + return (LED_PS & LED_MASK) >> LED_SHIFT; +} + + +/******************************************************************************* +* Function Name: LED_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 LED_ReadDataReg(void) +{ + return (LED_DR & LED_MASK) >> LED_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(LED_INTSTAT) + + /******************************************************************************* + * Function Name: LED_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 LED_ClearInterrupt(void) + { + return (LED_INTSTAT & LED_MASK) >> LED_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h new file mode 100644 index 0000000..d29df9e --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_H) /* Pins LED_H */ +#define CY_PINS_LED_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "LED_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + LED__PORT == 15 && ((LED__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void LED_Write(uint8 value) ; +void LED_SetDriveMode(uint8 mode) ; +uint8 LED_ReadDataReg(void) ; +uint8 LED_Read(void) ; +uint8 LED_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define LED_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define LED_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define LED_DM_RES_UP PIN_DM_RES_UP +#define LED_DM_RES_DWN PIN_DM_RES_DWN +#define LED_DM_OD_LO PIN_DM_OD_LO +#define LED_DM_OD_HI PIN_DM_OD_HI +#define LED_DM_STRONG PIN_DM_STRONG +#define LED_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define LED_MASK LED__MASK +#define LED_SHIFT LED__SHIFT +#define LED_WIDTH 2u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define LED_PS (* (reg8 *) LED__PS) +/* Data Register */ +#define LED_DR (* (reg8 *) LED__DR) +/* Port Number */ +#define LED_PRT_NUM (* (reg8 *) LED__PRT) +/* Connect to Analog Globals */ +#define LED_AG (* (reg8 *) LED__AG) +/* Analog MUX bux enable */ +#define LED_AMUX (* (reg8 *) LED__AMUX) +/* Bidirectional Enable */ +#define LED_BIE (* (reg8 *) LED__BIE) +/* Bit-mask for Aliased Register Access */ +#define LED_BIT_MASK (* (reg8 *) LED__BIT_MASK) +/* Bypass Enable */ +#define LED_BYP (* (reg8 *) LED__BYP) +/* Port wide control signals */ +#define LED_CTL (* (reg8 *) LED__CTL) +/* Drive Modes */ +#define LED_DM0 (* (reg8 *) LED__DM0) +#define LED_DM1 (* (reg8 *) LED__DM1) +#define LED_DM2 (* (reg8 *) LED__DM2) +/* Input Buffer Disable Override */ +#define LED_INP_DIS (* (reg8 *) LED__INP_DIS) +/* LCD Common or Segment Drive */ +#define LED_LCD_COM_SEG (* (reg8 *) LED__LCD_COM_SEG) +/* Enable Segment LCD */ +#define LED_LCD_EN (* (reg8 *) LED__LCD_EN) +/* Slew Rate Control */ +#define LED_SLW (* (reg8 *) LED__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define LED_PRTDSI__CAPS_SEL (* (reg8 *) LED__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define LED_PRTDSI__DBL_SYNC_IN (* (reg8 *) LED__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define LED_PRTDSI__OE_SEL0 (* (reg8 *) LED__PRTDSI__OE_SEL0) +#define LED_PRTDSI__OE_SEL1 (* (reg8 *) LED__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define LED_PRTDSI__OUT_SEL0 (* (reg8 *) LED__PRTDSI__OUT_SEL0) +#define LED_PRTDSI__OUT_SEL1 (* (reg8 *) LED__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define LED_PRTDSI__SYNC_OUT (* (reg8 *) LED__PRTDSI__SYNC_OUT) + + +#if defined(LED__INTSTAT) /* Interrupt Registers */ + + #define LED_INTSTAT (* (reg8 *) LED__INTSTAT) + #define LED_SNAP (* (reg8 *) LED__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_LED_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h new file mode 100644 index 0000000..6ba9bb4 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/LED_aliases.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* File Name: LED.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_LED_ALIASES_H) /* Pins LED_ALIASES_H */ +#define CY_PINS_LED_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define LED_0 (LED__0__PC) +#define LED_1 (LED__1__PC) + +#endif /* End Pins LED_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h new file mode 100644 index 0000000..6fcc5f6 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_Out_DBx.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_DBx_ALIASES_H) /* Pins SCSI_Out_DBx_ALIASES_H */ +#define CY_PINS_SCSI_Out_DBx_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_DBx_0 (SCSI_Out_DBx__0__PC) +#define SCSI_Out_DBx_1 (SCSI_Out_DBx__1__PC) +#define SCSI_Out_DBx_2 (SCSI_Out_DBx__2__PC) +#define SCSI_Out_DBx_3 (SCSI_Out_DBx__3__PC) +#define SCSI_Out_DBx_4 (SCSI_Out_DBx__4__PC) +#define SCSI_Out_DBx_5 (SCSI_Out_DBx__5__PC) +#define SCSI_Out_DBx_6 (SCSI_Out_DBx__6__PC) +#define SCSI_Out_DBx_7 (SCSI_Out_DBx__7__PC) + +#define SCSI_Out_DBx_DB0 (SCSI_Out_DBx__DB0__PC) +#define SCSI_Out_DBx_DB1 (SCSI_Out_DBx__DB1__PC) +#define SCSI_Out_DBx_DB2 (SCSI_Out_DBx__DB2__PC) +#define SCSI_Out_DBx_DB3 (SCSI_Out_DBx__DB3__PC) +#define SCSI_Out_DBx_DB4 (SCSI_Out_DBx__DB4__PC) +#define SCSI_Out_DBx_DB5 (SCSI_Out_DBx__DB5__PC) +#define SCSI_Out_DBx_DB6 (SCSI_Out_DBx__DB6__PC) +#define SCSI_Out_DBx_DB7 (SCSI_Out_DBx__DB7__PC) + +#endif /* End Pins SCSI_Out_DBx_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h new file mode 100644 index 0000000..a06c1fa --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SCSI_Out_aliases.h @@ -0,0 +1,48 @@ +/******************************************************************************* +* File Name: SCSI_Out.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SCSI_Out_ALIASES_H) /* Pins SCSI_Out_ALIASES_H */ +#define CY_PINS_SCSI_Out_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SCSI_Out_0 (SCSI_Out__0__PC) +#define SCSI_Out_1 (SCSI_Out__1__PC) +#define SCSI_Out_2 (SCSI_Out__2__PC) +#define SCSI_Out_3 (SCSI_Out__3__PC) +#define SCSI_Out_4 (SCSI_Out__4__PC) +#define SCSI_Out_5 (SCSI_Out__5__PC) +#define SCSI_Out_6 (SCSI_Out__6__PC) +#define SCSI_Out_7 (SCSI_Out__7__PC) + +#define SCSI_Out_DBP_raw (SCSI_Out__DBP_raw__PC) +#define SCSI_Out_BSY (SCSI_Out__BSY__PC) +#define SCSI_Out_RST (SCSI_Out__RST__PC) +#define SCSI_Out_MSG (SCSI_Out__MSG__PC) +#define SCSI_Out_SEL (SCSI_Out__SEL__PC) +#define SCSI_Out_CD (SCSI_Out__CD__PC) +#define SCSI_Out_REQ (SCSI_Out__REQ__PC) +#define SCSI_Out_IO_raw (SCSI_Out__IO_raw__PC) + +#endif /* End Pins SCSI_Out_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c new file mode 100644 index 0000000..fb427cc --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.c @@ -0,0 +1,149 @@ +/******************************************************************************* +* File Name: SD_PULLUP.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SD_PULLUP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SD_PULLUP_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_Write(uint8 value) +{ + uint8 staticBits = (SD_PULLUP_DR & (uint8)(~SD_PULLUP_MASK)); + SD_PULLUP_DR = staticBits | ((uint8)(value << SD_PULLUP_SHIFT) & SD_PULLUP_MASK); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* SD_PULLUP_DM_STRONG Strong Drive +* SD_PULLUP_DM_OD_HI Open Drain, Drives High +* SD_PULLUP_DM_OD_LO Open Drain, Drives Low +* SD_PULLUP_DM_RES_UP Resistive Pull Up +* SD_PULLUP_DM_RES_DWN Resistive Pull Down +* SD_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down +* SD_PULLUP_DM_DIG_HIZ High Impedance Digital +* SD_PULLUP_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void SD_PULLUP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SD_PULLUP_0, mode); + CyPins_SetPinDriveMode(SD_PULLUP_1, mode); + CyPins_SetPinDriveMode(SD_PULLUP_2, mode); + CyPins_SetPinDriveMode(SD_PULLUP_3, mode); +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SD_PULLUP_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SD_PULLUP_Read(void) +{ + return (SD_PULLUP_PS & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/******************************************************************************* +* Function Name: SD_PULLUP_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SD_PULLUP_ReadDataReg(void) +{ + return (SD_PULLUP_DR & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SD_PULLUP_INTSTAT) + + /******************************************************************************* + * Function Name: SD_PULLUP_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SD_PULLUP_ClearInterrupt(void) + { + return (SD_PULLUP_INTSTAT & SD_PULLUP_MASK) >> SD_PULLUP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h new file mode 100644 index 0000000..4090a3b --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_H) /* Pins SD_PULLUP_H */ +#define CY_PINS_SD_PULLUP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SD_PULLUP_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SD_PULLUP__PORT == 15 && ((SD_PULLUP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SD_PULLUP_Write(uint8 value) ; +void SD_PULLUP_SetDriveMode(uint8 mode) ; +uint8 SD_PULLUP_ReadDataReg(void) ; +uint8 SD_PULLUP_Read(void) ; +uint8 SD_PULLUP_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SD_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SD_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SD_PULLUP_DM_RES_UP PIN_DM_RES_UP +#define SD_PULLUP_DM_RES_DWN PIN_DM_RES_DWN +#define SD_PULLUP_DM_OD_LO PIN_DM_OD_LO +#define SD_PULLUP_DM_OD_HI PIN_DM_OD_HI +#define SD_PULLUP_DM_STRONG PIN_DM_STRONG +#define SD_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SD_PULLUP_MASK SD_PULLUP__MASK +#define SD_PULLUP_SHIFT SD_PULLUP__SHIFT +#define SD_PULLUP_WIDTH 4u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SD_PULLUP_PS (* (reg8 *) SD_PULLUP__PS) +/* Data Register */ +#define SD_PULLUP_DR (* (reg8 *) SD_PULLUP__DR) +/* Port Number */ +#define SD_PULLUP_PRT_NUM (* (reg8 *) SD_PULLUP__PRT) +/* Connect to Analog Globals */ +#define SD_PULLUP_AG (* (reg8 *) SD_PULLUP__AG) +/* Analog MUX bux enable */ +#define SD_PULLUP_AMUX (* (reg8 *) SD_PULLUP__AMUX) +/* Bidirectional Enable */ +#define SD_PULLUP_BIE (* (reg8 *) SD_PULLUP__BIE) +/* Bit-mask for Aliased Register Access */ +#define SD_PULLUP_BIT_MASK (* (reg8 *) SD_PULLUP__BIT_MASK) +/* Bypass Enable */ +#define SD_PULLUP_BYP (* (reg8 *) SD_PULLUP__BYP) +/* Port wide control signals */ +#define SD_PULLUP_CTL (* (reg8 *) SD_PULLUP__CTL) +/* Drive Modes */ +#define SD_PULLUP_DM0 (* (reg8 *) SD_PULLUP__DM0) +#define SD_PULLUP_DM1 (* (reg8 *) SD_PULLUP__DM1) +#define SD_PULLUP_DM2 (* (reg8 *) SD_PULLUP__DM2) +/* Input Buffer Disable Override */ +#define SD_PULLUP_INP_DIS (* (reg8 *) SD_PULLUP__INP_DIS) +/* LCD Common or Segment Drive */ +#define SD_PULLUP_LCD_COM_SEG (* (reg8 *) SD_PULLUP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SD_PULLUP_LCD_EN (* (reg8 *) SD_PULLUP__LCD_EN) +/* Slew Rate Control */ +#define SD_PULLUP_SLW (* (reg8 *) SD_PULLUP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SD_PULLUP_PRTDSI__CAPS_SEL (* (reg8 *) SD_PULLUP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SD_PULLUP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SD_PULLUP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SD_PULLUP_PRTDSI__OE_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL0) +#define SD_PULLUP_PRTDSI__OE_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SD_PULLUP_PRTDSI__OUT_SEL0 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL0) +#define SD_PULLUP_PRTDSI__OUT_SEL1 (* (reg8 *) SD_PULLUP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SD_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SD_PULLUP__PRTDSI__SYNC_OUT) + + +#if defined(SD_PULLUP__INTSTAT) /* Interrupt Registers */ + + #define SD_PULLUP_INTSTAT (* (reg8 *) SD_PULLUP__INTSTAT) + #define SD_PULLUP_SNAP (* (reg8 *) SD_PULLUP__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SD_PULLUP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h new file mode 100644 index 0000000..32f544b --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SD_PULLUP_aliases.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* File Name: SD_PULLUP.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SD_PULLUP_ALIASES_H) /* Pins SD_PULLUP_ALIASES_H */ +#define CY_PINS_SD_PULLUP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SD_PULLUP_0 (SD_PULLUP__0__PC) +#define SD_PULLUP_1 (SD_PULLUP__1__PC) +#define SD_PULLUP_2 (SD_PULLUP__2__PC) +#define SD_PULLUP_3 (SD_PULLUP__3__PC) + +#endif /* End Pins SD_PULLUP_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c new file mode 100644 index 0000000..d6b0e46 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.c @@ -0,0 +1,149 @@ +/******************************************************************************* +* File Name: SPI_PULLUP.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_PULLUP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SPI_PULLUP__PORT == 15 && ((SPI_PULLUP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SPI_PULLUP_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SPI_PULLUP_Write(uint8 value) +{ + uint8 staticBits = (SPI_PULLUP_DR & (uint8)(~SPI_PULLUP_MASK)); + SPI_PULLUP_DR = staticBits | ((uint8)(value << SPI_PULLUP_SHIFT) & SPI_PULLUP_MASK); +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* SPI_PULLUP_DM_STRONG Strong Drive +* SPI_PULLUP_DM_OD_HI Open Drain, Drives High +* SPI_PULLUP_DM_OD_LO Open Drain, Drives Low +* SPI_PULLUP_DM_RES_UP Resistive Pull Up +* SPI_PULLUP_DM_RES_DWN Resistive Pull Down +* SPI_PULLUP_DM_RES_UPDWN Resistive Pull Up/Down +* SPI_PULLUP_DM_DIG_HIZ High Impedance Digital +* SPI_PULLUP_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void SPI_PULLUP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SPI_PULLUP_0, mode); + CyPins_SetPinDriveMode(SPI_PULLUP_1, mode); + CyPins_SetPinDriveMode(SPI_PULLUP_2, mode); + CyPins_SetPinDriveMode(SPI_PULLUP_3, mode); +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SPI_PULLUP_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SPI_PULLUP_Read(void) +{ + return (SPI_PULLUP_PS & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SPI_PULLUP_ReadDataReg(void) +{ + return (SPI_PULLUP_DR & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SPI_PULLUP_INTSTAT) + + /******************************************************************************* + * Function Name: SPI_PULLUP_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SPI_PULLUP_ClearInterrupt(void) + { + return (SPI_PULLUP_INTSTAT & SPI_PULLUP_MASK) >> SPI_PULLUP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h new file mode 100644 index 0000000..6f2c043 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SPI_PULLUP.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_PULLUP_H) /* Pins SPI_PULLUP_H */ +#define CY_PINS_SPI_PULLUP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SPI_PULLUP_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SPI_PULLUP__PORT == 15 && ((SPI_PULLUP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SPI_PULLUP_Write(uint8 value) ; +void SPI_PULLUP_SetDriveMode(uint8 mode) ; +uint8 SPI_PULLUP_ReadDataReg(void) ; +uint8 SPI_PULLUP_Read(void) ; +uint8 SPI_PULLUP_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SPI_PULLUP_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SPI_PULLUP_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SPI_PULLUP_DM_RES_UP PIN_DM_RES_UP +#define SPI_PULLUP_DM_RES_DWN PIN_DM_RES_DWN +#define SPI_PULLUP_DM_OD_LO PIN_DM_OD_LO +#define SPI_PULLUP_DM_OD_HI PIN_DM_OD_HI +#define SPI_PULLUP_DM_STRONG PIN_DM_STRONG +#define SPI_PULLUP_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SPI_PULLUP_MASK SPI_PULLUP__MASK +#define SPI_PULLUP_SHIFT SPI_PULLUP__SHIFT +#define SPI_PULLUP_WIDTH 4u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SPI_PULLUP_PS (* (reg8 *) SPI_PULLUP__PS) +/* Data Register */ +#define SPI_PULLUP_DR (* (reg8 *) SPI_PULLUP__DR) +/* Port Number */ +#define SPI_PULLUP_PRT_NUM (* (reg8 *) SPI_PULLUP__PRT) +/* Connect to Analog Globals */ +#define SPI_PULLUP_AG (* (reg8 *) SPI_PULLUP__AG) +/* Analog MUX bux enable */ +#define SPI_PULLUP_AMUX (* (reg8 *) SPI_PULLUP__AMUX) +/* Bidirectional Enable */ +#define SPI_PULLUP_BIE (* (reg8 *) SPI_PULLUP__BIE) +/* Bit-mask for Aliased Register Access */ +#define SPI_PULLUP_BIT_MASK (* (reg8 *) SPI_PULLUP__BIT_MASK) +/* Bypass Enable */ +#define SPI_PULLUP_BYP (* (reg8 *) SPI_PULLUP__BYP) +/* Port wide control signals */ +#define SPI_PULLUP_CTL (* (reg8 *) SPI_PULLUP__CTL) +/* Drive Modes */ +#define SPI_PULLUP_DM0 (* (reg8 *) SPI_PULLUP__DM0) +#define SPI_PULLUP_DM1 (* (reg8 *) SPI_PULLUP__DM1) +#define SPI_PULLUP_DM2 (* (reg8 *) SPI_PULLUP__DM2) +/* Input Buffer Disable Override */ +#define SPI_PULLUP_INP_DIS (* (reg8 *) SPI_PULLUP__INP_DIS) +/* LCD Common or Segment Drive */ +#define SPI_PULLUP_LCD_COM_SEG (* (reg8 *) SPI_PULLUP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SPI_PULLUP_LCD_EN (* (reg8 *) SPI_PULLUP__LCD_EN) +/* Slew Rate Control */ +#define SPI_PULLUP_SLW (* (reg8 *) SPI_PULLUP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SPI_PULLUP_PRTDSI__CAPS_SEL (* (reg8 *) SPI_PULLUP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SPI_PULLUP_PRTDSI__DBL_SYNC_IN (* (reg8 *) SPI_PULLUP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SPI_PULLUP_PRTDSI__OE_SEL0 (* (reg8 *) SPI_PULLUP__PRTDSI__OE_SEL0) +#define SPI_PULLUP_PRTDSI__OE_SEL1 (* (reg8 *) SPI_PULLUP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SPI_PULLUP_PRTDSI__OUT_SEL0 (* (reg8 *) SPI_PULLUP__PRTDSI__OUT_SEL0) +#define SPI_PULLUP_PRTDSI__OUT_SEL1 (* (reg8 *) SPI_PULLUP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SPI_PULLUP_PRTDSI__SYNC_OUT (* (reg8 *) SPI_PULLUP__PRTDSI__SYNC_OUT) + + +#if defined(SPI_PULLUP__INTSTAT) /* Interrupt Registers */ + + #define SPI_PULLUP_INTSTAT (* (reg8 *) SPI_PULLUP__INTSTAT) + #define SPI_PULLUP_SNAP (* (reg8 *) SPI_PULLUP__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SPI_PULLUP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c new file mode 100644 index 0000000..55aa560 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.c @@ -0,0 +1,147 @@ +/******************************************************************************* +* File Name: SPI_PULLUP_1.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "SPI_PULLUP_1.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + SPI_PULLUP_1__PORT == 15 && ((SPI_PULLUP_1__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: SPI_PULLUP_1_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void SPI_PULLUP_1_Write(uint8 value) +{ + uint8 staticBits = (SPI_PULLUP_1_DR & (uint8)(~SPI_PULLUP_1_MASK)); + SPI_PULLUP_1_DR = staticBits | ((uint8)(value << SPI_PULLUP_1_SHIFT) & SPI_PULLUP_1_MASK); +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_1_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* SPI_PULLUP_1_DM_STRONG Strong Drive +* SPI_PULLUP_1_DM_OD_HI Open Drain, Drives High +* SPI_PULLUP_1_DM_OD_LO Open Drain, Drives Low +* SPI_PULLUP_1_DM_RES_UP Resistive Pull Up +* SPI_PULLUP_1_DM_RES_DWN Resistive Pull Down +* SPI_PULLUP_1_DM_RES_UPDWN Resistive Pull Up/Down +* SPI_PULLUP_1_DM_DIG_HIZ High Impedance Digital +* SPI_PULLUP_1_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void SPI_PULLUP_1_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(SPI_PULLUP_1_0, mode); + CyPins_SetPinDriveMode(SPI_PULLUP_1_1, mode); +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_1_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro SPI_PULLUP_1_ReadPS calls this function. +* +*******************************************************************************/ +uint8 SPI_PULLUP_1_Read(void) +{ + return (SPI_PULLUP_1_PS & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; +} + + +/******************************************************************************* +* Function Name: SPI_PULLUP_1_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 SPI_PULLUP_1_ReadDataReg(void) +{ + return (SPI_PULLUP_1_DR & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(SPI_PULLUP_1_INTSTAT) + + /******************************************************************************* + * Function Name: SPI_PULLUP_1_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 SPI_PULLUP_1_ClearInterrupt(void) + { + return (SPI_PULLUP_1_INTSTAT & SPI_PULLUP_1_MASK) >> SPI_PULLUP_1_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h new file mode 100644 index 0000000..7b83fd4 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: SPI_PULLUP_1.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_PULLUP_1_H) /* Pins SPI_PULLUP_1_H */ +#define CY_PINS_SPI_PULLUP_1_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "SPI_PULLUP_1_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + SPI_PULLUP_1__PORT == 15 && ((SPI_PULLUP_1__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void SPI_PULLUP_1_Write(uint8 value) ; +void SPI_PULLUP_1_SetDriveMode(uint8 mode) ; +uint8 SPI_PULLUP_1_ReadDataReg(void) ; +uint8 SPI_PULLUP_1_Read(void) ; +uint8 SPI_PULLUP_1_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define SPI_PULLUP_1_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define SPI_PULLUP_1_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define SPI_PULLUP_1_DM_RES_UP PIN_DM_RES_UP +#define SPI_PULLUP_1_DM_RES_DWN PIN_DM_RES_DWN +#define SPI_PULLUP_1_DM_OD_LO PIN_DM_OD_LO +#define SPI_PULLUP_1_DM_OD_HI PIN_DM_OD_HI +#define SPI_PULLUP_1_DM_STRONG PIN_DM_STRONG +#define SPI_PULLUP_1_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define SPI_PULLUP_1_MASK SPI_PULLUP_1__MASK +#define SPI_PULLUP_1_SHIFT SPI_PULLUP_1__SHIFT +#define SPI_PULLUP_1_WIDTH 2u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define SPI_PULLUP_1_PS (* (reg8 *) SPI_PULLUP_1__PS) +/* Data Register */ +#define SPI_PULLUP_1_DR (* (reg8 *) SPI_PULLUP_1__DR) +/* Port Number */ +#define SPI_PULLUP_1_PRT_NUM (* (reg8 *) SPI_PULLUP_1__PRT) +/* Connect to Analog Globals */ +#define SPI_PULLUP_1_AG (* (reg8 *) SPI_PULLUP_1__AG) +/* Analog MUX bux enable */ +#define SPI_PULLUP_1_AMUX (* (reg8 *) SPI_PULLUP_1__AMUX) +/* Bidirectional Enable */ +#define SPI_PULLUP_1_BIE (* (reg8 *) SPI_PULLUP_1__BIE) +/* Bit-mask for Aliased Register Access */ +#define SPI_PULLUP_1_BIT_MASK (* (reg8 *) SPI_PULLUP_1__BIT_MASK) +/* Bypass Enable */ +#define SPI_PULLUP_1_BYP (* (reg8 *) SPI_PULLUP_1__BYP) +/* Port wide control signals */ +#define SPI_PULLUP_1_CTL (* (reg8 *) SPI_PULLUP_1__CTL) +/* Drive Modes */ +#define SPI_PULLUP_1_DM0 (* (reg8 *) SPI_PULLUP_1__DM0) +#define SPI_PULLUP_1_DM1 (* (reg8 *) SPI_PULLUP_1__DM1) +#define SPI_PULLUP_1_DM2 (* (reg8 *) SPI_PULLUP_1__DM2) +/* Input Buffer Disable Override */ +#define SPI_PULLUP_1_INP_DIS (* (reg8 *) SPI_PULLUP_1__INP_DIS) +/* LCD Common or Segment Drive */ +#define SPI_PULLUP_1_LCD_COM_SEG (* (reg8 *) SPI_PULLUP_1__LCD_COM_SEG) +/* Enable Segment LCD */ +#define SPI_PULLUP_1_LCD_EN (* (reg8 *) SPI_PULLUP_1__LCD_EN) +/* Slew Rate Control */ +#define SPI_PULLUP_1_SLW (* (reg8 *) SPI_PULLUP_1__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define SPI_PULLUP_1_PRTDSI__CAPS_SEL (* (reg8 *) SPI_PULLUP_1__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define SPI_PULLUP_1_PRTDSI__DBL_SYNC_IN (* (reg8 *) SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define SPI_PULLUP_1_PRTDSI__OE_SEL0 (* (reg8 *) SPI_PULLUP_1__PRTDSI__OE_SEL0) +#define SPI_PULLUP_1_PRTDSI__OE_SEL1 (* (reg8 *) SPI_PULLUP_1__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define SPI_PULLUP_1_PRTDSI__OUT_SEL0 (* (reg8 *) SPI_PULLUP_1__PRTDSI__OUT_SEL0) +#define SPI_PULLUP_1_PRTDSI__OUT_SEL1 (* (reg8 *) SPI_PULLUP_1__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define SPI_PULLUP_1_PRTDSI__SYNC_OUT (* (reg8 *) SPI_PULLUP_1__PRTDSI__SYNC_OUT) + + +#if defined(SPI_PULLUP_1__INTSTAT) /* Interrupt Registers */ + + #define SPI_PULLUP_1_INTSTAT (* (reg8 *) SPI_PULLUP_1__INTSTAT) + #define SPI_PULLUP_1_SNAP (* (reg8 *) SPI_PULLUP_1__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_SPI_PULLUP_1_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h new file mode 100644 index 0000000..7cf3fa9 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_1_aliases.h @@ -0,0 +1,33 @@ +/******************************************************************************* +* File Name: SPI_PULLUP_1.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_PULLUP_1_ALIASES_H) /* Pins SPI_PULLUP_1_ALIASES_H */ +#define CY_PINS_SPI_PULLUP_1_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SPI_PULLUP_1_0 (SPI_PULLUP_1__0__PC) +#define SPI_PULLUP_1_1 (SPI_PULLUP_1__1__PC) + +#endif /* End Pins SPI_PULLUP_1_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h new file mode 100644 index 0000000..3d26b85 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/SPI_PULLUP_aliases.h @@ -0,0 +1,35 @@ +/******************************************************************************* +* File Name: SPI_PULLUP.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_SPI_PULLUP_ALIASES_H) /* Pins SPI_PULLUP_ALIASES_H */ +#define CY_PINS_SPI_PULLUP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define SPI_PULLUP_0 (SPI_PULLUP__0__PC) +#define SPI_PULLUP_1 (SPI_PULLUP__1__PC) +#define SPI_PULLUP_2 (SPI_PULLUP__2__PC) +#define SPI_PULLUP_3 (SPI_PULLUP__3__PC) + +#endif /* End Pins SPI_PULLUP_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.c new file mode 100644 index 0000000..7f78738 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: TERM_EN.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "TERM_EN.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + TERM_EN__PORT == 15 && ((TERM_EN__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: TERM_EN_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_Write +*******************************************************************************/ +void TERM_EN_Write(uint8 value) +{ + uint8 staticBits = (TERM_EN_DR & (uint8)(~TERM_EN_MASK)); + TERM_EN_DR = staticBits | ((uint8)(value << TERM_EN_SHIFT) & TERM_EN_MASK); +} + + +/******************************************************************************* +* Function Name: TERM_EN_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_SetDriveMode +*******************************************************************************/ +void TERM_EN_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(TERM_EN_0, mode); +} + + +/******************************************************************************* +* Function Name: TERM_EN_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_Read +*******************************************************************************/ +uint8 TERM_EN_Read(void) +{ + return (TERM_EN_PS & TERM_EN_MASK) >> TERM_EN_SHIFT; +} + + +/******************************************************************************* +* Function Name: TERM_EN_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred TERM_EN_Read() API because the +* TERM_EN_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet TERM_EN_SUT.c usage_TERM_EN_ReadDataReg +*******************************************************************************/ +uint8 TERM_EN_ReadDataReg(void) +{ + return (TERM_EN_DR & TERM_EN_MASK) >> TERM_EN_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(TERM_EN_INTSTAT) + + /******************************************************************************* + * Function Name: TERM_EN_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use TERM_EN_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - TERM_EN_0_INTR (First pin in the list) + * - TERM_EN_1_INTR (Second pin in the list) + * - ... + * - TERM_EN_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet TERM_EN_SUT.c usage_TERM_EN_SetInterruptMode + *******************************************************************************/ + void TERM_EN_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & TERM_EN_0_INTR) != 0u) + { + TERM_EN_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: TERM_EN_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet TERM_EN_SUT.c usage_TERM_EN_ClearInterrupt + *******************************************************************************/ + uint8 TERM_EN_ClearInterrupt(void) + { + return (TERM_EN_INTSTAT & TERM_EN_MASK) >> TERM_EN_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.h new file mode 100644 index 0000000..bf5d366 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: TERM_EN.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_TERM_EN_H) /* Pins TERM_EN_H */ +#define CY_PINS_TERM_EN_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "TERM_EN_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + TERM_EN__PORT == 15 && ((TERM_EN__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void TERM_EN_Write(uint8 value); +void TERM_EN_SetDriveMode(uint8 mode); +uint8 TERM_EN_ReadDataReg(void); +uint8 TERM_EN_Read(void); +void TERM_EN_SetInterruptMode(uint16 position, uint16 mode); +uint8 TERM_EN_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the TERM_EN_SetDriveMode() function. + * @{ + */ + #define TERM_EN_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define TERM_EN_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define TERM_EN_DM_RES_UP PIN_DM_RES_UP + #define TERM_EN_DM_RES_DWN PIN_DM_RES_DWN + #define TERM_EN_DM_OD_LO PIN_DM_OD_LO + #define TERM_EN_DM_OD_HI PIN_DM_OD_HI + #define TERM_EN_DM_STRONG PIN_DM_STRONG + #define TERM_EN_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define TERM_EN_MASK TERM_EN__MASK +#define TERM_EN_SHIFT TERM_EN__SHIFT +#define TERM_EN_WIDTH 1u + +/* Interrupt constants */ +#if defined(TERM_EN__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in TERM_EN_SetInterruptMode() function. + * @{ + */ + #define TERM_EN_INTR_NONE (uint16)(0x0000u) + #define TERM_EN_INTR_RISING (uint16)(0x0001u) + #define TERM_EN_INTR_FALLING (uint16)(0x0002u) + #define TERM_EN_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define TERM_EN_INTR_MASK (0x01u) +#endif /* (TERM_EN__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define TERM_EN_PS (* (reg8 *) TERM_EN__PS) +/* Data Register */ +#define TERM_EN_DR (* (reg8 *) TERM_EN__DR) +/* Port Number */ +#define TERM_EN_PRT_NUM (* (reg8 *) TERM_EN__PRT) +/* Connect to Analog Globals */ +#define TERM_EN_AG (* (reg8 *) TERM_EN__AG) +/* Analog MUX bux enable */ +#define TERM_EN_AMUX (* (reg8 *) TERM_EN__AMUX) +/* Bidirectional Enable */ +#define TERM_EN_BIE (* (reg8 *) TERM_EN__BIE) +/* Bit-mask for Aliased Register Access */ +#define TERM_EN_BIT_MASK (* (reg8 *) TERM_EN__BIT_MASK) +/* Bypass Enable */ +#define TERM_EN_BYP (* (reg8 *) TERM_EN__BYP) +/* Port wide control signals */ +#define TERM_EN_CTL (* (reg8 *) TERM_EN__CTL) +/* Drive Modes */ +#define TERM_EN_DM0 (* (reg8 *) TERM_EN__DM0) +#define TERM_EN_DM1 (* (reg8 *) TERM_EN__DM1) +#define TERM_EN_DM2 (* (reg8 *) TERM_EN__DM2) +/* Input Buffer Disable Override */ +#define TERM_EN_INP_DIS (* (reg8 *) TERM_EN__INP_DIS) +/* LCD Common or Segment Drive */ +#define TERM_EN_LCD_COM_SEG (* (reg8 *) TERM_EN__LCD_COM_SEG) +/* Enable Segment LCD */ +#define TERM_EN_LCD_EN (* (reg8 *) TERM_EN__LCD_EN) +/* Slew Rate Control */ +#define TERM_EN_SLW (* (reg8 *) TERM_EN__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define TERM_EN_PRTDSI__CAPS_SEL (* (reg8 *) TERM_EN__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define TERM_EN_PRTDSI__DBL_SYNC_IN (* (reg8 *) TERM_EN__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define TERM_EN_PRTDSI__OE_SEL0 (* (reg8 *) TERM_EN__PRTDSI__OE_SEL0) +#define TERM_EN_PRTDSI__OE_SEL1 (* (reg8 *) TERM_EN__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define TERM_EN_PRTDSI__OUT_SEL0 (* (reg8 *) TERM_EN__PRTDSI__OUT_SEL0) +#define TERM_EN_PRTDSI__OUT_SEL1 (* (reg8 *) TERM_EN__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define TERM_EN_PRTDSI__SYNC_OUT (* (reg8 *) TERM_EN__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(TERM_EN__SIO_CFG) + #define TERM_EN_SIO_HYST_EN (* (reg8 *) TERM_EN__SIO_HYST_EN) + #define TERM_EN_SIO_REG_HIFREQ (* (reg8 *) TERM_EN__SIO_REG_HIFREQ) + #define TERM_EN_SIO_CFG (* (reg8 *) TERM_EN__SIO_CFG) + #define TERM_EN_SIO_DIFF (* (reg8 *) TERM_EN__SIO_DIFF) +#endif /* (TERM_EN__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(TERM_EN__INTSTAT) + #define TERM_EN_INTSTAT (* (reg8 *) TERM_EN__INTSTAT) + #define TERM_EN_SNAP (* (reg8 *) TERM_EN__SNAP) + + #define TERM_EN_0_INTTYPE_REG (* (reg8 *) TERM_EN__0__INTTYPE) +#endif /* (TERM_EN__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_TERM_EN_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h new file mode 100644 index 0000000..95659ca --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/TERM_EN_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: TERM_EN.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_TERM_EN_ALIASES_H) /* Pins TERM_EN_ALIASES_H */ +#define CY_PINS_TERM_EN_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define TERM_EN_0 (TERM_EN__0__PC) +#define TERM_EN_0_INTR ((uint16)((uint16)0x0001u << TERM_EN__0__SHIFT)) + +#define TERM_EN_INTR_ALL ((uint16)(TERM_EN_0_INTR)) + +#endif /* End Pins TERM_EN_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c new file mode 100644 index 0000000..ef789c5 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.c @@ -0,0 +1,1473 @@ +/******************************************************************************* +* File Name: USBFS.c +* Version 2.80 +* +* Description: +* API for USBFS Component. +* +* Note: +* Many of the functions use endpoint number. RAM arrays are sized with 9 +* elements so they are indexed directly by epNumber. The SIE and ARB +* registers are indexed by variations of epNumber - 1. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "USBFS.h" +#include "USBFS_pvt.h" +#include "USBFS_hid.h" +#if(USBFS_DMA1_REMOVE == 0u) + #include "USBFS_ep1_dma.h" +#endif /* USBFS_DMA1_REMOVE */ +#if(USBFS_DMA2_REMOVE == 0u) + #include "USBFS_ep2_dma.h" +#endif /* USBFS_DMA2_REMOVE */ +#if(USBFS_DMA3_REMOVE == 0u) + #include "USBFS_ep3_dma.h" +#endif /* USBFS_DMA3_REMOVE */ +#if(USBFS_DMA4_REMOVE == 0u) + #include "USBFS_ep4_dma.h" +#endif /* USBFS_DMA4_REMOVE */ +#if(USBFS_DMA5_REMOVE == 0u) + #include "USBFS_ep5_dma.h" +#endif /* USBFS_DMA5_REMOVE */ +#if(USBFS_DMA6_REMOVE == 0u) + #include "USBFS_ep6_dma.h" +#endif /* USBFS_DMA6_REMOVE */ +#if(USBFS_DMA7_REMOVE == 0u) + #include "USBFS_ep7_dma.h" +#endif /* USBFS_DMA7_REMOVE */ +#if(USBFS_DMA8_REMOVE == 0u) + #include "USBFS_ep8_dma.h" +#endif /* USBFS_DMA8_REMOVE */ +#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + #include "USBFS_EP_DMA_Done_isr.h" + #include "USBFS_EP8_DMA_Done_SR.h" + #include "USBFS_EP17_DMA_Done_SR.h" +#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + +/*************************************** +* Global data allocation +***************************************/ + +uint8 USBFS_initVar = 0u; +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint8 USBFS_DmaChan[USBFS_MAX_EP]; + uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* USBFS_EP_MM */ +#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + static uint8 clearInDataRdyStatus = USBFS_ARB_EPX_CFG_DEFAULT; + uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP] = + { 0u, + USBFS_ep1_TD_TERMOUT_EN, + USBFS_ep2_TD_TERMOUT_EN, + USBFS_ep3_TD_TERMOUT_EN, + USBFS_ep4_TD_TERMOUT_EN, + USBFS_ep5_TD_TERMOUT_EN, + USBFS_ep6_TD_TERMOUT_EN, + USBFS_ep7_TD_TERMOUT_EN, + USBFS_ep8_TD_TERMOUT_EN + }; + volatile uint16 USBFS_inLength[USBFS_MAX_EP]; + const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; +#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + +/******************************************************************************* +* Function Name: USBFS_Start +******************************************************************************** +* +* Summary: +* This function initialize the USB SIE, arbiter and the +* endpoint APIs, including setting the D+ Pullup +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* The USBFS_intiVar variable is used to indicate initial +* configuration of this component. The variable is initialized to zero (0u) +* and set to one (1u) the first time USBFS_Start() is called. +* This allows for component Re-Start without unnecessary re-initialization +* in all subsequent calls to the USBFS_Start() routine. +* If re-initialization of the component is required the variable should be set +* to zero before call of UART_Start() routine, or the user may call +* USBFS_Init() and USBFS_InitComponent() as done +* in the USBFS_Start() routine. +* +* Side Effects: +* This function will reset all communication states to default. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Start(uint8 device, uint8 mode) +{ + /* If not Initialized then initialize all required hardware and software */ + if(USBFS_initVar == 0u) + { + USBFS_Init(); + USBFS_initVar = 1u; + } + USBFS_InitComponent(device, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Init +******************************************************************************** +* +* Summary: +* Initialize component's hardware. Usually called in USBFS_Start(). +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Init(void) +{ + uint8 enableInterrupts; + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + uint16 i; + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + enableInterrupts = CyEnterCriticalSection(); + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + + /* Enable core clock */ + USBFS_USB_CLK_EN_REG = USBFS_USB_CLK_ENABLE; + + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + + /* ENABLING USBIO PADS IN USB MODE FROM I/O MODE */ + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= ((uint8)(~USBFS_USBIO_CR0_TEN)); + CyDelayUs(0u); /*~50ns delay */ + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) + * high. This will have been set low by the power manger out of reset. + * Also confirm USBIO pull-up disabled + */ + USBFS_PM_USB_CR0_REG &= ((uint8)(~(USBFS_PM_USB_CR0_PD_N | + USBFS_PM_USB_CR0_PD_PULLUP_N))); + + /* Select iomode to USB mode*/ + USBFS_USBIO_CR1_REG &= ((uint8)(~USBFS_USBIO_CR1_IOMODE)); + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available 1 us after the regulator is enabled */ + CyDelayUs(1u); + /* OR 40us after power restored */ + CyDelayUs(40u); + /* Ensure the single ended disable bits are low (PRT15.INP_DIS[7:6])(input receiver enabled). */ + USBFS_DM_INP_DIS_REG &= ((uint8)(~USBFS_DM_MASK)); + USBFS_DP_INP_DIS_REG &= ((uint8)(~USBFS_DP_MASK)); + + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Write WAx */ + CY_SET_REG8(USBFS_ARB_RW1_WA_PTR, 0u); + CY_SET_REG8(USBFS_ARB_RW1_WA_MSB_PTR, 0u); + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Init transfer descriptor. This will be used to detect the DMA state - initialized or not. */ + for (i = 0u; i < USBFS_MAX_EP; i++) + { + USBFS_DmaTd[i] = DMA_INVALID_TD; + #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + } + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + CyExitCriticalSection(enableInterrupts); + + + /* Set the bus reset Interrupt. */ + (void) CyIntSetVector(USBFS_BUS_RESET_VECT_NUM, &USBFS_BUS_RESET_ISR); + CyIntSetPriority(USBFS_BUS_RESET_VECT_NUM, USBFS_BUS_RESET_PRIOR); + + /* Set the SOF Interrupt. */ + #if(USBFS_SOF_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_SOF_VECT_NUM, &USBFS_SOF_ISR); + CyIntSetPriority(USBFS_SOF_VECT_NUM, USBFS_SOF_PRIOR); + #endif /* USBFS_SOF_ISR_REMOVE */ + + /* Set the Control Endpoint Interrupt. */ + (void) CyIntSetVector(USBFS_EP_0_VECT_NUM, &USBFS_EP_0_ISR); + CyIntSetPriority(USBFS_EP_0_VECT_NUM, USBFS_EP_0_PRIOR); + + /* Set the Data Endpoint 1 Interrupt. */ + #if(USBFS_EP1_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_1_VECT_NUM, &USBFS_EP_1_ISR); + CyIntSetPriority(USBFS_EP_1_VECT_NUM, USBFS_EP_1_PRIOR); + #endif /* USBFS_EP1_ISR_REMOVE */ + + /* Set the Data Endpoint 2 Interrupt. */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_2_VECT_NUM, &USBFS_EP_2_ISR); + CyIntSetPriority(USBFS_EP_2_VECT_NUM, USBFS_EP_2_PRIOR); + #endif /* USBFS_EP2_ISR_REMOVE */ + + /* Set the Data Endpoint 3 Interrupt. */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_3_VECT_NUM, &USBFS_EP_3_ISR); + CyIntSetPriority(USBFS_EP_3_VECT_NUM, USBFS_EP_3_PRIOR); + #endif /* USBFS_EP3_ISR_REMOVE */ + + /* Set the Data Endpoint 4 Interrupt. */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_4_VECT_NUM, &USBFS_EP_4_ISR); + CyIntSetPriority(USBFS_EP_4_VECT_NUM, USBFS_EP_4_PRIOR); + #endif /* USBFS_EP4_ISR_REMOVE */ + + /* Set the Data Endpoint 5 Interrupt. */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_5_VECT_NUM, &USBFS_EP_5_ISR); + CyIntSetPriority(USBFS_EP_5_VECT_NUM, USBFS_EP_5_PRIOR); + #endif /* USBFS_EP5_ISR_REMOVE */ + + /* Set the Data Endpoint 6 Interrupt. */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_6_VECT_NUM, &USBFS_EP_6_ISR); + CyIntSetPriority(USBFS_EP_6_VECT_NUM, USBFS_EP_6_PRIOR); + #endif /* USBFS_EP6_ISR_REMOVE */ + + /* Set the Data Endpoint 7 Interrupt. */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_7_VECT_NUM, &USBFS_EP_7_ISR); + CyIntSetPriority(USBFS_EP_7_VECT_NUM, USBFS_EP_7_PRIOR); + #endif /* USBFS_EP7_ISR_REMOVE */ + + /* Set the Data Endpoint 8 Interrupt. */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_EP_8_VECT_NUM, &USBFS_EP_8_ISR); + CyIntSetPriority(USBFS_EP_8_VECT_NUM, USBFS_EP_8_PRIOR); + #endif /* USBFS_EP8_ISR_REMOVE */ + + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* Set the ARB Interrupt. */ + (void) CyIntSetVector(USBFS_ARB_VECT_NUM, &USBFS_ARB_ISR); + CyIntSetPriority(USBFS_ARB_VECT_NUM, USBFS_ARB_PRIOR); + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + +} + + +/******************************************************************************* +* Function Name: USBFS_InitComponent +******************************************************************************** +* +* Summary: +* Initialize the component, except for the HW which is done one time in +* the Start function. This function pulls up D+. +* +* Parameters: +* device: Contains the device number of the desired device descriptor. +* The device number can be found in the Device Descriptor Tab of +* "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* mode: The operating voltage. This determines whether the voltage regulator +* is enabled for 5V operation or if pass through mode is used for 3.3V +* operation. Symbolic names and their associated values are given in the +* following table. +* USBFS_3V_OPERATION - Disable voltage regulator and pass-thru +* Vcc for pull-up +* USBFS_5V_OPERATION - Enable voltage regulator and use +* regulator for pull-up +* USBFS_DWR_VDDD_OPERATION - Enable or Disable voltage +* regulator depend on Vddd Voltage configuration in DWR. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitComponent(uint8 device, uint8 mode) +{ + /* Initialize _hidProtocol variable to comply with + * HID 7.2.6 Set_Protocol Request: + * "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + /* Enable Interrupts. */ + CyIntEnable(USBFS_BUS_RESET_VECT_NUM); + CyIntEnable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_1_VECT_NUM); + #endif /* USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_2_VECT_NUM); + #endif /* USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_3_VECT_NUM); + #endif /* USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_4_VECT_NUM); + #endif /* USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_5_VECT_NUM); + #endif /* USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_7_VECT_NUM); + #endif /* USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntEnable(USBFS_EP_8_VECT_NUM); + #endif /* USBFS_EP8_ISR_REMOVE */ + #if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + /* usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + CyIntEnable(USBFS_ARB_VECT_NUM); + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #if(USBFS_EP_DMA_AUTO_OPT == 0u) + /* Init interrupt which handles verification of the successful DMA transaction */ + USBFS_EP_DMA_Done_isr_StartEx(&USBFS_EP_DMA_DONE_ISR); + USBFS_EP17_DMA_Done_SR_InterruptEnable(); + USBFS_EP8_DMA_Done_SR_InterruptEnable(); + #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */ + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* USB Locking: Enabled, VRegulator: depend on mode or DWR Voltage configuration*/ + switch(mode) + { + case USBFS_3V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + break; + case USBFS_5V_OPERATION: + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + break; + default: /*USBFS_DWR_VDDD_OPERATION */ + #if(USBFS_VDDD_MV < USBFS_3500MV) + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK; + #else + USBFS_CR1_REG = USBFS_CR1_ENABLE_LOCK | USBFS_CR1_REG_ENABLE; + #endif /* USBFS_VDDD_MV < USBFS_3500MV */ + break; + } + + /* Record the descriptor selection */ + USBFS_device = device; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + + /* Workaround for PSOC5LP */ + CyDelayCycles(1u); + + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); +} + + +/******************************************************************************* +* Function Name: USBFS_ReInitComponent +******************************************************************************** +* +* Summary: +* This function reinitialize the component configuration and is +* intend to be called from the Reset interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_device: Contains the device number of the desired device +* descriptor. The device number can be found in the Device Descriptor Tab +* of "Configure" dialog, under the settings of desired Device Descriptor, +* in the "Device Number" field. +* USBFS_transferState: This variable used by the communication +* functions to handle current transfer state. Initialized to +* TRANS_STATE_IDLE in this API. +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_lastPacketSize initialized to 0; +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ReInitComponent(void) +{ + /* Initialize _hidProtocol variable to comply with HID 7.2.6 Set_Protocol + * Request: "When initialized, all devices default to report protocol." + */ + #if defined(USBFS_ENABLE_HID_CLASS) + uint8 i; + + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_hidProtocol[i] = USBFS_PROTOCOL_REPORT; + } + #endif /* USBFS_ENABLE_HID_CLASS */ + + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + + USBFS_lastPacketSize = 0u; + + + /* ACK Setup, Stall IN/OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + + /* Enable the SIE with an address 0 */ + CY_SET_REG8(USBFS_CR0_PTR, USBFS_CR0_ENABLE); + +} + + +/******************************************************************************* +* Function Name: USBFS_Stop +******************************************************************************** +* +* Summary: +* This function shuts down the USB function including to release +* the D+ Pullup and disabling the SIE. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_configuration: Contains current configuration number +* which is set by the Host using SET_CONFIGURATION request. +* Initialized to zero in this API. +* USBFS_deviceAddress: Contains current device address. This +* variable is initialized to zero in this API. Host starts to communicate +* to device with address 0 and then set it to whatever value using +* SET_ADDRESS request. +* USBFS_deviceStatus: initialized to 0. +* This is two bit variable which contain power status in first bit +* (DEVICE_STATUS_BUS_POWERED or DEVICE_STATUS_SELF_POWERED) and remote +* wakeup status (DEVICE_STATUS_REMOTE_WAKEUP) in second bit. +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* USBFS_intiVar variable is set to zero +* +*******************************************************************************/ +void USBFS_Stop(void) +{ + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)(~USBFS_CR0_ENABLE); + /* Disable the d+ pullup */ + USBFS_USBIO_CR1_REG &= (uint8)(~USBFS_USBIO_CR1_USBPUEN); + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)(~USBFS_PM_ACT_EN_FSUSB); + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)(~USBFS_PM_STBY_EN_FSUSB); + + /* Disable the reset and EP interrupts */ + CyIntDisable(USBFS_BUS_RESET_VECT_NUM); + CyIntDisable(USBFS_EP_0_VECT_NUM); + #if(USBFS_EP1_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_1_VECT_NUM); + #endif /* USBFS_EP1_ISR_REMOVE */ + #if(USBFS_EP2_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_2_VECT_NUM); + #endif /* USBFS_EP2_ISR_REMOVE */ + #if(USBFS_EP3_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_3_VECT_NUM); + #endif /* USBFS_EP3_ISR_REMOVE */ + #if(USBFS_EP4_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_4_VECT_NUM); + #endif /* USBFS_EP4_ISR_REMOVE */ + #if(USBFS_EP5_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_5_VECT_NUM); + #endif /* USBFS_EP5_ISR_REMOVE */ + #if(USBFS_EP6_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_6_VECT_NUM); + #endif /* USBFS_EP6_ISR_REMOVE */ + #if(USBFS_EP7_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_7_VECT_NUM); + #endif /* USBFS_EP7_ISR_REMOVE */ + #if(USBFS_EP8_ISR_REMOVE == 0u) + CyIntDisable(USBFS_EP_8_VECT_NUM); + #endif /* USBFS_EP8_ISR_REMOVE */ + + /* Clear all of the component data */ + USBFS_configuration = 0u; + USBFS_interfaceNumber = 0u; + USBFS_configurationChanged = 0u; + USBFS_deviceAddress = 0u; + USBFS_deviceStatus = 0u; + USBFS_initVar = 0u; + +} + + +/******************************************************************************* +* Function Name: USBFS_CheckActivity +******************************************************************************** +* +* Summary: +* Returns the activity status of the bus. Clears the status hardware to +* provide fresh activity status on the next call of this routine. +* +* Parameters: +* None. +* +* Return: +* 1 - If bus activity was detected since the last call to this function +* 0 - If bus activity not was detected since the last call to this function +* +*******************************************************************************/ +uint8 USBFS_CheckActivity(void) +{ + uint8 r; + + r = CY_GET_REG8(USBFS_CR1_PTR); + CY_SET_REG8(USBFS_CR1_PTR, (r & ((uint8)(~USBFS_CR1_BUS_ACTIVITY)))); + + return((r & USBFS_CR1_BUS_ACTIVITY) >> USBFS_CR1_BUS_ACTIVITY_SHIFT); +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfiguration +******************************************************************************** +* +* Summary: +* Returns the current configuration setting +* +* Parameters: +* None. +* +* Return: +* configuration. +* +*******************************************************************************/ +uint8 USBFS_GetConfiguration(void) +{ + return(USBFS_configuration); +} + + +/******************************************************************************* +* Function Name: USBFS_IsConfigurationChanged +******************************************************************************** +* +* Summary: +* Returns the clear on read configuration state. It is usefull when PC send +* double SET_CONFIGURATION request with same configuration number. +* +* Parameters: +* None. +* +* Return: +* Not zero value when new configuration has been changed, otherwise zero is +* returned. +* +* Global variables: +* USBFS_configurationChanged: This variable is set to one after +* SET_CONFIGURATION request and cleared in this function. +* +*******************************************************************************/ +uint8 USBFS_IsConfigurationChanged(void) +{ + uint8 res = 0u; + + if(USBFS_configurationChanged != 0u) + { + res = USBFS_configurationChanged; + USBFS_configurationChanged = 0u; + } + + return(res); +} + + +/******************************************************************************* +* Function Name: USBFS_GetInterfaceSetting +******************************************************************************** +* +* Summary: +* Returns the alternate setting from current interface +* +* Parameters: +* uint8 interfaceNumber, interface number +* +* Return: +* Alternate setting. +* +*******************************************************************************/ +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + +{ + return(USBFS_interfaceSetting[interfaceNumber]); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPState +******************************************************************************** +* +* Summary: +* Returned the state of the requested endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* +* Return: +* State of the requested endpoint. +* +*******************************************************************************/ +uint8 USBFS_GetEPState(uint8 epNumber) +{ + return(USBFS_EP[epNumber].apiEpState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPCount +******************************************************************************** +* +* Summary: +* This function supports Data Endpoints only(EP1-EP8). +* Returns the transfer count for the requested endpoint. The value from +* the count registers includes 2 counts for the two byte checksum of the +* packet. This function subtracts the two counts. +* +* Parameters: +* epNumber: Data Endpoint Number. +* Valid values are between 1 and 8. +* +* Return: +* Returns the current byte count from the specified endpoint or 0 for an +* invalid endpoint. +* +*******************************************************************************/ +uint16 USBFS_GetEPCount(uint8 epNumber) +{ + uint8 ri; + uint16 result = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + result = (uint8)(CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & + USBFS_EPX_CNT0_MASK); + result = (result << 8u) | CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri)); + result -= USBFS_EPX_CNTX_CRC_COUNT; + } + return(result); +} + + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + + + /******************************************************************************* + * Function Name: USBFS_InitEP_DMA + ******************************************************************************** + * + * Summary: + * This function allocates and initializes a DMA channel to be used by the + * USBFS_LoadInEP() or USBFS_ReadOutEP() APIs for data + * transfer. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * Valid values are between 1 and 8. + * *pData: Pointer to a data array that is related to the EP transfers. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData) + + { + uint16 src; + uint16 dst; + #if (CY_PSOC3) /* PSoC 3 */ + src = HI16(CYDEV_SRAM_BASE); + dst = HI16(CYDEV_PERIPH_BASE); + pData = pData; + #else /* PSoC 5 */ + if((USBFS_EP[epNumber].addr & USBFS_DIR_IN) != 0u ) + { /* for the IN EP source is the SRAM memory buffer */ + src = HI16(pData); + dst = HI16(CYDEV_PERIPH_BASE); + } + else + { /* for the OUT EP source is the SIE register */ + src = HI16(CYDEV_PERIPH_BASE); + dst = HI16(pData); + } + #endif /* C51 */ + switch(epNumber) + { + case USBFS_EP1: + #if(USBFS_DMA1_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep1_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA1_REMOVE */ + break; + case USBFS_EP2: + #if(USBFS_DMA2_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep2_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA2_REMOVE */ + break; + case USBFS_EP3: + #if(USBFS_DMA3_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep3_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA3_REMOVE */ + break; + case USBFS_EP4: + #if(USBFS_DMA4_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep4_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA4_REMOVE */ + break; + case USBFS_EP5: + #if(USBFS_DMA5_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep5_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA5_REMOVE */ + break; + case USBFS_EP6: + #if(USBFS_DMA6_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep6_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA6_REMOVE */ + break; + case USBFS_EP7: + #if(USBFS_DMA7_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep7_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA7_REMOVE */ + break; + case USBFS_EP8: + #if(USBFS_DMA8_REMOVE == 0u) + USBFS_DmaChan[epNumber] = USBFS_ep8_DmaInitialize( + USBFS_DMA_BYTES_PER_BURST, USBFS_DMA_REQUEST_PER_BURST, src, dst); + #endif /* USBFS_DMA8_REMOVE */ + break; + default: + /* Do not support EP0 DMA transfers */ + break; + } + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + USBFS_DmaTd[epNumber] = CyDmaTdAllocate(); + #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + USBFS_DmaNextTd[epNumber] = CyDmaTdAllocate(); + #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + } + } + + + /******************************************************************************* + * Function Name: USBFS_Stop_DMA + ******************************************************************************** + * + * Summary: Stops and free DMA + * + * Parameters: + * epNumber: Contains the data endpoint number or + * USBFS_MAX_EP to stop all DMAs + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_Stop_DMA(uint8 epNumber) + { + uint8 i; + i = (epNumber < USBFS_MAX_EP) ? epNumber : USBFS_EP1; + do + { + if(USBFS_DmaTd[i] != DMA_INVALID_TD) + { + (void) CyDmaChDisable(USBFS_DmaChan[i]); + CyDmaTdFree(USBFS_DmaTd[i]); + USBFS_DmaTd[i] = DMA_INVALID_TD; + } + #if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + if(USBFS_DmaNextTd[i] != DMA_INVALID_TD) + { + CyDmaTdFree(USBFS_DmaNextTd[i]); + USBFS_DmaNextTd[i] = DMA_INVALID_TD; + } + #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + i++; + }while((i < USBFS_MAX_EP) && (epNumber == USBFS_MAX_EP)); + } + +#endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + +#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + + + /******************************************************************************* + * Function Name: USBFS_LoadNextInEP + ******************************************************************************** + * + * Summary: + * This internal function is used for IN endpoint DMA reconfiguration in + * Auto DMA mode. + * + * Parameters: + * epNumber: Contains the data endpoint number. + * mode: 0 - Configure DMA to send the the rest of data. + * 1 - Configure DMA to repeat 2 last bytes of the first burst. + * + * Return: + * None. + * + *******************************************************************************/ + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) + { + reg16 *convert; + + if(mode == 0u) + { + /* Configure DMA to send the the rest of data */ + /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length */ + CY_SET_REG16(convert, USBFS_inLength[epNumber] - USBFS_DMA_BYTES_PER_BURST); + /* CyDmaTdSetAddress API is optimized to change only source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + USBFS_DMA_BYTES_PER_BURST)); + USBFS_inBufFull[epNumber] = 1u; + } + else + { + /* Configure DMA to repeat 2 last bytes of the first burst. */ + /* CyDmaTdSetConfiguration API is optimised to change only transfer length and configure TD */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD0[0u]; + /* Set transfer length */ + CY_SET_REG16(convert, USBFS_DMA_BYTES_REPEAT); + /* CyDmaTdSetAddress API is optimized to change only source address */ + convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[USBFS_DmaTd[epNumber]].TD1[0u]; + CY_SET_REG16(convert, LO16((uint32)USBFS_inDataPointer[epNumber] + + USBFS_DMA_BYTES_PER_BURST - USBFS_DMA_BYTES_REPEAT)); + } + + /* CyDmaChSetInitialTd API is optimised to init TD */ + CY_DMA_CH_STRUCT_PTR[USBFS_DmaChan[epNumber]].basic_status[1u] = USBFS_DmaTd[epNumber]; + } +#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + +/******************************************************************************* +* Function Name: USBFS_LoadInEP +******************************************************************************** +* +* Summary: +* Loads and enables the specified USB data endpoint for an IN transfer. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* *pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the array and then send as a +* result of an IN request. Valid values are between 0 and 512. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Limits length to available buffer space, auto MM could send packets up to 1024 bytes */ + if(length > (USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset)) + { + length = USBFS_EPX_DATA_BUF_MAX - USBFS_EP[epNumber].buffOffset; + } + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Set the count and data toggle */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + (length >> 8u) | (USBFS_EP[epNumber].epToggle)); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), length & 0xFFu); + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + if(pData != NULL) + { + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + CY_SET_REG8(p, pData[i]); + } + } + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + #else + /* Init DMA if it was not initialized */ + if (USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if ((pData != NULL) && (length > 0u)) + { + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Mode register will be written in arb ISR after DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + if (pData != NULL) + { + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inDataPointer[epNumber] = pData; + /* Configure DMA to send the data only for the first burst */ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], + (length > USBFS_DMA_BYTES_PER_BURST) ? USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + /* The second TD will be executed only when the first one fails. + * The intention of this TD is to generate NRQ interrupt + * and repeat 2 last bytes of the first burst. + */ + (void) CyDmaTdSetConfiguration(USBFS_DmaNextTd[epNumber], 1u, + USBFS_DmaNextTd[epNumber], + USBFS_epX_TD_TERMOUT_EN[epNumber]); + /* Configure DmaNextTd to clear Data ready status */ + (void) CyDmaTdSetAddress(USBFS_DmaNextTd[epNumber], LO16((uint32)&clearInDataRdyStatus), + LO16((uint32)(USBFS_ARB_EP1_CFG_IND + ri))); + #else /* Configure DMA to send all data*/ + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, + USBFS_DmaTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)pData), LO16((uint32)p)); + #endif /* USBFS_EP_DMA_AUTO_OPT == 0u */ + + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + } + else + { + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + if(length > 0u) + { + #if (USBFS_EP_DMA_AUTO_OPT == 0u) + USBFS_inLength[epNumber] = length; + USBFS_inBufFull[epNumber] = 0u; + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + /* Configure DMA to send the data only for the first burst */ + (void) CyDmaTdSetConfiguration( + USBFS_DmaTd[epNumber], (length > USBFS_DMA_BYTES_PER_BURST) ? + USBFS_DMA_BYTES_PER_BURST : length, + USBFS_DmaNextTd[epNumber], TD_TERMIN_EN | TD_INC_SRC_ADR ); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], + LO16((uint32)USBFS_inDataPointer[epNumber]), LO16((uint32)p)); + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + #endif /* (USBFS_EP_DMA_AUTO_OPT == 0u) */ + + /* Set Data ready status, This will generate DMA request */ + #ifndef USBFS_MANUAL_IN_EP_ARM + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #endif /* USBFS_MANUAL_IN_EP_ARM */ + /* Mode register will be written in arb ISR(In Buffer Full) after first DMA transfer complete */ + } + else + { + /* When zero-length packet - write the Mode register directly */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } + } + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } +} + + +/******************************************************************************* +* Function Name: USBFS_ReadOutEP +******************************************************************************** +* +* Summary: +* Read data from an endpoint. The application must call +* USBFS_GetEPState to see if an event is pending. +* +* Parameters: +* epNumber: Contains the data endpoint number. +* Valid values are between 1 and 8. +* pData: A pointer to a data array from which the data for the endpoint space +* is loaded. +* length: The number of bytes to transfer from the USB Out endpoint and loads +* it into data array. Valid values are between 0 and 1023. The function +* moves fewer than the requested number of bytes if the host sends +* fewer bytes than requested. +* +* Returns: +* Number of bytes received, 0 for an invalid endpoint. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + +{ + uint8 ri; + reg8 *p; + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + uint16 i; + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 xferCount; + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP) && (pData != NULL)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + p = (reg8 *)(USBFS_ARB_RW1_DR_IND + ri); + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* Determine which is smaller the requested data or the available data */ + xferCount = USBFS_GetEPCount(epNumber); + if (length > xferCount) + { + length = xferCount; + } + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + /* Copy the data using the arbiter data register */ + for (i = 0u; i < length; i++) + { + pData[i] = CY_GET_REG8(p); + } + + /* (re)arming of OUT endpoint */ + USBFS_EnableOutEP(epNumber); + #else + /*Init DMA if it was not initialized */ + if(USBFS_DmaTd[epNumber] == DMA_INVALID_TD) + { + USBFS_InitEP_DMA(epNumber, pData); + } + + #endif /* USBFS_EP_MM == USBFS__EP_MANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* Enable DMA in mode2 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, CY_DMA_DISABLE_TD, + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + + /* Generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) |= USBFS_ARB_EPX_CFG_DMA_REQ; + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= ((uint8)(~USBFS_ARB_EPX_CFG_DMA_REQ)); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable DMA in mode3 for transferring data */ + (void) CyDmaChDisable(USBFS_DmaChan[epNumber]); + (void) CyDmaTdSetConfiguration(USBFS_DmaTd[epNumber], length, USBFS_DmaTd[epNumber], + TD_TERMIN_EN | TD_INC_DST_ADR); + (void) CyDmaTdSetAddress(USBFS_DmaTd[epNumber], LO16((uint32)p), LO16((uint32)pData)); + + /* Clear Any potential pending DMA requests before starting the DMA channel to transfer data */ + (void) CyDmaClearPendingDrq(USBFS_DmaChan[epNumber]); + /* Enable the DMA */ + (void) CyDmaChSetInitialTd(USBFS_DmaChan[epNumber], USBFS_DmaTd[epNumber]); + (void) CyDmaChEnable(USBFS_DmaChan[epNumber], 1u); + /* Out EP will be (re)armed in arb ISR after transfer complete */ + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + } + else + { + length = 0u; + } + + return(length); +} + + +/******************************************************************************* +* Function Name: USBFS_EnableOutEP +******************************************************************************** +* +* Summary: +* This function enables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +* Global variables: +* USBFS_EP[epNumber].apiEpState - set to NO_EVENT_PENDING +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_EnableOutEP(uint8 epNumber) +{ + uint8 ri; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + USBFS_EP[epNumber].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_EP[epNumber].epMode); + } +} + + +/******************************************************************************* +* Function Name: USBFS_DisableOutEP +******************************************************************************** +* +* Summary: +* This function disables an OUT endpoint. It should not be +* called for an IN endpoint. +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_DisableOutEP(uint8 epNumber) +{ + uint8 ri ; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Force +******************************************************************************** +* +* Summary: +* Forces the bus state +* +* Parameters: +* bState +* USBFS_FORCE_J +* USBFS_FORCE_K +* USBFS_FORCE_SE0 +* USBFS_FORCE_NONE +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_Force(uint8 bState) +{ + CY_SET_REG8(USBFS_USBIO_CR0_PTR, bState); +} + + +/******************************************************************************* +* Function Name: USBFS_GetEPAckState +******************************************************************************** +* +* Summary: +* Returns the ACK of the CR0 Register (ACKD) +* +* Parameters: +* epNumber: Endpoint Number +* Valid values are between 1 and 8. +* +* Returns +* 0 if nothing has been ACKD, non-=zero something has been ACKD +* +*******************************************************************************/ +uint8 USBFS_GetEPAckState(uint8 epNumber) +{ + uint8 ri; + uint8 cr = 0u; + + if((epNumber > USBFS_EP0) && (epNumber < USBFS_MAX_EP)) + { + ri = ((epNumber - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + cr = CY_GET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri)) & USBFS_MODE_ACKD; + } + + return(cr); +} + + +/******************************************************************************* +* Function Name: USBFS_SetPowerStatus +******************************************************************************** +* +* Summary: +* Sets the device power status for reporting in the Get Device Status +* request +* +* Parameters: +* powerStatus: USBFS_DEVICE_STATUS_BUS_POWERED(0) - Bus Powered, +* USBFS_DEVICE_STATUS_SELF_POWERED(1) - Self Powered +* +* Return: +* None. +* +* Global variables: +* USBFS_deviceStatus - set power status +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SetPowerStatus(uint8 powerStatus) +{ + if (powerStatus != USBFS_DEVICE_STATUS_BUS_POWERED) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= ((uint8)(~USBFS_DEVICE_STATUS_SELF_POWERED)); + } +} + + +#if (USBFS_MON_VBUS == 1u) + + /******************************************************************************* + * Function Name: USBFS_VBusPresent + ******************************************************************************** + * + * Summary: + * Determines VBUS presence for Self Powered Devices. + * + * Parameters: + * None. + * + * Return: + * 1 if VBUS is present, otherwise 0. + * + *******************************************************************************/ + uint8 USBFS_VBusPresent(void) + { + return((0u != (CY_GET_REG8(USBFS_VBUS_PS_PTR) & USBFS_VBUS_MASK)) ? 1u : 0u); + } + +#endif /* USBFS_MON_VBUS */ + + +/******************************************************************************* +* Function Name: USBFS_RWUEnabled +******************************************************************************** +* +* Summary: +* Returns TRUE if Remote Wake Up is enabled, otherwise FALSE +* +* Parameters: +* None. +* +* Return: +* TRUE - Remote Wake Up Enabled +* FALSE - Remote Wake Up Disabled +* +* Global variables: +* USBFS_deviceStatus - checked to determine remote status +* +*******************************************************************************/ +uint8 USBFS_RWUEnabled(void) +{ + uint8 result = USBFS_FALSE; + if((USBFS_deviceStatus & USBFS_DEVICE_STATUS_REMOTE_WAKEUP) != 0u) + { + result = USBFS_TRUE; + } + + return(result); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h new file mode 100644 index 0000000..2dde8d0 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS.h @@ -0,0 +1,1248 @@ +/******************************************************************************* +* File Name: USBFS.h +* Version 2.80 +* +* Description: +* Header File for the USBFS component. Contains prototypes and constant values. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_H) +#define CY_USBFS_USBFS_H + +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" + +/* User supplied definitions. */ +/* `#START USER_DEFINITIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component USBFS_v2_80 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Memory Type Definitions +***************************************/ + +/* Renamed Type Definitions for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_CODE CYCODE +#define USBFS_FAR CYFAR +#if defined(__C51__) || defined(__CX51__) + #define USBFS_DATA data + #define USBFS_XDATA xdata +#else + #define USBFS_DATA + #define USBFS_XDATA +#endif /* __C51__ */ +#define USBFS_NULL NULL + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +#define USBFS__EP_MANUAL 0 +#define USBFS__EP_DMAMANUAL 1 +#define USBFS__EP_DMAAUTO 2 + +#define USBFS__MA_STATIC 0 +#define USBFS__MA_DYNAMIC 1 + + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define USBFS_NUM_DEVICES (1u) +#define USBFS_ENABLE_DESCRIPTOR_STRINGS +#define USBFS_ENABLE_SN_STRING +#define USBFS_ENABLE_STRINGS +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_IN_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE (65u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_NUM_OUT_RPTS (1u) +#define USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT (1u) +#define USBFS_ENABLE_HID_CLASS +#define USBFS_HID_RPT_1_SIZE_LSB (0x24u) +#define USBFS_HID_RPT_1_SIZE_MSB (0x00u) +#define USBFS_MAX_REPORTID_NUMBER (0u) + +#define USBFS_MON_VBUS (0u) +#define USBFS_EXTERN_VBUS (0u) +#define USBFS_EXTERN_VND (0u) +#define USBFS_EXTERN_CLS (0u) +#define USBFS_MAX_INTERFACES_NUMBER (1u) +#define USBFS_EP0_ISR_REMOVE (0u) +#define USBFS_EP1_ISR_REMOVE (0u) +#define USBFS_EP2_ISR_REMOVE (0u) +#define USBFS_EP3_ISR_REMOVE (1u) +#define USBFS_EP4_ISR_REMOVE (1u) +#define USBFS_EP5_ISR_REMOVE (1u) +#define USBFS_EP6_ISR_REMOVE (1u) +#define USBFS_EP7_ISR_REMOVE (1u) +#define USBFS_EP8_ISR_REMOVE (1u) +#define USBFS_EP_MM (0u) +#define USBFS_EP_MA (0u) +#define USBFS_EP_DMA_AUTO_OPT (0u) +#define USBFS_DMA1_REMOVE (1u) +#define USBFS_DMA2_REMOVE (1u) +#define USBFS_DMA3_REMOVE (1u) +#define USBFS_DMA4_REMOVE (1u) +#define USBFS_DMA5_REMOVE (1u) +#define USBFS_DMA6_REMOVE (1u) +#define USBFS_DMA7_REMOVE (1u) +#define USBFS_DMA8_REMOVE (1u) +#define USBFS_SOF_ISR_REMOVE (0u) +#define USBFS_ARB_ISR_REMOVE (0u) +#define USBFS_DP_ISR_REMOVE (0u) +#define USBFS_ENABLE_CDC_CLASS_API (1u) +#define USBFS_ENABLE_MIDI_API (1u) +#define USBFS_MIDI_EXT_MODE (0u) + + +/*************************************** +* Data Struct Definition +***************************************/ + +typedef struct +{ + uint8 attrib; + uint8 apiEpState; + uint8 hwEpState; + uint8 epToggle; + uint8 addr; + uint8 epMode; + uint16 buffOffset; + uint16 bufferSize; + uint8 interface; +} T_USBFS_EP_CTL_BLOCK; + +typedef struct +{ + uint8 interface; + uint8 altSetting; + uint8 addr; + uint8 attributes; + uint16 bufferSize; + uint8 bMisc; +} T_USBFS_EP_SETTINGS_BLOCK; + +typedef struct +{ + uint8 status; + uint16 length; +} T_USBFS_XFER_STATUS_BLOCK; + +typedef struct +{ + uint16 count; + volatile uint8 *pData; + T_USBFS_XFER_STATUS_BLOCK *pStatusBlock; +} T_USBFS_TD; + + +typedef struct +{ + uint8 c; + const void *p_list; +} T_USBFS_LUT; + +/* Resume/Suspend API Support */ +typedef struct +{ + uint8 enableState; + uint8 mode; +} USBFS_BACKUP_STRUCT; + + +/* Renamed structure fields for backward compatibility. +* Should not be used in new designs. +*/ +#define wBuffOffset buffOffset +#define wBufferSize bufferSize +#define bStatus status +#define wLength length +#define wCount count + +/* Renamed global variable for backward compatibility. +* Should not be used in new designs. +*/ +#define CurrentTD USBFS_currentTD + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Start(uint8 device, uint8 mode) ; +void USBFS_Init(void) ; +void USBFS_InitComponent(uint8 device, uint8 mode) ; +void USBFS_Stop(void) ; +uint8 USBFS_CheckActivity(void) ; +uint8 USBFS_GetConfiguration(void) ; +uint8 USBFS_IsConfigurationChanged(void) ; +uint8 USBFS_GetInterfaceSetting(uint8 interfaceNumber) + ; +uint8 USBFS_GetEPState(uint8 epNumber) ; +uint16 USBFS_GetEPCount(uint8 epNumber) ; +void USBFS_LoadInEP(uint8 epNumber, const uint8 pData[], uint16 length) + ; +uint16 USBFS_ReadOutEP(uint8 epNumber, uint8 pData[], uint16 length) + ; +void USBFS_EnableOutEP(uint8 epNumber) ; +void USBFS_DisableOutEP(uint8 epNumber) ; +void USBFS_Force(uint8 bState) ; +uint8 USBFS_GetEPAckState(uint8 epNumber) ; +void USBFS_SetPowerStatus(uint8 powerStatus) ; +uint8 USBFS_RWUEnabled(void) ; +void USBFS_TerminateEP(uint8 ep) ; + +void USBFS_Suspend(void) ; +void USBFS_Resume(void) ; + +#if defined(USBFS_ENABLE_FWSN_STRING) + void USBFS_SerialNumString(uint8 snString[]) ; +#endif /* USBFS_ENABLE_FWSN_STRING */ +#if (USBFS_MON_VBUS == 1u) + uint8 USBFS_VBusPresent(void) ; +#endif /* USBFS_MON_VBUS */ + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + void USBFS_CyBtldrCommStart(void) ; + void USBFS_CyBtldrCommStop(void) ; + void USBFS_CyBtldrCommReset(void) ; + cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + cystatus USBFS_CyBtldrCommRead (uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + ; + + #define USBFS_BTLDR_OUT_EP (0x01u) + #define USBFS_BTLDR_IN_EP (0x02u) + + #define USBFS_BTLDR_SIZEOF_WRITE_BUFFER (64u) /* EP 1 OUT */ + #define USBFS_BTLDR_SIZEOF_READ_BUFFER (64u) /* EP 2 IN */ + #define USBFS_BTLDR_MAX_PACKET_SIZE USBFS_BTLDR_SIZEOF_WRITE_BUFFER + + #define USBFS_BTLDR_WAIT_1_MS (1u) /* Time Out quantity equal 1mS */ + + /* These defines active if used USBFS interface as an + * IO Component for bootloading. When Custom_Interface selected + * in Bootloder configuration as the IO Component, user must + * provide these functions. + */ + #if (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) + #define CyBtldrCommStart USBFS_CyBtldrCommStart + #define CyBtldrCommStop USBFS_CyBtldrCommStop + #define CyBtldrCommReset USBFS_CyBtldrCommReset + #define CyBtldrCommWrite USBFS_CyBtldrCommWrite + #define CyBtldrCommRead USBFS_CyBtldrCommRead + #endif /*End CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + +#endif /* CYDEV_BOOTLOADER_IO_COMP */ + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + void USBFS_InitEP_DMA(uint8 epNumber, const uint8* pData) + ; + void USBFS_Stop_DMA(uint8 epNumber) ; +#endif /* USBFS_EP_MM != USBFS__EP_MANUAL) */ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u) + void USBFS_MIDI_EP_Init(void) ; + + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + void USBFS_MIDI_IN_Service(void) ; + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + ; + #endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + void USBFS_MIDI_OUT_EP_Service(void) ; + #endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#endif /* USBFS_ENABLE_MIDI_API != 0u */ + +/* Renamed Functions for backward compatibility. +* Should not be used in new designs. +*/ + +#define USBFS_bCheckActivity USBFS_CheckActivity +#define USBFS_bGetConfiguration USBFS_GetConfiguration +#define USBFS_bGetInterfaceSetting USBFS_GetInterfaceSetting +#define USBFS_bGetEPState USBFS_GetEPState +#define USBFS_wGetEPCount USBFS_GetEPCount +#define USBFS_bGetEPAckState USBFS_GetEPAckState +#define USBFS_bRWUEnabled USBFS_RWUEnabled +#define USBFS_bVBusPresent USBFS_VBusPresent + +#define USBFS_bConfiguration USBFS_configuration +#define USBFS_bInterfaceSetting USBFS_interfaceSetting +#define USBFS_bDeviceAddress USBFS_deviceAddress +#define USBFS_bDeviceStatus USBFS_deviceStatus +#define USBFS_bDevice USBFS_device +#define USBFS_bTransferState USBFS_transferState +#define USBFS_bLastPacketSize USBFS_lastPacketSize + +#define USBFS_LoadEP USBFS_LoadInEP +#define USBFS_LoadInISOCEP USBFS_LoadInEP +#define USBFS_EnableOutISOCEP USBFS_EnableOutEP + +#define USBFS_SetVector CyIntSetVector +#define USBFS_SetPriority CyIntSetPriority +#define USBFS_EnableInt CyIntEnable + + +/*************************************** +* API Constants +***************************************/ + +#define USBFS_EP0 (0u) +#define USBFS_EP1 (1u) +#define USBFS_EP2 (2u) +#define USBFS_EP3 (3u) +#define USBFS_EP4 (4u) +#define USBFS_EP5 (5u) +#define USBFS_EP6 (6u) +#define USBFS_EP7 (7u) +#define USBFS_EP8 (8u) +#define USBFS_MAX_EP (9u) + +#define USBFS_TRUE (1u) +#define USBFS_FALSE (0u) + +#define USBFS_NO_EVENT_ALLOWED (2u) +#define USBFS_EVENT_PENDING (1u) +#define USBFS_NO_EVENT_PENDING (0u) + +#define USBFS_IN_BUFFER_FULL USBFS_NO_EVENT_PENDING +#define USBFS_IN_BUFFER_EMPTY USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_FULL USBFS_EVENT_PENDING +#define USBFS_OUT_BUFFER_EMPTY USBFS_NO_EVENT_PENDING + +#define USBFS_FORCE_J (0xA0u) +#define USBFS_FORCE_K (0x80u) +#define USBFS_FORCE_SE0 (0xC0u) +#define USBFS_FORCE_NONE (0x00u) + +#define USBFS_IDLE_TIMER_RUNNING (0x02u) +#define USBFS_IDLE_TIMER_EXPIRED (0x01u) +#define USBFS_IDLE_TIMER_INDEFINITE (0x00u) + +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) + +#define USBFS_3V_OPERATION (0x00u) +#define USBFS_5V_OPERATION (0x01u) +#define USBFS_DWR_VDDD_OPERATION (0x02u) + +#define USBFS_MODE_DISABLE (0x00u) +#define USBFS_MODE_NAK_IN_OUT (0x01u) +#define USBFS_MODE_STATUS_OUT_ONLY (0x02u) +#define USBFS_MODE_STALL_IN_OUT (0x03u) +#define USBFS_MODE_RESERVED_0100 (0x04u) +#define USBFS_MODE_ISO_OUT (0x05u) +#define USBFS_MODE_STATUS_IN_ONLY (0x06u) +#define USBFS_MODE_ISO_IN (0x07u) +#define USBFS_MODE_NAK_OUT (0x08u) +#define USBFS_MODE_ACK_OUT (0x09u) +#define USBFS_MODE_RESERVED_1010 (0x0Au) +#define USBFS_MODE_ACK_OUT_STATUS_IN (0x0Bu) +#define USBFS_MODE_NAK_IN (0x0Cu) +#define USBFS_MODE_ACK_IN (0x0Du) +#define USBFS_MODE_RESERVED_1110 (0x0Eu) +#define USBFS_MODE_ACK_IN_STATUS_OUT (0x0Fu) +#define USBFS_MODE_MASK (0x0Fu) +#define USBFS_MODE_STALL_DATA_EP (0x80u) + +#define USBFS_MODE_ACKD (0x10u) +#define USBFS_MODE_OUT_RCVD (0x20u) +#define USBFS_MODE_IN_RCVD (0x40u) +#define USBFS_MODE_SETUP_RCVD (0x80u) + +#define USBFS_RQST_TYPE_MASK (0x60u) +#define USBFS_RQST_TYPE_STD (0x00u) +#define USBFS_RQST_TYPE_CLS (0x20u) +#define USBFS_RQST_TYPE_VND (0x40u) +#define USBFS_RQST_DIR_MASK (0x80u) +#define USBFS_RQST_DIR_D2H (0x80u) +#define USBFS_RQST_DIR_H2D (0x00u) +#define USBFS_RQST_RCPT_MASK (0x03u) +#define USBFS_RQST_RCPT_DEV (0x00u) +#define USBFS_RQST_RCPT_IFC (0x01u) +#define USBFS_RQST_RCPT_EP (0x02u) +#define USBFS_RQST_RCPT_OTHER (0x03u) + +/* USB Class Codes */ +#define USBFS_CLASS_DEVICE (0x00u) /* Use class code info from Interface Descriptors */ +#define USBFS_CLASS_AUDIO (0x01u) /* Audio device */ +#define USBFS_CLASS_CDC (0x02u) /* Communication device class */ +#define USBFS_CLASS_HID (0x03u) /* Human Interface Device */ +#define USBFS_CLASS_PDC (0x05u) /* Physical device class */ +#define USBFS_CLASS_IMAGE (0x06u) /* Still Imaging device */ +#define USBFS_CLASS_PRINTER (0x07u) /* Printer device */ +#define USBFS_CLASS_MSD (0x08u) /* Mass Storage device */ +#define USBFS_CLASS_HUB (0x09u) /* Full/Hi speed Hub */ +#define USBFS_CLASS_CDC_DATA (0x0Au) /* CDC data device */ +#define USBFS_CLASS_SMART_CARD (0x0Bu) /* Smart Card device */ +#define USBFS_CLASS_CSD (0x0Du) /* Content Security device */ +#define USBFS_CLASS_VIDEO (0x0Eu) /* Video device */ +#define USBFS_CLASS_PHD (0x0Fu) /* Personal Healthcare device */ +#define USBFS_CLASS_WIRELESSD (0xDCu) /* Wireless Controller */ +#define USBFS_CLASS_MIS (0xE0u) /* Miscellaneous */ +#define USBFS_CLASS_APP (0xEFu) /* Application Specific */ +#define USBFS_CLASS_VENDOR (0xFFu) /* Vendor specific */ + + +/* Standard Request Types (Table 9-4) */ +#define USBFS_GET_STATUS (0x00u) +#define USBFS_CLEAR_FEATURE (0x01u) +#define USBFS_SET_FEATURE (0x03u) +#define USBFS_SET_ADDRESS (0x05u) +#define USBFS_GET_DESCRIPTOR (0x06u) +#define USBFS_SET_DESCRIPTOR (0x07u) +#define USBFS_GET_CONFIGURATION (0x08u) +#define USBFS_SET_CONFIGURATION (0x09u) +#define USBFS_GET_INTERFACE (0x0Au) +#define USBFS_SET_INTERFACE (0x0Bu) +#define USBFS_SYNCH_FRAME (0x0Cu) + +/* Vendor Specific Request Types */ +/* Request for Microsoft OS String Descriptor */ +#define USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR (0x01u) + +/* Descriptor Types (Table 9-5) */ +#define USBFS_DESCR_DEVICE (1u) +#define USBFS_DESCR_CONFIG (2u) +#define USBFS_DESCR_STRING (3u) +#define USBFS_DESCR_INTERFACE (4u) +#define USBFS_DESCR_ENDPOINT (5u) +#define USBFS_DESCR_DEVICE_QUALIFIER (6u) +#define USBFS_DESCR_OTHER_SPEED (7u) +#define USBFS_DESCR_INTERFACE_POWER (8u) + +/* Device Descriptor Defines */ +#define USBFS_DEVICE_DESCR_LENGTH (18u) +#define USBFS_DEVICE_DESCR_SN_SHIFT (16u) + +/* Config Descriptor Shifts and Masks */ +#define USBFS_CONFIG_DESCR_LENGTH (0u) +#define USBFS_CONFIG_DESCR_TYPE (1u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW (2u) +#define USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI (3u) +#define USBFS_CONFIG_DESCR_NUM_INTERFACES (4u) +#define USBFS_CONFIG_DESCR_CONFIG_VALUE (5u) +#define USBFS_CONFIG_DESCR_CONFIGURATION (6u) +#define USBFS_CONFIG_DESCR_ATTRIB (7u) +#define USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED (0x40u) +#define USBFS_CONFIG_DESCR_ATTRIB_RWU_EN (0x20u) + +/* Feature Selectors (Table 9-6) */ +#define USBFS_DEVICE_REMOTE_WAKEUP (0x01u) +#define USBFS_ENDPOINT_HALT (0x00u) +#define USBFS_TEST_MODE (0x02u) + +/* USB Device Status (Figure 9-4) */ +#define USBFS_DEVICE_STATUS_BUS_POWERED (0x00u) +#define USBFS_DEVICE_STATUS_SELF_POWERED (0x01u) +#define USBFS_DEVICE_STATUS_REMOTE_WAKEUP (0x02u) + +/* USB Endpoint Status (Figure 9-4) */ +#define USBFS_ENDPOINT_STATUS_HALT (0x01u) + +/* USB Endpoint Directions */ +#define USBFS_DIR_IN (0x80u) +#define USBFS_DIR_OUT (0x00u) +#define USBFS_DIR_UNUSED (0x7Fu) + +/* USB Endpoint Attributes */ +#define USBFS_EP_TYPE_CTRL (0x00u) +#define USBFS_EP_TYPE_ISOC (0x01u) +#define USBFS_EP_TYPE_BULK (0x02u) +#define USBFS_EP_TYPE_INT (0x03u) +#define USBFS_EP_TYPE_MASK (0x03u) + +#define USBFS_EP_SYNC_TYPE_NO_SYNC (0x00u) +#define USBFS_EP_SYNC_TYPE_ASYNC (0x04u) +#define USBFS_EP_SYNC_TYPE_ADAPTIVE (0x08u) +#define USBFS_EP_SYNC_TYPE_SYNCHRONOUS (0x0Cu) +#define USBFS_EP_SYNC_TYPE_MASK (0x0Cu) + +#define USBFS_EP_USAGE_TYPE_DATA (0x00u) +#define USBFS_EP_USAGE_TYPE_FEEDBACK (0x10u) +#define USBFS_EP_USAGE_TYPE_IMPLICIT (0x20u) +#define USBFS_EP_USAGE_TYPE_RESERVED (0x30u) +#define USBFS_EP_USAGE_TYPE_MASK (0x30u) + +/* point Status defines */ +#define USBFS_EP_STATUS_LENGTH (0x02u) + +/* point Device defines */ +#define USBFS_DEVICE_STATUS_LENGTH (0x02u) + +#define USBFS_STATUS_LENGTH_MAX \ + ( (USBFS_EP_STATUS_LENGTH > USBFS_DEVICE_STATUS_LENGTH) ? \ + USBFS_EP_STATUS_LENGTH : USBFS_DEVICE_STATUS_LENGTH ) +/* Transfer Completion Notification */ +#define USBFS_XFER_IDLE (0x00u) +#define USBFS_XFER_STATUS_ACK (0x01u) +#define USBFS_XFER_PREMATURE (0x02u) +#define USBFS_XFER_ERROR (0x03u) + +/* Driver State defines */ +#define USBFS_TRANS_STATE_IDLE (0x00u) +#define USBFS_TRANS_STATE_CONTROL_READ (0x02u) +#define USBFS_TRANS_STATE_CONTROL_WRITE (0x04u) +#define USBFS_TRANS_STATE_NO_DATA_CONTROL (0x06u) + +/* String Descriptor defines */ +#define USBFS_STRING_MSOS (0xEEu) +#define USBFS_MSOS_DESCRIPTOR_LENGTH (18u) +#define USBFS_MSOS_CONF_DESCR_LENGTH (40u) + +#if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + /* DMA manual mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (0u) + #define USBFS_DMA_REQUEST_PER_BURST (0u) +#endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* DMA automatic mode defines */ + #define USBFS_DMA_BYTES_PER_BURST (32u) + #define USBFS_DMA_BYTES_REPEAT (2u) + /* BUF_SIZE-BYTES_PER_BURST examples: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + #define USBFS_DMA_BUF_SIZE (0x55u) + #define USBFS_DMA_REQUEST_PER_BURST (1u) + + #if(USBFS_DMA1_REMOVE == 0u) + #define USBFS_ep1_TD_TERMOUT_EN USBFS_ep1__TD_TERMOUT_EN + #else + #define USBFS_ep1_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA1_REMOVE == 0u */ + #if(USBFS_DMA2_REMOVE == 0u) + #define USBFS_ep2_TD_TERMOUT_EN USBFS_ep2__TD_TERMOUT_EN + #else + #define USBFS_ep2_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA2_REMOVE == 0u */ + #if(USBFS_DMA3_REMOVE == 0u) + #define USBFS_ep3_TD_TERMOUT_EN USBFS_ep3__TD_TERMOUT_EN + #else + #define USBFS_ep3_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA3_REMOVE == 0u */ + #if(USBFS_DMA4_REMOVE == 0u) + #define USBFS_ep4_TD_TERMOUT_EN USBFS_ep4__TD_TERMOUT_EN + #else + #define USBFS_ep4_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA4_REMOVE == 0u */ + #if(USBFS_DMA5_REMOVE == 0u) + #define USBFS_ep5_TD_TERMOUT_EN USBFS_ep5__TD_TERMOUT_EN + #else + #define USBFS_ep5_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA5_REMOVE == 0u */ + #if(USBFS_DMA6_REMOVE == 0u) + #define USBFS_ep6_TD_TERMOUT_EN USBFS_ep6__TD_TERMOUT_EN + #else + #define USBFS_ep6_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA6_REMOVE == 0u */ + #if(USBFS_DMA7_REMOVE == 0u) + #define USBFS_ep7_TD_TERMOUT_EN USBFS_ep7__TD_TERMOUT_EN + #else + #define USBFS_ep7_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA7_REMOVE == 0u */ + #if(USBFS_DMA8_REMOVE == 0u) + #define USBFS_ep8_TD_TERMOUT_EN USBFS_ep8__TD_TERMOUT_EN + #else + #define USBFS_ep8_TD_TERMOUT_EN (0u) + #endif /* USBFS_DMA8_REMOVE == 0u */ + + #define USBFS_EP17_SR_MASK (0x7fu) + #define USBFS_EP8_SR_MASK (0x03u) + +#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + +/* DIE ID string descriptor defines */ +#if defined(USBFS_ENABLE_IDSN_STRING) + #define USBFS_IDSN_DESCR_LENGTH (0x22u) +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/*************************************** +* External data references +***************************************/ + +extern uint8 USBFS_initVar; +extern volatile uint8 USBFS_device; +extern volatile uint8 USBFS_transferState; +extern volatile uint8 USBFS_configuration; +extern volatile uint8 USBFS_configurationChanged; +extern volatile uint8 USBFS_deviceStatus; + +/* HID Variables */ +#if defined(USBFS_ENABLE_HID_CLASS) + extern volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; + extern volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* Registers +***************************************/ + +#define USBFS_ARB_CFG_PTR ( (reg8 *) USBFS_USB__ARB_CFG) +#define USBFS_ARB_CFG_REG (* (reg8 *) USBFS_USB__ARB_CFG) + +#define USBFS_ARB_EP1_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP1_CFG) +#define USBFS_ARB_EP1_CFG_IND USBFS_USB__ARB_EP1_CFG +#define USBFS_ARB_EP1_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP1_INT_EN) +#define USBFS_ARB_EP1_INT_EN_IND USBFS_USB__ARB_EP1_INT_EN +#define USBFS_ARB_EP1_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_REG (* (reg8 *) USBFS_USB__ARB_EP1_SR) +#define USBFS_ARB_EP1_SR_IND USBFS_USB__ARB_EP1_SR + +#define USBFS_ARB_EP2_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP2_CFG) +#define USBFS_ARB_EP2_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP2_INT_EN) +#define USBFS_ARB_EP2_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP2_SR) +#define USBFS_ARB_EP2_SR_REG (* (reg8 *) USBFS_USB__ARB_EP2_SR) + +#define USBFS_ARB_EP3_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP3_CFG) +#define USBFS_ARB_EP3_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP3_INT_EN) +#define USBFS_ARB_EP3_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP3_SR) +#define USBFS_ARB_EP3_SR_REG (* (reg8 *) USBFS_USB__ARB_EP3_SR) + +#define USBFS_ARB_EP4_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP4_CFG) +#define USBFS_ARB_EP4_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP4_INT_EN) +#define USBFS_ARB_EP4_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP4_SR) +#define USBFS_ARB_EP4_SR_REG (* (reg8 *) USBFS_USB__ARB_EP4_SR) + +#define USBFS_ARB_EP5_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP5_CFG) +#define USBFS_ARB_EP5_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP5_INT_EN) +#define USBFS_ARB_EP5_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP5_SR) +#define USBFS_ARB_EP5_SR_REG (* (reg8 *) USBFS_USB__ARB_EP5_SR) + +#define USBFS_ARB_EP6_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP6_CFG) +#define USBFS_ARB_EP6_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP6_INT_EN) +#define USBFS_ARB_EP6_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP6_SR) +#define USBFS_ARB_EP6_SR_REG (* (reg8 *) USBFS_USB__ARB_EP6_SR) + +#define USBFS_ARB_EP7_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP7_CFG) +#define USBFS_ARB_EP7_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP7_INT_EN) +#define USBFS_ARB_EP7_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP7_SR) +#define USBFS_ARB_EP7_SR_REG (* (reg8 *) USBFS_USB__ARB_EP7_SR) + +#define USBFS_ARB_EP8_CFG_PTR ( (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_CFG_REG (* (reg8 *) USBFS_USB__ARB_EP8_CFG) +#define USBFS_ARB_EP8_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_EP8_INT_EN) +#define USBFS_ARB_EP8_SR_PTR ( (reg8 *) USBFS_USB__ARB_EP8_SR) +#define USBFS_ARB_EP8_SR_REG (* (reg8 *) USBFS_USB__ARB_EP8_SR) + +#define USBFS_ARB_INT_EN_PTR ( (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_EN_REG (* (reg8 *) USBFS_USB__ARB_INT_EN) +#define USBFS_ARB_INT_SR_PTR ( (reg8 *) USBFS_USB__ARB_INT_SR) +#define USBFS_ARB_INT_SR_REG (* (reg8 *) USBFS_USB__ARB_INT_SR) + +#define USBFS_ARB_RW1_DR_PTR ((reg8 *) USBFS_USB__ARB_RW1_DR) +#define USBFS_ARB_RW1_DR_IND USBFS_USB__ARB_RW1_DR +#define USBFS_ARB_RW1_RA_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA) +#define USBFS_ARB_RW1_RA_IND USBFS_USB__ARB_RW1_RA +#define USBFS_ARB_RW1_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_RA_MSB) +#define USBFS_ARB_RW1_RA_MSB_IND USBFS_USB__ARB_RW1_RA_MSB +#define USBFS_ARB_RW1_WA_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA) +#define USBFS_ARB_RW1_WA_IND USBFS_USB__ARB_RW1_WA +#define USBFS_ARB_RW1_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW1_WA_MSB) +#define USBFS_ARB_RW1_WA_MSB_IND USBFS_USB__ARB_RW1_WA_MSB + +#define USBFS_ARB_RW2_DR_PTR ((reg8 *) USBFS_USB__ARB_RW2_DR) +#define USBFS_ARB_RW2_RA_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA) +#define USBFS_ARB_RW2_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_RA_MSB) +#define USBFS_ARB_RW2_WA_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA) +#define USBFS_ARB_RW2_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW2_WA_MSB) + +#define USBFS_ARB_RW3_DR_PTR ((reg8 *) USBFS_USB__ARB_RW3_DR) +#define USBFS_ARB_RW3_RA_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA) +#define USBFS_ARB_RW3_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_RA_MSB) +#define USBFS_ARB_RW3_WA_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA) +#define USBFS_ARB_RW3_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW3_WA_MSB) + +#define USBFS_ARB_RW4_DR_PTR ((reg8 *) USBFS_USB__ARB_RW4_DR) +#define USBFS_ARB_RW4_RA_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA) +#define USBFS_ARB_RW4_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_RA_MSB) +#define USBFS_ARB_RW4_WA_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA) +#define USBFS_ARB_RW4_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW4_WA_MSB) + +#define USBFS_ARB_RW5_DR_PTR ((reg8 *) USBFS_USB__ARB_RW5_DR) +#define USBFS_ARB_RW5_RA_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA) +#define USBFS_ARB_RW5_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_RA_MSB) +#define USBFS_ARB_RW5_WA_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA) +#define USBFS_ARB_RW5_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW5_WA_MSB) + +#define USBFS_ARB_RW6_DR_PTR ((reg8 *) USBFS_USB__ARB_RW6_DR) +#define USBFS_ARB_RW6_RA_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA) +#define USBFS_ARB_RW6_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_RA_MSB) +#define USBFS_ARB_RW6_WA_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA) +#define USBFS_ARB_RW6_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW6_WA_MSB) + +#define USBFS_ARB_RW7_DR_PTR ((reg8 *) USBFS_USB__ARB_RW7_DR) +#define USBFS_ARB_RW7_RA_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA) +#define USBFS_ARB_RW7_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_RA_MSB) +#define USBFS_ARB_RW7_WA_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA) +#define USBFS_ARB_RW7_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW7_WA_MSB) + +#define USBFS_ARB_RW8_DR_PTR ((reg8 *) USBFS_USB__ARB_RW8_DR) +#define USBFS_ARB_RW8_RA_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA) +#define USBFS_ARB_RW8_RA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_RA_MSB) +#define USBFS_ARB_RW8_WA_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA) +#define USBFS_ARB_RW8_WA_MSB_PTR ((reg8 *) USBFS_USB__ARB_RW8_WA_MSB) + +#define USBFS_BUF_SIZE_PTR ( (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUF_SIZE_REG (* (reg8 *) USBFS_USB__BUF_SIZE) +#define USBFS_BUS_RST_CNT_PTR ( (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_BUS_RST_CNT_REG (* (reg8 *) USBFS_USB__BUS_RST_CNT) +#define USBFS_CWA_PTR ( (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_REG (* (reg8 *) USBFS_USB__CWA) +#define USBFS_CWA_MSB_PTR ( (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CWA_MSB_REG (* (reg8 *) USBFS_USB__CWA_MSB) +#define USBFS_CR0_PTR ( (reg8 *) USBFS_USB__CR0) +#define USBFS_CR0_REG (* (reg8 *) USBFS_USB__CR0) +#define USBFS_CR1_PTR ( (reg8 *) USBFS_USB__CR1) +#define USBFS_CR1_REG (* (reg8 *) USBFS_USB__CR1) + +#define USBFS_DMA_THRES_PTR ( (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_REG (* (reg8 *) USBFS_USB__DMA_THRES) +#define USBFS_DMA_THRES_MSB_PTR ( (reg8 *) USBFS_USB__DMA_THRES_MSB) +#define USBFS_DMA_THRES_MSB_REG (* (reg8 *) USBFS_USB__DMA_THRES_MSB) + +#define USBFS_EP_ACTIVE_PTR ( (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_ACTIVE_REG (* (reg8 *) USBFS_USB__EP_ACTIVE) +#define USBFS_EP_TYPE_PTR ( (reg8 *) USBFS_USB__EP_TYPE) +#define USBFS_EP_TYPE_REG (* (reg8 *) USBFS_USB__EP_TYPE) + +#define USBFS_EP0_CNT_PTR ( (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CNT_REG (* (reg8 *) USBFS_USB__EP0_CNT) +#define USBFS_EP0_CR_PTR ( (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_CR_REG (* (reg8 *) USBFS_USB__EP0_CR) +#define USBFS_EP0_DR0_PTR ( (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_REG (* (reg8 *) USBFS_USB__EP0_DR0) +#define USBFS_EP0_DR0_IND USBFS_USB__EP0_DR0 +#define USBFS_EP0_DR1_PTR ( (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR1_REG (* (reg8 *) USBFS_USB__EP0_DR1) +#define USBFS_EP0_DR2_PTR ( (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR2_REG (* (reg8 *) USBFS_USB__EP0_DR2) +#define USBFS_EP0_DR3_PTR ( (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR3_REG (* (reg8 *) USBFS_USB__EP0_DR3) +#define USBFS_EP0_DR4_PTR ( (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR4_REG (* (reg8 *) USBFS_USB__EP0_DR4) +#define USBFS_EP0_DR5_PTR ( (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR5_REG (* (reg8 *) USBFS_USB__EP0_DR5) +#define USBFS_EP0_DR6_PTR ( (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR6_REG (* (reg8 *) USBFS_USB__EP0_DR6) +#define USBFS_EP0_DR7_PTR ( (reg8 *) USBFS_USB__EP0_DR7) +#define USBFS_EP0_DR7_REG (* (reg8 *) USBFS_USB__EP0_DR7) + +#define USBFS_OSCLK_DR0_PTR ( (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR0_REG (* (reg8 *) USBFS_USB__OSCLK_DR0) +#define USBFS_OSCLK_DR1_PTR ( (reg8 *) USBFS_USB__OSCLK_DR1) +#define USBFS_OSCLK_DR1_REG (* (reg8 *) USBFS_USB__OSCLK_DR1) + +#define USBFS_PM_ACT_CFG_PTR ( (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_ACT_CFG_REG (* (reg8 *) USBFS_USB__PM_ACT_CFG) +#define USBFS_PM_STBY_CFG_PTR ( (reg8 *) USBFS_USB__PM_STBY_CFG) +#define USBFS_PM_STBY_CFG_REG (* (reg8 *) USBFS_USB__PM_STBY_CFG) + +#define USBFS_SIE_EP_INT_EN_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_EN_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_EN) +#define USBFS_SIE_EP_INT_SR_PTR ( (reg8 *) USBFS_USB__SIE_EP_INT_SR) +#define USBFS_SIE_EP_INT_SR_REG (* (reg8 *) USBFS_USB__SIE_EP_INT_SR) + +#define USBFS_SIE_EP1_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT0) +#define USBFS_SIE_EP1_CNT0_IND USBFS_USB__SIE_EP1_CNT0 +#define USBFS_SIE_EP1_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP1_CNT1) +#define USBFS_SIE_EP1_CNT1_IND USBFS_USB__SIE_EP1_CNT1 +#define USBFS_SIE_EP1_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP1_CR0) +#define USBFS_SIE_EP1_CR0_IND USBFS_USB__SIE_EP1_CR0 + +#define USBFS_SIE_EP2_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT0) +#define USBFS_SIE_EP2_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP2_CNT1) +#define USBFS_SIE_EP2_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP2_CR0) +#define USBFS_SIE_EP2_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP2_CR0) + +#define USBFS_SIE_EP3_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT0) +#define USBFS_SIE_EP3_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP3_CNT1) +#define USBFS_SIE_EP3_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP3_CR0) +#define USBFS_SIE_EP3_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP3_CR0) + +#define USBFS_SIE_EP4_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT0) +#define USBFS_SIE_EP4_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP4_CNT1) +#define USBFS_SIE_EP4_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP4_CR0) +#define USBFS_SIE_EP4_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP4_CR0) + +#define USBFS_SIE_EP5_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT0) +#define USBFS_SIE_EP5_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP5_CNT1) +#define USBFS_SIE_EP5_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP5_CR0) +#define USBFS_SIE_EP5_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP5_CR0) + +#define USBFS_SIE_EP6_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT0) +#define USBFS_SIE_EP6_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP6_CNT1) +#define USBFS_SIE_EP6_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP6_CR0) +#define USBFS_SIE_EP6_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP6_CR0) + +#define USBFS_SIE_EP7_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT0) +#define USBFS_SIE_EP7_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP7_CNT1) +#define USBFS_SIE_EP7_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP7_CR0) +#define USBFS_SIE_EP7_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP7_CR0) + +#define USBFS_SIE_EP8_CNT0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT0) +#define USBFS_SIE_EP8_CNT1_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CNT1_REG (* (reg8 *) USBFS_USB__SIE_EP8_CNT1) +#define USBFS_SIE_EP8_CR0_PTR ( (reg8 *) USBFS_USB__SIE_EP8_CR0) +#define USBFS_SIE_EP8_CR0_REG (* (reg8 *) USBFS_USB__SIE_EP8_CR0) + +#define USBFS_SOF0_PTR ( (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF0_REG (* (reg8 *) USBFS_USB__SOF0) +#define USBFS_SOF1_PTR ( (reg8 *) USBFS_USB__SOF1) +#define USBFS_SOF1_REG (* (reg8 *) USBFS_USB__SOF1) + +#define USBFS_USB_CLK_EN_PTR ( (reg8 *) USBFS_USB__USB_CLK_EN) +#define USBFS_USB_CLK_EN_REG (* (reg8 *) USBFS_USB__USB_CLK_EN) + +#define USBFS_USBIO_CR0_PTR ( (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR0_REG (* (reg8 *) USBFS_USB__USBIO_CR0) +#define USBFS_USBIO_CR1_PTR ( (reg8 *) USBFS_USB__USBIO_CR1) +#define USBFS_USBIO_CR1_REG (* (reg8 *) USBFS_USB__USBIO_CR1) +#if(!CY_PSOC5LP) + #define USBFS_USBIO_CR2_PTR ( (reg8 *) USBFS_USB__USBIO_CR2) + #define USBFS_USBIO_CR2_REG (* (reg8 *) USBFS_USB__USBIO_CR2) +#endif /* CY_PSOC5LP */ + +#define USBFS_DIE_ID CYDEV_FLSHID_CUST_TABLES_BASE + +#define USBFS_PM_USB_CR0_PTR ( (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_PM_USB_CR0_REG (* (reg8 *) CYREG_PM_USB_CR0) +#define USBFS_DYN_RECONFIG_PTR ( (reg8 *) USBFS_USB__DYN_RECONFIG) +#define USBFS_DYN_RECONFIG_REG (* (reg8 *) USBFS_USB__DYN_RECONFIG) + +#define USBFS_DM_INP_DIS_PTR ( (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DM_INP_DIS_REG (* (reg8 *) USBFS_Dm__INP_DIS) +#define USBFS_DP_INP_DIS_PTR ( (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INP_DIS_REG (* (reg8 *) USBFS_Dp__INP_DIS) +#define USBFS_DP_INTSTAT_PTR ( (reg8 *) USBFS_Dp__INTSTAT) +#define USBFS_DP_INTSTAT_REG (* (reg8 *) USBFS_Dp__INTSTAT) + +#if (USBFS_MON_VBUS == 1u) + #if (USBFS_EXTERN_VBUS == 0u) + #define USBFS_VBUS_DR_PTR ( (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_DR_REG (* (reg8 *) USBFS_VBUS__DR) + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_PS_REG (* (reg8 *) USBFS_VBUS__PS) + #define USBFS_VBUS_MASK USBFS_VBUS__MASK + #else + #define USBFS_VBUS_PS_PTR ( (reg8 *) USBFS_Vbus_ps_sts_sts_reg__STATUS_REG ) + #define USBFS_VBUS_MASK (0x01u) + #endif /* USBFS_EXTERN_VBUS == 0u */ +#endif /* USBFS_MON_VBUS */ + +/* Renamed Registers for backward compatibility. +* Should not be used in new designs. +*/ +#define USBFS_ARB_CFG USBFS_ARB_CFG_PTR + +#define USBFS_ARB_EP1_CFG USBFS_ARB_EP1_CFG_PTR +#define USBFS_ARB_EP1_INT_EN USBFS_ARB_EP1_INT_EN_PTR +#define USBFS_ARB_EP1_SR USBFS_ARB_EP1_SR_PTR + +#define USBFS_ARB_EP2_CFG USBFS_ARB_EP2_CFG_PTR +#define USBFS_ARB_EP2_INT_EN USBFS_ARB_EP2_INT_EN_PTR +#define USBFS_ARB_EP2_SR USBFS_ARB_EP2_SR_PTR + +#define USBFS_ARB_EP3_CFG USBFS_ARB_EP3_CFG_PTR +#define USBFS_ARB_EP3_INT_EN USBFS_ARB_EP3_INT_EN_PTR +#define USBFS_ARB_EP3_SR USBFS_ARB_EP3_SR_PTR + +#define USBFS_ARB_EP4_CFG USBFS_ARB_EP4_CFG_PTR +#define USBFS_ARB_EP4_INT_EN USBFS_ARB_EP4_INT_EN_PTR +#define USBFS_ARB_EP4_SR USBFS_ARB_EP4_SR_PTR + +#define USBFS_ARB_EP5_CFG USBFS_ARB_EP5_CFG_PTR +#define USBFS_ARB_EP5_INT_EN USBFS_ARB_EP5_INT_EN_PTR +#define USBFS_ARB_EP5_SR USBFS_ARB_EP5_SR_PTR + +#define USBFS_ARB_EP6_CFG USBFS_ARB_EP6_CFG_PTR +#define USBFS_ARB_EP6_INT_EN USBFS_ARB_EP6_INT_EN_PTR +#define USBFS_ARB_EP6_SR USBFS_ARB_EP6_SR_PTR + +#define USBFS_ARB_EP7_CFG USBFS_ARB_EP7_CFG_PTR +#define USBFS_ARB_EP7_INT_EN USBFS_ARB_EP7_INT_EN_PTR +#define USBFS_ARB_EP7_SR USBFS_ARB_EP7_SR_PTR + +#define USBFS_ARB_EP8_CFG USBFS_ARB_EP8_CFG_PTR +#define USBFS_ARB_EP8_INT_EN USBFS_ARB_EP8_INT_EN_PTR +#define USBFS_ARB_EP8_SR USBFS_ARB_EP8_SR_PTR + +#define USBFS_ARB_INT_EN USBFS_ARB_INT_EN_PTR +#define USBFS_ARB_INT_SR USBFS_ARB_INT_SR_PTR + +#define USBFS_ARB_RW1_DR USBFS_ARB_RW1_DR_PTR +#define USBFS_ARB_RW1_RA USBFS_ARB_RW1_RA_PTR +#define USBFS_ARB_RW1_RA_MSB USBFS_ARB_RW1_RA_MSB_PTR +#define USBFS_ARB_RW1_WA USBFS_ARB_RW1_WA_PTR +#define USBFS_ARB_RW1_WA_MSB USBFS_ARB_RW1_WA_MSB_PTR + +#define USBFS_ARB_RW2_DR USBFS_ARB_RW2_DR_PTR +#define USBFS_ARB_RW2_RA USBFS_ARB_RW2_RA_PTR +#define USBFS_ARB_RW2_RA_MSB USBFS_ARB_RW2_RA_MSB_PTR +#define USBFS_ARB_RW2_WA USBFS_ARB_RW2_WA_PTR +#define USBFS_ARB_RW2_WA_MSB USBFS_ARB_RW2_WA_MSB_PTR + +#define USBFS_ARB_RW3_DR USBFS_ARB_RW3_DR_PTR +#define USBFS_ARB_RW3_RA USBFS_ARB_RW3_RA_PTR +#define USBFS_ARB_RW3_RA_MSB USBFS_ARB_RW3_RA_MSB_PTR +#define USBFS_ARB_RW3_WA USBFS_ARB_RW3_WA_PTR +#define USBFS_ARB_RW3_WA_MSB USBFS_ARB_RW3_WA_MSB_PTR + +#define USBFS_ARB_RW4_DR USBFS_ARB_RW4_DR_PTR +#define USBFS_ARB_RW4_RA USBFS_ARB_RW4_RA_PTR +#define USBFS_ARB_RW4_RA_MSB USBFS_ARB_RW4_RA_MSB_PTR +#define USBFS_ARB_RW4_WA USBFS_ARB_RW4_WA_PTR +#define USBFS_ARB_RW4_WA_MSB USBFS_ARB_RW4_WA_MSB_PTR + +#define USBFS_ARB_RW5_DR USBFS_ARB_RW5_DR_PTR +#define USBFS_ARB_RW5_RA USBFS_ARB_RW5_RA_PTR +#define USBFS_ARB_RW5_RA_MSB USBFS_ARB_RW5_RA_MSB_PTR +#define USBFS_ARB_RW5_WA USBFS_ARB_RW5_WA_PTR +#define USBFS_ARB_RW5_WA_MSB USBFS_ARB_RW5_WA_MSB_PTR + +#define USBFS_ARB_RW6_DR USBFS_ARB_RW6_DR_PTR +#define USBFS_ARB_RW6_RA USBFS_ARB_RW6_RA_PTR +#define USBFS_ARB_RW6_RA_MSB USBFS_ARB_RW6_RA_MSB_PTR +#define USBFS_ARB_RW6_WA USBFS_ARB_RW6_WA_PTR +#define USBFS_ARB_RW6_WA_MSB USBFS_ARB_RW6_WA_MSB_PTR + +#define USBFS_ARB_RW7_DR USBFS_ARB_RW7_DR_PTR +#define USBFS_ARB_RW7_RA USBFS_ARB_RW7_RA_PTR +#define USBFS_ARB_RW7_RA_MSB USBFS_ARB_RW7_RA_MSB_PTR +#define USBFS_ARB_RW7_WA USBFS_ARB_RW7_WA_PTR +#define USBFS_ARB_RW7_WA_MSB USBFS_ARB_RW7_WA_MSB_PTR + +#define USBFS_ARB_RW8_DR USBFS_ARB_RW8_DR_PTR +#define USBFS_ARB_RW8_RA USBFS_ARB_RW8_RA_PTR +#define USBFS_ARB_RW8_RA_MSB USBFS_ARB_RW8_RA_MSB_PTR +#define USBFS_ARB_RW8_WA USBFS_ARB_RW8_WA_PTR +#define USBFS_ARB_RW8_WA_MSB USBFS_ARB_RW8_WA_MSB_PTR + +#define USBFS_BUF_SIZE USBFS_BUF_SIZE_PTR +#define USBFS_BUS_RST_CNT USBFS_BUS_RST_CNT_PTR +#define USBFS_CR0 USBFS_CR0_PTR +#define USBFS_CR1 USBFS_CR1_PTR +#define USBFS_CWA USBFS_CWA_PTR +#define USBFS_CWA_MSB USBFS_CWA_MSB_PTR + +#define USBFS_DMA_THRES USBFS_DMA_THRES_PTR +#define USBFS_DMA_THRES_MSB USBFS_DMA_THRES_MSB_PTR + +#define USBFS_EP_ACTIVE USBFS_EP_ACTIVE_PTR +#define USBFS_EP_TYPE USBFS_EP_TYPE_PTR + +#define USBFS_EP0_CNT USBFS_EP0_CNT_PTR +#define USBFS_EP0_CR USBFS_EP0_CR_PTR +#define USBFS_EP0_DR0 USBFS_EP0_DR0_PTR +#define USBFS_EP0_DR1 USBFS_EP0_DR1_PTR +#define USBFS_EP0_DR2 USBFS_EP0_DR2_PTR +#define USBFS_EP0_DR3 USBFS_EP0_DR3_PTR +#define USBFS_EP0_DR4 USBFS_EP0_DR4_PTR +#define USBFS_EP0_DR5 USBFS_EP0_DR5_PTR +#define USBFS_EP0_DR6 USBFS_EP0_DR6_PTR +#define USBFS_EP0_DR7 USBFS_EP0_DR7_PTR + +#define USBFS_OSCLK_DR0 USBFS_OSCLK_DR0_PTR +#define USBFS_OSCLK_DR1 USBFS_OSCLK_DR1_PTR + +#define USBFS_PM_ACT_CFG USBFS_PM_ACT_CFG_PTR +#define USBFS_PM_STBY_CFG USBFS_PM_STBY_CFG_PTR + +#define USBFS_SIE_EP_INT_EN USBFS_SIE_EP_INT_EN_PTR +#define USBFS_SIE_EP_INT_SR USBFS_SIE_EP_INT_SR_PTR + +#define USBFS_SIE_EP1_CNT0 USBFS_SIE_EP1_CNT0_PTR +#define USBFS_SIE_EP1_CNT1 USBFS_SIE_EP1_CNT1_PTR +#define USBFS_SIE_EP1_CR0 USBFS_SIE_EP1_CR0_PTR + +#define USBFS_SIE_EP2_CNT0 USBFS_SIE_EP2_CNT0_PTR +#define USBFS_SIE_EP2_CNT1 USBFS_SIE_EP2_CNT1_PTR +#define USBFS_SIE_EP2_CR0 USBFS_SIE_EP2_CR0_PTR + +#define USBFS_SIE_EP3_CNT0 USBFS_SIE_EP3_CNT0_PTR +#define USBFS_SIE_EP3_CNT1 USBFS_SIE_EP3_CNT1_PTR +#define USBFS_SIE_EP3_CR0 USBFS_SIE_EP3_CR0_PTR + +#define USBFS_SIE_EP4_CNT0 USBFS_SIE_EP4_CNT0_PTR +#define USBFS_SIE_EP4_CNT1 USBFS_SIE_EP4_CNT1_PTR +#define USBFS_SIE_EP4_CR0 USBFS_SIE_EP4_CR0_PTR + +#define USBFS_SIE_EP5_CNT0 USBFS_SIE_EP5_CNT0_PTR +#define USBFS_SIE_EP5_CNT1 USBFS_SIE_EP5_CNT1_PTR +#define USBFS_SIE_EP5_CR0 USBFS_SIE_EP5_CR0_PTR + +#define USBFS_SIE_EP6_CNT0 USBFS_SIE_EP6_CNT0_PTR +#define USBFS_SIE_EP6_CNT1 USBFS_SIE_EP6_CNT1_PTR +#define USBFS_SIE_EP6_CR0 USBFS_SIE_EP6_CR0_PTR + +#define USBFS_SIE_EP7_CNT0 USBFS_SIE_EP7_CNT0_PTR +#define USBFS_SIE_EP7_CNT1 USBFS_SIE_EP7_CNT1_PTR +#define USBFS_SIE_EP7_CR0 USBFS_SIE_EP7_CR0_PTR + +#define USBFS_SIE_EP8_CNT0 USBFS_SIE_EP8_CNT0_PTR +#define USBFS_SIE_EP8_CNT1 USBFS_SIE_EP8_CNT1_PTR +#define USBFS_SIE_EP8_CR0 USBFS_SIE_EP8_CR0_PTR + +#define USBFS_SOF0 USBFS_SOF0_PTR +#define USBFS_SOF1 USBFS_SOF1_PTR + +#define USBFS_USB_CLK_EN USBFS_USB_CLK_EN_PTR + +#define USBFS_USBIO_CR0 USBFS_USBIO_CR0_PTR +#define USBFS_USBIO_CR1 USBFS_USBIO_CR1_PTR +#define USBFS_USBIO_CR2 USBFS_USBIO_CR2_PTR + +#define USBFS_USB_MEM ((reg8 *) CYDEV_USB_MEM_BASE) + +#if(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_LEOPARD) + /* PSoC3 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_INTC_PRIOR0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_INTC_SET_EN0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_INTC_CLR_EN0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_INTC_VECT_MBASE) +#elif(CYDEV_CHIP_DIE_EXPECT == CYDEV_CHIP_DIE_PANTHER) + /* PSoC5 interrupt registers*/ + #define USBFS_USB_ISR_PRIOR ((reg8 *) CYDEV_NVIC_PRI_0) + #define USBFS_USB_ISR_SET_EN ((reg8 *) CYDEV_NVIC_SETENA0) + #define USBFS_USB_ISR_CLR_EN ((reg8 *) CYDEV_NVIC_CLRENA0) + #define USBFS_USB_ISR_VECT ((cyisraddress *) CYDEV_NVIC_VECT_OFFSET) +#endif /* CYDEV_CHIP_DIE_EXPECT */ + + +/*************************************** +* Interrupt vectors, masks and priorities +***************************************/ + +#define USBFS_BUS_RESET_PRIOR USBFS_bus_reset__INTC_PRIOR_NUM +#define USBFS_BUS_RESET_MASK USBFS_bus_reset__INTC_MASK +#define USBFS_BUS_RESET_VECT_NUM USBFS_bus_reset__INTC_NUMBER + +#define USBFS_SOF_PRIOR USBFS_sof_int__INTC_PRIOR_NUM +#define USBFS_SOF_MASK USBFS_sof_int__INTC_MASK +#define USBFS_SOF_VECT_NUM USBFS_sof_int__INTC_NUMBER + +#define USBFS_EP_0_PRIOR USBFS_ep_0__INTC_PRIOR_NUM +#define USBFS_EP_0_MASK USBFS_ep_0__INTC_MASK +#define USBFS_EP_0_VECT_NUM USBFS_ep_0__INTC_NUMBER + +#define USBFS_EP_1_PRIOR USBFS_ep_1__INTC_PRIOR_NUM +#define USBFS_EP_1_MASK USBFS_ep_1__INTC_MASK +#define USBFS_EP_1_VECT_NUM USBFS_ep_1__INTC_NUMBER + +#define USBFS_EP_2_PRIOR USBFS_ep_2__INTC_PRIOR_NUM +#define USBFS_EP_2_MASK USBFS_ep_2__INTC_MASK +#define USBFS_EP_2_VECT_NUM USBFS_ep_2__INTC_NUMBER + +#define USBFS_EP_3_PRIOR USBFS_ep_3__INTC_PRIOR_NUM +#define USBFS_EP_3_MASK USBFS_ep_3__INTC_MASK +#define USBFS_EP_3_VECT_NUM USBFS_ep_3__INTC_NUMBER + +#define USBFS_EP_4_PRIOR USBFS_ep_4__INTC_PRIOR_NUM +#define USBFS_EP_4_MASK USBFS_ep_4__INTC_MASK +#define USBFS_EP_4_VECT_NUM USBFS_ep_4__INTC_NUMBER + +#define USBFS_EP_5_PRIOR USBFS_ep_5__INTC_PRIOR_NUM +#define USBFS_EP_5_MASK USBFS_ep_5__INTC_MASK +#define USBFS_EP_5_VECT_NUM USBFS_ep_5__INTC_NUMBER + +#define USBFS_EP_6_PRIOR USBFS_ep_6__INTC_PRIOR_NUM +#define USBFS_EP_6_MASK USBFS_ep_6__INTC_MASK +#define USBFS_EP_6_VECT_NUM USBFS_ep_6__INTC_NUMBER + +#define USBFS_EP_7_PRIOR USBFS_ep_7__INTC_PRIOR_NUM +#define USBFS_EP_7_MASK USBFS_ep_7__INTC_MASK +#define USBFS_EP_7_VECT_NUM USBFS_ep_7__INTC_NUMBER + +#define USBFS_EP_8_PRIOR USBFS_ep_8__INTC_PRIOR_NUM +#define USBFS_EP_8_MASK USBFS_ep_8__INTC_MASK +#define USBFS_EP_8_VECT_NUM USBFS_ep_8__INTC_NUMBER + +#define USBFS_DP_INTC_PRIOR USBFS_dp_int__INTC_PRIOR_NUM +#define USBFS_DP_INTC_MASK USBFS_dp_int__INTC_MASK +#define USBFS_DP_INTC_VECT_NUM USBFS_dp_int__INTC_NUMBER + +/* ARB ISR should have higher priority from EP_X ISR, therefore it is defined to highest (0) */ +#define USBFS_ARB_PRIOR (0u) +#define USBFS_ARB_MASK USBFS_arb_int__INTC_MASK +#define USBFS_ARB_VECT_NUM USBFS_arb_int__INTC_NUMBER + +/*************************************** + * Endpoint 0 offsets (Table 9-2) + **************************************/ + +#define USBFS_bmRequestType USBFS_EP0_DR0_PTR +#define USBFS_bRequest USBFS_EP0_DR1_PTR +#define USBFS_wValue USBFS_EP0_DR2_PTR +#define USBFS_wValueHi USBFS_EP0_DR3_PTR +#define USBFS_wValueLo USBFS_EP0_DR2_PTR +#define USBFS_wIndex USBFS_EP0_DR4_PTR +#define USBFS_wIndexHi USBFS_EP0_DR5_PTR +#define USBFS_wIndexLo USBFS_EP0_DR4_PTR +#define USBFS_length USBFS_EP0_DR6_PTR +#define USBFS_lengthHi USBFS_EP0_DR7_PTR +#define USBFS_lengthLo USBFS_EP0_DR6_PTR + + +/*************************************** +* Register Constants +***************************************/ +#define USBFS_VDDD_MV CYDEV_VDDD_MV +#define USBFS_3500MV (3500u) + +#define USBFS_CR1_REG_ENABLE (0x01u) +#define USBFS_CR1_ENABLE_LOCK (0x02u) +#define USBFS_CR1_BUS_ACTIVITY_SHIFT (0x02u) +#define USBFS_CR1_BUS_ACTIVITY ((uint8)(0x01u << USBFS_CR1_BUS_ACTIVITY_SHIFT)) +#define USBFS_CR1_TRIM_MSB_EN (0x08u) + +#define USBFS_EP0_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT_DATA_TOGGLE (0x80u) +#define USBFS_EPX_CNT0_MASK (0x0Fu) +#define USBFS_EPX_CNTX_MSB_MASK (0x07u) +#define USBFS_EPX_CNTX_ADDR_SHIFT (0x04u) +#define USBFS_EPX_CNTX_ADDR_OFFSET (0x10u) +#define USBFS_EPX_CNTX_CRC_COUNT (0x02u) +#define USBFS_EPX_DATA_BUF_MAX (512u) + +#define USBFS_CR0_ENABLE (0x80u) + +/* A 100 KHz clock is used for BUS reset count. Recommended is to count 10 pulses */ +#define USBFS_BUS_RST_COUNT (0x0au) + +#define USBFS_USBIO_CR1_IOMODE (0x20u) +#define USBFS_USBIO_CR1_USBPUEN (0x04u) +#define USBFS_USBIO_CR1_DP0 (0x02u) +#define USBFS_USBIO_CR1_DM0 (0x01u) + +#define USBFS_USBIO_CR0_TEN (0x80u) +#define USBFS_USBIO_CR0_TSE0 (0x40u) +#define USBFS_USBIO_CR0_TD (0x20u) +#define USBFS_USBIO_CR0_RD (0x01u) + +#define USBFS_FASTCLK_IMO_CR_USBCLK_ON (0x40u) +#define USBFS_FASTCLK_IMO_CR_XCLKEN (0x20u) +#define USBFS_FASTCLK_IMO_CR_FX2ON (0x10u) + +#define USBFS_ARB_EPX_CFG_RESET (0x08u) +#define USBFS_ARB_EPX_CFG_CRC_BYPASS (0x04u) +#define USBFS_ARB_EPX_CFG_DMA_REQ (0x02u) +#define USBFS_ARB_EPX_CFG_IN_DATA_RDY (0x01u) +#define USBFS_ARB_EPX_CFG_DEFAULT (USBFS_ARB_EPX_CFG_RESET | \ + USBFS_ARB_EPX_CFG_CRC_BYPASS) + +#define USBFS_ARB_EPX_SR_IN_BUF_FULL (0x01u) +#define USBFS_ARB_EPX_SR_DMA_GNT (0x02u) +#define USBFS_ARB_EPX_SR_BUF_OVER (0x04u) +#define USBFS_ARB_EPX_SR_BUF_UNDER (0x08u) + +#define USBFS_ARB_CFG_AUTO_MEM (0x10u) +#define USBFS_ARB_CFG_MANUAL_DMA (0x20u) +#define USBFS_ARB_CFG_AUTO_DMA (0x40u) +#define USBFS_ARB_CFG_CFG_CPM (0x80u) + +#if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #define USBFS_ARB_EPX_INT_MASK (0x1Du) +#else + #define USBFS_ARB_EPX_INT_MASK (0x1Fu) +#endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ +#define USBFS_ARB_INT_MASK (uint8)((USBFS_DMA1_REMOVE ^ 1u) | \ + (uint8)((USBFS_DMA2_REMOVE ^ 1u) << 1u) | \ + (uint8)((USBFS_DMA3_REMOVE ^ 1u) << 2u) | \ + (uint8)((USBFS_DMA4_REMOVE ^ 1u) << 3u) | \ + (uint8)((USBFS_DMA5_REMOVE ^ 1u) << 4u) | \ + (uint8)((USBFS_DMA6_REMOVE ^ 1u) << 5u) | \ + (uint8)((USBFS_DMA7_REMOVE ^ 1u) << 6u) | \ + (uint8)((USBFS_DMA8_REMOVE ^ 1u) << 7u) ) + +#define USBFS_SIE_EP_INT_EP1_MASK (0x01u) +#define USBFS_SIE_EP_INT_EP2_MASK (0x02u) +#define USBFS_SIE_EP_INT_EP3_MASK (0x04u) +#define USBFS_SIE_EP_INT_EP4_MASK (0x08u) +#define USBFS_SIE_EP_INT_EP5_MASK (0x10u) +#define USBFS_SIE_EP_INT_EP6_MASK (0x20u) +#define USBFS_SIE_EP_INT_EP7_MASK (0x40u) +#define USBFS_SIE_EP_INT_EP8_MASK (0x80u) + +#define USBFS_PM_ACT_EN_FSUSB USBFS_USB__PM_ACT_MSK +#define USBFS_PM_STBY_EN_FSUSB USBFS_USB__PM_STBY_MSK +#define USBFS_PM_AVAIL_EN_FSUSBIO (0x10u) + +#define USBFS_PM_USB_CR0_REF_EN (0x01u) +#define USBFS_PM_USB_CR0_PD_N (0x02u) +#define USBFS_PM_USB_CR0_PD_PULLUP_N (0x04u) + +#define USBFS_USB_CLK_ENABLE (0x01u) + +#define USBFS_DM_MASK USBFS_Dm__0__MASK +#define USBFS_DP_MASK USBFS_Dp__0__MASK + +#define USBFS_DYN_RECONFIG_ENABLE (0x01u) +#define USBFS_DYN_RECONFIG_EP_SHIFT (0x01u) +#define USBFS_DYN_RECONFIG_RDY_STS (0x10u) + + +#endif /* CY_USBFS_USBFS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c new file mode 100644 index 0000000..3840625 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.c @@ -0,0 +1,146 @@ +/******************************************************************************* +* File Name: USBFS_Dm.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dm.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dm_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dm_DR & (uint8)(~USBFS_Dm_MASK)); + USBFS_Dm_DR = staticBits | ((uint8)(value << USBFS_Dm_SHIFT) & USBFS_Dm_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* USBFS_Dm_DM_STRONG Strong Drive +* USBFS_Dm_DM_OD_HI Open Drain, Drives High +* USBFS_Dm_DM_OD_LO Open Drain, Drives Low +* USBFS_Dm_DM_RES_UP Resistive Pull Up +* USBFS_Dm_DM_RES_DWN Resistive Pull Down +* USBFS_Dm_DM_RES_UPDWN Resistive Pull Up/Down +* USBFS_Dm_DM_DIG_HIZ High Impedance Digital +* USBFS_Dm_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dm_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dm_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dm_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dm_Read(void) +{ + return (USBFS_Dm_PS & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dm_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dm_ReadDataReg(void) +{ + return (USBFS_Dm_DR & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dm_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dm_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dm_ClearInterrupt(void) + { + return (USBFS_Dm_INTSTAT & USBFS_Dm_MASK) >> USBFS_Dm_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h new file mode 100644 index 0000000..42e93ad --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_H) /* Pins USBFS_Dm_H */ +#define CY_PINS_USBFS_Dm_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dm_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dm__PORT == 15 && ((USBFS_Dm__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dm_Write(uint8 value) ; +void USBFS_Dm_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dm_ReadDataReg(void) ; +uint8 USBFS_Dm_Read(void) ; +uint8 USBFS_Dm_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dm_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dm_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dm_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dm_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dm_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dm_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dm_DM_STRONG PIN_DM_STRONG +#define USBFS_Dm_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dm_MASK USBFS_Dm__MASK +#define USBFS_Dm_SHIFT USBFS_Dm__SHIFT +#define USBFS_Dm_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dm_PS (* (reg8 *) USBFS_Dm__PS) +/* Data Register */ +#define USBFS_Dm_DR (* (reg8 *) USBFS_Dm__DR) +/* Port Number */ +#define USBFS_Dm_PRT_NUM (* (reg8 *) USBFS_Dm__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dm_AG (* (reg8 *) USBFS_Dm__AG) +/* Analog MUX bux enable */ +#define USBFS_Dm_AMUX (* (reg8 *) USBFS_Dm__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dm_BIE (* (reg8 *) USBFS_Dm__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dm_BIT_MASK (* (reg8 *) USBFS_Dm__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dm_BYP (* (reg8 *) USBFS_Dm__BYP) +/* Port wide control signals */ +#define USBFS_Dm_CTL (* (reg8 *) USBFS_Dm__CTL) +/* Drive Modes */ +#define USBFS_Dm_DM0 (* (reg8 *) USBFS_Dm__DM0) +#define USBFS_Dm_DM1 (* (reg8 *) USBFS_Dm__DM1) +#define USBFS_Dm_DM2 (* (reg8 *) USBFS_Dm__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dm_INP_DIS (* (reg8 *) USBFS_Dm__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dm_LCD_COM_SEG (* (reg8 *) USBFS_Dm__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dm_LCD_EN (* (reg8 *) USBFS_Dm__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dm_SLW (* (reg8 *) USBFS_Dm__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dm_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dm__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dm_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dm__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dm_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL0) +#define USBFS_Dm_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dm_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL0) +#define USBFS_Dm_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dm__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dm_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dm__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dm__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dm_INTSTAT (* (reg8 *) USBFS_Dm__INTSTAT) + #define USBFS_Dm_SNAP (* (reg8 *) USBFS_Dm__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dm_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h new file mode 100644 index 0000000..2f64935 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dm_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dm.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dm_ALIASES_H) /* Pins USBFS_Dm_ALIASES_H */ +#define CY_PINS_USBFS_Dm_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dm_0 (USBFS_Dm__0__PC) + +#endif /* End Pins USBFS_Dm_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c new file mode 100644 index 0000000..6f4efef --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.c @@ -0,0 +1,146 @@ +/******************************************************************************* +* File Name: USBFS_Dp.c +* Version 2.10 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "USBFS_Dp.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: USBFS_Dp_Write +******************************************************************************** +* +* Summary: +* Assign a new value to the digital port's data output register. +* +* Parameters: +* prtValue: The value to be assigned to the Digital Port. +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_Write(uint8 value) +{ + uint8 staticBits = (USBFS_Dp_DR & (uint8)(~USBFS_Dp_MASK)); + USBFS_Dp_DR = staticBits | ((uint8)(value << USBFS_Dp_SHIFT) & USBFS_Dp_MASK); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_SetDriveMode +******************************************************************************** +* +* Summary: +* Change the drive mode on the pins of the port. +* +* Parameters: +* mode: Change the pins to one of the following drive modes. +* +* USBFS_Dp_DM_STRONG Strong Drive +* USBFS_Dp_DM_OD_HI Open Drain, Drives High +* USBFS_Dp_DM_OD_LO Open Drain, Drives Low +* USBFS_Dp_DM_RES_UP Resistive Pull Up +* USBFS_Dp_DM_RES_DWN Resistive Pull Down +* USBFS_Dp_DM_RES_UPDWN Resistive Pull Up/Down +* USBFS_Dp_DM_DIG_HIZ High Impedance Digital +* USBFS_Dp_DM_ALG_HIZ High Impedance Analog +* +* Return: +* None +* +*******************************************************************************/ +void USBFS_Dp_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(USBFS_Dp_0, mode); +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_Read +******************************************************************************** +* +* Summary: +* Read the current value on the pins of the Digital Port in right justified +* form. +* +* Parameters: +* None +* +* Return: +* Returns the current value of the Digital Port as a right justified number +* +* Note: +* Macro USBFS_Dp_ReadPS calls this function. +* +*******************************************************************************/ +uint8 USBFS_Dp_Read(void) +{ + return (USBFS_Dp_PS & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/******************************************************************************* +* Function Name: USBFS_Dp_ReadDataReg +******************************************************************************** +* +* Summary: +* Read the current value assigned to a Digital Port's data output register +* +* Parameters: +* None +* +* Return: +* Returns the current value assigned to the Digital Port's data output register +* +*******************************************************************************/ +uint8 USBFS_Dp_ReadDataReg(void) +{ + return (USBFS_Dp_DR & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; +} + + +/* If Interrupts Are Enabled for this Pins component */ +#if defined(USBFS_Dp_INTSTAT) + + /******************************************************************************* + * Function Name: USBFS_Dp_ClearInterrupt + ******************************************************************************** + * Summary: + * Clears any active interrupts attached to port and returns the value of the + * interrupt status register. + * + * Parameters: + * None + * + * Return: + * Returns the value of the interrupt status register + * + *******************************************************************************/ + uint8 USBFS_Dp_ClearInterrupt(void) + { + return (USBFS_Dp_INTSTAT & USBFS_Dp_MASK) >> USBFS_Dp_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h new file mode 100644 index 0000000..a367129 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp.h @@ -0,0 +1,130 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_H) /* Pins USBFS_Dp_H */ +#define CY_PINS_USBFS_Dp_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "USBFS_Dp_aliases.h" + +/* Check to see if required defines such as CY_PSOC5A are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5A) + #error Component cy_pins_v2_10 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5A) */ + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + USBFS_Dp__PORT == 15 && ((USBFS_Dp__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +void USBFS_Dp_Write(uint8 value) ; +void USBFS_Dp_SetDriveMode(uint8 mode) ; +uint8 USBFS_Dp_ReadDataReg(void) ; +uint8 USBFS_Dp_Read(void) ; +uint8 USBFS_Dp_ClearInterrupt(void) ; + + +/*************************************** +* API Constants +***************************************/ + +/* Drive Modes */ +#define USBFS_Dp_DM_ALG_HIZ PIN_DM_ALG_HIZ +#define USBFS_Dp_DM_DIG_HIZ PIN_DM_DIG_HIZ +#define USBFS_Dp_DM_RES_UP PIN_DM_RES_UP +#define USBFS_Dp_DM_RES_DWN PIN_DM_RES_DWN +#define USBFS_Dp_DM_OD_LO PIN_DM_OD_LO +#define USBFS_Dp_DM_OD_HI PIN_DM_OD_HI +#define USBFS_Dp_DM_STRONG PIN_DM_STRONG +#define USBFS_Dp_DM_RES_UPDWN PIN_DM_RES_UPDWN + +/* Digital Port Constants */ +#define USBFS_Dp_MASK USBFS_Dp__MASK +#define USBFS_Dp_SHIFT USBFS_Dp__SHIFT +#define USBFS_Dp_WIDTH 1u + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define USBFS_Dp_PS (* (reg8 *) USBFS_Dp__PS) +/* Data Register */ +#define USBFS_Dp_DR (* (reg8 *) USBFS_Dp__DR) +/* Port Number */ +#define USBFS_Dp_PRT_NUM (* (reg8 *) USBFS_Dp__PRT) +/* Connect to Analog Globals */ +#define USBFS_Dp_AG (* (reg8 *) USBFS_Dp__AG) +/* Analog MUX bux enable */ +#define USBFS_Dp_AMUX (* (reg8 *) USBFS_Dp__AMUX) +/* Bidirectional Enable */ +#define USBFS_Dp_BIE (* (reg8 *) USBFS_Dp__BIE) +/* Bit-mask for Aliased Register Access */ +#define USBFS_Dp_BIT_MASK (* (reg8 *) USBFS_Dp__BIT_MASK) +/* Bypass Enable */ +#define USBFS_Dp_BYP (* (reg8 *) USBFS_Dp__BYP) +/* Port wide control signals */ +#define USBFS_Dp_CTL (* (reg8 *) USBFS_Dp__CTL) +/* Drive Modes */ +#define USBFS_Dp_DM0 (* (reg8 *) USBFS_Dp__DM0) +#define USBFS_Dp_DM1 (* (reg8 *) USBFS_Dp__DM1) +#define USBFS_Dp_DM2 (* (reg8 *) USBFS_Dp__DM2) +/* Input Buffer Disable Override */ +#define USBFS_Dp_INP_DIS (* (reg8 *) USBFS_Dp__INP_DIS) +/* LCD Common or Segment Drive */ +#define USBFS_Dp_LCD_COM_SEG (* (reg8 *) USBFS_Dp__LCD_COM_SEG) +/* Enable Segment LCD */ +#define USBFS_Dp_LCD_EN (* (reg8 *) USBFS_Dp__LCD_EN) +/* Slew Rate Control */ +#define USBFS_Dp_SLW (* (reg8 *) USBFS_Dp__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define USBFS_Dp_PRTDSI__CAPS_SEL (* (reg8 *) USBFS_Dp__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define USBFS_Dp_PRTDSI__DBL_SYNC_IN (* (reg8 *) USBFS_Dp__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define USBFS_Dp_PRTDSI__OE_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL0) +#define USBFS_Dp_PRTDSI__OE_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define USBFS_Dp_PRTDSI__OUT_SEL0 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL0) +#define USBFS_Dp_PRTDSI__OUT_SEL1 (* (reg8 *) USBFS_Dp__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define USBFS_Dp_PRTDSI__SYNC_OUT (* (reg8 *) USBFS_Dp__PRTDSI__SYNC_OUT) + + +#if defined(USBFS_Dp__INTSTAT) /* Interrupt Registers */ + + #define USBFS_Dp_INTSTAT (* (reg8 *) USBFS_Dp__INTSTAT) + #define USBFS_Dp_SNAP (* (reg8 *) USBFS_Dp__SNAP) + +#endif /* Interrupt Registers */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_USBFS_Dp_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h new file mode 100644 index 0000000..fd69396 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_Dp_aliases.h @@ -0,0 +1,32 @@ +/******************************************************************************* +* File Name: USBFS_Dp.h +* Version 2.10 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_USBFS_Dp_ALIASES_H) /* Pins USBFS_Dp_ALIASES_H */ +#define CY_PINS_USBFS_Dp_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + + +/*************************************** +* Constants +***************************************/ +#define USBFS_Dp_0 (USBFS_Dp__0__PC) + +#endif /* End Pins USBFS_Dp_ALIASES_H */ + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c new file mode 100644 index 0000000..732a135 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.c @@ -0,0 +1,358 @@ +/******************************************************************************* +* File Name: USBFS_audio.c +* Version 2.80 +* +* Description: +* USB AUDIO Class request handler. +* +* Related Document: +* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + + +#if defined(USBFS_ENABLE_AUDIO_CLASS) + +#include "USBFS_audio.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if !defined(USER_SUPPLIED_AUDIO_HANDLER) + + +/*************************************** +* AUDIO Variables +***************************************/ + +#if defined(USBFS_ENABLE_AUDIO_STREAMING) + volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP][USBFS_SAMPLE_FREQ_LEN]; + volatile uint8 USBFS_frequencyChanged; + volatile uint8 USBFS_currentMute; + volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; + volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MIN_LSB, + USBFS_VOL_MIN_MSB}; + volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_MAX_LSB, + USBFS_VOL_MAX_MSB}; + volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN] = {USBFS_VOL_RES_LSB, + USBFS_VOL_RES_MSB}; +#endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchAUDIOClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_currentSampleFrequency: Contains the current audio Sample +* Frequency. It is set by the Host using SET_CUR request to the endpoint. +* USBFS_frequencyChanged: This variable is used as a flag for the +* user code, to be aware that Host has been sent request for changing +* Sample Frequency. Sample frequency will be sent on the next OUT +* transaction. It is contains endpoint address when set. The following +* code is recommended for detecting new Sample Frequency in main code: +* if((USBFS_frequencyChanged != 0) && +* (USBFS_transferState == USBFS_TRANS_STATE_IDLE)) +* { +* USBFS_frequencyChanged = 0; +* } +* USBFS_transferState variable is checked to be sure that +* transfer completes. +* USBFS_currentMute: Contains mute configuration set by Host. +* USBFS_currentVolume: Contains volume level set by Host. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchAUDIOClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 bmRequestType = CY_GET_REG8(USBFS_bmRequestType); + + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + uint8 epNumber; + epNumber = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + + if ((bmRequestType & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP) + { + /* Endpoint */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* point Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlRead(); + } + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_READ_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_READ_REQUESTS_CALLBACK */ + + break; + default: + break; + } + } + else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_CONTROL_GET_REQUEST_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_CONTROL_GET_REQUEST_CALLBACK */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlRead(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_GET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_GET_REQUEST_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_GET_REQUEST_CALLBACK */ + + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlRead(); + } + else + { + /* `#START OTHER_GET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_GET_CUR_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_GET_CUR_REQUESTS_CALLBACK */ + } + break; + case USBFS_GET_MIN: /* GET_MIN */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_minimumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_MAX: /* GET_MAX */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_maximumVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_GET_RES: /* GET_RES */ + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* Entity ID Control Selector is VOLUME, */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = &USBFS_resolutionVolume[0]; + requestHandled = USBFS_InitControlRead(); + } + break; + /* The contents of the status message is reserved for future use. + * For the time being, a null packet should be returned in the data stage of the + * control transfer, and the received null packet should be ACKed. + */ + case USBFS_GET_STAT: + USBFS_currentTD.wCount = 0u; + requestHandled = USBFS_InitControlWrite(); + + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_WRITE_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_WRITE_REQUESTS_CALLBACK */ + + break; + default: + break; + } + } + else + { /* USBFS_RQST_RCPT_OTHER */ + } + } + else + { + /* Control Write */ + if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_EP) + { + /* point */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_SAMPLING_FREQ_CONTROL) + { + /* point Control Selector is Sampling Frequency */ + USBFS_currentTD.wCount = USBFS_SAMPLE_FREQ_LEN; + USBFS_currentTD.pData = USBFS_currentSampleFrequency[epNumber]; + requestHandled = USBFS_InitControlWrite(); + USBFS_frequencyChanged = epNumber; + } + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_SAMPLING_FREQ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_SAMPLING_FREQ_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_SAMPLING_FREQ_REQUESTS_CALLBACK */ + + break; + default: + break; + } + } + else if((bmRequestType & USBFS_RQST_RCPT_MASK) == USBFS_RQST_RCPT_IFC) + { + /* Interface or Entity ID */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_CUR: + #if defined(USBFS_ENABLE_AUDIO_STREAMING) + if(CY_GET_REG8(USBFS_wValueHi) == USBFS_MUTE_CONTROL) + { + /* `#START MUTE_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_MUTE_SET_REQUEST_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_MUTE_SET_REQUEST_CALLBACK */ + + /* Entity ID Control Selector is MUTE */ + USBFS_currentTD.wCount = 1u; + USBFS_currentTD.pData = &USBFS_currentMute; + requestHandled = USBFS_InitControlWrite(); + } + else if(CY_GET_REG8(USBFS_wValueHi) == USBFS_VOLUME_CONTROL) + { + /* `#START VOLUME_CONTROL_SET_REQUEST` Place multi-channel handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK + USBFS_DispatchAUDIOClass_VOLUME_CONTROL_SET_REQUEST_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_VOLUME_CONTROL_SET_REQUEST_CALLBACK */ + + /* Entity ID Control Selector is VOLUME */ + USBFS_currentTD.wCount = USBFS_VOLUME_LEN; + USBFS_currentTD.pData = USBFS_currentVolume; + requestHandled = USBFS_InitControlWrite(); + } + else + { + /* `#START OTHER_SET_CUR_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_OTHER_SET_CUR_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_OTHER_SET_CUR_REQUESTS_CALLBACK */ + } + #endif /* USBFS_ENABLE_AUDIO_STREAMING */ + + /* `#START AUDIO_CONTROL_SEL_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK + USBFS_DispatchAUDIOClass_AUDIO_CONTROL_SEL_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_AUDIO_CLASS_AUDIO_CONTROL_SEL_REQUESTS_CALLBACK */ + + break; + default: + break; + } + } + else + { + /* USBFS_RQST_RCPT_OTHER */ + } + } + + return(requestHandled); +} + +#endif /* USER_SUPPLIED_AUDIO_HANDLER */ + + +/******************************************************************************* +* Additional user functions supporting AUDIO Requests +********************************************************************************/ + +/* `#START AUDIO_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_ENABLE_AUDIO_CLASS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h new file mode 100644 index 0000000..6aa9357 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_audio.h @@ -0,0 +1,98 @@ +/******************************************************************************* +* File Name: USBFS_audio.h +* Version 2.80 +* +* Description: +* Header File for the USBFS component. Contains prototypes and constant values. +* +* Related Document: +* Universal Serial Bus Device Class Definition for Audio Devices Release 1.0 +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_audio_H) +#define CY_USBFS_USBFS_audio_H + +#include "cytypes.h" + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CUSTOM_CONSTANTS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Constants for USBFS_audio API. +***************************************/ + +/* Audio Class-Specific Request Codes (AUDIO Table A-9) */ +#define USBFS_REQUEST_CODE_UNDEFINED (0x00u) +#define USBFS_SET_CUR (0x01u) +#define USBFS_GET_CUR (0x81u) +#define USBFS_SET_MIN (0x02u) +#define USBFS_GET_MIN (0x82u) +#define USBFS_SET_MAX (0x03u) +#define USBFS_GET_MAX (0x83u) +#define USBFS_SET_RES (0x04u) +#define USBFS_GET_RES (0x84u) +#define USBFS_SET_MEM (0x05u) +#define USBFS_GET_MEM (0x85u) +#define USBFS_GET_STAT (0xFFu) + +/* point Control Selectors (AUDIO Table A-19) */ +#define USBFS_EP_CONTROL_UNDEFINED (0x00u) +#define USBFS_SAMPLING_FREQ_CONTROL (0x01u) +#define USBFS_PITCH_CONTROL (0x02u) + +/* Feature Unit Control Selectors (AUDIO Table A-11) */ +#define USBFS_FU_CONTROL_UNDEFINED (0x00u) +#define USBFS_MUTE_CONTROL (0x01u) +#define USBFS_VOLUME_CONTROL (0x02u) +#define USBFS_BASS_CONTROL (0x03u) +#define USBFS_MID_CONTROL (0x04u) +#define USBFS_TREBLE_CONTROL (0x05u) +#define USBFS_GRAPHIC_EQUALIZER_CONTROL (0x06u) +#define USBFS_AUTOMATIC_GAIN_CONTROL (0x07u) +#define USBFS_DELAY_CONTROL (0x08u) +#define USBFS_BASS_BOOST_CONTROL (0x09u) +#define USBFS_LOUDNESS_CONTROL (0x0Au) + +#define USBFS_SAMPLE_FREQ_LEN (3u) +#define USBFS_VOLUME_LEN (2u) + +#if !defined(USER_SUPPLIED_DEFAULT_VOLUME_VALUE) + #define USBFS_VOL_MIN_MSB (0x80u) + #define USBFS_VOL_MIN_LSB (0x01u) + #define USBFS_VOL_MAX_MSB (0x7Fu) + #define USBFS_VOL_MAX_LSB (0xFFu) + #define USBFS_VOL_RES_MSB (0x00u) + #define USBFS_VOL_RES_LSB (0x01u) +#endif /* USER_SUPPLIED_DEFAULT_VOLUME_VALUE */ + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_currentSampleFrequency[USBFS_MAX_EP] + [USBFS_SAMPLE_FREQ_LEN]; +extern volatile uint8 USBFS_frequencyChanged; +extern volatile uint8 USBFS_currentMute; +extern volatile uint8 USBFS_currentVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_minimumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_maximumVolume[USBFS_VOLUME_LEN]; +extern volatile uint8 USBFS_resolutionVolume[USBFS_VOLUME_LEN]; + +#endif /* CY_USBFS_USBFS_audio_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c new file mode 100644 index 0000000..747b0b0 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_boot.c @@ -0,0 +1,256 @@ +/******************************************************************************* +* File Name: USBFS_boot.c +* Version 2.80 +* +* Description: +* Boot loader API for USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(CYDEV_BOOTLOADER_IO_COMP) && ((CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS) || \ + (CYDEV_BOOTLOADER_IO_COMP == CyBtldr_Custom_Interface)) + + +/*************************************** +* Bootloader Variables +***************************************/ + +static uint8 USBFS_started = 0u; + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStart +******************************************************************************** +* +* Summary: +* Starts the component and enables the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* This function starts the USB with 3V or 5V operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStart(void) +{ + CyGlobalIntEnable; /* Enable Global Interrupts */ + + /*Start USBFS Operation/device 0 and with 5V or 3V operation depend on Voltage Configuration in DWR */ + USBFS_Start(0u, USBFS_DWR_VDDD_OPERATION); + + /* USB component started, the correct enumeration will be checked in first Read operation */ + USBFS_started = 1u; +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommStop. +******************************************************************************** +* +* Summary: +* Disable the component and disable the interrupt. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_CyBtldrCommStop(void) +{ + USBFS_Stop(); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommReset. +******************************************************************************** +* +* Summary: +* Resets the receive and transmit communication Buffers. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +void USBFS_CyBtldrCommReset(void) +{ + USBFS_EnableOutEP(USBFS_BTLDR_OUT_EP); /* Enable the OUT endpoint */ +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommWrite. +******************************************************************************** +* +* Summary: +* Allows the caller to write data to the boot loader host. The function will +* handle polling to allow a block of data to be completely sent to the host +* device. +* +* Parameters: +* pData: A pointer to the block of data to send to the device +* size: The number of bytes to write. +* count: Pointer to an unsigned short variable to write the number of +* bytes actually written. +* timeOut: Number of units to wait before returning because of a timeout. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommWrite(const uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus retCode; + uint16 timeoutMs; + + timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */ + + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_BTLDR_IN_EP, pData, USBFS_BTLDR_SIZEOF_READ_BUFFER); + + /* Wait for the master to read it. */ + while ((USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) && + (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + if (USBFS_GetEPState(USBFS_BTLDR_IN_EP) == USBFS_IN_BUFFER_FULL) + { + retCode = CYRET_TIMEOUT; + } + else + { + *count = size; + retCode = CYRET_SUCCESS; + } + + return(retCode); +} + + +/******************************************************************************* +* Function Name: USBFS_CyBtldrCommRead. +******************************************************************************** +* +* Summary: +* Allows the caller to read data from the boot loader host. The function will +* handle polling to allow a block of data to be completely received from the +* host device. +* +* Parameters: +* pData: A pointer to the area to store the block of data received +* from the device. +* size: The number of bytes to read. +* count: Pointer to an unsigned short variable to write the number +* of bytes actually read. +* timeOut: Number of units to wait before returning because of a timeOut. +* Timeout is measured in 10s of ms. +* +* Return: +* Returns the value that best describes the problem. +* +* Reentrant: +* No +* +*******************************************************************************/ +cystatus USBFS_CyBtldrCommRead(uint8 pData[], uint16 size, uint16 *count, uint8 timeOut) CYSMALL + +{ + cystatus retCode; + uint16 timeoutMs; + + timeoutMs = ((uint16) 10u * timeOut); /* Convert from 10mS check to number 1mS checks */ + + if (size > USBFS_BTLDR_SIZEOF_WRITE_BUFFER) + { + size = USBFS_BTLDR_SIZEOF_WRITE_BUFFER; + } + + /* Wait on enumeration in first time */ + if (0u != USBFS_started) + { + /* Wait for Device to enumerate */ + while ((0u ==USBFS_GetConfiguration()) && (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + /* Enable first OUT, if enumeration complete */ + if (0u != USBFS_GetConfiguration()) + { + (void) USBFS_IsConfigurationChanged(); /* Clear configuration changes state status */ + USBFS_CyBtldrCommReset(); + USBFS_started = 0u; + } + } + else /* Check for configuration changes, has been done by Host */ + { + if (0u != USBFS_IsConfigurationChanged()) /* Host could send double SET_INTERFACE request or RESET */ + { + if (0u != USBFS_GetConfiguration()) /* Init OUT endpoints when device reconfigured */ + { + USBFS_CyBtldrCommReset(); + } + } + } + + timeoutMs = ((uint16) 10u * timeOut); /* Re-arm timeout */ + + /* Wait on next packet */ + while((USBFS_GetEPState(USBFS_BTLDR_OUT_EP) != USBFS_OUT_BUFFER_FULL) && \ + (0u != timeoutMs)) + { + CyDelay(USBFS_BTLDR_WAIT_1_MS); + timeoutMs--; + } + + /* OUT EP has completed */ + if (USBFS_GetEPState(USBFS_BTLDR_OUT_EP) == USBFS_OUT_BUFFER_FULL) + { + *count = USBFS_ReadOutEP(USBFS_BTLDR_OUT_EP, pData, size); + retCode = CYRET_SUCCESS; + } + else + { + *count = 0u; + retCode = CYRET_TIMEOUT; + } + + return(retCode); +} + +#endif /* CYDEV_BOOTLOADER_IO_COMP == CyBtldr_USBFS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c new file mode 100644 index 0000000..9e35fa5 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.c @@ -0,0 +1,760 @@ +/******************************************************************************* +* File Name: USBFS_cdc.c +* Version 2.80 +* +* Description: +* USB CDC class request handler. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_CDC_CLASS) + +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" + + + +/*************************************** +* CDC Variables +***************************************/ + +volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE] = +{ + 0x00u, 0xC2u, 0x01u, 0x00u, /* Data terminal rate 115200 */ + 0x00u, /* 1 Stop bit */ + 0x00u, /* None parity */ + 0x08u /* 8 data bits */ +}; +volatile uint8 USBFS_lineChanged; +volatile uint16 USBFS_lineControlBitmap; +volatile uint8 USBFS_cdc_data_in_ep; +volatile uint8 USBFS_cdc_data_out_ep; + + +/*************************************** +* Static Function Prototypes +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + static uint16 USBFS_StrLen(const char8 string[]) ; +#endif /* (USBFS_ENABLE_CDC_CLASS_API != 0u) */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START CDC_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchCDCClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches CDC class requests. +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Global variables: +* USBFS_lineCoding: Contains the current line coding structure. +* It is set by the Host using SET_LINE_CODING request and returned to the +* user code by the USBFS_GetDTERate(), USBFS_GetCharFormat(), +* USBFS_GetParityType(), USBFS_GetDataBits() APIs. +* USBFS_lineControlBitmap: Contains the current control signal +* bitmap. It is set by the Host using SET_CONTROL_LINE request and returned +* to the user code by the USBFS_GetLineControl() API. +* USBFS_lineChanged: This variable is used as a flag for the +* USBFS_IsLineChanged() API, to be aware that Host has been sent request +* for changing Line Coding or Control Bitmap. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchCDCClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_GET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + requestHandled = USBFS_InitControlRead(); + break; + + /* `#START CDC_READ_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK + USBFS_DispatchCDCClass_CDC_READ_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_READ_REQUESTS_CALLBACK */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == \ + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_CDC_SET_LINE_CODING: + USBFS_currentTD.count = USBFS_LINE_CODING_SIZE; + USBFS_currentTD.pData = USBFS_lineCoding; + USBFS_lineChanged |= USBFS_LINE_CODING_CHANGED; + requestHandled = USBFS_InitControlWrite(); + break; + + case USBFS_CDC_SET_CONTROL_LINE_STATE: + USBFS_lineControlBitmap = CY_GET_REG8(USBFS_wValueLo); + USBFS_lineChanged |= USBFS_LINE_CONTROL_CHANGED; + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + + /* `#START CDC_WRITE_REQUESTS` Place other request handler here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK + USBFS_DispatchCDCClass_CDC_WRITE_REQUESTS_Callback(); + #endif /* USBFS_DISPATCH_CDC_CLASS_CDC_WRITE_REQUESTS_CALLBACK */ + + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/*************************************** +* Optional CDC APIs +***************************************/ +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + + /******************************************************************************* + * Function Name: USBFS_CDC_Init + ******************************************************************************** + * + * Summary: + * This function initialize the CDC interface to be ready for the receive data + * from the PC. + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_lineChanged: Initialized to zero. + * USBFS_cdc_data_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_CDC_Init(void) + { + USBFS_lineChanged = 0u; + USBFS_EnableOutEP(USBFS_cdc_data_out_ep); + } + + + /******************************************************************************* + * Function Name: USBFS_PutData + ******************************************************************************** + * + * Summary: + * This function sends a specified number of bytes from the location specified + * by a pointer to the PC. The USBFS_CDCIsReady() function should be + * called before sending new data, to be sure that the previous data has + * finished sending. + * If the last sent packet is less than maximum packet size the USB transfer + * of this short packet will identify the end of the segment. If the last sent + * packet is exactly maximum packet size, it shall be followed by a zero-length + * packet (which is a short packet) to assure the end of segment is properly + * identified. To send zero-length packet, use USBFS_PutData() API + * with length parameter set to zero. + * + * Parameters: + * pData: pointer to the buffer containing data to be sent. + * length: Specifies the number of bytes to send from the pData + * buffer. Maximum length will be limited by the maximum packet + * size for the endpoint. Data will be lost if length is greater than Max + * Packet Size. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutData(const uint8* pData, uint16 length) + { + /* Limits length to maximum packet size for the EP */ + if(length > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) + { + /* Caution: Data will be lost if length is greater than Max Packet Length */ + length = USBFS_EP[USBFS_cdc_data_in_ep].bufferSize; + /* Halt CPU in debug mode */ + CYASSERT(0u != 0u); + } + USBFS_LoadInEP(USBFS_cdc_data_in_ep, pData, length); + } + + + /******************************************************************************* + * Function Name: USBFS_StrLen + ******************************************************************************** + * + * Summary: + * Calculates length of a null terminated string. + * + * Parameters: + * string: pointer to the string. + * + * Return: + * Length of the string + * + *******************************************************************************/ + static uint16 USBFS_StrLen(const char8 string[]) + { + uint16 len = 0u; + + while (string[len] != (char8)0) + { + len++; + } + + return (len); + } + + + /******************************************************************************* + * Function Name: USBFS_PutString + ******************************************************************************** + * + * Summary: + * This function sends a null terminated string to the PC. This function will + * block if there is not enough memory to place the whole string. It will block + * until the entire string has been written to the transmit buffer. + * The USBUART_CDCIsReady() function should be called before sending data with + * a new call to USBFS_PutString(), to be sure that the previous data + * has finished sending. + * + * Parameters: + * string: pointer to the string to be sent to the PC. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutString(const char8 string[]) + { + uint16 strLength; + uint16 sendLength; + uint16 bufIndex = 0u; + + /* Get length of the null terminated string */ + strLength = USBFS_StrLen(string); + do + { + /* Limits length to maximum packet size for the EP */ + sendLength = (strLength > USBFS_EP[USBFS_cdc_data_in_ep].bufferSize) ? + USBFS_EP[USBFS_cdc_data_in_ep].bufferSize : strLength; + /* Enable IN transfer */ + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)&string[bufIndex], sendLength); + strLength -= sendLength; + + /* If more data are present to send or full packet was sent */ + if((strLength > 0u) || (sendLength == USBFS_EP[USBFS_cdc_data_in_ep].bufferSize)) + { + bufIndex += sendLength; + /* Wait for the Host to read it. */ + while(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState == + USBFS_IN_BUFFER_FULL) + { + ; + } + /* If the last sent packet is exactly maximum packet size, + * it shall be followed by a zero-length packet to assure the + * end of segment is properly identified by the terminal. + */ + if(strLength == 0u) + { + USBFS_LoadInEP(USBFS_cdc_data_in_ep, NULL, 0u); + } + } + }while(strLength > 0u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutChar + ******************************************************************************** + * + * Summary: + * Writes a single character to the PC. + * + * Parameters: + * txDataByte: Character to be sent to the PC. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutChar(char8 txDataByte) + { + uint8 dataByte; + dataByte = (uint8)txDataByte; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, &dataByte, 1u); + } + + + /******************************************************************************* + * Function Name: USBFS_PutCRLF + ******************************************************************************** + * + * Summary: + * Sends a carriage return (0x0D) and line feed (0x0A) to the PC + * + * Parameters: + * None. + * + * Return: + * None. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used for sending + * data. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_PutCRLF(void) + { + const uint8 CYCODE txData[] = {0x0Du, 0x0Au}; + + USBFS_LoadInEP(USBFS_cdc_data_in_ep, (const uint8 *)txData, 2u); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCount + ******************************************************************************** + * + * Summary: + * This function returns the number of bytes that were received from the PC. + * The returned length value should be passed to USBFS_GetData() as + * a parameter to read all received data. If all of the received data is not + * read at one time by the USBFS_GetData() API, the unread data will + * be lost. + * + * Parameters: + * None. + * + * Return: + * Returns the number of received bytes. The maximum amount of received data at + * a time is limited by the maximum packet size for the endpoint. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint16 USBFS_GetCount(void) + { + uint16 bytesCount; + + if (USBFS_EP[USBFS_cdc_data_out_ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { + bytesCount = USBFS_GetEPCount(USBFS_cdc_data_out_ep); + } + else + { + bytesCount = 0u; + } + + return(bytesCount); + } + + + /******************************************************************************* + * Function Name: USBFS_DataIsReady + ******************************************************************************** + * + * Summary: + * Returns a nonzero value if the component received data or received + * zero-length packet. The USBFS_GetAll() or + * USBFS_GetData() API should be called to read data from the buffer + * and re-init OUT endpoint even when zero-length packet received. + * + * Parameters: + * None. + * + * Return: + * If the OUT packet received this function returns a nonzero value. + * Otherwise zero is returned. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_DataIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_out_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_CDCIsReady + ******************************************************************************** + * + * Summary: + * This function returns a nonzero value if the component is ready to send more + * data to the PC; otherwise, it returns zero. The function should be called + * before sending new data when using any of the following APIs: + * USBFS_PutData(),USBFS_PutString(), + * USBFS_PutChar or USBFS_PutCRLF(), + * to be sure that the previous data has finished sending. + * + * Parameters: + * None. + * + * Return: + * If the buffer can accept new data, this function returns a nonzero value. + * Otherwise, it returns zero. + * + * Global variables: + * USBFS_cdc_data_in_ep: CDC IN endpoint number used. + * + *******************************************************************************/ + uint8 USBFS_CDCIsReady(void) + { + return(USBFS_EP[USBFS_cdc_data_in_ep].apiEpState); + } + + + /******************************************************************************* + * Function Name: USBFS_GetData + ******************************************************************************** + * + * Summary: + * This function gets a specified number of bytes from the input buffer and + * places them in a data array specified by the passed pointer. + * The USBFS_DataIsReady() API should be called first, to be sure + * that data is received from the host. If all received data will not be read at + * once, the unread data will be lost. The USBFS_GetData() API should + * be called to get the number of bytes that were received. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * Length: Number of bytes to read into the data array from the RX buffer. + * Maximum length is limited by the the number of received bytes. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetData(uint8* pData, uint16 length) + { + return(USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, length)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetAll + ******************************************************************************** + * + * Summary: + * Gets all bytes of received data from the input buffer and places it into a + * specified data array. USBFS_DataIsReady() API should be called + * before, to be sure that data is received from the Host. + * + * Parameters: + * pData: Pointer to the data array where data will be placed. + * + * Return: + * Number of bytes received. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * USBFS_EP[].bufferSize: EP max packet size is used as a length + * to read all data from the EP buffer. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint16 USBFS_GetAll(uint8* pData) + { + return (USBFS_ReadOutEP(USBFS_cdc_data_out_ep, pData, + USBFS_EP[USBFS_cdc_data_out_ep].bufferSize)); + } + + + /******************************************************************************* + * Function Name: USBFS_GetChar + ******************************************************************************** + * + * Summary: + * This function reads one byte of received data from the buffer. If more than + * one byte has been received from the host, the rest of the data will be lost. + * + * Parameters: + * None. + * + * Return: + * Received one character. + * + * Global variables: + * USBFS_cdc_data_out_ep: CDC OUT endpoint number used. + * + * Reentrant: + * No. + * + *******************************************************************************/ + uint8 USBFS_GetChar(void) + { + uint8 rxData; + + (void) USBFS_ReadOutEP(USBFS_cdc_data_out_ep, &rxData, 1u); + + return(rxData); + } + + /******************************************************************************* + * Function Name: USBFS_IsLineChanged + ******************************************************************************** + * + * Summary: + * This function returns clear on read status of the line. It returns not zero + * value when the host sends updated coding or control information to the + * device. The USBFS_GetDTERate(), USBFS_GetCharFormat() + * or USBFS_GetParityType() or USBFS_GetDataBits() API + * should be called to read data coding information. + * The USBFS_GetLineControl() API should be called to read line + * control information. + * + * Parameters: + * None. + * + * Return: + * If SET_LINE_CODING or CDC_SET_CONTROL_LINE_STATE requests are received, it + * returns a nonzero value. Otherwise, it returns zero. + * + * Global variables: + * USBFS_transferState: it is checked to be sure then OUT data + * phase has been complete, and data written to the lineCoding or Control + * Bitmap buffer. + * USBFS_lineChanged: used as a flag to be aware that Host has been + * sent request for changing Line Coding or Control Bitmap. + * + *******************************************************************************/ + uint8 USBFS_IsLineChanged(void) + { + uint8 state = 0u; + + /* transferState is checked to be sure then OUT data phase has been complete */ + if(USBFS_transferState == USBFS_TRANS_STATE_IDLE) + { + if(USBFS_lineChanged != 0u) + { + state = USBFS_lineChanged; + USBFS_lineChanged = 0u; + } + } + + return(state); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDTERate + ******************************************************************************** + * + * Summary: + * Returns the data terminal rate set for this port in bits per second. + * + * Parameters: + * None. + * + * Return: + * Returns a uint32 value of the data rate in bits per second. + * + * Global variables: + * USBFS_lineCoding: First four bytes converted to uint32 + * depend on compiler, and returned as a data rate. + * + *******************************************************************************/ + uint32 USBFS_GetDTERate(void) + { + uint32 rate; + + rate = USBFS_lineCoding[USBFS_LINE_CODING_RATE + 3u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 2u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE + 1u]; + rate = (rate << 8u) | USBFS_lineCoding[USBFS_LINE_CODING_RATE]; + + return(rate); + } + + + /******************************************************************************* + * Function Name: USBFS_GetCharFormat + ******************************************************************************** + * + * Summary: + * Returns the number of stop bits. + * + * Parameters: + * None. + * + * Return: + * Returns the number of stop bits. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetCharFormat(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_STOP_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetParityType + ******************************************************************************** + * + * Summary: + * Returns the parity type for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the parity type. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetParityType(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_PARITY]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetDataBits + ******************************************************************************** + * + * Summary: + * Returns the number of data bits for the CDC port. + * + * Parameters: + * None. + * + * Return: + * Returns the number of data bits. + * The number of data bits can be 5, 6, 7, 8 or 16. + * + * Global variables: + * USBFS_lineCoding: used to get a parameter. + * + *******************************************************************************/ + uint8 USBFS_GetDataBits(void) + { + return(USBFS_lineCoding[USBFS_LINE_CODING_DATA_BITS]); + } + + + /******************************************************************************* + * Function Name: USBFS_GetLineControl + ******************************************************************************** + * + * Summary: + * Returns Line control bitmap. + * + * Parameters: + * None. + * + * Return: + * Returns Line control bitmap. + * + * Global variables: + * USBFS_lineControlBitmap: used to get a parameter. + * + *******************************************************************************/ + uint16 USBFS_GetLineControl(void) + { + return(USBFS_lineControlBitmap); + } + +#endif /* USBFS_ENABLE_CDC_CLASS_API*/ + + +/******************************************************************************* +* Additional user functions supporting CDC Requests +********************************************************************************/ + +/* `#START CDC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_ENABLE_CDC_CLASS*/ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h new file mode 100644 index 0000000..0b95f08 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.h @@ -0,0 +1,95 @@ +/******************************************************************************* +* File Name: USBFS_cdc.h +* Version 2.80 +* +* Description: +* Header File for the USBFS component. +* Contains CDC class prototypes and constant values. +* +* Related Document: +* Universal Serial Bus Class Definitions for Communication Devices Version 1.1 +* +******************************************************************************** +* Copyright 2012-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_cdc_H) +#define CY_USBFS_USBFS_cdc_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_cdc API. +***************************************/ + +#if (USBFS_ENABLE_CDC_CLASS_API != 0u) + void USBFS_CDC_Init(void) ; + void USBFS_PutData(const uint8* pData, uint16 length) ; + void USBFS_PutString(const char8 string[]) ; + void USBFS_PutChar(char8 txDataByte) ; + void USBFS_PutCRLF(void) ; + uint16 USBFS_GetCount(void) ; + uint8 USBFS_CDCIsReady(void) ; + uint8 USBFS_DataIsReady(void) ; + uint16 USBFS_GetData(uint8* pData, uint16 length) ; + uint16 USBFS_GetAll(uint8* pData) ; + uint8 USBFS_GetChar(void) ; + uint8 USBFS_IsLineChanged(void) ; + uint32 USBFS_GetDTERate(void) ; + uint8 USBFS_GetCharFormat(void) ; + uint8 USBFS_GetParityType(void) ; + uint8 USBFS_GetDataBits(void) ; + uint16 USBFS_GetLineControl(void) ; +#endif /* USBFS_ENABLE_CDC_CLASS_API */ + + +/*************************************** +* Constants for USBFS_cdc API. +***************************************/ + +/* CDC Class-Specific Request Codes (CDC ver 1.2 Table 19) */ +#define USBFS_CDC_SET_LINE_CODING (0x20u) +#define USBFS_CDC_GET_LINE_CODING (0x21u) +#define USBFS_CDC_SET_CONTROL_LINE_STATE (0x22u) + +#define USBFS_LINE_CODING_CHANGED (0x01u) +#define USBFS_LINE_CONTROL_CHANGED (0x02u) + +#define USBFS_1_STOPBIT (0x00u) +#define USBFS_1_5_STOPBITS (0x01u) +#define USBFS_2_STOPBITS (0x02u) + +#define USBFS_PARITY_NONE (0x00u) +#define USBFS_PARITY_ODD (0x01u) +#define USBFS_PARITY_EVEN (0x02u) +#define USBFS_PARITY_MARK (0x03u) +#define USBFS_PARITY_SPACE (0x04u) + +#define USBFS_LINE_CODING_SIZE (0x07u) +#define USBFS_LINE_CODING_RATE (0x00u) +#define USBFS_LINE_CODING_STOP_BITS (0x04u) +#define USBFS_LINE_CODING_PARITY (0x05u) +#define USBFS_LINE_CODING_DATA_BITS (0x06u) + +#define USBFS_LINE_CONTROL_DTR (0x01u) +#define USBFS_LINE_CONTROL_RTS (0x02u) + + +/*************************************** +* External data references +***************************************/ + +extern volatile uint8 USBFS_lineCoding[USBFS_LINE_CODING_SIZE]; +extern volatile uint8 USBFS_lineChanged; +extern volatile uint16 USBFS_lineControlBitmap; +extern volatile uint8 USBFS_cdc_data_in_ep; +extern volatile uint8 USBFS_cdc_data_out_ep; + +#endif /* CY_USBFS_USBFS_cdc_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf new file mode 100644 index 0000000..e1fa37f --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cdc.inf @@ -0,0 +1,122 @@ +;****************************************************************************** +; File Name: USBFS_cdc.inf +; Version 2.80 +; +; Description: +; Windows USB CDC setup file for USBUART Device. +; +;****************************************************************************** +; Copyright 2007-2014, Cypress Semiconductor Corporation. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;****************************************************************************** + +[Version] +Signature="$Windows NT$" +Class=Ports +ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} +Provider=%PROVIDER% +LayoutFile=layout.inf +DriverVer=03/05/2007,2.0.0000.0 + +[Manufacturer] +%MFGNAME%=DeviceList, NTx86, NTia64, NTamd64 + +[DestinationDirs] +DefaultDestDir=12 + +[SourceDisksFiles] + +[SourceDisksNames] + +[DeviceList.NTx86] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTia64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + +[DeviceList.NTamd64] +%DESCRIPTION%=DriverInstall, USB\VID_04B4&PID_F232 + + +;------------------------------------------------------------------------------ +; 32 bit section for Windows 2000/2003/XP/Vista +;------------------------------------------------------------------------------ + +[DriverInstall.NTx86] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTx86.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTx86.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTx86.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for Intel Itanium based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTia64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTia64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTia64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTia64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; 64 bit section for AMD64 and Intel EM64T based systems +;------------------------------------------------------------------------------ + +[DriverInstall.NTamd64] +include=mdmcpq.inf +CopyFiles=DriverCopyFiles +AddReg=DriverInstall.NTamd64.AddReg + +[DriverCopyFiles] +usbser.sys,,,0x20 + +[DriverInstall.NTamd64.AddReg] +HKR,,DevLoader,,*ntkern +HKR,,NTMPDriver,,usbser.sys +HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" + +[DriverInstall.NTamd64.Services] +AddService=usbser, 0x00000002, DriverService + +;------------------------------------------------------------------------------ +; +;------------------------------------------------------------------------------ + +[DriverService] +DisplayName=%SERVICE% +ServiceType=1 +StartType=3 +ErrorControl=1 +ServiceBinary=%12%\usbser.sys + +;------------------------------------------------------------------------------ +; String Definitions +;------------------------------------------------------------------------------ + +[Strings] +PROVIDER="Cypress" +MFGNAME="Cypress Semiconductor Corporation" +DESCRIPTION="Cypress USB UART" +SERVICE="USB UART" diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c new file mode 100644 index 0000000..13832cd --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_cls.c @@ -0,0 +1,112 @@ +/******************************************************************************* +* File Name: USBFS_cls.c +* Version 2.80 +* +* Description: +* USB Class request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if(USBFS_EXTERN_CLS == USBFS_FALSE) + +#include "USBFS_pvt.h" + + + +/*************************************** +* User Implemented Class Driver Declarations. +***************************************/ +/* `#START USER_DEFINED_CLASS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_DispatchClassRqst +******************************************************************************** +* Summary: +* This routine dispatches class specific requests depend on interface class. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber = 0u; + + switch(CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_IFC: /* Class-specific request directed to an interface */ + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); /* wIndexLo contain Interface number */ + break; + case USBFS_RQST_RCPT_EP: /* Class-specific request directed to the endpoint */ + /* Find related interface to the endpoint, wIndexLo contain EP number */ + interfaceNumber = USBFS_EP[CY_GET_REG8(USBFS_wIndexLo) & + USBFS_DIR_UNUSED].interface; + break; + default: /* RequestHandled is initialized as FALSE by default */ + break; + } + /* Handle Class request depend on interface type */ + switch(USBFS_interfaceClass[interfaceNumber]) + { + case USBFS_CLASS_HID: + #if defined(USBFS_ENABLE_HID_CLASS) + requestHandled = USBFS_DispatchHIDClassRqst(); + #endif /* USBFS_ENABLE_HID_CLASS */ + break; + case USBFS_CLASS_AUDIO: + #if defined(USBFS_ENABLE_AUDIO_CLASS) + requestHandled = USBFS_DispatchAUDIOClassRqst(); + #endif /* USBFS_CLASS_AUDIO */ + break; + case USBFS_CLASS_CDC: + #if defined(USBFS_ENABLE_CDC_CLASS) + requestHandled = USBFS_DispatchCDCClassRqst(); + #endif /* USBFS_ENABLE_CDC_CLASS */ + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + + /* `#START USER_DEFINED_CLASS_CODE` Place your Class request here */ + + /* `#END` */ + + #ifdef USBFS_DISPATCH_CLASS_RQST_CALLBACK + USBFS_DispatchClassRqst_Callback(); + #endif /* USBFS_DISPATCH_CLASS_RQST_CALLBACK */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Class Specific Requests +********************************************************************************/ + +/* `#START CLASS_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_CLS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c new file mode 100644 index 0000000..67c28b3 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_descr.c @@ -0,0 +1,322 @@ +/******************************************************************************* +* File Name: USBFS_descr.c +* Version 2.80 +* +* Description: +* USB descriptors and storage. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +/***************************************************************************** +* User supplied descriptors. If you want to specify your own descriptors, +* define USER_SUPPLIED_DESCRIPTORS below and add your descriptors. +*****************************************************************************/ +/* `#START USER_DESCRIPTORS_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* USB Customizer Generated Descriptors +***************************************/ + +#if !defined(USER_SUPPLIED_DESCRIPTORS) +/********************************************************************* +* Device Descriptors +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_DESCR[18u] = { +/* Descriptor Length */ 0x12u, +/* DescriptorType: DEVICE */ 0x01u, +/* bcdUSB (ver 2.0) */ 0x00u, 0x02u, +/* bDeviceClass */ 0x00u, +/* bDeviceSubClass */ 0x00u, +/* bDeviceProtocol */ 0x00u, +/* bMaxPacketSize0 */ 0x08u, +/* idVendor */ 0xB4u, 0x04u, +/* idProduct */ 0x1Du, 0xB7u, +/* bcdDevice */ 0x03u, 0x30u, +/* iManufacturer */ 0x01u, +/* iProduct */ 0x02u, +/* iSerialNumber */ 0x80u, +/* bNumConfigurations */ 0x01u +}; +/********************************************************************* +* Config Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u] = { +/* Config Descriptor Length */ 0x09u, +/* DescriptorType: CONFIG */ 0x02u, +/* wTotalLength */ 0x29u, 0x00u, +/* bNumInterfaces */ 0x01u, +/* bConfigurationValue */ 0x01u, +/* iConfiguration */ 0x00u, +/* bmAttributes */ 0x80u, +/* bMaxPower */ 0x00u, +/********************************************************************* +* Interface Descriptor +*********************************************************************/ +/* Interface Descriptor Length */ 0x09u, +/* DescriptorType: INTERFACE */ 0x04u, +/* bInterfaceNumber */ 0x00u, +/* bAlternateSetting */ 0x00u, +/* bNumEndpoints */ 0x02u, +/* bInterfaceClass */ 0x03u, +/* bInterfaceSubClass */ 0x00u, +/* bInterfaceProtocol */ 0x00u, +/* iInterface */ 0x02u, +/********************************************************************* +* HID Class Descriptor +*********************************************************************/ +/* HID Class Descriptor Length */ 0x09u, +/* DescriptorType: HID_CLASS */ 0x21u, +/* bcdHID */ 0x11u, 0x01u, +/* bCountryCode */ 0x00u, +/* bNumDescriptors */ 0x01u, +/* bDescriptorType */ 0x22u, +/* wDescriptorLength (LSB) */ USBFS_HID_RPT_1_SIZE_LSB, +/* wDescriptorLength (MSB) */ USBFS_HID_RPT_1_SIZE_MSB, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x01u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u, +/********************************************************************* +* Endpoint Descriptor +*********************************************************************/ +/* Endpoint Descriptor Length */ 0x07u, +/* DescriptorType: ENDPOINT */ 0x05u, +/* bEndpointAddress */ 0x82u, +/* bmAttributes */ 0x03u, +/* wMaxPacketSize */ 0x40u, 0x00u, +/* bInterval */ 0x01u +}; + +/********************************************************************* +* String Descriptor Table +*********************************************************************/ +const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u] = { +/********************************************************************* +* Language ID Descriptor +*********************************************************************/ +/* Descriptor Length */ 0x04u, +/* DescriptorType: STRING */ 0x03u, +/* Language Id */ 0x09u, 0x04u, +/********************************************************************* +* String Descriptor: "Cypress Semiconductor" +*********************************************************************/ +/* Descriptor Length */ 0x2Cu, +/* DescriptorType: STRING */ 0x03u, + (uint8)'C', 0u,(uint8)'y', 0u,(uint8)'p', 0u,(uint8)'r', 0u,(uint8)'e', 0u, + (uint8)'s', 0u,(uint8)'s', 0u,(uint8)' ', 0u,(uint8)'S', 0u,(uint8)'e', 0u, + (uint8)'m', 0u,(uint8)'i', 0u,(uint8)'c', 0u,(uint8)'o', 0u,(uint8)'n', 0u, + (uint8)'d', 0u,(uint8)'u', 0u,(uint8)'c', 0u,(uint8)'t', 0u,(uint8)'o', 0u, + (uint8)'r', 0u, +/********************************************************************* +* String Descriptor: "PSoC3 Bootloader" +*********************************************************************/ +/* Descriptor Length */ 0x22u, +/* DescriptorType: STRING */ 0x03u, + (uint8)'P', 0u,(uint8)'S', 0u,(uint8)'o', 0u,(uint8)'C', 0u,(uint8)'3', 0u, + (uint8)' ', 0u,(uint8)'B', 0u,(uint8)'o', 0u,(uint8)'o', 0u,(uint8)'t', 0u, + (uint8)'l', 0u,(uint8)'o', 0u,(uint8)'a', 0u,(uint8)'d', 0u,(uint8)'e', 0u, + (uint8)'r', 0u, +/*********************************************************************/ +/* Marks the end of the list. */ 0x00u}; +/*********************************************************************/ + +/********************************************************************* +* Serial Number String Descriptor +*********************************************************************/ +const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10] = { +/* Descriptor Length */ 0x0Au, +/* DescriptorType: STRING */ 0x03u, +(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'0', 0u,(uint8)'1', 0u +}; + +/********************************************************************* +* HID Report Descriptor: Generic HID +*********************************************************************/ +const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u] = { +/* Descriptor Size (Not part of descriptor)*/ USBFS_HID_RPT_1_SIZE_LSB, +USBFS_HID_RPT_1_SIZE_MSB, +/* USAGE_PAGE */ 0x05u, 0x01u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* COLLECTION */ 0xA1u, 0x00u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* OUTPUT */ 0x91u, 0x02u, +/* USAGE */ 0x09u, 0x00u, +/* LOGICAL_MINIMUM */ 0x15u, 0x00u, +/* LOGICAL_MAXIMUM */ 0x25u, 0xFFu, +/* REPORT_SIZE */ 0x75u, 0x08u, +/* REPORT_COUNT */ 0x95u, 0x40u, +/* INPUT */ 0x81u, 0x02u, +/* END_COLLECTION */ 0xC0u, +/* END_COLLECTION */ 0xC0u, +/*********************************************************************/ +/* End of the HID Report Descriptor */ 0x00u, 0x00u}; +/*********************************************************************/ + +#if !defined(USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE) +/********************************************************************* +* HID Input Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; + +/********************************************************************* +* HID Input Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB}, +}; +/********************************************************************* +* HID Output Report Storage +*********************************************************************/ +T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; + +/********************************************************************* +* HID Output Report TD Table +*********************************************************************/ +const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[0u], + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB}, +}; +/********************************************************************* +* HID Report Look Up Table This table has four entries: +* IN Report Table +* OUT Report Table +* Feature Report Table +* HID Report Descriptor +* HID Class Descriptor +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u] = { + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE}, + {0x00u, NULL}, + {0x01u, (const void *)&USBFS_HIDREPORT_DESCRIPTOR1[0]}, + {0x01u, (const void *)&USBFS_DEVICE0_CONFIGURATION0_DESCR[18]} +}; +#endif /* USER_DEFINE_USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_HID_RPT_STORAGE */ + +/********************************************************************* +* Interface Dispatch Table -- Points to the Class Dispatch Tables +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u] = { + {USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_COUNT, + &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE} +}; +/********************************************************************* +* Endpoint Setting Table -- This table contain the endpoint setting +* for each endpoint in the configuration. It +* contains the necessary information to +* configure the endpoint hardware for each +* interface and alternate setting. +*********************************************************************/ +const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u] = { +/* IFC ALT EPAddr bmAttr MaxPktSize Class ********************/ +{0x00u, 0x00u, 0x01u, 0x03u, 0x0040u, 0x03u}, +{0x00u, 0x00u, 0x82u, 0x03u, 0x0040u, 0x03u} +}; +const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u] = { +0x03u +}; +/********************************************************************* +* Config Dispatch Table -- Points to the Config Descriptor and each of +* and endpoint setup table and to each +* interface table if it specifies a USB Class +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u] = { + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_DESCR}, + {0x02u, &USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE}, + {0x00u, &USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS} +}; +/********************************************************************* +* Device Dispatch Table -- Points to the Device Descriptor and each of +* and Configuration Tables for this Device +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u] = { + {0x01u, &USBFS_DEVICE0_DESCR}, + {0x01u, &USBFS_DEVICE0_CONFIGURATION0_TABLE} +}; +/********************************************************************* +* Device Table -- Indexed by the device number. +*********************************************************************/ +const T_USBFS_LUT CYCODE USBFS_TABLE[1u] = { + {0x01u, &USBFS_DEVICE0_TABLE} +}; + +#endif /* USER_SUPPLIED_DESCRIPTORS */ + +#if defined(USBFS_ENABLE_MSOS_STRING) + + /****************************************************************************** + * USB Microsoft OS String Descriptor + * "MSFT" identifies a Microsoft host + * "100" specifies version 1.00 + * USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR becomes the bRequest value + * in a host vendor device/class request + ******************************************************************************/ + + const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH] = { + /* Descriptor Length */ 0x12u, + /* DescriptorType: STRING */ 0x03u, + /* qwSignature - "MSFT100" */ (uint8)'M', 0u, (uint8)'S', 0u, (uint8)'F', 0u, (uint8)'T', 0u, + (uint8)'1', 0u, (uint8)'0', 0u, (uint8)'0', 0u, + /* bMS_VendorCode: */ USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR, + /* bPad */ 0x00u + }; + + /* Extended Configuration Descriptor */ + + const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH] = { + /* Length of the descriptor 4 bytes */ 0x28u, 0x00u, 0x00u, 0x00u, + /* Version of the descriptor 2 bytes */ 0x00u, 0x01u, + /* wIndex - Fixed:INDEX_CONFIG_DESCRIPTOR */ 0x04u, 0x00u, + /* bCount - Count of device functions. */ 0x01u, + /* Reserved : 7 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + /* bFirstInterfaceNumber */ 0x00u, + /* Reserved */ 0x01u, + /* compatibleID - "CYUSB\0\0" */ (uint8)'C', (uint8)'Y', (uint8)'U', (uint8)'S', (uint8)'B', + 0x00u, 0x00u, 0x00u, + /* subcompatibleID - "00001\0\0" */ (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'0', (uint8)'1', + 0x00u, 0x00u, 0x00u, + /* Reserved : 6 bytes */ 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u + }; + +#endif /* USBFS_ENABLE_MSOS_STRING */ + +/* DIE ID string descriptor for 8 bytes ID */ +#if defined(USBFS_ENABLE_IDSN_STRING) + uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c new file mode 100644 index 0000000..37deb96 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_drv.c @@ -0,0 +1,788 @@ +/******************************************************************************* +* File Name: USBFS_drv.c +* Version 2.80 +* +* Description: +* Endpoint 0 Driver for the USBFS Component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + + +/*************************************** +* Global data allocation +***************************************/ + +volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +volatile uint8 USBFS_configuration; +volatile uint8 USBFS_interfaceNumber; +volatile uint8 USBFS_configurationChanged; +volatile uint8 USBFS_deviceAddress; +volatile uint8 USBFS_deviceStatus; +volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +volatile uint8 USBFS_device; +const uint8 CYCODE *USBFS_interfaceClass; + + +/*************************************** +* Local data allocation +***************************************/ + +volatile uint8 USBFS_ep0Toggle; +volatile uint8 USBFS_lastPacketSize; +volatile uint8 USBFS_transferState; +volatile T_USBFS_TD USBFS_currentTD; +volatile uint8 USBFS_ep0Mode; +volatile uint8 USBFS_ep0Count; +volatile uint16 USBFS_transferByteCount; + + +/******************************************************************************* +* Function Name: USBFS_ep_0_Interrupt +******************************************************************************** +* +* Summary: +* This Interrupt Service Routine handles Endpoint 0 (Control Pipe) traffic. +* It dispatches setup requests and handles the data and status stages. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_EP_0_ISR) +{ + uint8 bRegTemp; + uint8 modifyReg; + + #ifdef USBFS_EP_0_ISR_ENTRY_CALLBACK + USBFS_EP_0_ISR_EntryCallback(); + #endif /* USBFS_EP_0_ISR_ENTRY_CALLBACK */ + + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); + if ((bRegTemp & USBFS_MODE_ACKD) != 0u) + { + modifyReg = 1u; + if ((bRegTemp & USBFS_MODE_SETUP_RCVD) != 0u) + { + if((bRegTemp & USBFS_MODE_MASK) != USBFS_MODE_NAK_IN_OUT) + { + modifyReg = 0u; /* When mode not NAK_IN_OUT => invalid setup */ + } + else + { + USBFS_HandleSetup(); + if((USBFS_ep0Mode & USBFS_MODE_SETUP_RCVD) != 0u) + { + modifyReg = 0u; /* if SETUP bit set -> exit without modifying the mode */ + } + + } + } + else if ((bRegTemp & USBFS_MODE_IN_RCVD) != 0u) + { + USBFS_HandleIN(); + } + else if ((bRegTemp & USBFS_MODE_OUT_RCVD) != 0u) + { + USBFS_HandleOUT(); + } + else + { + modifyReg = 0u; + } + if(modifyReg != 0u) + { + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + if((bRegTemp & USBFS_MODE_SETUP_RCVD) == 0u) /* Check if SETUP bit is not set, otherwise exit */ + { + /* Update the count register */ + bRegTemp = USBFS_ep0Toggle | USBFS_ep0Count; + CY_SET_REG8(USBFS_EP0_CNT_PTR, bRegTemp); + if(bRegTemp == CY_GET_REG8(USBFS_EP0_CNT_PTR)) /* continue if writing was successful */ + { + do + { + modifyReg = USBFS_ep0Mode; /* Init temporary variable */ + /* Unlock registers */ + bRegTemp = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_SETUP_RCVD; + if(bRegTemp == 0u) /* Check if SETUP bit is not set */ + { + /* Set the Mode Register */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_ep0Mode); + /* Writing check */ + modifyReg = CY_GET_REG8(USBFS_EP0_CR_PTR) & USBFS_MODE_MASK; + } + }while(modifyReg != USBFS_ep0Mode); /* Repeat if writing was not successful */ + } + } + } + } + #ifdef USBFS_EP_0_ISR_EXIT_CALLBACK + USBFS_EP_0_ISR_ExitCallback(); + #endif /* USBFS_EP_0_ISR_EXIT_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: USBFS_HandleSetup +******************************************************************************** +* +* Summary: +* This Routine dispatches requests for the four USB request types +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleSetup(void) +{ + uint8 requestHandled; + + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* unlock registers */ + CY_SET_REG8(USBFS_EP0_CR_PTR, requestHandled); /* clear setup bit */ + requestHandled = CY_GET_REG8(USBFS_EP0_CR_PTR); /* reread register */ + if((requestHandled & USBFS_MODE_SETUP_RCVD) != 0u) + { + USBFS_ep0Mode = requestHandled; /* if SETUP bit set -> exit without modifying the mode */ + } + else + { + /* In case the previous transfer did not complete, close it out */ + USBFS_UpdateStatusBlock(USBFS_XFER_PREMATURE); + + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_TYPE_MASK) + { + case USBFS_RQST_TYPE_STD: + requestHandled = USBFS_HandleStandardRqst(); + break; + case USBFS_RQST_TYPE_CLS: + requestHandled = USBFS_DispatchClassRqst(); + break; + case USBFS_RQST_TYPE_VND: + requestHandled = USBFS_HandleVendorRqst(); + break; + default: + requestHandled = USBFS_FALSE; + break; + } + if (requestHandled == USBFS_FALSE) + { + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleIN +******************************************************************************** +* +* Summary: +* This routine handles EP0 IN transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleIN(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadDataStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteStatusStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + USBFS_NoDataControlStatusStage(); + break; + default: /* there are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_HandleOUT +******************************************************************************** +* +* Summary: +* This routine handles EP0 OUT transfers. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_HandleOUT(void) +{ + switch (USBFS_transferState) + { + case USBFS_TRANS_STATE_IDLE: + break; + case USBFS_TRANS_STATE_CONTROL_READ: + USBFS_ControlReadStatusStage(); + break; + case USBFS_TRANS_STATE_CONTROL_WRITE: + USBFS_ControlWriteDataStage(); + break; + case USBFS_TRANS_STATE_NO_DATA_CONTROL: + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_ERROR); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; + break; + default: /* There are no more states */ + break; + } +} + + +/******************************************************************************* +* Function Name: USBFS_LoadEP0 +******************************************************************************** +* +* Summary: +* This routine loads the EP0 data registers for OUT transfers. It uses the +* currentTD (previously initialized by the _InitControlWrite function and +* updated for each OUT transfer, and the bLastPacketSize) to determine how +* many uint8s to transfer on the current OUT. +* +* If the number of uint8s remaining is zero and the last transfer was full, +* we need to send a zero length packet. Otherwise we send the minimum +* of the control endpoint size (8) or remaining number of uint8s for the +* transaction. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded to the SIE memory in +* current packet. +* USBFS_lastPacketSize - remembers the USBFS_ep0Count value for the +* next packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_LoadEP0(void) +{ + uint8 ep0Count = 0u; + + /* Update the transfer byte count from the last transaction */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Now load the next transaction */ + while ((USBFS_currentTD.count > 0u) && (ep0Count < 8u)) + { + CY_SET_REG8((reg8 *)(USBFS_EP0_DR0_IND + ep0Count), *USBFS_currentTD.pData); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + ep0Count++; + USBFS_currentTD.count--; + } + /* Support zero-length packet*/ + if( (USBFS_lastPacketSize == 8u) || (ep0Count > 0u) ) + { + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + else + { + /* Expect Status Stage Out */ + USBFS_ep0Mode = USBFS_MODE_STATUS_OUT_ONLY; + /* Update the state (or stay the same) */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + } + + /* Save the packet size for next time */ + USBFS_lastPacketSize = ep0Count; + USBFS_ep0Count = ep0Count; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlRead +******************************************************************************** +* +* Summary: +* Initialize a control read transaction, usable to send data to the host. +* The following global variables should be initialized before this function +* called. To send zero length packet use InitZeroLengthControlTransfer +* function. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_currentTD.count - counts of data to be sent. +* USBFS_currentTD.pData - data pointer. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlRead(void) +{ + uint16 xferCount; + if(USBFS_currentTD.count == 0u) + { + (void) USBFS_InitZeroLengthControlTransfer(); + } + else + { + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the toggle, it gets updated in LoadEP */ + USBFS_ep0Toggle = 0u; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + USBFS_LoadEP0(); + } + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_InitZeroLengthControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a zero length data IN transfer. +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - prepare for mode register content. +* USBFS_transferState - set to TRANS_STATE_CONTROL_READ +* USBFS_ep0Count - cleared, means the zero-length packet. +* USBFS_lastPacketSize - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitZeroLengthControlTransfer(void) + +{ + /* Update the state */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_READ; + /* Set the data toggle */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Set the Mode Register */ + USBFS_ep0Mode = USBFS_MODE_ACK_IN_STATUS_OUT; + /* Save the packet size for next time */ + USBFS_lastPacketSize = 0u; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadDataStage(void) + +{ + USBFS_LoadEP0(); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlReadStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control read transfer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_USBFS_transferByteCount - updated with last packet size. +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlReadStatusStage(void) +{ + /* Update the transfer byte count */ + USBFS_transferByteCount += USBFS_lastPacketSize; + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitControlWrite +******************************************************************************** +* +* Summary: +* Initialize a control write transaction +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_USBFS_transferState - set to TRANS_STATE_CONTROL_WRITE +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitControlWrite(void) +{ + uint16 xferCount; + + /* Set up the state machine */ + USBFS_transferState = USBFS_TRANS_STATE_CONTROL_WRITE; + /* This might not be necessary */ + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + /* Initialize the Status Block */ + USBFS_InitializeStatusBlock(); + + xferCount = (((uint16)CY_GET_REG8(USBFS_lengthHi) << 8u) | (CY_GET_REG8(USBFS_lengthLo))); + + if (USBFS_currentTD.count > xferCount) + { + USBFS_currentTD.count = xferCount; + } + + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteDataStage +******************************************************************************** +* +* Summary: +* Handle the Data Stage of a control write transfer +* 1. Get the data (We assume the destination was validated previously) +* 2. Update the count and data toggle +* 3. Update the mode register for the next transaction +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferByteCount - Update the transfer byte count from the +* last transaction. +* USBFS_ep0Count - counts the data loaded from the SIE memory +* in current packet. +* USBFS_transferByteCount - sum of the previous bytes transferred +* on previous packets(sum of USBFS_lastPacketSize) +* USBFS_ep0Toggle - inverted +* USBFS_ep0Mode - set to MODE_ACK_OUT_STATUS_IN. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteDataStage(void) +{ + uint8 ep0Count; + uint8 regIndex = 0u; + + ep0Count = (CY_GET_REG8(USBFS_EP0_CNT_PTR) & USBFS_EPX_CNT0_MASK) - + USBFS_EPX_CNTX_CRC_COUNT; + + USBFS_transferByteCount += ep0Count; + + while ((USBFS_currentTD.count > 0u) && (ep0Count > 0u)) + { + *USBFS_currentTD.pData = CY_GET_REG8((reg8 *)(USBFS_EP0_DR0_IND + regIndex)); + USBFS_currentTD.pData = &USBFS_currentTD.pData[1u]; + regIndex++; + ep0Count--; + USBFS_currentTD.count--; + } + USBFS_ep0Count = ep0Count; + /* Update the data toggle */ + USBFS_ep0Toggle ^= USBFS_EP0_CNT_DATA_TOGGLE; + /* Expect Data or Status Stage */ + USBFS_ep0Mode = USBFS_MODE_ACK_OUT_STATUS_IN; +} + + +/******************************************************************************* +* Function Name: USBFS_ControlWriteStatusStage +******************************************************************************** +* +* Summary: +* Handle the Status Stage of a control write transfer +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ControlWriteStatusStage(void) +{ + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_InitNoDataControlTransfer +******************************************************************************** +* +* Summary: +* Initialize a no data control transfer +* +* Parameters: +* None. +* +* Return: +* requestHandled state. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_NO_DATA_CONTROL. +* USBFS_ep0Mode - set to MODE_STATUS_IN_ONLY. +* USBFS_ep0Count - cleared. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_InitNoDataControlTransfer(void) +{ + USBFS_transferState = USBFS_TRANS_STATE_NO_DATA_CONTROL; + USBFS_ep0Mode = USBFS_MODE_STATUS_IN_ONLY; + USBFS_ep0Toggle = USBFS_EP0_CNT_DATA_TOGGLE; + USBFS_ep0Count = 0u; + + return(USBFS_TRUE); +} + + +/******************************************************************************* +* Function Name: USBFS_NoDataControlStatusStage +******************************************************************************** +* Summary: +* Handle the Status Stage of a no data control transfer. +* +* SET_ADDRESS is special, since we need to receive the status stage with +* the old address. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_transferState - set to TRANS_STATE_IDLE. +* USBFS_ep0Mode - set to MODE_STALL_IN_OUT. +* USBFS_ep0Toggle - set to EP0_CNT_DATA_TOGGLE +* USBFS_deviceAddress - used to set new address and cleared +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_NoDataControlStatusStage(void) +{ + /* Change the USB address register if we got a SET_ADDRESS. */ + if (USBFS_deviceAddress != 0u) + { + CY_SET_REG8(USBFS_CR0_PTR, USBFS_deviceAddress | USBFS_CR0_ENABLE); + USBFS_deviceAddress = 0u; + } + /* Go Idle */ + USBFS_transferState = USBFS_TRANS_STATE_IDLE; + /* Update the completion block */ + USBFS_UpdateStatusBlock(USBFS_XFER_STATUS_ACK); + /* We expect no more data, so stall INs and OUTs */ + USBFS_ep0Mode = USBFS_MODE_STALL_IN_OUT; +} + + +/******************************************************************************* +* Function Name: USBFS_UpdateStatusBlock +******************************************************************************** +* +* Summary: +* Update the Completion Status Block for a Request. The block is updated +* with the completion code the USBFS_transferByteCount. The +* StatusBlock Pointer is set to NULL. +* +* Parameters: +* completionCode - status. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - updated by the +* completionCode parameter. +* USBFS_currentTD.pStatusBlock->length - updated. +* USBFS_currentTD.pStatusBlock - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_UpdateStatusBlock(uint8 completionCode) +{ + if (USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = completionCode; + USBFS_currentTD.pStatusBlock->length = USBFS_transferByteCount; + USBFS_currentTD.pStatusBlock = NULL; + } +} + + +/******************************************************************************* +* Function Name: USBFS_InitializeStatusBlock +******************************************************************************** +* +* Summary: +* Initialize the Completion Status Block for a Request. The completion +* code is set to USB_XFER_IDLE. +* +* Also, initializes USBFS_transferByteCount. Save some space, +* this is the only consumer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_currentTD.pStatusBlock->status - set to XFER_IDLE. +* USBFS_currentTD.pStatusBlock->length - cleared. +* USBFS_transferByteCount - cleared. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_InitializeStatusBlock(void) +{ + USBFS_transferByteCount = 0u; + if(USBFS_currentTD.pStatusBlock != NULL) + { + USBFS_currentTD.pStatusBlock->status = USBFS_XFER_IDLE; + USBFS_currentTD.pStatusBlock->length = 0u; + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c new file mode 100644 index 0000000..d2668a1 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_episr.c @@ -0,0 +1,881 @@ +/******************************************************************************* +* File Name: USBFS_episr.c +* Version 2.80 +* +* Description: +* Data endpoint Interrupt Service Routines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + +#if (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) + #include "USBFS_midi.h" +#endif /* (defined(USBFS_ENABLE_MIDI_STREAMING) && (USBFS_ENABLE_MIDI_API != 0u)) */ +#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + #include "USBFS_EP8_DMA_Done_SR.h" + #include "USBFS_EP17_DMA_Done_SR.h" +#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +#if(USBFS_EP1_ISR_REMOVE == 0u) + + + /****************************************************************************** + * Function Name: USBFS_EP_1_ISR + ******************************************************************************* + * + * Summary: + * Endpoint 1 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + ******************************************************************************/ + CY_ISR(USBFS_EP_1_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + #ifdef USBFS_EP_1_ISR_ENTRY_CALLBACK + USBFS_EP_1_ISR_EntryCallback(); + #endif /* USBFS_EP_1_ISR_ENTRY_CALLBACK */ + + /* `#START EP1_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP1_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP1].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP1].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP1].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) & + (uint8)~USBFS_SIE_EP_INT_EP1_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP1) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP1_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_1_ISR_EXIT_CALLBACK + USBFS_EP_1_ISR_ExitCallback(); + #endif /* USBFS_EP_1_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* USBFS_EP1_ISR_REMOVE */ + + +#if(USBFS_EP2_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_2_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 2 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_2_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + #ifdef USBFS_EP_2_ISR_ENTRY_CALLBACK + USBFS_EP_2_ISR_EntryCallback(); + #endif /* USBFS_EP_2_ISR_ENTRY_CALLBACK */ + + /* `#START EP2_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + CY_GET_REG8(USBFS_SIE_EP2_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP2].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP2].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP2].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP2_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP2) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP2_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_2_ISR_EXIT_CALLBACK + USBFS_EP_2_ISR_ExitCallback(); + #endif /* USBFS_EP_2_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + } + +#endif /* USBFS_EP2_ISR_REMOVE */ + + +#if(USBFS_EP3_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_3_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 3 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_3_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3 */ + + #ifdef USBFS_EP_3_ISR_ENTRY_CALLBACK + USBFS_EP_3_ISR_EntryCallback(); + #endif /* USBFS_EP_3_ISR_ENTRY_CALLBACK */ + + /* `#START EP3_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP3_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP3].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP3].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP3].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP3_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP3) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP3_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_3_ISR_EXIT_CALLBACK + USBFS_EP_3_ISR_ExitCallback(); + #endif /* USBFS_EP_3_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* USBFS_EP3_ISR_REMOVE */ + + +#if(USBFS_EP4_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_4_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 4 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_4_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + #ifdef USBFS_EP_4_ISR_ENTRY_CALLBACK + USBFS_EP_4_ISR_EntryCallback(); + #endif /* USBFS_EP_4_ISR_ENTRY_CALLBACK */ + + /* `#START EP4_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP4_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP4].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP4].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP4].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP4_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP4) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP4_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_4_ISR_EXIT_CALLBACK + USBFS_EP_4_ISR_ExitCallback(); + #endif /* USBFS_EP_4_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* USBFS_EP4_ISR_REMOVE */ + + +#if(USBFS_EP5_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_5_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 5 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_5_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + #ifdef USBFS_EP_5_ISR_ENTRY_CALLBACK + USBFS_EP_5_ISR_EntryCallback(); + #endif /* USBFS_EP_5_ISR_ENTRY_CALLBACK */ + + /* `#START EP5_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP5_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP5].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP5].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP5].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP5_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP5) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP5_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_5_ISR_EXIT_CALLBACK + USBFS_EP_5_ISR_ExitCallback(); + #endif /* USBFS_EP_5_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } +#endif /* USBFS_EP5_ISR_REMOVE */ + + +#if(USBFS_EP6_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_6_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 6 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_6_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + #ifdef USBFS_EP_6_ISR_ENTRY_CALLBACK + USBFS_EP_6_ISR_EntryCallback(); + #endif /* USBFS_EP_6_ISR_ENTRY_CALLBACK */ + + /* `#START EP6_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP6_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP6].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP6].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP6].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP6_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP6) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP6_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_6_ISR_EXIT_CALLBACK + USBFS_EP_6_ISR_ExitCallback(); + #endif /* USBFS_EP_6_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* USBFS_EP6_ISR_REMOVE */ + + +#if(USBFS_EP7_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_7_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 7 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_7_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + #ifdef USBFS_EP_7_ISR_ENTRY_CALLBACK + USBFS_EP_7_ISR_EntryCallback(); + #endif /* USBFS_EP_7_ISR_ENTRY_CALLBACK */ + + /* `#START EP7_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP7_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP7].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP7].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP7].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP7_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP7) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP7_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_7_ISR_EXIT_CALLBACK + USBFS_EP_7_ISR_ExitCallback(); + #endif /* USBFS_EP_7_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* USBFS_EP7_ISR_REMOVE */ + + +#if(USBFS_EP8_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_EP_8_ISR + ******************************************************************************** + * + * Summary: + * Endpoint 8 Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_EP_8_ISR) + { + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + uint8 int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + #ifdef USBFS_EP_8_ISR_ENTRY_CALLBACK + USBFS_EP_8_ISR_EntryCallback(); + #endif /* USBFS_EP_8_ISR_ENTRY_CALLBACK */ + + /* `#START EP8_USER_CODE` Place your code here */ + + /* `#END` */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + int_en = EA; + CyGlobalIntEnable; /* Make sure nested interrupt is enabled */ + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + + CY_GET_REG8(USBFS_SIE_EP8_CR0_PTR); /* Must read the mode reg */ + /* Do not toggle ISOC endpoint */ + if((USBFS_EP[USBFS_EP8].attrib & USBFS_EP_TYPE_MASK) != + USBFS_EP_TYPE_ISOC) + { + USBFS_EP[USBFS_EP8].epToggle ^= USBFS_EPX_CNT_DATA_TOGGLE; + } + USBFS_EP[USBFS_EP8].apiEpState = USBFS_EVENT_PENDING; + CY_SET_REG8(USBFS_SIE_EP_INT_SR_PTR, CY_GET_REG8(USBFS_SIE_EP_INT_SR_PTR) + & (uint8)~USBFS_SIE_EP_INT_EP8_MASK); + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT) + if(USBFS_midi_out_ep == USBFS_EP8) + { + USBFS_MIDI_OUT_EP_Service(); + } + #endif /* USBFS_ISR_SERVICE_MIDI_OUT */ + + /* `#START EP8_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_8_ISR_EXIT_CALLBACK + USBFS_EP_8_ISR_ExitCallback(); + #endif /* USBFS_EP_8_ISR_EXIT_CALLBACK */ + + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && !defined(USBFS_MAIN_SERVICE_MIDI_OUT) && \ + USBFS_ISR_SERVICE_MIDI_OUT && CY_PSOC3) + EA = int_en; + #endif /* CY_PSOC3 & USBFS_ISR_SERVICE_MIDI_OUT */ + } + +#endif /* USBFS_EP8_ISR_REMOVE */ + + +/******************************************************************************* +* Function Name: USBFS_SOF_ISR +******************************************************************************** +* +* Summary: +* Start of Frame Interrupt Service Routine +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_SOF_ISR) +{ + #ifdef USBFS_SOF_ISR_INTERRUPT_CALLBACK + USBFS_SOF_ISR_InterruptCallback(); + #endif /* USBFS_SOF_ISR_INTERRUPT_CALLBACK */ + + /* `#START SOF_USER_CODE` Place your code here */ + + /* `#END` */ +} + + +/******************************************************************************* +* Function Name: USBFS_BUS_RESET_ISR +******************************************************************************** +* +* Summary: +* USB Bus Reset Interrupt Service Routine. Calls _Start with the same +* parameters as the last USER call to _Start +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +CY_ISR(USBFS_BUS_RESET_ISR) +{ + #ifdef USBFS_BUS_RESET_ISR_ENTRY_CALLBACK + USBFS_BUS_RESET_ISR_EntryCallback(); + #endif /* USBFS_BUS_RESET_ISR_ENTRY_CALLBACK */ + + /* `#START BUS_RESET_USER_CODE` Place your code here */ + + /* `#END` */ + + USBFS_ReInitComponent(); + + #ifdef USBFS_BUS_RESET_ISR_EXIT_CALLBACK + USBFS_BUS_RESET_ISR_ExitCallback(); + #endif /* USBFS_BUS_RESET_ISR_EXIT_CALLBACK */ +} + + +#if((USBFS_EP_MM != USBFS__EP_MANUAL) && (USBFS_ARB_ISR_REMOVE == 0u)) + + + /******************************************************************************* + * Function Name: USBFS_ARB_ISR + ******************************************************************************** + * + * Summary: + * Arbiter Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + * Side effect: + * Search for EP8 int_status will be much slower than search for EP1 int_status. + * + *******************************************************************************/ + CY_ISR(USBFS_ARB_ISR) + { + uint8 int_status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + uint8 ptr = 0u; + + #ifdef USBFS_ARB_ISR_ENTRY_CALLBACK + USBFS_ARB_ISR_EntryCallback(); + #endif /* USBFS_ARB_ISR_ENTRY_CALLBACK */ + + /* `#START ARB_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + int_status = USBFS_ARB_INT_SR_REG; /* read Arbiter Status Register */ + USBFS_ARB_INT_SR_REG = int_status; /* Clear Serviced Interrupts */ + + while(int_status != 0u) + { + if((int_status & 1u) != 0u) /* If EpX interrupt present */ + { /* read Endpoint Status Register */ + ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); + /* If In Buffer Full */ + if((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* Clear Data ready status */ + *(reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) &= + (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + #if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /* Setup common area DMA with rest of the data */ + if(USBFS_inLength[ep] > USBFS_DMA_BYTES_PER_BURST) + { + USBFS_LoadNextInEP(ep, 0u); + } + else + { + USBFS_inBufFull[ep] = 1u; + } + #endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), USBFS_EP[ep].epMode); + #if (defined(USBFS_ENABLE_MIDI_STREAMING) && USBFS_ISR_SERVICE_MIDI_IN) + if(ep == USBFS_midi_in_ep) + { /* Clear MIDI input pointer */ + USBFS_midiInPointer = 0u; + } + #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + } + } + /* (re)arm Out EP only for mode2 */ + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + /* If DMA Grant */ + if((ep_status & USBFS_ARB_EPX_SR_DMA_GNT) != 0u) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + /* Write the Mode register */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ptr), + USBFS_EP[ep].epMode); + } + } + #endif /* USBFS_EP_MM */ + + /* `#START ARB_USER_CODE` Place your code here for handle Buffer Underflow/Overflow */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_CALLBACK + USBFS_ARB_ISR_Callback(); + #endif /* USBFS_ARB_ISR_CALLBACK */ + + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr), ep_status); /* Clear Serviced events */ + } + ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ + ep++; + int_status >>= 1u; + } + + /* `#START ARB_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_ARB_ISR_EXIT_CALLBACK + USBFS_ARB_ISR_ExitCallback(); + #endif /* USBFS_ARB_ISR_EXIT_CALLBACK */ + } + +#endif /* USBFS_EP_MM */ + +#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + /****************************************************************************** + * Function Name: USBFS_EP_DMA_DONE_ISR + ******************************************************************************* + * + * Summary: + * Endpoint 1 DMA Done Interrupt Service Routine + * + * Parameters: + * None. + * + * Return: + * None. + * + ******************************************************************************/ + CY_ISR(USBFS_EP_DMA_DONE_ISR) + { + uint8 int8Status; + uint8 int17Status; + uint8 ep_status; + uint8 ep = USBFS_EP1; + uint8 ptr = 0u; + + #ifdef USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK + USBFS_EP_DMA_DONE_ISR_EntryCallback(); + #endif /* USBFS_EP_DMA_DONE_ISR_ENTRY_CALLBACK */ + + /* `#START EP_DMA_DONE_BEGIN_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Read clear on read status register with the EP source of interrupt */ + int17Status = USBFS_EP17_DMA_Done_SR_Read() & USBFS_EP17_SR_MASK; + int8Status = USBFS_EP8_DMA_Done_SR_Read() & USBFS_EP8_SR_MASK; + + while(int8Status != 0u) + { + while(int17Status != 0u) + { + if((int17Status & 1u) != 0u) /* If EpX interrupt present */ + { + /* Read Endpoint Status Register */ + ep_status = CY_GET_REG8((reg8 *)(USBFS_ARB_EP1_SR_IND + ptr)); + if( ((ep_status & USBFS_ARB_EPX_SR_IN_BUF_FULL) == 0u) && + (USBFS_inBufFull[ep] == 0u)) + { + /* `#START EP_DMA_DONE_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_CALLBACK + USBFS_EP_DMA_DONE_ISR_Callback(); + #endif /* USBFS_EP_DMA_DONE_ISR_CALLBACK */ + + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ptr), 0x00u); + /* repeat 2 last bytes to prefetch endpoint area */ + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ptr), + USBFS_DMA_BYTES_PER_BURST * ep - USBFS_DMA_BYTES_REPEAT); + USBFS_LoadNextInEP(ep, 1); + /* Set Data ready status, This will generate DMA request */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ptr) |= USBFS_ARB_EPX_CFG_IN_DATA_RDY; + } + } + ptr += USBFS_EPX_CNTX_ADDR_OFFSET; /* prepare pointer for next EP */ + ep++; + int17Status >>= 1u; + } + int8Status >>= 1u; + if(int8Status != 0u) + { + /* Prepare pointer for EP8 */ + ptr = ((USBFS_EP8 - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + ep = USBFS_EP8; + int17Status = int8Status & 0x01u; + } + } + + /* `#START EP_DMA_DONE_END_USER_CODE` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK + USBFS_EP_DMA_DONE_ISR_ExitCallback(); + #endif /* USBFS_EP_DMA_DONE_ISR_EXIT_CALLBACK */ + } +#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c new file mode 100644 index 0000000..0573c0c --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.c @@ -0,0 +1,431 @@ +/******************************************************************************* +* File Name: USBFS_hid.c +* Version 2.80 +* +* Description: +* USB HID Class request handler. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_HID_CLASS) + +#include "USBFS_pvt.h" +#include "USBFS_hid.h" + + + +/*************************************** +* HID Variables +***************************************/ + +volatile uint8 USBFS_hidProtocol[USBFS_MAX_INTERFACES_NUMBER]; /* HID device protocol status */ +volatile uint8 USBFS_hidIdleRate[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle reload value */ +volatile uint8 USBFS_hidIdleTimer[USBFS_MAX_INTERFACES_NUMBER]; /* HID device idle rate value */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START HID_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_UpdateHIDTimer +******************************************************************************** +* +* Summary: +* Updates the HID report timer and reloads it if expired +* +* Parameters: +* interface: Interface Number. +* +* Return: +* status. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_UpdateHIDTimer(uint8 interface) +{ + uint8 stat = USBFS_IDLE_TIMER_INDEFINITE; + + if(USBFS_hidIdleRate[interface] != 0u) + { + if(USBFS_hidIdleTimer[interface] > 0u) + { + USBFS_hidIdleTimer[interface]--; + stat = USBFS_IDLE_TIMER_RUNNING; + } + else + { + USBFS_hidIdleTimer[interface] = USBFS_hidIdleRate[interface]; + stat = USBFS_IDLE_TIMER_EXPIRED; + } + } + + return(stat); +} + + +/******************************************************************************* +* Function Name: USBFS_GetProtocol +******************************************************************************** +* +* Summary: +* Returns the selected protocol value to the application +* +* Parameters: +* interface: Interface Number. +* +* Return: +* Interface protocol. +* +*******************************************************************************/ +uint8 USBFS_GetProtocol(uint8 interface) +{ + return(USBFS_hidProtocol[interface]); +} + + +/******************************************************************************* +* Function Name: USBFS_DispatchHIDClassRqst +******************************************************************************** +* +* Summary: +* This routine dispatches class requests +* +* Parameters: +* None. +* +* Return: +* requestHandled +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_DispatchHIDClassRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_CLASS) + { + USBFS_FindHidClassDecriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_HID_REPORT) + { + USBFS_FindReportDescriptor(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + } + else + { /* requestHandled is initialezed as FALSE by default */ + } + break; + case USBFS_HID_GET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlRead(); + } + break; + + case USBFS_HID_GET_IDLE: + /* This function does not support multiple reports per interface*/ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidIdleRate[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + case USBFS_HID_GET_PROTOCOL: + /* Validate interfaceNumber */ + if( interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = &USBFS_hidProtocol[interfaceNumber]; + requestHandled = USBFS_InitControlRead(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == + USBFS_RQST_DIR_H2D) + { /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_HID_SET_REPORT: + USBFS_FindReport(); + if (USBFS_currentTD.count != 0u) + { + requestHandled = USBFS_InitControlWrite(); + } + break; + case USBFS_HID_SET_IDLE: + /* This function does not support multiple reports per interface */ + /* Validate interfaceNumber and Report ID (should be 0) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) == 0u ) ) /* Do not support Idle per Report ID */ + { + USBFS_hidIdleRate[interfaceNumber] = CY_GET_REG8(USBFS_wValueHi); + /* With regards to HID spec: "7.2.4 Set_Idle Request" + * Latency. If the current period has gone past the + * newly proscribed time duration, then a report + * will be generated immediately. + */ + if(USBFS_hidIdleRate[interfaceNumber] < + USBFS_hidIdleTimer[interfaceNumber]) + { + /* Set the timer to zero and let the UpdateHIDTimer() API return IDLE_TIMER_EXPIRED status*/ + USBFS_hidIdleTimer[interfaceNumber] = 0u; + } + /* If the new request is received within 4 milliseconds + * (1 count) of the end of the current period, then the + * new request will have no effect until after the report. + */ + else if(USBFS_hidIdleTimer[interfaceNumber] <= 1u) + { + /* Do nothing. + * Let the UpdateHIDTimer() API continue to work and + * return IDLE_TIMER_EXPIRED status + */ + } + else + { /* Reload the timer*/ + USBFS_hidIdleTimer[interfaceNumber] = + USBFS_hidIdleRate[interfaceNumber]; + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + + case USBFS_HID_SET_PROTOCOL: + /* Validate interfaceNumber and protocol (must be 0 or 1) */ + if( (interfaceNumber < USBFS_MAX_INTERFACES_NUMBER) && + (CY_GET_REG8(USBFS_wValueLo) <= 1u) ) + { + USBFS_hidProtocol[interfaceNumber] = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else + { /* requestHandled is initialized as FALSE by default */ + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USB_FindHidClassDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Class Descriptor pointer based on the Interface number +* and Alternate setting then loads the currentTD structure with the address of +* the buffer and the size. +* The HID Class Descriptor resides inside the config descriptor. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindHidClassDecriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number*/ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fifth entry in the LUT points to Hid Class Descriptor in Configuration Descriptor */ + pTmp = &pTmp[4u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The first byte contains the descriptor length */ + USBFS_currentTD.count = *pDescr; + USBFS_currentTD.pData = pDescr; +} + + +/******************************************************************************* +* Function Name: USB_FindReportDescriptor +******************************************************************************** +* +* Summary: +* This routine find Hid Report Descriptor pointer based on the Interface +* number, then loads the currentTD structure with the address of the buffer +* and the size. +* Hid Report Descriptor is located after IN/OUT/FEATURE reports. +* +* Parameters: +* void +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReportDescriptor(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + volatile uint8 *pDescr; + uint8 interfaceN; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Fourth entry in the LUT starts the Hid Report Descriptor */ + pTmp = &pTmp[3u]; + pDescr = (volatile uint8 *)pTmp->p_list; + /* The 1st and 2nd bytes of descriptor contain its length. LSB is 1st. */ + USBFS_currentTD.count = (((uint16)pDescr[1u] << 8u) | pDescr[0u]); + USBFS_currentTD.pData = &pDescr[2u]; +} + + +/******************************************************************************* +* Function Name: USBFS_FindReport +******************************************************************************** +* +* Summary: +* This routine sets up a transfer based on the Interface number, Report Type +* and Report ID, then loads the currentTD structure with the address of the +* buffer and the size. The caller has to decide if it is a control read or +* control write. +* +* Parameters: +* None. +* +* Return: +* currentTD +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_FindReport(void) +{ + const T_USBFS_LUT CYCODE *pTmp; + T_USBFS_TD *pTD; + uint8 interfaceN; + uint8 reportType; + + /* `#START HID_FINDREPORT` Place custom handling here */ + + /* `#END` */ + + #ifdef USBFS_FIND_REPORT_CALLBACK + USBFS_FindReport_Callback(); + #endif /* USBFS_FIND_REPORT_CALLBACK */ + + USBFS_currentTD.count = 0u; /* Init not supported condition */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + reportType = CY_GET_REG8(USBFS_wValueHi); + interfaceN = CY_GET_REG8(USBFS_wIndexLo); + /* Third entry in the LUT COnfiguration Table starts the Interface Table pointers */ + /* Now use the request interface number */ + pTmp = &pTmp[interfaceN + 2u]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_TABLE*/ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + if(interfaceN < USBFS_MAX_INTERFACES_NUMBER) + { + /* Now use Alternate setting number */ + pTmp = &pTmp[USBFS_interfaceSetting[interfaceN]]; + /* USB_DEVICEx_CONFIGURATIONy_INTERFACEz_ALTERNATEi_HID_TABLE */ + pTmp = (const T_USBFS_LUT CYCODE *) pTmp->p_list; + /* Validate reportType to comply with "7.2.1 Get_Report Request" */ + if((reportType >= USBFS_HID_GET_REPORT_INPUT) && + (reportType <= USBFS_HID_GET_REPORT_FEATURE)) + { + /* Get the entry proper TD (IN, OUT or Feature Report Table)*/ + pTmp = &pTmp[reportType - 1u]; + reportType = CY_GET_REG8(USBFS_wValueLo); /* Get reportID */ + /* Validate table support by the HID descriptor, compare table count with reportID */ + if(pTmp->c >= reportType) + { + pTD = (T_USBFS_TD *) pTmp->p_list; + pTD = &pTD[reportType]; /* select entry depend on report ID*/ + USBFS_currentTD.pData = pTD->pData; /* Buffer pointer */ + USBFS_currentTD.count = pTD->count; /* Buffer Size */ + USBFS_currentTD.pStatusBlock = pTD->pStatusBlock; + } + } + } +} + + +/******************************************************************************* +* Additional user functions supporting HID Requests +********************************************************************************/ + +/* `#START HID_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h new file mode 100644 index 0000000..c8075d2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_hid.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: USBFS_hid.h +* Version 2.80 +* +* Description: +* Header File for the USBFS component. Contains prototypes and constant values. +* +* Related Document: +* Device Class Definition for Human Interface Devices (HID) Version 1.11 +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_hid_H) +#define CY_USBFS_USBFS_hid_H + +#include "cytypes.h" + + +/*************************************** +* Prototypes of the USBFS_hid API. +***************************************/ + +uint8 USBFS_UpdateHIDTimer(uint8 interface) ; +uint8 USBFS_GetProtocol(uint8 interface) ; + + +/*************************************** +*Renamed Functions for backward compatible +***************************************/ + +#define USBFS_bGetProtocol USBFS_GetProtocol + + +/*************************************** +* Constants for USBFS_hid API. +***************************************/ + +#define USBFS_PROTOCOL_BOOT (0x00u) +#define USBFS_PROTOCOL_REPORT (0x01u) + +/* Request Types (HID Chapter 7.2) */ +#define USBFS_HID_GET_REPORT (0x01u) +#define USBFS_HID_GET_IDLE (0x02u) +#define USBFS_HID_GET_PROTOCOL (0x03u) +#define USBFS_HID_SET_REPORT (0x09u) +#define USBFS_HID_SET_IDLE (0x0Au) +#define USBFS_HID_SET_PROTOCOL (0x0Bu) + +/* Descriptor Types (HID Chapter 7.1) */ +#define USBFS_DESCR_HID_CLASS (0x21u) +#define USBFS_DESCR_HID_REPORT (0x22u) +#define USBFS_DESCR_HID_PHYSICAL (0x23u) + +/* Report Request Types (HID Chapter 7.2.1) */ +#define USBFS_HID_GET_REPORT_INPUT (0x01u) +#define USBFS_HID_GET_REPORT_OUTPUT (0x02u) +#define USBFS_HID_GET_REPORT_FEATURE (0x03u) + +#endif /* CY_USBFS_USBFS_hid_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c new file mode 100644 index 0000000..68f32a2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.c @@ -0,0 +1,1382 @@ +/******************************************************************************* +* File Name: USBFS_midi.c +* Version 2.80 +* +* Description: +* MIDI Streaming request handler. +* This file contains routines for sending and receiving MIDI +* messages, and handles running status in both directions. +* +* Related Document: +* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0 +* MIDI 1.0 Detailed Specification Document Version 4.2 +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#include "USBFS_midi.h" +#include "USBFS_pvt.h" + + + +/*************************************** +* MIDI Constants +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + /* The Size of the MIDI messages (MIDI Table 4-1) */ + static const uint8 CYCODE USBFS_MIDI_SIZE[] = { + /* Miscellaneous function codes(Reserved) */ 0x03u, + /* Cable events (Reserved) */ 0x03u, + /* Two-byte System Common messages */ 0x02u, + /* Three-byte System Common messages */ 0x03u, + /* SysEx starts or continues */ 0x03u, + /* Single-byte System Common Message or + SysEx ends with following single byte */ 0x01u, + /* SysEx ends with following two bytes */ 0x02u, + /* SysEx ends with following three bytes */ 0x03u, + /* Note-off */ 0x03u, + /* Note-on */ 0x03u, + /* Poly-KeyPress */ 0x03u, + /* Control Change */ 0x03u, + /* Program Change */ 0x02u, + /* Channel Pressure */ 0x02u, + /* PitchBend Change */ 0x03u, + /* Single Byte */ 0x01u + }; +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + + +/*************************************** +* Global variables +***************************************/ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* (USBFS_MIDI_IN_BUFF_SIZE >= 256) */ + volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI1_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI1_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + static USBFS_MIDI_RX_STATUS USBFS_MIDI2_Event; /* MIDI RX status structure */ + static volatile uint8 USBFS_MIDI2_TxRunStat; /* MIDI Output running status */ + volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + +/*************************************** +* Custom Declarations +***************************************/ + +/* `#START MIDI_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Optional MIDI APIs +***************************************/ +#if (USBFS_ENABLE_MIDI_API != 0u) + + +/******************************************************************************* +* Function Name: USBFS_MIDI_EP_Init +******************************************************************************** +* +* Summary: +* This function initializes the MIDI interface and UART(s) to be ready to +* receive data from the PC and MIDI ports. +* +* Parameters: +* None +* +* Return: +* None +* +* Global variables: +* USBFS_midiInBuffer: This buffer is used for saving and combining +* the received data from UART(s) and(or) generated internally by +* PutUsbMidiIn() function messages. USBFS_MIDI_IN_EP_Service() +* function transfers the data from this buffer to the PC. +* USBFS_midiOutBuffer: This buffer is used by the +* USBFS_MIDI_OUT_EP_Service() function for saving the received +* from the PC data, then the data are parsed and transferred to UART(s) +* buffer and to the internal processing by the +* USBFS_callbackLocalMidiEvent function. +* USBFS_midi_out_ep: Used as an OUT endpoint number. +* USBFS_midi_in_ep: Used as an IN endpoint number. +* USBFS_midiInPointer: Initialized to zero. +* +* Reentrant: +* No +* +*******************************************************************************/ +void USBFS_MIDI_EP_Init(void) +{ + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + USBFS_midiInPointer = 0u; + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + #if (USBFS_MIDI_IN_BUFF_SIZE > 0) + /* Init DMA configurations for IN EP*/ + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + USBFS_MIDI_IN_BUFF_SIZE); + + #endif /* (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + /* Init DMA configurations for OUT EP*/ + (void)USBFS_ReadOutEP(USBFS_midi_out_ep, USBFS_midiOutBuffer, + USBFS_MIDI_OUT_BUFF_SIZE); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */ + + #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + + /* Initialize the MIDI port(s) */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + USBFS_MIDI_Init(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ +} + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_OUT_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI OUT endpoints. + * This function is called from OUT EP ISR. It transfers the received from PC + * data to the external MIDI port(UART TX buffer) and calls the + * USBFS_callbackLocalMidiEvent() function to internal process + * of the MIDI data. + * This function is blocked by UART, if not enough space is available in UART + * TX buffer. Therefore it is recommended to use large UART TX buffer size. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiOutBuffer: Used as temporary buffer between USB internal + * memory and UART TX buffer. + * USBFS_midi_out_ep: Used as an OUT endpoint number. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_OUT_EP_Service(void) + { + #if USBFS_MIDI_OUT_BUFF_SIZE >= 256 + uint16 outLength; + uint16 outPointer; + #else + uint8 outLength; + uint8 outPointer; + #endif /* USBFS_MIDI_OUT_BUFF_SIZE >=256 */ + + uint8 dmaState = 0u; + + /* Service the USB MIDI output endpoint */ + if (USBFS_GetEPState(USBFS_midi_out_ep) == USBFS_OUT_BUFFER_FULL) + { + #if(USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_GetEPCount(USBFS_midi_out_ep); + #else + outLength = (uint8)USBFS_GetEPCount(USBFS_midi_out_ep); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + #if (USBFS_MIDI_OUT_BUFF_SIZE >= 256) + outLength = USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, outLength); + #else + outLength = (uint8)USBFS_ReadOutEP(USBFS_midi_out_ep, + USBFS_midiOutBuffer, (uint16)outLength); + #endif /* (USBFS_MIDI_OUT_BUFF_SIZE >= 256) */ + + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + do /* wait for DMA transfer complete */ + { + (void) CyDmaChStatus(USBFS_DmaChan[USBFS_midi_out_ep], NULL, &dmaState); + } + while((dmaState & (STATUS_TD_ACTIVE | STATUS_CHAIN_ACTIVE)) != 0u); + #endif /* (USBFS_EP_MM == USBFS__EP_DMAMANUAL) */ + + #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */ + + if(dmaState != 0u) + { + /* Suppress compiler warning */ + } + + if (outLength >= USBFS_EVENT_LENGTH) + { + outPointer = 0u; + while (outPointer < outLength) + { + /* In some OS OUT packet could be appended by nulls which could be skipped */ + if (USBFS_midiOutBuffer[outPointer] == 0u) + { + break; + } + /* Route USB MIDI to the External connection */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_00) + { + USBFS_MIDI1_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + } + else if ((USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK) == + USBFS_MIDI_CABLE_01) + { + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_ProcessUsbOut(&USBFS_midiOutBuffer[outPointer]); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + } + else + { + /* `#START CUSTOM_MIDI_OUT_EP_SERV` Place your code here */ + + /* `#END` */ + + #ifdef USBFS_MIDI_OUT_EP_SERVICE_CALLBACK + USBFS_MIDI_OUT_EP_Service_Callback(); + #endif /* USBFS_MIDI_OUT_EP_SERVICE_CALLBACK */ + } + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + /* Process any local MIDI output functions */ + USBFS_callbackLocalMidiEvent( + USBFS_midiOutBuffer[outPointer] & USBFS_CABLE_MASK, + &USBFS_midiOutBuffer[outPointer + USBFS_EVENT_BYTE1]); + outPointer += USBFS_EVENT_LENGTH; + } + } + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* Enable Out EP*/ + USBFS_EnableOutEP(USBFS_midi_out_ep); + #endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) */ + } + } + +#endif /* #if (USBFS_MIDI_OUT_BUFF_SIZE > 0) */ + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_EP_Service + ******************************************************************************** + * + * Summary: + * Services the USB MIDI IN endpoint. Non-blocking. + * Checks that previous packet was processed by HOST, otherwise service the + * input endpoint on the subsequent call. It is called from the + * USBFS_MIDI_IN_Service() and from the + * USBFS_PutUsbMidiIn() function. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midi_in_ep: Used as an IN endpoint number. + * USBFS_midiInBuffer: Function loads the data from this buffer to + * the USB IN endpoint. + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_EP_Service(void) + { + /* Service the USB MIDI input endpoint */ + /* Check that previous packet was processed by HOST, otherwise service the USB later */ + if (USBFS_midiInPointer != 0u) + { + if(USBFS_GetEPState(USBFS_midi_in_ep) == USBFS_EVENT_PENDING) + { + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + USBFS_LoadInEP(USBFS_midi_in_ep, USBFS_midiInBuffer, + (uint16)USBFS_midiInPointer); + #else /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + /* rearm IN EP */ + USBFS_LoadInEP(USBFS_midi_in_ep, NULL, (uint16)USBFS_midiInPointer); + #endif /* (USBFS_EP_MM != USBFS__EP_DMAAUTO) */ + + /* Clear the midiInPointer. For DMA mode, clear this pointer in the ARB ISR when data are moved by DMA */ + #if(USBFS_EP_MM == USBFS__EP_MANUAL) + USBFS_midiInPointer = 0u; + #endif /* (USBFS_EP_MM == USBFS__EP_MANUAL) */ + } + } + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI_IN_Service + ******************************************************************************** + * + * Summary: + * Services the traffic from the MIDI input ports (RX UART) and prepare data + * in USB MIDI IN endpoint buffer. + * Calls the USBFS_MIDI_IN_EP_Service() function to sent the + * data from buffer to PC. Non-blocking. Should be called from main foreground + * task. + * This function is not protected from the reentrant calls. When it is required + * to use this function in UART RX ISR to guaranty low latency, care should be + * taken to protect from reentrant calls. + * + * Parameters: + * None + * + * Return: + * None + * + * Global variables: + * USBFS_midiInPointer: Cleared to zero when data are sent. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_MIDI_IN_Service(void) + { + /* Service the MIDI UART inputs until either both receivers have no more + * events or until the input endpoint buffer fills up. + */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + uint8 m1 = 0u; + uint8 m2 = 0u; + do + { + if (USBFS_midiInPointer <= + (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI1 input port for a complete event */ + m1 = USBFS_MIDI1_GetEvent(); + if (m1 != 0u) + { + USBFS_PrepareInBuffer(m1, (uint8 *)&USBFS_MIDI1_Event.msgBuff[0], + USBFS_MIDI1_Event.size, USBFS_MIDI_CABLE_00); + } + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + if (USBFS_midiInPointer <= + (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) + { + /* Check MIDI2 input port for a complete event */ + m2 = USBFS_MIDI2_GetEvent(); + if (m2 != 0u) + { + USBFS_PrepareInBuffer(m2, (uint8 *)&USBFS_MIDI2_Event.msgBuff[0], + USBFS_MIDI2_Event.size, USBFS_MIDI_CABLE_01); + } + } + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ + + }while( (USBFS_midiInPointer <= + (USBFS_MIDI_IN_BUFF_SIZE - USBFS_EVENT_LENGTH)) && + ((m1 != 0u) || (m2 != 0u)) ); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + /* Service the USB MIDI input endpoint */ + USBFS_MIDI_IN_EP_Service(); + } + + + /******************************************************************************* + * Function Name: USBFS_PutUsbMidiIn + ******************************************************************************** + * + * Summary: + * Puts one MIDI messages into the USB MIDI In endpoint buffer. These are + * MIDI input messages to the host. This function is only used if the device + * has internal MIDI input functionality. USBMIDI_MIDI_IN_Service() function + * should additionally be called to send the message from local buffer to + * IN endpoint. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message in midiMsg + * 3 - IN EP LENGTH = Complete SySEx message(without EOSEX byte) in + * midiMsg. The length is limited by the max BULK EP size(64) + * MIDI_SYSEX = Start or continuation of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_EOSEX = End of SysEx message + * (put event bytes in midiMsg buffer) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * midiMsg: pointer to MIDI message. + * cable: cable number. + * + * Return: + * USBFS_TRUE if error. + * USBFS_FALSE if success. + * + * Global variables: + * USBFS_midi_in_ep: MIDI IN endpoint number used for sending data. + * USBFS_midiInPointer: Checked this variable to see if there is + * enough free space in the IN endpoint buffer. If buffer is full, initiate + * sending to PC. + * + * Reentrant: + * No + * + *******************************************************************************/ + uint8 USBFS_PutUsbMidiIn(uint8 ic, const uint8 midiMsg[], uint8 cable) + + { + uint8 retError = USBFS_FALSE; + uint8 msgIndex; + + /* Protect PrepareInBuffer() function from concurrent calls */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_DisableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_DisableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + } + if (USBFS_midiInPointer <= + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + if((ic < USBFS_EVENT_LENGTH) || (ic >= USBFS_MIDI_STATUS_MASK)) + { + USBFS_PrepareInBuffer(ic, midiMsg, ic, cable); + } + else + { /* Only SysEx message is greater than 4 bytes */ + msgIndex = 0u; + do + { + USBFS_PrepareInBuffer(USBFS_MIDI_SYSEX, &midiMsg[msgIndex], + USBFS_EVENT_BYTE3, cable); + ic -= USBFS_EVENT_BYTE3; + msgIndex += USBFS_EVENT_BYTE3; + if (USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + USBFS_MIDI_IN_EP_Service(); + if(USBFS_midiInPointer > + (USBFS_EP[USBFS_midi_in_ep].bufferSize - USBFS_EVENT_LENGTH)) + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + break; + } + } + } + while(ic > USBFS_EVENT_BYTE3); + + if(retError == USBFS_FALSE) + { + USBFS_PrepareInBuffer(USBFS_MIDI_EOSEX, midiMsg, ic, cable); + } + } + } + else + { + /* Error condition. HOST is not ready to receive this packet. */ + retError = USBFS_TRUE; + } + + #if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + MIDI1_UART_EnableRxInt(); + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + MIDI2_UART_EnableRxInt(); + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ + #endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + + return (retError); + } + + + /******************************************************************************* + * Function Name: USBFS_PrepareInBuffer + ******************************************************************************** + * + * Summary: + * Builds a USB MIDI event in the input endpoint buffer at the current pointer. + * Puts one MIDI message into the USB MIDI In endpoint buffer. + * + * Parameters: + * ic: 0 = No message (should never happen) + * 1 - 3 = Complete MIDI message at pMdat[0] + * MIDI_SYSEX = Start or continuation of SysEx message + * (put eventLen bytes in buffer) + * MIDI_EOSEX = End of SysEx message + * (put eventLen bytes in buffer, + * and append MIDI_EOSEX) + * MIDI_TUNEREQ = Tune Request message (single byte system common msg) + * 0xf8 - 0xff = Single byte real-time message + * + * srcBuff: pointer to MIDI data + * eventLen: number of bytes in MIDI event + * cable: MIDI source port number + * + * Return: + * None + * + * Global variables: + * USBFS_midiInBuffer: This buffer is used for saving and combine the + * received from UART(s) and(or) generated internally by + * USBFS_PutUsbMidiIn() function messages. + * USBFS_midiInPointer: Used as an index for midiInBuffer to + * write data. + * + * Reentrant: + * No + * + *******************************************************************************/ + void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + + { + uint8 srcBuffZero; + uint8 srcBuffOne; + + srcBuffZero = srcBuff[0u]; + srcBuffOne = srcBuff[1u]; + + if (ic >= (USBFS_MIDI_STATUS_MASK | USBFS_MIDI_SINGLE_BYTE_MASK)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SINGLE_BYTE | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = ic; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + } + else if((ic < USBFS_EVENT_LENGTH) || (ic == USBFS_MIDI_SYSEX)) + { + if(ic == USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_SYSEX | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero < USBFS_MIDI_SYSEX) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = (srcBuffZero >> 4u) | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_TUNEREQ) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_1BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if ((srcBuffZero == USBFS_MIDI_QFM) || (srcBuffZero == USBFS_MIDI_SONGSEL)) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_2BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else if (srcBuffZero == USBFS_MIDI_SPP) + { + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_3BYTE_COMMON | cable; + USBFS_midiInPointer++; + } + else + { + } + + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuff[2u]; + USBFS_midiInPointer++; + } + else if (ic == USBFS_MIDI_EOSEX) + { + switch (eventLen) + { + case 0u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH1 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 1u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH2 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = 0u; + USBFS_midiInPointer++; + break; + case 2u: + USBFS_midiInBuffer[USBFS_midiInPointer] = + USBFS_SYSEX_ENDS_WITH3 | cable; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffZero; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = srcBuffOne; + USBFS_midiInPointer++; + USBFS_midiInBuffer[USBFS_midiInPointer] = USBFS_MIDI_EOSEX; + USBFS_midiInPointer++; + break; + default: + break; + } + } + else + { + } + } + +#endif /* #if (USBFS_MIDI_IN_BUFF_SIZE > 0) */ + + +/* The implementation for external serial input and output connections +* to route USB MIDI data to and from those connections. +*/ +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI_Init + ******************************************************************************** + * + * Summary: + * Initializes MIDI variables and starts the UART(s) hardware block(s). + * + * Parameters: + * None + * + * Return: + * None + * + * Side Effects: + * Change the priority of the UART(s) TX interrupts to be higher than the + * default EP ISR priority. + * + * Global variables: + * USBFS_MIDI_Event: initialized to zero. + * USBFS_MIDI_TxRunStat: initialized to zero. + * + *******************************************************************************/ + void USBFS_MIDI_Init(void) + { + USBFS_MIDI1_Event.length = 0u; + USBFS_MIDI1_Event.count = 0u; + USBFS_MIDI1_Event.size = 0u; + USBFS_MIDI1_Event.runstat = 0u; + USBFS_MIDI1_TxRunStat = 0u; + USBFS_MIDI1_InqFlags = 0u; + /* Start UART block */ + MIDI1_UART_Start(); + /* Change the priority of the UART TX and RX interrupt */ + CyIntSetPriority(MIDI1_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI1_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + USBFS_MIDI2_Event.length = 0u; + USBFS_MIDI2_Event.count = 0u; + USBFS_MIDI2_Event.size = 0u; + USBFS_MIDI2_Event.runstat = 0u; + USBFS_MIDI2_TxRunStat = 0u; + USBFS_MIDI2_InqFlags = 0u; + /* Start second UART block */ + MIDI2_UART_Start(); + /* Change the priority of the UART TX interrupt */ + CyIntSetPriority(MIDI2_UART_TX_VECT_NUM, USBFS_CUSTOM_UART_TX_PRIOR_NUM); + CyIntSetPriority(MIDI2_UART_RX_VECT_NUM, USBFS_CUSTOM_UART_RX_PRIOR_NUM); + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF*/ + + /* `#START MIDI_INIT_CUSTOM` Init other extended UARTs here */ + + /* `#END` */ + + #ifdef USBFS_MIDI_INIT_CALLBACK + USBFS_MIDI_Init_Callback(); + #endif /* USBFS_MIDI_INIT_CALLBACK */ + } + + + /******************************************************************************* + * Function Name: USBFS_ProcessMidiIn + ******************************************************************************** + * + * Summary: + * Processes one byte of incoming MIDI data. + * + * Parameters: + * mData = current MIDI input data byte + * *rxStat = pointer to a MIDI_RX_STATUS structure + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + *******************************************************************************/ + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + + { + uint8 midiReturn = 0u; + + /* Check for a MIDI status byte. All status bytes, except real time messages, + * which are a single byte, force the start of a new buffer cycle. + */ + if ((mData & USBFS_MIDI_STATUS_BYTE_MASK) != 0u) + { + if ((mData & USBFS_MIDI_STATUS_MASK) == USBFS_MIDI_STATUS_MASK) + { + if ((mData & USBFS_MIDI_SINGLE_BYTE_MASK) != 0u) /* System Real-Time Messages(single byte) */ + { + midiReturn = mData; + } + else /* System Common Messages */ + { + switch (mData) + { + case USBFS_MIDI_SYSEX: + rxStat->msgBuff[0u] = USBFS_MIDI_SYSEX; + rxStat->runstat = USBFS_MIDI_SYSEX; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_EOSEX: + rxStat->runstat = 0u; + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_EOSEX; + break; + case USBFS_MIDI_SPP: + rxStat->msgBuff[0u] = USBFS_MIDI_SPP; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 3u; + break; + case USBFS_MIDI_SONGSEL: + rxStat->msgBuff[0u] = USBFS_MIDI_SONGSEL; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_QFM: + rxStat->msgBuff[0u] = USBFS_MIDI_QFM; + rxStat->runstat = 0u; + rxStat->count = 1u; + rxStat->length = 2u; + break; + case USBFS_MIDI_TUNEREQ: + rxStat->msgBuff[0u] = USBFS_MIDI_TUNEREQ; + rxStat->runstat = 0u; + rxStat->size = 1u; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + break; + } + } + } + else /* Channel Messages */ + { + rxStat->msgBuff[0u] = mData; + rxStat->runstat = mData; + rxStat->count = 1u; + switch (mData & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->length = 2u; + break; + default: + rxStat->runstat = 0u; + rxStat->count = 0u; + break; + } + } + } + + /* Otherwise, it's a data byte */ + else + { + if (rxStat->runstat == USBFS_MIDI_SYSEX) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = USBFS_MIDI_SYSEX; + } + } + else if (rxStat->count > 0u) + { + rxStat->msgBuff[rxStat->count] = mData; + rxStat->count++; + if (rxStat->count >= rxStat->length) + { + rxStat->size = rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + } + } + else if (rxStat->runstat != 0u) + { + rxStat->msgBuff[0u] = rxStat->runstat; + rxStat->msgBuff[1u] = mData; + rxStat->count = 2u; + switch (rxStat->runstat & USBFS_MIDI_STATUS_MASK) + { + case USBFS_MIDI_NOTE_OFF: + case USBFS_MIDI_NOTE_ON: + case USBFS_MIDI_POLY_KEY_PRESSURE: + case USBFS_MIDI_CONTROL_CHANGE: + case USBFS_MIDI_PITCH_BEND_CHANGE: + rxStat->length = 3u; + break; + case USBFS_MIDI_PROGRAM_CHANGE: + case USBFS_MIDI_CHANNEL_PRESSURE: + rxStat->size =rxStat->count; + rxStat->count = 0u; + midiReturn = rxStat->size; + break; + default: + rxStat->count = 0u; + break; + } + } + else + { + } + } + return (midiReturn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI1_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI1_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI1_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if (CY_PSOC3) /* This local variable is required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* (CY_PSOC3) */ + #else + uint8 rxBufferRead; + #endif /* (MIDI1_UART_RXBUFFERSIZE >= 256u) */ + + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + + if ( (MIDI1_UART_rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + rxBufferRead = MIDI1_UART_rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI1_UART_rxBufferWrite; + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary buffer pointer + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI1_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + { + rxData = MIDI1_UART_rxBuffer[rxBufferRead]; + /* Increment pointer with a wrap */ + rxBufferRead++; + if(rxBufferRead >= MIDI1_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI1_UART_rxBufferLoopDetect = 0u; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* MIDI1_UART_RXBUFFERSIZE >= 256 */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI1_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI1_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + MIDI1_UART_rxBufferRead = rxBufferRead; + #if ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI1_UART_RX_VECT_NUM); + #endif /* ((MIDI1_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI1_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI1_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI1_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI1_PROCESS_OUT_BEGIN` */ + + /* `#END` */ + + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI1_ProcessUsbOut_EntryCallback(); + #endif /* USBFS_MIDI1_PROCESS_USB_OUT_ENTRY_CALLBACK */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* Non-Real Time SySEx starts */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI1_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI1_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI1_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI1_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI1_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI1_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI1_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI1_PROCESS_OUT_END` */ + + /* `#END` */ + + #ifdef USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI1_ProcessUsbOut_ExitCallback(); + #endif /* USBFS_MIDI1_PROCESS_USB_OUT_EXIT_CALLBACK */ + } + + +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_GetEvent + ******************************************************************************** + * + * Summary: + * Checks for incoming MIDI data, calls the MIDI event builder if so. + * Returns either empty or with a complete event. + * + * Parameters: + * None + * + * Return: + * 0, if no complete message + * 1 - 4, if message complete + * MIDI_SYSEX, if start or continuation of system exclusive + * MIDI_EOSEX, if end of system exclusive + * 0xf8 - 0xff, if single byte real time message + * + * Global variables: + * USBFS_MIDI2_Event: RX status structure used to parse received + * data. + * + *******************************************************************************/ + uint8 USBFS_MIDI2_GetEvent(void) + { + uint8 msgRtn = 0u; + uint8 rxData; + #if (MIDI2_UART_RXBUFFERSIZE >= 256u) + uint16 rxBufferRead; + #if (CY_PSOC3) /* This local variable required only for PSOC3 and large buffer */ + uint16 rxBufferWrite; + #endif /* (CY_PSOC3) */ + #else + uint8 rxBufferRead; + #endif /* (MIDI2_UART_RXBUFFERSIZE >= 256) */ + + uint8 rxBufferLoopDetect; + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + + if ( (MIDI2_UART_rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u) ) + { + /* Protect variables that could change on interrupt by disabling Rx interrupt.*/ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + rxBufferRead = MIDI2_UART_rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + rxBufferWrite = MIDI2_UART_rxBufferWrite; + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + + /* Stay here until either the buffer is empty or we have a complete message + * in the message buffer. Note that we must use a temporary output pointer to + * since it takes two instructions to increment with a wrap, and we can't + * risk doing that with the real pointer and getting an interrupt in between + * instructions. + */ + + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + while ( ((rxBufferRead != rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #else + while ( ((rxBufferRead != MIDI2_UART_rxBufferWrite) || (rxBufferLoopDetect != 0u)) && (msgRtn == 0u) ) + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + { + rxData = MIDI2_UART_rxBuffer[rxBufferRead]; + rxBufferRead++; + if(rxBufferRead >= MIDI2_UART_RXBUFFERSIZE) + { + rxBufferRead = 0u; + } + /* If loop condition was set - update real read buffer pointer + * to avoid overflow status + */ + if(rxBufferLoopDetect != 0u ) + { + MIDI2_UART_rxBufferLoopDetect = 0u; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + msgRtn = USBFS_ProcessMidiIn(rxData, + (USBFS_MIDI_RX_STATUS *)&USBFS_MIDI2_Event); + + /* Read buffer loop condition to the local variable */ + rxBufferLoopDetect = MIDI2_UART_rxBufferLoopDetect; + } + + /* Finally, update the real output pointer, then return with + * an indication as to whether there's a complete message in the buffer. + */ + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntDisable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + MIDI2_UART_rxBufferRead = rxBufferRead; + #if ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) + CyIntEnable(MIDI2_UART_RX_VECT_NUM); + #endif /* ((MIDI2_UART_RXBUFFERSIZE >= 256u) && (CY_PSOC3)) */ + } + + return (msgRtn); + } + + + /******************************************************************************* + * Function Name: USBFS_MIDI2_ProcessUsbOut + ******************************************************************************** + * + * Summary: + * Process a USB MIDI output event. + * Puts data into the MIDI TX output buffer. + * + * Parameters: + * *epBuf: pointer on MIDI event. + * + * Return: + * None + * + * Global variables: + * USBFS_MIDI2_TxRunStat: This variable used to save the MIDI + * status byte and skip to send the repeated status byte in subsequent event. + * USBFS_MIDI2_InqFlags: The following flags are set when SysEx + * message comes. + * USBFS_INQ_SYSEX_FLAG: Non-Real Time SySEx message received. + * USBFS_INQ_IDENTITY_REQ_FLAG: Identity Request received. + * This bit should be cleared by user when Identity Reply message generated. + * + *******************************************************************************/ + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + + { + uint8 cmd; + uint8 len; + uint8 i; + + /* User code is required at the beginning of the procedure */ + /* `#START MIDI2_PROCESS_OUT_START` */ + + /* `#END` */ + + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK + USBFS_MIDI2_ProcessUsbOut_EntryCallback(); + #endif /* USBFS_MIDI2_PROCESS_USB_OUT_ENTRY_CALLBACK */ + + cmd = epBuf[USBFS_EVENT_BYTE0] & USBFS_CIN_MASK; + if((cmd != USBFS_RESERVED0) && (cmd != USBFS_RESERVED1)) + { + len = USBFS_MIDI_SIZE[cmd]; + i = USBFS_EVENT_BYTE1; + /* Universal System Exclusive message parsing */ + if(cmd == USBFS_SYSEX) + { + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_NON_REAL_TIME)) + { /* SySEx starts */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_SYSEX_FLAG; + } + else + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + } + else if(cmd == USBFS_SYSEX_ENDS_WITH1) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH2) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + } + else if(cmd == USBFS_SYSEX_ENDS_WITH3) + { + /* Identify Request support */ + if((USBFS_MIDI2_InqFlags & USBFS_INQ_SYSEX_FLAG) != 0u) + { + USBFS_MIDI2_InqFlags &= (uint8)~USBFS_INQ_SYSEX_FLAG; + if((epBuf[USBFS_EVENT_BYTE1] == USBFS_MIDI_SYSEX_GEN_INFORMATION) && + (epBuf[USBFS_EVENT_BYTE2] == USBFS_MIDI_SYSEX_IDENTITY_REQ)) + { /* Set the flag about received the Identity Request. + * The Identity Reply message may be send by user code. + */ + USBFS_MIDI2_InqFlags |= USBFS_INQ_IDENTITY_REQ_FLAG; + } + } + } + else /* Do nothing for other command */ + { + } + /* Running Status for Voice and Mode messages only. */ + if((cmd >= USBFS_NOTE_OFF) && ( cmd <= USBFS_PITCH_BEND_CHANGE)) + { + if(USBFS_MIDI2_TxRunStat == epBuf[USBFS_EVENT_BYTE1]) + { /* Skip the repeated Status byte */ + i++; + } + else + { /* Save Status byte for next event */ + USBFS_MIDI2_TxRunStat = epBuf[USBFS_EVENT_BYTE1]; + } + } + else + { /* Clear Running Status */ + USBFS_MIDI2_TxRunStat = 0u; + } + /* Puts data into the MIDI TX output buffer.*/ + do + { + MIDI2_UART_PutChar(epBuf[i]); + i++; + } while (i <= len); + } + + /* User code is required at the end of the procedure */ + /* `#START MIDI2_PROCESS_OUT_END` */ + + /* `#END` */ + + #ifdef USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK + USBFS_MIDI2_ProcessUsbOut_ExitCallback(); + #endif /* USBFS_MIDI2_PROCESS_USB_OUT_EXIT_CALLBACK */ + } +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) */ +#endif /* (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) */ + +#endif /* (USBFS_ENABLE_MIDI_API != 0u) */ + + +/* `#START MIDI_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* defined(USBFS_ENABLE_MIDI_STREAMING) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h new file mode 100644 index 0000000..c4c236d --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_midi.h @@ -0,0 +1,205 @@ +/******************************************************************************* +* File Name: USBFS_midi.h +* Version 2.80 +* +* Description: +* Header File for the USBFS MIDI module. +* Contains prototypes and constant values. +* +* Related Document: +* Universal Serial Bus Device Class Definition for MIDI Devices Release 1.0 +* MIDI 1.0 Detailed Specification Document Version 4.2 +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_midi_H) +#define CY_USBFS_USBFS_midi_H + +#include "cytypes.h" +#include "USBFS.h" + + +/*************************************** +* Data Structure Definition +***************************************/ + +/* The following structure is used to hold status information for + building and parsing incoming MIDI messages. */ +typedef struct +{ + uint8 length; /* expected length */ + uint8 count; /* current byte count */ + uint8 size; /* complete size */ + uint8 runstat; /* running status */ + uint8 msgBuff[4]; /* message buffer */ +} USBFS_MIDI_RX_STATUS; + + +/*************************************** +* MIDI Constants. +***************************************/ + +#define USBFS_ONE_EXT_INTRF (0x01u) +#define USBFS_TWO_EXT_INTRF (0x02u) + +/* Flag definitions for use with MIDI device inquiry */ +#define USBFS_INQ_SYSEX_FLAG (0x01u) +#define USBFS_INQ_IDENTITY_REQ_FLAG (0x02u) + +/* USB-MIDI Code Index Number Classifications (MIDI Table 4-1) */ +#define USBFS_CIN_MASK (0x0Fu) +#define USBFS_RESERVED0 (0x00u) +#define USBFS_RESERVED1 (0x01u) +#define USBFS_2BYTE_COMMON (0x02u) +#define USBFS_3BYTE_COMMON (0x03u) +#define USBFS_SYSEX (0x04u) +#define USBFS_1BYTE_COMMON (0x05u) +#define USBFS_SYSEX_ENDS_WITH1 (0x05u) +#define USBFS_SYSEX_ENDS_WITH2 (0x06u) +#define USBFS_SYSEX_ENDS_WITH3 (0x07u) +#define USBFS_NOTE_OFF (0x08u) +#define USBFS_NOTE_ON (0x09u) +#define USBFS_POLY_KEY_PRESSURE (0x0Au) +#define USBFS_CONTROL_CHANGE (0x0Bu) +#define USBFS_PROGRAM_CHANGE (0x0Cu) +#define USBFS_CHANNEL_PRESSURE (0x0Du) +#define USBFS_PITCH_BEND_CHANGE (0x0Eu) +#define USBFS_SINGLE_BYTE (0x0Fu) + +#define USBFS_CABLE_MASK (0xF0u) +#define USBFS_MIDI_CABLE_00 (0x00u) +#define USBFS_MIDI_CABLE_01 (0x10u) + +#define USBFS_EVENT_BYTE0 (0x00u) +#define USBFS_EVENT_BYTE1 (0x01u) +#define USBFS_EVENT_BYTE2 (0x02u) +#define USBFS_EVENT_BYTE3 (0x03u) +#define USBFS_EVENT_LENGTH (0x04u) + +#define USBFS_MIDI_STATUS_BYTE_MASK (0x80u) +#define USBFS_MIDI_STATUS_MASK (0xF0u) +#define USBFS_MIDI_SINGLE_BYTE_MASK (0x08u) +#define USBFS_MIDI_NOTE_OFF (0x80u) +#define USBFS_MIDI_NOTE_ON (0x90u) +#define USBFS_MIDI_POLY_KEY_PRESSURE (0xA0u) +#define USBFS_MIDI_CONTROL_CHANGE (0xB0u) +#define USBFS_MIDI_PROGRAM_CHANGE (0xC0u) +#define USBFS_MIDI_CHANNEL_PRESSURE (0xD0u) +#define USBFS_MIDI_PITCH_BEND_CHANGE (0xE0u) +#define USBFS_MIDI_SYSEX (0xF0u) +#define USBFS_MIDI_EOSEX (0xF7u) +#define USBFS_MIDI_QFM (0xF1u) +#define USBFS_MIDI_SPP (0xF2u) +#define USBFS_MIDI_SONGSEL (0xF3u) +#define USBFS_MIDI_TUNEREQ (0xF6u) +#define USBFS_MIDI_ACTIVESENSE (0xFEu) + +/* MIDI Universal System Exclusive defines */ +#define USBFS_MIDI_SYSEX_NON_REAL_TIME (0x7Eu) +#define USBFS_MIDI_SYSEX_REALTIME (0x7Fu) +/* ID of target device */ +#define USBFS_MIDI_SYSEX_ID_ALL (0x7Fu) +/* Sub-ID#1*/ +#define USBFS_MIDI_SYSEX_GEN_INFORMATION (0x06u) +#define USBFS_MIDI_SYSEX_GEN_MESSAGE (0x09u) +/* Sub-ID#2*/ +#define USBFS_MIDI_SYSEX_IDENTITY_REQ (0x01u) +#define USBFS_MIDI_SYSEX_IDENTITY_REPLY (0x02u) +#define USBFS_MIDI_SYSEX_SYSTEM_ON (0x01u) +#define USBFS_MIDI_SYSEX_SYSTEM_OFF (0x02u) + +#define USBFS_CUSTOM_UART_TX_PRIOR_NUM (0x04u) +#define USBFS_CUSTOM_UART_RX_PRIOR_NUM (0x02u) + +#define USBFS_ISR_SERVICE_MIDI_OUT \ + ( (USBFS_ENABLE_MIDI_API != 0u) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) && (USBFS_EP_MM == USBFS__EP_DMAAUTO)) +#define USBFS_ISR_SERVICE_MIDI_IN \ + ( (USBFS_ENABLE_MIDI_API != 0u) && (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + + +/*************************************** +* External function references +***************************************/ + +void USBFS_callbackLocalMidiEvent(uint8 cable, uint8 *midiMsg) + ; + + +/*************************************** +* External references +***************************************/ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + #include "MIDI1_UART.h" +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ +#if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + #include "MIDI2_UART.h" +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + #include +#endif /* USBFS_EP_MM */ + + +/*************************************** +* Private function prototypes +***************************************/ + +void USBFS_PrepareInBuffer(uint8 ic, const uint8 srcBuff[], uint8 eventLen, uint8 cable) + ; +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + void USBFS_MIDI_Init(void) ; + uint8 USBFS_ProcessMidiIn(uint8 mData, USBFS_MIDI_RX_STATUS *rxStat) + ; + uint8 USBFS_MIDI1_GetEvent(void) ; + void USBFS_MIDI1_ProcessUsbOut(const uint8 epBuf[]) + ; + + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + uint8 USBFS_MIDI2_GetEvent(void) ; + void USBFS_MIDI2_ProcessUsbOut(const uint8 epBuf[]) + ; + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + + +/*************************************** +* External data references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + +#if (USBFS_MIDI_IN_BUFF_SIZE > 0) + #if (USBFS_MIDI_IN_BUFF_SIZE >= 256) + extern volatile uint16 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #else + extern volatile uint8 USBFS_midiInPointer; /* Input endpoint buffer pointer */ + #endif /* USBFS_MIDI_IN_BUFF_SIZE >=256 */ + extern volatile uint8 USBFS_midi_in_ep; /* Input endpoint number */ + extern uint8 USBFS_midiInBuffer[USBFS_MIDI_IN_BUFF_SIZE]; /* Input endpoint buffer */ +#endif /* USBFS_MIDI_IN_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_OUT_BUFF_SIZE > 0) + extern volatile uint8 USBFS_midi_out_ep; /* Output endpoint number */ + extern uint8 USBFS_midiOutBuffer[USBFS_MIDI_OUT_BUFF_SIZE]; /* Output endpoint buffer */ +#endif /* USBFS_MIDI_OUT_BUFF_SIZE > 0 */ + +#if (USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF) + extern volatile uint8 USBFS_MIDI1_InqFlags; /* Device inquiry flag */ + #if (USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF) + extern volatile uint8 USBFS_MIDI2_InqFlags; /* Device inquiry flag */ + #endif /* USBFS_MIDI_EXT_MODE >= USBFS_TWO_EXT_INTRF */ +#endif /* USBFS_MIDI_EXT_MODE >= USBFS_ONE_EXT_INTRF */ + +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* CY_USBFS_USBFS_midi_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c new file mode 100644 index 0000000..1a00d00 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pm.c @@ -0,0 +1,285 @@ +/******************************************************************************* +* File Name: USBFS_pm.c +* Version 2.80 +* +* Description: +* This file provides Suspend/Resume APIs functionality. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "project.h" +#include "USBFS.h" +#include "USBFS_pvt.h" + + + +/*************************************** +* Custom Declarations +***************************************/ +/* `#START PM_CUSTOM_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/*************************************** +* Local data allocation +***************************************/ + +static USBFS_BACKUP_STRUCT USBFS_backup; + + +#if(USBFS_DP_ISR_REMOVE == 0u) + + /******************************************************************************* + * Function Name: USBFS_DP_Interrupt + ******************************************************************************** + * + * Summary: + * This Interrupt Service Routine handles DP pin changes for wake-up from + * the sleep mode. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + CY_ISR(USBFS_DP_ISR) + { + #ifdef USBFS_DP_ISR_ENTRY_CALLBACK + USBFS_DP_ISR_EntryCallback(); + #endif /* USBFS_DP_ISR_ENTRY_CALLBACK */ + + /* `#START DP_USER_CODE` Place your code here */ + + /* `#END` */ + + /* Clears active interrupt */ + CY_GET_REG8(USBFS_DP_INTSTAT_PTR); + + #ifdef USBFS_DP_ISR_EXIT_CALLBACK + USBFS_DP_ISR_ExitCallback(); + #endif /* USBFS_DP_ISR_EXIT_CALLBACK */ + } + +#endif /* (USBFS_DP_ISR_REMOVE == 0u) */ + + +/******************************************************************************* +* Function Name: USBFS_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: USBFS_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the current user configuration. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_RestoreConfig(void) +{ + if(USBFS_configuration != 0u) + { + USBFS_ConfigReg(); + } +} + + +/******************************************************************************* +* Function Name: USBFS_Suspend +******************************************************************************** +* +* Summary: +* This function disables the USBFS block and prepares for power down mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup.enable: modified. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Suspend(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if((CY_GET_REG8(USBFS_CR0_PTR) & USBFS_CR0_ENABLE) != 0u) + { /* USB block is enabled */ + USBFS_backup.enableState = 1u; + + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + USBFS_Stop_DMA(USBFS_MAX_EP); /* Stop all DMAs */ + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* Ensure USB transmit enable is low (USB_USBIO_CR0.ten). - Manual Transmission - Disabled */ + USBFS_USBIO_CR0_REG &= (uint8)~USBFS_USBIO_CR0_TEN; + CyDelayUs(0u); /*~50ns delay */ + + /* Disable the USBIO by asserting PM.USB_CR0.fsusbio_pd_n(Inverted) and pd_pullup_hv(Inverted) high. */ + USBFS_PM_USB_CR0_REG &= + (uint8)~(USBFS_PM_USB_CR0_PD_N | USBFS_PM_USB_CR0_PD_PULLUP_N); + + /* Disable the SIE */ + USBFS_CR0_REG &= (uint8)~USBFS_CR0_ENABLE; + + CyDelayUs(0u); /* ~50ns delay */ + /* Store mode and Disable VRegulator*/ + USBFS_backup.mode = USBFS_CR1_REG & USBFS_CR1_REG_ENABLE; + USBFS_CR1_REG &= (uint8)~USBFS_CR1_REG_ENABLE; + + CyDelayUs(1u); /* 0.5 us min delay */ + /* Disable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG &= (uint8)~USBFS_PM_USB_CR0_REF_EN; + + /* Switch DP and DM terminals to GPIO mode and disconnect 1.5k pullup*/ + USBFS_USBIO_CR1_REG |= USBFS_USBIO_CR1_IOMODE; + + /* Disable USB in ACT PM */ + USBFS_PM_ACT_CFG_REG &= (uint8)~USBFS_PM_ACT_EN_FSUSB; + /* Disable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG &= (uint8)~USBFS_PM_STBY_EN_FSUSB; + CyDelayUs(1u); /* min 0.5us delay required */ + + } + else + { + USBFS_backup.enableState = 0u; + } + + CyExitCriticalSection(enableInterrupts); + + /* Set the DP Interrupt for wake-up from sleep mode. */ + #if(USBFS_DP_ISR_REMOVE == 0u) + (void) CyIntSetVector(USBFS_DP_INTC_VECT_NUM, &USBFS_DP_ISR); + CyIntSetPriority(USBFS_DP_INTC_VECT_NUM, USBFS_DP_INTC_PRIOR); + CyIntClearPending(USBFS_DP_INTC_VECT_NUM); + CyIntEnable(USBFS_DP_INTC_VECT_NUM); + #endif /* (USBFS_DP_ISR_REMOVE == 0u) */ +} + + +/******************************************************************************* +* Function Name: USBFS_Resume +******************************************************************************** +* +* Summary: +* This function enables the USBFS block after power down mode. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* USBFS_backup - checked. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Resume(void) +{ + uint8 enableInterrupts; + enableInterrupts = CyEnterCriticalSection(); + + if(USBFS_backup.enableState != 0u) + { + #if(USBFS_DP_ISR_REMOVE == 0u) + CyIntDisable(USBFS_DP_INTC_VECT_NUM); + #endif /* USBFS_DP_ISR_REMOVE */ + + /* Enable USB block */ + USBFS_PM_ACT_CFG_REG |= USBFS_PM_ACT_EN_FSUSB; + /* Enable USB block for Standby Power Mode */ + USBFS_PM_STBY_CFG_REG |= USBFS_PM_STBY_EN_FSUSB; + /* Enable core clock */ + USBFS_USB_CLK_EN_REG |= USBFS_USB_CLK_ENABLE; + + /* Enable the USBIO reference by setting PM.USB_CR0.fsusbio_ref_en.*/ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_REF_EN; + /* The reference will be available ~40us after power restored */ + CyDelayUs(40u); + /* Return VRegulator*/ + USBFS_CR1_REG |= USBFS_backup.mode; + CyDelayUs(0u); /*~50ns delay */ + /* Enable USBIO */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_N; + CyDelayUs(2u); + /* Set the USBIO pull-up enable */ + USBFS_PM_USB_CR0_REG |= USBFS_PM_USB_CR0_PD_PULLUP_N; + + /* Re-init Arbiter configuration for DMA transfers */ + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Usb arb interrupt enable */ + USBFS_ARB_INT_EN_REG = USBFS_ARB_INT_MASK; + #if(USBFS_EP_MM == USBFS__EP_DMAMANUAL) + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_MANUAL_DMA; + #endif /* USBFS_EP_MM == USBFS__EP_DMAMANUAL */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /*Set cfg cmplt this rises DMA request when the full configuration is done */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + /* STALL_IN_OUT */ + CY_SET_REG8(USBFS_EP0_CR_PTR, USBFS_MODE_STALL_IN_OUT); + /* Enable the SIE with a last address */ + USBFS_CR0_REG |= USBFS_CR0_ENABLE; + CyDelayCycles(1u); + /* Finally, Enable d+ pullup and select iomode to USB mode*/ + CY_SET_REG8(USBFS_USBIO_CR1_PTR, USBFS_USBIO_CR1_USBPUEN); + + /* Restore USB register settings */ + USBFS_RestoreConfig(); + } + + CyExitCriticalSection(enableInterrupts); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h new file mode 100644 index 0000000..a2f18c8 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_pvt.h @@ -0,0 +1,218 @@ +/******************************************************************************* +* File Name: .h +* Version 2.80 +* +* Description: +* This private file provides constants and parameter values for the +* USBFS Component. +* Please do not use this file or its content in your project. +* +* Note: +* +******************************************************************************** +* Copyright 2013-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_USBFS_USBFS_pvt_H) +#define CY_USBFS_USBFS_pvt_H + + +/*************************************** +* Private Variables +***************************************/ + +/* Generated external references for descriptors*/ +extern const uint8 CYCODE USBFS_DEVICE0_DESCR[18u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_DESCR[41u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_TABLE[1u]; +extern const T_USBFS_EP_SETTINGS_BLOCK CYCODE USBFS_DEVICE0_CONFIGURATION0_EP_SETTINGS_TABLE[2u]; +extern const uint8 CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE_CLASS[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_TABLE[4u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_TABLE[2u]; +extern const T_USBFS_LUT CYCODE USBFS_TABLE[1u]; +extern const uint8 CYCODE USBFS_SN_STRING_DESCRIPTOR[10]; +extern const uint8 CYCODE USBFS_STRING_DESCRIPTORS[83u]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_BUF_SIZE]; +extern T_USBFS_XFER_STATUS_BLOCK USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_SCB; +extern uint8 USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF[ + USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_BUF_SIZE]; +extern const uint8 CYCODE USBFS_HIDREPORT_DESCRIPTOR1[40u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_IN_RPT_TABLE[1u]; +extern const T_USBFS_TD CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_OUT_RPT_TABLE[1u]; +extern const T_USBFS_LUT CYCODE USBFS_DEVICE0_CONFIGURATION0_INTERFACE0_ALTERNATE0_HID_TABLE[5u]; + + +extern const uint8 CYCODE USBFS_MSOS_DESCRIPTOR[USBFS_MSOS_DESCRIPTOR_LENGTH]; +extern const uint8 CYCODE USBFS_MSOS_CONFIGURATION_DESCR[USBFS_MSOS_CONF_DESCR_LENGTH]; +#if defined(USBFS_ENABLE_IDSN_STRING) + extern uint8 USBFS_idSerialNumberStringDescriptor[USBFS_IDSN_DESCR_LENGTH]; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +extern volatile uint8 USBFS_interfaceNumber; +extern volatile uint8 USBFS_interfaceSetting[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_interfaceSetting_last[USBFS_MAX_INTERFACES_NUMBER]; +extern volatile uint8 USBFS_deviceAddress; +extern volatile uint8 USBFS_interfaceStatus[USBFS_MAX_INTERFACES_NUMBER]; +extern const uint8 CYCODE *USBFS_interfaceClass; + +extern volatile T_USBFS_EP_CTL_BLOCK USBFS_EP[USBFS_MAX_EP]; +extern volatile T_USBFS_TD USBFS_currentTD; + +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + extern uint8 USBFS_DmaChan[USBFS_MAX_EP]; + extern uint8 USBFS_DmaTd[USBFS_MAX_EP]; +#endif /* USBFS_EP_MM */ +#if((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + extern uint8 USBFS_DmaNextTd[USBFS_MAX_EP]; + extern const uint8 USBFS_epX_TD_TERMOUT_EN[USBFS_MAX_EP]; + extern volatile uint16 USBFS_inLength[USBFS_MAX_EP]; + extern const uint8 *USBFS_inDataPointer[USBFS_MAX_EP]; + extern volatile uint8 USBFS_inBufFull[USBFS_MAX_EP]; +#endif /* ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) */ + +extern volatile uint8 USBFS_ep0Toggle; +extern volatile uint8 USBFS_lastPacketSize; +extern volatile uint8 USBFS_ep0Mode; +extern volatile uint8 USBFS_ep0Count; +extern volatile uint16 USBFS_transferByteCount; + + +/*************************************** +* Private Function Prototypes +***************************************/ +void USBFS_ReInitComponent(void) ; +void USBFS_HandleSetup(void) ; +void USBFS_HandleIN(void) ; +void USBFS_HandleOUT(void) ; +void USBFS_LoadEP0(void) ; +uint8 USBFS_InitControlRead(void) ; +uint8 USBFS_InitControlWrite(void) ; +void USBFS_ControlReadDataStage(void) ; +void USBFS_ControlReadStatusStage(void) ; +void USBFS_ControlReadPrematureStatus(void) + ; +uint8 USBFS_InitControlWrite(void) ; +uint8 USBFS_InitZeroLengthControlTransfer(void) + ; +void USBFS_ControlWriteDataStage(void) ; +void USBFS_ControlWriteStatusStage(void) ; +void USBFS_ControlWritePrematureStatus(void) + ; +uint8 USBFS_InitNoDataControlTransfer(void) ; +void USBFS_NoDataControlStatusStage(void) ; +void USBFS_InitializeStatusBlock(void) ; +void USBFS_UpdateStatusBlock(uint8 completionCode) ; +uint8 USBFS_DispatchClassRqst(void) ; + +void USBFS_Config(uint8 clearAltSetting) ; +void USBFS_ConfigAltChanged(void) ; +void USBFS_ConfigReg(void) ; + +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) + ; +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + ; +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + ; +uint8 USBFS_ClearEndpointHalt(void) ; +uint8 USBFS_SetEndpointHalt(void) ; +uint8 USBFS_ValidateAlternateSetting(void) ; + +void USBFS_SaveConfig(void) ; +void USBFS_RestoreConfig(void) ; + +#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + void USBFS_LoadNextInEP(uint8 epNumber, uint8 mode) ; +#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ + +#if defined(USBFS_ENABLE_IDSN_STRING) + void USBFS_ReadDieID(uint8 descr[]) ; +#endif /* USBFS_ENABLE_IDSN_STRING */ + +#if defined(USBFS_ENABLE_HID_CLASS) + uint8 USBFS_DispatchHIDClassRqst(void); +#endif /* USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_AUDIO_CLASS) + uint8 USBFS_DispatchAUDIOClassRqst(void); +#endif /* USBFS_ENABLE_HID_CLASS */ +#if defined(USBFS_ENABLE_CDC_CLASS) + uint8 USBFS_DispatchCDCClassRqst(void); +#endif /* USBFS_ENABLE_CDC_CLASS */ + +CY_ISR_PROTO(USBFS_EP_0_ISR); +#if(USBFS_EP1_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_1_ISR); +#endif /* USBFS_EP1_ISR_REMOVE */ +#if(USBFS_EP2_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_2_ISR); +#endif /* USBFS_EP2_ISR_REMOVE */ +#if(USBFS_EP3_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_3_ISR); +#endif /* USBFS_EP3_ISR_REMOVE */ +#if(USBFS_EP4_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_4_ISR); +#endif /* USBFS_EP4_ISR_REMOVE */ +#if(USBFS_EP5_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_5_ISR); +#endif /* USBFS_EP5_ISR_REMOVE */ +#if(USBFS_EP6_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_6_ISR); +#endif /* USBFS_EP6_ISR_REMOVE */ +#if(USBFS_EP7_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_7_ISR); +#endif /* USBFS_EP7_ISR_REMOVE */ +#if(USBFS_EP8_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_EP_8_ISR); +#endif /* USBFS_EP8_ISR_REMOVE */ +CY_ISR_PROTO(USBFS_BUS_RESET_ISR); +#if(USBFS_SOF_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_SOF_ISR); +#endif /* USBFS_SOF_ISR_REMOVE */ +#if(USBFS_EP_MM != USBFS__EP_MANUAL) + CY_ISR_PROTO(USBFS_ARB_ISR); +#endif /* USBFS_EP_MM */ +#if(USBFS_DP_ISR_REMOVE == 0u) + CY_ISR_PROTO(USBFS_DP_ISR); +#endif /* USBFS_DP_ISR_REMOVE */ +#if ((USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u)) + CY_ISR_PROTO(USBFS_EP_DMA_DONE_ISR); +#endif /* (USBFS_EP_MM == USBFS__EP_DMAAUTO) && (USBFS_EP_DMA_AUTO_OPT == 0u) */ + +/*************************************** +* Request Handlers +***************************************/ + +uint8 USBFS_HandleStandardRqst(void) ; +uint8 USBFS_DispatchClassRqst(void) ; +uint8 USBFS_HandleVendorRqst(void) ; + + +/*************************************** +* HID Internal references +***************************************/ + +#if defined(USBFS_ENABLE_HID_CLASS) + void USBFS_FindReport(void) ; + void USBFS_FindReportDescriptor(void) ; + void USBFS_FindHidClassDecriptor(void) ; +#endif /* USBFS_ENABLE_HID_CLASS */ + + +/*************************************** +* MIDI Internal references +***************************************/ + +#if defined(USBFS_ENABLE_MIDI_STREAMING) + void USBFS_MIDI_IN_EP_Service(void) ; +#endif /* USBFS_ENABLE_MIDI_STREAMING */ + + +#endif /* CY_USBFS_USBFS_pvt_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c new file mode 100644 index 0000000..0a177d2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_std.c @@ -0,0 +1,1174 @@ +/******************************************************************************* +* File Name: USBFS_std.c +* Version 2.80 +* +* Description: +* USB Standard request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_cdc.h" +#include "USBFS_pvt.h" +#if defined(USBFS_ENABLE_MIDI_STREAMING) + #include "USBFS_midi.h" +#endif /* USBFS_ENABLE_MIDI_STREAMING*/ + + +/*************************************** +* Static data allocation +***************************************/ + +#if defined(USBFS_ENABLE_FWSN_STRING) + static volatile uint8 *USBFS_fwSerialNumberStringDescriptor; + static volatile uint8 USBFS_snStringConfirm = USBFS_FALSE; +#endif /* USBFS_ENABLE_FWSN_STRING */ + +#if defined(USBFS_ENABLE_FWSN_STRING) + + /******************************************************************************* + * Function Name: USBFS_SerialNumString + ******************************************************************************** + * + * Summary: + * Application firmware may supply the source of the USB device descriptors + * serial number string during runtime. + * + * Parameters: + * snString: pointer to string. + * + * Return: + * None. + * + * Reentrant: + * No. + * + *******************************************************************************/ + void USBFS_SerialNumString(uint8 snString[]) + { + USBFS_snStringConfirm = USBFS_FALSE; + if(snString != NULL) + { + /* Check descriptor validation */ + if( (snString[0u] > 1u ) && (snString[1u] == USBFS_DESCR_STRING) ) + { + USBFS_fwSerialNumberStringDescriptor = snString; + USBFS_snStringConfirm = USBFS_TRUE; + } + } + } + +#endif /* USBFS_ENABLE_FWSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_HandleStandardRqst +******************************************************************************** +* +* Summary: +* This Routine dispatches standard requests +* +* Parameters: +* None. +* +* Return: +* TRUE if request handled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleStandardRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + uint8 interfaceNumber; + uint8 configurationN; + #if defined(USBFS_ENABLE_STRINGS) + volatile uint8 *pStr = 0u; + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + uint8 nStr; + uint8 descrLength; + #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ + #endif /* USBFS_ENABLE_STRINGS */ + static volatile uint8 USBFS_tBuffer[USBFS_STATUS_LENGTH_MAX]; + const T_USBFS_LUT CYCODE *pTmp; + USBFS_currentTD.count = 0u; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_DESCRIPTOR: + if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_DEVICE) + { + pTmp = USBFS_GetDeviceTablePtr(); + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = USBFS_DEVICE_DESCR_LENGTH; + requestHandled = USBFS_InitControlRead(); + } + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_CONFIG) + { + pTmp = USBFS_GetConfigTablePtr(CY_GET_REG8(USBFS_wValueLo)); + if( pTmp != NULL ) /* Verify that requested descriptor exists */ + { + USBFS_currentTD.pData = (volatile uint8 *)pTmp->p_list; + USBFS_currentTD.count = ((uint16)(USBFS_currentTD.pData)[ \ + USBFS_CONFIG_DESCR_TOTAL_LENGTH_HI] << 8u) | \ + (USBFS_currentTD.pData)[USBFS_CONFIG_DESCR_TOTAL_LENGTH_LOW]; + requestHandled = USBFS_InitControlRead(); + } + } + #if defined(USBFS_ENABLE_STRINGS) + else if (CY_GET_REG8(USBFS_wValueHi) == USBFS_DESCR_STRING) + { + /* Descriptor Strings*/ + #if defined(USBFS_ENABLE_DESCRIPTOR_STRINGS) + nStr = 0u; + pStr = (volatile uint8 *)&USBFS_STRING_DESCRIPTORS[0u]; + while ( (CY_GET_REG8(USBFS_wValueLo) > nStr) && (*pStr != 0u) ) + { + /* Read descriptor length from 1st byte */ + descrLength = *pStr; + /* Move to next string descriptor */ + pStr = &pStr[descrLength]; + nStr++; + } + #endif /* USBFS_ENABLE_DESCRIPTOR_STRINGS */ + /* Microsoft OS String*/ + #if defined(USBFS_ENABLE_MSOS_STRING) + if( CY_GET_REG8(USBFS_wValueLo) == USBFS_STRING_MSOS ) + { + pStr = (volatile uint8 *)&USBFS_MSOS_DESCRIPTOR[0u]; + } + #endif /* USBFS_ENABLE_MSOS_STRING*/ + /* SN string */ + #if defined(USBFS_ENABLE_SN_STRING) + if( (CY_GET_REG8(USBFS_wValueLo) != 0u) && + (CY_GET_REG8(USBFS_wValueLo) == + USBFS_DEVICE0_DESCR[USBFS_DEVICE_DESCR_SN_SHIFT]) ) + { + + #if defined(USBFS_ENABLE_IDSN_STRING) + /* Read DIE ID and generate string descriptor in RAM */ + USBFS_ReadDieID(USBFS_idSerialNumberStringDescriptor); + pStr = USBFS_idSerialNumberStringDescriptor; + #elif defined(USBFS_ENABLE_FWSN_STRING) + if(USBFS_snStringConfirm != USBFS_FALSE) + { + pStr = USBFS_fwSerialNumberStringDescriptor; + } + else + { + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + } + #else + pStr = (volatile uint8 *)&USBFS_SN_STRING_DESCRIPTOR[0u]; + #endif /* defined(USBFS_ENABLE_IDSN_STRING) */ + } + #endif /* USBFS_ENABLE_SN_STRING */ + if (*pStr != 0u) + { + USBFS_currentTD.count = *pStr; + USBFS_currentTD.pData = pStr; + requestHandled = USBFS_InitControlRead(); + } + } + #endif /* USBFS_ENABLE_STRINGS */ + else + { + requestHandled = USBFS_DispatchClassRqst(); + } + break; + case USBFS_GET_STATUS: + switch ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK)) + { + case USBFS_RQST_RCPT_EP: + USBFS_currentTD.count = USBFS_EP_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_EP[ \ + CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED].hwEpState; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_RQST_RCPT_DEV: + USBFS_currentTD.count = USBFS_DEVICE_STATUS_LENGTH; + USBFS_tBuffer[0u] = USBFS_deviceStatus; + USBFS_tBuffer[1u] = 0u; + USBFS_currentTD.pData = &USBFS_tBuffer[0u]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_GET_CONFIGURATION: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_configuration; + requestHandled = USBFS_InitControlRead(); + break; + case USBFS_GET_INTERFACE: + USBFS_currentTD.count = 1u; + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_interfaceSetting[ \ + CY_GET_REG8(USBFS_wIndexLo)]; + requestHandled = USBFS_InitControlRead(); + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + else { + /* Control Write */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_SET_ADDRESS: + USBFS_deviceAddress = CY_GET_REG8(USBFS_wValueLo); + requestHandled = USBFS_InitNoDataControlTransfer(); + break; + case USBFS_SET_CONFIGURATION: + configurationN = CY_GET_REG8(USBFS_wValueLo); + if(configurationN > 0u) + { /* Verify that configuration descriptor exists */ + pTmp = USBFS_GetConfigTablePtr(configurationN - 1u); + } + /* Responds with a Request Error when configuration number is invalid */ + if (((configurationN > 0u) && (pTmp != NULL)) || (configurationN == 0u)) + { + /* Set new configuration if it has been changed */ + if(configurationN != USBFS_configuration) + { + USBFS_configuration = configurationN; + USBFS_configurationChanged = USBFS_TRUE; + USBFS_Config(USBFS_TRUE); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_SET_INTERFACE: + if (USBFS_ValidateAlternateSetting() != 0u) + { + interfaceNumber = CY_GET_REG8(USBFS_wIndexLo); + USBFS_interfaceNumber = interfaceNumber; + USBFS_configurationChanged = USBFS_TRUE; + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + USBFS_Config(USBFS_FALSE); + #else + USBFS_ConfigAltChanged(); + #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + /* Update handled Alt setting changes status */ + USBFS_interfaceSetting_last[interfaceNumber] = + USBFS_interfaceSetting[interfaceNumber]; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_CLEAR_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_ClearEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Clear device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + case USBFS_SET_FEATURE: + switch (CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_RCPT_MASK) + { + case USBFS_RQST_RCPT_EP: + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_ENDPOINT_HALT) + { + requestHandled = USBFS_SetEndpointHalt(); + } + break; + case USBFS_RQST_RCPT_DEV: + /* Set device REMOTE_WAKEUP */ + if (CY_GET_REG8(USBFS_wValueLo) == USBFS_DEVICE_REMOTE_WAKEUP) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_REMOTE_WAKEUP; + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + case USBFS_RQST_RCPT_IFC: + /* Validate interfaceNumber */ + if (CY_GET_REG8(USBFS_wIndexLo) < USBFS_MAX_INTERFACES_NUMBER) + { + USBFS_interfaceStatus[CY_GET_REG8(USBFS_wIndexLo)] &= + (uint8)~(CY_GET_REG8(USBFS_wValueLo)); + requestHandled = USBFS_InitNoDataControlTransfer(); + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + break; + default: /* requestHandled is initialized as FALSE by default */ + break; + } + } + return(requestHandled); +} + + +#if defined(USBFS_ENABLE_IDSN_STRING) + + /*************************************************************************** + * Function Name: USBFS_ReadDieID + **************************************************************************** + * + * Summary: + * This routine read Die ID and generate Serial Number string descriptor. + * + * Parameters: + * descr: pointer on string descriptor. + * + * Return: + * None. + * + * Reentrant: + * No. + * + ***************************************************************************/ + void USBFS_ReadDieID(uint8 descr[]) + { + uint8 i; + uint8 j = 0u; + uint8 value; + const char8 CYCODE hex[16u] = "0123456789ABCDEF"; + + /* Check descriptor validation */ + if( descr != NULL) + { + descr[0u] = USBFS_IDSN_DESCR_LENGTH; + descr[1u] = USBFS_DESCR_STRING; + + /* fill descriptor */ + for(i = 2u; i < USBFS_IDSN_DESCR_LENGTH; i += 4u) + { + value = CY_GET_XTND_REG8((void CYFAR *)(USBFS_DIE_ID + j)); + j++; + descr[i] = (uint8)hex[value >> 4u]; + descr[i + 2u] = (uint8)hex[value & 0x0Fu]; + } + } + } + +#endif /* USBFS_ENABLE_IDSN_STRING */ + + +/******************************************************************************* +* Function Name: USBFS_ConfigReg +******************************************************************************** +* +* Summary: +* This routine configures hardware registers from the variables. +* It is called from USBFS_Config() function and from RestoreConfig +* after Wakeup. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void USBFS_ConfigReg(void) +{ + uint8 ep; + uint8 i; + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + uint8 epType = 0u; + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + /* Set the endpoint buffer addresses */ + ep = USBFS_EP1; + for (i = 0u; i < 0x80u; i+= 0x10u) + { + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_CFG_IND + i), USBFS_ARB_EPX_CFG_DEFAULT); + #if(USBFS_EP_MM != USBFS__EP_MANUAL) + /* Enable all Arbiter EP Interrupts : err, buf under, buf over, dma gnt(mode2 only), in buf full */ + CY_SET_REG8((reg8 *)(USBFS_ARB_EP1_INT_EN_IND + i), USBFS_ARB_EPX_INT_MASK); + #endif /* USBFS_EP_MM != USBFS__EP_MANUAL */ + + if(USBFS_EP[ep].epMode != USBFS_MODE_DISABLE) + { + if((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u ) + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_IN); + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_NAK_OUT); + /* Prepare EP type mask for automatic memory allocation */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + epType |= (uint8)(0x01u << (ep - USBFS_EP1)); + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + else + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + i), USBFS_MODE_STALL_DATA_EP); + } + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + i), USBFS_EP[ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + i), USBFS_EP[ep].bufferSize & 0xFFu); + + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + i), USBFS_EP[ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + i), USBFS_EP[ep].buffOffset >> 8u); + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + ep++; + } + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* BUF_SIZE depend on DMA_THRESS value: 55-32 bytes 44-16 bytes 33-8 bytes 22-4 bytes 11-2 bytes */ + USBFS_BUF_SIZE_REG = USBFS_DMA_BUF_SIZE; + USBFS_DMA_THRES_REG = USBFS_DMA_BYTES_PER_BURST; /* DMA burst threshold */ + USBFS_DMA_THRES_MSB_REG = 0u; + USBFS_EP_ACTIVE_REG = USBFS_ARB_INT_MASK; + USBFS_EP_TYPE_REG = epType; + /* Cfg_cmp bit set to 1 once configuration is complete. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM | + USBFS_ARB_CFG_CFG_CPM; + /* Cfg_cmp bit set to 0 during configuration of PFSUSB Registers. */ + USBFS_ARB_CFG_REG = USBFS_ARB_CFG_AUTO_DMA | USBFS_ARB_CFG_AUTO_MEM; + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + + CY_SET_REG8(USBFS_SIE_EP_INT_EN_PTR, 0xFFu); +} + + +/******************************************************************************* +* Function Name: USBFS_Config +******************************************************************************** +* +* Summary: +* This routine configures endpoints for the entire configuration by scanning +* the configuration descriptor. +* +* Parameters: +* clearAltSetting: It configures the bAlternateSetting 0 for each interface. +* +* Return: +* None. +* +* USBFS_interfaceClass - Initialized class array for each interface. +* It is used for handling Class specific requests depend on interface class. +* Different classes in multiple Alternate settings does not supported. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_Config(uint8 clearAltSetting) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 epType; + const uint8 *pDescr; + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + uint16 buffCount = 0u; + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + /* Clear all of the endpoints */ + for (ep = 0u; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].attrib = 0u; + USBFS_EP[ep].hwEpState = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].epMode = USBFS_MODE_DISABLE; + USBFS_EP[ep].bufferSize = 0u; + USBFS_EP[ep].interface = 0u; + + } + + /* Clear Alternate settings for all interfaces */ + if(clearAltSetting != 0u) + { + for (i = 0u; i < USBFS_MAX_INTERFACES_NUMBER; i++) + { + USBFS_interfaceSetting[i] = 0x00u; + USBFS_interfaceSetting_last[i] = 0x00u; + } + } + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + /* Set Power status for current configuration */ + pDescr = (const uint8 *)pTmp->p_list; + if((pDescr[USBFS_CONFIG_DESCR_ATTRIB] & USBFS_CONFIG_DESCR_ATTRIB_SELF_POWERED) != 0u) + { + USBFS_deviceStatus |= USBFS_DEVICE_STATUS_SELF_POWERED; + } + else + { + USBFS_deviceStatus &= (uint8)~USBFS_DEVICE_STATUS_SELF_POWERED; + } + /* Move to next element */ + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + #if ((USBFS_EP_MA == USBFS__MA_DYNAMIC) && \ + (USBFS_EP_MM == USBFS__EP_MANUAL) ) + /* Configure for dynamic EP memory allocation */ + /* p_list points the endpoint setting table. */ + pEP = (T_USBFS_EP_SETTINGS_BLOCK *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Compare current Alternate setting with EP Alt */ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + if (pEP->addr & USBFS_DIR_IN) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (epType != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = cur_ep; + } + #endif /* USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = cur_ep; + } + #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (epType != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = cur_ep; + } + #endif /* USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = cur_ep; + } + #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + } + pEP = &pEP[1u]; + } + #else /* Configure for static EP memory allocation */ + for (i = USBFS_EP1; i < USBFS_MAX_EP; i++) + { + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + /* Find max length for each EP and select it (length could be different in different Alt settings) */ + /* but other settings should be correct with regards to Interface alt Setting */ + for (cur_ep = 0u; cur_ep < ep; cur_ep++) + { + /* EP count is equal to EP # in table and we found larger EP length than have before*/ + if(i == (pEP->addr & USBFS_DIR_UNUSED)) + { + if(USBFS_EP[i].bufferSize < pEP->bufferSize) + { + USBFS_EP[i].bufferSize = pEP->bufferSize; + } + /* Compare current Alternate setting with EP Alt*/ + if(USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) + { + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[i].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + /* Find and initialize CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (epType != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_in_ep = i; + } + #endif /* USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_IN_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_in_ep = i; + } + #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + } + else + { + /* OUT Endpoint */ + USBFS_EP[i].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[i].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + /* Find and initialize CDC IN endpoint number */ + #if defined(USBFS_ENABLE_CDC_CLASS) + if(((pEP->bMisc == USBFS_CLASS_CDC_DATA) || + (pEP->bMisc == USBFS_CLASS_CDC)) && + (epType != USBFS_EP_TYPE_INT)) + { + USBFS_cdc_data_out_ep = i; + } + #endif /* USBFS_ENABLE_CDC_CLASS*/ + #if ( defined(USBFS_ENABLE_MIDI_STREAMING) && \ + (USBFS_MIDI_OUT_BUFF_SIZE > 0) ) + if((pEP->bMisc == USBFS_CLASS_AUDIO) && + (epType == USBFS_EP_TYPE_BULK)) + { + USBFS_midi_out_ep = i; + } + #endif /* USBFS_ENABLE_MIDI_STREAMING*/ + } + USBFS_EP[i].addr = pEP->addr; + USBFS_EP[i].attrib = pEP->attributes; + + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + break; /* use first EP setting in Auto memory managment */ + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + } + pEP = &pEP[1u]; + } + } + #endif /* (USBFS_EP_MA == USBFS__MA_DYNAMIC) */ + + /* Init class array for each interface and interface number for each EP. + * It is used for handling Class specific requests directed to either an + * interface or the endpoint. + */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /* Configure interface number for each EP*/ + USBFS_EP[pEP->addr & USBFS_DIR_UNUSED].interface = pEP->interface; + pEP = &pEP[1u]; + } + /* Init pointer on interface class table*/ + USBFS_interfaceClass = USBFS_GetInterfaceClassTablePtr(); + /* Set the endpoint buffer addresses */ + + #if(USBFS_EP_MM != USBFS__EP_DMAAUTO) + for (ep = USBFS_EP1; ep < USBFS_MAX_EP; ep++) + { + USBFS_EP[ep].buffOffset = buffCount; + buffCount += USBFS_EP[ep].bufferSize; + } + #endif /* USBFS_EP_MM != USBFS__EP_DMAAUTO */ + + /* Configure hardware registers */ + USBFS_ConfigReg(); + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_ConfigAltChanged +******************************************************************************** +* +* Summary: +* This routine update configuration for the required endpoints only. +* It is called after SET_INTERFACE request when Static memory allocation used. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_ConfigAltChanged(void) +{ + uint8 ep; + uint8 cur_ep; + uint8 i; + uint8 epType; + uint8 ri; + + const T_USBFS_LUT CYCODE *pTmp; + const T_USBFS_EP_SETTINGS_BLOCK CYCODE *pEP; + + + /* Init Endpoints and Device Status if configured */ + if(USBFS_configuration > 0u) + { + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + pTmp = &pTmp[1u]; + ep = pTmp->c; /* For this table, c is the number of endpoints configurations */ + + /* Do not touch EP which doesn't need reconfiguration */ + /* When Alt setting changed, the only required endpoints need to be reconfigured */ + /* p_list points the endpoint setting table. */ + pEP = (const T_USBFS_EP_SETTINGS_BLOCK CYCODE *) pTmp->p_list; + for (i = 0u; i < ep; i++) + { + /*If Alt setting changed and new is same with EP Alt */ + if((USBFS_interfaceSetting[pEP->interface] != + USBFS_interfaceSetting_last[pEP->interface] ) && + (USBFS_interfaceSetting[pEP->interface] == pEP->altSetting) && + (pEP->interface == CY_GET_REG8(USBFS_wIndexLo))) + { + cur_ep = pEP->addr & USBFS_DIR_UNUSED; + ri = ((cur_ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + epType = pEP->attributes & USBFS_EP_TYPE_MASK; + if ((pEP->addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_IN : USBFS_MODE_ACK_IN; + } + else + { + /* OUT Endpoint */ + USBFS_EP[cur_ep].apiEpState = USBFS_NO_EVENT_PENDING; + USBFS_EP[cur_ep].epMode = (epType == USBFS_EP_TYPE_ISOC) ? + USBFS_MODE_ISO_OUT : USBFS_MODE_ACK_OUT; + } + /* Change the SIE mode for the selected EP to NAK ALL */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN_OUT); + USBFS_EP[cur_ep].bufferSize = pEP->bufferSize; + USBFS_EP[cur_ep].addr = pEP->addr; + USBFS_EP[cur_ep].attrib = pEP->attributes; + + /* Clear the data toggle */ + USBFS_EP[cur_ep].epToggle = 0u; + + /* Dynamic reconfiguration for mode 3 transfer */ + #if(USBFS_EP_MM == USBFS__EP_DMAAUTO) + /* In_data_rdy for selected EP should be set to 0 */ + * (reg8 *)(USBFS_ARB_EP1_CFG_IND + ri) &= (uint8)~USBFS_ARB_EPX_CFG_IN_DATA_RDY; + + /* write the EP number for which reconfiguration is required */ + USBFS_DYN_RECONFIG_REG = (cur_ep - USBFS_EP1) << + USBFS_DYN_RECONFIG_EP_SHIFT; + /* Set the dyn_config_en bit in dynamic reconfiguration register */ + USBFS_DYN_RECONFIG_REG |= USBFS_DYN_RECONFIG_ENABLE; + /* wait for the dyn_config_rdy bit to set by the block, + * this bit will be set to 1 when block is ready for reconfiguration. + */ + while((USBFS_DYN_RECONFIG_REG & USBFS_DYN_RECONFIG_RDY_STS) == 0u) + { + ; + } + /* Once dyn_config_rdy bit is set, FW can change the EP configuration. */ + /* Change EP Type with new direction */ + if((pEP->addr & USBFS_DIR_IN) == 0u) + { + USBFS_EP_TYPE_REG |= (uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + else + { + USBFS_EP_TYPE_REG &= (uint8)~(uint8)(0x01u << (cur_ep - USBFS_EP1)); + } + /* dynamic reconfiguration enable bit cleared, pointers and control/status + * signals for the selected EP is cleared/re-initialized on negative edge + * of dynamic reconfiguration enable bit). + */ + USBFS_DYN_RECONFIG_REG &= (uint8)~USBFS_DYN_RECONFIG_ENABLE; + /* The main loop has to re-enable DMA and OUT endpoint*/ + #else + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), + USBFS_EP[cur_ep].bufferSize >> 8u); + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT1_IND + ri), + USBFS_EP[cur_ep].bufferSize & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_RA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_IND + ri), + USBFS_EP[cur_ep].buffOffset & 0xFFu); + CY_SET_REG8((reg8 *)(USBFS_ARB_RW1_WA_MSB_IND + ri), + USBFS_EP[cur_ep].buffOffset >> 8u); + #endif /* USBFS_EP_MM == USBFS__EP_DMAAUTO */ + } + /* Get next EP element */ + pEP = &pEP[1u]; + } + } /* USBFS_configuration > 0 */ +} + + +/******************************************************************************* +* Function Name: USBFS_GetConfigTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer a configuration table entry +* +* Parameters: +* confIndex: Configuration Index +* +* Return: +* Device Descriptor pointer or NULL when descriptor isn't exists. +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetConfigTablePtr(uint8 confIndex) + +{ + /* Device Table */ + const T_USBFS_LUT CYCODE *pTmp; + + pTmp = (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list; + + /* The first entry points to the Device Descriptor, + * the rest configuration entries. + * Set pointer to the first Configuration Descriptor + */ + pTmp = &pTmp[1u]; + /* For this table, c is the number of configuration descriptors */ + if(confIndex >= pTmp->c) /* Verify that required configuration descriptor exists */ + { + pTmp = (const T_USBFS_LUT CYCODE *) NULL; + } + else + { + pTmp = (const T_USBFS_LUT CYCODE *) pTmp[confIndex].p_list; + } + + return( pTmp ); +} + + +/******************************************************************************* +* Function Name: USBFS_GetDeviceTablePtr +******************************************************************************** +* +* Summary: +* This routine returns a pointer to the Device table +* +* Parameters: +* None. +* +* Return: +* Device Table pointer +* +*******************************************************************************/ +const T_USBFS_LUT CYCODE *USBFS_GetDeviceTablePtr(void) + +{ + /* Device Table */ + return( (const T_USBFS_LUT CYCODE *) USBFS_TABLE[USBFS_device].p_list ); +} + + +/******************************************************************************* +* Function Name: USB_GetInterfaceClassTablePtr +******************************************************************************** +* +* Summary: +* This routine returns Interface Class table pointer, which contains +* the relation between interface number and interface class. +* +* Parameters: +* None. +* +* Return: +* Interface Class table pointer. +* +*******************************************************************************/ +const uint8 CYCODE *USBFS_GetInterfaceClassTablePtr(void) + +{ + const T_USBFS_LUT CYCODE *pTmp; + const uint8 CYCODE *pInterfaceClass; + uint8 currentInterfacesNum; + + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + if( pTmp != NULL ) + { + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + /* Third entry in the LUT starts the Interface Table pointers */ + /* The INTERFACE_CLASS table is located after all interfaces */ + pTmp = &pTmp[currentInterfacesNum + 2u]; + pInterfaceClass = (const uint8 CYCODE *) pTmp->p_list; + } + else + { + pInterfaceClass = (const uint8 CYCODE *) NULL; + } + + return( pInterfaceClass ); +} + + +/******************************************************************************* +* Function Name: USBFS_TerminateEP +******************************************************************************** +* +* Summary: +* This function terminates the specified USBFS endpoint. +* This function should be used before endpoint reconfiguration. +* +* Parameters: +* Endpoint number. +* +* Return: +* None. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void USBFS_TerminateEP(uint8 ep) +{ + uint8 ri; + + ep &= USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState = USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + } +} + + +/******************************************************************************* +* Function Name: USBFS_SetEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles set endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_SetEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Set endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Set the endpoint Halt */ + USBFS_EP[ep].hwEpState |= (USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + USBFS_EP[ep].apiEpState |= USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_IN); + } + else + { + /* OUT Endpoint */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_STALL_DATA_EP | + USBFS_MODE_ACK_OUT); + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ClearEndpointHalt +******************************************************************************** +* +* Summary: +* This routine handles clear endpoint halt. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ClearEndpointHalt(void) +{ + uint8 ep; + uint8 ri; + uint8 requestHandled = USBFS_FALSE; + + /* Clear endpoint halt */ + ep = CY_GET_REG8(USBFS_wIndexLo) & USBFS_DIR_UNUSED; + ri = ((ep - USBFS_EP1) << USBFS_EPX_CNTX_ADDR_SHIFT); + + if ((ep > USBFS_EP0) && (ep < USBFS_MAX_EP)) + { + /* Clear the endpoint Halt */ + USBFS_EP[ep].hwEpState &= (uint8)~(USBFS_ENDPOINT_STATUS_HALT); + + /* Clear the data toggle */ + USBFS_EP[ep].epToggle = 0u; + /* Clear toggle bit for already armed packet */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri), CY_GET_REG8( + (reg8 *)(USBFS_SIE_EP1_CNT0_IND + ri)) & (uint8)~USBFS_EPX_CNT_DATA_TOGGLE); + /* Return API State as it was defined before */ + USBFS_EP[ep].apiEpState &= (uint8)~USBFS_NO_EVENT_ALLOWED; + + if ((USBFS_EP[ep].addr & USBFS_DIR_IN) != 0u) + { + /* IN Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_IN_BUFFER_EMPTY) + { /* Wait for next packet from application */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_IN); + } + else /* Continue armed transfer */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_IN); + } + } + else + { + /* OUT Endpoint */ + if(USBFS_EP[ep].apiEpState == USBFS_OUT_BUFFER_FULL) + { /* Allow application to read full buffer */ + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_NAK_OUT); + } + else /* Mark endpoint as empty, so it will be reloaded */ + { + CY_SET_REG8((reg8 *)(USBFS_SIE_EP1_CR0_IND + ri), USBFS_MODE_ACK_OUT); + } + } + requestHandled = USBFS_InitNoDataControlTransfer(); + } + + return(requestHandled); +} + + +/******************************************************************************* +* Function Name: USBFS_ValidateAlternateSetting +******************************************************************************** +* +* Summary: +* Validates (and records) a SET INTERFACE request. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_ValidateAlternateSetting(void) +{ + uint8 requestHandled = USBFS_TRUE; + uint8 interfaceNum; + const T_USBFS_LUT CYCODE *pTmp; + uint8 currentInterfacesNum; + + interfaceNum = CY_GET_REG8(USBFS_wIndexLo); + /* Validate interface setting, stall if invalid. */ + pTmp = USBFS_GetConfigTablePtr(USBFS_configuration - 1u); + currentInterfacesNum = ((const uint8 *) pTmp->p_list)[USBFS_CONFIG_DESCR_NUM_INTERFACES]; + + if((interfaceNum >= currentInterfacesNum) || (interfaceNum >= USBFS_MAX_INTERFACES_NUMBER)) + { /* Wrong interface number */ + requestHandled = USBFS_FALSE; + } + else + { + /* Save current Alt setting to find out the difference in Config() function */ + USBFS_interfaceSetting_last[interfaceNum] = USBFS_interfaceSetting[interfaceNum]; + USBFS_interfaceSetting[interfaceNum] = CY_GET_REG8(USBFS_wValueLo); + } + + return (requestHandled); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c new file mode 100644 index 0000000..6f61e5e --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/USBFS_vnd.c @@ -0,0 +1,100 @@ +/******************************************************************************* +* File Name: USBFS_vnd.c +* Version 2.80 +* +* Description: +* USB vendor request handler. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "USBFS.h" +#include "USBFS_pvt.h" + + +#if(USBFS_EXTERN_VND == USBFS_FALSE) + + +/*************************************** +* Vendor Specific Declarations +***************************************/ + +/* `#START VENDOR_SPECIFIC_DECLARATIONS` Place your declaration here */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: USBFS_HandleVendorRqst +******************************************************************************** +* +* Summary: +* This routine provide users with a method to implement vendor specific +* requests. +* +* To implement vendor specific requests, add your code in this function to +* decode and disposition the request. If the request is handled, your code +* must set the variable "requestHandled" to TRUE, indicating that the +* request has been handled. +* +* Parameters: +* None. +* +* Return: +* requestHandled. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 USBFS_HandleVendorRqst(void) +{ + uint8 requestHandled = USBFS_FALSE; + + if ((CY_GET_REG8(USBFS_bmRequestType) & USBFS_RQST_DIR_MASK) == USBFS_RQST_DIR_D2H) + { + /* Control Read */ + switch (CY_GET_REG8(USBFS_bRequest)) + { + case USBFS_GET_EXTENDED_CONFIG_DESCRIPTOR: + #if defined(USBFS_ENABLE_MSOS_STRING) + USBFS_currentTD.pData = (volatile uint8 *)&USBFS_MSOS_CONFIGURATION_DESCR[0u]; + USBFS_currentTD.count = USBFS_MSOS_CONFIGURATION_DESCR[0u]; + requestHandled = USBFS_InitControlRead(); + #endif /* USBFS_ENABLE_MSOS_STRING */ + break; + default: + break; + } + } + + /* `#START VENDOR_SPECIFIC_CODE` Place your vendor specific request here */ + + /* `#END` */ + + #ifdef USBFS_HANDLE_VENDOR_RQST_CALLBACK + USBFS_HandleVendorRqst_Callback(); + #endif /* USBFS_HANDLE_VENDOR_RQST_CALLBACK */ + + return(requestHandled); +} + + +/******************************************************************************* +* Additional user functions supporting Vendor Specific Requests +********************************************************************************/ + +/* `#START VENDOR_SPECIFIC_FUNCTIONS` Place any additional functions here */ + +/* `#END` */ + +#endif /* USBFS_EXTERN_VND */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld new file mode 100644 index 0000000..6972232 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cm3gcc.ld @@ -0,0 +1,295 @@ +/* Linker script for ARM M-profile Simulator + * + * Version: Sourcery G++ Lite 2010q1-188 + * Support: https://support.codesourcery.com/GNUToolchain/ + * + * Copyright (c) 2007, 2008, 2009, 2010 CodeSourcery, Inc. + * + * The authors hereby grant permission to use, copy, modify, distribute, + * and license this software and its documentation for any purpose, provided + * that existing copyright notices are retained in all copies and that this + * notice is included verbatim in any distributions. No written agreement, + * license, or royalty fee is required for any of the authorized uses. + * Modifications to this software may be copyrighted by their authors + * and need not follow the licensing terms described here, provided that + * the new terms are clearly indicated on the first page of each file where + * they apply. + */ +OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") +ENTRY(__cy_reset) +SEARCH_DIR(.) +GROUP(-lgcc -lc -lnosys) + + +MEMORY +{ + rom (rx) : ORIGIN = 0x0, LENGTH = 131072 + ram (rwx) : ORIGIN = 0x20000000 - (32768 / 2), LENGTH = 32768 +} + + +CY_APPL_ORIGIN = 0; +CY_FLASH_ROW_SIZE = 256; +CY_ECC_ROW_SIZE = 32; +CY_EE_IN_BTLDR = 0x0; +CY_APPL_LOADABLE = 0; +CY_EE_SIZE = 2048; +CY_APPL_NUM = 1; +CY_APPL_MAX = 1; +CY_METADATA_SIZE = 64; + + +/* These force the linker to search for particular symbols from + * the start of the link process and thus ensure the user's + * overrides are picked up + */ +EXTERN(Reset) + +/* Bring in interrupt routines & vector */ +EXTERN(main) + +/* Bring in meta data */ +EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader) +EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata) + +/* Provide fall-back values */ +PROVIDE(__cy_heap_start = _end); +PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16); +PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram)); +PROVIDE(__cy_heap_end = __cy_stack - 0x2000); + + +SECTIONS +{ + /* The bootloader location */ + .cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom + + /* Calculate where the loadables should start */ + appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE); + appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE); + appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start; + ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE; + ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0; + ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE; + PROVIDE(CY_ECC_OFFSET = ecc_offset); + + .text appl_start : + { + CREATE_OBJECT_SYMBOLS + PROVIDE(__cy_interrupt_vector = RomVectors); + + *(.romvectors) + + /* Make sure we pulled in an interrupt vector. */ + ASSERT (. != __cy_interrupt_vector, "No interrupt vector"); + + ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location"); + + PROVIDE(__cy_reset = Reset); + *(.text.Reset) + /* Make sure we pulled in some reset code. */ + ASSERT (. != __cy_reset, "No reset code"); + + /* Place DMA initialization before text to ensure it gets placed in first 64K of flash */ + *(.dma_init) + ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash"); + + *(.text .text.* .gnu.linkonce.t.*) + *(.plt) + *(.gnu.warning) + *(.glue_7t) *(.glue_7) *(.vfp11_veneer) + + KEEP(*(.bootloader)) /* necessary for bootloader's, but doesn't impact non-bootloaders */ + + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.gcc_except_table) + } >rom + .eh_frame_hdr : ALIGN (4) + { + KEEP (*(.eh_frame_hdr)) + } >rom + .eh_frame : ALIGN (4) + { + KEEP (*(.eh_frame)) + } >rom + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >rom + __exidx_end = .; + .rodata : ALIGN (4) + { + *(.rodata .rodata.* .gnu.linkonce.r.*) + + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(0x4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + __cy_regions = .; + LONG (__cy_region_init_ram) + LONG (__cy_region_start_data) + LONG (__cy_region_init_size_ram) + LONG (__cy_region_zero_size_ram) + __cy_regions_end = .; + + . = ALIGN (8); + _etext = .; + } >rom + + .ramvectors (NOLOAD) : ALIGN(8) + { + __cy_region_start_ram = .; + KEEP(*(.ramvectors)) + } + + .noinit (NOLOAD) : ALIGN(8) + { + KEEP(*(.noinit)) + } + + .data : ALIGN(8) + { + __cy_region_start_data = .; + + KEEP(*(.jcr)) + *(.got.plt) *(.got) + *(.shdata) + *(.data .data.* .gnu.linkonce.d.*) + . = ALIGN (8); + *(.ram) + _edata = .; + } >ram AT>rom + .bss : ALIGN(8) + { + PROVIDE(__bss_start__ = .); + *(.shbss) + *(.bss .bss.* .gnu.linkonce.b.*) + *(COMMON) + . = ALIGN (8); + *(.ram.b) + _end = .; + __end = .; + } >ram AT>rom + PROVIDE(end = .); + PROVIDE(__bss_end__ = .); + + __cy_region_init_ram = LOADADDR (.data); + __cy_region_init_size_ram = _edata - ADDR (.data); + __cy_region_zero_size_ram = _end - _edata; + + /* The .stack and .heap sections don't contain any symbols. + * They are only used for linker to calculate RAM utilization. + */ + .heap (NOLOAD) : + { + . = _end; + . += 0x0800; + __cy_heap_limit = .; + } >ram + + .stack (__cy_stack - 0x2000) (NOLOAD) : + { + __cy_stack_limit = .; + . += 0x2000; + } >ram + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack") + + .cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) : + { + KEEP(*(.cyloadermeta)) + } :NONE + + .cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) : + { + KEEP(*(.cyloadablemeta)) + } >rom + + .cyconfigecc (0x80000000 + ecc_offset) : + { + KEEP(*(.cyconfigecc)) + } :NONE + + .cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE + .cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE + + .cyeeprom (0x90200000 + ee_offset) : + { + KEEP(*(.cyeeprom)) + ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM"); + } :NONE + + .cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE + .cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE + + .stab 0 (NOLOAD) : { *(.stab) } + .stabstr 0 (NOLOAD) : { *(.stabstr) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. + */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* DWARF 2.1 */ + .debug_ranges 0 : { *(.debug_ranges) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) } + .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) } +} + diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h new file mode 100644 index 0000000..122c9aa --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3.h @@ -0,0 +1,1627 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + #define __STATIC_INLINE static __inline + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + #define __STATIC_INLINE static inline + +#elif defined ( __TMS470__ ) + #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + #define __STATIC_INLINE static inline + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + #define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TMS470__ ) + #if defined __TI__VFP_SUPPORT____ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200 + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0 + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 4 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __O union + { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ +} + + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ +} + + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ +} + + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ +} + + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ +} + + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ +} + + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ + else { + return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return ( + ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits )) - 1))) + ); +} + + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; + SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); +} + + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0); + ITM->PORT[0].u8 = (uint8_t) ch; + } + return (ch); +} + + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) { + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) { + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h new file mode 100644 index 0000000..011f057 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: core_cm3_psoc5.h +* Version 4.20 +* +* Description: +* Provides important type information for the PSoC5. This includes types +* necessary for core_cm3.h. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#if !defined(__CORE_CM3_PSOC5_H__) +#define __CORE_CM3_PSOC5_H__ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ +/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ + BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ + SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ + SysTick_IRQn = -1 /*!< 15 Cortex-M3 System Tick Interrupt */ +/****** PSoC5 Peripheral Interrupt Numbers *******************************************************/ + /* Not relevant. All peripheral interrupts are defined by the user */ +} IRQn_Type; + +#include + +#define __CHECK_DEVICE_DEFINES + +#define __CM3_REV 0x0201 + +#define __MPU_PRESENT 0 +#define __NVIC_PRIO_BITS 3 +#define __Vendor_SysTickConfig 0 + +#include + + +#endif /* __CORE_CM3_PSOC5_H__ */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h new file mode 100644 index 0000000..0a18faf --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmFunc.h @@ -0,0 +1,636 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +/** \brief Get IPSR Register + + This function returns the content of the IPSR Register. + + \return IPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp"); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp"); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory"); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + __ASM volatile (""); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile (""); + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc"); + __ASM volatile (""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h new file mode 100644 index 0000000..ab3a010 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/core_cmInstr.h @@ -0,0 +1,688 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +#endif +} + + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c new file mode 100644 index 0000000..4780df0 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.c @@ -0,0 +1,1873 @@ +/******************************************************************************* +* File Name: cyPm.c +* Version 4.20 +* +* Description: +* Provides an API for the power management. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cyPm.h" + + +/******************************************************************* +* Place your includes, defines, and code here. Do not use the merge +* region below unless any component datasheet suggests doing so. +*******************************************************************/ +/* `#START CY_PM_HEADER_INCLUDE` */ + +/* `#END` */ + + +static CY_PM_BACKUP_STRUCT cyPmBackup; +static CY_PM_CLOCK_BACKUP_STRUCT cyPmClockBackup; + +/* Convertion table between register's values and frequency in MHz */ +static const uint8 CYCODE cyPmImoFreqReg2Mhz[7u] = {12u, 6u, 24u, 3u, 48u, 62u, 74u}; + +/* Function Prototypes */ +static void CyPmHibSaveSet(void); +static void CyPmHibRestore(void) ; + +static void CyPmHibSlpSaveSet(void) ; +static void CyPmHibSlpRestore(void) ; + +static void CyPmHviLviSaveDisable(void) ; +static void CyPmHviLviRestore(void) ; + + +/******************************************************************************* +* Function Name: CyPmSaveClocks +******************************************************************************** +* +* Summary: +* This function is called in preparation for entering sleep or hibernate low +* power modes. Saves all the states of the clocking system that do not persist +* during sleep/hibernate or that need to be altered in preparation for +* sleep/hibernate. Shutdowns all the digital and analog clock dividers for the +* active power mode configuration. +* +* Switches the master clock over to the IMO and shuts down the PLL and MHz +* Crystal. The IMO frequency is set to either 12 MHz or 48 MHz to match the +* Design-Wide Resources System Editor "Enable Fast IMO During Startup" setting. +* The ILO and 32 KHz oscillators are not impacted. The current Flash wait state +* setting is saved and the Flash wait state setting is set for the current IMO +* speed. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* Parameters: +* None +* +* Return: +* None +* +* Side Effects: +* All peripheral clocks are going to be off after this API method call. +* +*******************************************************************************/ +void CyPmSaveClocks(void) +{ + /* Digital and analog clocks - save enable state and disable them all */ + cyPmClockBackup.enClkA = CY_PM_ACT_CFG1_REG & CY_PM_ACT_EN_CLK_A_MASK; + cyPmClockBackup.enClkD = CY_PM_ACT_CFG2_REG; + CY_PM_ACT_CFG1_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_A_MASK)); + CY_PM_ACT_CFG2_REG &= ((uint8)(~CY_PM_ACT_EN_CLK_D_MASK)); + + /* Save current flash wait cycles and set the maximum value */ + cyPmClockBackup.flashWaitCycles = CY_PM_CACHE_CR_CYCLES_MASK & CY_PM_CACHE_CR_REG; + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* IMO - save current IMO MHz OSC frequency and USB mode is on bit */ + cyPmClockBackup.imoFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + cyPmClockBackup.imoUsbClk = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_USB; + + /* IMO doubler - save enable state */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + /* IMO doubler enabled - save and disable */ + cyPmClockBackup.imo2x = CY_PM_ENABLED; + } + else + { + /* IMO doubler disabled */ + cyPmClockBackup.imo2x = CY_PM_DISABLED; + } + + /* Master clock - save source */ + cyPmClockBackup.masterClkSrc = CY_PM_CLKDIST_MSTR1_REG & CY_PM_MASTER_CLK_SRC_MASK; + + /* Switch Master clock's source from PLL's output to PLL's source */ + if(CY_MASTER_SOURCE_PLL == cyPmClockBackup.masterClkSrc) + { + switch (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_PLL_SRC_MASK) + { + case CY_PM_CLKDIST_PLL_SRC_IMO: + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + break; + + case CY_PM_CLKDIST_PLL_SRC_XTAL: + CyMasterClk_SetSource(CY_MASTER_SOURCE_XTAL); + break; + + case CY_PM_CLKDIST_PLL_SRC_DSI: + CyMasterClk_SetSource(CY_MASTER_SOURCE_DSI); + break; + + default: + CYASSERT(0u != 0u); + break; + } + } + + /* PLL - check enable state, disable if needed */ + if(0u != (CY_PM_FASTCLK_PLL_CFG0_REG & CY_PM_PLL_CFG0_ENABLE)) + { + /* PLL is enabled - save state and disable */ + cyPmClockBackup.pllEnableState = CY_PM_ENABLED; + CyPLL_OUT_Stop(); + } + else + { + /* PLL is disabled - save state */ + cyPmClockBackup.pllEnableState = CY_PM_DISABLED; + } + + /* IMO - set appropriate frequency for LPM */ + CyIMO_SetFreq(CY_PM_IMO_FREQ_LPM); + + /* IMO - save enable state and enable without wait to settle */ + if(0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG)) + { + /* IMO - save enabled state */ + cyPmClockBackup.imoEnable = CY_PM_ENABLED; + } + else + { + /* IMO - save disabled state */ + cyPmClockBackup.imoEnable = CY_PM_DISABLED; + + /* Enable the IMO. Use software delay instead of the FTW-based inside */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + + /* Settling time of the IMO is of the order of less than 6us */ + CyDelayUs(6u); + } + + /* IMO - save the current IMOCLK source and set to IMO if not yet */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_XCLKEN)) + { + /* DSI or XTAL CLK */ + cyPmClockBackup.imoClkSrc = + (0u == (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO2X_SRC)) ? CY_IMO_SOURCE_DSI : CY_IMO_SOURCE_XTAL; + + /* IMO - set IMOCLK source to IMO */ + CyIMO_SetSource(CY_IMO_SOURCE_IMO); + } + else + { + /* IMO */ + cyPmClockBackup.imoClkSrc = CY_IMO_SOURCE_IMO; + } + + /* Save clk_imo source */ + cyPmClockBackup.clkImoSrc = CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK; + + /* If IMOCLK2X or SPC OSC is source for clk_imo, set it to IMOCLK */ + if(CY_PM_CLKDIST_IMO_OUT_IMO != cyPmClockBackup.clkImoSrc) + { + /* Set IMOCLK to source for clk_imo */ + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + CY_PM_CLKDIST_IMO_OUT_IMO; + } /* Need to change nothing if IMOCLK is source clk_imo */ + + /* IMO doubler - disable it (saved above) */ + if(0u != (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_F2XON)) + { + CyIMO_DisableDoubler(); + } + + /* Master clock - save divider and set it to divide-by-one (if no yet) */ + cyPmClockBackup.clkSyncDiv = CY_PM_CLKDIST_MSTR0_REG; + if(CY_PM_DIV_BY_ONE != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(CY_PM_DIV_BY_ONE); + } /* No change if master clock divider is 1 */ + + /* Master clock source - set it to IMO if not yet. */ + if(CY_MASTER_SOURCE_IMO != cyPmClockBackup.masterClkSrc) + { + CyMasterClk_SetSource(CY_MASTER_SOURCE_IMO); + } /* No change if master clock source is IMO */ + + /* Bus clock - save divider and set it, if needed, to divide-by-one */ + cyPmClockBackup.clkBusDiv = (uint16) ((uint16) CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + cyPmClockBackup.clkBusDiv |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(CY_PM_BUS_CLK_DIV_BY_ONE != cyPmClockBackup.clkBusDiv) + { + CyBusClk_SetDivider(CY_PM_BUS_CLK_DIV_BY_ONE); + } /* Do nothing if saved and actual values are equal */ + + /* Set number of wait cycles for flash according to CPU frequency in MHz */ + CyFlash_SetWaitCycles((uint8)CY_PM_GET_CPU_FREQ_MHZ); + + /* MHz ECO - check enable state and disable if needed */ + if(0u != (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_ENABLE)) + { + /* MHz ECO is enabled - save state and disable */ + cyPmClockBackup.xmhzEnableState = CY_PM_ENABLED; + CyXTAL_Stop(); + } + else + { + /* MHz ECO is disabled - save state */ + cyPmClockBackup.xmhzEnableState = CY_PM_DISABLED; + } + + + /*************************************************************************** + * Save the enable state of delay between the system bus clock and each of the + * 4 individual analog clocks. This bit non-retention and its value should + * be restored on wakeup. + ***************************************************************************/ + if(0u != (CY_PM_CLKDIST_DELAY_REG & CY_PM_CLKDIST_DELAY_EN)) + { + cyPmClockBackup.clkDistDelay = CY_PM_ENABLED; + } + else + { + cyPmClockBackup.clkDistDelay = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmRestoreClocks +******************************************************************************** +* +* Summary: +* Restores any state that was preserved by the last call to CyPmSaveClocks(). +* The Flash wait state setting is also restored. +* +* Note If the Master Clock source is routed through the DSI inputs, then it +* must be set manually to another source before using the +* CyPmSaveClocks()/CyPmRestoreClocks() functions. +* +* PSoC 3 and PSoC 5LP: +* The merge region could be used to process state when the megahertz crystal is +* not ready after a hold-off timeout. +* +* PSoC 5: +* The 130 ms is given for the megahertz crystal to stabilize. Its readiness is +* not verified after a hold-off timeout. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmRestoreClocks(void) +{ + cystatus status = CYRET_TIMEOUT; + uint16 i; + uint16 clkBusDivTmp; + + + /* Convertion table between CyIMO_SetFreq() parameters and register's value */ + const uint8 CYCODE cyPmImoFreqMhz2Reg[7u] = { + CY_IMO_FREQ_12MHZ, CY_IMO_FREQ_6MHZ, CY_IMO_FREQ_24MHZ, CY_IMO_FREQ_3MHZ, + CY_IMO_FREQ_48MHZ, 5u, 6u}; + + /* Restore enable state of delay between system bus clock and ACLKs. */ + if(CY_PM_ENABLED == cyPmClockBackup.clkDistDelay) + { + /* Delay for both bandgap and delay line to settle out */ + CyDelayCycles((uint32)(CY_PM_CLK_DELAY_BANDGAP_SETTLE_US + CY_PM_CLK_DELAY_BIAS_SETTLE_US) * + CY_PM_GET_CPU_FREQ_MHZ); + + CY_PM_CLKDIST_DELAY_REG |= CY_PM_CLKDIST_DELAY_EN; + } + + /* MHz ECO restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) + { + /*********************************************************************** + * Enabling XMHZ XTAL. The actual CyXTAL_Start() with a non zero wait + * period uses FTW for period measurement. This could cause a problem + * if CTW/FTW is used as a wake up time in the low power modes APIs. + * So, the XTAL wait procedure is implemented with a software delay. + ***********************************************************************/ + + /* Enable XMHZ XTAL with no wait */ + (void) CyXTAL_Start(CY_PM_XTAL_MHZ_NO_WAIT); + + /* Read XERR bit to clear it */ + (void) CY_PM_FASTCLK_XMHZ_CSR_REG; + + /* Wait */ + for(i = CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US; i > 0u; i--) + { + /* Make a 200 microseconds delay */ + CyDelayCycles((uint32)CY_PM_WAIT_200_US * CY_PM_GET_CPU_FREQ_MHZ); + + /* High output indicates oscillator failure */ + if(0u == (CY_PM_FASTCLK_XMHZ_CSR_REG & CY_PM_XMHZ_CSR_XERR)) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when megahertz crystal is not ready. + * Time to stabilize the value is crystal specific. + *******************************************************************/ + /* `#START_MHZ_ECO_TIMEOUT` */ + + /* `#END` */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.xmhzEnableState) */ + + + /* Temprorary set maximum flash wait cycles */ + CyFlash_SetWaitCycles(CY_PM_MAX_FLASH_WAIT_CYCLES); + + /* XTAL and DSI clocks are ready to be source for Master clock. */ + if((CY_PM_MASTER_CLK_SRC_XTAL == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_DSI == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock's divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + /* Restore Master clock divider */ + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - restore IMO frequency */ + if((0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) && + (CY_IMO_FREQ_24MHZ == cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq])) + { + /* Restore IMO frequency (24 MHz) and trim it for USB */ + CyIMO_SetFreq(CY_IMO_FREQ_USB); + } + else + { + /* Restore IMO frequency */ + CyIMO_SetFreq(cyPmImoFreqMhz2Reg[cyPmClockBackup.imoFreq]); + + if(0u != (cyPmClockBackup.imoUsbClk & CY_PM_FASTCLK_IMO_CR_USB)) + { + CY_PM_FASTCLK_IMO_CR_REG |= CY_PM_FASTCLK_IMO_CR_USB; + } + else + { + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8)(~CY_PM_FASTCLK_IMO_CR_USB)); + } + } + + /* IMO - restore enable state if needed */ + if((CY_PM_ENABLED == cyPmClockBackup.imoEnable) && + (0u == (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + /* IMO - restore enabled state */ + CyIMO_Start(CY_PM_IMO_NO_WAIT_TO_SETTLE); + } + + /* IMO - restore IMOCLK source */ + CyIMO_SetSource(cyPmClockBackup.imoClkSrc); + + /* Restore IMO doubler enable state (turned off by CyPmSaveClocks()) */ + if(CY_PM_ENABLED == cyPmClockBackup.imo2x) + { + CyIMO_EnableDoubler(); + } + + /* IMO - restore clk_imo source, if needed */ + if(cyPmClockBackup.clkImoSrc != (CY_PM_CLKDIST_CR_REG & CY_PM_CLKDIST_IMO_OUT_MASK)) + { + CY_PM_CLKDIST_CR_REG = (CY_PM_CLKDIST_CR_REG & ((uint8)(~CY_PM_CLKDIST_IMO_OUT_MASK))) | + cyPmClockBackup.clkImoSrc; + } + + + /* PLL restore state */ + if(CY_PM_ENABLED == cyPmClockBackup.pllEnableState) + { + /*********************************************************************** + * Enable PLL. The actual CyPLL_OUT_Start() without wait period uses FTW + * for period measurement. This could cause a problem if CTW/FTW is used + * as a wakeup time in the low power modes APIs. To omit this issue PLL + * wait procedure is implemented with a software delay. + ***********************************************************************/ + status = CYRET_TIMEOUT; + + /* Enable PLL */ + (void) CyPLL_OUT_Start(CY_PM_PLL_OUT_NO_WAIT); + + /* Read to clear lock status after delay */ + CyDelayUs((uint32)80u); + (void) CY_PM_FASTCLK_PLL_SR_REG; + + /* It should take 250 us lock: 251-80 = 171 */ + for(i = 171u; i > 0u; i--) + { + CyDelayUs((uint32)1u); + + /* Accept PLL is OK after two consecutive polls indicate PLL lock */ + if((0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED)) && + (0u != (CY_PM_FASTCLK_PLL_SR_REG & CY_PM_FASTCLK_PLL_LOCKED))) + { + status = CYRET_SUCCESS; + break; + } + } + + if(CYRET_TIMEOUT == status) + { + /******************************************************************* + * Process the situation when PLL is not ready. + *******************************************************************/ + /* `#START_PLL_TIMEOUT` */ + + /* `#END` */ + } + } /* (CY_PM_ENABLED == cyPmClockBackup.pllEnableState) */ + + + /* PLL and IMO is ready to be source for Master clock */ + if((CY_PM_MASTER_CLK_SRC_IMO == cyPmClockBackup.masterClkSrc) || + (CY_PM_MASTER_CLK_SRC_PLL == cyPmClockBackup.masterClkSrc)) + { + /* Restore Master clock divider */ + if(CY_PM_CLKDIST_MSTR0_REG != cyPmClockBackup.clkSyncDiv) + { + CyMasterClk_SetDivider(cyPmClockBackup.clkSyncDiv); + } + + /* Restore Master clock source */ + CyMasterClk_SetSource(cyPmClockBackup.masterClkSrc); + } + + /* IMO - disable if it was originally disabled */ + if((CY_PM_DISABLED == cyPmClockBackup.imoEnable) && + (0u != (CY_PM_ACT_CFG0_IMO & CY_PM_ACT_CFG0_REG))) + { + CyIMO_Stop(); + } + + /* Bus clock - restore divider, if needed */ + clkBusDivTmp = (uint16) ((uint16)CY_PM_CLK_BUS_MSB_DIV_REG << 8u); + clkBusDivTmp |= CY_PM_CLK_BUS_LSB_DIV_REG; + if(cyPmClockBackup.clkBusDiv != clkBusDivTmp) + { + CyBusClk_SetDivider(cyPmClockBackup.clkBusDiv); + } + + /* Restore flash wait cycles */ + CY_PM_CACHE_CR_REG = ((CY_PM_CACHE_CR_REG & ((uint8)(~CY_PM_CACHE_CR_CYCLES_MASK))) | + cyPmClockBackup.flashWaitCycles); + + /* Digital and analog clocks - restore state */ + CY_PM_ACT_CFG1_REG = cyPmClockBackup.enClkA; + CY_PM_ACT_CFG2_REG = cyPmClockBackup.enClkD; +} + + +/******************************************************************************* +* Function Name: CyPmAltAct +******************************************************************************** +* +* Summary: +* Puts the part into the Alternate Active (Standby) state. The Alternate Active +* state can allow for any of the capabilities of the device to be active, but +* the operation of this function is dependent on the CPU being disabled during +* the Alternate Active state. The configuration code and the component APIs +* will configure the template for the Alternate Active state to be the same as +* the Active state with the exception that the CPU will be disabled during +* Alternate Active. +* +* Note Before calling this function, you must manually configure the power mode +* of the source clocks for the timer that is used as the wakeup timer. +* +* PSoC 3: +* Before switching to Alternate Active, if a wakeupTime other than NONE is +* specified, then the appropriate timer state is configured as specified with +* the interrupt for that timer disabled. The wakeup source will be the +* combination of the values specified in the wakeupSource and any timer +* specified in the wakeupTime argument. Once the wakeup condition is +* satisfied, then all saved state is restored and the function returns in the +* Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW, FTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* This function is used to both enter the Alternate Active mode and halt the +* processor. For PSoC 3 these two actions must be paired together. With PSoC +* 5LP the processor can be halted independently with the __WFI() function from +* the CMSIS library that is included in Creator. This function should be used +* instead when the action required is just to halt the processor until an +* enabled interrupt occurs. +* +* The wakeupTime parameter is not used for this device. It must be set to zero +* (PM_ALT_ACT_TIME_NONE). The wake up time configuration can be done by a +* separate component: the CTW wakeup interval should be configured with the +* Sleep Timer component and one second interval should be configured with the +* RTC component. +* +* The wakeup behavior depends on the wakeupSource parameter in the following +* manner: upon function execution the device will be switched from Active to +* Alternate Active mode and then the CPU will be halted. When an enabled wakeup +* event occurs the device will return to Active mode. Similarly when an +* enabled interrupt occurs the CPU will be started. These two actions will +* occur together provided that the event that occurs is an enabled wakeup +* source and also generates an interrupt. If just the wakeup event occurs then +* the device will be in Active mode, but the CPU will remain halted waiting for +* an interrupt. If an interrupt occurs from something other than a wakeup +* source, then the CPU will restart with the device in Alternate Active mode +* until a wakeup event occurs. +* +* For example, if CyPmAltAct(PM_ALT_ACT_TIME_NONE, PM_ALT_ACT_SRC_PICU) is +* called and PICU interrupt occurs, the CPU will be started and device will be +* switched into Active mode. And if CyPmAltAct(PM_ALT_ACT_TIME_NONE, +* PM_ALT_ACT_SRC_NONE) is called and PICU interrupt occurs, the CPU will be +* started while device remains in Alternate Active mode. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP this parameter is ignored. +* +* Define Time +* PM_ALT_ACT_TIME_NONE None +* PM_ALT_ACT_TIME_ONE_PPS One PPS: 1 second +* PM_ALT_ACT_TIME_CTW_2MS CTW: 2 ms +* PM_ALT_ACT_TIME_CTW_4MS CTW: 4 ms +* PM_ALT_ACT_TIME_CTW_8MS CTW: 8 ms +* PM_ALT_ACT_TIME_CTW_16MS CTW: 16 ms +* PM_ALT_ACT_TIME_CTW_32MS CTW: 32 ms +* PM_ALT_ACT_TIME_CTW_64MS CTW: 64 ms +* PM_ALT_ACT_TIME_CTW_128MS CTW: 128 ms +* PM_ALT_ACT_TIME_CTW_256MS CTW: 256 ms +* PM_ALT_ACT_TIME_CTW_512MS CTW: 512 ms +* PM_ALT_ACT_TIME_CTW_1024MS CTW: 1024 ms +* PM_ALT_ACT_TIME_CTW_2048MS CTW: 2048 ms +* PM_ALT_ACT_TIME_CTW_4096MS CTW: 4096 ms +* PM_ALT_ACT_TIME_FTW(1-256)* FTW: 10us to 2.56 ms +* +* *Note: PM_ALT_ACT_TIME_FTW() is a macro that takes an argument that +* specifies how many increments of 10 us to delay. + For PSoC 3 silicon the valid range of values is 1 to 256. +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified, the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_ALT_ACT_SRC_NONE None +* PM_ALT_ACT_SRC_COMPARATOR0 Comparator 0 +* PM_ALT_ACT_SRC_COMPARATOR1 Comparator 1 +* PM_ALT_ACT_SRC_COMPARATOR2 Comparator 2 +* PM_ALT_ACT_SRC_COMPARATOR3 Comparator 3 +* PM_ALT_ACT_SRC_INTERRUPT Interrupt +* PM_ALT_ACT_SRC_PICU PICU +* PM_ALT_ACT_SRC_I2C I2C +* PM_ALT_ACT_SRC_BOOSTCONVERTER Boost Converter +* PM_ALT_ACT_SRC_FTW Fast Timewheel* +* PM_ALT_ACT_SRC_VD High and Low Voltage Detection (HVI, LVI)* +* PM_ALT_ACT_SRC_CTW Central Timewheel** +* PM_ALT_ACT_SRC_ONE_PPS One PPS** +* PM_ALT_ACT_SRC_LCD LCD +* +* *Note : FTW and HVI/LVI wakeup signals are in the same mask bit. +* **Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource, an instance specific define +* that will track with the specific comparator that the instance +* is placed into should be used. As an example, for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW, FTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with a corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wakeup time) or ILO 100 KHz (if the FTW timer is used as wakeup time) +* will be left started. +* +*******************************************************************************/ +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) +{ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_ALT_ACT_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + #if(CY_PSOC3) + + /* FTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_FTW(1u)) && (wakeupTime <= PM_ALT_ACT_TIME_FTW(256u))) + { + CyPmFtwSetInterval(PM_ALT_ACT_FTW_INTERVAL(wakeupTime)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_FTW; + } + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_ALT_ACT_TIME_CTW_2MS) && (wakeupTime <= PM_ALT_ACT_TIME_CTW_4096MS)) + { + /* Save current CTW configuration and set new one */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_ALT_ACT_TIME_ONE_PPS == wakeupTime) + { + /* Save current 1PPS configuration and set new one */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_ALT_ACT_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /* Switch to the Alternate Active mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_ALT_ACT); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into the mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Alternate Active Mode */ + + /* Restore wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; +} + + +/******************************************************************************* +* Function Name: CyPmSleep +******************************************************************************** +* +* Summary: +* Puts the part into the Sleep state. +* +* Note Before calling this function, you must manually configure the power +* mode of the source clocks for the timer that is used as the wakeup timer. +* +* Note Before calling this function, you must prepare clock tree configuration +* for the low power mode by calling CyPmSaveClocks(). And restore clock +* configuration after CyPmSleep() execution by calling CyPmRestoreClocks(). See +* Power Management section, Clock Configuration subsection of the System +* Reference Guide for more information. +* +* PSoC 3: +* Before switching to Sleep, if a wakeupTime other than NONE is specified, +* then the appropriate timer state is configured as specified with the +* interrupt for that timer disabled. The wakeup source will be a combination +* of the values specified in the wakeupSource and any timer specified in the +* wakeupTime argument. Once the wakeup condition is satisfied, then all saved +* state is restored and the function returns in the Active state. +* +* Note that if the wakeupTime is made with a different value, the period before +* the wakeup occurs can be significantly shorter than the specified time. If +* the next call is made with the same wakeupTime value, then the wakeup will +* occur the specified period after the previous wakeup occurred. +* +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. If the CTW or One PPS is already +* configured for wakeup, for example with the SleepTimer or RTC components, +* then specify NONE for the wakeupTime and include the appropriate source for +* wakeupSource. +* +* PSoC 5LP: +* The wakeupTime parameter is not used and the only NONE can be specified. +* The wakeup time must be configured with the component, SleepTimer for CTW +* intervals and RTC for 1PPS interval. The component must be configured to +* generate interrupt. +* +* Parameters: +* wakeupTime: Specifies a timer wakeup source and the frequency of that +* source. For PSoC 5LP, this parameter is ignored. +* +* Define Time +* PM_SLEEP_TIME_NONE None +* PM_SLEEP_TIME_ONE_PPS One PPS: 1 second +* PM_SLEEP_TIME_CTW_2MS CTW: 2 ms +* PM_SLEEP_TIME_CTW_4MS CTW: 4 ms +* PM_SLEEP_TIME_CTW_8MS CTW: 8 ms +* PM_SLEEP_TIME_CTW_16MS CTW: 16 ms +* PM_SLEEP_TIME_CTW_32MS CTW: 32 ms +* PM_SLEEP_TIME_CTW_64MS CTW: 64 ms +* PM_SLEEP_TIME_CTW_128MS CTW: 128 ms +* PM_SLEEP_TIME_CTW_256MS CTW: 256 ms +* PM_SLEEP_TIME_CTW_512MS CTW: 512 ms +* PM_SLEEP_TIME_CTW_1024MS CTW: 1024 ms +* PM_SLEEP_TIME_CTW_2048MS CTW: 2048 ms +* PM_SLEEP_TIME_CTW_4096MS CTW: 4096 ms +* +* wakeUpSource: Specifies a bitwise mask of wakeup sources. In addition, if +* a wakeupTime has been specified the associated timer will be +* included as a wakeup source. +* +* Define Source +* PM_SLEEP_SRC_NONE None +* PM_SLEEP_SRC_COMPARATOR0 Comparator 0 +* PM_SLEEP_SRC_COMPARATOR1 Comparator 1 +* PM_SLEEP_SRC_COMPARATOR2 Comparator 2 +* PM_SLEEP_SRC_COMPARATOR3 Comparator 3 +* PM_SLEEP_SRC_PICU PICU +* PM_SLEEP_SRC_I2C I2C +* PM_SLEEP_SRC_BOOSTCONVERTER Boost Converter +* PM_SLEEP_SRC_VD High and Low Voltage Detection (HVI, LVI) +* PM_SLEEP_SRC_CTW Central Timewheel* +* PM_SLEEP_SRC_ONE_PPS One PPS* +* PM_SLEEP_SRC_LCD LCD +* +* *Note: CTW and One PPS wakeup signals are in the same mask bit. +* +* When specifying a Comparator as the wakeupSource an instance specific define +* should be used that will track with the specific comparator that the instance +* is placed into. As an example for a Comparator instance named MyComp the +* value to OR into the mask is: MyComp_ctComp__CMP_MASK. +* +* When CTW or One PPS is used as a wakeup source, the CyPmReadStatus() +* function must be called upon wakeup with corresponding parameter. Please +* refer to the CyPmReadStatus() API in the System Reference Guide for more +* information. +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects and Restrictions: +* If a wakeupTime other than NONE is specified, then upon exit the state of the +* specified timer will be left as specified by wakeupTime with the timer +* enabled and the interrupt disabled. Also, the ILO 1 KHz (if CTW timer is +* used as wake up time) will be left started. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using rising edges of the 1 kHz ILO. +* +* For PSoC 3 silicon hardware buzz should be disabled before entering a sleep +* power mode. It is disabled by PSoC Creator during startup. +* If a Low Voltage Interrupt (LVI), High Voltage Interrupt (HVI) or Brown Out +* detect (power supply supervising capabilities) are required in a design +* during sleep, use the Central Time Wheel (CTW) to periodically wake the +* device, perform software buzz, and refresh the supervisory services. If LVI, +* HVI, or Brown Out is not required, then CTW is not required. +* Refer to the device errata for more information. +* +*******************************************************************************/ +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter Sleep and + * Hibernate modes. The holdoff delay is measured using rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + + /*********************************************************************** + * PSoC3 < TO6: + * - Hardware buzz must be disabled before the sleep mode entry. + * - Voltage supervision (HVI/LVI) requires hardware buzz, so they must + * be also disabled. + * + * PSoC3 >= TO6: + * - Voltage supervision (HVI/LVI) requires hardware buzz, so hardware + * buzz must be enabled before the sleep mode entry and restored on + * the wakeup. + ***********************************************************************/ + #if(CY_PSOC3) + + /* Silicon Revision ID is below TO6 */ + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* Hardware buzz expected to be disabled in Sleep mode */ + CYASSERT(0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)); + } + + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL < 5u) + { + /* LVI/HVI requires hardware buzz to be enabled */ + CYASSERT(0u != 0u); + } + else + { + if (0u == (CY_PM_PWRSYS_WAKE_TR2_REG & CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ)) + { + cyPmBackup.hardwareBuzz = CY_PM_DISABLED; + CY_PM_PWRSYS_WAKE_TR2_REG |= CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ; + } + else + { + cyPmBackup.hardwareBuzz = CY_PM_ENABLED; + } + } + } + + #endif /* (CY_PSOC3) */ + + + /******************************************************************************* + * For ARM-based devices,interrupt is required for the CPU to wake up. The + * Power Management implementation assumes that wakeup time is configured with a + * separate component (component-based wakeup time configuration) for + * interrupt to be issued on terminal count. For more information, refer to the + * Wakeup Time Configuration section of System Reference Guide. + *******************************************************************************/ + #if(CY_PSOC5) + + /* Arguments expected to be 0 */ + CYASSERT(PM_SLEEP_TIME_NONE == wakeupTime); + + if(0u != wakeupTime) + { + /* To remove unreferenced local variable warning */ + } + + #endif /* (CY_PSOC5) */ + + + CyPmHibSlpSaveSet(); + + + #if(CY_PSOC3) + + /* CTW - save current and set new configuration */ + if((wakeupTime >= PM_SLEEP_TIME_CTW_2MS) && (wakeupTime <= PM_SLEEP_TIME_CTW_4096MS)) + { + /* Save current and set new configuration of CTW */ + CyPmCtwSetInterval((uint8)(wakeupTime - 1u)); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_CTW; + } + + /* 1PPS - save current and set new configuration */ + if(PM_SLEEP_TIME_ONE_PPS == wakeupTime) + { + /* Save current and set new configuration of the 1PPS */ + CyPmOppsSet(); + + /* Include associated timer to wakeupSource */ + wakeupSource |= PM_SLEEP_SRC_ONE_PPS; + } + + #endif /* (CY_PSOC3) */ + + + /* Save and set new wake up configuration */ + + /* Interrupt, PICU, I2C, Boost converter, CTW/1PPS */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = (uint8) (wakeupSource >> 4u); + + /* Comparators */ + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = (((uint8) wakeupSource) & CY_PM_WAKEUP_SRC_CMPS_MASK); + + /* LCD */ + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = ((uint8) ((wakeupSource >> 12u) & 0x01u)); + + + /******************************************************************* + * Do not use the merge region below unless any component datasheet + * suggests doing so. + *******************************************************************/ + /* `#START CY_PM_JUST_BEFORE_SLEEP` */ + + /* `#END` */ + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + /* Switch to Sleep mode */ + CY_PM_MODE_CSR_REG = ((CY_PM_MODE_CSR_REG & ((uint8)(~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_SLEEP); + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + /* Point of return from Sleep Mode */ + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /******************************************************************* + * Do not use merge region below unless any component datasheet + * suggest to do so. + *******************************************************************/ + /* `#START CY_PM_JUST_AFTER_WAKEUP_FROM_SLEEP` */ + + /* `#END` */ + + + /* Restore hardware configuration */ + CyPmHibSlpRestore(); + + + /* Disable hardware buzz, if it was previously enabled */ + #if(CY_PSOC3) + + if(0u != (CY_PM_RESET_CR1_REG & (CY_PM_RESET_CR1_HVIA_EN | + CY_PM_RESET_CR1_LVIA_EN | CY_PM_RESET_CR1_LVID_EN))) + { + if(CYDEV_CHIP_REV_ACTUAL >= 5u) + { + if (CY_PM_DISABLED == cyPmBackup.hardwareBuzz) + { + CY_PM_PWRSYS_WAKE_TR2_REG &= (uint8)(~CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ); + } + } + } + + #endif /* (CY_PSOC3) */ + + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmHibernate +******************************************************************************** +* +* Summary: +* Puts the part into the Hibernate state. +* +* PSoC 3 and PSoC 5LP: +* Before switching to Hibernate, the current status of the PICU wakeup source +* bit is saved and then set. This configures the device to wake up from the +* PICU. Make sure you have at least one pin configured to generate PICU +* interrupt. For pin Px.y, the register "PICU_INTTYPE_PICUx_INTTYPEy" controls +* the PICU behavior. In the TRM, this register is "PICU[0..15]_INTTYPE[0..7]." +* In the Pins component datasheet, this register is referred to as the IRQ +* option. Once the wakeup occurs, the PICU wakeup source bit is restored and +* the PSoC returns to the Active state. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +* Side Effects: +* Applications must wait 20 us before re-entering hibernate or sleep after +* waking up from hibernate. The 20 us allows the sleep regulator time to +* stabilize before the next hibernate / sleep event occurs. The 20 us +* requirement begins when the device wakes up. There is no hardware check that +* this requirement is met. The specified delay should be done on ISR entry. +* +* After the wakeup PICU interrupt occurs, the Pin_ClearInterrupt() (where Pin is +* instance name of the Pins component) function must be called to clear the +* latched pin events to allow the proper Hibernate mode entry and to enable +* detection of future events. +* +* The 1 kHz ILO clock is expected to be enabled for PSoC 3 and PSoC 5LP to +* measure Hibernate/Sleep regulator settling time after a reset. The holdoff +* delay is measured using the rising edges of the 1 kHz ILO. +* +*******************************************************************************/ +void CyPmHibernate(void) +{ + uint8 interruptState; + + /* Save current global interrupt enable and disable it */ + interruptState = CyEnterCriticalSection(); + + /*********************************************************************** + * The Hibernate/Sleep regulator has a settling time after a reset. + * During this time, the system ignores requests to enter the Sleep and + * Hibernate modes. The holdoff delay is measured using the rising edges of + * the 1 kHz ILO. + ***********************************************************************/ + if(0u == (CY_PM_MODE_CSR_REG & CY_PM_MODE_CSR_PWRUP_PULSE_Q)) + { + /* Disable hold off - no action on restore */ + CY_PM_PWRSYS_SLP_TR_REG &= CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK; + } + else + { + /* Abort, device is not ready for low power mode entry */ + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); + + return; + } + + CyPmHibSaveSet(); + + + /* Save and enable only wakeup on PICU */ + cyPmBackup.wakeupCfg0 = CY_PM_WAKEUP_CFG0_REG; + CY_PM_WAKEUP_CFG0_REG = CY_PM_WAKEUP_PICU; + + cyPmBackup.wakeupCfg1 = CY_PM_WAKEUP_CFG1_REG; + CY_PM_WAKEUP_CFG1_REG = 0x00u; + + cyPmBackup.wakeupCfg2 = CY_PM_WAKEUP_CFG2_REG; + CY_PM_WAKEUP_CFG2_REG = 0x00u; + + + /* Last moment IMO frequency change */ + if(0u == (CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK)) + { + /* IMO frequency is 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_ENABLED; + } + else + { + /* IMO frequency is not 12 MHz */ + cyPmBackup.imoActFreq12Mhz = CY_PM_DISABLED; + + /* Save IMO frequency */ + cyPmBackup.imoActFreq = CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK; + + /* Set IMO frequency to 12 MHz */ + CY_PM_FASTCLK_IMO_CR_REG &= ((uint8) (~CY_PM_FASTCLK_IMO_CR_FREQ_MASK)); + } + + + /* Switch to Hibernate Mode */ + CY_PM_MODE_CSR_REG = (CY_PM_MODE_CSR_REG & ((uint8) (~CY_PM_MODE_CSR_MASK))) | CY_PM_MODE_CSR_HIBERNATE; + + /* Recommended readback. */ + (void) CY_PM_MODE_CSR_REG; + + /* Two recommended NOPs to get into mode. */ + CY_NOP; + CY_NOP; + + /* Execute WFI instruction (for ARM-based devices only) */ + CY_PM_WFI; + + + /* Point of return from Hibernate mode */ + + + /* Restore last moment IMO frequency change */ + if(CY_PM_ENABLED != cyPmBackup.imoActFreq12Mhz) + { + CY_PM_FASTCLK_IMO_CR_REG = (CY_PM_FASTCLK_IMO_CR_REG & ((uint8)(~CY_PM_FASTCLK_IMO_CR_FREQ_MASK))) | + cyPmBackup.imoActFreq; + } + + + /* Restore device for proper Hibernate mode exit*/ + CyPmHibRestore(); + + /* Restore current wake up configuration */ + CY_PM_WAKEUP_CFG0_REG = cyPmBackup.wakeupCfg0; + CY_PM_WAKEUP_CFG1_REG = cyPmBackup.wakeupCfg1; + CY_PM_WAKEUP_CFG2_REG = cyPmBackup.wakeupCfg2; + + /* Restore global interrupt enable state */ + CyExitCriticalSection(interruptState); +} + + +/******************************************************************************* +* Function Name: CyPmReadStatus +******************************************************************************** +* +* Summary: +* Manages the Power Manager Interrupt Status Register. This register has the +* interrupt status for the one pulse per second, central timewheel and fast +* timewheel timers. This hardware register clears on read. To allow for only +* clearing the bits of interest and preserving the other bits, this function +* uses a shadow register that retains the state. This function reads the +* status register and ORs that value with the shadow register. That is the +* value that is returned. Then the bits in the mask that are set are cleared +* from this value and written back to the shadow register. +* +* Note You must call this function within 1 ms (1 clock cycle of the ILO) +* after a CTW event has occurred. +* +* Parameters: +* mask: Bits in the shadow register to clear. +* +* Define Source +* CY_PM_FTW_INT Fast Timewheel +* CY_PM_CTW_INT Central Timewheel +* CY_PM_ONEPPS_INT One Pulse Per Second +* +* Return: +* Status. Same bits values as the mask parameter. +* +*******************************************************************************/ +uint8 CyPmReadStatus(uint8 mask) +{ + static uint8 interruptStatus; + uint8 interruptState; + uint8 tmpStatus; + + /* Enter critical section */ + interruptState = CyEnterCriticalSection(); + + /* Save value of register, copy it and clear desired bit */ + interruptStatus |= CY_PM_INT_SR_REG; + tmpStatus = interruptStatus; + interruptStatus &= ((uint8)(~mask)); + + /* Exit critical section */ + CyExitCriticalSection(interruptState); + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: CyPmHibSaveSet +******************************************************************************** +* +* Summary: +* Prepare device for proper Hibernate low power mode entry: +* - Disables I2C backup regulator +* - Saves ILO power down mode state and enable it +* - Saves state of 1 kHz and 100 kHz ILO and disable them +* - Disables sleep regulator and shorts vccd to vpwrsleep +* - Save LVI/HVI configuration and disable them - CyPmHviLviSaveDisable() +* - CyPmHibSlpSaveSet() function is called +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSaveSet(void) +{ + /* I2C backup reg must be off when the sleep regulator is unavailable */ + if(0u != (CY_PM_PWRSYS_CR1_REG & CY_PM_PWRSYS_CR1_I2CREG_BACKUP)) + { + /*********************************************************************** + * If the I2C backup regulator is enabled, all the fixed-function registers + * store their values while the device is in the low power mode, otherwise their + * configuration is lost. The I2C API makes a decision to restore or not + * to restore I2C registers based on this. If this regulator will be + * disabled and then enabled, I2C API will suppose that the I2C block + * registers preserved their values, while this is not true. So, the + * backup regulator is disabled. The I2C sleep APIs is responsible for + * restoration. + ***********************************************************************/ + + /* Disable I2C backup register */ + CY_PM_PWRSYS_CR1_REG &= ((uint8)(~CY_PM_PWRSYS_CR1_I2CREG_BACKUP)); + } + + + /* Save current ILO power mode and ensure low power mode */ + cyPmBackup.iloPowerMode = CyILO_SetPowerMode(CY_PM_POWERDOWN_MODE); + + /* Save current 1kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo1kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_1K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + /* Save current 100kHz ILO enable state. Disabled automatically. */ + cyPmBackup.ilo100kEnable = (0u == (CY_PM_SLOWCLK_ILO_CR0_REG & CY_PM_ILO_CR0_EN_100K)) ? + CY_PM_DISABLED : CY_PM_ENABLED; + + + /* Disable the sleep regulator and shorts vccd to vpwrsleep */ + if(0u == (CY_PM_PWRSYS_SLP_TR_REG & CY_PM_PWRSYS_SLP_TR_BYPASS)) + { + /* Save current bypass state */ + cyPmBackup.slpTrBypass = CY_PM_DISABLED; + CY_PM_PWRSYS_SLP_TR_REG |= CY_PM_PWRSYS_SLP_TR_BYPASS; + } + else + { + cyPmBackup.slpTrBypass = CY_PM_ENABLED; + } + + /* LPCOMPs are always enabled (even when BOTH ext_vccd=1 and ext_vcca=1)*/ + + + /*************************************************************************** + * LVI/HVI must be disabled in Hibernate + ***************************************************************************/ + + /* Save LVI/HVI configuration and disable them */ + CyPmHviLviSaveDisable(); + + + /* Make the same preparations for Hibernate and Sleep modes */ + CyPmHibSlpSaveSet(); + + + /*************************************************************************** + * Save and set the power mode wakeup trim registers + ***************************************************************************/ + cyPmBackup.wakeupTrim0 = CY_PM_PWRSYS_WAKE_TR0_REG; + cyPmBackup.wakeupTrim1 = CY_PM_PWRSYS_WAKE_TR1_REG; + + CY_PM_PWRSYS_WAKE_TR0_REG = CY_PM_PWRSYS_WAKE_TR0; + CY_PM_PWRSYS_WAKE_TR1_REG = CY_PM_PWRSYS_WAKE_TR1; +} + + +/******************************************************************************* +* Function Name: CyPmHibRestore +******************************************************************************** +* +* Summary: +* Restores the device for the proper Hibernate mode exit: +* - Restores LVI/HVI configuration - calsl CyPmHviLviRestore() +* - CyPmHibSlpSaveRestore() function is called +* - Restores ILO power down mode state and enables it +* - Restores the state of 1 kHz and 100 kHz ILO and disables them +* - Restores the sleep regulator settings +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibRestore(void) +{ + /* Restore LVI/HVI configuration */ + CyPmHviLviRestore(); + + /* Restore the same configuration for Hibernate and Sleep modes */ + CyPmHibSlpRestore(); + + /* Restore 1kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo1kEnable) + { + /* Enable 1kHz ILO */ + CyILO_Start1K(); + } + + /* Restore 100kHz ILO enable state */ + if(CY_PM_ENABLED == cyPmBackup.ilo100kEnable) + { + /* Enable 100kHz ILO */ + CyILO_Start100K(); + } + + /* Restore ILO power mode */ + (void) CyILO_SetPowerMode(cyPmBackup.iloPowerMode); + + + if(CY_PM_DISABLED == cyPmBackup.slpTrBypass) + { + /* Enable the sleep regulator */ + CY_PM_PWRSYS_SLP_TR_REG &= ((uint8)(~CY_PM_PWRSYS_SLP_TR_BYPASS)); + } + + + /*************************************************************************** + * Restore the power mode wakeup trim registers + ***************************************************************************/ + CY_PM_PWRSYS_WAKE_TR0_REG = cyPmBackup.wakeupTrim0; + CY_PM_PWRSYS_WAKE_TR1_REG = cyPmBackup.wakeupTrim1; +} + + +/******************************************************************************* +* Function Name: CyPmCtwSetInterval +******************************************************************************** +* +* Summary: +* Performs the CTW configuration: +* - Disables the CTW interrupt +* - Enables 1 kHz ILO +* - Sets a new CTW interval +* +* Parameters: +* ctwInterval: the CTW interval to be set. +* +* Return: +* None +* +* Side Effects: +* Enables ILO 1 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmCtwSetInterval(uint8 ctwInterval) +{ + /* Disable CTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_IE)); + + /* Enable 1kHz ILO (required for CTW operation) */ + CyILO_Start1K(); + + /* Interval could be set only while CTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_CTW_EN)) + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Disable the CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_CTW_EN)); + CY_PM_TW_CFG1_REG = ctwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set CTW interval if needed */ + if(CY_PM_TW_CFG1_REG != ctwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG1_REG = ctwInterval; + } /* Required interval is already set */ + + /* Enable CTW */ + CY_PM_TW_CFG2_REG |= CY_PM_CTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmOppsSet +******************************************************************************** +* +* Summary: +* Performs 1PPS configuration: +* - Starts 32 KHz XTAL +* - Disables 1PPS interrupts +* - Enables 1PPS +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void CyPmOppsSet(void) +{ + /* Enable 32kHz XTAL if needed */ + if(0u == (CY_PM_SLOWCLK_X32_CR_REG & CY_PM_X32_CR_X32EN)) + { + /* Enable 32kHz XTAL */ + CyXTAL_32KHZ_Start(); + } + + /* Disable 1PPS interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_1PPS_IE)); + + /* Enable 1PPS operation */ + CY_PM_TW_CFG2_REG |= CY_PM_1PPS_EN; +} + + +/******************************************************************************* +* Function Name: CyPmFtwSetInterval +******************************************************************************** +* +* Summary: +* Performs the FTW configuration: +* - Disables the FTW interrupt +* - Enables 100 kHz ILO +* - Sets a new FTW interval. +* +* Parameters: +* ftwInterval - FTW counter interval. +* +* Return: +* None +* +* Side Effects: +* Enables the ILO 100 KHz clock and leaves it enabled. +* +*******************************************************************************/ +void CyPmFtwSetInterval(uint8 ftwInterval) +{ + /* Disable FTW interrupt enable */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_IE)); + + /* Enable 100kHz ILO */ + CyILO_Start100K(); + + /* Interval could be set only while FTW is disabled */ + if(0u != (CY_PM_TW_CFG2_REG & CY_PM_FTW_EN)) + { + /* Disable FTW, set new FTW interval if needed and enable it again */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Disable CTW, set new CTW interval and enable it again */ + CY_PM_TW_CFG2_REG &= ((uint8)(~CY_PM_FTW_EN)); + CY_PM_TW_CFG0_REG = ftwInterval; + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } /* Required interval is already set */ + } + else + { + /* Set new FTW counter interval if needed. FTW is disabled. */ + if(CY_PM_TW_CFG0_REG != ftwInterval) + { + /* Set new CTW interval. Could be changed if CTW is disabled */ + CY_PM_TW_CFG0_REG = ftwInterval; + } /* Required interval is already set */ + + /* Enable FTW */ + CY_PM_TW_CFG2_REG |= CY_PM_FTW_EN; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpSaveSet +******************************************************************************** +* +* Summary: +* This API is used for preparing the device for the Sleep and Hibernate low power +* modes entry: +* - Saves the COMP, VIDAC, DSM, and SAR routing connections (PSoC 5) +* - Saves the SC/CT routing connections (PSoC 3/5/5LP) +* - Disables the Serial Wire Viewer (SWV) (PSoC 3) +* - Saves the boost reference selection and sets it to internal +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHibSlpSaveSet(void) +{ + /* Save SC/CT routing registers */ + cyPmBackup.scctData[0u] = CY_GET_REG8(CYREG_SC0_SW0 ); + cyPmBackup.scctData[1u] = CY_GET_REG8(CYREG_SC0_SW2 ); + cyPmBackup.scctData[2u] = CY_GET_REG8(CYREG_SC0_SW3 ); + cyPmBackup.scctData[3u] = CY_GET_REG8(CYREG_SC0_SW4 ); + cyPmBackup.scctData[4u] = CY_GET_REG8(CYREG_SC0_SW6 ); + cyPmBackup.scctData[5u] = CY_GET_REG8(CYREG_SC0_SW8 ); + cyPmBackup.scctData[6u] = CY_GET_REG8(CYREG_SC0_SW10); + + cyPmBackup.scctData[7u] = CY_GET_REG8(CYREG_SC1_SW0 ); + cyPmBackup.scctData[8u] = CY_GET_REG8(CYREG_SC1_SW2 ); + cyPmBackup.scctData[9u] = CY_GET_REG8(CYREG_SC1_SW3 ); + cyPmBackup.scctData[10u] = CY_GET_REG8(CYREG_SC1_SW4 ); + cyPmBackup.scctData[11u] = CY_GET_REG8(CYREG_SC1_SW6 ); + cyPmBackup.scctData[12u] = CY_GET_REG8(CYREG_SC1_SW8 ); + cyPmBackup.scctData[13u] = CY_GET_REG8(CYREG_SC1_SW10); + + cyPmBackup.scctData[14u] = CY_GET_REG8(CYREG_SC2_SW0 ); + cyPmBackup.scctData[15u] = CY_GET_REG8(CYREG_SC2_SW2 ); + cyPmBackup.scctData[16u] = CY_GET_REG8(CYREG_SC2_SW3 ); + cyPmBackup.scctData[17u] = CY_GET_REG8(CYREG_SC2_SW4 ); + cyPmBackup.scctData[18u] = CY_GET_REG8(CYREG_SC2_SW6 ); + cyPmBackup.scctData[19u] = CY_GET_REG8(CYREG_SC2_SW8 ); + cyPmBackup.scctData[20u] = CY_GET_REG8(CYREG_SC2_SW10); + + cyPmBackup.scctData[21u] = CY_GET_REG8(CYREG_SC3_SW0 ); + cyPmBackup.scctData[22u] = CY_GET_REG8(CYREG_SC3_SW2 ); + cyPmBackup.scctData[23u] = CY_GET_REG8(CYREG_SC3_SW3 ); + cyPmBackup.scctData[24u] = CY_GET_REG8(CYREG_SC3_SW4 ); + cyPmBackup.scctData[25u] = CY_GET_REG8(CYREG_SC3_SW6 ); + cyPmBackup.scctData[26u] = CY_GET_REG8(CYREG_SC3_SW8 ); + cyPmBackup.scctData[27u] = CY_GET_REG8(CYREG_SC3_SW10); + + CY_SET_REG8(CYREG_SC0_SW0 , 0u); + CY_SET_REG8(CYREG_SC0_SW2 , 0u); + CY_SET_REG8(CYREG_SC0_SW3 , 0u); + CY_SET_REG8(CYREG_SC0_SW4 , 0u); + CY_SET_REG8(CYREG_SC0_SW6 , 0u); + CY_SET_REG8(CYREG_SC0_SW8 , 0u); + CY_SET_REG8(CYREG_SC0_SW10, 0u); + + CY_SET_REG8(CYREG_SC1_SW0 , 0u); + CY_SET_REG8(CYREG_SC1_SW2 , 0u); + CY_SET_REG8(CYREG_SC1_SW3 , 0u); + CY_SET_REG8(CYREG_SC1_SW4 , 0u); + CY_SET_REG8(CYREG_SC1_SW6 , 0u); + CY_SET_REG8(CYREG_SC1_SW8 , 0u); + CY_SET_REG8(CYREG_SC1_SW10, 0u); + + CY_SET_REG8(CYREG_SC2_SW0 , 0u); + CY_SET_REG8(CYREG_SC2_SW2 , 0u); + CY_SET_REG8(CYREG_SC2_SW3 , 0u); + CY_SET_REG8(CYREG_SC2_SW4 , 0u); + CY_SET_REG8(CYREG_SC2_SW6 , 0u); + CY_SET_REG8(CYREG_SC2_SW8 , 0u); + CY_SET_REG8(CYREG_SC2_SW10, 0u); + + CY_SET_REG8(CYREG_SC3_SW0 , 0u); + CY_SET_REG8(CYREG_SC3_SW2 , 0u); + CY_SET_REG8(CYREG_SC3_SW3 , 0u); + CY_SET_REG8(CYREG_SC3_SW4 , 0u); + CY_SET_REG8(CYREG_SC3_SW6 , 0u); + CY_SET_REG8(CYREG_SC3_SW8 , 0u); + CY_SET_REG8(CYREG_SC3_SW10, 0u); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + + /* Disable SWV before entering low power mode */ + if(0u != (CY_PM_MLOGIC_DBG_REG & CY_PM_MLOGIC_DBG_SWV_CLK_EN)) + { + /* Save SWV clock enabled state */ + cyPmBackup.swvClkEnabled = CY_PM_ENABLED; + + /* Save current ports drive mode settings */ + cyPmBackup.prt1Dm = CY_PM_PRT1_PC3_REG & ((uint8)(~CY_PM_PRT1_PC3_DM_MASK)); + + /* Set drive mode to strong output */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + CY_PM_PRT1_PC3_DM_STRONG; + + /* Disable SWV clocks */ + CY_PM_MLOGIC_DBG_REG &= ((uint8)(~CY_PM_MLOGIC_DBG_SWV_CLK_EN)); + } + else + { + /* Save SWV clock disabled state */ + cyPmBackup.swvClkEnabled = CY_PM_DISABLED; + } + + #endif /* (CY_PSOC3) */ + + + /*************************************************************************** + * Save boost reference and set it to boost's internal by clearing the bit. + * External (chip bandgap) reference is not available in Sleep and Hibernate. + ***************************************************************************/ + if(0u != (CY_PM_BOOST_CR2_REG & CY_PM_BOOST_CR2_EREFSEL_EXT)) + { + cyPmBackup.boostRefExt = CY_PM_ENABLED; + CY_PM_BOOST_CR2_REG &= ((uint8)(~CY_PM_BOOST_CR2_EREFSEL_EXT)); + } + else + { + cyPmBackup.boostRefExt = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHibSlpRestore +******************************************************************************** +* +* Summary: +* This API is used for restoring the device configurations after wakeup from the Sleep +* and Hibernate low power modes: +* - Restores the SC/CT routing connections +* - Restores the enable state of the Serial Wire Viewer (SWV) (PSoC 3) +* - Restores the boost reference selection +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +static void CyPmHibSlpRestore(void) +{ + /* Restore SC/CT routing registers */ + CY_SET_REG8(CYREG_SC0_SW0 , cyPmBackup.scctData[0u] ); + CY_SET_REG8(CYREG_SC0_SW2 , cyPmBackup.scctData[1u] ); + CY_SET_REG8(CYREG_SC0_SW3 , cyPmBackup.scctData[2u] ); + CY_SET_REG8(CYREG_SC0_SW4 , cyPmBackup.scctData[3u] ); + CY_SET_REG8(CYREG_SC0_SW6 , cyPmBackup.scctData[4u] ); + CY_SET_REG8(CYREG_SC0_SW8 , cyPmBackup.scctData[5u] ); + CY_SET_REG8(CYREG_SC0_SW10, cyPmBackup.scctData[6u] ); + + CY_SET_REG8(CYREG_SC1_SW0 , cyPmBackup.scctData[7u] ); + CY_SET_REG8(CYREG_SC1_SW2 , cyPmBackup.scctData[8u] ); + CY_SET_REG8(CYREG_SC1_SW3 , cyPmBackup.scctData[9u] ); + CY_SET_REG8(CYREG_SC1_SW4 , cyPmBackup.scctData[10u]); + CY_SET_REG8(CYREG_SC1_SW6 , cyPmBackup.scctData[11u]); + CY_SET_REG8(CYREG_SC1_SW8 , cyPmBackup.scctData[12u]); + CY_SET_REG8(CYREG_SC1_SW10, cyPmBackup.scctData[13u]); + + CY_SET_REG8(CYREG_SC2_SW0 , cyPmBackup.scctData[14u]); + CY_SET_REG8(CYREG_SC2_SW2 , cyPmBackup.scctData[15u]); + CY_SET_REG8(CYREG_SC2_SW3 , cyPmBackup.scctData[16u]); + CY_SET_REG8(CYREG_SC2_SW4 , cyPmBackup.scctData[17u]); + CY_SET_REG8(CYREG_SC2_SW6 , cyPmBackup.scctData[18u]); + CY_SET_REG8(CYREG_SC2_SW8 , cyPmBackup.scctData[19u]); + CY_SET_REG8(CYREG_SC2_SW10, cyPmBackup.scctData[20u]); + + CY_SET_REG8(CYREG_SC3_SW0 , cyPmBackup.scctData[21u]); + CY_SET_REG8(CYREG_SC3_SW2 , cyPmBackup.scctData[22u]); + CY_SET_REG8(CYREG_SC3_SW3 , cyPmBackup.scctData[23u]); + CY_SET_REG8(CYREG_SC3_SW4 , cyPmBackup.scctData[24u]); + CY_SET_REG8(CYREG_SC3_SW6 , cyPmBackup.scctData[25u]); + CY_SET_REG8(CYREG_SC3_SW8 , cyPmBackup.scctData[26u]); + CY_SET_REG8(CYREG_SC3_SW10, cyPmBackup.scctData[27u]); + + + #if(CY_PSOC3) + + /* Serial Wire Viewer (SWV) workaround */ + if(CY_PM_ENABLED == cyPmBackup.swvClkEnabled) + { + /* Restore ports drive mode */ + CY_PM_PRT1_PC3_REG = (CY_PM_PRT1_PC3_REG & CY_PM_PRT1_PC3_DM_MASK) | + cyPmBackup.prt1Dm; + + /* Enable SWV clocks */ + CY_PM_MLOGIC_DBG_REG |= CY_PM_MLOGIC_DBG_SWV_CLK_EN; + } + + #endif /* (CY_PSOC3) */ + + + /* Restore boost reference */ + if(CY_PM_ENABLED == cyPmBackup.boostRefExt) + { + CY_PM_BOOST_CR2_REG |= CY_PM_BOOST_CR2_EREFSEL_EXT; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviSaveDisable +******************************************************************************** +* +* Summary: +* Saves analog and digital LVI and HVI configuration and disables them. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviSaveDisable(void) +{ + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVID_EN)) + { + cyPmBackup.lvidEn = CY_PM_ENABLED; + cyPmBackup.lvidTrip = CY_VD_LVI_TRIP_REG & CY_VD_LVI_TRIP_LVID_MASK; + + /* Save state of reset device at specified Vddd threshold */ + cyPmBackup.lvidRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESD_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvDigitDisable(); + } + else + { + cyPmBackup.lvidEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_LVIA_EN)) + { + cyPmBackup.lviaEn = CY_PM_ENABLED; + cyPmBackup.lviaTrip = CY_VD_LVI_TRIP_REG >> 4u; + + /* Save state of reset device at specified Vdda threshold */ + cyPmBackup.lviaRst = (0u == (CY_VD_PRES_CONTROL_REG & CY_VD_PRESA_EN)) ? \ + CY_PM_DISABLED : CY_PM_ENABLED; + + CyVdLvAnalogDisable(); + } + else + { + cyPmBackup.lviaEn = CY_PM_DISABLED; + } + + if(0u != (CY_VD_LVI_HVI_CONTROL_REG & CY_VD_HVIA_EN)) + { + cyPmBackup.hviaEn = CY_PM_ENABLED; + CyVdHvAnalogDisable(); + } + else + { + cyPmBackup.hviaEn = CY_PM_DISABLED; + } +} + + +/******************************************************************************* +* Function Name: CyPmHviLviRestore +******************************************************************************** +* +* Summary: +* Restores the analog and digital LVI and HVI configuration. +* +* Parameters: +* None +* +* Return: +* None +* +* Reentrant: +* No +* +*******************************************************************************/ +static void CyPmHviLviRestore(void) +{ + /* Restore LVI/HVI configuration */ + if(CY_PM_ENABLED == cyPmBackup.lvidEn) + { + CyVdLvDigitEnable(cyPmBackup.lvidRst, cyPmBackup.lvidTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.lviaEn) + { + CyVdLvAnalogEnable(cyPmBackup.lviaRst, cyPmBackup.lviaTrip); + } + + if(CY_PM_ENABLED == cyPmBackup.hviaEn) + { + CyVdHvAnalogEnable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h new file mode 100644 index 0000000..6ea9bd6 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyPm.h @@ -0,0 +1,676 @@ +/******************************************************************************* +* File Name: cyPm.h +* Version 4.20 +* +* Description: +* Provides the function definitions for the power management API. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPM_H) +#define CY_BOOT_CYPM_H + +#include "cytypes.h" /* Register access API */ +#include "cydevice_trm.h" /* Registers addresses */ +#include "cyfitter.h" /* Comparators placement */ +#include "CyLib.h" /* Clock API */ +#include "CyFlash.h" /* Flash API - CyFlash_SetWaitCycles() */ + + +/*************************************** +* Function Prototypes +***************************************/ +void CyPmSaveClocks(void) ; +void CyPmRestoreClocks(void) ; +void CyPmAltAct(uint16 wakeupTime, uint16 wakeupSource) ; +void CyPmSleep(uint8 wakeupTime, uint16 wakeupSource) ; +void CyPmHibernate(void) ; + +uint8 CyPmReadStatus(uint8 mask) ; + +/* Internal APIs and are not meant to be called directly by the user */ +void CyPmCtwSetInterval(uint8 ctwInterval) ; +void CyPmFtwSetInterval(uint8 ftwInterval) ; +void CyPmOppsSet(void) ; + + +/*************************************** +* API Constants +***************************************/ + +#define PM_SLEEP_SRC_NONE (0x0000u) +#define PM_SLEEP_TIME_NONE (0x00u) +#define PM_ALT_ACT_SRC_NONE (0x0000u) +#define PM_ALT_ACT_TIME_NONE (0x0000u) + +#if(CY_PSOC3) + + /* Wake up time for Sleep mode */ + #define PM_SLEEP_TIME_ONE_PPS (0x01u) + #define PM_SLEEP_TIME_CTW_2MS (0x02u) + #define PM_SLEEP_TIME_CTW_4MS (0x03u) + #define PM_SLEEP_TIME_CTW_8MS (0x04u) + #define PM_SLEEP_TIME_CTW_16MS (0x05u) + #define PM_SLEEP_TIME_CTW_32MS (0x06u) + #define PM_SLEEP_TIME_CTW_64MS (0x07u) + #define PM_SLEEP_TIME_CTW_128MS (0x08u) + #define PM_SLEEP_TIME_CTW_256MS (0x09u) + #define PM_SLEEP_TIME_CTW_512MS (0x0Au) + #define PM_SLEEP_TIME_CTW_1024MS (0x0Bu) + #define PM_SLEEP_TIME_CTW_2048MS (0x0Cu) + #define PM_SLEEP_TIME_CTW_4096MS (0x0Du) + + /* Difference between parameter's value and register's one */ + #define CY_PM_FTW_INTERVAL_SHIFT (0x000Eu) + + /* Wake up time for Alternate Active mode */ + #define PM_ALT_ACT_TIME_ONE_PPS (0x0001u) + #define PM_ALT_ACT_TIME_CTW_2MS (0x0002u) + #define PM_ALT_ACT_TIME_CTW_4MS (0x0003u) + #define PM_ALT_ACT_TIME_CTW_8MS (0x0004u) + #define PM_ALT_ACT_TIME_CTW_16MS (0x0005u) + #define PM_ALT_ACT_TIME_CTW_32MS (0x0006u) + #define PM_ALT_ACT_TIME_CTW_64MS (0x0007u) + #define PM_ALT_ACT_TIME_CTW_128MS (0x0008u) + #define PM_ALT_ACT_TIME_CTW_256MS (0x0009u) + #define PM_ALT_ACT_TIME_CTW_512MS (0x000Au) + #define PM_ALT_ACT_TIME_CTW_1024MS (0x000Bu) + #define PM_ALT_ACT_TIME_CTW_2048MS (0x000Cu) + #define PM_ALT_ACT_TIME_CTW_4096MS (0x000Du) + #define PM_ALT_ACT_TIME_FTW(x) ((x) + CY_PM_FTW_INTERVAL_SHIFT) + +#endif /* (CY_PSOC3) */ + + +/* Wake up sources for Sleep mode */ +#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u) +#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u) +#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u) +#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u) +#define PM_SLEEP_SRC_PICU (0x0040u) +#define PM_SLEEP_SRC_I2C (0x0080u) +#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u) +#define PM_SLEEP_SRC_VD (0x0400u) +#define PM_SLEEP_SRC_CTW (0x0800u) +#define PM_SLEEP_SRC_ONE_PPS (0x0800u) +#define PM_SLEEP_SRC_LCD (0x1000u) + +/* Wake up sources for Alternate Active mode */ +#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u) +#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u) +#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u) +#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u) +#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u) +#define PM_ALT_ACT_SRC_PICU (0x0040u) +#define PM_ALT_ACT_SRC_I2C (0x0080u) +#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u) +#define PM_ALT_ACT_SRC_FTW (0x0400u) +#define PM_ALT_ACT_SRC_VD (0x0400u) +#define PM_ALT_ACT_SRC_CTW (0x0800u) +#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u) +#define PM_ALT_ACT_SRC_LCD (0x1000u) + + +#define CY_PM_WAKEUP_PICU (0x04u) +#define CY_PM_IMO_NO_WAIT_TO_SETTLE (0x00u) +#define CY_PM_POWERDOWN_MODE (0x01u) +#define CY_PM_HIGHPOWER_MODE (0x00u) /* Deprecated */ +#define CY_PM_ENABLED (0x01u) +#define CY_PM_DISABLED (0x00u) + +/* No wait for PLL to stabilize, used in CyPLL_OUT_Start() */ +#define CY_PM_PLL_OUT_NO_WAIT (0u) + +/* No wait for MHZ XTAL to stabilize, used in CyXTAL_Start() */ +#define CY_PM_XTAL_MHZ_NO_WAIT (0u) + +#define CY_PM_WAIT_200_US (200u) +#define CY_PM_WAIT_250_US (250u) +#define CY_PM_WAIT_20_US (20u) + +#define CY_PM_FREQ_3MHZ (3u) +#define CY_PM_FREQ_12MHZ (12u) +#define CY_PM_FREQ_48MHZ (48u) + + +#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u) + + +/* Delay line bandgap current settling time starting from wakeup event */ +#define CY_PM_CLK_DELAY_BANDGAP_SETTLE_US (50u) + +/* Delay line internal bias settling */ +#define CY_PM_CLK_DELAY_BIAS_SETTLE_US (25u) + + +/* Max flash wait cycles for each device */ +#if(CY_PSOC3) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (45u) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + #define CY_PM_MAX_FLASH_WAIT_CYCLES (55u) +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* This marco is used to obtain the CPU frequency in MHz. It should be only used +* when the clock distribution system is prepared for the low power mode entry. +* This macro is silicon dependent as PSoC 5 devices have no CPU clock divider +* and PSoC 3 devices have different placement of the CPU clock divider register +* bitfield. +*******************************************************************************/ +#if(CY_PSOC3) + #define CY_PM_GET_CPU_FREQ_MHZ \ + ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \ + ((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u))) +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + /* CPU clock is directly derived from bus clock */ + #define CY_PM_GET_CPU_FREQ_MHZ (cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* The low power mode entry is different for PSoC 3 and PSoC 5 devices. The low +* power modes in PSoC 5 devices are invoked by Wait-For-Interrupt (WFI) +* instruction. The ARM compilers has __wfi() intrinsic that inserts a WFI +* instruction into the instruction stream generated by the compiler. The GCC +* compiler has to execute assembly language instruction. +*******************************************************************************/ +#if(CY_PSOC5) + + #if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */ + #define CY_PM_WFI __wfi() + #else /* ASM for GCC & IAR */ + #define CY_PM_WFI asm volatile ("WFI \n") + #endif /* (__ARMCC_VERSION) */ + +#else + + #define CY_PM_WFI CY_NOP + +#endif /* (CY_PSOC5) */ + + +/******************************************************************************* +* Macro for the wakeupTime argument of the CyPmAltAct() function. The FTW should +* be programmed manually for non PSoC 3 devices. +*******************************************************************************/ +#if(CY_PSOC3) + + #define PM_ALT_ACT_FTW_INTERVAL(x) ((uint8)((x) - CY_PM_FTW_INTERVAL_SHIFT)) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* This macro defines the IMO frequency that will be set by CyPmSaveClocks() +* function based on Enable Fast IMO during Startup option from the DWR file. +* The CyPmSleep()/CyPmHibernate() will set IMO 12 MHz just before entering the +* low power mode and restore IMO back to the value set by CyPmSaveClocks() +* immediately on wakeup. +*******************************************************************************/ + +/* Enable Fast IMO during Startup - enabled */ +#if(1u == CYDEV_CONFIGURATION_IMOENABLED) + + /* IMO will be configured to 48 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_48MHZ) + +#else + + /* IMO will be configured to 12 MHz */ + #define CY_PM_IMO_FREQ_LPM (CY_IMO_FREQ_12MHZ) + +#endif /* (1u == CYDEV_CONFIGURATION_IMOENABLED) */ + + +typedef struct cyPmClockBackupStruct +{ + /* CyPmSaveClocks()/CyPmRestoreClocks() */ + uint8 enClkA; /* Analog clocks enable */ + uint8 enClkD; /* Digital clocks enable */ + uint8 masterClkSrc; /* Master clock source */ + uint8 imoFreq; /* IMO frequency (reg's value) */ + uint8 imoUsbClk; /* IMO USB CLK (reg's value) */ + uint8 flashWaitCycles; /* Flash wait cycles */ + uint8 imoEnable; /* IMO enable in Active mode */ + uint8 imoClkSrc; /* The IMO output */ + uint8 clkImoSrc; + uint8 imo2x; /* IMO doubler enable state */ + uint8 clkSyncDiv; /* Master clk divider */ + uint16 clkBusDiv; /* clk_bus divider */ + uint8 pllEnableState; /* PLL enable state */ + uint8 xmhzEnableState; /* XM HZ enable state */ + uint8 clkDistDelay; /* Delay for clk_bus and ACLKs */ + +} CY_PM_CLOCK_BACKUP_STRUCT; + + +typedef struct cyPmBackupStruct +{ + uint8 iloPowerMode; /* ILO power mode */ + uint8 ilo1kEnable; /* ILO 1K enable state */ + uint8 ilo100kEnable; /* ILO 100K enable state */ + + uint8 slpTrBypass; /* Sleep Trim Bypass */ + + #if(CY_PSOC3) + + uint8 swvClkEnabled; /* SWV clock enable state */ + uint8 prt1Dm; /* Ports drive mode configuration */ + uint8 hardwareBuzz; + + #endif /* (CY_PSOC3) */ + + uint8 wakeupCfg0; /* Wake up configuration 0 */ + uint8 wakeupCfg1; /* Wake up configuration 1 */ + uint8 wakeupCfg2; /* Wake up configuration 2 */ + + uint8 wakeupTrim0; + uint8 wakeupTrim1; + + uint8 scctData[28u]; /* SC/CT routing registers */ + + /* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */ + uint8 lvidEn; + uint8 lvidTrip; + uint8 lviaEn; + uint8 lviaTrip; + uint8 hviaEn; + uint8 lvidRst; + uint8 lviaRst; + + uint8 imoActFreq; /* Last moment IMO change */ + uint8 imoActFreq12Mhz; /* 12 MHz or not */ + + uint8 boostRefExt; /* Boost reference selection */ + +} CY_PM_BACKUP_STRUCT; + + +/*************************************** +* Registers +***************************************/ + +/* Power Mode Wakeup Trim Register 1 */ +#define CY_PM_PWRSYS_WAKE_TR1_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) +#define CY_PM_PWRSYS_WAKE_TR1_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR1 ) + +/* Master clock Divider Value Register */ +#define CY_PM_CLKDIST_MSTR0_REG (* (reg8 *) CYREG_CLKDIST_MSTR0 ) +#define CY_PM_CLKDIST_MSTR0_PTR ( (reg8 *) CYREG_CLKDIST_MSTR0 ) + +/* Master Clock Configuration Register/CPU Divider Value */ +#define CY_PM_CLKDIST_MSTR1_REG (* (reg8 *) CYREG_CLKDIST_MSTR1 ) +#define CY_PM_CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1 ) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_CR_REG (* (reg8 *) CYREG_CLKDIST_CR ) +#define CY_PM_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR ) + +/* CLK_BUS LSB Divider Value Register */ +#define CY_PM_CLK_BUS_LSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG0 ) +#define CY_PM_CLK_BUS_LSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG0 ) + +/* CLK_BUS MSB Divider Value Register */ +#define CY_PM_CLK_BUS_MSB_DIV_REG (* (reg8 *) CYREG_CLKDIST_BCFG1 ) +#define CY_PM_CLK_BUS_MSB_DIV_PTR ( (reg8 *) CYREG_CLKDIST_BCFG1 ) + +/* CLK_BUS Configuration Register */ +#define CLK_BUS_CFG_REG (* (reg8 *) CYREG_CLKDIST_BCFG2 ) +#define CLK_BUS_CFG_PTR ( (reg8 *) CYREG_CLKDIST_BCFG2 ) + +/* Power Mode Control/Status Register */ +#define CY_PM_MODE_CSR_REG (* (reg8 *) CYREG_PM_MODE_CSR ) +#define CY_PM_MODE_CSR_PTR ( (reg8 *) CYREG_PM_MODE_CSR ) + +/* Power System Control Register 1 */ +#define CY_PM_PWRSYS_CR1_REG (* (reg8 *) CYREG_PWRSYS_CR1 ) +#define CY_PM_PWRSYS_CR1_PTR ( (reg8 *) CYREG_PWRSYS_CR1 ) + +/* Power System Control Register 0 */ +#define CY_PM_PWRSYS_CR0_REG (* (reg8 *) CYREG_PWRSYS_CR0 ) +#define CY_PM_PWRSYS_CR0_PTR ( (reg8 *) CYREG_PWRSYS_CR0 ) + +/* Internal Low-speed Oscillator Control Register 0 */ +#define CY_PM_SLOWCLK_ILO_CR0_REG (* (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) +#define CY_PM_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0 ) + +/* External 32kHz Crystal Oscillator Control Register */ +#define CY_PM_SLOWCLK_X32_CR_REG (* (reg8 *) CYREG_SLOWCLK_X32_CR ) +#define CY_PM_SLOWCLK_X32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR ) + +#if(CY_PSOC3) + + /* MLOGIC Debug Register */ + #define CY_PM_MLOGIC_DBG_REG (* (reg8 *) CYREG_MLOGIC_DEBUG ) + #define CY_PM_MLOGIC_DBG_PTR ( (reg8 *) CYREG_MLOGIC_DEBUG ) + + /* Port Pin Configuration Register */ + #define CY_PM_PRT1_PC3_REG (* (reg8 *) CYREG_PRT1_PC3 ) + #define CY_PM_PRT1_PC3_PTR ( (reg8 *) CYREG_PRT1_PC3 ) + +#endif /* (CY_PSOC3) */ + + +/* Sleep Regulator Trim Register */ +#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR ) +#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR ) + + +/* Reset System Control Register */ +#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 ) +#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 ) + +/* Power Mode Wakeup Trim Register 0 */ +#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) +#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 ) + +#if(CY_PSOC3) + + /* Power Mode Wakeup Trim Register 2 */ + #define CY_PM_PWRSYS_WAKE_TR2_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + #define CY_PM_PWRSYS_WAKE_TR2_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR2 ) + +#endif /* (CY_PSOC3) */ + +/* Power Manager Interrupt Status Register */ +#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR ) +#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR ) + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_REG (* (reg8 *) CYREG_PM_ACT_CFG0 ) +#define CY_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0 ) + +/* Active Power Mode Configuration Register 1 */ +#define CY_PM_ACT_CFG1_REG (* (reg8 *) CYREG_PM_ACT_CFG1 ) +#define CY_PM_ACT_CFG1_PTR ( (reg8 *) CYREG_PM_ACT_CFG1 ) + +/* Active Power Mode Configuration Register 2 */ +#define CY_PM_ACT_CFG2_REG (* (reg8 *) CYREG_PM_ACT_CFG2 ) +#define CY_PM_ACT_CFG2_PTR ( (reg8 *) CYREG_PM_ACT_CFG2 ) + +/* Boost Control 1 */ +#define CY_PM_BOOST_CR1_REG (* (reg8 *) CYREG_BOOST_CR1 ) +#define CY_PM_BOOST_CR1_PTR ( (reg8 *) CYREG_BOOST_CR1 ) + +/* Timewheel Configuration Register 0 */ +#define CY_PM_TW_CFG0_REG (* (reg8 *) CYREG_PM_TW_CFG0 ) +#define CY_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0 ) + +/* Timewheel Configuration Register 1 */ +#define CY_PM_TW_CFG1_REG (* (reg8 *) CYREG_PM_TW_CFG1 ) +#define CY_PM_TW_CFG1_PTR ( (reg8 *) CYREG_PM_TW_CFG1 ) + +/* Timewheel Configuration Register 2 */ +#define CY_PM_TW_CFG2_REG (* (reg8 *) CYREG_PM_TW_CFG2 ) +#define CY_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2 ) + +/* PLL Status Register */ +#define CY_PM_FASTCLK_PLL_SR_REG (*(reg8 *) CYREG_FASTCLK_PLL_SR ) +#define CY_PM_FASTCLK_PLL_SR_PTR ( (reg8 *) CYREG_FASTCLK_PLL_SR ) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_REG (* (reg8 *) CYREG_FASTCLK_IMO_CR ) +#define CY_PM_FASTCLK_IMO_CR_PTR ( (reg8 *) CYREG_FASTCLK_IMO_CR ) + +/* PLL Configuration Register */ +#define CY_PM_FASTCLK_PLL_CFG0_REG (* (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) +#define CY_PM_FASTCLK_PLL_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_PLL_CFG0 ) + +/* External 4-33 MHz Crystal Oscillator Status and Control Register */ +#define CY_PM_FASTCLK_XMHZ_CSR_REG (* (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) +#define CY_PM_FASTCLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR ) + +/* Delay block Configuration Register */ +#define CY_PM_CLKDIST_DELAY_REG (* (reg8 *) CYREG_CLKDIST_DLY1 ) +#define CY_PM_CLKDIST_DELAY_PTR ( (reg8 *) CYREG_CLKDIST_DLY1 ) + + +#if(CY_PSOC3) + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CR ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CR ) + +#else /* Device is PSoC 5 */ + + /* Cache Control Register */ + #define CY_PM_CACHE_CR_REG (* (reg8 *) CYREG_CACHE_CC_CTL ) + #define CY_PM_CACHE_CR_PTR ( (reg8 *) CYREG_CACHE_CC_CTL ) + +#endif /* (CY_PSOC3) */ + + +/* Power Mode Wakeup Mask Configuration Register 0 */ +#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 ) +#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 ) + +/* Power Mode Wakeup Mask Configuration Register 1 */ +#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 ) +#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 ) + +/* Power Mode Wakeup Mask Configuration Register 2 */ +#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 ) +#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 ) + +/* Boost Control 2 */ +#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 ) +#define CY_PM_BOOST_CR2_PTR ( (reg8 *) CYREG_BOOST_CR2 ) + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_REG (* (reg8 *) CYREG_INTC_CSR_EN ) + #define CY_PM_INTC_CSR_EN_PTR ( (reg8 *) CYREG_INTC_CSR_EN ) + +#endif /* (CY_PSOC3) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Internal Main Oscillator Control Register */ + +#define CY_PM_FASTCLK_IMO_CR_FREQ_MASK (0x07u) /* IMO frequency mask */ +#define CY_PM_FASTCLK_IMO_CR_FREQ_12MHZ (0x00u) /* IMO frequency 12 MHz */ +#define CY_PM_FASTCLK_IMO_CR_F2XON (0x10u) /* IMO doubler enable */ +#define CY_PM_FASTCLK_IMO_CR_USB (0x40u) /* IMO is in USB mode */ + +#define CY_PM_MASTER_CLK_SRC_IMO (0u) +#define CY_PM_MASTER_CLK_SRC_PLL (1u) +#define CY_PM_MASTER_CLK_SRC_XTAL (2u) +#define CY_PM_MASTER_CLK_SRC_DSI (3u) +#define CY_PM_MASTER_CLK_SRC_MASK (3u) + +#define CY_PM_PLL_CFG0_ENABLE (0x01u) /* PLL enable */ +#define CY_PM_PLL_STATUS_LOCK (0x01u) /* PLL Lock Status */ +#define CY_PM_XMHZ_CSR_ENABLE (0x01u) /* Enable X MHz OSC */ +#define CY_PM_XMHZ_CSR_XERR (0x80u) /* High indicates failure */ +#define CY_PM_BOOST_ENABLE (0x08u) /* Boost enable */ +#define CY_PM_ILO_CR0_EN_1K (0x02u) /* Enable 1kHz ILO */ +#define CY_PM_ILO_CR0_EN_100K (0x04u) /* Enable 100kHz ILO */ +#define CY_PM_ILO_CR0_PD_MODE (0x10u) /* Power down mode for ILO*/ +#define CY_PM_X32_CR_X32EN (0x01u) /* Enable 32kHz OSC */ + +#define CY_PM_CTW_IE (0x08u) /* CTW interrupt enable */ +#define CY_PM_CTW_EN (0x04u) /* CTW enable */ +#define CY_PM_FTW_IE (0x02u) /* FTW interrupt enable */ +#define CY_PM_FTW_EN (0x01u) /* FTW enable */ +#define CY_PM_1PPS_EN (0x10u) /* 1PPS enable */ +#define CY_PM_1PPS_IE (0x20u) /* 1PPS interrupt enable */ + + +#define CY_PM_ACT_EN_CLK_A_MASK (0x0Fu) +#define CY_PM_ACT_EN_CLK_D_MASK (0xFFu) + +#define CY_PM_DIV_BY_ONE (0x00u) + +/* Internal Main Oscillator Control Register */ +#define CY_PM_FASTCLK_IMO_CR_XCLKEN (0x20u) + +/* Clock distribution configuration Register */ +#define CY_PM_CLKDIST_IMO_OUT_MASK (0x30u) +#define CY_PM_CLKDIST_IMO_OUT_IMO (0x00u) +#define CY_PM_CLKDIST_IMO2X_SRC (0x40u) + +#define CY_PM_CLKDIST_PLL_SRC_MASK (0x03u) +#define CY_PM_CLKDIST_PLL_SRC_IMO (0x00u) +#define CY_PM_CLKDIST_PLL_SRC_XTAL (0x01u) +#define CY_PM_CLKDIST_PLL_SRC_DSI (0x02u) + +/* Waiting for hibernate/sleep regulator to stabilize */ +#define CY_PM_MODE_CSR_PWRUP_PULSE_Q (0x08u) + +#define CY_PM_MODE_CSR_ACTIVE (0x00u) /* Active power mode */ +#define CY_PM_MODE_CSR_ALT_ACT (0x01u) /* Alternate Active power */ +#define CY_PM_MODE_CSR_SLEEP (0x03u) /* Sleep power mode */ +#define CY_PM_MODE_CSR_HIBERNATE (0x04u) /* Hibernate power mode */ +#define CY_PM_MODE_CSR_MASK (0x07u) + +/* I2C regulator backup enable */ +#define CY_PM_PWRSYS_CR1_I2CREG_BACKUP (0x04u) + +/* When set, prepares system to disable LDO-A */ +#define CY_PM_PWRSYS_CR1_LDOA_ISO (0x01u) + +/* When set, disables analog LDO regulator */ +#define CY_PM_PWRSYS_CR1_LDOA_DIS (0x02u) + +#define CY_PM_PWRSYS_WAKE_TR2_VCCD_CLK_DET (0x04u) + +#define CY_PM_FTW_INT (0x01u) /* FTW event has occured */ +#define CY_PM_CTW_INT (0x02u) /* CTW event has occured */ +#define CY_PM_ONEPPS_INT (0x04u) /* 1PPS event has occured */ + +/* Active Power Mode Configuration Register 0 */ +#define CY_PM_ACT_CFG0_IMO (0x10u) /* IMO enable in Active */ + +/* Cache Control Register (same mask for all device revisions) */ +#define CY_PM_CACHE_CR_CYCLES_MASK (0xC0u) + +/* Bus Clock divider to divide-by-one */ +#define CY_PM_BUS_CLK_DIV_BY_ONE (0x00u) + +/* HVI/LVI feature on external analog and digital supply mask */ +#define CY_PM_RESET_CR1_HVI_LVI_EN_MASK (0x07u) + +/* High-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_HVIA_EN (0x04u) + +/* Low-voltage-interrupt feature on external analog supply */ +#define CY_PM_RESET_CR1_LVIA_EN (0x02u) + +/* Low-voltage-interrupt feature on external digital supply */ +#define CY_PM_RESET_CR1_LVID_EN (0x01u) + +/* Allows system to program delays on clk_sync_d */ +#define CY_PM_CLKDIST_DELAY_EN (0x04u) + + +#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu) + +/* Holdoff mask sleep trim */ +#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu) + +#if(CY_PSOC3) + + /* CPU clock divider mask */ + #define CY_PM_CLKDIST_CPU_DIV_MASK (0xF0u) + + /* Serial Wire View (SWV) clock enable */ + #define CY_PM_MLOGIC_DBG_SWV_CLK_EN (0x04u) + + /* Port drive mode */ + #define CY_PM_PRT1_PC3_DM_MASK (0xf1u) + + /* Mode 6, stong pull-up, strong pull-down */ + #define CY_PM_PRT1_PC3_DM_STRONG (0x0Cu) + + /* When set, enables buzz wakeups */ + #define CY_PM_PWRSYS_WAKE_TR2_EN_BUZZ (0x01u) + +#endif /* (CY_PSOC3) */ + + +/* Disables sleep regulator and shorts vccd to vpwrsleep */ +#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u) + +/* Boost Control 2: Select external precision reference */ +#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u) + +#if(CY_PSOC3) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0x90u) + +#endif /* (CY_PSOC3) */ + +#if(CY_PSOC5) + + #define CY_PM_PWRSYS_WAKE_TR0 (0xFFu) + #define CY_PM_PWRSYS_WAKE_TR1 (0xB0u) + +#endif /* (CY_PSOC5) */ + +#if(CY_PSOC3) + + /* Interrrupt Controller Configuration and Status Register */ + #define CY_PM_INTC_CSR_EN_CLK (0x01u) + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Lock Status Flag. If lock is acquired this flag will stay set (regardless of +* whether lock is subsequently lost) until it is read. Upon reading it will +* clear. If lock is still true then the bit will simply set again. If lock +* happens to be false when the clear on read occurs then the bit will stay +* cleared until the next lock event. +*******************************************************************************/ +#define CY_PM_FASTCLK_PLL_LOCKED (0x01u) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting with cy_boot 3.30 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#if(CY_PSOC3) + + /* Was removed as redundant */ + #define CY_PM_FTW_INTERVAL_MASK (0xFFu) + +#endif /* (CY_PSOC3) */ + +/* Was removed as redundant */ +#define CY_PM_CTW_INTERVAL_MASK (0x0Fu) + +#endif /* (CY_BOOT_CYPM_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c new file mode 100644 index 0000000..ce94d9c --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.c @@ -0,0 +1,1416 @@ +/***************************************************************************//** +* \file cy_em_eeprom.c +* \version 2.0 +* +* \brief +* This file provides source code of the API for the Emulated EEPROM library. +* The Emulated EEPROM API allows creating of an emulated EEPROM in flash that +* has the ability to do wear leveling and restore corrupted data from a +* redundant copy. +* +******************************************************************************** +* \copyright +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + + +#include "cytypes.h" +#include + +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include "em_eeprom/cy_em_eeprom.h" +#else + #include "cy_em_eeprom.h" +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + + +#if defined(__cplusplus) +extern "C" { +#endif + + +/*************************************** +* Private Function Prototypes +***************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context); +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context); +static uint8 CalcChecksum(uint8 rowData[], uint32 len); +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config); +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, uint32 *rowData, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, uint32 ramBuffAddr, cy_stc_eeprom_context_t * context); +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context); +static uint32 GetAddresses(uint32 *startAddr, uint32 *endAddr, uint32 *offset, uint32 rowNum, uint32 addr, uint32 len); +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context); + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Init +****************************************************************************//** +* +* Initializes the Emulated EEPROM library by filling the context structure. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \param context +* The pointer to the EEPROM context structure to be filled by the function. +* \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* The context structure should not be modified by the user after it is filled +* with this function. Modification of context structure may cause the +* unexpected behavior of the Cy_Em_EEPROM API functions which rely on it. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* If the "Redundant Copy" option is used, the function performs a number of +* write operations to the EEPROM to initialize flash rows checksums. Therefore, +* Cy_Em_EEPROM_NumWrites(), when it is called right after Cy_Em_EEPROM_Init(), +* will return a non-zero value that identifies the number of writes performed +* by Cy_Em_EEPROM_Init(). +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + if((NULL != context) && (NULL != config) && (NULL != ((uint32 *)config->userFlashStartAddr)) && + (config->wearLevelingFactor <= CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR) && (config->eepromSize != 0u)) + { + ret = CheckRanges(config); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Copy the user config structure fields into context */ + context->eepromSize = config->eepromSize; + context->wearLevelingFactor = config->wearLevelingFactor; + context->redundantCopy = config->redundantCopy; + context->blockingWrite = config->blockingWrite; + context->userFlashStartAddr = config->userFlashStartAddr; + /* Store frequently used data for internal use */ + context->numberOfRows = CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(config->eepromSize); + context->wlEndAddr = ((CY_EM_EEPROM_GET_EEPROM_SIZE(context->numberOfRows) * config->wearLevelingFactor) + + config->userFlashStartAddr); + /* Find last written EEPROM row and store it for quick access */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + + if((0u == CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)) && (0u != context->redundantCopy)) + { + /* Call the function only after device reprogramming in case + * if redundant copy is enabled. + */ + ret = FillChecksum(context); + + /* Update the last written EEPROM row for Cy_Em_EEPROM_NumWrites() */ + FindLastWrittenRow(&context->lastWrRowAddr, context); + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Read +****************************************************************************//** +* +* This function takes the logical EEPROM address, converts it to the actual +* physical address where the data is stored and returns the data to the user. +* +* \param addr +* The logical start address in EEPROM to start reading data from. +* +* \param eepromData +* The pointer to a user array to write data to. +* +* \param size +* The amount of data to read. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \note +* In case if redundant copy option is enabled the function may perform writes +* to EEPROM. This is done in case if the data in the EEPPROM is corrupted and +* the data in redundant copy is valid based on CRC-8 data integrity check. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 numBytesToRead; + uint32 curEepromBaseAddr; + uint32 curRowOffset; + uint32 startRowAddr; + uint32 actEepromRowNum; + uint32 curRdEepromRowNum = 0u; + uint32 dataStartEepromRowNum = 0u; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Validate input parameters */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 rdAddr = addr; + uint32 rdSize = size; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr); + uint32 updateAddrFlag = 0u; + + /* Calculate the number of the row read operations. Currently this only concerns + * the reads from the EEPROM data locations. + */ + uint32 numRowReads = ((((rdAddr + rdSize) - 1u) / CY_EM_EEPROM_EEPROM_DATA_LEN) - + (rdAddr / CY_EM_EEPROM_EEPROM_DATA_LEN)) + 1u; + + /* Get the address of the first row of the currently active EEPROM sector. If + * no wear leveling is used - the EEPROM has only one sector, so use the base + * addr stored in "context->userFlashStartAddr". + */ + curEepromBaseAddr = (((context->lastWrRowAddr - context->userFlashStartAddr) / + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) * + (CY_EM_EEPROM_FLASH_SIZEOF_ROW * context->numberOfRows)) + + context->userFlashStartAddr; + + /* Find the number of the row that contains the start address of the data */ + for(i = 0u; i < context->numberOfRows; i++) + { + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(rdAddr, i)) + { + dataStartEepromRowNum = i; + curRdEepromRowNum = dataStartEepromRowNum; + break; + } + } + + /* Find the row number of the last written row */ + actEepromRowNum = (context->lastWrRowAddr - curEepromBaseAddr) / CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + /* Check if wear leveling is used */ + if(context->wearLevelingFactor > 1u) + { + uint32 dataEndEepromRowNum = dataStartEepromRowNum + (numRowReads - 1u); + + /* Check if the future validation of the read address is required. */ + updateAddrFlag = (dataStartEepromRowNum > actEepromRowNum) ? 1u : + ((dataEndEepromRowNum > actEepromRowNum) ? 1u : 0u); + } + + /* Copy data from the EEPROM data locations to the user buffer */ + for(i = 0u; i < numRowReads; i++) + { + startRowAddr = curEepromBaseAddr + (curRdEepromRowNum * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + curRowOffset = CY_EM_EEPROM_EEPROM_DATA_LEN + (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Check if there are more reads pending and update the number of the + * remaining bytes to read respectively. + */ + if((i + 1u) < numRowReads) + { + numBytesToRead = CY_EM_EEPROM_EEPROM_DATA_LEN - (rdAddr % CY_EM_EEPROM_EEPROM_DATA_LEN); + } + else + { + numBytesToRead = rdSize; + } + + /* Check if the read address needs to be updated to point to the correct + * EEPROM sector. + */ + if((0u != updateAddrFlag) && (curRdEepromRowNum > actEepromRowNum)) + { + startRowAddr -= context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if(startRowAddr < context->userFlashStartAddr) + { + startRowAddr = context->wlEndAddr - + ((context->numberOfRows - curRdEepromRowNum) * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + + if(0u != context->redundantCopy) + { + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in + * the corresponding row in redundant copy, otherwise return failure. + */ + ret = CheckCrcAndCopy(startRowAddr, eeData, curRowOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + /* Copy the data to the user buffer */ + (void)memcpy((void *)(eeData), + (void *)(startRowAddr + curRowOffset), + numBytesToRead); + + /* Indicate success to be able to execute next code block */ + ret = CY_EM_EEPROM_SUCCESS; + } + + /* Update variables anticipated in the read operation */ + rdAddr += numBytesToRead; + rdSize -= numBytesToRead; + eeData += numBytesToRead; + curRdEepromRowNum++; + } + + /* This code block will copy the latest data from the EEPROM headers into the + * user buffer. The data previously copied into the user buffer may be updated + * as the EEPROM headers contain more recent data. + * The code block is executed when two following conditions are true: + * 1) The reads from "historic" data locations were successful; + * 2) The user performed at least one write operation to Em_EEPROM (0u != + * seqNum). + */ + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != seqNum)) + { + numRowReads = (context->numberOfRows <= seqNum) ? (context->numberOfRows) : (seqNum); + numRowReads--; + + for(i = (seqNum - numRowReads); i <= seqNum; i++) + { + startRowAddr = GetRowAddrBySeqNum(i, context); + + if (0u != startRowAddr) + { + /* The following variables are introduced to increase code readability. */ + uint32 startAddr = *(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET); + uint32 endAddr = startAddr + (*(uint32 *)(startRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + + /* Check if the current row EEPROM header contains the data requested for read */ + if(0u != CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr, endAddr, addr, addr + size)) + { + uint32 srcOffset = (startAddr > addr) ? (0u) : (addr - startAddr); + uint32 dstOffset = (startAddr > addr) ? (startAddr - addr): (0u); + rdAddr = (startAddr > addr) ? (startAddr) : (addr); + + srcOffset += CY_EM_EEPROM_HEADER_DATA_OFFSET; + + /* Calculate the number of bytes to be read from the current row's EEPROM header */ + numBytesToRead = ((endAddr < (addr + size)) ? endAddr : (addr + size)) - rdAddr; + + /* Calculate the offset in the user buffer from which the data will be updated. */ + eeData = ((uint32)eepromData) + dstOffset; + + /* Check a checksum of the EEPROM row and if it is bad, check a checksum in the + * corresponding row in redundant copy, otherwise return failure. Copy the data + * from the recent EEPROM headers to the user buffer. This will overwrite the + * data copied form EEPROM data locations as the data in EEPROM headers is newer. + */ + if(0u != context->redundantCopy) + { + ret = CheckCrcAndCopy(startRowAddr, eeData, srcOffset, numBytesToRead, context); + + if(CY_EM_EEPROM_SUCCESS != ret) + { + break; + } + } + else + { + (void)memcpy((void *)(eeData), (void *)(startRowAddr + srcOffset), numBytesToRead); + } + } + } + } + } + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Write +****************************************************************************//** +* +* This function takes the logical EEPROM address and converts it to the actual +* physical address and writes data there. If wear leveling is implemented, the +* writing process will use the wear leveling techniques. This is a blocking +* function and it does not return until the write operation is completed. The +* user firmware should not enter Hibernate mode until write is completed. The +* write operation is allowed in Sleep and Deep-Sleep modes. During the flash +* operation, the device should not be reset, including the XRES pin, a software +* reset, and watchdog reset sources. Also, low-voltage detect circuits should +* be configured to generate an interrupt instead of a reset. Otherwise, portions +* of flash may undergo unexpected changes. +* +* \param addr +* The logical start address in EEPROM to start writing data from. +* +* \param eepromData +* Data to write to EEPROM. +* +* \param size +* The amount of data to write to EEPROM. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform write +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM write is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + uint32 i; + uint32 wrCnt; + uint32 actEmEepromRowNum; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 startAddr = 0u; + uint32 endAddr = 0u; + uint32 tmpRowAddr; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + void * tmpData; + uint32 eeData = (uint32) eepromData; /* To avoid the pointer arithmetic with void */ + + /* Check if the EEPROM data does not exceed the EEPROM capacity */ + if((0u != size) && ((addr + size) <= (context->eepromSize)) && (NULL != eepromData)) + { + uint32 numWrites = ((size - 1u) / CY_EM_EEPROM_HEADER_DATA_LEN) + 1u; + uint32 eeHeaderDataOffset = 0u; + + for(wrCnt = 0u; wrCnt < numWrites; wrCnt++) + { + uint32 skipOperation = 0u; + /* Get the sequence number of the last written row */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* Get the address of the row to be written. The "emEepromRowAddr" may be + * updated with the proper address (if wear leveling is used). The + * "emEepromRowRdAddr" will point to the row address from which the historic + * data will be read into the RAM buffer. + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + + /* Clear the RAM buffer so to not put junk into flash */ + (void)memset(writeRamBuffer, 0, CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Fill the EM_EEPROM header info for the row in the RAM buffer */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + writeRamBuffer[CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32] = addr; + tmpData = (void *) eeData; + + /* Check if this is the last row to write */ + if(wrCnt == (numWrites - 1u)) + { + /* Fill in the remaining size value to the EEPROM header. */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = size; + } + else + { + /* This is not the last row to write in the current EEPROM write operation. + * Write the maximum possible data size to the EEPROM header. Update the + * size, eeData and addr respectively. + */ + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32] = CY_EM_EEPROM_HEADER_DATA_LEN; + size -= CY_EM_EEPROM_HEADER_DATA_LEN; + addr += CY_EM_EEPROM_HEADER_DATA_LEN; + eeData += CY_EM_EEPROM_HEADER_DATA_LEN; + } + + /* Write the data to the EEPROM header */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_HEADER_DATA_OFFSET_U32], + tmpData, + writeRamBuffer[CY_EM_EEPROM_HEADER_LEN_OFFSET_U32]); + + if(emEepromRowRdAddr != 0UL) + { + /* Copy the EEPROM historic data for this row from flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + (void *)(emEepromRowRdAddr + CY_EM_EEPROM_EEPROM_DATA_LEN), + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + /* Check if there is data for this location in other EEPROM headers: + * find out the row with the lowest possible sequence number which + * may contain the data for the current row. + */ + i = (seqNum > context->numberOfRows) ? ((seqNum - (context->numberOfRows)) + 1u) : 1u; + + for(; i <= seqNum; i++) + { + if(i == seqNum) + { + /* The code reached the row that is about to be written. Analyze the recently + * created EEPROM header (stored in the RAM buffer currently): if it contains + * the data for EEPROM data locations in the row that is about to be written. + */ + tmpRowAddr = (uint32) writeRamBuffer; + } + else + { + /* Retrieve the address of the previously written row by its sequence number. + * The pointer will be used to get data from the respective EEPROM header. + */ + tmpRowAddr = GetRowAddrBySeqNum(i, context); + } + + actEmEepromRowNum = CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(emEepromRowAddr, + context->numberOfRows, + context->userFlashStartAddr); + if(0UL != tmpRowAddr) + { + /* Calculate the required addressed for the later EEPROM historic data update */ + skipOperation = GetAddresses( + &startAddr, + &endAddr, + &eeHeaderDataOffset, + actEmEepromRowNum, + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_ADDR_OFFSET), + *(uint32 *)(tmpRowAddr + CY_EM_EEPROM_HEADER_LEN_OFFSET)); + } + else + { + /* Skip writes to the RAM buffer */ + skipOperation++; + } + + /* Write data to the RAM buffer */ + if(0u == skipOperation) + { + uint32 dataAddr = ((uint32)((uint8 *)&writeRamBuffer)) + startAddr; + + /* Update the address to point to the EEPROM header data and not to + * the start of the row. + */ + tmpRowAddr = tmpRowAddr + CY_EM_EEPROM_HEADER_DATA_OFFSET + eeHeaderDataOffset; + (void)memcpy((void *)(dataAddr), (void *)(tmpRowAddr), endAddr - startAddr); + } + + /* Calculate the checksum if redundant copy is enabled */ + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + } + + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, writeRamBuffer, context); + tmpRowAddr = emEepromRowAddr; + + /* Check if redundant copy is used */ + if((0u != context->redundantCopy) && (CY_EM_EEPROM_SUCCESS == ret)) + { + /* Update the row address to point to the row in the redundant EEPROM's copy */ + tmpRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Store last written row address only when EEPROM and redundant + * copy writes were successful. + */ + context->lastWrRowAddr = emEepromRowAddr; + } + else + { + break; + } + } + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_Erase +****************************************************************************//** +* +* This function erases the entire contents of the EEPROM. Erased values are all +* zeros. This is a blocking function and it does not return until the write +* operation is completed. The user firmware should not enter Hibernate mode until +* erase is completed. The erase operation is allowed in Sleep and Deep-Sleep modes. +* During the flash operation, the device should not be reset, including the +* XRES pin, a software reset, and watchdog reset sources. Also, low-voltage +* detect circuits should be configured to generate an interrupt instead of a +* reset. Otherwise, portions of flash may undergo unexpected changes. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* This function returns \ref cy_en_em_eeprom_status_t. +* +* \note +* For all non PSoC 6 devices the erase operation is performed by clearing +* the EEPROM data using flash write. This affects the flash durability. +* So it is recommended to use this function in utmost case to prolongate +* flash life. +* +* \note +* This function uses a buffer of the flash row size to perform erase +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +* \sideeffect +* In case when blocking write option is used, if this function is called by +* the CM4 the user code on CM0P and the user code on CM4 are blocked until erase +* flash row operation is finished. If this function is called by the CM0P the +* user code on CM4 is not blocked and the user code on CM0P is blocked until +* erase flash row operation is finished. Plan your task allocation accordingly. +* +* \sideeffect +* In case if non-blocking write option is used and when user flash is used as +* an EEPROM storage care should be taken to prevent the read while write (RWW) +* exception. To prevent the RWW exception the user flash macro that includes +* the EEPROM storage should not be read while the EEPROM erase is not completed. +* The read also means the user code execution from the respective flash macro. +* +*******************************************************************************/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 seqNum; + uint32 emEepromRowAddr = context->lastWrRowAddr; + uint32 emEepromRowRdAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV] = {0u}; +#if (CY_PSOC6) + uint32 emEepromStoredRowAddr = context->lastWrRowAddr; + uint32 storedSeqNum; +#endif /* (!CY_PSOC6) */ + + /* Get the sequence number of the last written row */ + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + + /* If there were no writes to EEPROM - nothing to erase */ + if(0u != seqNum) + { + /* Calculate the number of row erase operations required */ + uint32 numWrites = context->numberOfRows * context->wearLevelingFactor; + + #if (CY_PSOC6) + GetNextRowToWrite(seqNum, &emEepromStoredRowAddr, &emEepromRowRdAddr, context); + storedSeqNum = seqNum + 1u; + #endif /* (CY_PSOC6) */ + + if(0u != context->redundantCopy) + { + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + } + + for(i = 0u; i < numWrites; i++) + { + #if (CY_PSOC6) + /* For PSoC 6 the erase operation moves backwards. From last written row + * identified by "seqNum" down to "seqNum" - "numWrites". If "emEepromRowAddr" + * is zero this means that the row identified by "seqNum" was previously + * erased. + */ + if(0u != emEepromRowAddr) + { + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + } + + seqNum--; + + if(0u == seqNum) + { + /* Exit the loop as there is no more row is EEPROM to be erased */ + break; + } + emEepromRowAddr = GetRowAddrBySeqNum(seqNum, context); + #else + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromRowAddr); + /* Get the address of the row to be erased. "emEepromRowAddr" may be updated + * with the proper address (if wear leveling is used). + */ + GetNextRowToWrite(seqNum, &emEepromRowAddr, &emEepromRowRdAddr, context); + seqNum++; + writeRamBuffer[0u] = seqNum; + ret = EraseRow(emEepromRowAddr, (uint32)writeRamBuffer, context); + #endif /* (CY_PSOC6) */ + } + + #if (CY_PSOC6) + if(CY_EM_EEPROM_SUCCESS == ret) + { + writeRamBuffer[0u] = storedSeqNum; + + /* Write the previously stored sequence number to the flash row which would be + * written next if the erase wouldn't happen. In this case the write to + * redundant copy can be skipped as it does not add any value. + */ + ret = WriteRow(emEepromStoredRowAddr, writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = emEepromStoredRowAddr; + } + } + #endif /* (CY_PSOC6) */ + + } + return(ret); +} + + +/******************************************************************************* +* Function Name: Cy_Em_EEPROM_NumWrites +****************************************************************************//** +* +* Returns the number of the EEPROM writes completed so far. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* The number of writes performed to the EEPROM. +* +*******************************************************************************/ +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context) +{ + return(CY_EM_EEPROM_GET_SEQ_NUM(context->lastWrRowAddr)); +} + +/** \} */ + +/** \cond INTERNAL */ + + +/******************************************************************************* +* Function Name: FindLastWrittenRow +****************************************************************************//** +* +* Performs a search of the last written row address of the EEPROM associated +* with the context structure. If there were no writes to the EEPROM the +* function returns the start address of the EEPROM. The row address is returned +* in the input parameter. +* +* \param lastWrRowPtr +* The pointer to a memory where the last written row will be returned. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void FindLastWrittenRow(uint32 * lastWrRowPtr, cy_stc_eeprom_context_t * context) +{ + uint32 seqNum = 0u; + uint32 prevSeqNum = 0u; + uint32 numRows; + uint32 emEepromAddr = context->userFlashStartAddr; + + *lastWrRowPtr = emEepromAddr; + + for(numRows = 0u; numRows < (context->numberOfRows * context->wearLevelingFactor); numRows++) + { + seqNum = CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr); + if((0u != seqNum) && (seqNum > prevSeqNum)) + { + /* Some record in EEPROM was found. Store found sequence + * number and row address. + */ + prevSeqNum = seqNum; + *lastWrRowPtr = emEepromAddr; + } + + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } +} + + +/******************************************************************************* +* Function Name: GetRowAddrBySeqNum +****************************************************************************//** +* +* Returns the address of the row in EEPROM using its sequence number. +* +* \param seqNum +* The sequence number of the row. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* The address of the row or zero if the row with the sequence number was not +* found. +* +*******************************************************************************/ +static uint32 GetRowAddrBySeqNum(uint32 seqNum, cy_stc_eeprom_context_t * context) +{ + uint32 emEepromAddr = context->userFlashStartAddr; + + while(CY_EM_EEPROM_GET_SEQ_NUM(emEepromAddr) != seqNum) + { + /* Switch to the next row */ + emEepromAddr = emEepromAddr + CY_EM_EEPROM_FLASH_SIZEOF_ROW; + + if (CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(emEepromAddr, context->wlEndAddr)) + { + emEepromAddr = 0u; + /* Exit the loop as we reached the end of EEPROM */ + break; + } + } + + return (emEepromAddr); +} + + +/******************************************************************************* +* Function Name: GetNextRowToWrite +****************************************************************************//** +* +* Performs a range check of the row that should be written and updates the +* address to the row respectively. The similar actions are done for the read +* address. +* +* \param seqNum +* The sequence number of the last written row. +* +* \param rowToWrPtr +* The address of the last written row (input). The address of the row to be +* written (output). +* +* \param rowToRdPtr +* The address of the row from which the data should be read into the RAM buffer +* in a later write operation. Out parameter. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +*******************************************************************************/ +static void GetNextRowToWrite(uint32 seqNum, + uint32 * rowToWrPtr, + uint32 * rowToRdPtr, + cy_stc_eeprom_context_t * context) +{ + /* Switch to the next row to be written if the current sequence number is + * not zero. + */ + if(0u != seqNum) + { + *rowToWrPtr = (*rowToWrPtr + CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + + /* If the resulting row address is out of EEPROM, then switch to the base + * EEPROM address (Row#0). + */ + if(CY_EM_EEPROM_ADDR_IN_RANGE != + CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(*rowToWrPtr, context->wlEndAddr)) + { + *rowToWrPtr = context->userFlashStartAddr; + } + + *rowToRdPtr = 0u; + + /* Check if the sequence number is larger than the number of rows in the EEPROM. + * If not, do not update the row read address because there is no historic + * data to be read. + */ + if(context->numberOfRows <= seqNum) + { + /* Check if wear leveling is used in EEPROM */ + if(context->wearLevelingFactor > 1u) + { + /* The read row address should be taken from an EEPROM copy that became + * inactive recently. This condition check handles that. + */ + if((*rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW)) < + context->userFlashStartAddr) + { + *rowToRdPtr = context->userFlashStartAddr + + (context->numberOfRows * (context->wearLevelingFactor - 1u) * + CY_EM_EEPROM_FLASH_SIZEOF_ROW) + (*rowToWrPtr - context->userFlashStartAddr); + } + else + { + *rowToRdPtr = *rowToWrPtr - (context->numberOfRows * CY_EM_EEPROM_FLASH_SIZEOF_ROW); + } + } + else + { + /* If no wear leveling, always read from the same flash row that + * should be written. + */ + *rowToRdPtr = *rowToWrPtr; + } + } +} + + +/******************************************************************************* +* Function Name: CalcChecksum +****************************************************************************//** +* +* Implements CRC-8 that is used in checksum calculation for the redundant copy +* algorithm. +* +* \param rowData +* The row data to be used to calculate the checksum. +* +* \param len +* The length of rowData. +* +* \return +* The calculated value of CRC-8. +* +*******************************************************************************/ +static uint8 CalcChecksum(uint8 rowData[], uint32 len) +{ + uint8 crc = CY_EM_EEPROM_CRC8_SEED; + uint8 i; + uint16 cnt = 0u; + + while(cnt != len) + { + crc ^= rowData[cnt]; + for (i = 0u; i < CY_EM_EEPROM_CRC8_POLYNOM_LEN; i++) + { + crc = CY_EM_EEPROM_CALCULATE_CRC8(crc); + } + cnt++; + } + + return (crc); +} + + +/******************************************************************************* +* Function Name: CheckRanges +****************************************************************************//** +* +* Checks if the EEPROM of the requested size can be placed in flash. +* +* \param config +* The pointer to a configuration structure. See \ref cy_stc_eeprom_config_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckRanges(cy_stc_eeprom_config_t* config) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_DATA; + uint32 startAddr = config->userFlashStartAddr; + uint32 endAddr = startAddr + CY_EM_EEPROM_GET_PHYSICAL_SIZE(config->eepromSize, + config->wearLevelingFactor, config->redundantCopy); + + /* Range check if there is enough flash for EEPROM */ + if (CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + return (ret); +} + + +/******************************************************************************* +* Function Name: WriteRow +****************************************************************************//** +* +* Writes one flash row starting from the specified row address. +* +* \param rowAdd +* The address of the flash row. +* +* \param rowData +* The pointer to the data to be written to the row. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t WriteRow(uint32 rowAddr, + uint32 *rowData, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (!CY_PSOC6) + cystatus rc; + uint32 rowId; + #if ((CY_PSOC3) || (CY_PSOC5)) + uint32 arrayId; + #endif /* (CY_PSOC3) */ + + #if (CY_PSOC3) + rowAddr &= CY_EM_EEPROM_CODE_ADDR_MASK; + context = context; /* To avoid compiler warning generation */ + #else + (void)context; /* To avoid compiler warning generation */ + #endif /* ((CY_PSOC3) */ + + /* For non-PSoC 6 devices, the Array ID and Row ID needed to write the row */ + rowId = (rowAddr / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % CY_EM_EEPROM_ROWS_IN_ARRAY; + + /* Write the flash row */ + #if (CY_PSOC4) + rc = CySysFlashWriteRow(rowId, (uint8 *)rowData); + #else + + #ifndef CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT + (void)CySetTemp(); + #endif /* (CY_EM_EEPROM_SKIP_TEMP_MEASUREMENT) */ + + arrayId = rowAddr / CY_FLASH_SIZEOF_ARRAY; + rc = CyWriteRowData((uint8)arrayId, (uint16)rowId, (uint8 *)rowData); + + #if (CY_PSOC5) + CyFlushCache(); + #endif /* (CY_PSOC5) */ + #endif /* (CY_PSOC4) */ + + if(CYRET_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } +#else /* PSoC 6 */ + if(0u != context->blockingWrite) + { + /* Do blocking write */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_WriteRow(rowAddr, (const uint32 *)rowData)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate write */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartWrite(rowAddr, (const uint32 *)rowData)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if write completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } +#endif /* (CY_PSOC6) */ + + return (ret); +} + + +/******************************************************************************* +* Function Name: EraseRow +****************************************************************************//** +* +* Erases one flash row starting from the specified row address. If the redundant +* copy option is enabled the corresponding row in the redundant copy will also +* be erased. +* +* \param rowAdd +* The address of the flash row. +* +* \param ramBuffAddr +* The address of the RAM buffer that contains zeroed data (used only for +* non-PSoC 6 devices). +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t EraseRow(uint32 rowAddr, + uint32 ramBuffAddr, + cy_stc_eeprom_context_t * context) +{ + uint32 emEepromRowAddr = rowAddr; + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_WRITE_FAIL; +#if (CY_PSOC6) + uint32 i = 1u; + + (void)ramBuffAddr; /* To avoid compiler warning */ + + if(0u != context->redundantCopy) + { + i++; + } + + do + { + if(0u != context->blockingWrite) + { + /* Erase the flash row */ + if(CY_FLASH_DRV_SUCCESS == Cy_Flash_EraseRow(emEepromRowAddr)) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + else + { + /* Initiate erase */ + if(CY_FLASH_DRV_OPERATION_STARTED == Cy_Flash_StartErase(emEepromRowAddr)) + { + uint32 countMs = CY_EM_EEPROM_MAX_WRITE_DURATION_MS; + cy_en_flashdrv_status_t rc; + + do + { + CyDelay(1u); /* Wait 1ms */ + rc = Cy_Flash_IsWriteComplete(); /* Check if erase completed */ + countMs--; + } + while ((rc == CY_FLASH_DRV_OPCODE_BUSY) && (0u != countMs)); + + if(CY_FLASH_DRV_SUCCESS == rc) + { + ret = CY_EM_EEPROM_SUCCESS; + } + } + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + } + else + { + break; + } + i--; + } while (0u != i); +#else + /* Write the data to the specified flash row */ + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + + if((CY_EM_EEPROM_SUCCESS == ret) && (0u != context->redundantCopy)) + { + /* Update the address to point to the redundant copy row */ + emEepromRowAddr = (emEepromRowAddr - context->userFlashStartAddr) + context->wlEndAddr; + ret = WriteRow(emEepromRowAddr, (uint32 *)ramBuffAddr, context); + } + + if(CY_EM_EEPROM_SUCCESS == ret) + { + context->lastWrRowAddr = rowAddr; + } +#endif /* (CY_PSOC6) */ + + return(ret); +} + + +/******************************************************************************* +* Function Name: CheckCrcAndCopy +****************************************************************************//** +* +* Checks the checksum of the specific row in EEPROM. If the CRC matches - copies +* the data to the "datAddr" from EEPROM. f the CRC does not match checks the +* CRC of the corresponding row in the EEPROM's redundant copy. If the CRC +* matches - copies the data to the "datAddr" from EEPROM redundant copy. If the +* CRC of the redundant copy does not match - returns bad checksum. +* +* \param startAddr +* The address that points to the start of the specified row. +* +* \param datAddr +* The start address of where the row data will be copied if the CRC check +* will succeed. +* +* \param rowOffset +* The offset in the row from which the data should be copied. +* +* \param numBytes +* The number of bytes to be copied. +* +* \param context +* The pointer to the EEPROM context structure \ref cy_stc_eeprom_context_t. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t CheckCrcAndCopy(uint32 startAddr, + uint32 dstAddr, + uint32 rowOffset, + uint32 numBytes, + cy_stc_eeprom_context_t * context) +{ + cy_en_em_eeprom_status_t ret; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + + /* Calculate the row address in the EEPROM's redundant copy */ + uint32 rcStartRowAddr = (startAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Check the row data CRC in the EEPROM */ + if((*(uint32 *)(startAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(startAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + (void)memcpy((void *)(dstAddr), (void *)(startAddr + rowOffset), numBytes); + + ret = CY_EM_EEPROM_SUCCESS; + } + /* Check the row data CRC in the EEPROM's redundant copy */ + else if((*(uint32 *)(rcStartRowAddr + CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET)) == + ((uint32) CalcChecksum((uint8 *)(rcStartRowAddr + CY_EM_EEPROM_EEPROM_DATA_OFFSET), + CY_EM_EEPROM_EEPROM_DATA_LEN))) + { + /* Copy the redundant copy row to RAM buffer to avoid read while write (RWW) + * flash exception. The RWW occurs while trying to write and read the data from + * same flash macro. + */ + (void)memcpy((void *)(writeRamBuffer), (void *)(rcStartRowAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Restore bad row data from the RAM buffer */ + ret = WriteRow(startAddr, (uint32 *)writeRamBuffer, context); + + if(CY_EM_EEPROM_SUCCESS == ret) + { + (void)memcpy((void *)(dstAddr), (void *)(writeRamBuffer + rowOffset), numBytes); + } + } + else + { + ret = CY_EM_EEPROM_BAD_CHECKSUM; + } + + return(ret); +} + + +/******************************************************************************* +* Function Name: GetAddresses +****************************************************************************//** +* +* Calculates the start and end address of the row's EEPROM data to be updated. +* The start and end are not absolute addresses but a relative addresses in a +* flash row. +* +* \param startAddr +* The pointer the address where the EEPROM data start address will be returned. +* +* \param endAddr +* The pointer the address where the EEPROM data end address will be returned. +* +* \param offset +* The pointer the address where the calculated offset of the EEPROM header data +* will be returned. +* +* \param rowNum +* The row number that is about to be written. +* +* \param addr +* The address of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \param len +* The length of the EEPROM header data in the currently analyzed row that may +* concern to the row about to be written. +* +* \return +* Zero indicates that the currently analyzed row has the data to be written to +* the active EEPROM row data locations. Non zero value indicates that there is +* no data to be written +* +*******************************************************************************/ +static uint32 GetAddresses(uint32 *startAddr, + uint32 *endAddr, + uint32 *offset, + uint32 rowNum, + uint32 addr, + uint32 len) +{ + uint32 skip = 0u; + + *offset =0u; + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN + (addr % CY_EM_EEPROM_EEPROM_DATA_LEN); + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *endAddr = *startAddr + len; + } + else + { + *endAddr = CY_EM_EEPROM_FLASH_SIZEOF_ROW; + } + } + else + { + + if(0u != CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr + len, rowNum)) + { + *startAddr = CY_EM_EEPROM_EEPROM_DATA_LEN; + *endAddr = (*startAddr + len) - (*startAddr - (addr % CY_EM_EEPROM_EEPROM_DATA_LEN)); + *offset = len - (*endAddr - *startAddr); + } + else + { + skip++; + } + } + + return (skip); +} + + +/******************************************************************************* +* Function Name: FillChecksum +****************************************************************************//** +* +* Performs calculation of the checksum on each row in the Em_EEPROM and fills +* the Em_EEPROM headers checksum field with the calculated checksums. +* +* \param context +* The pointer to the EEPROM context structure. +* +* \return +* error / status code. See \ref cy_en_em_eeprom_status_t. +* +* \theory +* In case if redundant copy option is used the Em_EEPROM would return bad +* checksum while trying to read the EEPROM rows which were not yet written by +* the user. E.g. any read after device reprogramming without previous Write() +* operation to the EEPROM would fail. This would happen because the Em_EEPROM +* headers checksum field values (which is zero at the moment) would not be +* equal to the actual data checksum. This function allows to avoid read failure +* after device reprogramming. +* +* \note +* This function uses a buffer of the flash row size to perform read +* operation. For the size of the row refer to the specific PSoC device +* datasheet. +* +*******************************************************************************/ +static cy_en_em_eeprom_status_t FillChecksum(cy_stc_eeprom_context_t * context) +{ + uint32 i; + uint32 rdAddr; + uint32 writeRamBuffer[CY_EM_EEPROM_FLASH_SIZEOF_ROW / CY_EM_EEPROM_U32_DIV]; + uint32 wrAddr = context->lastWrRowAddr; + uint32 tmpRowAddr; + /* Get the sequence number (number of writes) */ + uint32 seqNum = CY_EM_EEPROM_GET_SEQ_NUM(wrAddr); + cy_en_em_eeprom_status_t ret = CY_EM_EEPROM_BAD_PARAM; + + for(i = 0u; i < (context->numberOfRows * context->wearLevelingFactor); i++) + { + /* Copy the EEPROM row from Flash to RAM */ + (void)memcpy((void *)&writeRamBuffer[0u], (void *)(wrAddr), CY_EM_EEPROM_FLASH_SIZEOF_ROW); + + /* Increment the sequence number */ + seqNum++; + writeRamBuffer[CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32] = seqNum; + + /* Calculate and fill the checksum to the Em_EEPROM header */ + writeRamBuffer[CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32] = (uint32) + CalcChecksum((uint8 *) &writeRamBuffer[CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32], + CY_EM_EEPROM_EEPROM_DATA_LEN); + + /* Write the data to the specified flash row */ + ret = WriteRow(wrAddr, writeRamBuffer, context); + + /* Update the row address to point to the relevant row in the redundant + * EEPROM's copy. + */ + tmpRowAddr = (wrAddr - context->userFlashStartAddr) + context->wlEndAddr; + + /* Write the data to the specified flash row */ + ret = WriteRow(tmpRowAddr, writeRamBuffer, context); + + /* Get the address of the next row to be written. + * "rdAddr" is not used in this function but provided to prevent NULL + * pointer exception in GetNextRowToWrite(). + */ + GetNextRowToWrite(seqNum, &wrAddr, &rdAddr, context); + } + + return(ret); +} + +/** \endcond */ + +#if defined(__cplusplus) +} +#endif + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h new file mode 100644 index 0000000..4aef67b --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cy_em_eeprom.h @@ -0,0 +1,556 @@ +/******************************************************************************* +* \file cy_em_eeprom.h +* \version 2.0 +* +* \brief +* This file provides the function prototypes and constants for the Emulated +* EEPROM middleware library. +* +******************************************************************************** +* Copyright 2017, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +/** + * \mainpage Cypress Em_EEPROM Middleware Library + * + * The Emulated EEPROM provides an API that allows creating an emulated + * EEPROM in flash that has the ability to do wear leveling and restore + * corrupted data from a redundant copy. The Emulated EEPROM library is designed + * to be used with the Em_EEPROM component. + * + * The Cy_Em_EEPROM API is described in the following sections: + * - \ref group_em_eeprom_macros + * - \ref group_em_eeprom_data_structures + * - \ref group_em_eeprom_enums + * - \ref group_em_eeprom_functions + * + * Features: + * * EEPROM-Like Non-Volatile Storage + * * Easy to use Read and Write API + * * Optional Wear Leveling + * * Optional Redundant Data storage + * + * \section group_em_eeprom_configuration Configuration Considerations + * + * The Em_EEPROM operates on the top of the flash driver. The flash driver has + * some prerequisites for proper operation. Refer to the "Flash System + * Routine (Flash)" section of the PDL API Reference Manual. + * + * Initializing Emulated EEPROM in User flash + * + * To initialize an Emulated EEPROM in the User flash, the EEPROM storage should + * be declared by the user. For the proper operation, the EEPROM storage should + * be aligned to the size of the flash row. An example of the EEPROM storage + * declaration is below (applicable for GCC and MDK compilers): + * + * CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * Note that the name "emEeprom" is shown for reference. Any other name can be + * used instead. Also, note that the Em_EEPROM_PHYSICAL_SIZE constant is + * generated by the PSoC Creator Em_EEPROM component and so it is instance name + * dependent and its prefix should be changed when the name of the component + * changes. If the The Cy_Em_EEPROM middleware library is used without the + * Em_EEPROM component, the user has to provide a proper size for the EEPROM + * storage instead of Em_EEPROM_PHYSICAL_SIZE. The size of the EEPROM storage + * can be calculated using the following equation: + * + * Physical size = EEPROM data size * 2 * wear leveling * (1 + redundant copy) + * + * where, + * "EEPROM data size" - the size of data the user wants to store in the + * EEPROM. The data size must divide evenly to the half of the flash row size. + * "wear leveling" - the wear leveling factor (1-10). + * "redundant copy" - "zero" if a redundant copy is not used, and "one" + * otherwise. + * + * The start address of the storage should be filled to the Emulated EEPROM + * configuration structure and then passed to the Cy_Em_EEPROM_Init(). + * If the Em_EEPROM component is used, the config (Em_EEPROM_config) and + * context structures (Em_EEPROM_context) are defined by the component, so the + * user may just use that structures otherwise both of the structures need to + * be provided by the user. Note that if the "Config Data in Flash" + * option is selected in the component, then the configuration structure should + * be copied to RAM to allow EEPROM storage start address update. The following + * code demonstrates utilization of "Em_EEPROM_config" and "Em_EEPROM_context" + * Em_EEPROM component structures for Cy_Em_EEPROM middleware library + * initialization: + * + * cy_en_em_eeprom_status_t retValue; + * cy_stc_eeprom_config_t config; + * + * memcpy((void *)&config, + (void *)&Em_EEPROM_config, + sizeof(cy_stc_eeprom_config_t)); + * config.userFlashStartAddr = (uint32)emEeprom; + * retValue = Cy_Em_EEPROM_Init(&config, &Em_EEPROM_context); + * + * Initializing EEPROM in Emulated EEPROM flash area + * + * Initializing of the EEPROM storage in the Emulated EEPROM flash area is + * identical to initializing of the EEPROM storage in the User flash with one + * difference. The location of the Emulated EEPROM storage should be specified + * somewhere in the EmulatedEEPROM flash area. If the Em_EEPROM component is + * utilized in the project, then the respective storage + * (Em_EEPROM_em_EepromStorage[]) is automatically declared by the component + * if the "Use Emulated EEPROM" option is set to "Yes". The user just needs to + * fill the start address of the storage to the config structure. If the + * Em_EEPROM component is not used, the user needs to declare the storage + * in the Emulated EEPROM flash area. An example of such declaration is + * following (applicable for GCC and MDK compilers): + * + * CY_SECTION(".cy_em_eeprom") CY_ALIGN(CY_EM_EEPROM_FLASH_SIZEOF_ROW) + * const uint8_t emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * The same declaration for the IAR compiler: + * + * #pragma location = ".cy_em_eeprom" + * #pragma data_alignment = CY_EM_EEPROM_FLASH_SIZEOF_ROW + * const uint8 emEeprom[Em_EEPROM_PHYSICAL_SIZE] = {0u}; + * + * where, + * Em_EEPROM_PHYSICAL_SIZE - is a constant that is generated by the Em_EEPROM + * component when the component is utilized in the project or it should be + * provided by the user. The equation for the calculation of the constant is + * shown above. + * + * Note that the size of the Emulated EEPROM flash area is limited. Refer to the + * specific device datasheet for the value of the available EEPROM Emulation + * area. + * + * \section group_em_eeprom_more_information More Information + * See the Em_EEPROM Component datasheet. + * + * + * \section group_em_eeprom_MISRA MISRA-C Compliance + * + * The Cy_Em_EEPROM library has the following specific deviations: + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + * + *
MISRA RuleRule Class (Required/Advisory)Rule DescriptionDescription of Deviation(s)
11.4AThe cast should not be performed between a pointer to the object type + * and a different pointer to the object type.The cast from the object type and a different pointer to the object + * was used intentionally because of the performance reasons.
14.2RAll non-null statements shall either have at least one side-effect, + * however executed, or cause control flow to change.To maintain common codebase, some variables, unused for a specific + * device, are casted to void to prevent generation of an unused variable + * compiler warning.
16.7AThe object addressed by the pointer parameter is not modified and so + * the pointer could be of type 'pointer to const'.The warning is generated because of the pointer dereferencing to + * address which makes the MISRA checker think the data is not + * modified.
17.4RThe array indexing shall be the only allowed form of pointer + * arithmetic.The pointer arithmetic used in several places on the Cy_Em_EEPROM + * implementation is safe and preferred because it increases the code + * flexibility.
19.7AA function shall be used in preference to a function-like macro.Macro is used because of performance reasons.
+ * + * \section group_em_eeprom_changelog Changelog + * + * + * + * + * + * + * + *
VersionChangesReason for Change
1.0Initial Version
+ * + * \defgroup group_em_eeprom_macros Macros + * \brief + * This section describes the Emulated EEPROM Macros. + * + * \defgroup group_em_eeprom_functions Functions + * \brief + * This section describes the Emulated EEPROM Function Prototypes. + * + * \defgroup group_em_eeprom_data_structures Data Structures + * \brief + * Describes the data structures defined by the Emulated EEPROM. + * + * \defgroup group_em_eeprom_enums Enumerated types + * \brief + * Describes the enumeration types defined by the Emulated EEPROM. + * + */ + + +#if !defined(CY_EM_EEPROM_H) +#define CY_EM_EEPROM_H + +#include "cytypes.h" +#include +#if (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + #include + #include "syslib/cy_syslib.h" + #include "flash/cy_flash.h" +#else + #include "CyFlash.h" + #include +#endif /* (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) */ + +/* The C binding of definitions if building with the C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ +#define CY_PSOC6 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC6) + + +/*************************************** +* Data Structure definitions +***************************************/ +/** +* \addtogroup group_em_eeprom_data_structures +* \{ +*/ + +/** EEPROM configuration structure */ +typedef struct +{ + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_config_t; + +/** \} group_em_eeprom_data_structures */ + +/** The EEPROM context data structure. It is used to store the specific +* EEPROM context data. +*/ +typedef struct +{ + /** The pointer to the end address of EEPROM including wear leveling overhead + * and excluding redundant copy overhead. + */ + uint32 wlEndAddr; + + /** The number of flash rows allocated for the EEPROM excluding the number of + * rows allocated for wear leveling and redundant copy overhead. + */ + uint32 numberOfRows; + + /** The address of the last written EEPROM row */ + uint32 lastWrRowAddr; + + /** The number of bytes to store in EEPROM */ + uint32 eepromSize; + + /** The amount of wear leveling from 1 to 10. 1 means no wear leveling + * is used. + */ + uint32 wearLevelingFactor; + + /** If not zero, a redundant copy of the Em_EEPROM is included. */ + uint8 redundantCopy; + + /** If not zero, a blocking write to flash is used. Otherwise non-blocking + * write is used. This parameter is used only for PSoC 6. + */ + uint8 blockingWrite; + + /** The start address for the EEPROM memory in the user's flash. */ + uint32 userFlashStartAddr; +} cy_stc_eeprom_context_t; + +#if (CY_PSOC6) + + #define CY_EM_EEPROM_ID (CY_PDL_DRV_ID(0x1BuL)) /**< Em_EEPROM PDL ID */ + /** + * \addtogroup group_em_eeprom_enums + * \{ + * Specifies return values meaning. + */ + /** A prefix for EEPROM function error return-values */ + #define CY_EM_EEPROM_ID_ERROR (uint32_t)(CY_EM_EEPROM_ID | CY_PDL_STATUS_ERROR) + +#else + + /** A prefix for EEPROM function status codes. For non-PSoC6 devices, + * prefix is zero. + */ + #define CY_EM_EEPROM_ID_ERROR (0uL) + +#endif /* (CY_PSOC6) */ + + +/*************************************** +* Enumerated Types and Parameters +***************************************/ + +/** EEPROM return enumeration type */ +typedef enum +{ + CY_EM_EEPROM_SUCCESS = 0x00uL, /**< The function executed successfully */ + CY_EM_EEPROM_BAD_PARAM = (CY_EM_EEPROM_ID_ERROR + 1uL), /**< The input parameter is invalid */ + CY_EM_EEPROM_BAD_CHECKSUM = (CY_EM_EEPROM_ID_ERROR + 2uL), /**< The data in EEPROM is corrupted */ + CY_EM_EEPROM_BAD_DATA = (CY_EM_EEPROM_ID_ERROR + 3uL), /**< Failed to place the EEPROM in flash */ + CY_EM_EEPROM_WRITE_FAIL = (CY_EM_EEPROM_ID_ERROR + 4uL) /**< Write to EEPROM failed */ +} cy_en_em_eeprom_status_t; + +/** \} group_em_eeprom_enums */ + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_em_eeprom_functions +* \{ +*/ +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Init(cy_stc_eeprom_config_t* config, cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Read(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Write(uint32 addr, + void * eepromData, + uint32 size, + cy_stc_eeprom_context_t * context); +cy_en_em_eeprom_status_t Cy_Em_EEPROM_Erase(cy_stc_eeprom_context_t * context); +uint32 Cy_Em_EEPROM_NumWrites(cy_stc_eeprom_context_t * context); +/** \} group_em_eeprom_functions */ + + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ +/** Library major version */ +#define CY_EM_EEPROM_VERSION_MAJOR (2) + +/** Library minor version */ +#define CY_EM_EEPROM_VERSION_MINOR (0) + +/** Defines the maximum data length that can be stored in one flash row */ +#define CY_EM_EEPROM_EEPROM_DATA_LEN (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) + +/** \} group_em_eeprom_macros */ + + +/*************************************** +* Macro definitions +***************************************/ +/** \cond INTERNAL */ + +/* Defines the size of flash row */ +#define CY_EM_EEPROM_FLASH_SIZEOF_ROW (CY_FLASH_SIZEOF_ROW) + +/* Device specific flash constants */ +#if (!CY_PSOC6) + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CYDEV_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CYDEV_FLASH_SIZE) + #define CY_EM_EEPROM_ROWS_IN_ARRAY (CY_FLASH_SIZEOF_ARRAY / CY_EM_EEPROM_FLASH_SIZEOF_ROW) + #if (CY_PSOC3) + #define CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX (0xff0000uL) + #define CY_EM_EEPROM_CODE_ADDR_END \ + (CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX + (CY_EM_EEPROM_FLASH_SIZE - 1u)) + #define CY_EM_EEPROM_CODE_ADDR_MASK (0xffffu) + /* Checks if the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_CODE_MEM_CLASS_PREFIX) && \ + ((endAddr) <= CY_EM_EEPROM_CODE_ADDR_END)) + #else + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) + #endif /* (CY_PSOC3) */ +#else + #define CY_EM_EEPROM_FLASH_BASE_ADDR (CY_FLASH_BASE) + #define CY_EM_EEPROM_FLASH_SIZE (CY_FLASH_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_BASE_ADDR (CY_EM_EEPROM_BASE) + #define CY_EM_EEPROM_EM_EEPROM_SIZE (CY_EM_EEPROM_SIZE) + #define CY_EM_EEPROM_EM_EEPROM_END_ADDR (CY_EM_EEPROM_EM_EEPROM_BASE_ADDR + CY_EM_EEPROM_EM_EEPROM_SIZE) + /* Checks is the EEPROM is in flash range */ + #define CY_EM_EEPROM_IS_IN_FLASH_RANGE(startAddr, endAddr) \ + (((((startAddr) > CY_EM_EEPROM_FLASH_BASE_ADDR) && ((endAddr) <= CY_EM_EEPROM_FLASH_END_ADDR)) || \ + (((startAddr) >= CY_EM_EEPROM_EM_EEPROM_BASE_ADDR) && \ + ((endAddr) <= CY_EM_EEPROM_EM_EEPROM_END_ADDR)))) +#endif /* (!CY_PSOC6) */ + +#define CY_EM_EEPROM_FLASH_END_ADDR (CY_EM_EEPROM_FLASH_BASE_ADDR + CY_EM_EEPROM_FLASH_SIZE) + +/* Defines the length of EEPROM data that can be stored in Em_EEPROM header */ +#define CY_EM_EEPROM_HEADER_DATA_LEN ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) - 16u) + +#define CY_EM_EEPROM_ADDR_IN_RANGE (1u) + +/* Return CY_EM_EEPROM_ADDR_IN_RANGE if addr exceeded the upper range of +* EEPROM. The wear leveling overhead is included in the range but redundant copy +* is excluded. +*/ +#define CY_EM_EEPROM_IS_ADDR_EXCEED_RANGE(addr, endEepromAddr) \ + (((addr) >= (endEepromAddr)) ? (0u) : (CY_EM_EEPROM_ADDR_IN_RANGE)) + +/* Check to see if the specified address is present in the EEPROM */ +#define CY_EM_EEPROM_IS_ADDR_IN_RANGE(addr, startEepromAddr, endEepromAddr) \ + (((addr) > (startEepromAddr)) ? \ + (((addr) < (endEepromAddr)) ? (CY_EM_EEPROM_ADDR_IN_RANGE) : (0u)) : (0u)) + +/* Check if the EEPROM address locations from startAddr1 to endAddr1 +* are crossed with EEPROM address locations from startAddr2 to endAddr2. +*/ +#define CY_EM_EEPROM_IS_ADDRESES_CROSSING(startAddr1, endAddr1 , startAddr2, endAddr2) \ + (((startAddr1) > (startAddr2)) ? (((startAddr1) >= (endAddr2)) ? (0u) : (1u) ) : \ + (((startAddr2) >= (endAddr1)) ? (0u) : (1u))) + +/* Return the pointer to the start of the redundant copy of the EEPROM */ +#define CY_EM_EEPROM_GET_REDNT_COPY_ADDR_BASE(numRows, wearLeveling, eepromStartAddr) \ + ((((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) * (wearLeveling)) + (eepromStartAddr)) + +/* Return the number of the row in EM_EEPROM which contains an address defined by +* rowAddr. + */ +#define CY_EM_EEPROM_GET_ACT_ROW_NUM_FROM_ADDR(rowAddr, maxRows, eepromStartAddr) \ + ((((rowAddr) - (eepromStartAddr)) / CY_EM_EEPROM_FLASH_SIZEOF_ROW) % (maxRows)) + + +/** Returns the size allocated for the EEPROM excluding wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_EEPROM_SIZE(numRows) ((numRows) * CY_EM_EEPROM_FLASH_SIZEOF_ROW) + +/* Check if the given address belongs to the EEPROM address of the row +* specified by rowNum. +*/ +#define CY_EM_EEPROM_IS_ADDR_IN_ROW_RANGE(addr, rowNum) \ + (((addr) < ((rowNum) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u))) ? (0u) : \ + (((addr) > ((((rowNum) + 1u) * (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u)) - 1u)) ? \ + (0u) : (1u))) + +/* CRC-8 constants */ +#define CY_EM_EEPROM_CRC8_POLYNOM ((uint8)(0x31u)) +#define CY_EM_EEPROM_CRC8_POLYNOM_LEN (8u) +#define CY_EM_EEPROM_CRC8_SEED (0xFFu) +#define CY_EM_EEPROM_CRC8_XOR_VAL ((uint8) (0x80u)) + +#define CY_EM_EEPROM_CALCULATE_CRC8(crc) \ + ((CY_EM_EEPROM_CRC8_XOR_VAL == ((crc) & CY_EM_EEPROM_CRC8_XOR_VAL)) ? \ + ((uint8)(((uint8)((uint8)((crc) << 1u))) ^ CY_EM_EEPROM_CRC8_POLYNOM)) : ((uint8)((crc) << 1u))) + +#define CY_EM_EEPROM_GET_SEQ_NUM(addr) (*(uint32*)(addr)) + +/** \endcond */ + +/** +* \addtogroup group_em_eeprom_macros +* \{ +*/ + +/** Calculate the number of flash rows required to create an Em_EEPROM of +* dataSize. +*/ +#define CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) \ + (((dataSize) / (CY_EM_EEPROM_EEPROM_DATA_LEN)) + \ + ((((dataSize) % (CY_EM_EEPROM_EEPROM_DATA_LEN)) != 0u) ? 1U : 0U)) + +/** Returns the size of flash allocated for EEPROM including wear leveling and +* redundant copy overhead. +*/ +#define CY_EM_EEPROM_GET_PHYSICAL_SIZE(dataSize, wearLeveling, redundantCopy) \ + (((CY_EM_EEPROM_GET_NUM_ROWS_IN_EEPROM(dataSize) * \ + CY_EM_EEPROM_FLASH_SIZEOF_ROW) * \ + (wearLeveling)) * (1uL + (redundantCopy))) + +/** \} group_em_eeprom_macros */ + + +/****************************************************************************** +* Local definitions +*******************************************************************************/ +/** \cond INTERNAL */ + +/* Offsets for 32-bit RAM buffer addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 ((CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) / 4u) +#define CY_EM_EEPROM_HEADER_SEQ_NUM_OFFSET_U32 (0u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET_U32 (1u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET_U32 (2u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET_U32 (3u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET_U32 (CY_EM_EEPROM_EEPROM_DATA_OFFSET_U32 - 1u) + +/* The same offsets as above used for direct memory addressing */ +#define CY_EM_EEPROM_EEPROM_DATA_OFFSET (CY_EM_EEPROM_FLASH_SIZEOF_ROW / 2u) +#define CY_EM_EEPROM_HEADER_ADDR_OFFSET (4u) +#define CY_EM_EEPROM_HEADER_LEN_OFFSET (8u) +#define CY_EM_EEPROM_HEADER_DATA_OFFSET (12u) +#define CY_EM_EEPROM_HEADER_CHECKSUM_OFFSET (CY_EM_EEPROM_EEPROM_DATA_OFFSET - 4u) + +#define CY_EM_EEPROM_U32_DIV (4u) + +/* Maximum wear leveling value */ +#define CY_EM_EEPROM_MAX_WEAR_LEVELING_FACTOR (10u) + +/* Maximum allowed flash row write/erase operation duration */ +#define CY_EM_EEPROM_MAX_WRITE_DURATION_MS (50u) + +/** \endcond */ + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* CY_EM_EEPROM_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareexport.ld new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.ld new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cycodeshareimport.scat new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h new file mode 100644 index 0000000..59d3e2c --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* File Name: cydevice.h +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_H) +#define CYDEVICE_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYDEV_FLASH_DATA_MBASE 0x00000000u +#define CYDEV_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000u +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000u +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000u +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000u +#define CYDEV_SRAM_CODE_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA_MBASE 0x20000000u +#define CYDEV_SRAM_DATA_MSIZE 0x00004000u +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000u +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000u +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000u +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000u +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000u +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000u +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000u +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000u +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000u +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000u +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000u +#define CYDEV_DMA_SRAM_MBASE 0x2000f000u +#define CYDEV_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYDEV_CLKDIST_CR 0x40004000u +#define CYDEV_CLKDIST_LD 0x40004001u +#define CYDEV_CLKDIST_WRK0 0x40004002u +#define CYDEV_CLKDIST_WRK1 0x40004003u +#define CYDEV_CLKDIST_MSTR0 0x40004004u +#define CYDEV_CLKDIST_MSTR1 0x40004005u +#define CYDEV_CLKDIST_BCFG0 0x40004006u +#define CYDEV_CLKDIST_BCFG1 0x40004007u +#define CYDEV_CLKDIST_BCFG2 0x40004008u +#define CYDEV_CLKDIST_UCFG 0x40004009u +#define CYDEV_CLKDIST_DLY0 0x4000400au +#define CYDEV_CLKDIST_DLY1 0x4000400bu +#define CYDEV_CLKDIST_DMASK 0x40004010u +#define CYDEV_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYDEV_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210u +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220u +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221u +#define CYDEV_FASTCLK_PLL_P 0x40004222u +#define CYDEV_FASTCLK_PLL_Q 0x40004223u +#define CYDEV_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300u +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYDEV_SLOWCLK_X32_CR 0x40004308u +#define CYDEV_SLOWCLK_X32_CFG 0x40004309u +#define CYDEV_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYDEV_BOOST_CR0 0x40004320u +#define CYDEV_BOOST_CR1 0x40004321u +#define CYDEV_BOOST_CR2 0x40004322u +#define CYDEV_BOOST_CR3 0x40004323u +#define CYDEV_BOOST_SR 0x40004324u +#define CYDEV_BOOST_CR4 0x40004325u +#define CYDEV_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYDEV_PWRSYS_CR0 0x40004330u +#define CYDEV_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYDEV_PM_TW_CFG0 0x40004380u +#define CYDEV_PM_TW_CFG1 0x40004381u +#define CYDEV_PM_TW_CFG2 0x40004382u +#define CYDEV_PM_WDT_CFG 0x40004383u +#define CYDEV_PM_WDT_CR 0x40004384u +#define CYDEV_PM_INT_SR 0x40004390u +#define CYDEV_PM_MODE_CFG0 0x40004391u +#define CYDEV_PM_MODE_CFG1 0x40004392u +#define CYDEV_PM_MODE_CSR 0x40004393u +#define CYDEV_PM_USB_CR0 0x40004394u +#define CYDEV_PM_WAKEUP_CFG0 0x40004398u +#define CYDEV_PM_WAKEUP_CFG1 0x40004399u +#define CYDEV_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYDEV_PM_ACT_CFG0 0x400043a0u +#define CYDEV_PM_ACT_CFG1 0x400043a1u +#define CYDEV_PM_ACT_CFG2 0x400043a2u +#define CYDEV_PM_ACT_CFG3 0x400043a3u +#define CYDEV_PM_ACT_CFG4 0x400043a4u +#define CYDEV_PM_ACT_CFG5 0x400043a5u +#define CYDEV_PM_ACT_CFG6 0x400043a6u +#define CYDEV_PM_ACT_CFG7 0x400043a7u +#define CYDEV_PM_ACT_CFG8 0x400043a8u +#define CYDEV_PM_ACT_CFG9 0x400043a9u +#define CYDEV_PM_ACT_CFG10 0x400043aau +#define CYDEV_PM_ACT_CFG11 0x400043abu +#define CYDEV_PM_ACT_CFG12 0x400043acu +#define CYDEV_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYDEV_PM_STBY_CFG0 0x400043b0u +#define CYDEV_PM_STBY_CFG1 0x400043b1u +#define CYDEV_PM_STBY_CFG2 0x400043b2u +#define CYDEV_PM_STBY_CFG3 0x400043b3u +#define CYDEV_PM_STBY_CFG4 0x400043b4u +#define CYDEV_PM_STBY_CFG5 0x400043b5u +#define CYDEV_PM_STBY_CFG6 0x400043b6u +#define CYDEV_PM_STBY_CFG7 0x400043b7u +#define CYDEV_PM_STBY_CFG8 0x400043b8u +#define CYDEV_PM_STBY_CFG9 0x400043b9u +#define CYDEV_PM_STBY_CFG10 0x400043bau +#define CYDEV_PM_STBY_CFG11 0x400043bbu +#define CYDEV_PM_STBY_CFG12 0x400043bcu +#define CYDEV_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYDEV_PM_AVAIL_CR0 0x400043c0u +#define CYDEV_PM_AVAIL_CR1 0x400043c1u +#define CYDEV_PM_AVAIL_CR2 0x400043c2u +#define CYDEV_PM_AVAIL_CR3 0x400043c3u +#define CYDEV_PM_AVAIL_CR4 0x400043c4u +#define CYDEV_PM_AVAIL_CR5 0x400043c5u +#define CYDEV_PM_AVAIL_CR6 0x400043c6u +#define CYDEV_PM_AVAIL_SR0 0x400043d0u +#define CYDEV_PM_AVAIL_SR1 0x400043d1u +#define CYDEV_PM_AVAIL_SR2 0x400043d2u +#define CYDEV_PM_AVAIL_SR3 0x400043d3u +#define CYDEV_PM_AVAIL_SR4 0x400043d4u +#define CYDEV_PM_AVAIL_SR5 0x400043d5u +#define CYDEV_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506u +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509u +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450au +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450bu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450cu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450du +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450eu +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516u +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519u +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451au +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451bu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451cu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451du +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451eu +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526u +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529u +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452au +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452bu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452cu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452du +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452eu +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536u +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566u +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579u +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457au +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457bu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457cu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457du +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457eu +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681u +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682u +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683u +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686u +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687u +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689u +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYDEV_MFGCFG_ILO_TR0 0x40004690u +#define CYDEV_MFGCFG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYDEV_MFGCFG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0u +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1u +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2u +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3u +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8u +#define CYDEV_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYDEV_RESET_IPOR_CR0 0x400046f0u +#define CYDEV_RESET_IPOR_CR1 0x400046f1u +#define CYDEV_RESET_IPOR_CR2 0x400046f2u +#define CYDEV_RESET_IPOR_CR3 0x400046f3u +#define CYDEV_RESET_CR0 0x400046f4u +#define CYDEV_RESET_CR1 0x400046f5u +#define CYDEV_RESET_CR2 0x400046f6u +#define CYDEV_RESET_CR3 0x400046f7u +#define CYDEV_RESET_CR4 0x400046f8u +#define CYDEV_RESET_CR5 0x400046f9u +#define CYDEV_RESET_SR0 0x400046fau +#define CYDEV_RESET_SR1 0x400046fbu +#define CYDEV_RESET_SR2 0x400046fcu +#define CYDEV_RESET_SR3 0x400046fdu +#define CYDEV_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYDEV_SPC_FM_EE_CR 0x40004700u +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYDEV_SPC_EE_SCR 0x40004702u +#define CYDEV_SPC_EE_ERR 0x40004703u +#define CYDEV_SPC_CPU_DATA 0x40004720u +#define CYDEV_SPC_DMA_DATA 0x40004721u +#define CYDEV_SPC_SR 0x40004722u +#define CYDEV_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYDEV_CACHE_CC_CTL 0x40004800u +#define CYDEV_CACHE_ECC_CORR 0x40004880u +#define CYDEV_CACHE_ECC_ERR 0x40004888u +#define CYDEV_CACHE_FLASH_ERR 0x40004890u +#define CYDEV_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYDEV_I2C_XCFG 0x400049c8u +#define CYDEV_I2C_ADR 0x400049cau +#define CYDEV_I2C_CFG 0x400049d6u +#define CYDEV_I2C_CSR 0x400049d7u +#define CYDEV_I2C_D 0x400049d8u +#define CYDEV_I2C_MCSR 0x400049d9u +#define CYDEV_I2C_CLK_DIV1 0x400049dbu +#define CYDEV_I2C_CLK_DIV2 0x400049dcu +#define CYDEV_I2C_TMOUT_CSR 0x400049ddu +#define CYDEV_I2C_TMOUT_SR 0x400049deu +#define CYDEV_I2C_TMOUT_CFG0 0x400049dfu +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYDEV_DEC_CR 0x40004e00u +#define CYDEV_DEC_SR 0x40004e01u +#define CYDEV_DEC_SHIFT1 0x40004e02u +#define CYDEV_DEC_SHIFT2 0x40004e03u +#define CYDEV_DEC_DR2 0x40004e04u +#define CYDEV_DEC_DR2H 0x40004e05u +#define CYDEV_DEC_DR1 0x40004e06u +#define CYDEV_DEC_OCOR 0x40004e08u +#define CYDEV_DEC_OCORM 0x40004e09u +#define CYDEV_DEC_OCORH 0x40004e0au +#define CYDEV_DEC_GCOR 0x40004e0cu +#define CYDEV_DEC_GCORH 0x40004e0du +#define CYDEV_DEC_GVAL 0x40004e0eu +#define CYDEV_DEC_OUTSAMP 0x40004e10u +#define CYDEV_DEC_OUTSAMPM 0x40004e11u +#define CYDEV_DEC_OUTSAMPH 0x40004e12u +#define CYDEV_DEC_OUTSAMPS 0x40004e13u +#define CYDEV_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYDEV_TMR0_CFG0 0x40004f00u +#define CYDEV_TMR0_CFG1 0x40004f01u +#define CYDEV_TMR0_CFG2 0x40004f02u +#define CYDEV_TMR0_SR0 0x40004f03u +#define CYDEV_TMR0_PER0 0x40004f04u +#define CYDEV_TMR0_PER1 0x40004f05u +#define CYDEV_TMR0_CNT_CMP0 0x40004f06u +#define CYDEV_TMR0_CNT_CMP1 0x40004f07u +#define CYDEV_TMR0_CAP0 0x40004f08u +#define CYDEV_TMR0_CAP1 0x40004f09u +#define CYDEV_TMR0_RT0 0x40004f0au +#define CYDEV_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYDEV_TMR1_CFG0 0x40004f0cu +#define CYDEV_TMR1_CFG1 0x40004f0du +#define CYDEV_TMR1_CFG2 0x40004f0eu +#define CYDEV_TMR1_SR0 0x40004f0fu +#define CYDEV_TMR1_PER0 0x40004f10u +#define CYDEV_TMR1_PER1 0x40004f11u +#define CYDEV_TMR1_CNT_CMP0 0x40004f12u +#define CYDEV_TMR1_CNT_CMP1 0x40004f13u +#define CYDEV_TMR1_CAP0 0x40004f14u +#define CYDEV_TMR1_CAP1 0x40004f15u +#define CYDEV_TMR1_RT0 0x40004f16u +#define CYDEV_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYDEV_TMR2_CFG0 0x40004f18u +#define CYDEV_TMR2_CFG1 0x40004f19u +#define CYDEV_TMR2_CFG2 0x40004f1au +#define CYDEV_TMR2_SR0 0x40004f1bu +#define CYDEV_TMR2_PER0 0x40004f1cu +#define CYDEV_TMR2_PER1 0x40004f1du +#define CYDEV_TMR2_CNT_CMP0 0x40004f1eu +#define CYDEV_TMR2_CNT_CMP1 0x40004f1fu +#define CYDEV_TMR2_CAP0 0x40004f20u +#define CYDEV_TMR2_CAP1 0x40004f21u +#define CYDEV_TMR2_RT0 0x40004f22u +#define CYDEV_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYDEV_TMR3_CFG0 0x40004f24u +#define CYDEV_TMR3_CFG1 0x40004f25u +#define CYDEV_TMR3_CFG2 0x40004f26u +#define CYDEV_TMR3_SR0 0x40004f27u +#define CYDEV_TMR3_PER0 0x40004f28u +#define CYDEV_TMR3_PER1 0x40004f29u +#define CYDEV_TMR3_CNT_CMP0 0x40004f2au +#define CYDEV_TMR3_CNT_CMP1 0x40004f2bu +#define CYDEV_TMR3_CAP0 0x40004f2cu +#define CYDEV_TMR3_CAP1 0x40004f2du +#define CYDEV_TMR3_RT0 0x40004f2eu +#define CYDEV_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT0_PC0 0x40005000u +#define CYDEV_IO_PC_PRT0_PC1 0x40005001u +#define CYDEV_IO_PC_PRT0_PC2 0x40005002u +#define CYDEV_IO_PC_PRT0_PC3 0x40005003u +#define CYDEV_IO_PC_PRT0_PC4 0x40005004u +#define CYDEV_IO_PC_PRT0_PC5 0x40005005u +#define CYDEV_IO_PC_PRT0_PC6 0x40005006u +#define CYDEV_IO_PC_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT1_PC0 0x40005008u +#define CYDEV_IO_PC_PRT1_PC1 0x40005009u +#define CYDEV_IO_PC_PRT1_PC2 0x4000500au +#define CYDEV_IO_PC_PRT1_PC3 0x4000500bu +#define CYDEV_IO_PC_PRT1_PC4 0x4000500cu +#define CYDEV_IO_PC_PRT1_PC5 0x4000500du +#define CYDEV_IO_PC_PRT1_PC6 0x4000500eu +#define CYDEV_IO_PC_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT2_PC0 0x40005010u +#define CYDEV_IO_PC_PRT2_PC1 0x40005011u +#define CYDEV_IO_PC_PRT2_PC2 0x40005012u +#define CYDEV_IO_PC_PRT2_PC3 0x40005013u +#define CYDEV_IO_PC_PRT2_PC4 0x40005014u +#define CYDEV_IO_PC_PRT2_PC5 0x40005015u +#define CYDEV_IO_PC_PRT2_PC6 0x40005016u +#define CYDEV_IO_PC_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT3_PC0 0x40005018u +#define CYDEV_IO_PC_PRT3_PC1 0x40005019u +#define CYDEV_IO_PC_PRT3_PC2 0x4000501au +#define CYDEV_IO_PC_PRT3_PC3 0x4000501bu +#define CYDEV_IO_PC_PRT3_PC4 0x4000501cu +#define CYDEV_IO_PC_PRT3_PC5 0x4000501du +#define CYDEV_IO_PC_PRT3_PC6 0x4000501eu +#define CYDEV_IO_PC_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT4_PC0 0x40005020u +#define CYDEV_IO_PC_PRT4_PC1 0x40005021u +#define CYDEV_IO_PC_PRT4_PC2 0x40005022u +#define CYDEV_IO_PC_PRT4_PC3 0x40005023u +#define CYDEV_IO_PC_PRT4_PC4 0x40005024u +#define CYDEV_IO_PC_PRT4_PC5 0x40005025u +#define CYDEV_IO_PC_PRT4_PC6 0x40005026u +#define CYDEV_IO_PC_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT5_PC0 0x40005028u +#define CYDEV_IO_PC_PRT5_PC1 0x40005029u +#define CYDEV_IO_PC_PRT5_PC2 0x4000502au +#define CYDEV_IO_PC_PRT5_PC3 0x4000502bu +#define CYDEV_IO_PC_PRT5_PC4 0x4000502cu +#define CYDEV_IO_PC_PRT5_PC5 0x4000502du +#define CYDEV_IO_PC_PRT5_PC6 0x4000502eu +#define CYDEV_IO_PC_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT6_PC0 0x40005030u +#define CYDEV_IO_PC_PRT6_PC1 0x40005031u +#define CYDEV_IO_PC_PRT6_PC2 0x40005032u +#define CYDEV_IO_PC_PRT6_PC3 0x40005033u +#define CYDEV_IO_PC_PRT6_PC4 0x40005034u +#define CYDEV_IO_PC_PRT6_PC5 0x40005035u +#define CYDEV_IO_PC_PRT6_PC6 0x40005036u +#define CYDEV_IO_PC_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYDEV_IO_PC_PRT12_PC0 0x40005060u +#define CYDEV_IO_PC_PRT12_PC1 0x40005061u +#define CYDEV_IO_PC_PRT12_PC2 0x40005062u +#define CYDEV_IO_PC_PRT12_PC3 0x40005063u +#define CYDEV_IO_PC_PRT12_PC4 0x40005064u +#define CYDEV_IO_PC_PRT12_PC5 0x40005065u +#define CYDEV_IO_PC_PRT12_PC6 0x40005066u +#define CYDEV_IO_PC_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYDEV_IO_PC_PRT15_PC0 0x40005078u +#define CYDEV_IO_PC_PRT15_PC1 0x40005079u +#define CYDEV_IO_PC_PRT15_PC2 0x4000507au +#define CYDEV_IO_PC_PRT15_PC3 0x4000507bu +#define CYDEV_IO_PC_PRT15_PC4 0x4000507cu +#define CYDEV_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT0_DR 0x40005100u +#define CYDEV_IO_PRT_PRT0_PS 0x40005101u +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102u +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103u +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104u +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105u +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106u +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107u +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108u +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109u +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510au +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510bu +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510cu +#define CYDEV_IO_PRT_PRT0_AG 0x4000510du +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510eu +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT1_DR 0x40005110u +#define CYDEV_IO_PRT_PRT1_PS 0x40005111u +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112u +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113u +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114u +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115u +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116u +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117u +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118u +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119u +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511au +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511bu +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511cu +#define CYDEV_IO_PRT_PRT1_AG 0x4000511du +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511eu +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT2_DR 0x40005120u +#define CYDEV_IO_PRT_PRT2_PS 0x40005121u +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122u +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123u +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124u +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125u +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126u +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127u +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128u +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129u +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512au +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512bu +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512cu +#define CYDEV_IO_PRT_PRT2_AG 0x4000512du +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512eu +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT3_DR 0x40005130u +#define CYDEV_IO_PRT_PRT3_PS 0x40005131u +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132u +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133u +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134u +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135u +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136u +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137u +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138u +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139u +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513au +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513bu +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513cu +#define CYDEV_IO_PRT_PRT3_AG 0x4000513du +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513eu +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT4_DR 0x40005140u +#define CYDEV_IO_PRT_PRT4_PS 0x40005141u +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142u +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143u +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144u +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145u +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146u +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147u +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148u +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149u +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514au +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514bu +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514cu +#define CYDEV_IO_PRT_PRT4_AG 0x4000514du +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514eu +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT5_DR 0x40005150u +#define CYDEV_IO_PRT_PRT5_PS 0x40005151u +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152u +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153u +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154u +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155u +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156u +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157u +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158u +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159u +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515au +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515bu +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515cu +#define CYDEV_IO_PRT_PRT5_AG 0x4000515du +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515eu +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT6_DR 0x40005160u +#define CYDEV_IO_PRT_PRT6_PS 0x40005161u +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162u +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163u +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164u +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165u +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166u +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167u +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168u +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169u +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516au +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516bu +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516cu +#define CYDEV_IO_PRT_PRT6_AG 0x4000516du +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516eu +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0u +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1u +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2u +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3u +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4u +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5u +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6u +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7u +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8u +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9u +#define CYDEV_IO_PRT_PRT12_PRT 0x400051cau +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cbu +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYDEV_IO_PRT_PRT12_AG 0x400051cdu +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ceu +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0u +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1u +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2u +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3u +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4u +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5u +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6u +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7u +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8u +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9u +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fau +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fbu +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fcu +#define CYDEV_IO_PRT_PRT15_AG 0x400051fdu +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051feu +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200u +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201u +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202u +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203u +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204u +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205u +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208u +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209u +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520au +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520bu +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520du +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210u +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211u +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212u +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213u +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214u +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215u +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218u +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219u +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521au +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521bu +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521du +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220u +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221u +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222u +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223u +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224u +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225u +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228u +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229u +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522au +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522bu +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522du +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230u +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231u +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232u +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233u +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234u +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235u +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260u +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261u +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262u +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263u +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264u +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278u +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279u +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527au +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527bu +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527du +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYDEV_EMIF_NO_UDB 0x40005400u +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401u +#define CYDEV_EMIF_MEM_DWN 0x40005402u +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403u +#define CYDEV_EMIF_CLOCK_EN 0x40005404u +#define CYDEV_EMIF_EM_TYPE 0x40005405u +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801u +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805u +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809u +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580du +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821u +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825u +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829u +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582du +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586du +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586eu +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881u +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882u +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883u +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884u +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885u +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886u +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887u +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888u +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889u +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588au +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588bu +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588cu +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588du +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588eu +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588fu +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890u +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891u +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892u +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893u +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894u +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895u +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896u +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897u +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898u +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899u +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589au +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589bu +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589cu +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589du +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589eu +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901u +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902u +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903u +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904u +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905u +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909u +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590au +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590bu +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590cu +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590du +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02u +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03u +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04u +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06u +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07u +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08u +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0au +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0bu +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12u +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13u +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14u +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16u +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17u +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18u +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1au +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1bu +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22u +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23u +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24u +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26u +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27u +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28u +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2au +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2bu +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32u +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33u +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34u +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36u +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37u +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38u +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3au +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3bu +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82u +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83u +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84u +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8au +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8bu +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8cu +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92u +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93u +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94u +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9au +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9bu +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9cu +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2u +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3u +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4u +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6u +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005acau +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acbu +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005accu +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005aceu +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2u +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3u +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4u +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6u +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005adau +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adbu +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adcu +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005adeu +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02u +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03u +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04u +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06u +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22u +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23u +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24u +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26u +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2au +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2bu +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2cu +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2eu +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51u +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52u +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53u +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5au +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5du +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5eu +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5fu +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60u +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91u +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92u +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93u +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99u +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9au +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9bu +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYDEV_USB_EP0_DR0 0x40006000u +#define CYDEV_USB_EP0_DR1 0x40006001u +#define CYDEV_USB_EP0_DR2 0x40006002u +#define CYDEV_USB_EP0_DR3 0x40006003u +#define CYDEV_USB_EP0_DR4 0x40006004u +#define CYDEV_USB_EP0_DR5 0x40006005u +#define CYDEV_USB_EP0_DR6 0x40006006u +#define CYDEV_USB_EP0_DR7 0x40006007u +#define CYDEV_USB_CR0 0x40006008u +#define CYDEV_USB_CR1 0x40006009u +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600au +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600cu +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600du +#define CYDEV_USB_SIE_EP1_CR0 0x4000600eu +#define CYDEV_USB_USBIO_CR0 0x40006010u +#define CYDEV_USB_USBIO_CR1 0x40006012u +#define CYDEV_USB_DYN_RECONFIG 0x40006014u +#define CYDEV_USB_SOF0 0x40006018u +#define CYDEV_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601cu +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601du +#define CYDEV_USB_SIE_EP2_CR0 0x4000601eu +#define CYDEV_USB_EP0_CR 0x40006028u +#define CYDEV_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602cu +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602du +#define CYDEV_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603cu +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603du +#define CYDEV_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604cu +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604du +#define CYDEV_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605cu +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605du +#define CYDEV_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606cu +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606du +#define CYDEV_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607cu +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607du +#define CYDEV_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP1_CFG 0x40006080u +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081u +#define CYDEV_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW1_WA 0x40006084u +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYDEV_USB_ARB_RW1_RA 0x40006086u +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYDEV_USB_ARB_RW1_DR 0x40006088u +#define CYDEV_USB_BUF_SIZE 0x4000608cu +#define CYDEV_USB_EP_ACTIVE 0x4000608eu +#define CYDEV_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP2_CFG 0x40006090u +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091u +#define CYDEV_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW2_WA 0x40006094u +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYDEV_USB_ARB_RW2_RA 0x40006096u +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYDEV_USB_ARB_RW2_DR 0x40006098u +#define CYDEV_USB_ARB_CFG 0x4000609cu +#define CYDEV_USB_USB_CLK_EN 0x4000609du +#define CYDEV_USB_ARB_INT_EN 0x4000609eu +#define CYDEV_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0u +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYDEV_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW3_WA 0x400060a4u +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYDEV_USB_ARB_RW3_RA 0x400060a6u +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYDEV_USB_ARB_RW3_DR 0x400060a8u +#define CYDEV_USB_CWA 0x400060acu +#define CYDEV_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0u +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYDEV_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW4_WA 0x400060b4u +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYDEV_USB_ARB_RW4_RA 0x400060b6u +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYDEV_USB_ARB_RW4_DR 0x400060b8u +#define CYDEV_USB_DMA_THRES 0x400060bcu +#define CYDEV_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0u +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYDEV_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW5_WA 0x400060c4u +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYDEV_USB_ARB_RW5_RA 0x400060c6u +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYDEV_USB_ARB_RW5_DR 0x400060c8u +#define CYDEV_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0u +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYDEV_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW6_WA 0x400060d4u +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYDEV_USB_ARB_RW6_RA 0x400060d6u +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYDEV_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0u +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYDEV_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW7_WA 0x400060e4u +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYDEV_USB_ARB_RW7_RA 0x400060e6u +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYDEV_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0u +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYDEV_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYDEV_USB_ARB_RW8_WA 0x400060f4u +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYDEV_USB_ARB_RW8_RA 0x400060f6u +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYDEV_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100u +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410u +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411u +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412u +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413u +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414u +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415u +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416u +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417u +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418u +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419u +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641au +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641du +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430u +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431u +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432u +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433u +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434u +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435u +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436u +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437u +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438u +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439u +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643au +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643du +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450u +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451u +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452u +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453u +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454u +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455u +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456u +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457u +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458u +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459u +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645au +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645du +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470u +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471u +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472u +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473u +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474u +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475u +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476u +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477u +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478u +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479u +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647au +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647du +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648au +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648du +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490u +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491u +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492u +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493u +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494u +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495u +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496u +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497u +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498u +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499u +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649au +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649bu +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649cu +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649du +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649eu +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649fu +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0u +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1u +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2u +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3u +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4u +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5u +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6u +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7u +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8u +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9u +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aau +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064abu +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064acu +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064adu +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064aeu +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514u +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515u +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516u +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517u +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518u +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519u +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651au +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534u +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535u +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536u +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537u +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538u +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539u +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653au +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554u +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555u +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556u +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557u +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558u +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559u +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655au +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574u +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575u +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576u +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577u +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578u +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579u +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657au +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658au +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594u +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595u +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596u +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597u +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598u +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599u +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659au +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659bu +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4u +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5u +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6u +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7u +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8u +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9u +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aau +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068cau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068ccu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ceu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068dau +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dcu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068deu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694eu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958u +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695au +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695cu +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006acau +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006accu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006aceu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4au +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4cu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4eu +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54u +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068acu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068aeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068bau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068cau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068ccu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ceu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068dau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068eau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ecu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068eeu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fau +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fcu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694cu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694eu +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958u +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695au +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aacu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aaeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006acau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006accu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006aceu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aeau +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aecu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aeeu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4au +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4cu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4eu +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54u +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYDEV_PHUB_CFG 0x40007000u +#define CYDEV_PHUB_ERR 0x40007004u +#define CYDEV_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYDEV_PHUB_CH0_ACTION 0x40007014u +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYDEV_PHUB_CH1_ACTION 0x40007024u +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYDEV_PHUB_CH2_ACTION 0x40007034u +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYDEV_PHUB_CH3_ACTION 0x40007044u +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYDEV_PHUB_CH4_ACTION 0x40007054u +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYDEV_PHUB_CH5_ACTION 0x40007064u +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYDEV_PHUB_CH6_ACTION 0x40007074u +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYDEV_PHUB_CH7_ACTION 0x40007084u +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYDEV_PHUB_CH8_ACTION 0x40007094u +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYDEV_PHUB_CH9_ACTION 0x400070a4u +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYDEV_PHUB_CH10_ACTION 0x400070b4u +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYDEV_PHUB_CH11_ACTION 0x400070c4u +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYDEV_PHUB_CH12_ACTION 0x400070d4u +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYDEV_PHUB_CH13_ACTION 0x400070e4u +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYDEV_PHUB_CH14_ACTION 0x400070f4u +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYDEV_PHUB_CH15_ACTION 0x40007104u +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYDEV_PHUB_CH16_ACTION 0x40007114u +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYDEV_PHUB_CH17_ACTION 0x40007124u +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYDEV_PHUB_CH18_ACTION 0x40007134u +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYDEV_PHUB_CH19_ACTION 0x40007144u +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYDEV_PHUB_CH20_ACTION 0x40007154u +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYDEV_PHUB_CH21_ACTION 0x40007164u +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYDEV_PHUB_CH22_ACTION 0x40007174u +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYDEV_PHUB_CH23_ACTION 0x40007184u +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYDEV_EE_DATA_MBASE 0x40008000u +#define CYDEV_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000u +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004u +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008u +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYDEV_CAN0_CSR_CMD 0x4000a010u +#define CYDEV_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYDEV_CAN0_TX0_CMD 0x4000a020u +#define CYDEV_CAN0_TX0_ID 0x4000a024u +#define CYDEV_CAN0_TX0_DH 0x4000a028u +#define CYDEV_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYDEV_CAN0_TX1_CMD 0x4000a030u +#define CYDEV_CAN0_TX1_ID 0x4000a034u +#define CYDEV_CAN0_TX1_DH 0x4000a038u +#define CYDEV_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYDEV_CAN0_TX2_CMD 0x4000a040u +#define CYDEV_CAN0_TX2_ID 0x4000a044u +#define CYDEV_CAN0_TX2_DH 0x4000a048u +#define CYDEV_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYDEV_CAN0_TX3_CMD 0x4000a050u +#define CYDEV_CAN0_TX3_ID 0x4000a054u +#define CYDEV_CAN0_TX3_DH 0x4000a058u +#define CYDEV_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYDEV_CAN0_TX4_CMD 0x4000a060u +#define CYDEV_CAN0_TX4_ID 0x4000a064u +#define CYDEV_CAN0_TX4_DH 0x4000a068u +#define CYDEV_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYDEV_CAN0_TX5_CMD 0x4000a070u +#define CYDEV_CAN0_TX5_ID 0x4000a074u +#define CYDEV_CAN0_TX5_DH 0x4000a078u +#define CYDEV_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYDEV_CAN0_TX6_CMD 0x4000a080u +#define CYDEV_CAN0_TX6_ID 0x4000a084u +#define CYDEV_CAN0_TX6_DH 0x4000a088u +#define CYDEV_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYDEV_CAN0_TX7_CMD 0x4000a090u +#define CYDEV_CAN0_TX7_ID 0x4000a094u +#define CYDEV_CAN0_TX7_DH 0x4000a098u +#define CYDEV_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0u +#define CYDEV_CAN0_RX0_ID 0x4000a0a4u +#define CYDEV_CAN0_RX0_DH 0x4000a0a8u +#define CYDEV_CAN0_RX0_DL 0x4000a0acu +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0u +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4u +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8u +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0u +#define CYDEV_CAN0_RX1_ID 0x4000a0c4u +#define CYDEV_CAN0_RX1_DH 0x4000a0c8u +#define CYDEV_CAN0_RX1_DL 0x4000a0ccu +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0u +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4u +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8u +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0u +#define CYDEV_CAN0_RX2_ID 0x4000a0e4u +#define CYDEV_CAN0_RX2_DH 0x4000a0e8u +#define CYDEV_CAN0_RX2_DL 0x4000a0ecu +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0u +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4u +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8u +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYDEV_CAN0_RX3_CMD 0x4000a100u +#define CYDEV_CAN0_RX3_ID 0x4000a104u +#define CYDEV_CAN0_RX3_DH 0x4000a108u +#define CYDEV_CAN0_RX3_DL 0x4000a10cu +#define CYDEV_CAN0_RX3_AMR 0x4000a110u +#define CYDEV_CAN0_RX3_ACR 0x4000a114u +#define CYDEV_CAN0_RX3_AMRD 0x4000a118u +#define CYDEV_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYDEV_CAN0_RX4_CMD 0x4000a120u +#define CYDEV_CAN0_RX4_ID 0x4000a124u +#define CYDEV_CAN0_RX4_DH 0x4000a128u +#define CYDEV_CAN0_RX4_DL 0x4000a12cu +#define CYDEV_CAN0_RX4_AMR 0x4000a130u +#define CYDEV_CAN0_RX4_ACR 0x4000a134u +#define CYDEV_CAN0_RX4_AMRD 0x4000a138u +#define CYDEV_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYDEV_CAN0_RX5_CMD 0x4000a140u +#define CYDEV_CAN0_RX5_ID 0x4000a144u +#define CYDEV_CAN0_RX5_DH 0x4000a148u +#define CYDEV_CAN0_RX5_DL 0x4000a14cu +#define CYDEV_CAN0_RX5_AMR 0x4000a150u +#define CYDEV_CAN0_RX5_ACR 0x4000a154u +#define CYDEV_CAN0_RX5_AMRD 0x4000a158u +#define CYDEV_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYDEV_CAN0_RX6_CMD 0x4000a160u +#define CYDEV_CAN0_RX6_ID 0x4000a164u +#define CYDEV_CAN0_RX6_DH 0x4000a168u +#define CYDEV_CAN0_RX6_DL 0x4000a16cu +#define CYDEV_CAN0_RX6_AMR 0x4000a170u +#define CYDEV_CAN0_RX6_ACR 0x4000a174u +#define CYDEV_CAN0_RX6_AMRD 0x4000a178u +#define CYDEV_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYDEV_CAN0_RX7_CMD 0x4000a180u +#define CYDEV_CAN0_RX7_ID 0x4000a184u +#define CYDEV_CAN0_RX7_DH 0x4000a188u +#define CYDEV_CAN0_RX7_DL 0x4000a18cu +#define CYDEV_CAN0_RX7_AMR 0x4000a190u +#define CYDEV_CAN0_RX7_ACR 0x4000a194u +#define CYDEV_CAN0_RX7_AMRD 0x4000a198u +#define CYDEV_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0u +#define CYDEV_CAN0_RX8_ID 0x4000a1a4u +#define CYDEV_CAN0_RX8_DH 0x4000a1a8u +#define CYDEV_CAN0_RX8_DL 0x4000a1acu +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0u +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4u +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8u +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0u +#define CYDEV_CAN0_RX9_ID 0x4000a1c4u +#define CYDEV_CAN0_RX9_DH 0x4000a1c8u +#define CYDEV_CAN0_RX9_DL 0x4000a1ccu +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0u +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4u +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8u +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0u +#define CYDEV_CAN0_RX10_ID 0x4000a1e4u +#define CYDEV_CAN0_RX10_DH 0x4000a1e8u +#define CYDEV_CAN0_RX10_DL 0x4000a1ecu +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0u +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4u +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8u +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYDEV_CAN0_RX11_CMD 0x4000a200u +#define CYDEV_CAN0_RX11_ID 0x4000a204u +#define CYDEV_CAN0_RX11_DH 0x4000a208u +#define CYDEV_CAN0_RX11_DL 0x4000a20cu +#define CYDEV_CAN0_RX11_AMR 0x4000a210u +#define CYDEV_CAN0_RX11_ACR 0x4000a214u +#define CYDEV_CAN0_RX11_AMRD 0x4000a218u +#define CYDEV_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYDEV_CAN0_RX12_CMD 0x4000a220u +#define CYDEV_CAN0_RX12_ID 0x4000a224u +#define CYDEV_CAN0_RX12_DH 0x4000a228u +#define CYDEV_CAN0_RX12_DL 0x4000a22cu +#define CYDEV_CAN0_RX12_AMR 0x4000a230u +#define CYDEV_CAN0_RX12_ACR 0x4000a234u +#define CYDEV_CAN0_RX12_AMRD 0x4000a238u +#define CYDEV_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYDEV_CAN0_RX13_CMD 0x4000a240u +#define CYDEV_CAN0_RX13_ID 0x4000a244u +#define CYDEV_CAN0_RX13_DH 0x4000a248u +#define CYDEV_CAN0_RX13_DL 0x4000a24cu +#define CYDEV_CAN0_RX13_AMR 0x4000a250u +#define CYDEV_CAN0_RX13_ACR 0x4000a254u +#define CYDEV_CAN0_RX13_AMRD 0x4000a258u +#define CYDEV_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYDEV_CAN0_RX14_CMD 0x4000a260u +#define CYDEV_CAN0_RX14_ID 0x4000a264u +#define CYDEV_CAN0_RX14_DH 0x4000a268u +#define CYDEV_CAN0_RX14_DL 0x4000a26cu +#define CYDEV_CAN0_RX14_AMR 0x4000a270u +#define CYDEV_CAN0_RX14_ACR 0x4000a274u +#define CYDEV_CAN0_RX14_AMRD 0x4000a278u +#define CYDEV_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYDEV_CAN0_RX15_CMD 0x4000a280u +#define CYDEV_CAN0_RX15_ID 0x4000a284u +#define CYDEV_CAN0_RX15_DH 0x4000a288u +#define CYDEV_CAN0_RX15_DL 0x4000a28cu +#define CYDEV_CAN0_RX15_AMR 0x4000a290u +#define CYDEV_CAN0_RX15_ACR 0x4000a294u +#define CYDEV_CAN0_RX15_AMRD 0x4000a298u +#define CYDEV_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYDEV_DFB0_CR 0x4000c780u +#define CYDEV_DFB0_SR 0x4000c784u +#define CYDEV_DFB0_RAM_EN 0x4000c788u +#define CYDEV_DFB0_RAM_DIR 0x4000c78cu +#define CYDEV_DFB0_SEMA 0x4000c790u +#define CYDEV_DFB0_DSI_CTRL 0x4000c794u +#define CYDEV_DFB0_INT_CTRL 0x4000c798u +#define CYDEV_DFB0_DMA_CTRL 0x4000c79cu +#define CYDEV_DFB0_STAGEA 0x4000c7a0u +#define CYDEV_DFB0_STAGEAM 0x4000c7a1u +#define CYDEV_DFB0_STAGEAH 0x4000c7a2u +#define CYDEV_DFB0_STAGEB 0x4000c7a4u +#define CYDEV_DFB0_STAGEBM 0x4000c7a5u +#define CYDEV_DFB0_STAGEBH 0x4000c7a6u +#define CYDEV_DFB0_HOLDA 0x4000c7a8u +#define CYDEV_DFB0_HOLDAM 0x4000c7a9u +#define CYDEV_DFB0_HOLDAH 0x4000c7aau +#define CYDEV_DFB0_HOLDAS 0x4000c7abu +#define CYDEV_DFB0_HOLDB 0x4000c7acu +#define CYDEV_DFB0_HOLDBM 0x4000c7adu +#define CYDEV_DFB0_HOLDBH 0x4000c7aeu +#define CYDEV_DFB0_HOLDBS 0x4000c7afu +#define CYDEV_DFB0_COHER 0x4000c7b0u +#define CYDEV_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040u +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041u +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042u +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043u +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044u +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045u +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046u +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047u +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048u +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049u +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004au +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004bu +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004cu +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004du +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004eu +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004fu +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050u +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051u +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052u +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053u +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054u +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055u +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056u +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057u +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058u +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059u +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005au +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005bu +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005cu +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005du +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005eu +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005fu +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060u +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062u +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064u +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066u +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068u +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006au +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006cu +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0u +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1u +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2u +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3u +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4u +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5u +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6u +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7u +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8u +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9u +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100cau +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cbu +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100ccu +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cdu +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ceu +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cfu +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0u +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1u +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2u +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3u +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4u +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5u +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6u +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7u +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8u +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9u +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100dau +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100dbu +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dcu +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100ddu +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100deu +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100dfu +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0u +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2u +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4u +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6u +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8u +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100eau +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ecu +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240u +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241u +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242u +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243u +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244u +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245u +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246u +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247u +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248u +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249u +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024au +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024bu +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024cu +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024du +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024eu +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024fu +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250u +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251u +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252u +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253u +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254u +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255u +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256u +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257u +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258u +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259u +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025au +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025bu +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025cu +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025du +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025eu +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025fu +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260u +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262u +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264u +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266u +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268u +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026au +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026cu +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0u +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1u +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2u +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3u +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4u +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5u +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6u +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7u +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8u +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9u +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102cau +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cbu +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102ccu +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cdu +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ceu +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cfu +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0u +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1u +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2u +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3u +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4u +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5u +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6u +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7u +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8u +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9u +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102dau +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102dbu +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dcu +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102ddu +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102deu +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102dfu +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0u +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2u +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4u +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6u +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8u +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102eau +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ecu +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440u +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441u +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442u +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443u +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444u +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445u +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446u +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447u +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448u +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449u +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044au +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044bu +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044cu +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044du +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044eu +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044fu +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450u +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451u +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452u +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453u +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454u +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455u +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456u +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457u +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458u +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459u +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045au +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045bu +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045cu +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045du +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045eu +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045fu +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460u +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462u +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464u +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466u +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468u +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046au +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046cu +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0u +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1u +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2u +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3u +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4u +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5u +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6u +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7u +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8u +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9u +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104cau +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cbu +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104ccu +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cdu +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ceu +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cfu +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0u +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1u +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2u +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3u +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4u +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5u +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6u +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7u +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8u +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9u +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104dau +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104dbu +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dcu +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104ddu +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104deu +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104dfu +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0u +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2u +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4u +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6u +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8u +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104eau +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ecu +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640u +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641u +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642u +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643u +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644u +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645u +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646u +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647u +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648u +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649u +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064au +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064bu +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064cu +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064du +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064eu +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064fu +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650u +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651u +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652u +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653u +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654u +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655u +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656u +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657u +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658u +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659u +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065au +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065bu +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065cu +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065du +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065eu +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065fu +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660u +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662u +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664u +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666u +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668u +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066au +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066cu +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0u +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1u +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2u +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3u +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4u +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5u +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6u +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7u +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8u +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9u +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106cau +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cbu +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106ccu +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cdu +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ceu +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cfu +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0u +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1u +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2u +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3u +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4u +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5u +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6u +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7u +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8u +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9u +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106dau +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106dbu +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dcu +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106ddu +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106deu +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106dfu +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0u +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2u +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4u +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6u +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8u +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106eau +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ecu +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840u +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841u +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842u +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843u +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844u +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845u +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846u +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847u +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848u +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849u +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084au +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084bu +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084cu +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084du +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084eu +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084fu +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850u +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851u +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852u +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853u +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854u +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855u +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856u +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857u +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858u +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859u +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085au +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085bu +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085cu +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085du +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085eu +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085fu +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860u +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862u +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864u +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866u +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868u +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086au +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086cu +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0u +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1u +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2u +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3u +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4u +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5u +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6u +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7u +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8u +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9u +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108cau +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cbu +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108ccu +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cdu +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ceu +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cfu +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0u +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1u +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2u +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3u +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4u +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5u +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6u +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7u +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8u +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9u +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108dau +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108dbu +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dcu +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108ddu +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108deu +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108dfu +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0u +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2u +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4u +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6u +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8u +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108eau +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ecu +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40u +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41u +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42u +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43u +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44u +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45u +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46u +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47u +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48u +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49u +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4au +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4bu +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4cu +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4du +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4eu +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4fu +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50u +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51u +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52u +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53u +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54u +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55u +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56u +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57u +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58u +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59u +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5au +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5bu +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5cu +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5du +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5eu +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5fu +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60u +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62u +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64u +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66u +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68u +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6au +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0u +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1u +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2u +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3u +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4u +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5u +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6u +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7u +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8u +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9u +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010acau +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acbu +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010accu +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acdu +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010aceu +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acfu +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0u +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1u +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2u +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3u +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4u +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5u +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6u +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7u +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8u +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9u +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010adau +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adbu +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adcu +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010addu +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010adeu +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adfu +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aeau +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aecu +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40u +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41u +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42u +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43u +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44u +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45u +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46u +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47u +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48u +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49u +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4au +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4bu +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4cu +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4du +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4eu +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4fu +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50u +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51u +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52u +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53u +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54u +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55u +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56u +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57u +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58u +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59u +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5au +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5bu +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5cu +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5du +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5eu +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5fu +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60u +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62u +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64u +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66u +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68u +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6au +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0u +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1u +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2u +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3u +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4u +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5u +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6u +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7u +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8u +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9u +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010ccau +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccbu +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010cccu +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccdu +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cceu +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccfu +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0u +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1u +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2u +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3u +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4u +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5u +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6u +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7u +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8u +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9u +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cdau +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdbu +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdcu +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cddu +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cdeu +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdfu +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010ceau +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cecu +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40u +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41u +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42u +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43u +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44u +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45u +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46u +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47u +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48u +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49u +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4au +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4bu +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4cu +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4du +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4eu +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4fu +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50u +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51u +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52u +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53u +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54u +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55u +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56u +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57u +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58u +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59u +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5au +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5bu +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5cu +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5du +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5eu +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5fu +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60u +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62u +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64u +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66u +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68u +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6au +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0u +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1u +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2u +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3u +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4u +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5u +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6u +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7u +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8u +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9u +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010ecau +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecbu +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010eccu +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecdu +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010eceu +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecfu +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0u +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1u +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2u +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3u +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4u +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5u +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6u +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7u +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8u +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9u +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010edau +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edbu +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edcu +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010eddu +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010edeu +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edfu +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eeau +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eecu +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440u +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441u +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442u +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443u +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444u +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445u +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446u +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447u +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448u +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449u +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144au +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144bu +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144cu +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144du +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144eu +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144fu +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450u +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451u +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452u +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453u +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454u +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455u +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456u +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457u +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458u +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459u +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145au +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145bu +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145cu +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145du +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145eu +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145fu +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460u +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462u +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464u +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466u +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468u +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146au +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146cu +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0u +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1u +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2u +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3u +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4u +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5u +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6u +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7u +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8u +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9u +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114cau +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cbu +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114ccu +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cdu +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ceu +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cfu +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0u +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1u +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2u +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3u +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4u +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5u +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6u +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7u +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8u +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9u +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114dau +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114dbu +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dcu +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114ddu +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114deu +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114dfu +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0u +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2u +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4u +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6u +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8u +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114eau +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ecu +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640u +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641u +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642u +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643u +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644u +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645u +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646u +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647u +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648u +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649u +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164au +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164bu +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164cu +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164du +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164eu +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164fu +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650u +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651u +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652u +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653u +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654u +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655u +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656u +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657u +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658u +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659u +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165au +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165bu +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165cu +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165du +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165eu +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165fu +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660u +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662u +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664u +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666u +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668u +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166au +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166cu +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0u +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1u +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2u +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3u +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4u +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5u +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6u +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7u +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8u +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9u +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116cau +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cbu +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116ccu +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cdu +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ceu +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cfu +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0u +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1u +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2u +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3u +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4u +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5u +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6u +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7u +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8u +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9u +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116dau +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116dbu +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dcu +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116ddu +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116deu +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116dfu +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0u +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2u +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4u +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6u +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8u +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116eau +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ecu +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840u +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841u +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842u +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843u +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844u +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845u +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846u +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847u +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848u +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849u +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184au +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184bu +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184cu +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184du +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184eu +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184fu +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850u +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851u +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852u +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853u +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854u +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855u +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856u +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857u +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858u +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859u +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185au +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185bu +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185cu +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185du +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185eu +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185fu +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860u +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862u +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864u +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866u +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868u +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186au +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186cu +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0u +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1u +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2u +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3u +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4u +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5u +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6u +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7u +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8u +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9u +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118cau +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cbu +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118ccu +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cdu +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ceu +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cfu +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0u +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1u +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2u +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3u +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4u +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5u +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6u +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7u +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8u +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9u +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118dau +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118dbu +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dcu +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118ddu +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118deu +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118dfu +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0u +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2u +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4u +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6u +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8u +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118eau +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ecu +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40u +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41u +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42u +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43u +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44u +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45u +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46u +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47u +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48u +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49u +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4au +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4bu +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4cu +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4du +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4eu +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4fu +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50u +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51u +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52u +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53u +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54u +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55u +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56u +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57u +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58u +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59u +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5au +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5bu +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5cu +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5du +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5eu +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5fu +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60u +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62u +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64u +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66u +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68u +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6au +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0u +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1u +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2u +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3u +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4u +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5u +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6u +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7u +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8u +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9u +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011acau +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acbu +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011accu +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acdu +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011aceu +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acfu +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0u +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1u +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2u +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3u +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4u +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5u +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6u +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7u +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8u +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9u +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011adau +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adbu +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adcu +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011addu +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011adeu +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adfu +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aeau +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aecu +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000u +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001u +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002u +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003u +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007u +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008u +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009u +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500au +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500bu +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500cu +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500du +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500eu +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010u +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011u +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012u +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013u +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017u +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018u +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019u +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501au +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501bu +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501cu +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501du +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501eu +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100u +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101u +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102u +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103u +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104u +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105u +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106u +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107u +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110u +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111u +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112u +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113u +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114u +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000u +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYDEV_SFR_GPIO0 0x40050180u +#define CYDEV_SFR_GPIRD0 0x40050189u +#define CYDEV_SFR_GPIO0_SEL 0x4005018au +#define CYDEV_SFR_GPIO1 0x40050190u +#define CYDEV_SFR_GPIRD1 0x40050191u +#define CYDEV_SFR_GPIO2 0x40050198u +#define CYDEV_SFR_GPIRD2 0x40050199u +#define CYDEV_SFR_GPIO2_SEL 0x4005019au +#define CYDEV_SFR_GPIO1_SEL 0x400501a2u +#define CYDEV_SFR_GPIO3 0x400501b0u +#define CYDEV_SFR_GPIRD3 0x400501b1u +#define CYDEV_SFR_GPIO3_SEL 0x400501b2u +#define CYDEV_SFR_GPIO4 0x400501c0u +#define CYDEV_SFR_GPIRD4 0x400501c1u +#define CYDEV_SFR_GPIO4_SEL 0x400501c2u +#define CYDEV_SFR_GPIO5 0x400501c8u +#define CYDEV_SFR_GPIRD5 0x400501c9u +#define CYDEV_SFR_GPIO5_SEL 0x400501cau +#define CYDEV_SFR_GPIO6 0x400501d8u +#define CYDEV_SFR_GPIRD6 0x400501d9u +#define CYDEV_SFR_GPIO6_SEL 0x400501dau +#define CYDEV_SFR_GPIO12 0x400501e8u +#define CYDEV_SFR_GPIRD12 0x400501e9u +#define CYDEV_SFR_GPIO12_SEL 0x400501f2u +#define CYDEV_SFR_GPIO15 0x400501f8u +#define CYDEV_SFR_GPIRD15 0x400501f9u +#define CYDEV_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYDEV_P3BA_Y_START 0x40050300u +#define CYDEV_P3BA_YROLL 0x40050301u +#define CYDEV_P3BA_YCFG 0x40050302u +#define CYDEV_P3BA_X_START1 0x40050303u +#define CYDEV_P3BA_X_START2 0x40050304u +#define CYDEV_P3BA_XROLL1 0x40050305u +#define CYDEV_P3BA_XROLL2 0x40050306u +#define CYDEV_P3BA_XINC 0x40050307u +#define CYDEV_P3BA_XCFG 0x40050308u +#define CYDEV_P3BA_OFFSETADDR1 0x40050309u +#define CYDEV_P3BA_OFFSETADDR2 0x4005030au +#define CYDEV_P3BA_OFFSETADDR3 0x4005030bu +#define CYDEV_P3BA_ABSADDR1 0x4005030cu +#define CYDEV_P3BA_ABSADDR2 0x4005030du +#define CYDEV_P3BA_ABSADDR3 0x4005030eu +#define CYDEV_P3BA_ABSADDR4 0x4005030fu +#define CYDEV_P3BA_DATCFG1 0x40050310u +#define CYDEV_P3BA_DATCFG2 0x40050311u +#define CYDEV_P3BA_CMP_RSLT1 0x40050314u +#define CYDEV_P3BA_CMP_RSLT2 0x40050315u +#define CYDEV_P3BA_CMP_RSLT3 0x40050316u +#define CYDEV_P3BA_CMP_RSLT4 0x40050317u +#define CYDEV_P3BA_DATA_REG1 0x40050318u +#define CYDEV_P3BA_DATA_REG2 0x40050319u +#define CYDEV_P3BA_DATA_REG3 0x4005031au +#define CYDEV_P3BA_DATA_REG4 0x4005031bu +#define CYDEV_P3BA_EXP_DATA1 0x4005031cu +#define CYDEV_P3BA_EXP_DATA2 0x4005031du +#define CYDEV_P3BA_EXP_DATA3 0x4005031eu +#define CYDEV_P3BA_EXP_DATA4 0x4005031fu +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320u +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321u +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322u +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323u +#define CYDEV_P3BA_BIST_EN 0x40050324u +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYDEV_P3BA_SEQCFG1 0x40050326u +#define CYDEV_P3BA_SEQCFG2 0x40050327u +#define CYDEV_P3BA_Y_CURR 0x40050328u +#define CYDEV_P3BA_X_CURR1 0x40050329u +#define CYDEV_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000u +#define CYDEV_PANTHER_WAITPIPE 0x40080004u +#define CYDEV_PANTHER_TRACE_CFG 0x40080008u +#define CYDEV_PANTHER_DBG_CFG 0x4008000cu +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYDEV_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYDEV_FLSECC_DATA_MBASE 0x48000000u +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000u +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000u +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYDEV_ITM_TRACE_EN 0xe0000e00u +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80u +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4u +#define CYDEV_ITM_PID4 0xe0000fd0u +#define CYDEV_ITM_PID5 0xe0000fd4u +#define CYDEV_ITM_PID6 0xe0000fd8u +#define CYDEV_ITM_PID7 0xe0000fdcu +#define CYDEV_ITM_PID0 0xe0000fe0u +#define CYDEV_ITM_PID1 0xe0000fe4u +#define CYDEV_ITM_PID2 0xe0000fe8u +#define CYDEV_ITM_PID3 0xe0000fecu +#define CYDEV_ITM_CID0 0xe0000ff0u +#define CYDEV_ITM_CID1 0xe0000ff4u +#define CYDEV_ITM_CID2 0xe0000ff8u +#define CYDEV_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYDEV_DWT_CTRL 0xe0001000u +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004u +#define CYDEV_DWT_CPI_COUNT 0xe0001008u +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010u +#define CYDEV_DWT_LSU_COUNT 0xe0001014u +#define CYDEV_DWT_FOLD_COUNT 0xe0001018u +#define CYDEV_DWT_PC_SAMPLE 0xe000101cu +#define CYDEV_DWT_COMP_0 0xe0001020u +#define CYDEV_DWT_MASK_0 0xe0001024u +#define CYDEV_DWT_FUNCTION_0 0xe0001028u +#define CYDEV_DWT_COMP_1 0xe0001030u +#define CYDEV_DWT_MASK_1 0xe0001034u +#define CYDEV_DWT_FUNCTION_1 0xe0001038u +#define CYDEV_DWT_COMP_2 0xe0001040u +#define CYDEV_DWT_MASK_2 0xe0001044u +#define CYDEV_DWT_FUNCTION_2 0xe0001048u +#define CYDEV_DWT_COMP_3 0xe0001050u +#define CYDEV_DWT_MASK_3 0xe0001054u +#define CYDEV_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYDEV_FPB_CTRL 0xe0002000u +#define CYDEV_FPB_REMAP 0xe0002004u +#define CYDEV_FPB_FP_COMP_0 0xe0002008u +#define CYDEV_FPB_FP_COMP_1 0xe000200cu +#define CYDEV_FPB_FP_COMP_2 0xe0002010u +#define CYDEV_FPB_FP_COMP_3 0xe0002014u +#define CYDEV_FPB_FP_COMP_4 0xe0002018u +#define CYDEV_FPB_FP_COMP_5 0xe000201cu +#define CYDEV_FPB_FP_COMP_6 0xe0002020u +#define CYDEV_FPB_FP_COMP_7 0xe0002024u +#define CYDEV_FPB_PID4 0xe0002fd0u +#define CYDEV_FPB_PID5 0xe0002fd4u +#define CYDEV_FPB_PID6 0xe0002fd8u +#define CYDEV_FPB_PID7 0xe0002fdcu +#define CYDEV_FPB_PID0 0xe0002fe0u +#define CYDEV_FPB_PID1 0xe0002fe4u +#define CYDEV_FPB_PID2 0xe0002fe8u +#define CYDEV_FPB_PID3 0xe0002fecu +#define CYDEV_FPB_CID0 0xe0002ff0u +#define CYDEV_FPB_CID1 0xe0002ff4u +#define CYDEV_FPB_CID2 0xe0002ff8u +#define CYDEV_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010u +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYDEV_NVIC_SETENA0 0xe000e100u +#define CYDEV_NVIC_CLRENA0 0xe000e180u +#define CYDEV_NVIC_SETPEND0 0xe000e200u +#define CYDEV_NVIC_CLRPEND0 0xe000e280u +#define CYDEV_NVIC_ACTIVE0 0xe000e300u +#define CYDEV_NVIC_PRI_0 0xe000e400u +#define CYDEV_NVIC_PRI_1 0xe000e401u +#define CYDEV_NVIC_PRI_2 0xe000e402u +#define CYDEV_NVIC_PRI_3 0xe000e403u +#define CYDEV_NVIC_PRI_4 0xe000e404u +#define CYDEV_NVIC_PRI_5 0xe000e405u +#define CYDEV_NVIC_PRI_6 0xe000e406u +#define CYDEV_NVIC_PRI_7 0xe000e407u +#define CYDEV_NVIC_PRI_8 0xe000e408u +#define CYDEV_NVIC_PRI_9 0xe000e409u +#define CYDEV_NVIC_PRI_10 0xe000e40au +#define CYDEV_NVIC_PRI_11 0xe000e40bu +#define CYDEV_NVIC_PRI_12 0xe000e40cu +#define CYDEV_NVIC_PRI_13 0xe000e40du +#define CYDEV_NVIC_PRI_14 0xe000e40eu +#define CYDEV_NVIC_PRI_15 0xe000e40fu +#define CYDEV_NVIC_PRI_16 0xe000e410u +#define CYDEV_NVIC_PRI_17 0xe000e411u +#define CYDEV_NVIC_PRI_18 0xe000e412u +#define CYDEV_NVIC_PRI_19 0xe000e413u +#define CYDEV_NVIC_PRI_20 0xe000e414u +#define CYDEV_NVIC_PRI_21 0xe000e415u +#define CYDEV_NVIC_PRI_22 0xe000e416u +#define CYDEV_NVIC_PRI_23 0xe000e417u +#define CYDEV_NVIC_PRI_24 0xe000e418u +#define CYDEV_NVIC_PRI_25 0xe000e419u +#define CYDEV_NVIC_PRI_26 0xe000e41au +#define CYDEV_NVIC_PRI_27 0xe000e41bu +#define CYDEV_NVIC_PRI_28 0xe000e41cu +#define CYDEV_NVIC_PRI_29 0xe000e41du +#define CYDEV_NVIC_PRI_30 0xe000e41eu +#define CYDEV_NVIC_PRI_31 0xe000e41fu +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00u +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08u +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0cu +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYDEV_TPIU_PROTOCOL 0xe00400f0u +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYDEV_TPIU_TRIGGER 0xe0040ee8u +#define CYDEV_TPIU_ITETMDATA 0xe0040eecu +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0u +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8u +#define CYDEV_TPIU_ITITMDATA 0xe0040efcu +#define CYDEV_TPIU_ITCTRL 0xe0040f00u +#define CYDEV_TPIU_DEVID 0xe0040fc8u +#define CYDEV_TPIU_DEVTYPE 0xe0040fccu +#define CYDEV_TPIU_PID4 0xe0040fd0u +#define CYDEV_TPIU_PID5 0xe0040fd4u +#define CYDEV_TPIU_PID6 0xe0040fd8u +#define CYDEV_TPIU_PID7 0xe0040fdcu +#define CYDEV_TPIU_PID0 0xe0040fe0u +#define CYDEV_TPIU_PID1 0xe0040fe4u +#define CYDEV_TPIU_PID2 0xe0040fe8u +#define CYDEV_TPIU_PID3 0xe0040fecu +#define CYDEV_TPIU_CID0 0xe0040ff0u +#define CYDEV_TPIU_CID1 0xe0040ff4u +#define CYDEV_TPIU_CID2 0xe0040ff8u +#define CYDEV_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYDEV_ETM_CTL 0xe0041000u +#define CYDEV_ETM_CFG_CODE 0xe0041004u +#define CYDEV_ETM_TRIG_EVENT 0xe0041008u +#define CYDEV_ETM_STATUS 0xe0041010u +#define CYDEV_ETM_SYS_CFG 0xe0041014u +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0u +#define CYDEV_ETM_ETM_ID 0xe00411e4u +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200u +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYDEV_ETM_PDSR 0xe0041314u +#define CYDEV_ETM_ITMISCIN 0xe0041ee0u +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8u +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0u +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8u +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4u +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8u +#define CYDEV_ETM_DEV_TYPE 0xe0041fccu +#define CYDEV_ETM_PID4 0xe0041fd0u +#define CYDEV_ETM_PID5 0xe0041fd4u +#define CYDEV_ETM_PID6 0xe0041fd8u +#define CYDEV_ETM_PID7 0xe0041fdcu +#define CYDEV_ETM_PID0 0xe0041fe0u +#define CYDEV_ETM_PID1 0xe0041fe4u +#define CYDEV_ETM_PID2 0xe0041fe8u +#define CYDEV_ETM_PID3 0xe0041fecu +#define CYDEV_ETM_CID0 0xe0041ff0u +#define CYDEV_ETM_CID1 0xe0041ff4u +#define CYDEV_ETM_CID2 0xe0041ff8u +#define CYDEV_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000u +#define CYDEV_ROM_TABLE_DWT 0xe00ff004u +#define CYDEV_ROM_TABLE_FPB 0xe00ff008u +#define CYDEV_ROM_TABLE_ITM 0xe00ff00cu +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010u +#define CYDEV_ROM_TABLE_ETM 0xe00ff014u +#define CYDEV_ROM_TABLE_END 0xe00ff018u +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0u +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4u +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8u +#define CYDEV_ROM_TABLE_PID7 0xe00fffdcu +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0u +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4u +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8u +#define CYDEV_ROM_TABLE_PID3 0xe00fffecu +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0u +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4u +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8u +#define CYDEV_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h new file mode 100644 index 0000000..b05fd82 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevice_trm.h @@ -0,0 +1,5360 @@ +/******************************************************************************* +* File Name: cydevice_trm.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#if !defined(CYDEVICE_TRM_H) +#define CYDEVICE_TRM_H +#define CYDEV_FLASH_BASE 0x00000000u +#define CYDEV_FLASH_SIZE 0x00020000u +#define CYREG_FLASH_DATA_MBASE 0x00000000u +#define CYREG_FLASH_DATA_MSIZE 0x00020000u +#define CYDEV_SRAM_BASE 0x1fffc000u +#define CYDEV_SRAM_SIZE 0x00008000u +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000u +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000u +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000u +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000u +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000u +#define CYREG_SRAM_CODE_MBASE 0x1fffc000u +#define CYREG_SRAM_CODE_MSIZE 0x00004000u +#define CYREG_SRAM_DATA_MBASE 0x20000000u +#define CYREG_SRAM_DATA_MSIZE 0x00004000u +#define CYREG_SRAM_DATA16K_MBASE 0x20001000u +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000u +#define CYREG_SRAM_DATA32K_MBASE 0x20002000u +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000u +#define CYREG_SRAM_DATA64K_MBASE 0x20004000u +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000u +#define CYDEV_DMA_BASE 0x20008000u +#define CYDEV_DMA_SIZE 0x00008000u +#define CYREG_DMA_SRAM64K_MBASE 0x20008000u +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000u +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000u +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000u +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000u +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000u +#define CYREG_DMA_SRAM_MBASE 0x2000f000u +#define CYREG_DMA_SRAM_MSIZE 0x00001000u +#define CYDEV_CLKDIST_BASE 0x40004000u +#define CYDEV_CLKDIST_SIZE 0x00000110u +#define CYREG_CLKDIST_CR 0x40004000u +#define CYREG_CLKDIST_LD 0x40004001u +#define CYREG_CLKDIST_WRK0 0x40004002u +#define CYREG_CLKDIST_WRK1 0x40004003u +#define CYREG_CLKDIST_MSTR0 0x40004004u +#define CYREG_CLKDIST_MSTR1 0x40004005u +#define CYREG_CLKDIST_BCFG0 0x40004006u +#define CYREG_CLKDIST_BCFG1 0x40004007u +#define CYREG_CLKDIST_BCFG2 0x40004008u +#define CYREG_CLKDIST_UCFG 0x40004009u +#define CYREG_CLKDIST_DLY0 0x4000400au +#define CYREG_CLKDIST_DLY1 0x4000400bu +#define CYREG_CLKDIST_DMASK 0x40004010u +#define CYREG_CLKDIST_AMASK 0x40004014u +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080u +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080u +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081u +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082u +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084u +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084u +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085u +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086u +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088u +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088u +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089u +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408au +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408cu +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408cu +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408du +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408eu +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090u +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090u +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091u +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092u +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094u +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094u +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095u +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096u +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098u +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098u +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099u +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409au +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409cu +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003u +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409cu +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409du +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409eu +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100u +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100u +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101u +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102u +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103u +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104u +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104u +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105u +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106u +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107u +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108u +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108u +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109u +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410au +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410bu +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410cu +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004u +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410cu +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410du +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410eu +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410fu +#define CYDEV_FASTCLK_BASE 0x40004200u +#define CYDEV_FASTCLK_SIZE 0x00000026u +#define CYDEV_FASTCLK_IMO_BASE 0x40004200u +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001u +#define CYREG_FASTCLK_IMO_CR 0x40004200u +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210u +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004u +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210u +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212u +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213u +#define CYDEV_FASTCLK_PLL_BASE 0x40004220u +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006u +#define CYREG_FASTCLK_PLL_CFG0 0x40004220u +#define CYREG_FASTCLK_PLL_CFG1 0x40004221u +#define CYREG_FASTCLK_PLL_P 0x40004222u +#define CYREG_FASTCLK_PLL_Q 0x40004223u +#define CYREG_FASTCLK_PLL_SR 0x40004225u +#define CYDEV_SLOWCLK_BASE 0x40004300u +#define CYDEV_SLOWCLK_SIZE 0x0000000bu +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300u +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002u +#define CYREG_SLOWCLK_ILO_CR0 0x40004300u +#define CYREG_SLOWCLK_ILO_CR1 0x40004301u +#define CYDEV_SLOWCLK_X32_BASE 0x40004308u +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003u +#define CYREG_SLOWCLK_X32_CR 0x40004308u +#define CYREG_SLOWCLK_X32_CFG 0x40004309u +#define CYREG_SLOWCLK_X32_TST 0x4000430au +#define CYDEV_BOOST_BASE 0x40004320u +#define CYDEV_BOOST_SIZE 0x00000007u +#define CYREG_BOOST_CR0 0x40004320u +#define CYREG_BOOST_CR1 0x40004321u +#define CYREG_BOOST_CR2 0x40004322u +#define CYREG_BOOST_CR3 0x40004323u +#define CYREG_BOOST_SR 0x40004324u +#define CYREG_BOOST_CR4 0x40004325u +#define CYREG_BOOST_SR2 0x40004326u +#define CYDEV_PWRSYS_BASE 0x40004330u +#define CYDEV_PWRSYS_SIZE 0x00000002u +#define CYREG_PWRSYS_CR0 0x40004330u +#define CYREG_PWRSYS_CR1 0x40004331u +#define CYDEV_PM_BASE 0x40004380u +#define CYDEV_PM_SIZE 0x00000057u +#define CYREG_PM_TW_CFG0 0x40004380u +#define CYREG_PM_TW_CFG1 0x40004381u +#define CYREG_PM_TW_CFG2 0x40004382u +#define CYREG_PM_WDT_CFG 0x40004383u +#define CYREG_PM_WDT_CR 0x40004384u +#define CYREG_PM_INT_SR 0x40004390u +#define CYREG_PM_MODE_CFG0 0x40004391u +#define CYREG_PM_MODE_CFG1 0x40004392u +#define CYREG_PM_MODE_CSR 0x40004393u +#define CYREG_PM_USB_CR0 0x40004394u +#define CYREG_PM_WAKEUP_CFG0 0x40004398u +#define CYREG_PM_WAKEUP_CFG1 0x40004399u +#define CYREG_PM_WAKEUP_CFG2 0x4000439au +#define CYDEV_PM_ACT_BASE 0x400043a0u +#define CYDEV_PM_ACT_SIZE 0x0000000eu +#define CYREG_PM_ACT_CFG0 0x400043a0u +#define CYREG_PM_ACT_CFG1 0x400043a1u +#define CYREG_PM_ACT_CFG2 0x400043a2u +#define CYREG_PM_ACT_CFG3 0x400043a3u +#define CYREG_PM_ACT_CFG4 0x400043a4u +#define CYREG_PM_ACT_CFG5 0x400043a5u +#define CYREG_PM_ACT_CFG6 0x400043a6u +#define CYREG_PM_ACT_CFG7 0x400043a7u +#define CYREG_PM_ACT_CFG8 0x400043a8u +#define CYREG_PM_ACT_CFG9 0x400043a9u +#define CYREG_PM_ACT_CFG10 0x400043aau +#define CYREG_PM_ACT_CFG11 0x400043abu +#define CYREG_PM_ACT_CFG12 0x400043acu +#define CYREG_PM_ACT_CFG13 0x400043adu +#define CYDEV_PM_STBY_BASE 0x400043b0u +#define CYDEV_PM_STBY_SIZE 0x0000000eu +#define CYREG_PM_STBY_CFG0 0x400043b0u +#define CYREG_PM_STBY_CFG1 0x400043b1u +#define CYREG_PM_STBY_CFG2 0x400043b2u +#define CYREG_PM_STBY_CFG3 0x400043b3u +#define CYREG_PM_STBY_CFG4 0x400043b4u +#define CYREG_PM_STBY_CFG5 0x400043b5u +#define CYREG_PM_STBY_CFG6 0x400043b6u +#define CYREG_PM_STBY_CFG7 0x400043b7u +#define CYREG_PM_STBY_CFG8 0x400043b8u +#define CYREG_PM_STBY_CFG9 0x400043b9u +#define CYREG_PM_STBY_CFG10 0x400043bau +#define CYREG_PM_STBY_CFG11 0x400043bbu +#define CYREG_PM_STBY_CFG12 0x400043bcu +#define CYREG_PM_STBY_CFG13 0x400043bdu +#define CYDEV_PM_AVAIL_BASE 0x400043c0u +#define CYDEV_PM_AVAIL_SIZE 0x00000017u +#define CYREG_PM_AVAIL_CR0 0x400043c0u +#define CYREG_PM_AVAIL_CR1 0x400043c1u +#define CYREG_PM_AVAIL_CR2 0x400043c2u +#define CYREG_PM_AVAIL_CR3 0x400043c3u +#define CYREG_PM_AVAIL_CR4 0x400043c4u +#define CYREG_PM_AVAIL_CR5 0x400043c5u +#define CYREG_PM_AVAIL_CR6 0x400043c6u +#define CYREG_PM_AVAIL_SR0 0x400043d0u +#define CYREG_PM_AVAIL_SR1 0x400043d1u +#define CYREG_PM_AVAIL_SR2 0x400043d2u +#define CYREG_PM_AVAIL_SR3 0x400043d3u +#define CYREG_PM_AVAIL_SR4 0x400043d4u +#define CYREG_PM_AVAIL_SR5 0x400043d5u +#define CYREG_PM_AVAIL_SR6 0x400043d6u +#define CYDEV_PICU_BASE 0x40004500u +#define CYDEV_PICU_SIZE 0x000000b0u +#define CYDEV_PICU_INTTYPE_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080u +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500u +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008u +#define CYREG_PICU0_INTTYPE0 0x40004500u +#define CYREG_PICU0_INTTYPE1 0x40004501u +#define CYREG_PICU0_INTTYPE2 0x40004502u +#define CYREG_PICU0_INTTYPE3 0x40004503u +#define CYREG_PICU0_INTTYPE4 0x40004504u +#define CYREG_PICU0_INTTYPE5 0x40004505u +#define CYREG_PICU0_INTTYPE6 0x40004506u +#define CYREG_PICU0_INTTYPE7 0x40004507u +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508u +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008u +#define CYREG_PICU1_INTTYPE0 0x40004508u +#define CYREG_PICU1_INTTYPE1 0x40004509u +#define CYREG_PICU1_INTTYPE2 0x4000450au +#define CYREG_PICU1_INTTYPE3 0x4000450bu +#define CYREG_PICU1_INTTYPE4 0x4000450cu +#define CYREG_PICU1_INTTYPE5 0x4000450du +#define CYREG_PICU1_INTTYPE6 0x4000450eu +#define CYREG_PICU1_INTTYPE7 0x4000450fu +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510u +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008u +#define CYREG_PICU2_INTTYPE0 0x40004510u +#define CYREG_PICU2_INTTYPE1 0x40004511u +#define CYREG_PICU2_INTTYPE2 0x40004512u +#define CYREG_PICU2_INTTYPE3 0x40004513u +#define CYREG_PICU2_INTTYPE4 0x40004514u +#define CYREG_PICU2_INTTYPE5 0x40004515u +#define CYREG_PICU2_INTTYPE6 0x40004516u +#define CYREG_PICU2_INTTYPE7 0x40004517u +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518u +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008u +#define CYREG_PICU3_INTTYPE0 0x40004518u +#define CYREG_PICU3_INTTYPE1 0x40004519u +#define CYREG_PICU3_INTTYPE2 0x4000451au +#define CYREG_PICU3_INTTYPE3 0x4000451bu +#define CYREG_PICU3_INTTYPE4 0x4000451cu +#define CYREG_PICU3_INTTYPE5 0x4000451du +#define CYREG_PICU3_INTTYPE6 0x4000451eu +#define CYREG_PICU3_INTTYPE7 0x4000451fu +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520u +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008u +#define CYREG_PICU4_INTTYPE0 0x40004520u +#define CYREG_PICU4_INTTYPE1 0x40004521u +#define CYREG_PICU4_INTTYPE2 0x40004522u +#define CYREG_PICU4_INTTYPE3 0x40004523u +#define CYREG_PICU4_INTTYPE4 0x40004524u +#define CYREG_PICU4_INTTYPE5 0x40004525u +#define CYREG_PICU4_INTTYPE6 0x40004526u +#define CYREG_PICU4_INTTYPE7 0x40004527u +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528u +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008u +#define CYREG_PICU5_INTTYPE0 0x40004528u +#define CYREG_PICU5_INTTYPE1 0x40004529u +#define CYREG_PICU5_INTTYPE2 0x4000452au +#define CYREG_PICU5_INTTYPE3 0x4000452bu +#define CYREG_PICU5_INTTYPE4 0x4000452cu +#define CYREG_PICU5_INTTYPE5 0x4000452du +#define CYREG_PICU5_INTTYPE6 0x4000452eu +#define CYREG_PICU5_INTTYPE7 0x4000452fu +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530u +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008u +#define CYREG_PICU6_INTTYPE0 0x40004530u +#define CYREG_PICU6_INTTYPE1 0x40004531u +#define CYREG_PICU6_INTTYPE2 0x40004532u +#define CYREG_PICU6_INTTYPE3 0x40004533u +#define CYREG_PICU6_INTTYPE4 0x40004534u +#define CYREG_PICU6_INTTYPE5 0x40004535u +#define CYREG_PICU6_INTTYPE6 0x40004536u +#define CYREG_PICU6_INTTYPE7 0x40004537u +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560u +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008u +#define CYREG_PICU12_INTTYPE0 0x40004560u +#define CYREG_PICU12_INTTYPE1 0x40004561u +#define CYREG_PICU12_INTTYPE2 0x40004562u +#define CYREG_PICU12_INTTYPE3 0x40004563u +#define CYREG_PICU12_INTTYPE4 0x40004564u +#define CYREG_PICU12_INTTYPE5 0x40004565u +#define CYREG_PICU12_INTTYPE6 0x40004566u +#define CYREG_PICU12_INTTYPE7 0x40004567u +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578u +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008u +#define CYREG_PICU15_INTTYPE0 0x40004578u +#define CYREG_PICU15_INTTYPE1 0x40004579u +#define CYREG_PICU15_INTTYPE2 0x4000457au +#define CYREG_PICU15_INTTYPE3 0x4000457bu +#define CYREG_PICU15_INTTYPE4 0x4000457cu +#define CYREG_PICU15_INTTYPE5 0x4000457du +#define CYREG_PICU15_INTTYPE6 0x4000457eu +#define CYREG_PICU15_INTTYPE7 0x4000457fu +#define CYDEV_PICU_STAT_BASE 0x40004580u +#define CYDEV_PICU_STAT_SIZE 0x00000010u +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580u +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_INTSTAT 0x40004580u +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581u +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_INTSTAT 0x40004581u +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582u +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_INTSTAT 0x40004582u +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583u +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_INTSTAT 0x40004583u +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584u +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_INTSTAT 0x40004584u +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585u +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_INTSTAT 0x40004585u +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586u +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_INTSTAT 0x40004586u +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458cu +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_INTSTAT 0x4000458cu +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458fu +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_INTSTAT 0x4000458fu +#define CYDEV_PICU_SNAP_BASE 0x40004590u +#define CYDEV_PICU_SNAP_SIZE 0x00000010u +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590u +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_SNAP 0x40004590u +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591u +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_SNAP 0x40004591u +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592u +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_SNAP 0x40004592u +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593u +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_SNAP 0x40004593u +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594u +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_SNAP 0x40004594u +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595u +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_SNAP 0x40004595u +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596u +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_SNAP 0x40004596u +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459cu +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_SNAP 0x4000459cu +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459fu +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001u +#define CYREG_PICU_15_SNAP_15 0x4000459fu +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010u +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001u +#define CYREG_PICU0_DISABLE_COR 0x400045a0u +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001u +#define CYREG_PICU1_DISABLE_COR 0x400045a1u +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001u +#define CYREG_PICU2_DISABLE_COR 0x400045a2u +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001u +#define CYREG_PICU3_DISABLE_COR 0x400045a3u +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001u +#define CYREG_PICU4_DISABLE_COR 0x400045a4u +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001u +#define CYREG_PICU5_DISABLE_COR 0x400045a5u +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001u +#define CYREG_PICU6_DISABLE_COR 0x400045a6u +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001u +#define CYREG_PICU12_DISABLE_COR 0x400045acu +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045afu +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001u +#define CYREG_PICU15_DISABLE_COR 0x400045afu +#define CYDEV_MFGCFG_BASE 0x40004600u +#define CYDEV_MFGCFG_SIZE 0x000000edu +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600u +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038u +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_TR 0x40004608u +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_TR 0x40004609u +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_TR 0x4000460au +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_TR 0x4000460bu +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001u +#define CYREG_NPUMP_DSM_TR0 0x40004610u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001u +#define CYREG_NPUMP_SC_TR0 0x40004611u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612u +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001u +#define CYREG_NPUMP_OPAMP_TR0 0x40004612u +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001u +#define CYREG_SAR0_TR0 0x40004614u +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616u +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001u +#define CYREG_SAR1_TR0 0x40004616u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620u +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_TR0 0x40004620u +#define CYREG_OPAMP0_TR1 0x40004621u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622u +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_TR0 0x40004622u +#define CYREG_OPAMP1_TR1 0x40004623u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624u +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_TR0 0x40004624u +#define CYREG_OPAMP2_TR1 0x40004625u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626u +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_TR0 0x40004626u +#define CYREG_OPAMP3_TR1 0x40004627u +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630u +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002u +#define CYREG_CMP0_TR0 0x40004630u +#define CYREG_CMP0_TR1 0x40004631u +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632u +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002u +#define CYREG_CMP1_TR0 0x40004632u +#define CYREG_CMP1_TR1 0x40004633u +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634u +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002u +#define CYREG_CMP2_TR0 0x40004634u +#define CYREG_CMP2_TR1 0x40004635u +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636u +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002u +#define CYREG_CMP3_TR0 0x40004636u +#define CYREG_CMP3_TR1 0x40004637u +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680u +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000bu +#define CYREG_PWRSYS_HIB_TR0 0x40004680u +#define CYREG_PWRSYS_HIB_TR1 0x40004681u +#define CYREG_PWRSYS_I2C_TR 0x40004682u +#define CYREG_PWRSYS_SLP_TR 0x40004683u +#define CYREG_PWRSYS_BUZZ_TR 0x40004684u +#define CYREG_PWRSYS_WAKE_TR0 0x40004685u +#define CYREG_PWRSYS_WAKE_TR1 0x40004686u +#define CYREG_PWRSYS_BREF_TR 0x40004687u +#define CYREG_PWRSYS_BG_TR 0x40004688u +#define CYREG_PWRSYS_WAKE_TR2 0x40004689u +#define CYREG_PWRSYS_WAKE_TR3 0x4000468au +#define CYDEV_MFGCFG_ILO_BASE 0x40004690u +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002u +#define CYREG_ILO_TR0 0x40004690u +#define CYREG_ILO_TR1 0x40004691u +#define CYDEV_MFGCFG_X32_BASE 0x40004698u +#define CYDEV_MFGCFG_X32_SIZE 0x00000001u +#define CYREG_X32_TR 0x40004698u +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0u +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005u +#define CYREG_IMO_TR0 0x400046a0u +#define CYREG_IMO_TR1 0x400046a1u +#define CYREG_IMO_GAIN 0x400046a2u +#define CYREG_IMO_C36M 0x400046a3u +#define CYREG_IMO_TR2 0x400046a4u +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8u +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001u +#define CYREG_XMHZ_TR 0x400046a8u +#define CYREG_MFGCFG_DLY 0x400046c0u +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0u +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000du +#define CYREG_MLOGIC_DMPSTR 0x400046e2u +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4u +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002u +#define CYREG_MLOGIC_SEG_CR 0x400046e4u +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5u +#define CYREG_MLOGIC_DEBUG 0x400046e8u +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046eau +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001u +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046eau +#define CYREG_MLOGIC_REV_ID 0x400046ecu +#define CYDEV_RESET_BASE 0x400046f0u +#define CYDEV_RESET_SIZE 0x0000000fu +#define CYREG_RESET_IPOR_CR0 0x400046f0u +#define CYREG_RESET_IPOR_CR1 0x400046f1u +#define CYREG_RESET_IPOR_CR2 0x400046f2u +#define CYREG_RESET_IPOR_CR3 0x400046f3u +#define CYREG_RESET_CR0 0x400046f4u +#define CYREG_RESET_CR1 0x400046f5u +#define CYREG_RESET_CR2 0x400046f6u +#define CYREG_RESET_CR3 0x400046f7u +#define CYREG_RESET_CR4 0x400046f8u +#define CYREG_RESET_CR5 0x400046f9u +#define CYREG_RESET_SR0 0x400046fau +#define CYREG_RESET_SR1 0x400046fbu +#define CYREG_RESET_SR2 0x400046fcu +#define CYREG_RESET_SR3 0x400046fdu +#define CYREG_RESET_TR 0x400046feu +#define CYDEV_SPC_BASE 0x40004700u +#define CYDEV_SPC_SIZE 0x00000100u +#define CYREG_SPC_FM_EE_CR 0x40004700u +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701u +#define CYREG_SPC_EE_SCR 0x40004702u +#define CYREG_SPC_EE_ERR 0x40004703u +#define CYREG_SPC_CPU_DATA 0x40004720u +#define CYREG_SPC_DMA_DATA 0x40004721u +#define CYREG_SPC_SR 0x40004722u +#define CYREG_SPC_CR 0x40004723u +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780u +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080u +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780u +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080u +#define CYDEV_CACHE_BASE 0x40004800u +#define CYDEV_CACHE_SIZE 0x0000009cu +#define CYREG_CACHE_CC_CTL 0x40004800u +#define CYREG_CACHE_ECC_CORR 0x40004880u +#define CYREG_CACHE_ECC_ERR 0x40004888u +#define CYREG_CACHE_FLASH_ERR 0x40004890u +#define CYREG_CACHE_HITMISS 0x40004898u +#define CYDEV_I2C_BASE 0x40004900u +#define CYDEV_I2C_SIZE 0x000000e1u +#define CYREG_I2C_XCFG 0x400049c8u +#define CYREG_I2C_ADR 0x400049cau +#define CYREG_I2C_CFG 0x400049d6u +#define CYREG_I2C_CSR 0x400049d7u +#define CYREG_I2C_D 0x400049d8u +#define CYREG_I2C_MCSR 0x400049d9u +#define CYREG_I2C_CLK_DIV1 0x400049dbu +#define CYREG_I2C_CLK_DIV2 0x400049dcu +#define CYREG_I2C_TMOUT_CSR 0x400049ddu +#define CYREG_I2C_TMOUT_SR 0x400049deu +#define CYREG_I2C_TMOUT_CFG0 0x400049dfu +#define CYREG_I2C_TMOUT_CFG1 0x400049e0u +#define CYDEV_DEC_BASE 0x40004e00u +#define CYDEV_DEC_SIZE 0x00000015u +#define CYREG_DEC_CR 0x40004e00u +#define CYREG_DEC_SR 0x40004e01u +#define CYREG_DEC_SHIFT1 0x40004e02u +#define CYREG_DEC_SHIFT2 0x40004e03u +#define CYREG_DEC_DR2 0x40004e04u +#define CYREG_DEC_DR2H 0x40004e05u +#define CYREG_DEC_DR1 0x40004e06u +#define CYREG_DEC_OCOR 0x40004e08u +#define CYREG_DEC_OCORM 0x40004e09u +#define CYREG_DEC_OCORH 0x40004e0au +#define CYREG_DEC_GCOR 0x40004e0cu +#define CYREG_DEC_GCORH 0x40004e0du +#define CYREG_DEC_GVAL 0x40004e0eu +#define CYREG_DEC_OUTSAMP 0x40004e10u +#define CYREG_DEC_OUTSAMPM 0x40004e11u +#define CYREG_DEC_OUTSAMPH 0x40004e12u +#define CYREG_DEC_OUTSAMPS 0x40004e13u +#define CYREG_DEC_COHER 0x40004e14u +#define CYDEV_TMR0_BASE 0x40004f00u +#define CYDEV_TMR0_SIZE 0x0000000cu +#define CYREG_TMR0_CFG0 0x40004f00u +#define CYREG_TMR0_CFG1 0x40004f01u +#define CYREG_TMR0_CFG2 0x40004f02u +#define CYREG_TMR0_SR0 0x40004f03u +#define CYREG_TMR0_PER0 0x40004f04u +#define CYREG_TMR0_PER1 0x40004f05u +#define CYREG_TMR0_CNT_CMP0 0x40004f06u +#define CYREG_TMR0_CNT_CMP1 0x40004f07u +#define CYREG_TMR0_CAP0 0x40004f08u +#define CYREG_TMR0_CAP1 0x40004f09u +#define CYREG_TMR0_RT0 0x40004f0au +#define CYREG_TMR0_RT1 0x40004f0bu +#define CYDEV_TMR1_BASE 0x40004f0cu +#define CYDEV_TMR1_SIZE 0x0000000cu +#define CYREG_TMR1_CFG0 0x40004f0cu +#define CYREG_TMR1_CFG1 0x40004f0du +#define CYREG_TMR1_CFG2 0x40004f0eu +#define CYREG_TMR1_SR0 0x40004f0fu +#define CYREG_TMR1_PER0 0x40004f10u +#define CYREG_TMR1_PER1 0x40004f11u +#define CYREG_TMR1_CNT_CMP0 0x40004f12u +#define CYREG_TMR1_CNT_CMP1 0x40004f13u +#define CYREG_TMR1_CAP0 0x40004f14u +#define CYREG_TMR1_CAP1 0x40004f15u +#define CYREG_TMR1_RT0 0x40004f16u +#define CYREG_TMR1_RT1 0x40004f17u +#define CYDEV_TMR2_BASE 0x40004f18u +#define CYDEV_TMR2_SIZE 0x0000000cu +#define CYREG_TMR2_CFG0 0x40004f18u +#define CYREG_TMR2_CFG1 0x40004f19u +#define CYREG_TMR2_CFG2 0x40004f1au +#define CYREG_TMR2_SR0 0x40004f1bu +#define CYREG_TMR2_PER0 0x40004f1cu +#define CYREG_TMR2_PER1 0x40004f1du +#define CYREG_TMR2_CNT_CMP0 0x40004f1eu +#define CYREG_TMR2_CNT_CMP1 0x40004f1fu +#define CYREG_TMR2_CAP0 0x40004f20u +#define CYREG_TMR2_CAP1 0x40004f21u +#define CYREG_TMR2_RT0 0x40004f22u +#define CYREG_TMR2_RT1 0x40004f23u +#define CYDEV_TMR3_BASE 0x40004f24u +#define CYDEV_TMR3_SIZE 0x0000000cu +#define CYREG_TMR3_CFG0 0x40004f24u +#define CYREG_TMR3_CFG1 0x40004f25u +#define CYREG_TMR3_CFG2 0x40004f26u +#define CYREG_TMR3_SR0 0x40004f27u +#define CYREG_TMR3_PER0 0x40004f28u +#define CYREG_TMR3_PER1 0x40004f29u +#define CYREG_TMR3_CNT_CMP0 0x40004f2au +#define CYREG_TMR3_CNT_CMP1 0x40004f2bu +#define CYREG_TMR3_CAP0 0x40004f2cu +#define CYREG_TMR3_CAP1 0x40004f2du +#define CYREG_TMR3_RT0 0x40004f2eu +#define CYREG_TMR3_RT1 0x40004f2fu +#define CYDEV_IO_BASE 0x40005000u +#define CYDEV_IO_SIZE 0x00000200u +#define CYDEV_IO_PC_BASE 0x40005000u +#define CYDEV_IO_PC_SIZE 0x00000080u +#define CYDEV_IO_PC_PRT0_BASE 0x40005000u +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008u +#define CYREG_PRT0_PC0 0x40005000u +#define CYREG_PRT0_PC1 0x40005001u +#define CYREG_PRT0_PC2 0x40005002u +#define CYREG_PRT0_PC3 0x40005003u +#define CYREG_PRT0_PC4 0x40005004u +#define CYREG_PRT0_PC5 0x40005005u +#define CYREG_PRT0_PC6 0x40005006u +#define CYREG_PRT0_PC7 0x40005007u +#define CYDEV_IO_PC_PRT1_BASE 0x40005008u +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008u +#define CYREG_PRT1_PC0 0x40005008u +#define CYREG_PRT1_PC1 0x40005009u +#define CYREG_PRT1_PC2 0x4000500au +#define CYREG_PRT1_PC3 0x4000500bu +#define CYREG_PRT1_PC4 0x4000500cu +#define CYREG_PRT1_PC5 0x4000500du +#define CYREG_PRT1_PC6 0x4000500eu +#define CYREG_PRT1_PC7 0x4000500fu +#define CYDEV_IO_PC_PRT2_BASE 0x40005010u +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008u +#define CYREG_PRT2_PC0 0x40005010u +#define CYREG_PRT2_PC1 0x40005011u +#define CYREG_PRT2_PC2 0x40005012u +#define CYREG_PRT2_PC3 0x40005013u +#define CYREG_PRT2_PC4 0x40005014u +#define CYREG_PRT2_PC5 0x40005015u +#define CYREG_PRT2_PC6 0x40005016u +#define CYREG_PRT2_PC7 0x40005017u +#define CYDEV_IO_PC_PRT3_BASE 0x40005018u +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008u +#define CYREG_PRT3_PC0 0x40005018u +#define CYREG_PRT3_PC1 0x40005019u +#define CYREG_PRT3_PC2 0x4000501au +#define CYREG_PRT3_PC3 0x4000501bu +#define CYREG_PRT3_PC4 0x4000501cu +#define CYREG_PRT3_PC5 0x4000501du +#define CYREG_PRT3_PC6 0x4000501eu +#define CYREG_PRT3_PC7 0x4000501fu +#define CYDEV_IO_PC_PRT4_BASE 0x40005020u +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008u +#define CYREG_PRT4_PC0 0x40005020u +#define CYREG_PRT4_PC1 0x40005021u +#define CYREG_PRT4_PC2 0x40005022u +#define CYREG_PRT4_PC3 0x40005023u +#define CYREG_PRT4_PC4 0x40005024u +#define CYREG_PRT4_PC5 0x40005025u +#define CYREG_PRT4_PC6 0x40005026u +#define CYREG_PRT4_PC7 0x40005027u +#define CYDEV_IO_PC_PRT5_BASE 0x40005028u +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008u +#define CYREG_PRT5_PC0 0x40005028u +#define CYREG_PRT5_PC1 0x40005029u +#define CYREG_PRT5_PC2 0x4000502au +#define CYREG_PRT5_PC3 0x4000502bu +#define CYREG_PRT5_PC4 0x4000502cu +#define CYREG_PRT5_PC5 0x4000502du +#define CYREG_PRT5_PC6 0x4000502eu +#define CYREG_PRT5_PC7 0x4000502fu +#define CYDEV_IO_PC_PRT6_BASE 0x40005030u +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008u +#define CYREG_PRT6_PC0 0x40005030u +#define CYREG_PRT6_PC1 0x40005031u +#define CYREG_PRT6_PC2 0x40005032u +#define CYREG_PRT6_PC3 0x40005033u +#define CYREG_PRT6_PC4 0x40005034u +#define CYREG_PRT6_PC5 0x40005035u +#define CYREG_PRT6_PC6 0x40005036u +#define CYREG_PRT6_PC7 0x40005037u +#define CYDEV_IO_PC_PRT12_BASE 0x40005060u +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008u +#define CYREG_PRT12_PC0 0x40005060u +#define CYREG_PRT12_PC1 0x40005061u +#define CYREG_PRT12_PC2 0x40005062u +#define CYREG_PRT12_PC3 0x40005063u +#define CYREG_PRT12_PC4 0x40005064u +#define CYREG_PRT12_PC5 0x40005065u +#define CYREG_PRT12_PC6 0x40005066u +#define CYREG_PRT12_PC7 0x40005067u +#define CYDEV_IO_PC_PRT15_BASE 0x40005078u +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006u +#define CYREG_IO_PC_PRT15_PC0 0x40005078u +#define CYREG_IO_PC_PRT15_PC1 0x40005079u +#define CYREG_IO_PC_PRT15_PC2 0x4000507au +#define CYREG_IO_PC_PRT15_PC3 0x4000507bu +#define CYREG_IO_PC_PRT15_PC4 0x4000507cu +#define CYREG_IO_PC_PRT15_PC5 0x4000507du +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507eu +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002u +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507eu +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507fu +#define CYDEV_IO_DR_BASE 0x40005080u +#define CYDEV_IO_DR_SIZE 0x00000010u +#define CYDEV_IO_DR_PRT0_BASE 0x40005080u +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_DR_ALIAS 0x40005080u +#define CYDEV_IO_DR_PRT1_BASE 0x40005081u +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_DR_ALIAS 0x40005081u +#define CYDEV_IO_DR_PRT2_BASE 0x40005082u +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_DR_ALIAS 0x40005082u +#define CYDEV_IO_DR_PRT3_BASE 0x40005083u +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_DR_ALIAS 0x40005083u +#define CYDEV_IO_DR_PRT4_BASE 0x40005084u +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_DR_ALIAS 0x40005084u +#define CYDEV_IO_DR_PRT5_BASE 0x40005085u +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_DR_ALIAS 0x40005085u +#define CYDEV_IO_DR_PRT6_BASE 0x40005086u +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_DR_ALIAS 0x40005086u +#define CYDEV_IO_DR_PRT12_BASE 0x4000508cu +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_DR_ALIAS 0x4000508cu +#define CYDEV_IO_DR_PRT15_BASE 0x4000508fu +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_DR_15_ALIAS 0x4000508fu +#define CYDEV_IO_PS_BASE 0x40005090u +#define CYDEV_IO_PS_SIZE 0x00000010u +#define CYDEV_IO_PS_PRT0_BASE 0x40005090u +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001u +#define CYREG_PRT0_PS_ALIAS 0x40005090u +#define CYDEV_IO_PS_PRT1_BASE 0x40005091u +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001u +#define CYREG_PRT1_PS_ALIAS 0x40005091u +#define CYDEV_IO_PS_PRT2_BASE 0x40005092u +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001u +#define CYREG_PRT2_PS_ALIAS 0x40005092u +#define CYDEV_IO_PS_PRT3_BASE 0x40005093u +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001u +#define CYREG_PRT3_PS_ALIAS 0x40005093u +#define CYDEV_IO_PS_PRT4_BASE 0x40005094u +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001u +#define CYREG_PRT4_PS_ALIAS 0x40005094u +#define CYDEV_IO_PS_PRT5_BASE 0x40005095u +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001u +#define CYREG_PRT5_PS_ALIAS 0x40005095u +#define CYDEV_IO_PS_PRT6_BASE 0x40005096u +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001u +#define CYREG_PRT6_PS_ALIAS 0x40005096u +#define CYDEV_IO_PS_PRT12_BASE 0x4000509cu +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001u +#define CYREG_PRT12_PS_ALIAS 0x4000509cu +#define CYDEV_IO_PS_PRT15_BASE 0x4000509fu +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001u +#define CYREG_PRT15_PS15_ALIAS 0x4000509fu +#define CYDEV_IO_PRT_BASE 0x40005100u +#define CYDEV_IO_PRT_SIZE 0x00000100u +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100u +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010u +#define CYREG_PRT0_DR 0x40005100u +#define CYREG_PRT0_PS 0x40005101u +#define CYREG_PRT0_DM0 0x40005102u +#define CYREG_PRT0_DM1 0x40005103u +#define CYREG_PRT0_DM2 0x40005104u +#define CYREG_PRT0_SLW 0x40005105u +#define CYREG_PRT0_BYP 0x40005106u +#define CYREG_PRT0_BIE 0x40005107u +#define CYREG_PRT0_INP_DIS 0x40005108u +#define CYREG_PRT0_CTL 0x40005109u +#define CYREG_PRT0_PRT 0x4000510au +#define CYREG_PRT0_BIT_MASK 0x4000510bu +#define CYREG_PRT0_AMUX 0x4000510cu +#define CYREG_PRT0_AG 0x4000510du +#define CYREG_PRT0_LCD_COM_SEG 0x4000510eu +#define CYREG_PRT0_LCD_EN 0x4000510fu +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110u +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010u +#define CYREG_PRT1_DR 0x40005110u +#define CYREG_PRT1_PS 0x40005111u +#define CYREG_PRT1_DM0 0x40005112u +#define CYREG_PRT1_DM1 0x40005113u +#define CYREG_PRT1_DM2 0x40005114u +#define CYREG_PRT1_SLW 0x40005115u +#define CYREG_PRT1_BYP 0x40005116u +#define CYREG_PRT1_BIE 0x40005117u +#define CYREG_PRT1_INP_DIS 0x40005118u +#define CYREG_PRT1_CTL 0x40005119u +#define CYREG_PRT1_PRT 0x4000511au +#define CYREG_PRT1_BIT_MASK 0x4000511bu +#define CYREG_PRT1_AMUX 0x4000511cu +#define CYREG_PRT1_AG 0x4000511du +#define CYREG_PRT1_LCD_COM_SEG 0x4000511eu +#define CYREG_PRT1_LCD_EN 0x4000511fu +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120u +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010u +#define CYREG_PRT2_DR 0x40005120u +#define CYREG_PRT2_PS 0x40005121u +#define CYREG_PRT2_DM0 0x40005122u +#define CYREG_PRT2_DM1 0x40005123u +#define CYREG_PRT2_DM2 0x40005124u +#define CYREG_PRT2_SLW 0x40005125u +#define CYREG_PRT2_BYP 0x40005126u +#define CYREG_PRT2_BIE 0x40005127u +#define CYREG_PRT2_INP_DIS 0x40005128u +#define CYREG_PRT2_CTL 0x40005129u +#define CYREG_PRT2_PRT 0x4000512au +#define CYREG_PRT2_BIT_MASK 0x4000512bu +#define CYREG_PRT2_AMUX 0x4000512cu +#define CYREG_PRT2_AG 0x4000512du +#define CYREG_PRT2_LCD_COM_SEG 0x4000512eu +#define CYREG_PRT2_LCD_EN 0x4000512fu +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130u +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010u +#define CYREG_PRT3_DR 0x40005130u +#define CYREG_PRT3_PS 0x40005131u +#define CYREG_PRT3_DM0 0x40005132u +#define CYREG_PRT3_DM1 0x40005133u +#define CYREG_PRT3_DM2 0x40005134u +#define CYREG_PRT3_SLW 0x40005135u +#define CYREG_PRT3_BYP 0x40005136u +#define CYREG_PRT3_BIE 0x40005137u +#define CYREG_PRT3_INP_DIS 0x40005138u +#define CYREG_PRT3_CTL 0x40005139u +#define CYREG_PRT3_PRT 0x4000513au +#define CYREG_PRT3_BIT_MASK 0x4000513bu +#define CYREG_PRT3_AMUX 0x4000513cu +#define CYREG_PRT3_AG 0x4000513du +#define CYREG_PRT3_LCD_COM_SEG 0x4000513eu +#define CYREG_PRT3_LCD_EN 0x4000513fu +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140u +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010u +#define CYREG_PRT4_DR 0x40005140u +#define CYREG_PRT4_PS 0x40005141u +#define CYREG_PRT4_DM0 0x40005142u +#define CYREG_PRT4_DM1 0x40005143u +#define CYREG_PRT4_DM2 0x40005144u +#define CYREG_PRT4_SLW 0x40005145u +#define CYREG_PRT4_BYP 0x40005146u +#define CYREG_PRT4_BIE 0x40005147u +#define CYREG_PRT4_INP_DIS 0x40005148u +#define CYREG_PRT4_CTL 0x40005149u +#define CYREG_PRT4_PRT 0x4000514au +#define CYREG_PRT4_BIT_MASK 0x4000514bu +#define CYREG_PRT4_AMUX 0x4000514cu +#define CYREG_PRT4_AG 0x4000514du +#define CYREG_PRT4_LCD_COM_SEG 0x4000514eu +#define CYREG_PRT4_LCD_EN 0x4000514fu +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150u +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010u +#define CYREG_PRT5_DR 0x40005150u +#define CYREG_PRT5_PS 0x40005151u +#define CYREG_PRT5_DM0 0x40005152u +#define CYREG_PRT5_DM1 0x40005153u +#define CYREG_PRT5_DM2 0x40005154u +#define CYREG_PRT5_SLW 0x40005155u +#define CYREG_PRT5_BYP 0x40005156u +#define CYREG_PRT5_BIE 0x40005157u +#define CYREG_PRT5_INP_DIS 0x40005158u +#define CYREG_PRT5_CTL 0x40005159u +#define CYREG_PRT5_PRT 0x4000515au +#define CYREG_PRT5_BIT_MASK 0x4000515bu +#define CYREG_PRT5_AMUX 0x4000515cu +#define CYREG_PRT5_AG 0x4000515du +#define CYREG_PRT5_LCD_COM_SEG 0x4000515eu +#define CYREG_PRT5_LCD_EN 0x4000515fu +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160u +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010u +#define CYREG_PRT6_DR 0x40005160u +#define CYREG_PRT6_PS 0x40005161u +#define CYREG_PRT6_DM0 0x40005162u +#define CYREG_PRT6_DM1 0x40005163u +#define CYREG_PRT6_DM2 0x40005164u +#define CYREG_PRT6_SLW 0x40005165u +#define CYREG_PRT6_BYP 0x40005166u +#define CYREG_PRT6_BIE 0x40005167u +#define CYREG_PRT6_INP_DIS 0x40005168u +#define CYREG_PRT6_CTL 0x40005169u +#define CYREG_PRT6_PRT 0x4000516au +#define CYREG_PRT6_BIT_MASK 0x4000516bu +#define CYREG_PRT6_AMUX 0x4000516cu +#define CYREG_PRT6_AG 0x4000516du +#define CYREG_PRT6_LCD_COM_SEG 0x4000516eu +#define CYREG_PRT6_LCD_EN 0x4000516fu +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0u +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010u +#define CYREG_PRT12_DR 0x400051c0u +#define CYREG_PRT12_PS 0x400051c1u +#define CYREG_PRT12_DM0 0x400051c2u +#define CYREG_PRT12_DM1 0x400051c3u +#define CYREG_PRT12_DM2 0x400051c4u +#define CYREG_PRT12_SLW 0x400051c5u +#define CYREG_PRT12_BYP 0x400051c6u +#define CYREG_PRT12_BIE 0x400051c7u +#define CYREG_PRT12_INP_DIS 0x400051c8u +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9u +#define CYREG_PRT12_PRT 0x400051cau +#define CYREG_PRT12_BIT_MASK 0x400051cbu +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051ccu +#define CYREG_PRT12_AG 0x400051cdu +#define CYREG_PRT12_SIO_CFG 0x400051ceu +#define CYREG_PRT12_SIO_DIFF 0x400051cfu +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0u +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010u +#define CYREG_PRT15_DR 0x400051f0u +#define CYREG_PRT15_PS 0x400051f1u +#define CYREG_PRT15_DM0 0x400051f2u +#define CYREG_PRT15_DM1 0x400051f3u +#define CYREG_PRT15_DM2 0x400051f4u +#define CYREG_PRT15_SLW 0x400051f5u +#define CYREG_PRT15_BYP 0x400051f6u +#define CYREG_PRT15_BIE 0x400051f7u +#define CYREG_PRT15_INP_DIS 0x400051f8u +#define CYREG_PRT15_CTL 0x400051f9u +#define CYREG_PRT15_PRT 0x400051fau +#define CYREG_PRT15_BIT_MASK 0x400051fbu +#define CYREG_PRT15_AMUX 0x400051fcu +#define CYREG_PRT15_AG 0x400051fdu +#define CYREG_PRT15_LCD_COM_SEG 0x400051feu +#define CYREG_PRT15_LCD_EN 0x400051ffu +#define CYDEV_PRTDSI_BASE 0x40005200u +#define CYDEV_PRTDSI_SIZE 0x0000007fu +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200u +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007u +#define CYREG_PRT0_OUT_SEL0 0x40005200u +#define CYREG_PRT0_OUT_SEL1 0x40005201u +#define CYREG_PRT0_OE_SEL0 0x40005202u +#define CYREG_PRT0_OE_SEL1 0x40005203u +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204u +#define CYREG_PRT0_SYNC_OUT 0x40005205u +#define CYREG_PRT0_CAPS_SEL 0x40005206u +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208u +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007u +#define CYREG_PRT1_OUT_SEL0 0x40005208u +#define CYREG_PRT1_OUT_SEL1 0x40005209u +#define CYREG_PRT1_OE_SEL0 0x4000520au +#define CYREG_PRT1_OE_SEL1 0x4000520bu +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520cu +#define CYREG_PRT1_SYNC_OUT 0x4000520du +#define CYREG_PRT1_CAPS_SEL 0x4000520eu +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210u +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007u +#define CYREG_PRT2_OUT_SEL0 0x40005210u +#define CYREG_PRT2_OUT_SEL1 0x40005211u +#define CYREG_PRT2_OE_SEL0 0x40005212u +#define CYREG_PRT2_OE_SEL1 0x40005213u +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214u +#define CYREG_PRT2_SYNC_OUT 0x40005215u +#define CYREG_PRT2_CAPS_SEL 0x40005216u +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218u +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007u +#define CYREG_PRT3_OUT_SEL0 0x40005218u +#define CYREG_PRT3_OUT_SEL1 0x40005219u +#define CYREG_PRT3_OE_SEL0 0x4000521au +#define CYREG_PRT3_OE_SEL1 0x4000521bu +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521cu +#define CYREG_PRT3_SYNC_OUT 0x4000521du +#define CYREG_PRT3_CAPS_SEL 0x4000521eu +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220u +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007u +#define CYREG_PRT4_OUT_SEL0 0x40005220u +#define CYREG_PRT4_OUT_SEL1 0x40005221u +#define CYREG_PRT4_OE_SEL0 0x40005222u +#define CYREG_PRT4_OE_SEL1 0x40005223u +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224u +#define CYREG_PRT4_SYNC_OUT 0x40005225u +#define CYREG_PRT4_CAPS_SEL 0x40005226u +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228u +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007u +#define CYREG_PRT5_OUT_SEL0 0x40005228u +#define CYREG_PRT5_OUT_SEL1 0x40005229u +#define CYREG_PRT5_OE_SEL0 0x4000522au +#define CYREG_PRT5_OE_SEL1 0x4000522bu +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522cu +#define CYREG_PRT5_SYNC_OUT 0x4000522du +#define CYREG_PRT5_CAPS_SEL 0x4000522eu +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230u +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007u +#define CYREG_PRT6_OUT_SEL0 0x40005230u +#define CYREG_PRT6_OUT_SEL1 0x40005231u +#define CYREG_PRT6_OE_SEL0 0x40005232u +#define CYREG_PRT6_OE_SEL1 0x40005233u +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234u +#define CYREG_PRT6_SYNC_OUT 0x40005235u +#define CYREG_PRT6_CAPS_SEL 0x40005236u +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260u +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006u +#define CYREG_PRT12_OUT_SEL0 0x40005260u +#define CYREG_PRT12_OUT_SEL1 0x40005261u +#define CYREG_PRT12_OE_SEL0 0x40005262u +#define CYREG_PRT12_OE_SEL1 0x40005263u +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264u +#define CYREG_PRT12_SYNC_OUT 0x40005265u +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278u +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007u +#define CYREG_PRT15_OUT_SEL0 0x40005278u +#define CYREG_PRT15_OUT_SEL1 0x40005279u +#define CYREG_PRT15_OE_SEL0 0x4000527au +#define CYREG_PRT15_OE_SEL1 0x4000527bu +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527cu +#define CYREG_PRT15_SYNC_OUT 0x4000527du +#define CYREG_PRT15_CAPS_SEL 0x4000527eu +#define CYDEV_EMIF_BASE 0x40005400u +#define CYDEV_EMIF_SIZE 0x00000007u +#define CYREG_EMIF_NO_UDB 0x40005400u +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401u +#define CYREG_EMIF_MEM_DWN 0x40005402u +#define CYREG_EMIF_MEMCLK_DIV 0x40005403u +#define CYREG_EMIF_CLOCK_EN 0x40005404u +#define CYREG_EMIF_EM_TYPE 0x40005405u +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406u +#define CYDEV_ANAIF_BASE 0x40005800u +#define CYDEV_ANAIF_SIZE 0x000003a9u +#define CYDEV_ANAIF_CFG_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SIZE 0x0000010fu +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800u +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003u +#define CYREG_SC0_CR0 0x40005800u +#define CYREG_SC0_CR1 0x40005801u +#define CYREG_SC0_CR2 0x40005802u +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804u +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003u +#define CYREG_SC1_CR0 0x40005804u +#define CYREG_SC1_CR1 0x40005805u +#define CYREG_SC1_CR2 0x40005806u +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808u +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003u +#define CYREG_SC2_CR0 0x40005808u +#define CYREG_SC2_CR1 0x40005809u +#define CYREG_SC2_CR2 0x4000580au +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580cu +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003u +#define CYREG_SC3_CR0 0x4000580cu +#define CYREG_SC3_CR1 0x4000580du +#define CYREG_SC3_CR2 0x4000580eu +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820u +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003u +#define CYREG_DAC0_CR0 0x40005820u +#define CYREG_DAC0_CR1 0x40005821u +#define CYREG_DAC0_TST 0x40005822u +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824u +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003u +#define CYREG_DAC1_CR0 0x40005824u +#define CYREG_DAC1_CR1 0x40005825u +#define CYREG_DAC1_TST 0x40005826u +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828u +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003u +#define CYREG_DAC2_CR0 0x40005828u +#define CYREG_DAC2_CR1 0x40005829u +#define CYREG_DAC2_TST 0x4000582au +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582cu +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003u +#define CYREG_DAC3_CR0 0x4000582cu +#define CYREG_DAC3_CR1 0x4000582du +#define CYREG_DAC3_TST 0x4000582eu +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840u +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001u +#define CYREG_CMP0_CR 0x40005840u +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841u +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001u +#define CYREG_CMP1_CR 0x40005841u +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842u +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001u +#define CYREG_CMP2_CR 0x40005842u +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843u +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001u +#define CYREG_CMP3_CR 0x40005843u +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848u +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002u +#define CYREG_LUT0_CR 0x40005848u +#define CYREG_LUT0_MX 0x40005849u +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584au +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002u +#define CYREG_LUT1_CR 0x4000584au +#define CYREG_LUT1_MX 0x4000584bu +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584cu +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002u +#define CYREG_LUT2_CR 0x4000584cu +#define CYREG_LUT2_MX 0x4000584du +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584eu +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002u +#define CYREG_LUT3_CR 0x4000584eu +#define CYREG_LUT3_MX 0x4000584fu +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858u +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_CR 0x40005858u +#define CYREG_OPAMP0_RSVD 0x40005859u +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585au +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_CR 0x4000585au +#define CYREG_OPAMP1_RSVD 0x4000585bu +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585cu +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_CR 0x4000585cu +#define CYREG_OPAMP2_RSVD 0x4000585du +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585eu +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_CR 0x4000585eu +#define CYREG_OPAMP3_RSVD 0x4000585fu +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868u +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002u +#define CYREG_LCDDAC_CR0 0x40005868u +#define CYREG_LCDDAC_CR1 0x40005869u +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586au +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001u +#define CYREG_LCDDRV_CR 0x4000586au +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586bu +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001u +#define CYREG_LCDTMR_CFG 0x4000586bu +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586cu +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004u +#define CYREG_BG_CR0 0x4000586cu +#define CYREG_BG_RSVD 0x4000586du +#define CYREG_BG_DFT0 0x4000586eu +#define CYREG_BG_DFT1 0x4000586fu +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870u +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002u +#define CYREG_CAPSL_CFG0 0x40005870u +#define CYREG_CAPSL_CFG1 0x40005871u +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872u +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002u +#define CYREG_CAPSR_CFG0 0x40005872u +#define CYREG_CAPSR_CFG1 0x40005873u +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876u +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002u +#define CYREG_PUMP_CR0 0x40005876u +#define CYREG_PUMP_CR1 0x40005877u +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878u +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002u +#define CYREG_LPF0_CR0 0x40005878u +#define CYREG_LPF0_RSVD 0x40005879u +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587au +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002u +#define CYREG_LPF1_CR0 0x4000587au +#define CYREG_LPF1_RSVD 0x4000587bu +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587cu +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001u +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587cu +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880u +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020u +#define CYREG_DSM0_CR0 0x40005880u +#define CYREG_DSM0_CR1 0x40005881u +#define CYREG_DSM0_CR2 0x40005882u +#define CYREG_DSM0_CR3 0x40005883u +#define CYREG_DSM0_CR4 0x40005884u +#define CYREG_DSM0_CR5 0x40005885u +#define CYREG_DSM0_CR6 0x40005886u +#define CYREG_DSM0_CR7 0x40005887u +#define CYREG_DSM0_CR8 0x40005888u +#define CYREG_DSM0_CR9 0x40005889u +#define CYREG_DSM0_CR10 0x4000588au +#define CYREG_DSM0_CR11 0x4000588bu +#define CYREG_DSM0_CR12 0x4000588cu +#define CYREG_DSM0_CR13 0x4000588du +#define CYREG_DSM0_CR14 0x4000588eu +#define CYREG_DSM0_CR15 0x4000588fu +#define CYREG_DSM0_CR16 0x40005890u +#define CYREG_DSM0_CR17 0x40005891u +#define CYREG_DSM0_REF0 0x40005892u +#define CYREG_DSM0_REF1 0x40005893u +#define CYREG_DSM0_REF2 0x40005894u +#define CYREG_DSM0_REF3 0x40005895u +#define CYREG_DSM0_DEM0 0x40005896u +#define CYREG_DSM0_DEM1 0x40005897u +#define CYREG_DSM0_TST0 0x40005898u +#define CYREG_DSM0_TST1 0x40005899u +#define CYREG_DSM0_BUF0 0x4000589au +#define CYREG_DSM0_BUF1 0x4000589bu +#define CYREG_DSM0_BUF2 0x4000589cu +#define CYREG_DSM0_BUF3 0x4000589du +#define CYREG_DSM0_MISC 0x4000589eu +#define CYREG_DSM0_RSVD1 0x4000589fu +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900u +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007u +#define CYREG_SAR0_CSR0 0x40005900u +#define CYREG_SAR0_CSR1 0x40005901u +#define CYREG_SAR0_CSR2 0x40005902u +#define CYREG_SAR0_CSR3 0x40005903u +#define CYREG_SAR0_CSR4 0x40005904u +#define CYREG_SAR0_CSR5 0x40005905u +#define CYREG_SAR0_CSR6 0x40005906u +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908u +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007u +#define CYREG_SAR1_CSR0 0x40005908u +#define CYREG_SAR1_CSR1 0x40005909u +#define CYREG_SAR1_CSR2 0x4000590au +#define CYREG_SAR1_CSR3 0x4000590bu +#define CYREG_SAR1_CSR4 0x4000590cu +#define CYREG_SAR1_CSR5 0x4000590du +#define CYREG_SAR1_CSR6 0x4000590eu +#define CYDEV_ANAIF_RT_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SIZE 0x00000162u +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00u +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000du +#define CYREG_SC0_SW0 0x40005a00u +#define CYREG_SC0_SW2 0x40005a02u +#define CYREG_SC0_SW3 0x40005a03u +#define CYREG_SC0_SW4 0x40005a04u +#define CYREG_SC0_SW6 0x40005a06u +#define CYREG_SC0_SW7 0x40005a07u +#define CYREG_SC0_SW8 0x40005a08u +#define CYREG_SC0_SW10 0x40005a0au +#define CYREG_SC0_CLK 0x40005a0bu +#define CYREG_SC0_BST 0x40005a0cu +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10u +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000du +#define CYREG_SC1_SW0 0x40005a10u +#define CYREG_SC1_SW2 0x40005a12u +#define CYREG_SC1_SW3 0x40005a13u +#define CYREG_SC1_SW4 0x40005a14u +#define CYREG_SC1_SW6 0x40005a16u +#define CYREG_SC1_SW7 0x40005a17u +#define CYREG_SC1_SW8 0x40005a18u +#define CYREG_SC1_SW10 0x40005a1au +#define CYREG_SC1_CLK 0x40005a1bu +#define CYREG_SC1_BST 0x40005a1cu +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20u +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000du +#define CYREG_SC2_SW0 0x40005a20u +#define CYREG_SC2_SW2 0x40005a22u +#define CYREG_SC2_SW3 0x40005a23u +#define CYREG_SC2_SW4 0x40005a24u +#define CYREG_SC2_SW6 0x40005a26u +#define CYREG_SC2_SW7 0x40005a27u +#define CYREG_SC2_SW8 0x40005a28u +#define CYREG_SC2_SW10 0x40005a2au +#define CYREG_SC2_CLK 0x40005a2bu +#define CYREG_SC2_BST 0x40005a2cu +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30u +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000du +#define CYREG_SC3_SW0 0x40005a30u +#define CYREG_SC3_SW2 0x40005a32u +#define CYREG_SC3_SW3 0x40005a33u +#define CYREG_SC3_SW4 0x40005a34u +#define CYREG_SC3_SW6 0x40005a36u +#define CYREG_SC3_SW7 0x40005a37u +#define CYREG_SC3_SW8 0x40005a38u +#define CYREG_SC3_SW10 0x40005a3au +#define CYREG_SC3_CLK 0x40005a3bu +#define CYREG_SC3_BST 0x40005a3cu +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80u +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008u +#define CYREG_DAC0_SW0 0x40005a80u +#define CYREG_DAC0_SW2 0x40005a82u +#define CYREG_DAC0_SW3 0x40005a83u +#define CYREG_DAC0_SW4 0x40005a84u +#define CYREG_DAC0_STROBE 0x40005a87u +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88u +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008u +#define CYREG_DAC1_SW0 0x40005a88u +#define CYREG_DAC1_SW2 0x40005a8au +#define CYREG_DAC1_SW3 0x40005a8bu +#define CYREG_DAC1_SW4 0x40005a8cu +#define CYREG_DAC1_STROBE 0x40005a8fu +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90u +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008u +#define CYREG_DAC2_SW0 0x40005a90u +#define CYREG_DAC2_SW2 0x40005a92u +#define CYREG_DAC2_SW3 0x40005a93u +#define CYREG_DAC2_SW4 0x40005a94u +#define CYREG_DAC2_STROBE 0x40005a97u +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98u +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008u +#define CYREG_DAC3_SW0 0x40005a98u +#define CYREG_DAC3_SW2 0x40005a9au +#define CYREG_DAC3_SW3 0x40005a9bu +#define CYREG_DAC3_SW4 0x40005a9cu +#define CYREG_DAC3_STROBE 0x40005a9fu +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0u +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008u +#define CYREG_CMP0_SW0 0x40005ac0u +#define CYREG_CMP0_SW2 0x40005ac2u +#define CYREG_CMP0_SW3 0x40005ac3u +#define CYREG_CMP0_SW4 0x40005ac4u +#define CYREG_CMP0_SW6 0x40005ac6u +#define CYREG_CMP0_CLK 0x40005ac7u +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8u +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008u +#define CYREG_CMP1_SW0 0x40005ac8u +#define CYREG_CMP1_SW2 0x40005acau +#define CYREG_CMP1_SW3 0x40005acbu +#define CYREG_CMP1_SW4 0x40005accu +#define CYREG_CMP1_SW6 0x40005aceu +#define CYREG_CMP1_CLK 0x40005acfu +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0u +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008u +#define CYREG_CMP2_SW0 0x40005ad0u +#define CYREG_CMP2_SW2 0x40005ad2u +#define CYREG_CMP2_SW3 0x40005ad3u +#define CYREG_CMP2_SW4 0x40005ad4u +#define CYREG_CMP2_SW6 0x40005ad6u +#define CYREG_CMP2_CLK 0x40005ad7u +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8u +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008u +#define CYREG_CMP3_SW0 0x40005ad8u +#define CYREG_CMP3_SW2 0x40005adau +#define CYREG_CMP3_SW3 0x40005adbu +#define CYREG_CMP3_SW4 0x40005adcu +#define CYREG_CMP3_SW6 0x40005adeu +#define CYREG_CMP3_CLK 0x40005adfu +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00u +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008u +#define CYREG_DSM0_SW0 0x40005b00u +#define CYREG_DSM0_SW2 0x40005b02u +#define CYREG_DSM0_SW3 0x40005b03u +#define CYREG_DSM0_SW4 0x40005b04u +#define CYREG_DSM0_SW6 0x40005b06u +#define CYREG_DSM0_CLK 0x40005b07u +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20u +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008u +#define CYREG_SAR0_SW0 0x40005b20u +#define CYREG_SAR0_SW2 0x40005b22u +#define CYREG_SAR0_SW3 0x40005b23u +#define CYREG_SAR0_SW4 0x40005b24u +#define CYREG_SAR0_SW6 0x40005b26u +#define CYREG_SAR0_CLK 0x40005b27u +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28u +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008u +#define CYREG_SAR1_SW0 0x40005b28u +#define CYREG_SAR1_SW2 0x40005b2au +#define CYREG_SAR1_SW3 0x40005b2bu +#define CYREG_SAR1_SW4 0x40005b2cu +#define CYREG_SAR1_SW6 0x40005b2eu +#define CYREG_SAR1_CLK 0x40005b2fu +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40u +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002u +#define CYREG_OPAMP0_MX 0x40005b40u +#define CYREG_OPAMP0_SW 0x40005b41u +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42u +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002u +#define CYREG_OPAMP1_MX 0x40005b42u +#define CYREG_OPAMP1_SW 0x40005b43u +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44u +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002u +#define CYREG_OPAMP2_MX 0x40005b44u +#define CYREG_OPAMP2_SW 0x40005b45u +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46u +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002u +#define CYREG_OPAMP3_MX 0x40005b46u +#define CYREG_OPAMP3_SW 0x40005b47u +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50u +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005u +#define CYREG_LCDDAC_SW0 0x40005b50u +#define CYREG_LCDDAC_SW1 0x40005b51u +#define CYREG_LCDDAC_SW2 0x40005b52u +#define CYREG_LCDDAC_SW3 0x40005b53u +#define CYREG_LCDDAC_SW4 0x40005b54u +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56u +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001u +#define CYREG_SC_MISC 0x40005b56u +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58u +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004u +#define CYREG_BUS_SW0 0x40005b58u +#define CYREG_BUS_SW2 0x40005b5au +#define CYREG_BUS_SW3 0x40005b5bu +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5cu +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006u +#define CYREG_DFT_CR0 0x40005b5cu +#define CYREG_DFT_CR1 0x40005b5du +#define CYREG_DFT_CR2 0x40005b5eu +#define CYREG_DFT_CR3 0x40005b5fu +#define CYREG_DFT_CR4 0x40005b60u +#define CYREG_DFT_CR5 0x40005b61u +#define CYDEV_ANAIF_WRK_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_SIZE 0x00000029u +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001u +#define CYREG_DAC0_D 0x40005b80u +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001u +#define CYREG_DAC1_D 0x40005b81u +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001u +#define CYREG_DAC2_D 0x40005b82u +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83u +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001u +#define CYREG_DAC3_D 0x40005b83u +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88u +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002u +#define CYREG_DSM0_OUT0 0x40005b88u +#define CYREG_DSM0_OUT1 0x40005b89u +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90u +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005u +#define CYREG_LUT_SR 0x40005b90u +#define CYREG_LUT_WRK1 0x40005b91u +#define CYREG_LUT_MSK 0x40005b92u +#define CYREG_LUT_CLK 0x40005b93u +#define CYREG_LUT_CPTR 0x40005b94u +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96u +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002u +#define CYREG_CMP_WRK 0x40005b96u +#define CYREG_CMP_TST 0x40005b97u +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98u +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005u +#define CYREG_SC_SR 0x40005b98u +#define CYREG_SC_WRK1 0x40005b99u +#define CYREG_SC_MSK 0x40005b9au +#define CYREG_SC_CMPINV 0x40005b9bu +#define CYREG_SC_CPTR 0x40005b9cu +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0u +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002u +#define CYREG_SAR0_WRK0 0x40005ba0u +#define CYREG_SAR0_WRK1 0x40005ba1u +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2u +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002u +#define CYREG_SAR1_WRK0 0x40005ba2u +#define CYREG_SAR1_WRK1 0x40005ba3u +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8u +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001u +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8u +#define CYDEV_USB_BASE 0x40006000u +#define CYDEV_USB_SIZE 0x00000300u +#define CYREG_USB_EP0_DR0 0x40006000u +#define CYREG_USB_EP0_DR1 0x40006001u +#define CYREG_USB_EP0_DR2 0x40006002u +#define CYREG_USB_EP0_DR3 0x40006003u +#define CYREG_USB_EP0_DR4 0x40006004u +#define CYREG_USB_EP0_DR5 0x40006005u +#define CYREG_USB_EP0_DR6 0x40006006u +#define CYREG_USB_EP0_DR7 0x40006007u +#define CYREG_USB_CR0 0x40006008u +#define CYREG_USB_CR1 0x40006009u +#define CYREG_USB_SIE_EP_INT_EN 0x4000600au +#define CYREG_USB_SIE_EP_INT_SR 0x4000600bu +#define CYDEV_USB_SIE_EP1_BASE 0x4000600cu +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003u +#define CYREG_USB_SIE_EP1_CNT0 0x4000600cu +#define CYREG_USB_SIE_EP1_CNT1 0x4000600du +#define CYREG_USB_SIE_EP1_CR0 0x4000600eu +#define CYREG_USB_USBIO_CR0 0x40006010u +#define CYREG_USB_USBIO_CR1 0x40006012u +#define CYREG_USB_DYN_RECONFIG 0x40006014u +#define CYREG_USB_SOF0 0x40006018u +#define CYREG_USB_SOF1 0x40006019u +#define CYDEV_USB_SIE_EP2_BASE 0x4000601cu +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003u +#define CYREG_USB_SIE_EP2_CNT0 0x4000601cu +#define CYREG_USB_SIE_EP2_CNT1 0x4000601du +#define CYREG_USB_SIE_EP2_CR0 0x4000601eu +#define CYREG_USB_EP0_CR 0x40006028u +#define CYREG_USB_EP0_CNT 0x40006029u +#define CYDEV_USB_SIE_EP3_BASE 0x4000602cu +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003u +#define CYREG_USB_SIE_EP3_CNT0 0x4000602cu +#define CYREG_USB_SIE_EP3_CNT1 0x4000602du +#define CYREG_USB_SIE_EP3_CR0 0x4000602eu +#define CYDEV_USB_SIE_EP4_BASE 0x4000603cu +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003u +#define CYREG_USB_SIE_EP4_CNT0 0x4000603cu +#define CYREG_USB_SIE_EP4_CNT1 0x4000603du +#define CYREG_USB_SIE_EP4_CR0 0x4000603eu +#define CYDEV_USB_SIE_EP5_BASE 0x4000604cu +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003u +#define CYREG_USB_SIE_EP5_CNT0 0x4000604cu +#define CYREG_USB_SIE_EP5_CNT1 0x4000604du +#define CYREG_USB_SIE_EP5_CR0 0x4000604eu +#define CYDEV_USB_SIE_EP6_BASE 0x4000605cu +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003u +#define CYREG_USB_SIE_EP6_CNT0 0x4000605cu +#define CYREG_USB_SIE_EP6_CNT1 0x4000605du +#define CYREG_USB_SIE_EP6_CR0 0x4000605eu +#define CYDEV_USB_SIE_EP7_BASE 0x4000606cu +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003u +#define CYREG_USB_SIE_EP7_CNT0 0x4000606cu +#define CYREG_USB_SIE_EP7_CNT1 0x4000606du +#define CYREG_USB_SIE_EP7_CR0 0x4000606eu +#define CYDEV_USB_SIE_EP8_BASE 0x4000607cu +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003u +#define CYREG_USB_SIE_EP8_CNT0 0x4000607cu +#define CYREG_USB_SIE_EP8_CNT1 0x4000607du +#define CYREG_USB_SIE_EP8_CR0 0x4000607eu +#define CYDEV_USB_ARB_EP1_BASE 0x40006080u +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003u +#define CYREG_USB_ARB_EP1_CFG 0x40006080u +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081u +#define CYREG_USB_ARB_EP1_SR 0x40006082u +#define CYDEV_USB_ARB_RW1_BASE 0x40006084u +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005u +#define CYREG_USB_ARB_RW1_WA 0x40006084u +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085u +#define CYREG_USB_ARB_RW1_RA 0x40006086u +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087u +#define CYREG_USB_ARB_RW1_DR 0x40006088u +#define CYREG_USB_BUF_SIZE 0x4000608cu +#define CYREG_USB_EP_ACTIVE 0x4000608eu +#define CYREG_USB_EP_TYPE 0x4000608fu +#define CYDEV_USB_ARB_EP2_BASE 0x40006090u +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003u +#define CYREG_USB_ARB_EP2_CFG 0x40006090u +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091u +#define CYREG_USB_ARB_EP2_SR 0x40006092u +#define CYDEV_USB_ARB_RW2_BASE 0x40006094u +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005u +#define CYREG_USB_ARB_RW2_WA 0x40006094u +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095u +#define CYREG_USB_ARB_RW2_RA 0x40006096u +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097u +#define CYREG_USB_ARB_RW2_DR 0x40006098u +#define CYREG_USB_ARB_CFG 0x4000609cu +#define CYREG_USB_USB_CLK_EN 0x4000609du +#define CYREG_USB_ARB_INT_EN 0x4000609eu +#define CYREG_USB_ARB_INT_SR 0x4000609fu +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0u +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003u +#define CYREG_USB_ARB_EP3_CFG 0x400060a0u +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1u +#define CYREG_USB_ARB_EP3_SR 0x400060a2u +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4u +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005u +#define CYREG_USB_ARB_RW3_WA 0x400060a4u +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5u +#define CYREG_USB_ARB_RW3_RA 0x400060a6u +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7u +#define CYREG_USB_ARB_RW3_DR 0x400060a8u +#define CYREG_USB_CWA 0x400060acu +#define CYREG_USB_CWA_MSB 0x400060adu +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0u +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003u +#define CYREG_USB_ARB_EP4_CFG 0x400060b0u +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1u +#define CYREG_USB_ARB_EP4_SR 0x400060b2u +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4u +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005u +#define CYREG_USB_ARB_RW4_WA 0x400060b4u +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5u +#define CYREG_USB_ARB_RW4_RA 0x400060b6u +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7u +#define CYREG_USB_ARB_RW4_DR 0x400060b8u +#define CYREG_USB_DMA_THRES 0x400060bcu +#define CYREG_USB_DMA_THRES_MSB 0x400060bdu +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0u +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003u +#define CYREG_USB_ARB_EP5_CFG 0x400060c0u +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1u +#define CYREG_USB_ARB_EP5_SR 0x400060c2u +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4u +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005u +#define CYREG_USB_ARB_RW5_WA 0x400060c4u +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5u +#define CYREG_USB_ARB_RW5_RA 0x400060c6u +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7u +#define CYREG_USB_ARB_RW5_DR 0x400060c8u +#define CYREG_USB_BUS_RST_CNT 0x400060ccu +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0u +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003u +#define CYREG_USB_ARB_EP6_CFG 0x400060d0u +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1u +#define CYREG_USB_ARB_EP6_SR 0x400060d2u +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4u +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005u +#define CYREG_USB_ARB_RW6_WA 0x400060d4u +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5u +#define CYREG_USB_ARB_RW6_RA 0x400060d6u +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7u +#define CYREG_USB_ARB_RW6_DR 0x400060d8u +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0u +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003u +#define CYREG_USB_ARB_EP7_CFG 0x400060e0u +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1u +#define CYREG_USB_ARB_EP7_SR 0x400060e2u +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4u +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005u +#define CYREG_USB_ARB_RW7_WA 0x400060e4u +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5u +#define CYREG_USB_ARB_RW7_RA 0x400060e6u +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7u +#define CYREG_USB_ARB_RW7_DR 0x400060e8u +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0u +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003u +#define CYREG_USB_ARB_EP8_CFG 0x400060f0u +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1u +#define CYREG_USB_ARB_EP8_SR 0x400060f2u +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4u +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005u +#define CYREG_USB_ARB_RW8_WA 0x400060f4u +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5u +#define CYREG_USB_ARB_RW8_RA 0x400060f6u +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7u +#define CYREG_USB_ARB_RW8_DR 0x400060f8u +#define CYDEV_USB_MEM_BASE 0x40006100u +#define CYDEV_USB_MEM_SIZE 0x00000200u +#define CYREG_USB_MEM_DATA_MBASE 0x40006100u +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200u +#define CYDEV_UWRK_BASE 0x40006400u +#define CYDEV_UWRK_SIZE 0x00000b60u +#define CYDEV_UWRK_UWRK8_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0u +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400u +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0u +#define CYREG_B0_UDB00_A0 0x40006400u +#define CYREG_B0_UDB01_A0 0x40006401u +#define CYREG_B0_UDB02_A0 0x40006402u +#define CYREG_B0_UDB03_A0 0x40006403u +#define CYREG_B0_UDB04_A0 0x40006404u +#define CYREG_B0_UDB05_A0 0x40006405u +#define CYREG_B0_UDB06_A0 0x40006406u +#define CYREG_B0_UDB07_A0 0x40006407u +#define CYREG_B0_UDB08_A0 0x40006408u +#define CYREG_B0_UDB09_A0 0x40006409u +#define CYREG_B0_UDB10_A0 0x4000640au +#define CYREG_B0_UDB11_A0 0x4000640bu +#define CYREG_B0_UDB12_A0 0x4000640cu +#define CYREG_B0_UDB13_A0 0x4000640du +#define CYREG_B0_UDB14_A0 0x4000640eu +#define CYREG_B0_UDB15_A0 0x4000640fu +#define CYREG_B0_UDB00_A1 0x40006410u +#define CYREG_B0_UDB01_A1 0x40006411u +#define CYREG_B0_UDB02_A1 0x40006412u +#define CYREG_B0_UDB03_A1 0x40006413u +#define CYREG_B0_UDB04_A1 0x40006414u +#define CYREG_B0_UDB05_A1 0x40006415u +#define CYREG_B0_UDB06_A1 0x40006416u +#define CYREG_B0_UDB07_A1 0x40006417u +#define CYREG_B0_UDB08_A1 0x40006418u +#define CYREG_B0_UDB09_A1 0x40006419u +#define CYREG_B0_UDB10_A1 0x4000641au +#define CYREG_B0_UDB11_A1 0x4000641bu +#define CYREG_B0_UDB12_A1 0x4000641cu +#define CYREG_B0_UDB13_A1 0x4000641du +#define CYREG_B0_UDB14_A1 0x4000641eu +#define CYREG_B0_UDB15_A1 0x4000641fu +#define CYREG_B0_UDB00_D0 0x40006420u +#define CYREG_B0_UDB01_D0 0x40006421u +#define CYREG_B0_UDB02_D0 0x40006422u +#define CYREG_B0_UDB03_D0 0x40006423u +#define CYREG_B0_UDB04_D0 0x40006424u +#define CYREG_B0_UDB05_D0 0x40006425u +#define CYREG_B0_UDB06_D0 0x40006426u +#define CYREG_B0_UDB07_D0 0x40006427u +#define CYREG_B0_UDB08_D0 0x40006428u +#define CYREG_B0_UDB09_D0 0x40006429u +#define CYREG_B0_UDB10_D0 0x4000642au +#define CYREG_B0_UDB11_D0 0x4000642bu +#define CYREG_B0_UDB12_D0 0x4000642cu +#define CYREG_B0_UDB13_D0 0x4000642du +#define CYREG_B0_UDB14_D0 0x4000642eu +#define CYREG_B0_UDB15_D0 0x4000642fu +#define CYREG_B0_UDB00_D1 0x40006430u +#define CYREG_B0_UDB01_D1 0x40006431u +#define CYREG_B0_UDB02_D1 0x40006432u +#define CYREG_B0_UDB03_D1 0x40006433u +#define CYREG_B0_UDB04_D1 0x40006434u +#define CYREG_B0_UDB05_D1 0x40006435u +#define CYREG_B0_UDB06_D1 0x40006436u +#define CYREG_B0_UDB07_D1 0x40006437u +#define CYREG_B0_UDB08_D1 0x40006438u +#define CYREG_B0_UDB09_D1 0x40006439u +#define CYREG_B0_UDB10_D1 0x4000643au +#define CYREG_B0_UDB11_D1 0x4000643bu +#define CYREG_B0_UDB12_D1 0x4000643cu +#define CYREG_B0_UDB13_D1 0x4000643du +#define CYREG_B0_UDB14_D1 0x4000643eu +#define CYREG_B0_UDB15_D1 0x4000643fu +#define CYREG_B0_UDB00_F0 0x40006440u +#define CYREG_B0_UDB01_F0 0x40006441u +#define CYREG_B0_UDB02_F0 0x40006442u +#define CYREG_B0_UDB03_F0 0x40006443u +#define CYREG_B0_UDB04_F0 0x40006444u +#define CYREG_B0_UDB05_F0 0x40006445u +#define CYREG_B0_UDB06_F0 0x40006446u +#define CYREG_B0_UDB07_F0 0x40006447u +#define CYREG_B0_UDB08_F0 0x40006448u +#define CYREG_B0_UDB09_F0 0x40006449u +#define CYREG_B0_UDB10_F0 0x4000644au +#define CYREG_B0_UDB11_F0 0x4000644bu +#define CYREG_B0_UDB12_F0 0x4000644cu +#define CYREG_B0_UDB13_F0 0x4000644du +#define CYREG_B0_UDB14_F0 0x4000644eu +#define CYREG_B0_UDB15_F0 0x4000644fu +#define CYREG_B0_UDB00_F1 0x40006450u +#define CYREG_B0_UDB01_F1 0x40006451u +#define CYREG_B0_UDB02_F1 0x40006452u +#define CYREG_B0_UDB03_F1 0x40006453u +#define CYREG_B0_UDB04_F1 0x40006454u +#define CYREG_B0_UDB05_F1 0x40006455u +#define CYREG_B0_UDB06_F1 0x40006456u +#define CYREG_B0_UDB07_F1 0x40006457u +#define CYREG_B0_UDB08_F1 0x40006458u +#define CYREG_B0_UDB09_F1 0x40006459u +#define CYREG_B0_UDB10_F1 0x4000645au +#define CYREG_B0_UDB11_F1 0x4000645bu +#define CYREG_B0_UDB12_F1 0x4000645cu +#define CYREG_B0_UDB13_F1 0x4000645du +#define CYREG_B0_UDB14_F1 0x4000645eu +#define CYREG_B0_UDB15_F1 0x4000645fu +#define CYREG_B0_UDB00_ST 0x40006460u +#define CYREG_B0_UDB01_ST 0x40006461u +#define CYREG_B0_UDB02_ST 0x40006462u +#define CYREG_B0_UDB03_ST 0x40006463u +#define CYREG_B0_UDB04_ST 0x40006464u +#define CYREG_B0_UDB05_ST 0x40006465u +#define CYREG_B0_UDB06_ST 0x40006466u +#define CYREG_B0_UDB07_ST 0x40006467u +#define CYREG_B0_UDB08_ST 0x40006468u +#define CYREG_B0_UDB09_ST 0x40006469u +#define CYREG_B0_UDB10_ST 0x4000646au +#define CYREG_B0_UDB11_ST 0x4000646bu +#define CYREG_B0_UDB12_ST 0x4000646cu +#define CYREG_B0_UDB13_ST 0x4000646du +#define CYREG_B0_UDB14_ST 0x4000646eu +#define CYREG_B0_UDB15_ST 0x4000646fu +#define CYREG_B0_UDB00_CTL 0x40006470u +#define CYREG_B0_UDB01_CTL 0x40006471u +#define CYREG_B0_UDB02_CTL 0x40006472u +#define CYREG_B0_UDB03_CTL 0x40006473u +#define CYREG_B0_UDB04_CTL 0x40006474u +#define CYREG_B0_UDB05_CTL 0x40006475u +#define CYREG_B0_UDB06_CTL 0x40006476u +#define CYREG_B0_UDB07_CTL 0x40006477u +#define CYREG_B0_UDB08_CTL 0x40006478u +#define CYREG_B0_UDB09_CTL 0x40006479u +#define CYREG_B0_UDB10_CTL 0x4000647au +#define CYREG_B0_UDB11_CTL 0x4000647bu +#define CYREG_B0_UDB12_CTL 0x4000647cu +#define CYREG_B0_UDB13_CTL 0x4000647du +#define CYREG_B0_UDB14_CTL 0x4000647eu +#define CYREG_B0_UDB15_CTL 0x4000647fu +#define CYREG_B0_UDB00_MSK 0x40006480u +#define CYREG_B0_UDB01_MSK 0x40006481u +#define CYREG_B0_UDB02_MSK 0x40006482u +#define CYREG_B0_UDB03_MSK 0x40006483u +#define CYREG_B0_UDB04_MSK 0x40006484u +#define CYREG_B0_UDB05_MSK 0x40006485u +#define CYREG_B0_UDB06_MSK 0x40006486u +#define CYREG_B0_UDB07_MSK 0x40006487u +#define CYREG_B0_UDB08_MSK 0x40006488u +#define CYREG_B0_UDB09_MSK 0x40006489u +#define CYREG_B0_UDB10_MSK 0x4000648au +#define CYREG_B0_UDB11_MSK 0x4000648bu +#define CYREG_B0_UDB12_MSK 0x4000648cu +#define CYREG_B0_UDB13_MSK 0x4000648du +#define CYREG_B0_UDB14_MSK 0x4000648eu +#define CYREG_B0_UDB15_MSK 0x4000648fu +#define CYREG_B0_UDB00_ACTL 0x40006490u +#define CYREG_B0_UDB01_ACTL 0x40006491u +#define CYREG_B0_UDB02_ACTL 0x40006492u +#define CYREG_B0_UDB03_ACTL 0x40006493u +#define CYREG_B0_UDB04_ACTL 0x40006494u +#define CYREG_B0_UDB05_ACTL 0x40006495u +#define CYREG_B0_UDB06_ACTL 0x40006496u +#define CYREG_B0_UDB07_ACTL 0x40006497u +#define CYREG_B0_UDB08_ACTL 0x40006498u +#define CYREG_B0_UDB09_ACTL 0x40006499u +#define CYREG_B0_UDB10_ACTL 0x4000649au +#define CYREG_B0_UDB11_ACTL 0x4000649bu +#define CYREG_B0_UDB12_ACTL 0x4000649cu +#define CYREG_B0_UDB13_ACTL 0x4000649du +#define CYREG_B0_UDB14_ACTL 0x4000649eu +#define CYREG_B0_UDB15_ACTL 0x4000649fu +#define CYREG_B0_UDB00_MC 0x400064a0u +#define CYREG_B0_UDB01_MC 0x400064a1u +#define CYREG_B0_UDB02_MC 0x400064a2u +#define CYREG_B0_UDB03_MC 0x400064a3u +#define CYREG_B0_UDB04_MC 0x400064a4u +#define CYREG_B0_UDB05_MC 0x400064a5u +#define CYREG_B0_UDB06_MC 0x400064a6u +#define CYREG_B0_UDB07_MC 0x400064a7u +#define CYREG_B0_UDB08_MC 0x400064a8u +#define CYREG_B0_UDB09_MC 0x400064a9u +#define CYREG_B0_UDB10_MC 0x400064aau +#define CYREG_B0_UDB11_MC 0x400064abu +#define CYREG_B0_UDB12_MC 0x400064acu +#define CYREG_B0_UDB13_MC 0x400064adu +#define CYREG_B0_UDB14_MC 0x400064aeu +#define CYREG_B0_UDB15_MC 0x400064afu +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500u +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0u +#define CYREG_B1_UDB04_A0 0x40006504u +#define CYREG_B1_UDB05_A0 0x40006505u +#define CYREG_B1_UDB06_A0 0x40006506u +#define CYREG_B1_UDB07_A0 0x40006507u +#define CYREG_B1_UDB08_A0 0x40006508u +#define CYREG_B1_UDB09_A0 0x40006509u +#define CYREG_B1_UDB10_A0 0x4000650au +#define CYREG_B1_UDB11_A0 0x4000650bu +#define CYREG_B1_UDB04_A1 0x40006514u +#define CYREG_B1_UDB05_A1 0x40006515u +#define CYREG_B1_UDB06_A1 0x40006516u +#define CYREG_B1_UDB07_A1 0x40006517u +#define CYREG_B1_UDB08_A1 0x40006518u +#define CYREG_B1_UDB09_A1 0x40006519u +#define CYREG_B1_UDB10_A1 0x4000651au +#define CYREG_B1_UDB11_A1 0x4000651bu +#define CYREG_B1_UDB04_D0 0x40006524u +#define CYREG_B1_UDB05_D0 0x40006525u +#define CYREG_B1_UDB06_D0 0x40006526u +#define CYREG_B1_UDB07_D0 0x40006527u +#define CYREG_B1_UDB08_D0 0x40006528u +#define CYREG_B1_UDB09_D0 0x40006529u +#define CYREG_B1_UDB10_D0 0x4000652au +#define CYREG_B1_UDB11_D0 0x4000652bu +#define CYREG_B1_UDB04_D1 0x40006534u +#define CYREG_B1_UDB05_D1 0x40006535u +#define CYREG_B1_UDB06_D1 0x40006536u +#define CYREG_B1_UDB07_D1 0x40006537u +#define CYREG_B1_UDB08_D1 0x40006538u +#define CYREG_B1_UDB09_D1 0x40006539u +#define CYREG_B1_UDB10_D1 0x4000653au +#define CYREG_B1_UDB11_D1 0x4000653bu +#define CYREG_B1_UDB04_F0 0x40006544u +#define CYREG_B1_UDB05_F0 0x40006545u +#define CYREG_B1_UDB06_F0 0x40006546u +#define CYREG_B1_UDB07_F0 0x40006547u +#define CYREG_B1_UDB08_F0 0x40006548u +#define CYREG_B1_UDB09_F0 0x40006549u +#define CYREG_B1_UDB10_F0 0x4000654au +#define CYREG_B1_UDB11_F0 0x4000654bu +#define CYREG_B1_UDB04_F1 0x40006554u +#define CYREG_B1_UDB05_F1 0x40006555u +#define CYREG_B1_UDB06_F1 0x40006556u +#define CYREG_B1_UDB07_F1 0x40006557u +#define CYREG_B1_UDB08_F1 0x40006558u +#define CYREG_B1_UDB09_F1 0x40006559u +#define CYREG_B1_UDB10_F1 0x4000655au +#define CYREG_B1_UDB11_F1 0x4000655bu +#define CYREG_B1_UDB04_ST 0x40006564u +#define CYREG_B1_UDB05_ST 0x40006565u +#define CYREG_B1_UDB06_ST 0x40006566u +#define CYREG_B1_UDB07_ST 0x40006567u +#define CYREG_B1_UDB08_ST 0x40006568u +#define CYREG_B1_UDB09_ST 0x40006569u +#define CYREG_B1_UDB10_ST 0x4000656au +#define CYREG_B1_UDB11_ST 0x4000656bu +#define CYREG_B1_UDB04_CTL 0x40006574u +#define CYREG_B1_UDB05_CTL 0x40006575u +#define CYREG_B1_UDB06_CTL 0x40006576u +#define CYREG_B1_UDB07_CTL 0x40006577u +#define CYREG_B1_UDB08_CTL 0x40006578u +#define CYREG_B1_UDB09_CTL 0x40006579u +#define CYREG_B1_UDB10_CTL 0x4000657au +#define CYREG_B1_UDB11_CTL 0x4000657bu +#define CYREG_B1_UDB04_MSK 0x40006584u +#define CYREG_B1_UDB05_MSK 0x40006585u +#define CYREG_B1_UDB06_MSK 0x40006586u +#define CYREG_B1_UDB07_MSK 0x40006587u +#define CYREG_B1_UDB08_MSK 0x40006588u +#define CYREG_B1_UDB09_MSK 0x40006589u +#define CYREG_B1_UDB10_MSK 0x4000658au +#define CYREG_B1_UDB11_MSK 0x4000658bu +#define CYREG_B1_UDB04_ACTL 0x40006594u +#define CYREG_B1_UDB05_ACTL 0x40006595u +#define CYREG_B1_UDB06_ACTL 0x40006596u +#define CYREG_B1_UDB07_ACTL 0x40006597u +#define CYREG_B1_UDB08_ACTL 0x40006598u +#define CYREG_B1_UDB09_ACTL 0x40006599u +#define CYREG_B1_UDB10_ACTL 0x4000659au +#define CYREG_B1_UDB11_ACTL 0x4000659bu +#define CYREG_B1_UDB04_MC 0x400065a4u +#define CYREG_B1_UDB05_MC 0x400065a5u +#define CYREG_B1_UDB06_MC 0x400065a6u +#define CYREG_B1_UDB07_MC 0x400065a7u +#define CYREG_B1_UDB08_MC 0x400065a8u +#define CYREG_B1_UDB09_MC 0x400065a9u +#define CYREG_B1_UDB10_MC 0x400065aau +#define CYREG_B1_UDB11_MC 0x400065abu +#define CYDEV_UWRK_UWRK16_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760u +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160u +#define CYREG_B0_UDB00_A0_A1 0x40006800u +#define CYREG_B0_UDB01_A0_A1 0x40006802u +#define CYREG_B0_UDB02_A0_A1 0x40006804u +#define CYREG_B0_UDB03_A0_A1 0x40006806u +#define CYREG_B0_UDB04_A0_A1 0x40006808u +#define CYREG_B0_UDB05_A0_A1 0x4000680au +#define CYREG_B0_UDB06_A0_A1 0x4000680cu +#define CYREG_B0_UDB07_A0_A1 0x4000680eu +#define CYREG_B0_UDB08_A0_A1 0x40006810u +#define CYREG_B0_UDB09_A0_A1 0x40006812u +#define CYREG_B0_UDB10_A0_A1 0x40006814u +#define CYREG_B0_UDB11_A0_A1 0x40006816u +#define CYREG_B0_UDB12_A0_A1 0x40006818u +#define CYREG_B0_UDB13_A0_A1 0x4000681au +#define CYREG_B0_UDB14_A0_A1 0x4000681cu +#define CYREG_B0_UDB15_A0_A1 0x4000681eu +#define CYREG_B0_UDB00_D0_D1 0x40006840u +#define CYREG_B0_UDB01_D0_D1 0x40006842u +#define CYREG_B0_UDB02_D0_D1 0x40006844u +#define CYREG_B0_UDB03_D0_D1 0x40006846u +#define CYREG_B0_UDB04_D0_D1 0x40006848u +#define CYREG_B0_UDB05_D0_D1 0x4000684au +#define CYREG_B0_UDB06_D0_D1 0x4000684cu +#define CYREG_B0_UDB07_D0_D1 0x4000684eu +#define CYREG_B0_UDB08_D0_D1 0x40006850u +#define CYREG_B0_UDB09_D0_D1 0x40006852u +#define CYREG_B0_UDB10_D0_D1 0x40006854u +#define CYREG_B0_UDB11_D0_D1 0x40006856u +#define CYREG_B0_UDB12_D0_D1 0x40006858u +#define CYREG_B0_UDB13_D0_D1 0x4000685au +#define CYREG_B0_UDB14_D0_D1 0x4000685cu +#define CYREG_B0_UDB15_D0_D1 0x4000685eu +#define CYREG_B0_UDB00_F0_F1 0x40006880u +#define CYREG_B0_UDB01_F0_F1 0x40006882u +#define CYREG_B0_UDB02_F0_F1 0x40006884u +#define CYREG_B0_UDB03_F0_F1 0x40006886u +#define CYREG_B0_UDB04_F0_F1 0x40006888u +#define CYREG_B0_UDB05_F0_F1 0x4000688au +#define CYREG_B0_UDB06_F0_F1 0x4000688cu +#define CYREG_B0_UDB07_F0_F1 0x4000688eu +#define CYREG_B0_UDB08_F0_F1 0x40006890u +#define CYREG_B0_UDB09_F0_F1 0x40006892u +#define CYREG_B0_UDB10_F0_F1 0x40006894u +#define CYREG_B0_UDB11_F0_F1 0x40006896u +#define CYREG_B0_UDB12_F0_F1 0x40006898u +#define CYREG_B0_UDB13_F0_F1 0x4000689au +#define CYREG_B0_UDB14_F0_F1 0x4000689cu +#define CYREG_B0_UDB15_F0_F1 0x4000689eu +#define CYREG_B0_UDB00_ST_CTL 0x400068c0u +#define CYREG_B0_UDB01_ST_CTL 0x400068c2u +#define CYREG_B0_UDB02_ST_CTL 0x400068c4u +#define CYREG_B0_UDB03_ST_CTL 0x400068c6u +#define CYREG_B0_UDB04_ST_CTL 0x400068c8u +#define CYREG_B0_UDB05_ST_CTL 0x400068cau +#define CYREG_B0_UDB06_ST_CTL 0x400068ccu +#define CYREG_B0_UDB07_ST_CTL 0x400068ceu +#define CYREG_B0_UDB08_ST_CTL 0x400068d0u +#define CYREG_B0_UDB09_ST_CTL 0x400068d2u +#define CYREG_B0_UDB10_ST_CTL 0x400068d4u +#define CYREG_B0_UDB11_ST_CTL 0x400068d6u +#define CYREG_B0_UDB12_ST_CTL 0x400068d8u +#define CYREG_B0_UDB13_ST_CTL 0x400068dau +#define CYREG_B0_UDB14_ST_CTL 0x400068dcu +#define CYREG_B0_UDB15_ST_CTL 0x400068deu +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900u +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902u +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904u +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906u +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908u +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690au +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690cu +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690eu +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910u +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912u +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914u +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916u +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918u +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691au +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691cu +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691eu +#define CYREG_B0_UDB00_MC_00 0x40006940u +#define CYREG_B0_UDB01_MC_00 0x40006942u +#define CYREG_B0_UDB02_MC_00 0x40006944u +#define CYREG_B0_UDB03_MC_00 0x40006946u +#define CYREG_B0_UDB04_MC_00 0x40006948u +#define CYREG_B0_UDB05_MC_00 0x4000694au +#define CYREG_B0_UDB06_MC_00 0x4000694cu +#define CYREG_B0_UDB07_MC_00 0x4000694eu +#define CYREG_B0_UDB08_MC_00 0x40006950u +#define CYREG_B0_UDB09_MC_00 0x40006952u +#define CYREG_B0_UDB10_MC_00 0x40006954u +#define CYREG_B0_UDB11_MC_00 0x40006956u +#define CYREG_B0_UDB12_MC_00 0x40006958u +#define CYREG_B0_UDB13_MC_00 0x4000695au +#define CYREG_B0_UDB14_MC_00 0x4000695cu +#define CYREG_B0_UDB15_MC_00 0x4000695eu +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160u +#define CYREG_B1_UDB04_A0_A1 0x40006a08u +#define CYREG_B1_UDB05_A0_A1 0x40006a0au +#define CYREG_B1_UDB06_A0_A1 0x40006a0cu +#define CYREG_B1_UDB07_A0_A1 0x40006a0eu +#define CYREG_B1_UDB08_A0_A1 0x40006a10u +#define CYREG_B1_UDB09_A0_A1 0x40006a12u +#define CYREG_B1_UDB10_A0_A1 0x40006a14u +#define CYREG_B1_UDB11_A0_A1 0x40006a16u +#define CYREG_B1_UDB04_D0_D1 0x40006a48u +#define CYREG_B1_UDB05_D0_D1 0x40006a4au +#define CYREG_B1_UDB06_D0_D1 0x40006a4cu +#define CYREG_B1_UDB07_D0_D1 0x40006a4eu +#define CYREG_B1_UDB08_D0_D1 0x40006a50u +#define CYREG_B1_UDB09_D0_D1 0x40006a52u +#define CYREG_B1_UDB10_D0_D1 0x40006a54u +#define CYREG_B1_UDB11_D0_D1 0x40006a56u +#define CYREG_B1_UDB04_F0_F1 0x40006a88u +#define CYREG_B1_UDB05_F0_F1 0x40006a8au +#define CYREG_B1_UDB06_F0_F1 0x40006a8cu +#define CYREG_B1_UDB07_F0_F1 0x40006a8eu +#define CYREG_B1_UDB08_F0_F1 0x40006a90u +#define CYREG_B1_UDB09_F0_F1 0x40006a92u +#define CYREG_B1_UDB10_F0_F1 0x40006a94u +#define CYREG_B1_UDB11_F0_F1 0x40006a96u +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8u +#define CYREG_B1_UDB05_ST_CTL 0x40006acau +#define CYREG_B1_UDB06_ST_CTL 0x40006accu +#define CYREG_B1_UDB07_ST_CTL 0x40006aceu +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0u +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2u +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4u +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6u +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08u +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0au +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0cu +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0eu +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10u +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12u +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14u +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16u +#define CYREG_B1_UDB04_MC_00 0x40006b48u +#define CYREG_B1_UDB05_MC_00 0x40006b4au +#define CYREG_B1_UDB06_MC_00 0x40006b4cu +#define CYREG_B1_UDB07_MC_00 0x40006b4eu +#define CYREG_B1_UDB08_MC_00 0x40006b50u +#define CYREG_B1_UDB09_MC_00 0x40006b52u +#define CYREG_B1_UDB10_MC_00 0x40006b54u +#define CYREG_B1_UDB11_MC_00 0x40006b56u +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075eu +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800u +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015eu +#define CYREG_B0_UDB00_01_A0 0x40006800u +#define CYREG_B0_UDB01_02_A0 0x40006802u +#define CYREG_B0_UDB02_03_A0 0x40006804u +#define CYREG_B0_UDB03_04_A0 0x40006806u +#define CYREG_B0_UDB04_05_A0 0x40006808u +#define CYREG_B0_UDB05_06_A0 0x4000680au +#define CYREG_B0_UDB06_07_A0 0x4000680cu +#define CYREG_B0_UDB07_08_A0 0x4000680eu +#define CYREG_B0_UDB08_09_A0 0x40006810u +#define CYREG_B0_UDB09_10_A0 0x40006812u +#define CYREG_B0_UDB10_11_A0 0x40006814u +#define CYREG_B0_UDB11_12_A0 0x40006816u +#define CYREG_B0_UDB12_13_A0 0x40006818u +#define CYREG_B0_UDB13_14_A0 0x4000681au +#define CYREG_B0_UDB14_15_A0 0x4000681cu +#define CYREG_B0_UDB00_01_A1 0x40006820u +#define CYREG_B0_UDB01_02_A1 0x40006822u +#define CYREG_B0_UDB02_03_A1 0x40006824u +#define CYREG_B0_UDB03_04_A1 0x40006826u +#define CYREG_B0_UDB04_05_A1 0x40006828u +#define CYREG_B0_UDB05_06_A1 0x4000682au +#define CYREG_B0_UDB06_07_A1 0x4000682cu +#define CYREG_B0_UDB07_08_A1 0x4000682eu +#define CYREG_B0_UDB08_09_A1 0x40006830u +#define CYREG_B0_UDB09_10_A1 0x40006832u +#define CYREG_B0_UDB10_11_A1 0x40006834u +#define CYREG_B0_UDB11_12_A1 0x40006836u +#define CYREG_B0_UDB12_13_A1 0x40006838u +#define CYREG_B0_UDB13_14_A1 0x4000683au +#define CYREG_B0_UDB14_15_A1 0x4000683cu +#define CYREG_B0_UDB00_01_D0 0x40006840u +#define CYREG_B0_UDB01_02_D0 0x40006842u +#define CYREG_B0_UDB02_03_D0 0x40006844u +#define CYREG_B0_UDB03_04_D0 0x40006846u +#define CYREG_B0_UDB04_05_D0 0x40006848u +#define CYREG_B0_UDB05_06_D0 0x4000684au +#define CYREG_B0_UDB06_07_D0 0x4000684cu +#define CYREG_B0_UDB07_08_D0 0x4000684eu +#define CYREG_B0_UDB08_09_D0 0x40006850u +#define CYREG_B0_UDB09_10_D0 0x40006852u +#define CYREG_B0_UDB10_11_D0 0x40006854u +#define CYREG_B0_UDB11_12_D0 0x40006856u +#define CYREG_B0_UDB12_13_D0 0x40006858u +#define CYREG_B0_UDB13_14_D0 0x4000685au +#define CYREG_B0_UDB14_15_D0 0x4000685cu +#define CYREG_B0_UDB00_01_D1 0x40006860u +#define CYREG_B0_UDB01_02_D1 0x40006862u +#define CYREG_B0_UDB02_03_D1 0x40006864u +#define CYREG_B0_UDB03_04_D1 0x40006866u +#define CYREG_B0_UDB04_05_D1 0x40006868u +#define CYREG_B0_UDB05_06_D1 0x4000686au +#define CYREG_B0_UDB06_07_D1 0x4000686cu +#define CYREG_B0_UDB07_08_D1 0x4000686eu +#define CYREG_B0_UDB08_09_D1 0x40006870u +#define CYREG_B0_UDB09_10_D1 0x40006872u +#define CYREG_B0_UDB10_11_D1 0x40006874u +#define CYREG_B0_UDB11_12_D1 0x40006876u +#define CYREG_B0_UDB12_13_D1 0x40006878u +#define CYREG_B0_UDB13_14_D1 0x4000687au +#define CYREG_B0_UDB14_15_D1 0x4000687cu +#define CYREG_B0_UDB00_01_F0 0x40006880u +#define CYREG_B0_UDB01_02_F0 0x40006882u +#define CYREG_B0_UDB02_03_F0 0x40006884u +#define CYREG_B0_UDB03_04_F0 0x40006886u +#define CYREG_B0_UDB04_05_F0 0x40006888u +#define CYREG_B0_UDB05_06_F0 0x4000688au +#define CYREG_B0_UDB06_07_F0 0x4000688cu +#define CYREG_B0_UDB07_08_F0 0x4000688eu +#define CYREG_B0_UDB08_09_F0 0x40006890u +#define CYREG_B0_UDB09_10_F0 0x40006892u +#define CYREG_B0_UDB10_11_F0 0x40006894u +#define CYREG_B0_UDB11_12_F0 0x40006896u +#define CYREG_B0_UDB12_13_F0 0x40006898u +#define CYREG_B0_UDB13_14_F0 0x4000689au +#define CYREG_B0_UDB14_15_F0 0x4000689cu +#define CYREG_B0_UDB00_01_F1 0x400068a0u +#define CYREG_B0_UDB01_02_F1 0x400068a2u +#define CYREG_B0_UDB02_03_F1 0x400068a4u +#define CYREG_B0_UDB03_04_F1 0x400068a6u +#define CYREG_B0_UDB04_05_F1 0x400068a8u +#define CYREG_B0_UDB05_06_F1 0x400068aau +#define CYREG_B0_UDB06_07_F1 0x400068acu +#define CYREG_B0_UDB07_08_F1 0x400068aeu +#define CYREG_B0_UDB08_09_F1 0x400068b0u +#define CYREG_B0_UDB09_10_F1 0x400068b2u +#define CYREG_B0_UDB10_11_F1 0x400068b4u +#define CYREG_B0_UDB11_12_F1 0x400068b6u +#define CYREG_B0_UDB12_13_F1 0x400068b8u +#define CYREG_B0_UDB13_14_F1 0x400068bau +#define CYREG_B0_UDB14_15_F1 0x400068bcu +#define CYREG_B0_UDB00_01_ST 0x400068c0u +#define CYREG_B0_UDB01_02_ST 0x400068c2u +#define CYREG_B0_UDB02_03_ST 0x400068c4u +#define CYREG_B0_UDB03_04_ST 0x400068c6u +#define CYREG_B0_UDB04_05_ST 0x400068c8u +#define CYREG_B0_UDB05_06_ST 0x400068cau +#define CYREG_B0_UDB06_07_ST 0x400068ccu +#define CYREG_B0_UDB07_08_ST 0x400068ceu +#define CYREG_B0_UDB08_09_ST 0x400068d0u +#define CYREG_B0_UDB09_10_ST 0x400068d2u +#define CYREG_B0_UDB10_11_ST 0x400068d4u +#define CYREG_B0_UDB11_12_ST 0x400068d6u +#define CYREG_B0_UDB12_13_ST 0x400068d8u +#define CYREG_B0_UDB13_14_ST 0x400068dau +#define CYREG_B0_UDB14_15_ST 0x400068dcu +#define CYREG_B0_UDB00_01_CTL 0x400068e0u +#define CYREG_B0_UDB01_02_CTL 0x400068e2u +#define CYREG_B0_UDB02_03_CTL 0x400068e4u +#define CYREG_B0_UDB03_04_CTL 0x400068e6u +#define CYREG_B0_UDB04_05_CTL 0x400068e8u +#define CYREG_B0_UDB05_06_CTL 0x400068eau +#define CYREG_B0_UDB06_07_CTL 0x400068ecu +#define CYREG_B0_UDB07_08_CTL 0x400068eeu +#define CYREG_B0_UDB08_09_CTL 0x400068f0u +#define CYREG_B0_UDB09_10_CTL 0x400068f2u +#define CYREG_B0_UDB10_11_CTL 0x400068f4u +#define CYREG_B0_UDB11_12_CTL 0x400068f6u +#define CYREG_B0_UDB12_13_CTL 0x400068f8u +#define CYREG_B0_UDB13_14_CTL 0x400068fau +#define CYREG_B0_UDB14_15_CTL 0x400068fcu +#define CYREG_B0_UDB00_01_MSK 0x40006900u +#define CYREG_B0_UDB01_02_MSK 0x40006902u +#define CYREG_B0_UDB02_03_MSK 0x40006904u +#define CYREG_B0_UDB03_04_MSK 0x40006906u +#define CYREG_B0_UDB04_05_MSK 0x40006908u +#define CYREG_B0_UDB05_06_MSK 0x4000690au +#define CYREG_B0_UDB06_07_MSK 0x4000690cu +#define CYREG_B0_UDB07_08_MSK 0x4000690eu +#define CYREG_B0_UDB08_09_MSK 0x40006910u +#define CYREG_B0_UDB09_10_MSK 0x40006912u +#define CYREG_B0_UDB10_11_MSK 0x40006914u +#define CYREG_B0_UDB11_12_MSK 0x40006916u +#define CYREG_B0_UDB12_13_MSK 0x40006918u +#define CYREG_B0_UDB13_14_MSK 0x4000691au +#define CYREG_B0_UDB14_15_MSK 0x4000691cu +#define CYREG_B0_UDB00_01_ACTL 0x40006920u +#define CYREG_B0_UDB01_02_ACTL 0x40006922u +#define CYREG_B0_UDB02_03_ACTL 0x40006924u +#define CYREG_B0_UDB03_04_ACTL 0x40006926u +#define CYREG_B0_UDB04_05_ACTL 0x40006928u +#define CYREG_B0_UDB05_06_ACTL 0x4000692au +#define CYREG_B0_UDB06_07_ACTL 0x4000692cu +#define CYREG_B0_UDB07_08_ACTL 0x4000692eu +#define CYREG_B0_UDB08_09_ACTL 0x40006930u +#define CYREG_B0_UDB09_10_ACTL 0x40006932u +#define CYREG_B0_UDB10_11_ACTL 0x40006934u +#define CYREG_B0_UDB11_12_ACTL 0x40006936u +#define CYREG_B0_UDB12_13_ACTL 0x40006938u +#define CYREG_B0_UDB13_14_ACTL 0x4000693au +#define CYREG_B0_UDB14_15_ACTL 0x4000693cu +#define CYREG_B0_UDB00_01_MC 0x40006940u +#define CYREG_B0_UDB01_02_MC 0x40006942u +#define CYREG_B0_UDB02_03_MC 0x40006944u +#define CYREG_B0_UDB03_04_MC 0x40006946u +#define CYREG_B0_UDB04_05_MC 0x40006948u +#define CYREG_B0_UDB05_06_MC 0x4000694au +#define CYREG_B0_UDB06_07_MC 0x4000694cu +#define CYREG_B0_UDB07_08_MC 0x4000694eu +#define CYREG_B0_UDB08_09_MC 0x40006950u +#define CYREG_B0_UDB09_10_MC 0x40006952u +#define CYREG_B0_UDB10_11_MC 0x40006954u +#define CYREG_B0_UDB11_12_MC 0x40006956u +#define CYREG_B0_UDB12_13_MC 0x40006958u +#define CYREG_B0_UDB13_14_MC 0x4000695au +#define CYREG_B0_UDB14_15_MC 0x4000695cu +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00u +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015eu +#define CYREG_B1_UDB04_05_A0 0x40006a08u +#define CYREG_B1_UDB05_06_A0 0x40006a0au +#define CYREG_B1_UDB06_07_A0 0x40006a0cu +#define CYREG_B1_UDB07_08_A0 0x40006a0eu +#define CYREG_B1_UDB08_09_A0 0x40006a10u +#define CYREG_B1_UDB09_10_A0 0x40006a12u +#define CYREG_B1_UDB10_11_A0 0x40006a14u +#define CYREG_B1_UDB11_12_A0 0x40006a16u +#define CYREG_B1_UDB04_05_A1 0x40006a28u +#define CYREG_B1_UDB05_06_A1 0x40006a2au +#define CYREG_B1_UDB06_07_A1 0x40006a2cu +#define CYREG_B1_UDB07_08_A1 0x40006a2eu +#define CYREG_B1_UDB08_09_A1 0x40006a30u +#define CYREG_B1_UDB09_10_A1 0x40006a32u +#define CYREG_B1_UDB10_11_A1 0x40006a34u +#define CYREG_B1_UDB11_12_A1 0x40006a36u +#define CYREG_B1_UDB04_05_D0 0x40006a48u +#define CYREG_B1_UDB05_06_D0 0x40006a4au +#define CYREG_B1_UDB06_07_D0 0x40006a4cu +#define CYREG_B1_UDB07_08_D0 0x40006a4eu +#define CYREG_B1_UDB08_09_D0 0x40006a50u +#define CYREG_B1_UDB09_10_D0 0x40006a52u +#define CYREG_B1_UDB10_11_D0 0x40006a54u +#define CYREG_B1_UDB11_12_D0 0x40006a56u +#define CYREG_B1_UDB04_05_D1 0x40006a68u +#define CYREG_B1_UDB05_06_D1 0x40006a6au +#define CYREG_B1_UDB06_07_D1 0x40006a6cu +#define CYREG_B1_UDB07_08_D1 0x40006a6eu +#define CYREG_B1_UDB08_09_D1 0x40006a70u +#define CYREG_B1_UDB09_10_D1 0x40006a72u +#define CYREG_B1_UDB10_11_D1 0x40006a74u +#define CYREG_B1_UDB11_12_D1 0x40006a76u +#define CYREG_B1_UDB04_05_F0 0x40006a88u +#define CYREG_B1_UDB05_06_F0 0x40006a8au +#define CYREG_B1_UDB06_07_F0 0x40006a8cu +#define CYREG_B1_UDB07_08_F0 0x40006a8eu +#define CYREG_B1_UDB08_09_F0 0x40006a90u +#define CYREG_B1_UDB09_10_F0 0x40006a92u +#define CYREG_B1_UDB10_11_F0 0x40006a94u +#define CYREG_B1_UDB11_12_F0 0x40006a96u +#define CYREG_B1_UDB04_05_F1 0x40006aa8u +#define CYREG_B1_UDB05_06_F1 0x40006aaau +#define CYREG_B1_UDB06_07_F1 0x40006aacu +#define CYREG_B1_UDB07_08_F1 0x40006aaeu +#define CYREG_B1_UDB08_09_F1 0x40006ab0u +#define CYREG_B1_UDB09_10_F1 0x40006ab2u +#define CYREG_B1_UDB10_11_F1 0x40006ab4u +#define CYREG_B1_UDB11_12_F1 0x40006ab6u +#define CYREG_B1_UDB04_05_ST 0x40006ac8u +#define CYREG_B1_UDB05_06_ST 0x40006acau +#define CYREG_B1_UDB06_07_ST 0x40006accu +#define CYREG_B1_UDB07_08_ST 0x40006aceu +#define CYREG_B1_UDB08_09_ST 0x40006ad0u +#define CYREG_B1_UDB09_10_ST 0x40006ad2u +#define CYREG_B1_UDB10_11_ST 0x40006ad4u +#define CYREG_B1_UDB11_12_ST 0x40006ad6u +#define CYREG_B1_UDB04_05_CTL 0x40006ae8u +#define CYREG_B1_UDB05_06_CTL 0x40006aeau +#define CYREG_B1_UDB06_07_CTL 0x40006aecu +#define CYREG_B1_UDB07_08_CTL 0x40006aeeu +#define CYREG_B1_UDB08_09_CTL 0x40006af0u +#define CYREG_B1_UDB09_10_CTL 0x40006af2u +#define CYREG_B1_UDB10_11_CTL 0x40006af4u +#define CYREG_B1_UDB11_12_CTL 0x40006af6u +#define CYREG_B1_UDB04_05_MSK 0x40006b08u +#define CYREG_B1_UDB05_06_MSK 0x40006b0au +#define CYREG_B1_UDB06_07_MSK 0x40006b0cu +#define CYREG_B1_UDB07_08_MSK 0x40006b0eu +#define CYREG_B1_UDB08_09_MSK 0x40006b10u +#define CYREG_B1_UDB09_10_MSK 0x40006b12u +#define CYREG_B1_UDB10_11_MSK 0x40006b14u +#define CYREG_B1_UDB11_12_MSK 0x40006b16u +#define CYREG_B1_UDB04_05_ACTL 0x40006b28u +#define CYREG_B1_UDB05_06_ACTL 0x40006b2au +#define CYREG_B1_UDB06_07_ACTL 0x40006b2cu +#define CYREG_B1_UDB07_08_ACTL 0x40006b2eu +#define CYREG_B1_UDB08_09_ACTL 0x40006b30u +#define CYREG_B1_UDB09_10_ACTL 0x40006b32u +#define CYREG_B1_UDB10_11_ACTL 0x40006b34u +#define CYREG_B1_UDB11_12_ACTL 0x40006b36u +#define CYREG_B1_UDB04_05_MC 0x40006b48u +#define CYREG_B1_UDB05_06_MC 0x40006b4au +#define CYREG_B1_UDB06_07_MC 0x40006b4cu +#define CYREG_B1_UDB07_08_MC 0x40006b4eu +#define CYREG_B1_UDB08_09_MC 0x40006b50u +#define CYREG_B1_UDB09_10_MC 0x40006b52u +#define CYREG_B1_UDB10_11_MC 0x40006b54u +#define CYREG_B1_UDB11_12_MC 0x40006b56u +#define CYDEV_PHUB_BASE 0x40007000u +#define CYDEV_PHUB_SIZE 0x00000c00u +#define CYREG_PHUB_CFG 0x40007000u +#define CYREG_PHUB_ERR 0x40007004u +#define CYREG_PHUB_ERR_ADR 0x40007008u +#define CYDEV_PHUB_CH0_BASE 0x40007010u +#define CYDEV_PHUB_CH0_SIZE 0x0000000cu +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010u +#define CYREG_PHUB_CH0_ACTION 0x40007014u +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018u +#define CYDEV_PHUB_CH1_BASE 0x40007020u +#define CYDEV_PHUB_CH1_SIZE 0x0000000cu +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020u +#define CYREG_PHUB_CH1_ACTION 0x40007024u +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028u +#define CYDEV_PHUB_CH2_BASE 0x40007030u +#define CYDEV_PHUB_CH2_SIZE 0x0000000cu +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030u +#define CYREG_PHUB_CH2_ACTION 0x40007034u +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038u +#define CYDEV_PHUB_CH3_BASE 0x40007040u +#define CYDEV_PHUB_CH3_SIZE 0x0000000cu +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040u +#define CYREG_PHUB_CH3_ACTION 0x40007044u +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048u +#define CYDEV_PHUB_CH4_BASE 0x40007050u +#define CYDEV_PHUB_CH4_SIZE 0x0000000cu +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050u +#define CYREG_PHUB_CH4_ACTION 0x40007054u +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058u +#define CYDEV_PHUB_CH5_BASE 0x40007060u +#define CYDEV_PHUB_CH5_SIZE 0x0000000cu +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060u +#define CYREG_PHUB_CH5_ACTION 0x40007064u +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068u +#define CYDEV_PHUB_CH6_BASE 0x40007070u +#define CYDEV_PHUB_CH6_SIZE 0x0000000cu +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070u +#define CYREG_PHUB_CH6_ACTION 0x40007074u +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078u +#define CYDEV_PHUB_CH7_BASE 0x40007080u +#define CYDEV_PHUB_CH7_SIZE 0x0000000cu +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080u +#define CYREG_PHUB_CH7_ACTION 0x40007084u +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088u +#define CYDEV_PHUB_CH8_BASE 0x40007090u +#define CYDEV_PHUB_CH8_SIZE 0x0000000cu +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090u +#define CYREG_PHUB_CH8_ACTION 0x40007094u +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098u +#define CYDEV_PHUB_CH9_BASE 0x400070a0u +#define CYDEV_PHUB_CH9_SIZE 0x0000000cu +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0u +#define CYREG_PHUB_CH9_ACTION 0x400070a4u +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8u +#define CYDEV_PHUB_CH10_BASE 0x400070b0u +#define CYDEV_PHUB_CH10_SIZE 0x0000000cu +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0u +#define CYREG_PHUB_CH10_ACTION 0x400070b4u +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8u +#define CYDEV_PHUB_CH11_BASE 0x400070c0u +#define CYDEV_PHUB_CH11_SIZE 0x0000000cu +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0u +#define CYREG_PHUB_CH11_ACTION 0x400070c4u +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8u +#define CYDEV_PHUB_CH12_BASE 0x400070d0u +#define CYDEV_PHUB_CH12_SIZE 0x0000000cu +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0u +#define CYREG_PHUB_CH12_ACTION 0x400070d4u +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8u +#define CYDEV_PHUB_CH13_BASE 0x400070e0u +#define CYDEV_PHUB_CH13_SIZE 0x0000000cu +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0u +#define CYREG_PHUB_CH13_ACTION 0x400070e4u +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8u +#define CYDEV_PHUB_CH14_BASE 0x400070f0u +#define CYDEV_PHUB_CH14_SIZE 0x0000000cu +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0u +#define CYREG_PHUB_CH14_ACTION 0x400070f4u +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8u +#define CYDEV_PHUB_CH15_BASE 0x40007100u +#define CYDEV_PHUB_CH15_SIZE 0x0000000cu +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100u +#define CYREG_PHUB_CH15_ACTION 0x40007104u +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108u +#define CYDEV_PHUB_CH16_BASE 0x40007110u +#define CYDEV_PHUB_CH16_SIZE 0x0000000cu +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110u +#define CYREG_PHUB_CH16_ACTION 0x40007114u +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118u +#define CYDEV_PHUB_CH17_BASE 0x40007120u +#define CYDEV_PHUB_CH17_SIZE 0x0000000cu +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120u +#define CYREG_PHUB_CH17_ACTION 0x40007124u +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128u +#define CYDEV_PHUB_CH18_BASE 0x40007130u +#define CYDEV_PHUB_CH18_SIZE 0x0000000cu +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130u +#define CYREG_PHUB_CH18_ACTION 0x40007134u +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138u +#define CYDEV_PHUB_CH19_BASE 0x40007140u +#define CYDEV_PHUB_CH19_SIZE 0x0000000cu +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140u +#define CYREG_PHUB_CH19_ACTION 0x40007144u +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148u +#define CYDEV_PHUB_CH20_BASE 0x40007150u +#define CYDEV_PHUB_CH20_SIZE 0x0000000cu +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150u +#define CYREG_PHUB_CH20_ACTION 0x40007154u +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158u +#define CYDEV_PHUB_CH21_BASE 0x40007160u +#define CYDEV_PHUB_CH21_SIZE 0x0000000cu +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160u +#define CYREG_PHUB_CH21_ACTION 0x40007164u +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168u +#define CYDEV_PHUB_CH22_BASE 0x40007170u +#define CYDEV_PHUB_CH22_SIZE 0x0000000cu +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170u +#define CYREG_PHUB_CH22_ACTION 0x40007174u +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178u +#define CYDEV_PHUB_CH23_BASE 0x40007180u +#define CYDEV_PHUB_CH23_SIZE 0x0000000cu +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180u +#define CYREG_PHUB_CH23_ACTION 0x40007184u +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188u +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600u +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600u +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604u +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608u +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608u +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760cu +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610u +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610u +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614u +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618u +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618u +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761cu +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620u +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620u +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624u +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628u +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628u +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762cu +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630u +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630u +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634u +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638u +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638u +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763cu +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640u +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640u +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644u +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648u +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648u +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764cu +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650u +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650u +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654u +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658u +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658u +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765cu +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660u +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660u +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664u +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668u +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668u +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766cu +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670u +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670u +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674u +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678u +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678u +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767cu +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680u +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680u +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684u +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688u +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688u +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768cu +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690u +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690u +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694u +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698u +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698u +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769cu +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0u +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0u +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4u +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8u +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8u +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076acu +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0u +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0u +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4u +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8u +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008u +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8u +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bcu +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800u +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800u +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804u +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808u +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808u +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780cu +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810u +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810u +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814u +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818u +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818u +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781cu +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820u +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820u +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824u +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828u +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828u +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782cu +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830u +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830u +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834u +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838u +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838u +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783cu +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840u +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840u +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844u +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848u +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848u +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784cu +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850u +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850u +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854u +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858u +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858u +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785cu +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860u +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860u +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864u +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868u +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868u +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786cu +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870u +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870u +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874u +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878u +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878u +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787cu +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880u +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880u +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884u +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888u +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888u +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788cu +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890u +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890u +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894u +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898u +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898u +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789cu +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0u +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0u +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4u +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8u +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8u +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078acu +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0u +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0u +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4u +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8u +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8u +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bcu +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0u +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0u +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4u +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8u +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8u +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078ccu +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0u +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0u +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4u +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8u +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8u +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dcu +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0u +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0u +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4u +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8u +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8u +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ecu +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0u +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0u +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4u +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8u +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8u +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fcu +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900u +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900u +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904u +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908u +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908u +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790cu +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910u +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910u +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914u +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918u +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918u +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791cu +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920u +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920u +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924u +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928u +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928u +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792cu +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930u +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930u +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934u +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938u +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938u +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793cu +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940u +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940u +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944u +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948u +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948u +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794cu +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950u +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950u +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954u +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958u +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958u +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795cu +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960u +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960u +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964u +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968u +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968u +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796cu +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970u +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970u +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974u +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978u +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978u +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797cu +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980u +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980u +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984u +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988u +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988u +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798cu +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990u +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990u +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994u +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998u +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998u +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799cu +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0u +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0u +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4u +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8u +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8u +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079acu +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0u +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0u +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4u +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8u +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8u +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bcu +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0u +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0u +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4u +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8u +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8u +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079ccu +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0u +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0u +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4u +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8u +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8u +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dcu +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0u +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0u +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4u +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8u +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8u +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ecu +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0u +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0u +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4u +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8u +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8u +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fcu +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00u +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00u +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04u +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08u +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08u +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0cu +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10u +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10u +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14u +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18u +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18u +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1cu +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20u +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20u +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24u +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28u +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28u +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2cu +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30u +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30u +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34u +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38u +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38u +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3cu +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40u +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40u +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44u +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48u +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48u +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4cu +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50u +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50u +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54u +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58u +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58u +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5cu +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60u +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60u +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64u +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68u +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68u +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6cu +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70u +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70u +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74u +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78u +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78u +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7cu +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80u +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80u +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84u +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88u +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88u +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8cu +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90u +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90u +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94u +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98u +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98u +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9cu +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0u +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0u +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4u +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8u +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8u +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aacu +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0u +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0u +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4u +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8u +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8u +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abcu +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0u +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0u +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4u +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8u +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8u +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007accu +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0u +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0u +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4u +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8u +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8u +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adcu +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0u +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0u +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4u +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8u +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8u +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aecu +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0u +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0u +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4u +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8u +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8u +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afcu +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00u +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00u +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04u +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08u +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08u +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0cu +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10u +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10u +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14u +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18u +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18u +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1cu +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20u +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20u +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24u +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28u +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28u +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2cu +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30u +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30u +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34u +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38u +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38u +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3cu +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40u +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40u +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44u +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48u +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48u +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4cu +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50u +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50u +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54u +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58u +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58u +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5cu +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60u +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60u +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64u +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68u +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68u +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6cu +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70u +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70u +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74u +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78u +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78u +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7cu +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80u +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80u +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84u +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88u +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88u +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8cu +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90u +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90u +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94u +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98u +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98u +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9cu +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0u +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0u +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4u +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8u +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8u +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bacu +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0u +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0u +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4u +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8u +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8u +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbcu +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0u +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0u +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4u +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8u +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8u +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bccu +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0u +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0u +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4u +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8u +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8u +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdcu +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0u +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0u +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4u +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8u +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8u +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007becu +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0u +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0u +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4u +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8u +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008u +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8u +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfcu +#define CYDEV_EE_BASE 0x40008000u +#define CYDEV_EE_SIZE 0x00000800u +#define CYREG_EE_DATA_MBASE 0x40008000u +#define CYREG_EE_DATA_MSIZE 0x00000800u +#define CYDEV_CAN0_BASE 0x4000a000u +#define CYDEV_CAN0_SIZE 0x000002a0u +#define CYDEV_CAN0_CSR_BASE 0x4000a000u +#define CYDEV_CAN0_CSR_SIZE 0x00000018u +#define CYREG_CAN0_CSR_INT_SR 0x4000a000u +#define CYREG_CAN0_CSR_INT_EN 0x4000a004u +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008u +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00cu +#define CYREG_CAN0_CSR_CMD 0x4000a010u +#define CYREG_CAN0_CSR_CFG 0x4000a014u +#define CYDEV_CAN0_TX0_BASE 0x4000a020u +#define CYDEV_CAN0_TX0_SIZE 0x00000010u +#define CYREG_CAN0_TX0_CMD 0x4000a020u +#define CYREG_CAN0_TX0_ID 0x4000a024u +#define CYREG_CAN0_TX0_DH 0x4000a028u +#define CYREG_CAN0_TX0_DL 0x4000a02cu +#define CYDEV_CAN0_TX1_BASE 0x4000a030u +#define CYDEV_CAN0_TX1_SIZE 0x00000010u +#define CYREG_CAN0_TX1_CMD 0x4000a030u +#define CYREG_CAN0_TX1_ID 0x4000a034u +#define CYREG_CAN0_TX1_DH 0x4000a038u +#define CYREG_CAN0_TX1_DL 0x4000a03cu +#define CYDEV_CAN0_TX2_BASE 0x4000a040u +#define CYDEV_CAN0_TX2_SIZE 0x00000010u +#define CYREG_CAN0_TX2_CMD 0x4000a040u +#define CYREG_CAN0_TX2_ID 0x4000a044u +#define CYREG_CAN0_TX2_DH 0x4000a048u +#define CYREG_CAN0_TX2_DL 0x4000a04cu +#define CYDEV_CAN0_TX3_BASE 0x4000a050u +#define CYDEV_CAN0_TX3_SIZE 0x00000010u +#define CYREG_CAN0_TX3_CMD 0x4000a050u +#define CYREG_CAN0_TX3_ID 0x4000a054u +#define CYREG_CAN0_TX3_DH 0x4000a058u +#define CYREG_CAN0_TX3_DL 0x4000a05cu +#define CYDEV_CAN0_TX4_BASE 0x4000a060u +#define CYDEV_CAN0_TX4_SIZE 0x00000010u +#define CYREG_CAN0_TX4_CMD 0x4000a060u +#define CYREG_CAN0_TX4_ID 0x4000a064u +#define CYREG_CAN0_TX4_DH 0x4000a068u +#define CYREG_CAN0_TX4_DL 0x4000a06cu +#define CYDEV_CAN0_TX5_BASE 0x4000a070u +#define CYDEV_CAN0_TX5_SIZE 0x00000010u +#define CYREG_CAN0_TX5_CMD 0x4000a070u +#define CYREG_CAN0_TX5_ID 0x4000a074u +#define CYREG_CAN0_TX5_DH 0x4000a078u +#define CYREG_CAN0_TX5_DL 0x4000a07cu +#define CYDEV_CAN0_TX6_BASE 0x4000a080u +#define CYDEV_CAN0_TX6_SIZE 0x00000010u +#define CYREG_CAN0_TX6_CMD 0x4000a080u +#define CYREG_CAN0_TX6_ID 0x4000a084u +#define CYREG_CAN0_TX6_DH 0x4000a088u +#define CYREG_CAN0_TX6_DL 0x4000a08cu +#define CYDEV_CAN0_TX7_BASE 0x4000a090u +#define CYDEV_CAN0_TX7_SIZE 0x00000010u +#define CYREG_CAN0_TX7_CMD 0x4000a090u +#define CYREG_CAN0_TX7_ID 0x4000a094u +#define CYREG_CAN0_TX7_DH 0x4000a098u +#define CYREG_CAN0_TX7_DL 0x4000a09cu +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0u +#define CYDEV_CAN0_RX0_SIZE 0x00000020u +#define CYREG_CAN0_RX0_CMD 0x4000a0a0u +#define CYREG_CAN0_RX0_ID 0x4000a0a4u +#define CYREG_CAN0_RX0_DH 0x4000a0a8u +#define CYREG_CAN0_RX0_DL 0x4000a0acu +#define CYREG_CAN0_RX0_AMR 0x4000a0b0u +#define CYREG_CAN0_RX0_ACR 0x4000a0b4u +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8u +#define CYREG_CAN0_RX0_ACRD 0x4000a0bcu +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0u +#define CYDEV_CAN0_RX1_SIZE 0x00000020u +#define CYREG_CAN0_RX1_CMD 0x4000a0c0u +#define CYREG_CAN0_RX1_ID 0x4000a0c4u +#define CYREG_CAN0_RX1_DH 0x4000a0c8u +#define CYREG_CAN0_RX1_DL 0x4000a0ccu +#define CYREG_CAN0_RX1_AMR 0x4000a0d0u +#define CYREG_CAN0_RX1_ACR 0x4000a0d4u +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8u +#define CYREG_CAN0_RX1_ACRD 0x4000a0dcu +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0u +#define CYDEV_CAN0_RX2_SIZE 0x00000020u +#define CYREG_CAN0_RX2_CMD 0x4000a0e0u +#define CYREG_CAN0_RX2_ID 0x4000a0e4u +#define CYREG_CAN0_RX2_DH 0x4000a0e8u +#define CYREG_CAN0_RX2_DL 0x4000a0ecu +#define CYREG_CAN0_RX2_AMR 0x4000a0f0u +#define CYREG_CAN0_RX2_ACR 0x4000a0f4u +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8u +#define CYREG_CAN0_RX2_ACRD 0x4000a0fcu +#define CYDEV_CAN0_RX3_BASE 0x4000a100u +#define CYDEV_CAN0_RX3_SIZE 0x00000020u +#define CYREG_CAN0_RX3_CMD 0x4000a100u +#define CYREG_CAN0_RX3_ID 0x4000a104u +#define CYREG_CAN0_RX3_DH 0x4000a108u +#define CYREG_CAN0_RX3_DL 0x4000a10cu +#define CYREG_CAN0_RX3_AMR 0x4000a110u +#define CYREG_CAN0_RX3_ACR 0x4000a114u +#define CYREG_CAN0_RX3_AMRD 0x4000a118u +#define CYREG_CAN0_RX3_ACRD 0x4000a11cu +#define CYDEV_CAN0_RX4_BASE 0x4000a120u +#define CYDEV_CAN0_RX4_SIZE 0x00000020u +#define CYREG_CAN0_RX4_CMD 0x4000a120u +#define CYREG_CAN0_RX4_ID 0x4000a124u +#define CYREG_CAN0_RX4_DH 0x4000a128u +#define CYREG_CAN0_RX4_DL 0x4000a12cu +#define CYREG_CAN0_RX4_AMR 0x4000a130u +#define CYREG_CAN0_RX4_ACR 0x4000a134u +#define CYREG_CAN0_RX4_AMRD 0x4000a138u +#define CYREG_CAN0_RX4_ACRD 0x4000a13cu +#define CYDEV_CAN0_RX5_BASE 0x4000a140u +#define CYDEV_CAN0_RX5_SIZE 0x00000020u +#define CYREG_CAN0_RX5_CMD 0x4000a140u +#define CYREG_CAN0_RX5_ID 0x4000a144u +#define CYREG_CAN0_RX5_DH 0x4000a148u +#define CYREG_CAN0_RX5_DL 0x4000a14cu +#define CYREG_CAN0_RX5_AMR 0x4000a150u +#define CYREG_CAN0_RX5_ACR 0x4000a154u +#define CYREG_CAN0_RX5_AMRD 0x4000a158u +#define CYREG_CAN0_RX5_ACRD 0x4000a15cu +#define CYDEV_CAN0_RX6_BASE 0x4000a160u +#define CYDEV_CAN0_RX6_SIZE 0x00000020u +#define CYREG_CAN0_RX6_CMD 0x4000a160u +#define CYREG_CAN0_RX6_ID 0x4000a164u +#define CYREG_CAN0_RX6_DH 0x4000a168u +#define CYREG_CAN0_RX6_DL 0x4000a16cu +#define CYREG_CAN0_RX6_AMR 0x4000a170u +#define CYREG_CAN0_RX6_ACR 0x4000a174u +#define CYREG_CAN0_RX6_AMRD 0x4000a178u +#define CYREG_CAN0_RX6_ACRD 0x4000a17cu +#define CYDEV_CAN0_RX7_BASE 0x4000a180u +#define CYDEV_CAN0_RX7_SIZE 0x00000020u +#define CYREG_CAN0_RX7_CMD 0x4000a180u +#define CYREG_CAN0_RX7_ID 0x4000a184u +#define CYREG_CAN0_RX7_DH 0x4000a188u +#define CYREG_CAN0_RX7_DL 0x4000a18cu +#define CYREG_CAN0_RX7_AMR 0x4000a190u +#define CYREG_CAN0_RX7_ACR 0x4000a194u +#define CYREG_CAN0_RX7_AMRD 0x4000a198u +#define CYREG_CAN0_RX7_ACRD 0x4000a19cu +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0u +#define CYDEV_CAN0_RX8_SIZE 0x00000020u +#define CYREG_CAN0_RX8_CMD 0x4000a1a0u +#define CYREG_CAN0_RX8_ID 0x4000a1a4u +#define CYREG_CAN0_RX8_DH 0x4000a1a8u +#define CYREG_CAN0_RX8_DL 0x4000a1acu +#define CYREG_CAN0_RX8_AMR 0x4000a1b0u +#define CYREG_CAN0_RX8_ACR 0x4000a1b4u +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8u +#define CYREG_CAN0_RX8_ACRD 0x4000a1bcu +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0u +#define CYDEV_CAN0_RX9_SIZE 0x00000020u +#define CYREG_CAN0_RX9_CMD 0x4000a1c0u +#define CYREG_CAN0_RX9_ID 0x4000a1c4u +#define CYREG_CAN0_RX9_DH 0x4000a1c8u +#define CYREG_CAN0_RX9_DL 0x4000a1ccu +#define CYREG_CAN0_RX9_AMR 0x4000a1d0u +#define CYREG_CAN0_RX9_ACR 0x4000a1d4u +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8u +#define CYREG_CAN0_RX9_ACRD 0x4000a1dcu +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0u +#define CYDEV_CAN0_RX10_SIZE 0x00000020u +#define CYREG_CAN0_RX10_CMD 0x4000a1e0u +#define CYREG_CAN0_RX10_ID 0x4000a1e4u +#define CYREG_CAN0_RX10_DH 0x4000a1e8u +#define CYREG_CAN0_RX10_DL 0x4000a1ecu +#define CYREG_CAN0_RX10_AMR 0x4000a1f0u +#define CYREG_CAN0_RX10_ACR 0x4000a1f4u +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8u +#define CYREG_CAN0_RX10_ACRD 0x4000a1fcu +#define CYDEV_CAN0_RX11_BASE 0x4000a200u +#define CYDEV_CAN0_RX11_SIZE 0x00000020u +#define CYREG_CAN0_RX11_CMD 0x4000a200u +#define CYREG_CAN0_RX11_ID 0x4000a204u +#define CYREG_CAN0_RX11_DH 0x4000a208u +#define CYREG_CAN0_RX11_DL 0x4000a20cu +#define CYREG_CAN0_RX11_AMR 0x4000a210u +#define CYREG_CAN0_RX11_ACR 0x4000a214u +#define CYREG_CAN0_RX11_AMRD 0x4000a218u +#define CYREG_CAN0_RX11_ACRD 0x4000a21cu +#define CYDEV_CAN0_RX12_BASE 0x4000a220u +#define CYDEV_CAN0_RX12_SIZE 0x00000020u +#define CYREG_CAN0_RX12_CMD 0x4000a220u +#define CYREG_CAN0_RX12_ID 0x4000a224u +#define CYREG_CAN0_RX12_DH 0x4000a228u +#define CYREG_CAN0_RX12_DL 0x4000a22cu +#define CYREG_CAN0_RX12_AMR 0x4000a230u +#define CYREG_CAN0_RX12_ACR 0x4000a234u +#define CYREG_CAN0_RX12_AMRD 0x4000a238u +#define CYREG_CAN0_RX12_ACRD 0x4000a23cu +#define CYDEV_CAN0_RX13_BASE 0x4000a240u +#define CYDEV_CAN0_RX13_SIZE 0x00000020u +#define CYREG_CAN0_RX13_CMD 0x4000a240u +#define CYREG_CAN0_RX13_ID 0x4000a244u +#define CYREG_CAN0_RX13_DH 0x4000a248u +#define CYREG_CAN0_RX13_DL 0x4000a24cu +#define CYREG_CAN0_RX13_AMR 0x4000a250u +#define CYREG_CAN0_RX13_ACR 0x4000a254u +#define CYREG_CAN0_RX13_AMRD 0x4000a258u +#define CYREG_CAN0_RX13_ACRD 0x4000a25cu +#define CYDEV_CAN0_RX14_BASE 0x4000a260u +#define CYDEV_CAN0_RX14_SIZE 0x00000020u +#define CYREG_CAN0_RX14_CMD 0x4000a260u +#define CYREG_CAN0_RX14_ID 0x4000a264u +#define CYREG_CAN0_RX14_DH 0x4000a268u +#define CYREG_CAN0_RX14_DL 0x4000a26cu +#define CYREG_CAN0_RX14_AMR 0x4000a270u +#define CYREG_CAN0_RX14_ACR 0x4000a274u +#define CYREG_CAN0_RX14_AMRD 0x4000a278u +#define CYREG_CAN0_RX14_ACRD 0x4000a27cu +#define CYDEV_CAN0_RX15_BASE 0x4000a280u +#define CYDEV_CAN0_RX15_SIZE 0x00000020u +#define CYREG_CAN0_RX15_CMD 0x4000a280u +#define CYREG_CAN0_RX15_ID 0x4000a284u +#define CYREG_CAN0_RX15_DH 0x4000a288u +#define CYREG_CAN0_RX15_DL 0x4000a28cu +#define CYREG_CAN0_RX15_AMR 0x4000a290u +#define CYREG_CAN0_RX15_ACR 0x4000a294u +#define CYREG_CAN0_RX15_AMRD 0x4000a298u +#define CYREG_CAN0_RX15_ACRD 0x4000a29cu +#define CYDEV_DFB0_BASE 0x4000c000u +#define CYDEV_DFB0_SIZE 0x000007b5u +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000u +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000u +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200u +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200u +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200u +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200u +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400u +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400u +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500u +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500u +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600u +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100u +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600u +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100u +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700u +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040u +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700u +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040u +#define CYREG_DFB0_CR 0x4000c780u +#define CYREG_DFB0_SR 0x4000c784u +#define CYREG_DFB0_RAM_EN 0x4000c788u +#define CYREG_DFB0_RAM_DIR 0x4000c78cu +#define CYREG_DFB0_SEMA 0x4000c790u +#define CYREG_DFB0_DSI_CTRL 0x4000c794u +#define CYREG_DFB0_INT_CTRL 0x4000c798u +#define CYREG_DFB0_DMA_CTRL 0x4000c79cu +#define CYREG_DFB0_STAGEA 0x4000c7a0u +#define CYREG_DFB0_STAGEAM 0x4000c7a1u +#define CYREG_DFB0_STAGEAH 0x4000c7a2u +#define CYREG_DFB0_STAGEB 0x4000c7a4u +#define CYREG_DFB0_STAGEBM 0x4000c7a5u +#define CYREG_DFB0_STAGEBH 0x4000c7a6u +#define CYREG_DFB0_HOLDA 0x4000c7a8u +#define CYREG_DFB0_HOLDAM 0x4000c7a9u +#define CYREG_DFB0_HOLDAH 0x4000c7aau +#define CYREG_DFB0_HOLDAS 0x4000c7abu +#define CYREG_DFB0_HOLDB 0x4000c7acu +#define CYREG_DFB0_HOLDBM 0x4000c7adu +#define CYREG_DFB0_HOLDBH 0x4000c7aeu +#define CYREG_DFB0_HOLDBS 0x4000c7afu +#define CYREG_DFB0_COHER 0x4000c7b0u +#define CYREG_DFB0_DALIGN 0x4000c7b4u +#define CYDEV_UCFG_BASE 0x40010000u +#define CYDEV_UCFG_SIZE 0x00005040u +#define CYDEV_UCFG_B0_BASE 0x40010000u +#define CYDEV_UCFG_B0_SIZE 0x00000fefu +#define CYDEV_UCFG_B0_P0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000u +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070u +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000u +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004u +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008u +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000cu +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010u +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014u +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018u +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001cu +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020u +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024u +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028u +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002cu +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030u +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032u +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034u +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036u +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038u +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003au +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003cu +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003eu +#define CYREG_B0_P0_U0_CFG0 0x40010040u +#define CYREG_B0_P0_U0_CFG1 0x40010041u +#define CYREG_B0_P0_U0_CFG2 0x40010042u +#define CYREG_B0_P0_U0_CFG3 0x40010043u +#define CYREG_B0_P0_U0_CFG4 0x40010044u +#define CYREG_B0_P0_U0_CFG5 0x40010045u +#define CYREG_B0_P0_U0_CFG6 0x40010046u +#define CYREG_B0_P0_U0_CFG7 0x40010047u +#define CYREG_B0_P0_U0_CFG8 0x40010048u +#define CYREG_B0_P0_U0_CFG9 0x40010049u +#define CYREG_B0_P0_U0_CFG10 0x4001004au +#define CYREG_B0_P0_U0_CFG11 0x4001004bu +#define CYREG_B0_P0_U0_CFG12 0x4001004cu +#define CYREG_B0_P0_U0_CFG13 0x4001004du +#define CYREG_B0_P0_U0_CFG14 0x4001004eu +#define CYREG_B0_P0_U0_CFG15 0x4001004fu +#define CYREG_B0_P0_U0_CFG16 0x40010050u +#define CYREG_B0_P0_U0_CFG17 0x40010051u +#define CYREG_B0_P0_U0_CFG18 0x40010052u +#define CYREG_B0_P0_U0_CFG19 0x40010053u +#define CYREG_B0_P0_U0_CFG20 0x40010054u +#define CYREG_B0_P0_U0_CFG21 0x40010055u +#define CYREG_B0_P0_U0_CFG22 0x40010056u +#define CYREG_B0_P0_U0_CFG23 0x40010057u +#define CYREG_B0_P0_U0_CFG24 0x40010058u +#define CYREG_B0_P0_U0_CFG25 0x40010059u +#define CYREG_B0_P0_U0_CFG26 0x4001005au +#define CYREG_B0_P0_U0_CFG27 0x4001005bu +#define CYREG_B0_P0_U0_CFG28 0x4001005cu +#define CYREG_B0_P0_U0_CFG29 0x4001005du +#define CYREG_B0_P0_U0_CFG30 0x4001005eu +#define CYREG_B0_P0_U0_CFG31 0x4001005fu +#define CYREG_B0_P0_U0_DCFG0 0x40010060u +#define CYREG_B0_P0_U0_DCFG1 0x40010062u +#define CYREG_B0_P0_U0_DCFG2 0x40010064u +#define CYREG_B0_P0_U0_DCFG3 0x40010066u +#define CYREG_B0_P0_U0_DCFG4 0x40010068u +#define CYREG_B0_P0_U0_DCFG5 0x4001006au +#define CYREG_B0_P0_U0_DCFG6 0x4001006cu +#define CYREG_B0_P0_U0_DCFG7 0x4001006eu +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080u +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070u +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080u +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084u +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088u +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008cu +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090u +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094u +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098u +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009cu +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0u +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4u +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8u +#define CYREG_B0_P0_U1_PLD_IT11 0x400100acu +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0u +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2u +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4u +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6u +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8u +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100bau +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bcu +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100beu +#define CYREG_B0_P0_U1_CFG0 0x400100c0u +#define CYREG_B0_P0_U1_CFG1 0x400100c1u +#define CYREG_B0_P0_U1_CFG2 0x400100c2u +#define CYREG_B0_P0_U1_CFG3 0x400100c3u +#define CYREG_B0_P0_U1_CFG4 0x400100c4u +#define CYREG_B0_P0_U1_CFG5 0x400100c5u +#define CYREG_B0_P0_U1_CFG6 0x400100c6u +#define CYREG_B0_P0_U1_CFG7 0x400100c7u +#define CYREG_B0_P0_U1_CFG8 0x400100c8u +#define CYREG_B0_P0_U1_CFG9 0x400100c9u +#define CYREG_B0_P0_U1_CFG10 0x400100cau +#define CYREG_B0_P0_U1_CFG11 0x400100cbu +#define CYREG_B0_P0_U1_CFG12 0x400100ccu +#define CYREG_B0_P0_U1_CFG13 0x400100cdu +#define CYREG_B0_P0_U1_CFG14 0x400100ceu +#define CYREG_B0_P0_U1_CFG15 0x400100cfu +#define CYREG_B0_P0_U1_CFG16 0x400100d0u +#define CYREG_B0_P0_U1_CFG17 0x400100d1u +#define CYREG_B0_P0_U1_CFG18 0x400100d2u +#define CYREG_B0_P0_U1_CFG19 0x400100d3u +#define CYREG_B0_P0_U1_CFG20 0x400100d4u +#define CYREG_B0_P0_U1_CFG21 0x400100d5u +#define CYREG_B0_P0_U1_CFG22 0x400100d6u +#define CYREG_B0_P0_U1_CFG23 0x400100d7u +#define CYREG_B0_P0_U1_CFG24 0x400100d8u +#define CYREG_B0_P0_U1_CFG25 0x400100d9u +#define CYREG_B0_P0_U1_CFG26 0x400100dau +#define CYREG_B0_P0_U1_CFG27 0x400100dbu +#define CYREG_B0_P0_U1_CFG28 0x400100dcu +#define CYREG_B0_P0_U1_CFG29 0x400100ddu +#define CYREG_B0_P0_U1_CFG30 0x400100deu +#define CYREG_B0_P0_U1_CFG31 0x400100dfu +#define CYREG_B0_P0_U1_DCFG0 0x400100e0u +#define CYREG_B0_P0_U1_DCFG1 0x400100e2u +#define CYREG_B0_P0_U1_DCFG2 0x400100e4u +#define CYREG_B0_P0_U1_DCFG3 0x400100e6u +#define CYREG_B0_P0_U1_DCFG4 0x400100e8u +#define CYREG_B0_P0_U1_DCFG5 0x400100eau +#define CYREG_B0_P0_U1_DCFG6 0x400100ecu +#define CYREG_B0_P0_U1_DCFG7 0x400100eeu +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100u +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P1_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200u +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070u +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200u +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204u +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208u +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020cu +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210u +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214u +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218u +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021cu +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220u +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224u +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228u +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022cu +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230u +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232u +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234u +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236u +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238u +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023au +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023cu +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023eu +#define CYREG_B0_P1_U0_CFG0 0x40010240u +#define CYREG_B0_P1_U0_CFG1 0x40010241u +#define CYREG_B0_P1_U0_CFG2 0x40010242u +#define CYREG_B0_P1_U0_CFG3 0x40010243u +#define CYREG_B0_P1_U0_CFG4 0x40010244u +#define CYREG_B0_P1_U0_CFG5 0x40010245u +#define CYREG_B0_P1_U0_CFG6 0x40010246u +#define CYREG_B0_P1_U0_CFG7 0x40010247u +#define CYREG_B0_P1_U0_CFG8 0x40010248u +#define CYREG_B0_P1_U0_CFG9 0x40010249u +#define CYREG_B0_P1_U0_CFG10 0x4001024au +#define CYREG_B0_P1_U0_CFG11 0x4001024bu +#define CYREG_B0_P1_U0_CFG12 0x4001024cu +#define CYREG_B0_P1_U0_CFG13 0x4001024du +#define CYREG_B0_P1_U0_CFG14 0x4001024eu +#define CYREG_B0_P1_U0_CFG15 0x4001024fu +#define CYREG_B0_P1_U0_CFG16 0x40010250u +#define CYREG_B0_P1_U0_CFG17 0x40010251u +#define CYREG_B0_P1_U0_CFG18 0x40010252u +#define CYREG_B0_P1_U0_CFG19 0x40010253u +#define CYREG_B0_P1_U0_CFG20 0x40010254u +#define CYREG_B0_P1_U0_CFG21 0x40010255u +#define CYREG_B0_P1_U0_CFG22 0x40010256u +#define CYREG_B0_P1_U0_CFG23 0x40010257u +#define CYREG_B0_P1_U0_CFG24 0x40010258u +#define CYREG_B0_P1_U0_CFG25 0x40010259u +#define CYREG_B0_P1_U0_CFG26 0x4001025au +#define CYREG_B0_P1_U0_CFG27 0x4001025bu +#define CYREG_B0_P1_U0_CFG28 0x4001025cu +#define CYREG_B0_P1_U0_CFG29 0x4001025du +#define CYREG_B0_P1_U0_CFG30 0x4001025eu +#define CYREG_B0_P1_U0_CFG31 0x4001025fu +#define CYREG_B0_P1_U0_DCFG0 0x40010260u +#define CYREG_B0_P1_U0_DCFG1 0x40010262u +#define CYREG_B0_P1_U0_DCFG2 0x40010264u +#define CYREG_B0_P1_U0_DCFG3 0x40010266u +#define CYREG_B0_P1_U0_DCFG4 0x40010268u +#define CYREG_B0_P1_U0_DCFG5 0x4001026au +#define CYREG_B0_P1_U0_DCFG6 0x4001026cu +#define CYREG_B0_P1_U0_DCFG7 0x4001026eu +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280u +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070u +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280u +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284u +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288u +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028cu +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290u +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294u +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298u +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029cu +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0u +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4u +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8u +#define CYREG_B0_P1_U1_PLD_IT11 0x400102acu +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0u +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2u +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4u +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6u +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8u +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102bau +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bcu +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102beu +#define CYREG_B0_P1_U1_CFG0 0x400102c0u +#define CYREG_B0_P1_U1_CFG1 0x400102c1u +#define CYREG_B0_P1_U1_CFG2 0x400102c2u +#define CYREG_B0_P1_U1_CFG3 0x400102c3u +#define CYREG_B0_P1_U1_CFG4 0x400102c4u +#define CYREG_B0_P1_U1_CFG5 0x400102c5u +#define CYREG_B0_P1_U1_CFG6 0x400102c6u +#define CYREG_B0_P1_U1_CFG7 0x400102c7u +#define CYREG_B0_P1_U1_CFG8 0x400102c8u +#define CYREG_B0_P1_U1_CFG9 0x400102c9u +#define CYREG_B0_P1_U1_CFG10 0x400102cau +#define CYREG_B0_P1_U1_CFG11 0x400102cbu +#define CYREG_B0_P1_U1_CFG12 0x400102ccu +#define CYREG_B0_P1_U1_CFG13 0x400102cdu +#define CYREG_B0_P1_U1_CFG14 0x400102ceu +#define CYREG_B0_P1_U1_CFG15 0x400102cfu +#define CYREG_B0_P1_U1_CFG16 0x400102d0u +#define CYREG_B0_P1_U1_CFG17 0x400102d1u +#define CYREG_B0_P1_U1_CFG18 0x400102d2u +#define CYREG_B0_P1_U1_CFG19 0x400102d3u +#define CYREG_B0_P1_U1_CFG20 0x400102d4u +#define CYREG_B0_P1_U1_CFG21 0x400102d5u +#define CYREG_B0_P1_U1_CFG22 0x400102d6u +#define CYREG_B0_P1_U1_CFG23 0x400102d7u +#define CYREG_B0_P1_U1_CFG24 0x400102d8u +#define CYREG_B0_P1_U1_CFG25 0x400102d9u +#define CYREG_B0_P1_U1_CFG26 0x400102dau +#define CYREG_B0_P1_U1_CFG27 0x400102dbu +#define CYREG_B0_P1_U1_CFG28 0x400102dcu +#define CYREG_B0_P1_U1_CFG29 0x400102ddu +#define CYREG_B0_P1_U1_CFG30 0x400102deu +#define CYREG_B0_P1_U1_CFG31 0x400102dfu +#define CYREG_B0_P1_U1_DCFG0 0x400102e0u +#define CYREG_B0_P1_U1_DCFG1 0x400102e2u +#define CYREG_B0_P1_U1_DCFG2 0x400102e4u +#define CYREG_B0_P1_U1_DCFG3 0x400102e6u +#define CYREG_B0_P1_U1_DCFG4 0x400102e8u +#define CYREG_B0_P1_U1_DCFG5 0x400102eau +#define CYREG_B0_P1_U1_DCFG6 0x400102ecu +#define CYREG_B0_P1_U1_DCFG7 0x400102eeu +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300u +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P2_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400u +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070u +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400u +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404u +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408u +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040cu +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410u +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414u +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418u +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041cu +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420u +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424u +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428u +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042cu +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430u +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432u +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434u +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436u +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438u +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043au +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043cu +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043eu +#define CYREG_B0_P2_U0_CFG0 0x40010440u +#define CYREG_B0_P2_U0_CFG1 0x40010441u +#define CYREG_B0_P2_U0_CFG2 0x40010442u +#define CYREG_B0_P2_U0_CFG3 0x40010443u +#define CYREG_B0_P2_U0_CFG4 0x40010444u +#define CYREG_B0_P2_U0_CFG5 0x40010445u +#define CYREG_B0_P2_U0_CFG6 0x40010446u +#define CYREG_B0_P2_U0_CFG7 0x40010447u +#define CYREG_B0_P2_U0_CFG8 0x40010448u +#define CYREG_B0_P2_U0_CFG9 0x40010449u +#define CYREG_B0_P2_U0_CFG10 0x4001044au +#define CYREG_B0_P2_U0_CFG11 0x4001044bu +#define CYREG_B0_P2_U0_CFG12 0x4001044cu +#define CYREG_B0_P2_U0_CFG13 0x4001044du +#define CYREG_B0_P2_U0_CFG14 0x4001044eu +#define CYREG_B0_P2_U0_CFG15 0x4001044fu +#define CYREG_B0_P2_U0_CFG16 0x40010450u +#define CYREG_B0_P2_U0_CFG17 0x40010451u +#define CYREG_B0_P2_U0_CFG18 0x40010452u +#define CYREG_B0_P2_U0_CFG19 0x40010453u +#define CYREG_B0_P2_U0_CFG20 0x40010454u +#define CYREG_B0_P2_U0_CFG21 0x40010455u +#define CYREG_B0_P2_U0_CFG22 0x40010456u +#define CYREG_B0_P2_U0_CFG23 0x40010457u +#define CYREG_B0_P2_U0_CFG24 0x40010458u +#define CYREG_B0_P2_U0_CFG25 0x40010459u +#define CYREG_B0_P2_U0_CFG26 0x4001045au +#define CYREG_B0_P2_U0_CFG27 0x4001045bu +#define CYREG_B0_P2_U0_CFG28 0x4001045cu +#define CYREG_B0_P2_U0_CFG29 0x4001045du +#define CYREG_B0_P2_U0_CFG30 0x4001045eu +#define CYREG_B0_P2_U0_CFG31 0x4001045fu +#define CYREG_B0_P2_U0_DCFG0 0x40010460u +#define CYREG_B0_P2_U0_DCFG1 0x40010462u +#define CYREG_B0_P2_U0_DCFG2 0x40010464u +#define CYREG_B0_P2_U0_DCFG3 0x40010466u +#define CYREG_B0_P2_U0_DCFG4 0x40010468u +#define CYREG_B0_P2_U0_DCFG5 0x4001046au +#define CYREG_B0_P2_U0_DCFG6 0x4001046cu +#define CYREG_B0_P2_U0_DCFG7 0x4001046eu +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480u +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070u +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480u +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484u +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488u +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048cu +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490u +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494u +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498u +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049cu +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0u +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4u +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8u +#define CYREG_B0_P2_U1_PLD_IT11 0x400104acu +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0u +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2u +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4u +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6u +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8u +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104bau +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bcu +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104beu +#define CYREG_B0_P2_U1_CFG0 0x400104c0u +#define CYREG_B0_P2_U1_CFG1 0x400104c1u +#define CYREG_B0_P2_U1_CFG2 0x400104c2u +#define CYREG_B0_P2_U1_CFG3 0x400104c3u +#define CYREG_B0_P2_U1_CFG4 0x400104c4u +#define CYREG_B0_P2_U1_CFG5 0x400104c5u +#define CYREG_B0_P2_U1_CFG6 0x400104c6u +#define CYREG_B0_P2_U1_CFG7 0x400104c7u +#define CYREG_B0_P2_U1_CFG8 0x400104c8u +#define CYREG_B0_P2_U1_CFG9 0x400104c9u +#define CYREG_B0_P2_U1_CFG10 0x400104cau +#define CYREG_B0_P2_U1_CFG11 0x400104cbu +#define CYREG_B0_P2_U1_CFG12 0x400104ccu +#define CYREG_B0_P2_U1_CFG13 0x400104cdu +#define CYREG_B0_P2_U1_CFG14 0x400104ceu +#define CYREG_B0_P2_U1_CFG15 0x400104cfu +#define CYREG_B0_P2_U1_CFG16 0x400104d0u +#define CYREG_B0_P2_U1_CFG17 0x400104d1u +#define CYREG_B0_P2_U1_CFG18 0x400104d2u +#define CYREG_B0_P2_U1_CFG19 0x400104d3u +#define CYREG_B0_P2_U1_CFG20 0x400104d4u +#define CYREG_B0_P2_U1_CFG21 0x400104d5u +#define CYREG_B0_P2_U1_CFG22 0x400104d6u +#define CYREG_B0_P2_U1_CFG23 0x400104d7u +#define CYREG_B0_P2_U1_CFG24 0x400104d8u +#define CYREG_B0_P2_U1_CFG25 0x400104d9u +#define CYREG_B0_P2_U1_CFG26 0x400104dau +#define CYREG_B0_P2_U1_CFG27 0x400104dbu +#define CYREG_B0_P2_U1_CFG28 0x400104dcu +#define CYREG_B0_P2_U1_CFG29 0x400104ddu +#define CYREG_B0_P2_U1_CFG30 0x400104deu +#define CYREG_B0_P2_U1_CFG31 0x400104dfu +#define CYREG_B0_P2_U1_DCFG0 0x400104e0u +#define CYREG_B0_P2_U1_DCFG1 0x400104e2u +#define CYREG_B0_P2_U1_DCFG2 0x400104e4u +#define CYREG_B0_P2_U1_DCFG3 0x400104e6u +#define CYREG_B0_P2_U1_DCFG4 0x400104e8u +#define CYREG_B0_P2_U1_DCFG5 0x400104eau +#define CYREG_B0_P2_U1_DCFG6 0x400104ecu +#define CYREG_B0_P2_U1_DCFG7 0x400104eeu +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500u +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P3_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600u +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070u +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600u +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604u +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608u +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060cu +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610u +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614u +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618u +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061cu +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620u +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624u +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628u +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062cu +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630u +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632u +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634u +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636u +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638u +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063au +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063cu +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063eu +#define CYREG_B0_P3_U0_CFG0 0x40010640u +#define CYREG_B0_P3_U0_CFG1 0x40010641u +#define CYREG_B0_P3_U0_CFG2 0x40010642u +#define CYREG_B0_P3_U0_CFG3 0x40010643u +#define CYREG_B0_P3_U0_CFG4 0x40010644u +#define CYREG_B0_P3_U0_CFG5 0x40010645u +#define CYREG_B0_P3_U0_CFG6 0x40010646u +#define CYREG_B0_P3_U0_CFG7 0x40010647u +#define CYREG_B0_P3_U0_CFG8 0x40010648u +#define CYREG_B0_P3_U0_CFG9 0x40010649u +#define CYREG_B0_P3_U0_CFG10 0x4001064au +#define CYREG_B0_P3_U0_CFG11 0x4001064bu +#define CYREG_B0_P3_U0_CFG12 0x4001064cu +#define CYREG_B0_P3_U0_CFG13 0x4001064du +#define CYREG_B0_P3_U0_CFG14 0x4001064eu +#define CYREG_B0_P3_U0_CFG15 0x4001064fu +#define CYREG_B0_P3_U0_CFG16 0x40010650u +#define CYREG_B0_P3_U0_CFG17 0x40010651u +#define CYREG_B0_P3_U0_CFG18 0x40010652u +#define CYREG_B0_P3_U0_CFG19 0x40010653u +#define CYREG_B0_P3_U0_CFG20 0x40010654u +#define CYREG_B0_P3_U0_CFG21 0x40010655u +#define CYREG_B0_P3_U0_CFG22 0x40010656u +#define CYREG_B0_P3_U0_CFG23 0x40010657u +#define CYREG_B0_P3_U0_CFG24 0x40010658u +#define CYREG_B0_P3_U0_CFG25 0x40010659u +#define CYREG_B0_P3_U0_CFG26 0x4001065au +#define CYREG_B0_P3_U0_CFG27 0x4001065bu +#define CYREG_B0_P3_U0_CFG28 0x4001065cu +#define CYREG_B0_P3_U0_CFG29 0x4001065du +#define CYREG_B0_P3_U0_CFG30 0x4001065eu +#define CYREG_B0_P3_U0_CFG31 0x4001065fu +#define CYREG_B0_P3_U0_DCFG0 0x40010660u +#define CYREG_B0_P3_U0_DCFG1 0x40010662u +#define CYREG_B0_P3_U0_DCFG2 0x40010664u +#define CYREG_B0_P3_U0_DCFG3 0x40010666u +#define CYREG_B0_P3_U0_DCFG4 0x40010668u +#define CYREG_B0_P3_U0_DCFG5 0x4001066au +#define CYREG_B0_P3_U0_DCFG6 0x4001066cu +#define CYREG_B0_P3_U0_DCFG7 0x4001066eu +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680u +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070u +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680u +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684u +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688u +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068cu +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690u +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694u +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698u +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069cu +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0u +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4u +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8u +#define CYREG_B0_P3_U1_PLD_IT11 0x400106acu +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0u +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2u +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4u +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6u +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8u +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106bau +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bcu +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106beu +#define CYREG_B0_P3_U1_CFG0 0x400106c0u +#define CYREG_B0_P3_U1_CFG1 0x400106c1u +#define CYREG_B0_P3_U1_CFG2 0x400106c2u +#define CYREG_B0_P3_U1_CFG3 0x400106c3u +#define CYREG_B0_P3_U1_CFG4 0x400106c4u +#define CYREG_B0_P3_U1_CFG5 0x400106c5u +#define CYREG_B0_P3_U1_CFG6 0x400106c6u +#define CYREG_B0_P3_U1_CFG7 0x400106c7u +#define CYREG_B0_P3_U1_CFG8 0x400106c8u +#define CYREG_B0_P3_U1_CFG9 0x400106c9u +#define CYREG_B0_P3_U1_CFG10 0x400106cau +#define CYREG_B0_P3_U1_CFG11 0x400106cbu +#define CYREG_B0_P3_U1_CFG12 0x400106ccu +#define CYREG_B0_P3_U1_CFG13 0x400106cdu +#define CYREG_B0_P3_U1_CFG14 0x400106ceu +#define CYREG_B0_P3_U1_CFG15 0x400106cfu +#define CYREG_B0_P3_U1_CFG16 0x400106d0u +#define CYREG_B0_P3_U1_CFG17 0x400106d1u +#define CYREG_B0_P3_U1_CFG18 0x400106d2u +#define CYREG_B0_P3_U1_CFG19 0x400106d3u +#define CYREG_B0_P3_U1_CFG20 0x400106d4u +#define CYREG_B0_P3_U1_CFG21 0x400106d5u +#define CYREG_B0_P3_U1_CFG22 0x400106d6u +#define CYREG_B0_P3_U1_CFG23 0x400106d7u +#define CYREG_B0_P3_U1_CFG24 0x400106d8u +#define CYREG_B0_P3_U1_CFG25 0x400106d9u +#define CYREG_B0_P3_U1_CFG26 0x400106dau +#define CYREG_B0_P3_U1_CFG27 0x400106dbu +#define CYREG_B0_P3_U1_CFG28 0x400106dcu +#define CYREG_B0_P3_U1_CFG29 0x400106ddu +#define CYREG_B0_P3_U1_CFG30 0x400106deu +#define CYREG_B0_P3_U1_CFG31 0x400106dfu +#define CYREG_B0_P3_U1_DCFG0 0x400106e0u +#define CYREG_B0_P3_U1_DCFG1 0x400106e2u +#define CYREG_B0_P3_U1_DCFG2 0x400106e4u +#define CYREG_B0_P3_U1_DCFG3 0x400106e6u +#define CYREG_B0_P3_U1_DCFG4 0x400106e8u +#define CYREG_B0_P3_U1_DCFG5 0x400106eau +#define CYREG_B0_P3_U1_DCFG6 0x400106ecu +#define CYREG_B0_P3_U1_DCFG7 0x400106eeu +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700u +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P4_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800u +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070u +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800u +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804u +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808u +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080cu +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810u +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814u +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818u +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081cu +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820u +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824u +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828u +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082cu +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830u +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832u +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834u +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836u +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838u +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083au +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083cu +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083eu +#define CYREG_B0_P4_U0_CFG0 0x40010840u +#define CYREG_B0_P4_U0_CFG1 0x40010841u +#define CYREG_B0_P4_U0_CFG2 0x40010842u +#define CYREG_B0_P4_U0_CFG3 0x40010843u +#define CYREG_B0_P4_U0_CFG4 0x40010844u +#define CYREG_B0_P4_U0_CFG5 0x40010845u +#define CYREG_B0_P4_U0_CFG6 0x40010846u +#define CYREG_B0_P4_U0_CFG7 0x40010847u +#define CYREG_B0_P4_U0_CFG8 0x40010848u +#define CYREG_B0_P4_U0_CFG9 0x40010849u +#define CYREG_B0_P4_U0_CFG10 0x4001084au +#define CYREG_B0_P4_U0_CFG11 0x4001084bu +#define CYREG_B0_P4_U0_CFG12 0x4001084cu +#define CYREG_B0_P4_U0_CFG13 0x4001084du +#define CYREG_B0_P4_U0_CFG14 0x4001084eu +#define CYREG_B0_P4_U0_CFG15 0x4001084fu +#define CYREG_B0_P4_U0_CFG16 0x40010850u +#define CYREG_B0_P4_U0_CFG17 0x40010851u +#define CYREG_B0_P4_U0_CFG18 0x40010852u +#define CYREG_B0_P4_U0_CFG19 0x40010853u +#define CYREG_B0_P4_U0_CFG20 0x40010854u +#define CYREG_B0_P4_U0_CFG21 0x40010855u +#define CYREG_B0_P4_U0_CFG22 0x40010856u +#define CYREG_B0_P4_U0_CFG23 0x40010857u +#define CYREG_B0_P4_U0_CFG24 0x40010858u +#define CYREG_B0_P4_U0_CFG25 0x40010859u +#define CYREG_B0_P4_U0_CFG26 0x4001085au +#define CYREG_B0_P4_U0_CFG27 0x4001085bu +#define CYREG_B0_P4_U0_CFG28 0x4001085cu +#define CYREG_B0_P4_U0_CFG29 0x4001085du +#define CYREG_B0_P4_U0_CFG30 0x4001085eu +#define CYREG_B0_P4_U0_CFG31 0x4001085fu +#define CYREG_B0_P4_U0_DCFG0 0x40010860u +#define CYREG_B0_P4_U0_DCFG1 0x40010862u +#define CYREG_B0_P4_U0_DCFG2 0x40010864u +#define CYREG_B0_P4_U0_DCFG3 0x40010866u +#define CYREG_B0_P4_U0_DCFG4 0x40010868u +#define CYREG_B0_P4_U0_DCFG5 0x4001086au +#define CYREG_B0_P4_U0_DCFG6 0x4001086cu +#define CYREG_B0_P4_U0_DCFG7 0x4001086eu +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880u +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070u +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880u +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884u +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888u +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088cu +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890u +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894u +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898u +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089cu +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0u +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4u +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8u +#define CYREG_B0_P4_U1_PLD_IT11 0x400108acu +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0u +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2u +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4u +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6u +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8u +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108bau +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bcu +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108beu +#define CYREG_B0_P4_U1_CFG0 0x400108c0u +#define CYREG_B0_P4_U1_CFG1 0x400108c1u +#define CYREG_B0_P4_U1_CFG2 0x400108c2u +#define CYREG_B0_P4_U1_CFG3 0x400108c3u +#define CYREG_B0_P4_U1_CFG4 0x400108c4u +#define CYREG_B0_P4_U1_CFG5 0x400108c5u +#define CYREG_B0_P4_U1_CFG6 0x400108c6u +#define CYREG_B0_P4_U1_CFG7 0x400108c7u +#define CYREG_B0_P4_U1_CFG8 0x400108c8u +#define CYREG_B0_P4_U1_CFG9 0x400108c9u +#define CYREG_B0_P4_U1_CFG10 0x400108cau +#define CYREG_B0_P4_U1_CFG11 0x400108cbu +#define CYREG_B0_P4_U1_CFG12 0x400108ccu +#define CYREG_B0_P4_U1_CFG13 0x400108cdu +#define CYREG_B0_P4_U1_CFG14 0x400108ceu +#define CYREG_B0_P4_U1_CFG15 0x400108cfu +#define CYREG_B0_P4_U1_CFG16 0x400108d0u +#define CYREG_B0_P4_U1_CFG17 0x400108d1u +#define CYREG_B0_P4_U1_CFG18 0x400108d2u +#define CYREG_B0_P4_U1_CFG19 0x400108d3u +#define CYREG_B0_P4_U1_CFG20 0x400108d4u +#define CYREG_B0_P4_U1_CFG21 0x400108d5u +#define CYREG_B0_P4_U1_CFG22 0x400108d6u +#define CYREG_B0_P4_U1_CFG23 0x400108d7u +#define CYREG_B0_P4_U1_CFG24 0x400108d8u +#define CYREG_B0_P4_U1_CFG25 0x400108d9u +#define CYREG_B0_P4_U1_CFG26 0x400108dau +#define CYREG_B0_P4_U1_CFG27 0x400108dbu +#define CYREG_B0_P4_U1_CFG28 0x400108dcu +#define CYREG_B0_P4_U1_CFG29 0x400108ddu +#define CYREG_B0_P4_U1_CFG30 0x400108deu +#define CYREG_B0_P4_U1_CFG31 0x400108dfu +#define CYREG_B0_P4_U1_DCFG0 0x400108e0u +#define CYREG_B0_P4_U1_DCFG1 0x400108e2u +#define CYREG_B0_P4_U1_DCFG2 0x400108e4u +#define CYREG_B0_P4_U1_DCFG3 0x400108e6u +#define CYREG_B0_P4_U1_DCFG4 0x400108e8u +#define CYREG_B0_P4_U1_DCFG5 0x400108eau +#define CYREG_B0_P4_U1_DCFG6 0x400108ecu +#define CYREG_B0_P4_U1_DCFG7 0x400108eeu +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900u +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00u +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070u +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00u +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04u +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08u +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0cu +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10u +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14u +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18u +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1cu +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20u +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24u +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28u +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2cu +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30u +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32u +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34u +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36u +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38u +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3au +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3cu +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3eu +#define CYREG_B0_P5_U0_CFG0 0x40010a40u +#define CYREG_B0_P5_U0_CFG1 0x40010a41u +#define CYREG_B0_P5_U0_CFG2 0x40010a42u +#define CYREG_B0_P5_U0_CFG3 0x40010a43u +#define CYREG_B0_P5_U0_CFG4 0x40010a44u +#define CYREG_B0_P5_U0_CFG5 0x40010a45u +#define CYREG_B0_P5_U0_CFG6 0x40010a46u +#define CYREG_B0_P5_U0_CFG7 0x40010a47u +#define CYREG_B0_P5_U0_CFG8 0x40010a48u +#define CYREG_B0_P5_U0_CFG9 0x40010a49u +#define CYREG_B0_P5_U0_CFG10 0x40010a4au +#define CYREG_B0_P5_U0_CFG11 0x40010a4bu +#define CYREG_B0_P5_U0_CFG12 0x40010a4cu +#define CYREG_B0_P5_U0_CFG13 0x40010a4du +#define CYREG_B0_P5_U0_CFG14 0x40010a4eu +#define CYREG_B0_P5_U0_CFG15 0x40010a4fu +#define CYREG_B0_P5_U0_CFG16 0x40010a50u +#define CYREG_B0_P5_U0_CFG17 0x40010a51u +#define CYREG_B0_P5_U0_CFG18 0x40010a52u +#define CYREG_B0_P5_U0_CFG19 0x40010a53u +#define CYREG_B0_P5_U0_CFG20 0x40010a54u +#define CYREG_B0_P5_U0_CFG21 0x40010a55u +#define CYREG_B0_P5_U0_CFG22 0x40010a56u +#define CYREG_B0_P5_U0_CFG23 0x40010a57u +#define CYREG_B0_P5_U0_CFG24 0x40010a58u +#define CYREG_B0_P5_U0_CFG25 0x40010a59u +#define CYREG_B0_P5_U0_CFG26 0x40010a5au +#define CYREG_B0_P5_U0_CFG27 0x40010a5bu +#define CYREG_B0_P5_U0_CFG28 0x40010a5cu +#define CYREG_B0_P5_U0_CFG29 0x40010a5du +#define CYREG_B0_P5_U0_CFG30 0x40010a5eu +#define CYREG_B0_P5_U0_CFG31 0x40010a5fu +#define CYREG_B0_P5_U0_DCFG0 0x40010a60u +#define CYREG_B0_P5_U0_DCFG1 0x40010a62u +#define CYREG_B0_P5_U0_DCFG2 0x40010a64u +#define CYREG_B0_P5_U0_DCFG3 0x40010a66u +#define CYREG_B0_P5_U0_DCFG4 0x40010a68u +#define CYREG_B0_P5_U0_DCFG5 0x40010a6au +#define CYREG_B0_P5_U0_DCFG6 0x40010a6cu +#define CYREG_B0_P5_U0_DCFG7 0x40010a6eu +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80u +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070u +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80u +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84u +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88u +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8cu +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90u +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94u +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98u +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9cu +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0u +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4u +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8u +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aacu +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0u +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2u +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4u +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6u +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8u +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010abau +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abcu +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abeu +#define CYREG_B0_P5_U1_CFG0 0x40010ac0u +#define CYREG_B0_P5_U1_CFG1 0x40010ac1u +#define CYREG_B0_P5_U1_CFG2 0x40010ac2u +#define CYREG_B0_P5_U1_CFG3 0x40010ac3u +#define CYREG_B0_P5_U1_CFG4 0x40010ac4u +#define CYREG_B0_P5_U1_CFG5 0x40010ac5u +#define CYREG_B0_P5_U1_CFG6 0x40010ac6u +#define CYREG_B0_P5_U1_CFG7 0x40010ac7u +#define CYREG_B0_P5_U1_CFG8 0x40010ac8u +#define CYREG_B0_P5_U1_CFG9 0x40010ac9u +#define CYREG_B0_P5_U1_CFG10 0x40010acau +#define CYREG_B0_P5_U1_CFG11 0x40010acbu +#define CYREG_B0_P5_U1_CFG12 0x40010accu +#define CYREG_B0_P5_U1_CFG13 0x40010acdu +#define CYREG_B0_P5_U1_CFG14 0x40010aceu +#define CYREG_B0_P5_U1_CFG15 0x40010acfu +#define CYREG_B0_P5_U1_CFG16 0x40010ad0u +#define CYREG_B0_P5_U1_CFG17 0x40010ad1u +#define CYREG_B0_P5_U1_CFG18 0x40010ad2u +#define CYREG_B0_P5_U1_CFG19 0x40010ad3u +#define CYREG_B0_P5_U1_CFG20 0x40010ad4u +#define CYREG_B0_P5_U1_CFG21 0x40010ad5u +#define CYREG_B0_P5_U1_CFG22 0x40010ad6u +#define CYREG_B0_P5_U1_CFG23 0x40010ad7u +#define CYREG_B0_P5_U1_CFG24 0x40010ad8u +#define CYREG_B0_P5_U1_CFG25 0x40010ad9u +#define CYREG_B0_P5_U1_CFG26 0x40010adau +#define CYREG_B0_P5_U1_CFG27 0x40010adbu +#define CYREG_B0_P5_U1_CFG28 0x40010adcu +#define CYREG_B0_P5_U1_CFG29 0x40010addu +#define CYREG_B0_P5_U1_CFG30 0x40010adeu +#define CYREG_B0_P5_U1_CFG31 0x40010adfu +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0u +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2u +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4u +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6u +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8u +#define CYREG_B0_P5_U1_DCFG5 0x40010aeau +#define CYREG_B0_P5_U1_DCFG6 0x40010aecu +#define CYREG_B0_P5_U1_DCFG7 0x40010aeeu +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00u +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00u +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070u +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00u +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04u +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08u +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0cu +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10u +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14u +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18u +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1cu +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20u +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24u +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28u +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2cu +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30u +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32u +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34u +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36u +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38u +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3au +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3cu +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3eu +#define CYREG_B0_P6_U0_CFG0 0x40010c40u +#define CYREG_B0_P6_U0_CFG1 0x40010c41u +#define CYREG_B0_P6_U0_CFG2 0x40010c42u +#define CYREG_B0_P6_U0_CFG3 0x40010c43u +#define CYREG_B0_P6_U0_CFG4 0x40010c44u +#define CYREG_B0_P6_U0_CFG5 0x40010c45u +#define CYREG_B0_P6_U0_CFG6 0x40010c46u +#define CYREG_B0_P6_U0_CFG7 0x40010c47u +#define CYREG_B0_P6_U0_CFG8 0x40010c48u +#define CYREG_B0_P6_U0_CFG9 0x40010c49u +#define CYREG_B0_P6_U0_CFG10 0x40010c4au +#define CYREG_B0_P6_U0_CFG11 0x40010c4bu +#define CYREG_B0_P6_U0_CFG12 0x40010c4cu +#define CYREG_B0_P6_U0_CFG13 0x40010c4du +#define CYREG_B0_P6_U0_CFG14 0x40010c4eu +#define CYREG_B0_P6_U0_CFG15 0x40010c4fu +#define CYREG_B0_P6_U0_CFG16 0x40010c50u +#define CYREG_B0_P6_U0_CFG17 0x40010c51u +#define CYREG_B0_P6_U0_CFG18 0x40010c52u +#define CYREG_B0_P6_U0_CFG19 0x40010c53u +#define CYREG_B0_P6_U0_CFG20 0x40010c54u +#define CYREG_B0_P6_U0_CFG21 0x40010c55u +#define CYREG_B0_P6_U0_CFG22 0x40010c56u +#define CYREG_B0_P6_U0_CFG23 0x40010c57u +#define CYREG_B0_P6_U0_CFG24 0x40010c58u +#define CYREG_B0_P6_U0_CFG25 0x40010c59u +#define CYREG_B0_P6_U0_CFG26 0x40010c5au +#define CYREG_B0_P6_U0_CFG27 0x40010c5bu +#define CYREG_B0_P6_U0_CFG28 0x40010c5cu +#define CYREG_B0_P6_U0_CFG29 0x40010c5du +#define CYREG_B0_P6_U0_CFG30 0x40010c5eu +#define CYREG_B0_P6_U0_CFG31 0x40010c5fu +#define CYREG_B0_P6_U0_DCFG0 0x40010c60u +#define CYREG_B0_P6_U0_DCFG1 0x40010c62u +#define CYREG_B0_P6_U0_DCFG2 0x40010c64u +#define CYREG_B0_P6_U0_DCFG3 0x40010c66u +#define CYREG_B0_P6_U0_DCFG4 0x40010c68u +#define CYREG_B0_P6_U0_DCFG5 0x40010c6au +#define CYREG_B0_P6_U0_DCFG6 0x40010c6cu +#define CYREG_B0_P6_U0_DCFG7 0x40010c6eu +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80u +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070u +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80u +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84u +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88u +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8cu +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90u +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94u +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98u +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9cu +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0u +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4u +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8u +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cacu +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0u +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2u +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4u +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6u +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8u +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cbau +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbcu +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbeu +#define CYREG_B0_P6_U1_CFG0 0x40010cc0u +#define CYREG_B0_P6_U1_CFG1 0x40010cc1u +#define CYREG_B0_P6_U1_CFG2 0x40010cc2u +#define CYREG_B0_P6_U1_CFG3 0x40010cc3u +#define CYREG_B0_P6_U1_CFG4 0x40010cc4u +#define CYREG_B0_P6_U1_CFG5 0x40010cc5u +#define CYREG_B0_P6_U1_CFG6 0x40010cc6u +#define CYREG_B0_P6_U1_CFG7 0x40010cc7u +#define CYREG_B0_P6_U1_CFG8 0x40010cc8u +#define CYREG_B0_P6_U1_CFG9 0x40010cc9u +#define CYREG_B0_P6_U1_CFG10 0x40010ccau +#define CYREG_B0_P6_U1_CFG11 0x40010ccbu +#define CYREG_B0_P6_U1_CFG12 0x40010cccu +#define CYREG_B0_P6_U1_CFG13 0x40010ccdu +#define CYREG_B0_P6_U1_CFG14 0x40010cceu +#define CYREG_B0_P6_U1_CFG15 0x40010ccfu +#define CYREG_B0_P6_U1_CFG16 0x40010cd0u +#define CYREG_B0_P6_U1_CFG17 0x40010cd1u +#define CYREG_B0_P6_U1_CFG18 0x40010cd2u +#define CYREG_B0_P6_U1_CFG19 0x40010cd3u +#define CYREG_B0_P6_U1_CFG20 0x40010cd4u +#define CYREG_B0_P6_U1_CFG21 0x40010cd5u +#define CYREG_B0_P6_U1_CFG22 0x40010cd6u +#define CYREG_B0_P6_U1_CFG23 0x40010cd7u +#define CYREG_B0_P6_U1_CFG24 0x40010cd8u +#define CYREG_B0_P6_U1_CFG25 0x40010cd9u +#define CYREG_B0_P6_U1_CFG26 0x40010cdau +#define CYREG_B0_P6_U1_CFG27 0x40010cdbu +#define CYREG_B0_P6_U1_CFG28 0x40010cdcu +#define CYREG_B0_P6_U1_CFG29 0x40010cddu +#define CYREG_B0_P6_U1_CFG30 0x40010cdeu +#define CYREG_B0_P6_U1_CFG31 0x40010cdfu +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0u +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2u +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4u +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6u +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8u +#define CYREG_B0_P6_U1_DCFG5 0x40010ceau +#define CYREG_B0_P6_U1_DCFG6 0x40010cecu +#define CYREG_B0_P6_U1_DCFG7 0x40010ceeu +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00u +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_SIZE 0x000001efu +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00u +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070u +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00u +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04u +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08u +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0cu +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10u +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14u +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18u +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1cu +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20u +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24u +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28u +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2cu +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30u +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32u +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34u +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36u +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38u +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3au +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3cu +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3eu +#define CYREG_B0_P7_U0_CFG0 0x40010e40u +#define CYREG_B0_P7_U0_CFG1 0x40010e41u +#define CYREG_B0_P7_U0_CFG2 0x40010e42u +#define CYREG_B0_P7_U0_CFG3 0x40010e43u +#define CYREG_B0_P7_U0_CFG4 0x40010e44u +#define CYREG_B0_P7_U0_CFG5 0x40010e45u +#define CYREG_B0_P7_U0_CFG6 0x40010e46u +#define CYREG_B0_P7_U0_CFG7 0x40010e47u +#define CYREG_B0_P7_U0_CFG8 0x40010e48u +#define CYREG_B0_P7_U0_CFG9 0x40010e49u +#define CYREG_B0_P7_U0_CFG10 0x40010e4au +#define CYREG_B0_P7_U0_CFG11 0x40010e4bu +#define CYREG_B0_P7_U0_CFG12 0x40010e4cu +#define CYREG_B0_P7_U0_CFG13 0x40010e4du +#define CYREG_B0_P7_U0_CFG14 0x40010e4eu +#define CYREG_B0_P7_U0_CFG15 0x40010e4fu +#define CYREG_B0_P7_U0_CFG16 0x40010e50u +#define CYREG_B0_P7_U0_CFG17 0x40010e51u +#define CYREG_B0_P7_U0_CFG18 0x40010e52u +#define CYREG_B0_P7_U0_CFG19 0x40010e53u +#define CYREG_B0_P7_U0_CFG20 0x40010e54u +#define CYREG_B0_P7_U0_CFG21 0x40010e55u +#define CYREG_B0_P7_U0_CFG22 0x40010e56u +#define CYREG_B0_P7_U0_CFG23 0x40010e57u +#define CYREG_B0_P7_U0_CFG24 0x40010e58u +#define CYREG_B0_P7_U0_CFG25 0x40010e59u +#define CYREG_B0_P7_U0_CFG26 0x40010e5au +#define CYREG_B0_P7_U0_CFG27 0x40010e5bu +#define CYREG_B0_P7_U0_CFG28 0x40010e5cu +#define CYREG_B0_P7_U0_CFG29 0x40010e5du +#define CYREG_B0_P7_U0_CFG30 0x40010e5eu +#define CYREG_B0_P7_U0_CFG31 0x40010e5fu +#define CYREG_B0_P7_U0_DCFG0 0x40010e60u +#define CYREG_B0_P7_U0_DCFG1 0x40010e62u +#define CYREG_B0_P7_U0_DCFG2 0x40010e64u +#define CYREG_B0_P7_U0_DCFG3 0x40010e66u +#define CYREG_B0_P7_U0_DCFG4 0x40010e68u +#define CYREG_B0_P7_U0_DCFG5 0x40010e6au +#define CYREG_B0_P7_U0_DCFG6 0x40010e6cu +#define CYREG_B0_P7_U0_DCFG7 0x40010e6eu +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80u +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070u +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80u +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84u +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88u +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8cu +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90u +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94u +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98u +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9cu +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0u +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4u +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8u +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eacu +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0u +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2u +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4u +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6u +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8u +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010ebau +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebcu +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebeu +#define CYREG_B0_P7_U1_CFG0 0x40010ec0u +#define CYREG_B0_P7_U1_CFG1 0x40010ec1u +#define CYREG_B0_P7_U1_CFG2 0x40010ec2u +#define CYREG_B0_P7_U1_CFG3 0x40010ec3u +#define CYREG_B0_P7_U1_CFG4 0x40010ec4u +#define CYREG_B0_P7_U1_CFG5 0x40010ec5u +#define CYREG_B0_P7_U1_CFG6 0x40010ec6u +#define CYREG_B0_P7_U1_CFG7 0x40010ec7u +#define CYREG_B0_P7_U1_CFG8 0x40010ec8u +#define CYREG_B0_P7_U1_CFG9 0x40010ec9u +#define CYREG_B0_P7_U1_CFG10 0x40010ecau +#define CYREG_B0_P7_U1_CFG11 0x40010ecbu +#define CYREG_B0_P7_U1_CFG12 0x40010eccu +#define CYREG_B0_P7_U1_CFG13 0x40010ecdu +#define CYREG_B0_P7_U1_CFG14 0x40010eceu +#define CYREG_B0_P7_U1_CFG15 0x40010ecfu +#define CYREG_B0_P7_U1_CFG16 0x40010ed0u +#define CYREG_B0_P7_U1_CFG17 0x40010ed1u +#define CYREG_B0_P7_U1_CFG18 0x40010ed2u +#define CYREG_B0_P7_U1_CFG19 0x40010ed3u +#define CYREG_B0_P7_U1_CFG20 0x40010ed4u +#define CYREG_B0_P7_U1_CFG21 0x40010ed5u +#define CYREG_B0_P7_U1_CFG22 0x40010ed6u +#define CYREG_B0_P7_U1_CFG23 0x40010ed7u +#define CYREG_B0_P7_U1_CFG24 0x40010ed8u +#define CYREG_B0_P7_U1_CFG25 0x40010ed9u +#define CYREG_B0_P7_U1_CFG26 0x40010edau +#define CYREG_B0_P7_U1_CFG27 0x40010edbu +#define CYREG_B0_P7_U1_CFG28 0x40010edcu +#define CYREG_B0_P7_U1_CFG29 0x40010eddu +#define CYREG_B0_P7_U1_CFG30 0x40010edeu +#define CYREG_B0_P7_U1_CFG31 0x40010edfu +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0u +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2u +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4u +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6u +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8u +#define CYREG_B0_P7_U1_DCFG5 0x40010eeau +#define CYREG_B0_P7_U1_DCFG6 0x40010eecu +#define CYREG_B0_P7_U1_DCFG7 0x40010eeeu +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00u +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_BASE 0x40011000u +#define CYDEV_UCFG_B1_SIZE 0x00000fefu +#define CYDEV_UCFG_B1_P2_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400u +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070u +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400u +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404u +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408u +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140cu +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410u +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414u +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418u +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141cu +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420u +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424u +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428u +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142cu +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430u +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432u +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434u +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436u +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438u +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143au +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143cu +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143eu +#define CYREG_B1_P2_U0_CFG0 0x40011440u +#define CYREG_B1_P2_U0_CFG1 0x40011441u +#define CYREG_B1_P2_U0_CFG2 0x40011442u +#define CYREG_B1_P2_U0_CFG3 0x40011443u +#define CYREG_B1_P2_U0_CFG4 0x40011444u +#define CYREG_B1_P2_U0_CFG5 0x40011445u +#define CYREG_B1_P2_U0_CFG6 0x40011446u +#define CYREG_B1_P2_U0_CFG7 0x40011447u +#define CYREG_B1_P2_U0_CFG8 0x40011448u +#define CYREG_B1_P2_U0_CFG9 0x40011449u +#define CYREG_B1_P2_U0_CFG10 0x4001144au +#define CYREG_B1_P2_U0_CFG11 0x4001144bu +#define CYREG_B1_P2_U0_CFG12 0x4001144cu +#define CYREG_B1_P2_U0_CFG13 0x4001144du +#define CYREG_B1_P2_U0_CFG14 0x4001144eu +#define CYREG_B1_P2_U0_CFG15 0x4001144fu +#define CYREG_B1_P2_U0_CFG16 0x40011450u +#define CYREG_B1_P2_U0_CFG17 0x40011451u +#define CYREG_B1_P2_U0_CFG18 0x40011452u +#define CYREG_B1_P2_U0_CFG19 0x40011453u +#define CYREG_B1_P2_U0_CFG20 0x40011454u +#define CYREG_B1_P2_U0_CFG21 0x40011455u +#define CYREG_B1_P2_U0_CFG22 0x40011456u +#define CYREG_B1_P2_U0_CFG23 0x40011457u +#define CYREG_B1_P2_U0_CFG24 0x40011458u +#define CYREG_B1_P2_U0_CFG25 0x40011459u +#define CYREG_B1_P2_U0_CFG26 0x4001145au +#define CYREG_B1_P2_U0_CFG27 0x4001145bu +#define CYREG_B1_P2_U0_CFG28 0x4001145cu +#define CYREG_B1_P2_U0_CFG29 0x4001145du +#define CYREG_B1_P2_U0_CFG30 0x4001145eu +#define CYREG_B1_P2_U0_CFG31 0x4001145fu +#define CYREG_B1_P2_U0_DCFG0 0x40011460u +#define CYREG_B1_P2_U0_DCFG1 0x40011462u +#define CYREG_B1_P2_U0_DCFG2 0x40011464u +#define CYREG_B1_P2_U0_DCFG3 0x40011466u +#define CYREG_B1_P2_U0_DCFG4 0x40011468u +#define CYREG_B1_P2_U0_DCFG5 0x4001146au +#define CYREG_B1_P2_U0_DCFG6 0x4001146cu +#define CYREG_B1_P2_U0_DCFG7 0x4001146eu +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480u +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070u +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480u +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484u +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488u +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148cu +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490u +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494u +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498u +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149cu +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0u +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4u +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8u +#define CYREG_B1_P2_U1_PLD_IT11 0x400114acu +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0u +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2u +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4u +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6u +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8u +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114bau +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bcu +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114beu +#define CYREG_B1_P2_U1_CFG0 0x400114c0u +#define CYREG_B1_P2_U1_CFG1 0x400114c1u +#define CYREG_B1_P2_U1_CFG2 0x400114c2u +#define CYREG_B1_P2_U1_CFG3 0x400114c3u +#define CYREG_B1_P2_U1_CFG4 0x400114c4u +#define CYREG_B1_P2_U1_CFG5 0x400114c5u +#define CYREG_B1_P2_U1_CFG6 0x400114c6u +#define CYREG_B1_P2_U1_CFG7 0x400114c7u +#define CYREG_B1_P2_U1_CFG8 0x400114c8u +#define CYREG_B1_P2_U1_CFG9 0x400114c9u +#define CYREG_B1_P2_U1_CFG10 0x400114cau +#define CYREG_B1_P2_U1_CFG11 0x400114cbu +#define CYREG_B1_P2_U1_CFG12 0x400114ccu +#define CYREG_B1_P2_U1_CFG13 0x400114cdu +#define CYREG_B1_P2_U1_CFG14 0x400114ceu +#define CYREG_B1_P2_U1_CFG15 0x400114cfu +#define CYREG_B1_P2_U1_CFG16 0x400114d0u +#define CYREG_B1_P2_U1_CFG17 0x400114d1u +#define CYREG_B1_P2_U1_CFG18 0x400114d2u +#define CYREG_B1_P2_U1_CFG19 0x400114d3u +#define CYREG_B1_P2_U1_CFG20 0x400114d4u +#define CYREG_B1_P2_U1_CFG21 0x400114d5u +#define CYREG_B1_P2_U1_CFG22 0x400114d6u +#define CYREG_B1_P2_U1_CFG23 0x400114d7u +#define CYREG_B1_P2_U1_CFG24 0x400114d8u +#define CYREG_B1_P2_U1_CFG25 0x400114d9u +#define CYREG_B1_P2_U1_CFG26 0x400114dau +#define CYREG_B1_P2_U1_CFG27 0x400114dbu +#define CYREG_B1_P2_U1_CFG28 0x400114dcu +#define CYREG_B1_P2_U1_CFG29 0x400114ddu +#define CYREG_B1_P2_U1_CFG30 0x400114deu +#define CYREG_B1_P2_U1_CFG31 0x400114dfu +#define CYREG_B1_P2_U1_DCFG0 0x400114e0u +#define CYREG_B1_P2_U1_DCFG1 0x400114e2u +#define CYREG_B1_P2_U1_DCFG2 0x400114e4u +#define CYREG_B1_P2_U1_DCFG3 0x400114e6u +#define CYREG_B1_P2_U1_DCFG4 0x400114e8u +#define CYREG_B1_P2_U1_DCFG5 0x400114eau +#define CYREG_B1_P2_U1_DCFG6 0x400114ecu +#define CYREG_B1_P2_U1_DCFG7 0x400114eeu +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500u +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P3_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600u +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070u +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600u +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604u +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608u +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160cu +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610u +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614u +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618u +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161cu +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620u +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624u +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628u +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162cu +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630u +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632u +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634u +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636u +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638u +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163au +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163cu +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163eu +#define CYREG_B1_P3_U0_CFG0 0x40011640u +#define CYREG_B1_P3_U0_CFG1 0x40011641u +#define CYREG_B1_P3_U0_CFG2 0x40011642u +#define CYREG_B1_P3_U0_CFG3 0x40011643u +#define CYREG_B1_P3_U0_CFG4 0x40011644u +#define CYREG_B1_P3_U0_CFG5 0x40011645u +#define CYREG_B1_P3_U0_CFG6 0x40011646u +#define CYREG_B1_P3_U0_CFG7 0x40011647u +#define CYREG_B1_P3_U0_CFG8 0x40011648u +#define CYREG_B1_P3_U0_CFG9 0x40011649u +#define CYREG_B1_P3_U0_CFG10 0x4001164au +#define CYREG_B1_P3_U0_CFG11 0x4001164bu +#define CYREG_B1_P3_U0_CFG12 0x4001164cu +#define CYREG_B1_P3_U0_CFG13 0x4001164du +#define CYREG_B1_P3_U0_CFG14 0x4001164eu +#define CYREG_B1_P3_U0_CFG15 0x4001164fu +#define CYREG_B1_P3_U0_CFG16 0x40011650u +#define CYREG_B1_P3_U0_CFG17 0x40011651u +#define CYREG_B1_P3_U0_CFG18 0x40011652u +#define CYREG_B1_P3_U0_CFG19 0x40011653u +#define CYREG_B1_P3_U0_CFG20 0x40011654u +#define CYREG_B1_P3_U0_CFG21 0x40011655u +#define CYREG_B1_P3_U0_CFG22 0x40011656u +#define CYREG_B1_P3_U0_CFG23 0x40011657u +#define CYREG_B1_P3_U0_CFG24 0x40011658u +#define CYREG_B1_P3_U0_CFG25 0x40011659u +#define CYREG_B1_P3_U0_CFG26 0x4001165au +#define CYREG_B1_P3_U0_CFG27 0x4001165bu +#define CYREG_B1_P3_U0_CFG28 0x4001165cu +#define CYREG_B1_P3_U0_CFG29 0x4001165du +#define CYREG_B1_P3_U0_CFG30 0x4001165eu +#define CYREG_B1_P3_U0_CFG31 0x4001165fu +#define CYREG_B1_P3_U0_DCFG0 0x40011660u +#define CYREG_B1_P3_U0_DCFG1 0x40011662u +#define CYREG_B1_P3_U0_DCFG2 0x40011664u +#define CYREG_B1_P3_U0_DCFG3 0x40011666u +#define CYREG_B1_P3_U0_DCFG4 0x40011668u +#define CYREG_B1_P3_U0_DCFG5 0x4001166au +#define CYREG_B1_P3_U0_DCFG6 0x4001166cu +#define CYREG_B1_P3_U0_DCFG7 0x4001166eu +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680u +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070u +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680u +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684u +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688u +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168cu +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690u +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694u +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698u +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169cu +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0u +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4u +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8u +#define CYREG_B1_P3_U1_PLD_IT11 0x400116acu +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0u +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2u +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4u +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6u +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8u +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116bau +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bcu +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116beu +#define CYREG_B1_P3_U1_CFG0 0x400116c0u +#define CYREG_B1_P3_U1_CFG1 0x400116c1u +#define CYREG_B1_P3_U1_CFG2 0x400116c2u +#define CYREG_B1_P3_U1_CFG3 0x400116c3u +#define CYREG_B1_P3_U1_CFG4 0x400116c4u +#define CYREG_B1_P3_U1_CFG5 0x400116c5u +#define CYREG_B1_P3_U1_CFG6 0x400116c6u +#define CYREG_B1_P3_U1_CFG7 0x400116c7u +#define CYREG_B1_P3_U1_CFG8 0x400116c8u +#define CYREG_B1_P3_U1_CFG9 0x400116c9u +#define CYREG_B1_P3_U1_CFG10 0x400116cau +#define CYREG_B1_P3_U1_CFG11 0x400116cbu +#define CYREG_B1_P3_U1_CFG12 0x400116ccu +#define CYREG_B1_P3_U1_CFG13 0x400116cdu +#define CYREG_B1_P3_U1_CFG14 0x400116ceu +#define CYREG_B1_P3_U1_CFG15 0x400116cfu +#define CYREG_B1_P3_U1_CFG16 0x400116d0u +#define CYREG_B1_P3_U1_CFG17 0x400116d1u +#define CYREG_B1_P3_U1_CFG18 0x400116d2u +#define CYREG_B1_P3_U1_CFG19 0x400116d3u +#define CYREG_B1_P3_U1_CFG20 0x400116d4u +#define CYREG_B1_P3_U1_CFG21 0x400116d5u +#define CYREG_B1_P3_U1_CFG22 0x400116d6u +#define CYREG_B1_P3_U1_CFG23 0x400116d7u +#define CYREG_B1_P3_U1_CFG24 0x400116d8u +#define CYREG_B1_P3_U1_CFG25 0x400116d9u +#define CYREG_B1_P3_U1_CFG26 0x400116dau +#define CYREG_B1_P3_U1_CFG27 0x400116dbu +#define CYREG_B1_P3_U1_CFG28 0x400116dcu +#define CYREG_B1_P3_U1_CFG29 0x400116ddu +#define CYREG_B1_P3_U1_CFG30 0x400116deu +#define CYREG_B1_P3_U1_CFG31 0x400116dfu +#define CYREG_B1_P3_U1_DCFG0 0x400116e0u +#define CYREG_B1_P3_U1_DCFG1 0x400116e2u +#define CYREG_B1_P3_U1_DCFG2 0x400116e4u +#define CYREG_B1_P3_U1_DCFG3 0x400116e6u +#define CYREG_B1_P3_U1_DCFG4 0x400116e8u +#define CYREG_B1_P3_U1_DCFG5 0x400116eau +#define CYREG_B1_P3_U1_DCFG6 0x400116ecu +#define CYREG_B1_P3_U1_DCFG7 0x400116eeu +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700u +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P4_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800u +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070u +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800u +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804u +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808u +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180cu +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810u +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814u +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818u +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181cu +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820u +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824u +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828u +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182cu +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830u +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832u +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834u +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836u +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838u +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183au +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183cu +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183eu +#define CYREG_B1_P4_U0_CFG0 0x40011840u +#define CYREG_B1_P4_U0_CFG1 0x40011841u +#define CYREG_B1_P4_U0_CFG2 0x40011842u +#define CYREG_B1_P4_U0_CFG3 0x40011843u +#define CYREG_B1_P4_U0_CFG4 0x40011844u +#define CYREG_B1_P4_U0_CFG5 0x40011845u +#define CYREG_B1_P4_U0_CFG6 0x40011846u +#define CYREG_B1_P4_U0_CFG7 0x40011847u +#define CYREG_B1_P4_U0_CFG8 0x40011848u +#define CYREG_B1_P4_U0_CFG9 0x40011849u +#define CYREG_B1_P4_U0_CFG10 0x4001184au +#define CYREG_B1_P4_U0_CFG11 0x4001184bu +#define CYREG_B1_P4_U0_CFG12 0x4001184cu +#define CYREG_B1_P4_U0_CFG13 0x4001184du +#define CYREG_B1_P4_U0_CFG14 0x4001184eu +#define CYREG_B1_P4_U0_CFG15 0x4001184fu +#define CYREG_B1_P4_U0_CFG16 0x40011850u +#define CYREG_B1_P4_U0_CFG17 0x40011851u +#define CYREG_B1_P4_U0_CFG18 0x40011852u +#define CYREG_B1_P4_U0_CFG19 0x40011853u +#define CYREG_B1_P4_U0_CFG20 0x40011854u +#define CYREG_B1_P4_U0_CFG21 0x40011855u +#define CYREG_B1_P4_U0_CFG22 0x40011856u +#define CYREG_B1_P4_U0_CFG23 0x40011857u +#define CYREG_B1_P4_U0_CFG24 0x40011858u +#define CYREG_B1_P4_U0_CFG25 0x40011859u +#define CYREG_B1_P4_U0_CFG26 0x4001185au +#define CYREG_B1_P4_U0_CFG27 0x4001185bu +#define CYREG_B1_P4_U0_CFG28 0x4001185cu +#define CYREG_B1_P4_U0_CFG29 0x4001185du +#define CYREG_B1_P4_U0_CFG30 0x4001185eu +#define CYREG_B1_P4_U0_CFG31 0x4001185fu +#define CYREG_B1_P4_U0_DCFG0 0x40011860u +#define CYREG_B1_P4_U0_DCFG1 0x40011862u +#define CYREG_B1_P4_U0_DCFG2 0x40011864u +#define CYREG_B1_P4_U0_DCFG3 0x40011866u +#define CYREG_B1_P4_U0_DCFG4 0x40011868u +#define CYREG_B1_P4_U0_DCFG5 0x4001186au +#define CYREG_B1_P4_U0_DCFG6 0x4001186cu +#define CYREG_B1_P4_U0_DCFG7 0x4001186eu +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880u +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070u +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880u +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884u +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888u +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188cu +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890u +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894u +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898u +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189cu +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0u +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4u +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8u +#define CYREG_B1_P4_U1_PLD_IT11 0x400118acu +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0u +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2u +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4u +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6u +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8u +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118bau +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bcu +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118beu +#define CYREG_B1_P4_U1_CFG0 0x400118c0u +#define CYREG_B1_P4_U1_CFG1 0x400118c1u +#define CYREG_B1_P4_U1_CFG2 0x400118c2u +#define CYREG_B1_P4_U1_CFG3 0x400118c3u +#define CYREG_B1_P4_U1_CFG4 0x400118c4u +#define CYREG_B1_P4_U1_CFG5 0x400118c5u +#define CYREG_B1_P4_U1_CFG6 0x400118c6u +#define CYREG_B1_P4_U1_CFG7 0x400118c7u +#define CYREG_B1_P4_U1_CFG8 0x400118c8u +#define CYREG_B1_P4_U1_CFG9 0x400118c9u +#define CYREG_B1_P4_U1_CFG10 0x400118cau +#define CYREG_B1_P4_U1_CFG11 0x400118cbu +#define CYREG_B1_P4_U1_CFG12 0x400118ccu +#define CYREG_B1_P4_U1_CFG13 0x400118cdu +#define CYREG_B1_P4_U1_CFG14 0x400118ceu +#define CYREG_B1_P4_U1_CFG15 0x400118cfu +#define CYREG_B1_P4_U1_CFG16 0x400118d0u +#define CYREG_B1_P4_U1_CFG17 0x400118d1u +#define CYREG_B1_P4_U1_CFG18 0x400118d2u +#define CYREG_B1_P4_U1_CFG19 0x400118d3u +#define CYREG_B1_P4_U1_CFG20 0x400118d4u +#define CYREG_B1_P4_U1_CFG21 0x400118d5u +#define CYREG_B1_P4_U1_CFG22 0x400118d6u +#define CYREG_B1_P4_U1_CFG23 0x400118d7u +#define CYREG_B1_P4_U1_CFG24 0x400118d8u +#define CYREG_B1_P4_U1_CFG25 0x400118d9u +#define CYREG_B1_P4_U1_CFG26 0x400118dau +#define CYREG_B1_P4_U1_CFG27 0x400118dbu +#define CYREG_B1_P4_U1_CFG28 0x400118dcu +#define CYREG_B1_P4_U1_CFG29 0x400118ddu +#define CYREG_B1_P4_U1_CFG30 0x400118deu +#define CYREG_B1_P4_U1_CFG31 0x400118dfu +#define CYREG_B1_P4_U1_DCFG0 0x400118e0u +#define CYREG_B1_P4_U1_DCFG1 0x400118e2u +#define CYREG_B1_P4_U1_DCFG2 0x400118e4u +#define CYREG_B1_P4_U1_DCFG3 0x400118e6u +#define CYREG_B1_P4_U1_DCFG4 0x400118e8u +#define CYREG_B1_P4_U1_DCFG5 0x400118eau +#define CYREG_B1_P4_U1_DCFG6 0x400118ecu +#define CYREG_B1_P4_U1_DCFG7 0x400118eeu +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900u +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_SIZE 0x000001efu +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00u +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070u +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00u +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04u +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08u +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0cu +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10u +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14u +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18u +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1cu +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20u +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24u +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28u +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2cu +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30u +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32u +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34u +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36u +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38u +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3au +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3cu +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3eu +#define CYREG_B1_P5_U0_CFG0 0x40011a40u +#define CYREG_B1_P5_U0_CFG1 0x40011a41u +#define CYREG_B1_P5_U0_CFG2 0x40011a42u +#define CYREG_B1_P5_U0_CFG3 0x40011a43u +#define CYREG_B1_P5_U0_CFG4 0x40011a44u +#define CYREG_B1_P5_U0_CFG5 0x40011a45u +#define CYREG_B1_P5_U0_CFG6 0x40011a46u +#define CYREG_B1_P5_U0_CFG7 0x40011a47u +#define CYREG_B1_P5_U0_CFG8 0x40011a48u +#define CYREG_B1_P5_U0_CFG9 0x40011a49u +#define CYREG_B1_P5_U0_CFG10 0x40011a4au +#define CYREG_B1_P5_U0_CFG11 0x40011a4bu +#define CYREG_B1_P5_U0_CFG12 0x40011a4cu +#define CYREG_B1_P5_U0_CFG13 0x40011a4du +#define CYREG_B1_P5_U0_CFG14 0x40011a4eu +#define CYREG_B1_P5_U0_CFG15 0x40011a4fu +#define CYREG_B1_P5_U0_CFG16 0x40011a50u +#define CYREG_B1_P5_U0_CFG17 0x40011a51u +#define CYREG_B1_P5_U0_CFG18 0x40011a52u +#define CYREG_B1_P5_U0_CFG19 0x40011a53u +#define CYREG_B1_P5_U0_CFG20 0x40011a54u +#define CYREG_B1_P5_U0_CFG21 0x40011a55u +#define CYREG_B1_P5_U0_CFG22 0x40011a56u +#define CYREG_B1_P5_U0_CFG23 0x40011a57u +#define CYREG_B1_P5_U0_CFG24 0x40011a58u +#define CYREG_B1_P5_U0_CFG25 0x40011a59u +#define CYREG_B1_P5_U0_CFG26 0x40011a5au +#define CYREG_B1_P5_U0_CFG27 0x40011a5bu +#define CYREG_B1_P5_U0_CFG28 0x40011a5cu +#define CYREG_B1_P5_U0_CFG29 0x40011a5du +#define CYREG_B1_P5_U0_CFG30 0x40011a5eu +#define CYREG_B1_P5_U0_CFG31 0x40011a5fu +#define CYREG_B1_P5_U0_DCFG0 0x40011a60u +#define CYREG_B1_P5_U0_DCFG1 0x40011a62u +#define CYREG_B1_P5_U0_DCFG2 0x40011a64u +#define CYREG_B1_P5_U0_DCFG3 0x40011a66u +#define CYREG_B1_P5_U0_DCFG4 0x40011a68u +#define CYREG_B1_P5_U0_DCFG5 0x40011a6au +#define CYREG_B1_P5_U0_DCFG6 0x40011a6cu +#define CYREG_B1_P5_U0_DCFG7 0x40011a6eu +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80u +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070u +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80u +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84u +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88u +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8cu +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90u +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94u +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98u +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9cu +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0u +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4u +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8u +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aacu +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0u +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2u +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4u +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6u +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8u +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011abau +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abcu +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abeu +#define CYREG_B1_P5_U1_CFG0 0x40011ac0u +#define CYREG_B1_P5_U1_CFG1 0x40011ac1u +#define CYREG_B1_P5_U1_CFG2 0x40011ac2u +#define CYREG_B1_P5_U1_CFG3 0x40011ac3u +#define CYREG_B1_P5_U1_CFG4 0x40011ac4u +#define CYREG_B1_P5_U1_CFG5 0x40011ac5u +#define CYREG_B1_P5_U1_CFG6 0x40011ac6u +#define CYREG_B1_P5_U1_CFG7 0x40011ac7u +#define CYREG_B1_P5_U1_CFG8 0x40011ac8u +#define CYREG_B1_P5_U1_CFG9 0x40011ac9u +#define CYREG_B1_P5_U1_CFG10 0x40011acau +#define CYREG_B1_P5_U1_CFG11 0x40011acbu +#define CYREG_B1_P5_U1_CFG12 0x40011accu +#define CYREG_B1_P5_U1_CFG13 0x40011acdu +#define CYREG_B1_P5_U1_CFG14 0x40011aceu +#define CYREG_B1_P5_U1_CFG15 0x40011acfu +#define CYREG_B1_P5_U1_CFG16 0x40011ad0u +#define CYREG_B1_P5_U1_CFG17 0x40011ad1u +#define CYREG_B1_P5_U1_CFG18 0x40011ad2u +#define CYREG_B1_P5_U1_CFG19 0x40011ad3u +#define CYREG_B1_P5_U1_CFG20 0x40011ad4u +#define CYREG_B1_P5_U1_CFG21 0x40011ad5u +#define CYREG_B1_P5_U1_CFG22 0x40011ad6u +#define CYREG_B1_P5_U1_CFG23 0x40011ad7u +#define CYREG_B1_P5_U1_CFG24 0x40011ad8u +#define CYREG_B1_P5_U1_CFG25 0x40011ad9u +#define CYREG_B1_P5_U1_CFG26 0x40011adau +#define CYREG_B1_P5_U1_CFG27 0x40011adbu +#define CYREG_B1_P5_U1_CFG28 0x40011adcu +#define CYREG_B1_P5_U1_CFG29 0x40011addu +#define CYREG_B1_P5_U1_CFG30 0x40011adeu +#define CYREG_B1_P5_U1_CFG31 0x40011adfu +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0u +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2u +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4u +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6u +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8u +#define CYREG_B1_P5_U1_DCFG5 0x40011aeau +#define CYREG_B1_P5_U1_DCFG6 0x40011aecu +#define CYREG_B1_P5_U1_DCFG7 0x40011aeeu +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00u +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000efu +#define CYDEV_UCFG_DSI0_BASE 0x40014000u +#define CYDEV_UCFG_DSI0_SIZE 0x000000efu +#define CYDEV_UCFG_DSI1_BASE 0x40014100u +#define CYDEV_UCFG_DSI1_SIZE 0x000000efu +#define CYDEV_UCFG_DSI2_BASE 0x40014200u +#define CYDEV_UCFG_DSI2_SIZE 0x000000efu +#define CYDEV_UCFG_DSI3_BASE 0x40014300u +#define CYDEV_UCFG_DSI3_SIZE 0x000000efu +#define CYDEV_UCFG_DSI4_BASE 0x40014400u +#define CYDEV_UCFG_DSI4_SIZE 0x000000efu +#define CYDEV_UCFG_DSI5_BASE 0x40014500u +#define CYDEV_UCFG_DSI5_SIZE 0x000000efu +#define CYDEV_UCFG_DSI6_BASE 0x40014600u +#define CYDEV_UCFG_DSI6_SIZE 0x000000efu +#define CYDEV_UCFG_DSI7_BASE 0x40014700u +#define CYDEV_UCFG_DSI7_SIZE 0x000000efu +#define CYDEV_UCFG_DSI8_BASE 0x40014800u +#define CYDEV_UCFG_DSI8_SIZE 0x000000efu +#define CYDEV_UCFG_DSI9_BASE 0x40014900u +#define CYDEV_UCFG_DSI9_SIZE 0x000000efu +#define CYDEV_UCFG_DSI12_BASE 0x40014c00u +#define CYDEV_UCFG_DSI12_SIZE 0x000000efu +#define CYDEV_UCFG_DSI13_BASE 0x40014d00u +#define CYDEV_UCFG_DSI13_SIZE 0x000000efu +#define CYDEV_UCFG_BCTL0_BASE 0x40015000u +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010u +#define CYREG_BCTL0_MDCLK_EN 0x40015000u +#define CYREG_BCTL0_MBCLK_EN 0x40015001u +#define CYREG_BCTL0_WAIT_CFG 0x40015002u +#define CYREG_BCTL0_BANK_CTL 0x40015003u +#define CYREG_BCTL0_UDB_TEST_3 0x40015007u +#define CYREG_BCTL0_DCLK_EN0 0x40015008u +#define CYREG_BCTL0_BCLK_EN0 0x40015009u +#define CYREG_BCTL0_DCLK_EN1 0x4001500au +#define CYREG_BCTL0_BCLK_EN1 0x4001500bu +#define CYREG_BCTL0_DCLK_EN2 0x4001500cu +#define CYREG_BCTL0_BCLK_EN2 0x4001500du +#define CYREG_BCTL0_DCLK_EN3 0x4001500eu +#define CYREG_BCTL0_BCLK_EN3 0x4001500fu +#define CYDEV_UCFG_BCTL1_BASE 0x40015010u +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010u +#define CYREG_BCTL1_MDCLK_EN 0x40015010u +#define CYREG_BCTL1_MBCLK_EN 0x40015011u +#define CYREG_BCTL1_WAIT_CFG 0x40015012u +#define CYREG_BCTL1_BANK_CTL 0x40015013u +#define CYREG_BCTL1_UDB_TEST_3 0x40015017u +#define CYREG_BCTL1_DCLK_EN0 0x40015018u +#define CYREG_BCTL1_BCLK_EN0 0x40015019u +#define CYREG_BCTL1_DCLK_EN1 0x4001501au +#define CYREG_BCTL1_BCLK_EN1 0x4001501bu +#define CYREG_BCTL1_DCLK_EN2 0x4001501cu +#define CYREG_BCTL1_BCLK_EN2 0x4001501du +#define CYREG_BCTL1_DCLK_EN3 0x4001501eu +#define CYREG_BCTL1_BCLK_EN3 0x4001501fu +#define CYDEV_IDMUX_BASE 0x40015100u +#define CYDEV_IDMUX_SIZE 0x00000016u +#define CYREG_IDMUX_IRQ_CTL0 0x40015100u +#define CYREG_IDMUX_IRQ_CTL1 0x40015101u +#define CYREG_IDMUX_IRQ_CTL2 0x40015102u +#define CYREG_IDMUX_IRQ_CTL3 0x40015103u +#define CYREG_IDMUX_IRQ_CTL4 0x40015104u +#define CYREG_IDMUX_IRQ_CTL5 0x40015105u +#define CYREG_IDMUX_IRQ_CTL6 0x40015106u +#define CYREG_IDMUX_IRQ_CTL7 0x40015107u +#define CYREG_IDMUX_DRQ_CTL0 0x40015110u +#define CYREG_IDMUX_DRQ_CTL1 0x40015111u +#define CYREG_IDMUX_DRQ_CTL2 0x40015112u +#define CYREG_IDMUX_DRQ_CTL3 0x40015113u +#define CYREG_IDMUX_DRQ_CTL4 0x40015114u +#define CYREG_IDMUX_DRQ_CTL5 0x40015115u +#define CYDEV_CACHERAM_BASE 0x40030000u +#define CYDEV_CACHERAM_SIZE 0x00000400u +#define CYREG_CACHERAM_DATA_MBASE 0x40030000u +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400u +#define CYDEV_SFR_BASE 0x40050100u +#define CYDEV_SFR_SIZE 0x000000fbu +#define CYREG_SFR_GPIO0 0x40050180u +#define CYREG_SFR_GPIRD0 0x40050189u +#define CYREG_SFR_GPIO0_SEL 0x4005018au +#define CYREG_SFR_GPIO1 0x40050190u +#define CYREG_SFR_GPIRD1 0x40050191u +#define CYREG_SFR_GPIO2 0x40050198u +#define CYREG_SFR_GPIRD2 0x40050199u +#define CYREG_SFR_GPIO2_SEL 0x4005019au +#define CYREG_SFR_GPIO1_SEL 0x400501a2u +#define CYREG_SFR_GPIO3 0x400501b0u +#define CYREG_SFR_GPIRD3 0x400501b1u +#define CYREG_SFR_GPIO3_SEL 0x400501b2u +#define CYREG_SFR_GPIO4 0x400501c0u +#define CYREG_SFR_GPIRD4 0x400501c1u +#define CYREG_SFR_GPIO4_SEL 0x400501c2u +#define CYREG_SFR_GPIO5 0x400501c8u +#define CYREG_SFR_GPIRD5 0x400501c9u +#define CYREG_SFR_GPIO5_SEL 0x400501cau +#define CYREG_SFR_GPIO6 0x400501d8u +#define CYREG_SFR_GPIRD6 0x400501d9u +#define CYREG_SFR_GPIO6_SEL 0x400501dau +#define CYREG_SFR_GPIO12 0x400501e8u +#define CYREG_SFR_GPIRD12 0x400501e9u +#define CYREG_SFR_GPIO12_SEL 0x400501f2u +#define CYREG_SFR_GPIO15 0x400501f8u +#define CYREG_SFR_GPIRD15 0x400501f9u +#define CYREG_SFR_GPIO15_SEL 0x400501fau +#define CYDEV_P3BA_BASE 0x40050300u +#define CYDEV_P3BA_SIZE 0x0000002bu +#define CYREG_P3BA_Y_START 0x40050300u +#define CYREG_P3BA_YROLL 0x40050301u +#define CYREG_P3BA_YCFG 0x40050302u +#define CYREG_P3BA_X_START1 0x40050303u +#define CYREG_P3BA_X_START2 0x40050304u +#define CYREG_P3BA_XROLL1 0x40050305u +#define CYREG_P3BA_XROLL2 0x40050306u +#define CYREG_P3BA_XINC 0x40050307u +#define CYREG_P3BA_XCFG 0x40050308u +#define CYREG_P3BA_OFFSETADDR1 0x40050309u +#define CYREG_P3BA_OFFSETADDR2 0x4005030au +#define CYREG_P3BA_OFFSETADDR3 0x4005030bu +#define CYREG_P3BA_ABSADDR1 0x4005030cu +#define CYREG_P3BA_ABSADDR2 0x4005030du +#define CYREG_P3BA_ABSADDR3 0x4005030eu +#define CYREG_P3BA_ABSADDR4 0x4005030fu +#define CYREG_P3BA_DATCFG1 0x40050310u +#define CYREG_P3BA_DATCFG2 0x40050311u +#define CYREG_P3BA_CMP_RSLT1 0x40050314u +#define CYREG_P3BA_CMP_RSLT2 0x40050315u +#define CYREG_P3BA_CMP_RSLT3 0x40050316u +#define CYREG_P3BA_CMP_RSLT4 0x40050317u +#define CYREG_P3BA_DATA_REG1 0x40050318u +#define CYREG_P3BA_DATA_REG2 0x40050319u +#define CYREG_P3BA_DATA_REG3 0x4005031au +#define CYREG_P3BA_DATA_REG4 0x4005031bu +#define CYREG_P3BA_EXP_DATA1 0x4005031cu +#define CYREG_P3BA_EXP_DATA2 0x4005031du +#define CYREG_P3BA_EXP_DATA3 0x4005031eu +#define CYREG_P3BA_EXP_DATA4 0x4005031fu +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320u +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321u +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322u +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323u +#define CYREG_P3BA_BIST_EN 0x40050324u +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325u +#define CYREG_P3BA_SEQCFG1 0x40050326u +#define CYREG_P3BA_SEQCFG2 0x40050327u +#define CYREG_P3BA_Y_CURR 0x40050328u +#define CYREG_P3BA_X_CURR1 0x40050329u +#define CYREG_P3BA_X_CURR2 0x4005032au +#define CYDEV_PANTHER_BASE 0x40080000u +#define CYDEV_PANTHER_SIZE 0x00000020u +#define CYREG_PANTHER_STCALIB_CFG 0x40080000u +#define CYREG_PANTHER_WAITPIPE 0x40080004u +#define CYREG_PANTHER_TRACE_CFG 0x40080008u +#define CYREG_PANTHER_DBG_CFG 0x4008000cu +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018u +#define CYREG_PANTHER_DEVICE_ID 0x4008001cu +#define CYDEV_FLSECC_BASE 0x48000000u +#define CYDEV_FLSECC_SIZE 0x00008000u +#define CYREG_FLSECC_DATA_MBASE 0x48000000u +#define CYREG_FLSECC_DATA_MSIZE 0x00008000u +#define CYDEV_FLSHID_BASE 0x49000000u +#define CYDEV_FLSHID_SIZE 0x00000200u +#define CYREG_FLSHID_RSVD_MBASE 0x49000000u +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080u +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080u +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080u +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100u +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040u +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100u +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101u +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102u +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103u +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104u +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105u +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106u +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107u +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108u +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109u +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010au +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010bu +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010cu +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010du +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010eu +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010fu +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113u +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114u +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115u +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116u +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117u +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118u +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119u +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011au +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011bu +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011cu +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011du +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011eu +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011fu +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126u +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129u +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012au +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012bu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012cu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012du +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012eu +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012fu +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136u +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139u +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013au +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013bu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013cu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013du +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013eu +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013fu +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180u +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080u +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001acu +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001aeu +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2u +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4u +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6u +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8u +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001bau +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ceu +#define CYDEV_EXTMEM_BASE 0x60000000u +#define CYDEV_EXTMEM_SIZE 0x00800000u +#define CYREG_EXTMEM_DATA_MBASE 0x60000000u +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000u +#define CYDEV_ITM_BASE 0xe0000000u +#define CYDEV_ITM_SIZE 0x00001000u +#define CYREG_ITM_TRACE_EN 0xe0000e00u +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40u +#define CYREG_ITM_TRACE_CTRL 0xe0000e80u +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0u +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4u +#define CYREG_ITM_PID4 0xe0000fd0u +#define CYREG_ITM_PID5 0xe0000fd4u +#define CYREG_ITM_PID6 0xe0000fd8u +#define CYREG_ITM_PID7 0xe0000fdcu +#define CYREG_ITM_PID0 0xe0000fe0u +#define CYREG_ITM_PID1 0xe0000fe4u +#define CYREG_ITM_PID2 0xe0000fe8u +#define CYREG_ITM_PID3 0xe0000fecu +#define CYREG_ITM_CID0 0xe0000ff0u +#define CYREG_ITM_CID1 0xe0000ff4u +#define CYREG_ITM_CID2 0xe0000ff8u +#define CYREG_ITM_CID3 0xe0000ffcu +#define CYDEV_DWT_BASE 0xe0001000u +#define CYDEV_DWT_SIZE 0x0000005cu +#define CYREG_DWT_CTRL 0xe0001000u +#define CYREG_DWT_CYCLE_COUNT 0xe0001004u +#define CYREG_DWT_CPI_COUNT 0xe0001008u +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100cu +#define CYREG_DWT_SLEEP_COUNT 0xe0001010u +#define CYREG_DWT_LSU_COUNT 0xe0001014u +#define CYREG_DWT_FOLD_COUNT 0xe0001018u +#define CYREG_DWT_PC_SAMPLE 0xe000101cu +#define CYREG_DWT_COMP_0 0xe0001020u +#define CYREG_DWT_MASK_0 0xe0001024u +#define CYREG_DWT_FUNCTION_0 0xe0001028u +#define CYREG_DWT_COMP_1 0xe0001030u +#define CYREG_DWT_MASK_1 0xe0001034u +#define CYREG_DWT_FUNCTION_1 0xe0001038u +#define CYREG_DWT_COMP_2 0xe0001040u +#define CYREG_DWT_MASK_2 0xe0001044u +#define CYREG_DWT_FUNCTION_2 0xe0001048u +#define CYREG_DWT_COMP_3 0xe0001050u +#define CYREG_DWT_MASK_3 0xe0001054u +#define CYREG_DWT_FUNCTION_3 0xe0001058u +#define CYDEV_FPB_BASE 0xe0002000u +#define CYDEV_FPB_SIZE 0x00001000u +#define CYREG_FPB_CTRL 0xe0002000u +#define CYREG_FPB_REMAP 0xe0002004u +#define CYREG_FPB_FP_COMP_0 0xe0002008u +#define CYREG_FPB_FP_COMP_1 0xe000200cu +#define CYREG_FPB_FP_COMP_2 0xe0002010u +#define CYREG_FPB_FP_COMP_3 0xe0002014u +#define CYREG_FPB_FP_COMP_4 0xe0002018u +#define CYREG_FPB_FP_COMP_5 0xe000201cu +#define CYREG_FPB_FP_COMP_6 0xe0002020u +#define CYREG_FPB_FP_COMP_7 0xe0002024u +#define CYREG_FPB_PID4 0xe0002fd0u +#define CYREG_FPB_PID5 0xe0002fd4u +#define CYREG_FPB_PID6 0xe0002fd8u +#define CYREG_FPB_PID7 0xe0002fdcu +#define CYREG_FPB_PID0 0xe0002fe0u +#define CYREG_FPB_PID1 0xe0002fe4u +#define CYREG_FPB_PID2 0xe0002fe8u +#define CYREG_FPB_PID3 0xe0002fecu +#define CYREG_FPB_CID0 0xe0002ff0u +#define CYREG_FPB_CID1 0xe0002ff4u +#define CYREG_FPB_CID2 0xe0002ff8u +#define CYREG_FPB_CID3 0xe0002ffcu +#define CYDEV_NVIC_BASE 0xe000e000u +#define CYDEV_NVIC_SIZE 0x00000d3cu +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004u +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010u +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014u +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018u +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01cu +#define CYREG_NVIC_SETENA0 0xe000e100u +#define CYREG_NVIC_CLRENA0 0xe000e180u +#define CYREG_NVIC_SETPEND0 0xe000e200u +#define CYREG_NVIC_CLRPEND0 0xe000e280u +#define CYREG_NVIC_ACTIVE0 0xe000e300u +#define CYREG_NVIC_PRI_0 0xe000e400u +#define CYREG_NVIC_PRI_1 0xe000e401u +#define CYREG_NVIC_PRI_2 0xe000e402u +#define CYREG_NVIC_PRI_3 0xe000e403u +#define CYREG_NVIC_PRI_4 0xe000e404u +#define CYREG_NVIC_PRI_5 0xe000e405u +#define CYREG_NVIC_PRI_6 0xe000e406u +#define CYREG_NVIC_PRI_7 0xe000e407u +#define CYREG_NVIC_PRI_8 0xe000e408u +#define CYREG_NVIC_PRI_9 0xe000e409u +#define CYREG_NVIC_PRI_10 0xe000e40au +#define CYREG_NVIC_PRI_11 0xe000e40bu +#define CYREG_NVIC_PRI_12 0xe000e40cu +#define CYREG_NVIC_PRI_13 0xe000e40du +#define CYREG_NVIC_PRI_14 0xe000e40eu +#define CYREG_NVIC_PRI_15 0xe000e40fu +#define CYREG_NVIC_PRI_16 0xe000e410u +#define CYREG_NVIC_PRI_17 0xe000e411u +#define CYREG_NVIC_PRI_18 0xe000e412u +#define CYREG_NVIC_PRI_19 0xe000e413u +#define CYREG_NVIC_PRI_20 0xe000e414u +#define CYREG_NVIC_PRI_21 0xe000e415u +#define CYREG_NVIC_PRI_22 0xe000e416u +#define CYREG_NVIC_PRI_23 0xe000e417u +#define CYREG_NVIC_PRI_24 0xe000e418u +#define CYREG_NVIC_PRI_25 0xe000e419u +#define CYREG_NVIC_PRI_26 0xe000e41au +#define CYREG_NVIC_PRI_27 0xe000e41bu +#define CYREG_NVIC_PRI_28 0xe000e41cu +#define CYREG_NVIC_PRI_29 0xe000e41du +#define CYREG_NVIC_PRI_30 0xe000e41eu +#define CYREG_NVIC_PRI_31 0xe000e41fu +#define CYREG_NVIC_CPUID_BASE 0xe000ed00u +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04u +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08u +#define CYREG_NVIC_APPLN_INTR 0xe000ed0cu +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10u +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14u +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18u +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1cu +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20u +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24u +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28u +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29u +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2au +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2cu +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30u +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34u +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38u +#define CYDEV_CORE_DBG_BASE 0xe000edf0u +#define CYDEV_CORE_DBG_SIZE 0x00000010u +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0u +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4u +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8u +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfcu +#define CYDEV_TPIU_BASE 0xe0040000u +#define CYDEV_TPIU_SIZE 0x00001000u +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000u +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004u +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010u +#define CYREG_TPIU_PROTOCOL 0xe00400f0u +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300u +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304u +#define CYREG_TPIU_TRIGGER 0xe0040ee8u +#define CYREG_TPIU_ITETMDATA 0xe0040eecu +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0u +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8u +#define CYREG_TPIU_ITITMDATA 0xe0040efcu +#define CYREG_TPIU_ITCTRL 0xe0040f00u +#define CYREG_TPIU_DEVID 0xe0040fc8u +#define CYREG_TPIU_DEVTYPE 0xe0040fccu +#define CYREG_TPIU_PID4 0xe0040fd0u +#define CYREG_TPIU_PID5 0xe0040fd4u +#define CYREG_TPIU_PID6 0xe0040fd8u +#define CYREG_TPIU_PID7 0xe0040fdcu +#define CYREG_TPIU_PID0 0xe0040fe0u +#define CYREG_TPIU_PID1 0xe0040fe4u +#define CYREG_TPIU_PID2 0xe0040fe8u +#define CYREG_TPIU_PID3 0xe0040fecu +#define CYREG_TPIU_CID0 0xe0040ff0u +#define CYREG_TPIU_CID1 0xe0040ff4u +#define CYREG_TPIU_CID2 0xe0040ff8u +#define CYREG_TPIU_CID3 0xe0040ffcu +#define CYDEV_ETM_BASE 0xe0041000u +#define CYDEV_ETM_SIZE 0x00001000u +#define CYREG_ETM_CTL 0xe0041000u +#define CYREG_ETM_CFG_CODE 0xe0041004u +#define CYREG_ETM_TRIG_EVENT 0xe0041008u +#define CYREG_ETM_STATUS 0xe0041010u +#define CYREG_ETM_SYS_CFG 0xe0041014u +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020u +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024u +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102cu +#define CYREG_ETM_SYNC_FREQ 0xe00411e0u +#define CYREG_ETM_ETM_ID 0xe00411e4u +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8u +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0u +#define CYREG_ETM_CS_TRACE_ID 0xe0041200u +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300u +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304u +#define CYREG_ETM_PDSR 0xe0041314u +#define CYREG_ETM_ITMISCIN 0xe0041ee0u +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8u +#define CYREG_ETM_ITATBCTR2 0xe0041ef0u +#define CYREG_ETM_ITATBCTR0 0xe0041ef8u +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00u +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0u +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4u +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0u +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4u +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8u +#define CYREG_ETM_DEV_TYPE 0xe0041fccu +#define CYREG_ETM_PID4 0xe0041fd0u +#define CYREG_ETM_PID5 0xe0041fd4u +#define CYREG_ETM_PID6 0xe0041fd8u +#define CYREG_ETM_PID7 0xe0041fdcu +#define CYREG_ETM_PID0 0xe0041fe0u +#define CYREG_ETM_PID1 0xe0041fe4u +#define CYREG_ETM_PID2 0xe0041fe8u +#define CYREG_ETM_PID3 0xe0041fecu +#define CYREG_ETM_CID0 0xe0041ff0u +#define CYREG_ETM_CID1 0xe0041ff4u +#define CYREG_ETM_CID2 0xe0041ff8u +#define CYREG_ETM_CID3 0xe0041ffcu +#define CYDEV_ROM_TABLE_BASE 0xe00ff000u +#define CYDEV_ROM_TABLE_SIZE 0x00001000u +#define CYREG_ROM_TABLE_NVIC 0xe00ff000u +#define CYREG_ROM_TABLE_DWT 0xe00ff004u +#define CYREG_ROM_TABLE_FPB 0xe00ff008u +#define CYREG_ROM_TABLE_ITM 0xe00ff00cu +#define CYREG_ROM_TABLE_TPIU 0xe00ff010u +#define CYREG_ROM_TABLE_ETM 0xe00ff014u +#define CYREG_ROM_TABLE_END 0xe00ff018u +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffccu +#define CYREG_ROM_TABLE_PID4 0xe00fffd0u +#define CYREG_ROM_TABLE_PID5 0xe00fffd4u +#define CYREG_ROM_TABLE_PID6 0xe00fffd8u +#define CYREG_ROM_TABLE_PID7 0xe00fffdcu +#define CYREG_ROM_TABLE_PID0 0xe00fffe0u +#define CYREG_ROM_TABLE_PID1 0xe00fffe4u +#define CYREG_ROM_TABLE_PID2 0xe00fffe8u +#define CYREG_ROM_TABLE_PID3 0xe00fffecu +#define CYREG_ROM_TABLE_CID0 0xe00ffff0u +#define CYREG_ROM_TABLE_CID1 0xe00ffff4u +#define CYREG_ROM_TABLE_CID2 0xe00ffff8u +#define CYREG_ROM_TABLE_CID3 0xe00ffffcu +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000u +#define CYDEV_FLS_ROW_SIZE 0x00000100u +#define CYDEV_ECC_SECTOR_SIZE 0x00002000u +#define CYDEV_ECC_ROW_SIZE 0x00000020u +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400u +#define CYDEV_EEPROM_ROW_SIZE 0x00000010u +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004u +#define CYCLK_LD_SYNC_EN 0x00000002u +#define CYCLK_LD_LOAD 0x00000001u +#define CYCLK_PIPE 0x00000080u +#define CYCLK_SSS 0x00000040u +#define CYCLK_EARLY 0x00000020u +#define CYCLK_DUTY 0x00000010u +#define CYCLK_SYNC 0x00000008u +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 +#endif /* CYDEVICE_TRM_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc new file mode 100644 index 0000000..754b960 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* File Name: cydevicegnu.inc +* OBSOLETE: Do not use this file. Use the _trm version instead. +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYDEV_FLASH_DATA_MBASE, 0x00000000 +.set CYDEV_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYDEV_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYDEV_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYDEV_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYDEV_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_CODE_MBASE, 0x1fffc000 +.set CYDEV_SRAM_CODE_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA_MBASE, 0x20000000 +.set CYDEV_SRAM_DATA_MSIZE, 0x00004000 +.set CYDEV_SRAM_DATA16K_MBASE, 0x20001000 +.set CYDEV_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYDEV_SRAM_DATA32K_MBASE, 0x20002000 +.set CYDEV_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYDEV_SRAM_DATA64K_MBASE, 0x20004000 +.set CYDEV_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYDEV_DMA_SRAM64K_MBASE, 0x20008000 +.set CYDEV_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYDEV_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYDEV_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYDEV_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYDEV_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYDEV_DMA_SRAM_MBASE, 0x2000f000 +.set CYDEV_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYDEV_CLKDIST_CR, 0x40004000 +.set CYDEV_CLKDIST_LD, 0x40004001 +.set CYDEV_CLKDIST_WRK0, 0x40004002 +.set CYDEV_CLKDIST_WRK1, 0x40004003 +.set CYDEV_CLKDIST_MSTR0, 0x40004004 +.set CYDEV_CLKDIST_MSTR1, 0x40004005 +.set CYDEV_CLKDIST_BCFG0, 0x40004006 +.set CYDEV_CLKDIST_BCFG1, 0x40004007 +.set CYDEV_CLKDIST_BCFG2, 0x40004008 +.set CYDEV_CLKDIST_UCFG, 0x40004009 +.set CYDEV_CLKDIST_DLY0, 0x4000400a +.set CYDEV_CLKDIST_DLY1, 0x4000400b +.set CYDEV_CLKDIST_DMASK, 0x40004010 +.set CYDEV_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYDEV_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYDEV_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYDEV_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYDEV_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYDEV_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYDEV_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYDEV_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYDEV_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYDEV_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYDEV_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYDEV_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYDEV_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYDEV_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYDEV_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYDEV_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYDEV_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYDEV_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYDEV_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYDEV_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYDEV_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYDEV_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYDEV_FASTCLK_PLL_CFG0, 0x40004220 +.set CYDEV_FASTCLK_PLL_CFG1, 0x40004221 +.set CYDEV_FASTCLK_PLL_P, 0x40004222 +.set CYDEV_FASTCLK_PLL_Q, 0x40004223 +.set CYDEV_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYDEV_SLOWCLK_ILO_CR0, 0x40004300 +.set CYDEV_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYDEV_SLOWCLK_X32_CR, 0x40004308 +.set CYDEV_SLOWCLK_X32_CFG, 0x40004309 +.set CYDEV_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYDEV_BOOST_CR0, 0x40004320 +.set CYDEV_BOOST_CR1, 0x40004321 +.set CYDEV_BOOST_CR2, 0x40004322 +.set CYDEV_BOOST_CR3, 0x40004323 +.set CYDEV_BOOST_SR, 0x40004324 +.set CYDEV_BOOST_CR4, 0x40004325 +.set CYDEV_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYDEV_PWRSYS_CR0, 0x40004330 +.set CYDEV_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYDEV_PM_TW_CFG0, 0x40004380 +.set CYDEV_PM_TW_CFG1, 0x40004381 +.set CYDEV_PM_TW_CFG2, 0x40004382 +.set CYDEV_PM_WDT_CFG, 0x40004383 +.set CYDEV_PM_WDT_CR, 0x40004384 +.set CYDEV_PM_INT_SR, 0x40004390 +.set CYDEV_PM_MODE_CFG0, 0x40004391 +.set CYDEV_PM_MODE_CFG1, 0x40004392 +.set CYDEV_PM_MODE_CSR, 0x40004393 +.set CYDEV_PM_USB_CR0, 0x40004394 +.set CYDEV_PM_WAKEUP_CFG0, 0x40004398 +.set CYDEV_PM_WAKEUP_CFG1, 0x40004399 +.set CYDEV_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYDEV_PM_ACT_CFG0, 0x400043a0 +.set CYDEV_PM_ACT_CFG1, 0x400043a1 +.set CYDEV_PM_ACT_CFG2, 0x400043a2 +.set CYDEV_PM_ACT_CFG3, 0x400043a3 +.set CYDEV_PM_ACT_CFG4, 0x400043a4 +.set CYDEV_PM_ACT_CFG5, 0x400043a5 +.set CYDEV_PM_ACT_CFG6, 0x400043a6 +.set CYDEV_PM_ACT_CFG7, 0x400043a7 +.set CYDEV_PM_ACT_CFG8, 0x400043a8 +.set CYDEV_PM_ACT_CFG9, 0x400043a9 +.set CYDEV_PM_ACT_CFG10, 0x400043aa +.set CYDEV_PM_ACT_CFG11, 0x400043ab +.set CYDEV_PM_ACT_CFG12, 0x400043ac +.set CYDEV_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYDEV_PM_STBY_CFG0, 0x400043b0 +.set CYDEV_PM_STBY_CFG1, 0x400043b1 +.set CYDEV_PM_STBY_CFG2, 0x400043b2 +.set CYDEV_PM_STBY_CFG3, 0x400043b3 +.set CYDEV_PM_STBY_CFG4, 0x400043b4 +.set CYDEV_PM_STBY_CFG5, 0x400043b5 +.set CYDEV_PM_STBY_CFG6, 0x400043b6 +.set CYDEV_PM_STBY_CFG7, 0x400043b7 +.set CYDEV_PM_STBY_CFG8, 0x400043b8 +.set CYDEV_PM_STBY_CFG9, 0x400043b9 +.set CYDEV_PM_STBY_CFG10, 0x400043ba +.set CYDEV_PM_STBY_CFG11, 0x400043bb +.set CYDEV_PM_STBY_CFG12, 0x400043bc +.set CYDEV_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYDEV_PM_AVAIL_CR0, 0x400043c0 +.set CYDEV_PM_AVAIL_CR1, 0x400043c1 +.set CYDEV_PM_AVAIL_CR2, 0x400043c2 +.set CYDEV_PM_AVAIL_CR3, 0x400043c3 +.set CYDEV_PM_AVAIL_CR4, 0x400043c4 +.set CYDEV_PM_AVAIL_CR5, 0x400043c5 +.set CYDEV_PM_AVAIL_CR6, 0x400043c6 +.set CYDEV_PM_AVAIL_SR0, 0x400043d0 +.set CYDEV_PM_AVAIL_SR1, 0x400043d1 +.set CYDEV_PM_AVAIL_SR2, 0x400043d2 +.set CYDEV_PM_AVAIL_SR3, 0x400043d3 +.set CYDEV_PM_AVAIL_SR4, 0x400043d4 +.set CYDEV_PM_AVAIL_SR5, 0x400043d5 +.set CYDEV_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE0, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE1, 0x40004501 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE2, 0x40004502 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE3, 0x40004503 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE4, 0x40004504 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE5, 0x40004505 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE6, 0x40004506 +.set CYDEV_PICU_INTTYPE_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE0, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE1, 0x40004509 +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE2, 0x4000450a +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE3, 0x4000450b +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE4, 0x4000450c +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE5, 0x4000450d +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE6, 0x4000450e +.set CYDEV_PICU_INTTYPE_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE0, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE1, 0x40004511 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE2, 0x40004512 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE3, 0x40004513 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE4, 0x40004514 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE5, 0x40004515 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE6, 0x40004516 +.set CYDEV_PICU_INTTYPE_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE0, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE1, 0x40004519 +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE2, 0x4000451a +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE3, 0x4000451b +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE4, 0x4000451c +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE5, 0x4000451d +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE6, 0x4000451e +.set CYDEV_PICU_INTTYPE_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE0, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE1, 0x40004521 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE2, 0x40004522 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE3, 0x40004523 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE4, 0x40004524 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE5, 0x40004525 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE6, 0x40004526 +.set CYDEV_PICU_INTTYPE_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE0, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE1, 0x40004529 +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE2, 0x4000452a +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE3, 0x4000452b +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE4, 0x4000452c +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE5, 0x4000452d +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE6, 0x4000452e +.set CYDEV_PICU_INTTYPE_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE0, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE1, 0x40004531 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE2, 0x40004532 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE3, 0x40004533 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE4, 0x40004534 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE5, 0x40004535 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE6, 0x40004536 +.set CYDEV_PICU_INTTYPE_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE0, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE1, 0x40004561 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE2, 0x40004562 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE3, 0x40004563 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE4, 0x40004564 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE5, 0x40004565 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE6, 0x40004566 +.set CYDEV_PICU_INTTYPE_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE0, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE1, 0x40004579 +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE2, 0x4000457a +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE3, 0x4000457b +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE4, 0x4000457c +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE5, 0x4000457d +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE6, 0x4000457e +.set CYDEV_PICU_INTTYPE_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_STAT_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYDEV_PICU_SNAP_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYDEV_MFGCFG_ANAIF_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR0, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR0, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR0, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR0, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR0, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR0, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR0, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR0, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYDEV_MFGCFG_PWRSYS_HIB_TR0, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_HIB_TR1, 0x40004681 +.set CYDEV_MFGCFG_PWRSYS_I2C_TR, 0x40004682 +.set CYDEV_MFGCFG_PWRSYS_SLP_TR, 0x40004683 +.set CYDEV_MFGCFG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYDEV_MFGCFG_PWRSYS_BREF_TR, 0x40004687 +.set CYDEV_MFGCFG_PWRSYS_BG_TR, 0x40004688 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYDEV_MFGCFG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYDEV_MFGCFG_ILO_TR0, 0x40004690 +.set CYDEV_MFGCFG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYDEV_MFGCFG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYDEV_MFGCFG_IMO_TR0, 0x400046a0 +.set CYDEV_MFGCFG_IMO_TR1, 0x400046a1 +.set CYDEV_MFGCFG_IMO_GAIN, 0x400046a2 +.set CYDEV_MFGCFG_IMO_C36M, 0x400046a3 +.set CYDEV_MFGCFG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYDEV_MFGCFG_XMHZ_TR, 0x400046a8 +.set CYDEV_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYDEV_MFGCFG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYDEV_MFGCFG_MLOGIC_SEG_CR, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYDEV_MFGCFG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYDEV_RESET_IPOR_CR0, 0x400046f0 +.set CYDEV_RESET_IPOR_CR1, 0x400046f1 +.set CYDEV_RESET_IPOR_CR2, 0x400046f2 +.set CYDEV_RESET_IPOR_CR3, 0x400046f3 +.set CYDEV_RESET_CR0, 0x400046f4 +.set CYDEV_RESET_CR1, 0x400046f5 +.set CYDEV_RESET_CR2, 0x400046f6 +.set CYDEV_RESET_CR3, 0x400046f7 +.set CYDEV_RESET_CR4, 0x400046f8 +.set CYDEV_RESET_CR5, 0x400046f9 +.set CYDEV_RESET_SR0, 0x400046fa +.set CYDEV_RESET_SR1, 0x400046fb +.set CYDEV_RESET_SR2, 0x400046fc +.set CYDEV_RESET_SR3, 0x400046fd +.set CYDEV_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYDEV_SPC_FM_EE_CR, 0x40004700 +.set CYDEV_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYDEV_SPC_EE_SCR, 0x40004702 +.set CYDEV_SPC_EE_ERR, 0x40004703 +.set CYDEV_SPC_CPU_DATA, 0x40004720 +.set CYDEV_SPC_DMA_DATA, 0x40004721 +.set CYDEV_SPC_SR, 0x40004722 +.set CYDEV_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYDEV_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYDEV_CACHE_CC_CTL, 0x40004800 +.set CYDEV_CACHE_ECC_CORR, 0x40004880 +.set CYDEV_CACHE_ECC_ERR, 0x40004888 +.set CYDEV_CACHE_FLASH_ERR, 0x40004890 +.set CYDEV_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYDEV_I2C_XCFG, 0x400049c8 +.set CYDEV_I2C_ADR, 0x400049ca +.set CYDEV_I2C_CFG, 0x400049d6 +.set CYDEV_I2C_CSR, 0x400049d7 +.set CYDEV_I2C_D, 0x400049d8 +.set CYDEV_I2C_MCSR, 0x400049d9 +.set CYDEV_I2C_CLK_DIV1, 0x400049db +.set CYDEV_I2C_CLK_DIV2, 0x400049dc +.set CYDEV_I2C_TMOUT_CSR, 0x400049dd +.set CYDEV_I2C_TMOUT_SR, 0x400049de +.set CYDEV_I2C_TMOUT_CFG0, 0x400049df +.set CYDEV_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYDEV_DEC_CR, 0x40004e00 +.set CYDEV_DEC_SR, 0x40004e01 +.set CYDEV_DEC_SHIFT1, 0x40004e02 +.set CYDEV_DEC_SHIFT2, 0x40004e03 +.set CYDEV_DEC_DR2, 0x40004e04 +.set CYDEV_DEC_DR2H, 0x40004e05 +.set CYDEV_DEC_DR1, 0x40004e06 +.set CYDEV_DEC_OCOR, 0x40004e08 +.set CYDEV_DEC_OCORM, 0x40004e09 +.set CYDEV_DEC_OCORH, 0x40004e0a +.set CYDEV_DEC_GCOR, 0x40004e0c +.set CYDEV_DEC_GCORH, 0x40004e0d +.set CYDEV_DEC_GVAL, 0x40004e0e +.set CYDEV_DEC_OUTSAMP, 0x40004e10 +.set CYDEV_DEC_OUTSAMPM, 0x40004e11 +.set CYDEV_DEC_OUTSAMPH, 0x40004e12 +.set CYDEV_DEC_OUTSAMPS, 0x40004e13 +.set CYDEV_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYDEV_TMR0_CFG0, 0x40004f00 +.set CYDEV_TMR0_CFG1, 0x40004f01 +.set CYDEV_TMR0_CFG2, 0x40004f02 +.set CYDEV_TMR0_SR0, 0x40004f03 +.set CYDEV_TMR0_PER0, 0x40004f04 +.set CYDEV_TMR0_PER1, 0x40004f05 +.set CYDEV_TMR0_CNT_CMP0, 0x40004f06 +.set CYDEV_TMR0_CNT_CMP1, 0x40004f07 +.set CYDEV_TMR0_CAP0, 0x40004f08 +.set CYDEV_TMR0_CAP1, 0x40004f09 +.set CYDEV_TMR0_RT0, 0x40004f0a +.set CYDEV_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYDEV_TMR1_CFG0, 0x40004f0c +.set CYDEV_TMR1_CFG1, 0x40004f0d +.set CYDEV_TMR1_CFG2, 0x40004f0e +.set CYDEV_TMR1_SR0, 0x40004f0f +.set CYDEV_TMR1_PER0, 0x40004f10 +.set CYDEV_TMR1_PER1, 0x40004f11 +.set CYDEV_TMR1_CNT_CMP0, 0x40004f12 +.set CYDEV_TMR1_CNT_CMP1, 0x40004f13 +.set CYDEV_TMR1_CAP0, 0x40004f14 +.set CYDEV_TMR1_CAP1, 0x40004f15 +.set CYDEV_TMR1_RT0, 0x40004f16 +.set CYDEV_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYDEV_TMR2_CFG0, 0x40004f18 +.set CYDEV_TMR2_CFG1, 0x40004f19 +.set CYDEV_TMR2_CFG2, 0x40004f1a +.set CYDEV_TMR2_SR0, 0x40004f1b +.set CYDEV_TMR2_PER0, 0x40004f1c +.set CYDEV_TMR2_PER1, 0x40004f1d +.set CYDEV_TMR2_CNT_CMP0, 0x40004f1e +.set CYDEV_TMR2_CNT_CMP1, 0x40004f1f +.set CYDEV_TMR2_CAP0, 0x40004f20 +.set CYDEV_TMR2_CAP1, 0x40004f21 +.set CYDEV_TMR2_RT0, 0x40004f22 +.set CYDEV_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYDEV_TMR3_CFG0, 0x40004f24 +.set CYDEV_TMR3_CFG1, 0x40004f25 +.set CYDEV_TMR3_CFG2, 0x40004f26 +.set CYDEV_TMR3_SR0, 0x40004f27 +.set CYDEV_TMR3_PER0, 0x40004f28 +.set CYDEV_TMR3_PER1, 0x40004f29 +.set CYDEV_TMR3_CNT_CMP0, 0x40004f2a +.set CYDEV_TMR3_CNT_CMP1, 0x40004f2b +.set CYDEV_TMR3_CAP0, 0x40004f2c +.set CYDEV_TMR3_CAP1, 0x40004f2d +.set CYDEV_TMR3_RT0, 0x40004f2e +.set CYDEV_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT0_PC0, 0x40005000 +.set CYDEV_IO_PC_PRT0_PC1, 0x40005001 +.set CYDEV_IO_PC_PRT0_PC2, 0x40005002 +.set CYDEV_IO_PC_PRT0_PC3, 0x40005003 +.set CYDEV_IO_PC_PRT0_PC4, 0x40005004 +.set CYDEV_IO_PC_PRT0_PC5, 0x40005005 +.set CYDEV_IO_PC_PRT0_PC6, 0x40005006 +.set CYDEV_IO_PC_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT1_PC0, 0x40005008 +.set CYDEV_IO_PC_PRT1_PC1, 0x40005009 +.set CYDEV_IO_PC_PRT1_PC2, 0x4000500a +.set CYDEV_IO_PC_PRT1_PC3, 0x4000500b +.set CYDEV_IO_PC_PRT1_PC4, 0x4000500c +.set CYDEV_IO_PC_PRT1_PC5, 0x4000500d +.set CYDEV_IO_PC_PRT1_PC6, 0x4000500e +.set CYDEV_IO_PC_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT2_PC0, 0x40005010 +.set CYDEV_IO_PC_PRT2_PC1, 0x40005011 +.set CYDEV_IO_PC_PRT2_PC2, 0x40005012 +.set CYDEV_IO_PC_PRT2_PC3, 0x40005013 +.set CYDEV_IO_PC_PRT2_PC4, 0x40005014 +.set CYDEV_IO_PC_PRT2_PC5, 0x40005015 +.set CYDEV_IO_PC_PRT2_PC6, 0x40005016 +.set CYDEV_IO_PC_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT3_PC0, 0x40005018 +.set CYDEV_IO_PC_PRT3_PC1, 0x40005019 +.set CYDEV_IO_PC_PRT3_PC2, 0x4000501a +.set CYDEV_IO_PC_PRT3_PC3, 0x4000501b +.set CYDEV_IO_PC_PRT3_PC4, 0x4000501c +.set CYDEV_IO_PC_PRT3_PC5, 0x4000501d +.set CYDEV_IO_PC_PRT3_PC6, 0x4000501e +.set CYDEV_IO_PC_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT4_PC0, 0x40005020 +.set CYDEV_IO_PC_PRT4_PC1, 0x40005021 +.set CYDEV_IO_PC_PRT4_PC2, 0x40005022 +.set CYDEV_IO_PC_PRT4_PC3, 0x40005023 +.set CYDEV_IO_PC_PRT4_PC4, 0x40005024 +.set CYDEV_IO_PC_PRT4_PC5, 0x40005025 +.set CYDEV_IO_PC_PRT4_PC6, 0x40005026 +.set CYDEV_IO_PC_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT5_PC0, 0x40005028 +.set CYDEV_IO_PC_PRT5_PC1, 0x40005029 +.set CYDEV_IO_PC_PRT5_PC2, 0x4000502a +.set CYDEV_IO_PC_PRT5_PC3, 0x4000502b +.set CYDEV_IO_PC_PRT5_PC4, 0x4000502c +.set CYDEV_IO_PC_PRT5_PC5, 0x4000502d +.set CYDEV_IO_PC_PRT5_PC6, 0x4000502e +.set CYDEV_IO_PC_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT6_PC0, 0x40005030 +.set CYDEV_IO_PC_PRT6_PC1, 0x40005031 +.set CYDEV_IO_PC_PRT6_PC2, 0x40005032 +.set CYDEV_IO_PC_PRT6_PC3, 0x40005033 +.set CYDEV_IO_PC_PRT6_PC4, 0x40005034 +.set CYDEV_IO_PC_PRT6_PC5, 0x40005035 +.set CYDEV_IO_PC_PRT6_PC6, 0x40005036 +.set CYDEV_IO_PC_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYDEV_IO_PC_PRT12_PC0, 0x40005060 +.set CYDEV_IO_PC_PRT12_PC1, 0x40005061 +.set CYDEV_IO_PC_PRT12_PC2, 0x40005062 +.set CYDEV_IO_PC_PRT12_PC3, 0x40005063 +.set CYDEV_IO_PC_PRT12_PC4, 0x40005064 +.set CYDEV_IO_PC_PRT12_PC5, 0x40005065 +.set CYDEV_IO_PC_PRT12_PC6, 0x40005066 +.set CYDEV_IO_PC_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYDEV_IO_PC_PRT15_PC0, 0x40005078 +.set CYDEV_IO_PC_PRT15_PC1, 0x40005079 +.set CYDEV_IO_PC_PRT15_PC2, 0x4000507a +.set CYDEV_IO_PC_PRT15_PC3, 0x4000507b +.set CYDEV_IO_PC_PRT15_PC4, 0x4000507c +.set CYDEV_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYDEV_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_DR_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYDEV_IO_PS_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT0_DR, 0x40005100 +.set CYDEV_IO_PRT_PRT0_PS, 0x40005101 +.set CYDEV_IO_PRT_PRT0_DM0, 0x40005102 +.set CYDEV_IO_PRT_PRT0_DM1, 0x40005103 +.set CYDEV_IO_PRT_PRT0_DM2, 0x40005104 +.set CYDEV_IO_PRT_PRT0_SLW, 0x40005105 +.set CYDEV_IO_PRT_PRT0_BYP, 0x40005106 +.set CYDEV_IO_PRT_PRT0_BIE, 0x40005107 +.set CYDEV_IO_PRT_PRT0_INP_DIS, 0x40005108 +.set CYDEV_IO_PRT_PRT0_CTL, 0x40005109 +.set CYDEV_IO_PRT_PRT0_PRT, 0x4000510a +.set CYDEV_IO_PRT_PRT0_BIT_MASK, 0x4000510b +.set CYDEV_IO_PRT_PRT0_AMUX, 0x4000510c +.set CYDEV_IO_PRT_PRT0_AG, 0x4000510d +.set CYDEV_IO_PRT_PRT0_LCD_COM_SEG, 0x4000510e +.set CYDEV_IO_PRT_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT1_DR, 0x40005110 +.set CYDEV_IO_PRT_PRT1_PS, 0x40005111 +.set CYDEV_IO_PRT_PRT1_DM0, 0x40005112 +.set CYDEV_IO_PRT_PRT1_DM1, 0x40005113 +.set CYDEV_IO_PRT_PRT1_DM2, 0x40005114 +.set CYDEV_IO_PRT_PRT1_SLW, 0x40005115 +.set CYDEV_IO_PRT_PRT1_BYP, 0x40005116 +.set CYDEV_IO_PRT_PRT1_BIE, 0x40005117 +.set CYDEV_IO_PRT_PRT1_INP_DIS, 0x40005118 +.set CYDEV_IO_PRT_PRT1_CTL, 0x40005119 +.set CYDEV_IO_PRT_PRT1_PRT, 0x4000511a +.set CYDEV_IO_PRT_PRT1_BIT_MASK, 0x4000511b +.set CYDEV_IO_PRT_PRT1_AMUX, 0x4000511c +.set CYDEV_IO_PRT_PRT1_AG, 0x4000511d +.set CYDEV_IO_PRT_PRT1_LCD_COM_SEG, 0x4000511e +.set CYDEV_IO_PRT_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT2_DR, 0x40005120 +.set CYDEV_IO_PRT_PRT2_PS, 0x40005121 +.set CYDEV_IO_PRT_PRT2_DM0, 0x40005122 +.set CYDEV_IO_PRT_PRT2_DM1, 0x40005123 +.set CYDEV_IO_PRT_PRT2_DM2, 0x40005124 +.set CYDEV_IO_PRT_PRT2_SLW, 0x40005125 +.set CYDEV_IO_PRT_PRT2_BYP, 0x40005126 +.set CYDEV_IO_PRT_PRT2_BIE, 0x40005127 +.set CYDEV_IO_PRT_PRT2_INP_DIS, 0x40005128 +.set CYDEV_IO_PRT_PRT2_CTL, 0x40005129 +.set CYDEV_IO_PRT_PRT2_PRT, 0x4000512a +.set CYDEV_IO_PRT_PRT2_BIT_MASK, 0x4000512b +.set CYDEV_IO_PRT_PRT2_AMUX, 0x4000512c +.set CYDEV_IO_PRT_PRT2_AG, 0x4000512d +.set CYDEV_IO_PRT_PRT2_LCD_COM_SEG, 0x4000512e +.set CYDEV_IO_PRT_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT3_DR, 0x40005130 +.set CYDEV_IO_PRT_PRT3_PS, 0x40005131 +.set CYDEV_IO_PRT_PRT3_DM0, 0x40005132 +.set CYDEV_IO_PRT_PRT3_DM1, 0x40005133 +.set CYDEV_IO_PRT_PRT3_DM2, 0x40005134 +.set CYDEV_IO_PRT_PRT3_SLW, 0x40005135 +.set CYDEV_IO_PRT_PRT3_BYP, 0x40005136 +.set CYDEV_IO_PRT_PRT3_BIE, 0x40005137 +.set CYDEV_IO_PRT_PRT3_INP_DIS, 0x40005138 +.set CYDEV_IO_PRT_PRT3_CTL, 0x40005139 +.set CYDEV_IO_PRT_PRT3_PRT, 0x4000513a +.set CYDEV_IO_PRT_PRT3_BIT_MASK, 0x4000513b +.set CYDEV_IO_PRT_PRT3_AMUX, 0x4000513c +.set CYDEV_IO_PRT_PRT3_AG, 0x4000513d +.set CYDEV_IO_PRT_PRT3_LCD_COM_SEG, 0x4000513e +.set CYDEV_IO_PRT_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT4_DR, 0x40005140 +.set CYDEV_IO_PRT_PRT4_PS, 0x40005141 +.set CYDEV_IO_PRT_PRT4_DM0, 0x40005142 +.set CYDEV_IO_PRT_PRT4_DM1, 0x40005143 +.set CYDEV_IO_PRT_PRT4_DM2, 0x40005144 +.set CYDEV_IO_PRT_PRT4_SLW, 0x40005145 +.set CYDEV_IO_PRT_PRT4_BYP, 0x40005146 +.set CYDEV_IO_PRT_PRT4_BIE, 0x40005147 +.set CYDEV_IO_PRT_PRT4_INP_DIS, 0x40005148 +.set CYDEV_IO_PRT_PRT4_CTL, 0x40005149 +.set CYDEV_IO_PRT_PRT4_PRT, 0x4000514a +.set CYDEV_IO_PRT_PRT4_BIT_MASK, 0x4000514b +.set CYDEV_IO_PRT_PRT4_AMUX, 0x4000514c +.set CYDEV_IO_PRT_PRT4_AG, 0x4000514d +.set CYDEV_IO_PRT_PRT4_LCD_COM_SEG, 0x4000514e +.set CYDEV_IO_PRT_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT5_DR, 0x40005150 +.set CYDEV_IO_PRT_PRT5_PS, 0x40005151 +.set CYDEV_IO_PRT_PRT5_DM0, 0x40005152 +.set CYDEV_IO_PRT_PRT5_DM1, 0x40005153 +.set CYDEV_IO_PRT_PRT5_DM2, 0x40005154 +.set CYDEV_IO_PRT_PRT5_SLW, 0x40005155 +.set CYDEV_IO_PRT_PRT5_BYP, 0x40005156 +.set CYDEV_IO_PRT_PRT5_BIE, 0x40005157 +.set CYDEV_IO_PRT_PRT5_INP_DIS, 0x40005158 +.set CYDEV_IO_PRT_PRT5_CTL, 0x40005159 +.set CYDEV_IO_PRT_PRT5_PRT, 0x4000515a +.set CYDEV_IO_PRT_PRT5_BIT_MASK, 0x4000515b +.set CYDEV_IO_PRT_PRT5_AMUX, 0x4000515c +.set CYDEV_IO_PRT_PRT5_AG, 0x4000515d +.set CYDEV_IO_PRT_PRT5_LCD_COM_SEG, 0x4000515e +.set CYDEV_IO_PRT_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT6_DR, 0x40005160 +.set CYDEV_IO_PRT_PRT6_PS, 0x40005161 +.set CYDEV_IO_PRT_PRT6_DM0, 0x40005162 +.set CYDEV_IO_PRT_PRT6_DM1, 0x40005163 +.set CYDEV_IO_PRT_PRT6_DM2, 0x40005164 +.set CYDEV_IO_PRT_PRT6_SLW, 0x40005165 +.set CYDEV_IO_PRT_PRT6_BYP, 0x40005166 +.set CYDEV_IO_PRT_PRT6_BIE, 0x40005167 +.set CYDEV_IO_PRT_PRT6_INP_DIS, 0x40005168 +.set CYDEV_IO_PRT_PRT6_CTL, 0x40005169 +.set CYDEV_IO_PRT_PRT6_PRT, 0x4000516a +.set CYDEV_IO_PRT_PRT6_BIT_MASK, 0x4000516b +.set CYDEV_IO_PRT_PRT6_AMUX, 0x4000516c +.set CYDEV_IO_PRT_PRT6_AG, 0x4000516d +.set CYDEV_IO_PRT_PRT6_LCD_COM_SEG, 0x4000516e +.set CYDEV_IO_PRT_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT12_DR, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_PS, 0x400051c1 +.set CYDEV_IO_PRT_PRT12_DM0, 0x400051c2 +.set CYDEV_IO_PRT_PRT12_DM1, 0x400051c3 +.set CYDEV_IO_PRT_PRT12_DM2, 0x400051c4 +.set CYDEV_IO_PRT_PRT12_SLW, 0x400051c5 +.set CYDEV_IO_PRT_PRT12_BYP, 0x400051c6 +.set CYDEV_IO_PRT_PRT12_BIE, 0x400051c7 +.set CYDEV_IO_PRT_PRT12_INP_DIS, 0x400051c8 +.set CYDEV_IO_PRT_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYDEV_IO_PRT_PRT12_PRT, 0x400051ca +.set CYDEV_IO_PRT_PRT12_BIT_MASK, 0x400051cb +.set CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYDEV_IO_PRT_PRT12_AG, 0x400051cd +.set CYDEV_IO_PRT_PRT12_SIO_CFG, 0x400051ce +.set CYDEV_IO_PRT_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYDEV_IO_PRT_PRT15_DR, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_PS, 0x400051f1 +.set CYDEV_IO_PRT_PRT15_DM0, 0x400051f2 +.set CYDEV_IO_PRT_PRT15_DM1, 0x400051f3 +.set CYDEV_IO_PRT_PRT15_DM2, 0x400051f4 +.set CYDEV_IO_PRT_PRT15_SLW, 0x400051f5 +.set CYDEV_IO_PRT_PRT15_BYP, 0x400051f6 +.set CYDEV_IO_PRT_PRT15_BIE, 0x400051f7 +.set CYDEV_IO_PRT_PRT15_INP_DIS, 0x400051f8 +.set CYDEV_IO_PRT_PRT15_CTL, 0x400051f9 +.set CYDEV_IO_PRT_PRT15_PRT, 0x400051fa +.set CYDEV_IO_PRT_PRT15_BIT_MASK, 0x400051fb +.set CYDEV_IO_PRT_PRT15_AMUX, 0x400051fc +.set CYDEV_IO_PRT_PRT15_AG, 0x400051fd +.set CYDEV_IO_PRT_PRT15_LCD_COM_SEG, 0x400051fe +.set CYDEV_IO_PRT_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT0_OUT_SEL0, 0x40005200 +.set CYDEV_PRTDSI_PRT0_OUT_SEL1, 0x40005201 +.set CYDEV_PRTDSI_PRT0_OE_SEL0, 0x40005202 +.set CYDEV_PRTDSI_PRT0_OE_SEL1, 0x40005203 +.set CYDEV_PRTDSI_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYDEV_PRTDSI_PRT0_SYNC_OUT, 0x40005205 +.set CYDEV_PRTDSI_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT1_OUT_SEL0, 0x40005208 +.set CYDEV_PRTDSI_PRT1_OUT_SEL1, 0x40005209 +.set CYDEV_PRTDSI_PRT1_OE_SEL0, 0x4000520a +.set CYDEV_PRTDSI_PRT1_OE_SEL1, 0x4000520b +.set CYDEV_PRTDSI_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYDEV_PRTDSI_PRT1_SYNC_OUT, 0x4000520d +.set CYDEV_PRTDSI_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT2_OUT_SEL0, 0x40005210 +.set CYDEV_PRTDSI_PRT2_OUT_SEL1, 0x40005211 +.set CYDEV_PRTDSI_PRT2_OE_SEL0, 0x40005212 +.set CYDEV_PRTDSI_PRT2_OE_SEL1, 0x40005213 +.set CYDEV_PRTDSI_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYDEV_PRTDSI_PRT2_SYNC_OUT, 0x40005215 +.set CYDEV_PRTDSI_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT3_OUT_SEL0, 0x40005218 +.set CYDEV_PRTDSI_PRT3_OUT_SEL1, 0x40005219 +.set CYDEV_PRTDSI_PRT3_OE_SEL0, 0x4000521a +.set CYDEV_PRTDSI_PRT3_OE_SEL1, 0x4000521b +.set CYDEV_PRTDSI_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYDEV_PRTDSI_PRT3_SYNC_OUT, 0x4000521d +.set CYDEV_PRTDSI_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT4_OUT_SEL0, 0x40005220 +.set CYDEV_PRTDSI_PRT4_OUT_SEL1, 0x40005221 +.set CYDEV_PRTDSI_PRT4_OE_SEL0, 0x40005222 +.set CYDEV_PRTDSI_PRT4_OE_SEL1, 0x40005223 +.set CYDEV_PRTDSI_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYDEV_PRTDSI_PRT4_SYNC_OUT, 0x40005225 +.set CYDEV_PRTDSI_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT5_OUT_SEL0, 0x40005228 +.set CYDEV_PRTDSI_PRT5_OUT_SEL1, 0x40005229 +.set CYDEV_PRTDSI_PRT5_OE_SEL0, 0x4000522a +.set CYDEV_PRTDSI_PRT5_OE_SEL1, 0x4000522b +.set CYDEV_PRTDSI_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYDEV_PRTDSI_PRT5_SYNC_OUT, 0x4000522d +.set CYDEV_PRTDSI_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT6_OUT_SEL0, 0x40005230 +.set CYDEV_PRTDSI_PRT6_OUT_SEL1, 0x40005231 +.set CYDEV_PRTDSI_PRT6_OE_SEL0, 0x40005232 +.set CYDEV_PRTDSI_PRT6_OE_SEL1, 0x40005233 +.set CYDEV_PRTDSI_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYDEV_PRTDSI_PRT6_SYNC_OUT, 0x40005235 +.set CYDEV_PRTDSI_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYDEV_PRTDSI_PRT12_OUT_SEL0, 0x40005260 +.set CYDEV_PRTDSI_PRT12_OUT_SEL1, 0x40005261 +.set CYDEV_PRTDSI_PRT12_OE_SEL0, 0x40005262 +.set CYDEV_PRTDSI_PRT12_OE_SEL1, 0x40005263 +.set CYDEV_PRTDSI_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYDEV_PRTDSI_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYDEV_PRTDSI_PRT15_OUT_SEL0, 0x40005278 +.set CYDEV_PRTDSI_PRT15_OUT_SEL1, 0x40005279 +.set CYDEV_PRTDSI_PRT15_OE_SEL0, 0x4000527a +.set CYDEV_PRTDSI_PRT15_OE_SEL1, 0x4000527b +.set CYDEV_PRTDSI_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYDEV_PRTDSI_PRT15_SYNC_OUT, 0x4000527d +.set CYDEV_PRTDSI_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYDEV_EMIF_NO_UDB, 0x40005400 +.set CYDEV_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYDEV_EMIF_MEM_DWN, 0x40005402 +.set CYDEV_EMIF_MEMCLK_DIV, 0x40005403 +.set CYDEV_EMIF_CLOCK_EN, 0x40005404 +.set CYDEV_EMIF_EM_TYPE, 0x40005405 +.set CYDEV_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC0_CR0, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_CR1, 0x40005801 +.set CYDEV_ANAIF_CFG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC1_CR0, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_CR1, 0x40005805 +.set CYDEV_ANAIF_CFG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC2_CR0, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_CR1, 0x40005809 +.set CYDEV_ANAIF_CFG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_SC3_CR0, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_CR1, 0x4000580d +.set CYDEV_ANAIF_CFG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC0_CR0, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_CR1, 0x40005821 +.set CYDEV_ANAIF_CFG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC1_CR0, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_CR1, 0x40005825 +.set CYDEV_ANAIF_CFG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC2_CR0, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_CR1, 0x40005829 +.set CYDEV_ANAIF_CFG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYDEV_ANAIF_CFG_DAC3_CR0, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_CR1, 0x4000582d +.set CYDEV_ANAIF_CFG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT0_CR, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT1_CR, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT2_CR, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LUT3_CR, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP0_CR, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP1_CR, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP2_CR, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_OPAMP3_CR, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LCDDAC_CR0, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYDEV_ANAIF_CFG_BG_CR0, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_RSVD, 0x4000586d +.set CYDEV_ANAIF_CFG_BG_DFT0, 0x4000586e +.set CYDEV_ANAIF_CFG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSL_CFG0, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_CAPSR_CFG0, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_PUMP_CR0, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF0_CR0, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYDEV_ANAIF_CFG_LPF1_CR0, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYDEV_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYDEV_ANAIF_CFG_DSM0_CR0, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_CR1, 0x40005881 +.set CYDEV_ANAIF_CFG_DSM0_CR2, 0x40005882 +.set CYDEV_ANAIF_CFG_DSM0_CR3, 0x40005883 +.set CYDEV_ANAIF_CFG_DSM0_CR4, 0x40005884 +.set CYDEV_ANAIF_CFG_DSM0_CR5, 0x40005885 +.set CYDEV_ANAIF_CFG_DSM0_CR6, 0x40005886 +.set CYDEV_ANAIF_CFG_DSM0_CR7, 0x40005887 +.set CYDEV_ANAIF_CFG_DSM0_CR8, 0x40005888 +.set CYDEV_ANAIF_CFG_DSM0_CR9, 0x40005889 +.set CYDEV_ANAIF_CFG_DSM0_CR10, 0x4000588a +.set CYDEV_ANAIF_CFG_DSM0_CR11, 0x4000588b +.set CYDEV_ANAIF_CFG_DSM0_CR12, 0x4000588c +.set CYDEV_ANAIF_CFG_DSM0_CR13, 0x4000588d +.set CYDEV_ANAIF_CFG_DSM0_CR14, 0x4000588e +.set CYDEV_ANAIF_CFG_DSM0_CR15, 0x4000588f +.set CYDEV_ANAIF_CFG_DSM0_CR16, 0x40005890 +.set CYDEV_ANAIF_CFG_DSM0_CR17, 0x40005891 +.set CYDEV_ANAIF_CFG_DSM0_REF0, 0x40005892 +.set CYDEV_ANAIF_CFG_DSM0_REF1, 0x40005893 +.set CYDEV_ANAIF_CFG_DSM0_REF2, 0x40005894 +.set CYDEV_ANAIF_CFG_DSM0_REF3, 0x40005895 +.set CYDEV_ANAIF_CFG_DSM0_DEM0, 0x40005896 +.set CYDEV_ANAIF_CFG_DSM0_DEM1, 0x40005897 +.set CYDEV_ANAIF_CFG_DSM0_TST0, 0x40005898 +.set CYDEV_ANAIF_CFG_DSM0_TST1, 0x40005899 +.set CYDEV_ANAIF_CFG_DSM0_BUF0, 0x4000589a +.set CYDEV_ANAIF_CFG_DSM0_BUF1, 0x4000589b +.set CYDEV_ANAIF_CFG_DSM0_BUF2, 0x4000589c +.set CYDEV_ANAIF_CFG_DSM0_BUF3, 0x4000589d +.set CYDEV_ANAIF_CFG_DSM0_MISC, 0x4000589e +.set CYDEV_ANAIF_CFG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR0_CSR0, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_CSR1, 0x40005901 +.set CYDEV_ANAIF_CFG_SAR0_CSR2, 0x40005902 +.set CYDEV_ANAIF_CFG_SAR0_CSR3, 0x40005903 +.set CYDEV_ANAIF_CFG_SAR0_CSR4, 0x40005904 +.set CYDEV_ANAIF_CFG_SAR0_CSR5, 0x40005905 +.set CYDEV_ANAIF_CFG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYDEV_ANAIF_CFG_SAR1_CSR0, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_CSR1, 0x40005909 +.set CYDEV_ANAIF_CFG_SAR1_CSR2, 0x4000590a +.set CYDEV_ANAIF_CFG_SAR1_CSR3, 0x4000590b +.set CYDEV_ANAIF_CFG_SAR1_CSR4, 0x4000590c +.set CYDEV_ANAIF_CFG_SAR1_CSR5, 0x4000590d +.set CYDEV_ANAIF_CFG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC0_SW0, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SW2, 0x40005a02 +.set CYDEV_ANAIF_RT_SC0_SW3, 0x40005a03 +.set CYDEV_ANAIF_RT_SC0_SW4, 0x40005a04 +.set CYDEV_ANAIF_RT_SC0_SW6, 0x40005a06 +.set CYDEV_ANAIF_RT_SC0_SW7, 0x40005a07 +.set CYDEV_ANAIF_RT_SC0_SW8, 0x40005a08 +.set CYDEV_ANAIF_RT_SC0_SW10, 0x40005a0a +.set CYDEV_ANAIF_RT_SC0_CLK, 0x40005a0b +.set CYDEV_ANAIF_RT_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC1_SW0, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SW2, 0x40005a12 +.set CYDEV_ANAIF_RT_SC1_SW3, 0x40005a13 +.set CYDEV_ANAIF_RT_SC1_SW4, 0x40005a14 +.set CYDEV_ANAIF_RT_SC1_SW6, 0x40005a16 +.set CYDEV_ANAIF_RT_SC1_SW7, 0x40005a17 +.set CYDEV_ANAIF_RT_SC1_SW8, 0x40005a18 +.set CYDEV_ANAIF_RT_SC1_SW10, 0x40005a1a +.set CYDEV_ANAIF_RT_SC1_CLK, 0x40005a1b +.set CYDEV_ANAIF_RT_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC2_SW0, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SW2, 0x40005a22 +.set CYDEV_ANAIF_RT_SC2_SW3, 0x40005a23 +.set CYDEV_ANAIF_RT_SC2_SW4, 0x40005a24 +.set CYDEV_ANAIF_RT_SC2_SW6, 0x40005a26 +.set CYDEV_ANAIF_RT_SC2_SW7, 0x40005a27 +.set CYDEV_ANAIF_RT_SC2_SW8, 0x40005a28 +.set CYDEV_ANAIF_RT_SC2_SW10, 0x40005a2a +.set CYDEV_ANAIF_RT_SC2_CLK, 0x40005a2b +.set CYDEV_ANAIF_RT_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYDEV_ANAIF_RT_SC3_SW0, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SW2, 0x40005a32 +.set CYDEV_ANAIF_RT_SC3_SW3, 0x40005a33 +.set CYDEV_ANAIF_RT_SC3_SW4, 0x40005a34 +.set CYDEV_ANAIF_RT_SC3_SW6, 0x40005a36 +.set CYDEV_ANAIF_RT_SC3_SW7, 0x40005a37 +.set CYDEV_ANAIF_RT_SC3_SW8, 0x40005a38 +.set CYDEV_ANAIF_RT_SC3_SW10, 0x40005a3a +.set CYDEV_ANAIF_RT_SC3_CLK, 0x40005a3b +.set CYDEV_ANAIF_RT_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC0_SW0, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SW2, 0x40005a82 +.set CYDEV_ANAIF_RT_DAC0_SW3, 0x40005a83 +.set CYDEV_ANAIF_RT_DAC0_SW4, 0x40005a84 +.set CYDEV_ANAIF_RT_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC1_SW0, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SW2, 0x40005a8a +.set CYDEV_ANAIF_RT_DAC1_SW3, 0x40005a8b +.set CYDEV_ANAIF_RT_DAC1_SW4, 0x40005a8c +.set CYDEV_ANAIF_RT_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC2_SW0, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SW2, 0x40005a92 +.set CYDEV_ANAIF_RT_DAC2_SW3, 0x40005a93 +.set CYDEV_ANAIF_RT_DAC2_SW4, 0x40005a94 +.set CYDEV_ANAIF_RT_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DAC3_SW0, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SW2, 0x40005a9a +.set CYDEV_ANAIF_RT_DAC3_SW3, 0x40005a9b +.set CYDEV_ANAIF_RT_DAC3_SW4, 0x40005a9c +.set CYDEV_ANAIF_RT_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP0_SW0, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SW2, 0x40005ac2 +.set CYDEV_ANAIF_RT_CMP0_SW3, 0x40005ac3 +.set CYDEV_ANAIF_RT_CMP0_SW4, 0x40005ac4 +.set CYDEV_ANAIF_RT_CMP0_SW6, 0x40005ac6 +.set CYDEV_ANAIF_RT_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP1_SW0, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SW2, 0x40005aca +.set CYDEV_ANAIF_RT_CMP1_SW3, 0x40005acb +.set CYDEV_ANAIF_RT_CMP1_SW4, 0x40005acc +.set CYDEV_ANAIF_RT_CMP1_SW6, 0x40005ace +.set CYDEV_ANAIF_RT_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP2_SW0, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SW2, 0x40005ad2 +.set CYDEV_ANAIF_RT_CMP2_SW3, 0x40005ad3 +.set CYDEV_ANAIF_RT_CMP2_SW4, 0x40005ad4 +.set CYDEV_ANAIF_RT_CMP2_SW6, 0x40005ad6 +.set CYDEV_ANAIF_RT_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_CMP3_SW0, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SW2, 0x40005ada +.set CYDEV_ANAIF_RT_CMP3_SW3, 0x40005adb +.set CYDEV_ANAIF_RT_CMP3_SW4, 0x40005adc +.set CYDEV_ANAIF_RT_CMP3_SW6, 0x40005ade +.set CYDEV_ANAIF_RT_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_DSM0_SW0, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SW2, 0x40005b02 +.set CYDEV_ANAIF_RT_DSM0_SW3, 0x40005b03 +.set CYDEV_ANAIF_RT_DSM0_SW4, 0x40005b04 +.set CYDEV_ANAIF_RT_DSM0_SW6, 0x40005b06 +.set CYDEV_ANAIF_RT_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR0_SW0, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SW2, 0x40005b22 +.set CYDEV_ANAIF_RT_SAR0_SW3, 0x40005b23 +.set CYDEV_ANAIF_RT_SAR0_SW4, 0x40005b24 +.set CYDEV_ANAIF_RT_SAR0_SW6, 0x40005b26 +.set CYDEV_ANAIF_RT_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYDEV_ANAIF_RT_SAR1_SW0, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SW2, 0x40005b2a +.set CYDEV_ANAIF_RT_SAR1_SW3, 0x40005b2b +.set CYDEV_ANAIF_RT_SAR1_SW4, 0x40005b2c +.set CYDEV_ANAIF_RT_SAR1_SW6, 0x40005b2e +.set CYDEV_ANAIF_RT_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP0_MX, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP1_MX, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP2_MX, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYDEV_ANAIF_RT_OPAMP3_MX, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYDEV_ANAIF_RT_LCDDAC_SW0, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SW1, 0x40005b51 +.set CYDEV_ANAIF_RT_LCDDAC_SW2, 0x40005b52 +.set CYDEV_ANAIF_RT_LCDDAC_SW3, 0x40005b53 +.set CYDEV_ANAIF_RT_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYDEV_ANAIF_RT_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYDEV_ANAIF_RT_BUS_SW0, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SW2, 0x40005b5a +.set CYDEV_ANAIF_RT_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYDEV_ANAIF_RT_DFT_CR0, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_CR1, 0x40005b5d +.set CYDEV_ANAIF_RT_DFT_CR2, 0x40005b5e +.set CYDEV_ANAIF_RT_DFT_CR3, 0x40005b5f +.set CYDEV_ANAIF_RT_DFT_CR4, 0x40005b60 +.set CYDEV_ANAIF_RT_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_DSM0_OUT0, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_LUT_SR, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_WRK1, 0x40005b91 +.set CYDEV_ANAIF_WRK_LUT_MSK, 0x40005b92 +.set CYDEV_ANAIF_WRK_LUT_CLK, 0x40005b93 +.set CYDEV_ANAIF_WRK_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_CMP_WRK, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYDEV_ANAIF_WRK_SC_SR, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_WRK1, 0x40005b99 +.set CYDEV_ANAIF_WRK_SC_MSK, 0x40005b9a +.set CYDEV_ANAIF_WRK_SC_CMPINV, 0x40005b9b +.set CYDEV_ANAIF_WRK_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR0_WRK0, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYDEV_ANAIF_WRK_SAR1_WRK0, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYDEV_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYDEV_USB_EP0_DR0, 0x40006000 +.set CYDEV_USB_EP0_DR1, 0x40006001 +.set CYDEV_USB_EP0_DR2, 0x40006002 +.set CYDEV_USB_EP0_DR3, 0x40006003 +.set CYDEV_USB_EP0_DR4, 0x40006004 +.set CYDEV_USB_EP0_DR5, 0x40006005 +.set CYDEV_USB_EP0_DR6, 0x40006006 +.set CYDEV_USB_EP0_DR7, 0x40006007 +.set CYDEV_USB_CR0, 0x40006008 +.set CYDEV_USB_CR1, 0x40006009 +.set CYDEV_USB_SIE_EP_INT_EN, 0x4000600a +.set CYDEV_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP1_CNT0, 0x4000600c +.set CYDEV_USB_SIE_EP1_CNT1, 0x4000600d +.set CYDEV_USB_SIE_EP1_CR0, 0x4000600e +.set CYDEV_USB_USBIO_CR0, 0x40006010 +.set CYDEV_USB_USBIO_CR1, 0x40006012 +.set CYDEV_USB_DYN_RECONFIG, 0x40006014 +.set CYDEV_USB_SOF0, 0x40006018 +.set CYDEV_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP2_CNT0, 0x4000601c +.set CYDEV_USB_SIE_EP2_CNT1, 0x4000601d +.set CYDEV_USB_SIE_EP2_CR0, 0x4000601e +.set CYDEV_USB_EP0_CR, 0x40006028 +.set CYDEV_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP3_CNT0, 0x4000602c +.set CYDEV_USB_SIE_EP3_CNT1, 0x4000602d +.set CYDEV_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP4_CNT0, 0x4000603c +.set CYDEV_USB_SIE_EP4_CNT1, 0x4000603d +.set CYDEV_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP5_CNT0, 0x4000604c +.set CYDEV_USB_SIE_EP5_CNT1, 0x4000604d +.set CYDEV_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP6_CNT0, 0x4000605c +.set CYDEV_USB_SIE_EP6_CNT1, 0x4000605d +.set CYDEV_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP7_CNT0, 0x4000606c +.set CYDEV_USB_SIE_EP7_CNT1, 0x4000606d +.set CYDEV_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYDEV_USB_SIE_EP8_CNT0, 0x4000607c +.set CYDEV_USB_SIE_EP8_CNT1, 0x4000607d +.set CYDEV_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP1_CFG, 0x40006080 +.set CYDEV_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYDEV_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW1_WA, 0x40006084 +.set CYDEV_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYDEV_USB_ARB_RW1_RA, 0x40006086 +.set CYDEV_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYDEV_USB_ARB_RW1_DR, 0x40006088 +.set CYDEV_USB_BUF_SIZE, 0x4000608c +.set CYDEV_USB_EP_ACTIVE, 0x4000608e +.set CYDEV_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP2_CFG, 0x40006090 +.set CYDEV_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYDEV_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW2_WA, 0x40006094 +.set CYDEV_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYDEV_USB_ARB_RW2_RA, 0x40006096 +.set CYDEV_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYDEV_USB_ARB_RW2_DR, 0x40006098 +.set CYDEV_USB_ARB_CFG, 0x4000609c +.set CYDEV_USB_USB_CLK_EN, 0x4000609d +.set CYDEV_USB_ARB_INT_EN, 0x4000609e +.set CYDEV_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP3_CFG, 0x400060a0 +.set CYDEV_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYDEV_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW3_WA, 0x400060a4 +.set CYDEV_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYDEV_USB_ARB_RW3_RA, 0x400060a6 +.set CYDEV_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYDEV_USB_ARB_RW3_DR, 0x400060a8 +.set CYDEV_USB_CWA, 0x400060ac +.set CYDEV_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP4_CFG, 0x400060b0 +.set CYDEV_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYDEV_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW4_WA, 0x400060b4 +.set CYDEV_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYDEV_USB_ARB_RW4_RA, 0x400060b6 +.set CYDEV_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYDEV_USB_ARB_RW4_DR, 0x400060b8 +.set CYDEV_USB_DMA_THRES, 0x400060bc +.set CYDEV_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP5_CFG, 0x400060c0 +.set CYDEV_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYDEV_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW5_WA, 0x400060c4 +.set CYDEV_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYDEV_USB_ARB_RW5_RA, 0x400060c6 +.set CYDEV_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYDEV_USB_ARB_RW5_DR, 0x400060c8 +.set CYDEV_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP6_CFG, 0x400060d0 +.set CYDEV_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYDEV_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW6_WA, 0x400060d4 +.set CYDEV_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYDEV_USB_ARB_RW6_RA, 0x400060d6 +.set CYDEV_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYDEV_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP7_CFG, 0x400060e0 +.set CYDEV_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYDEV_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW7_WA, 0x400060e4 +.set CYDEV_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYDEV_USB_ARB_RW7_RA, 0x400060e6 +.set CYDEV_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYDEV_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYDEV_USB_ARB_EP8_CFG, 0x400060f0 +.set CYDEV_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYDEV_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYDEV_USB_ARB_RW8_WA, 0x400060f4 +.set CYDEV_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYDEV_USB_ARB_RW8_RA, 0x400060f6 +.set CYDEV_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYDEV_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYDEV_USB_MEM_DATA_MBASE, 0x40006100 +.set CYDEV_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B0_UDB00_A0, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A0, 0x40006401 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A0, 0x40006402 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A0, 0x40006403 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A0, 0x40006404 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A0, 0x40006405 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A0, 0x40006406 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A0, 0x40006407 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A0, 0x40006408 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A0, 0x40006409 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A0, 0x4000640a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A0, 0x4000640b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A0, 0x4000640c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A0, 0x4000640d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A0, 0x4000640e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A0, 0x4000640f +.set CYDEV_UWRK_UWRK8_B0_UDB00_A1, 0x40006410 +.set CYDEV_UWRK_UWRK8_B0_UDB01_A1, 0x40006411 +.set CYDEV_UWRK_UWRK8_B0_UDB02_A1, 0x40006412 +.set CYDEV_UWRK_UWRK8_B0_UDB03_A1, 0x40006413 +.set CYDEV_UWRK_UWRK8_B0_UDB04_A1, 0x40006414 +.set CYDEV_UWRK_UWRK8_B0_UDB05_A1, 0x40006415 +.set CYDEV_UWRK_UWRK8_B0_UDB06_A1, 0x40006416 +.set CYDEV_UWRK_UWRK8_B0_UDB07_A1, 0x40006417 +.set CYDEV_UWRK_UWRK8_B0_UDB08_A1, 0x40006418 +.set CYDEV_UWRK_UWRK8_B0_UDB09_A1, 0x40006419 +.set CYDEV_UWRK_UWRK8_B0_UDB10_A1, 0x4000641a +.set CYDEV_UWRK_UWRK8_B0_UDB11_A1, 0x4000641b +.set CYDEV_UWRK_UWRK8_B0_UDB12_A1, 0x4000641c +.set CYDEV_UWRK_UWRK8_B0_UDB13_A1, 0x4000641d +.set CYDEV_UWRK_UWRK8_B0_UDB14_A1, 0x4000641e +.set CYDEV_UWRK_UWRK8_B0_UDB15_A1, 0x4000641f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D0, 0x40006420 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D0, 0x40006421 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D0, 0x40006422 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D0, 0x40006423 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D0, 0x40006424 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D0, 0x40006425 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D0, 0x40006426 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D0, 0x40006427 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D0, 0x40006428 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D0, 0x40006429 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D0, 0x4000642a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D0, 0x4000642b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D0, 0x4000642c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D0, 0x4000642d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D0, 0x4000642e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D0, 0x4000642f +.set CYDEV_UWRK_UWRK8_B0_UDB00_D1, 0x40006430 +.set CYDEV_UWRK_UWRK8_B0_UDB01_D1, 0x40006431 +.set CYDEV_UWRK_UWRK8_B0_UDB02_D1, 0x40006432 +.set CYDEV_UWRK_UWRK8_B0_UDB03_D1, 0x40006433 +.set CYDEV_UWRK_UWRK8_B0_UDB04_D1, 0x40006434 +.set CYDEV_UWRK_UWRK8_B0_UDB05_D1, 0x40006435 +.set CYDEV_UWRK_UWRK8_B0_UDB06_D1, 0x40006436 +.set CYDEV_UWRK_UWRK8_B0_UDB07_D1, 0x40006437 +.set CYDEV_UWRK_UWRK8_B0_UDB08_D1, 0x40006438 +.set CYDEV_UWRK_UWRK8_B0_UDB09_D1, 0x40006439 +.set CYDEV_UWRK_UWRK8_B0_UDB10_D1, 0x4000643a +.set CYDEV_UWRK_UWRK8_B0_UDB11_D1, 0x4000643b +.set CYDEV_UWRK_UWRK8_B0_UDB12_D1, 0x4000643c +.set CYDEV_UWRK_UWRK8_B0_UDB13_D1, 0x4000643d +.set CYDEV_UWRK_UWRK8_B0_UDB14_D1, 0x4000643e +.set CYDEV_UWRK_UWRK8_B0_UDB15_D1, 0x4000643f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F0, 0x40006440 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F0, 0x40006441 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F0, 0x40006442 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F0, 0x40006443 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F0, 0x40006444 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F0, 0x40006445 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F0, 0x40006446 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F0, 0x40006447 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F0, 0x40006448 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F0, 0x40006449 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F0, 0x4000644a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F0, 0x4000644b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F0, 0x4000644c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F0, 0x4000644d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F0, 0x4000644e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F0, 0x4000644f +.set CYDEV_UWRK_UWRK8_B0_UDB00_F1, 0x40006450 +.set CYDEV_UWRK_UWRK8_B0_UDB01_F1, 0x40006451 +.set CYDEV_UWRK_UWRK8_B0_UDB02_F1, 0x40006452 +.set CYDEV_UWRK_UWRK8_B0_UDB03_F1, 0x40006453 +.set CYDEV_UWRK_UWRK8_B0_UDB04_F1, 0x40006454 +.set CYDEV_UWRK_UWRK8_B0_UDB05_F1, 0x40006455 +.set CYDEV_UWRK_UWRK8_B0_UDB06_F1, 0x40006456 +.set CYDEV_UWRK_UWRK8_B0_UDB07_F1, 0x40006457 +.set CYDEV_UWRK_UWRK8_B0_UDB08_F1, 0x40006458 +.set CYDEV_UWRK_UWRK8_B0_UDB09_F1, 0x40006459 +.set CYDEV_UWRK_UWRK8_B0_UDB10_F1, 0x4000645a +.set CYDEV_UWRK_UWRK8_B0_UDB11_F1, 0x4000645b +.set CYDEV_UWRK_UWRK8_B0_UDB12_F1, 0x4000645c +.set CYDEV_UWRK_UWRK8_B0_UDB13_F1, 0x4000645d +.set CYDEV_UWRK_UWRK8_B0_UDB14_F1, 0x4000645e +.set CYDEV_UWRK_UWRK8_B0_UDB15_F1, 0x4000645f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ST, 0x40006460 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ST, 0x40006461 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ST, 0x40006462 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ST, 0x40006463 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ST, 0x40006464 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ST, 0x40006465 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ST, 0x40006466 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ST, 0x40006467 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ST, 0x40006468 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ST, 0x40006469 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ST, 0x4000646a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ST, 0x4000646b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ST, 0x4000646c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ST, 0x4000646d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ST, 0x4000646e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ST, 0x4000646f +.set CYDEV_UWRK_UWRK8_B0_UDB00_CTL, 0x40006470 +.set CYDEV_UWRK_UWRK8_B0_UDB01_CTL, 0x40006471 +.set CYDEV_UWRK_UWRK8_B0_UDB02_CTL, 0x40006472 +.set CYDEV_UWRK_UWRK8_B0_UDB03_CTL, 0x40006473 +.set CYDEV_UWRK_UWRK8_B0_UDB04_CTL, 0x40006474 +.set CYDEV_UWRK_UWRK8_B0_UDB05_CTL, 0x40006475 +.set CYDEV_UWRK_UWRK8_B0_UDB06_CTL, 0x40006476 +.set CYDEV_UWRK_UWRK8_B0_UDB07_CTL, 0x40006477 +.set CYDEV_UWRK_UWRK8_B0_UDB08_CTL, 0x40006478 +.set CYDEV_UWRK_UWRK8_B0_UDB09_CTL, 0x40006479 +.set CYDEV_UWRK_UWRK8_B0_UDB10_CTL, 0x4000647a +.set CYDEV_UWRK_UWRK8_B0_UDB11_CTL, 0x4000647b +.set CYDEV_UWRK_UWRK8_B0_UDB12_CTL, 0x4000647c +.set CYDEV_UWRK_UWRK8_B0_UDB13_CTL, 0x4000647d +.set CYDEV_UWRK_UWRK8_B0_UDB14_CTL, 0x4000647e +.set CYDEV_UWRK_UWRK8_B0_UDB15_CTL, 0x4000647f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MSK, 0x40006480 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MSK, 0x40006481 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MSK, 0x40006482 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MSK, 0x40006483 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MSK, 0x40006484 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MSK, 0x40006485 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MSK, 0x40006486 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MSK, 0x40006487 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MSK, 0x40006488 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MSK, 0x40006489 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MSK, 0x4000648a +.set CYDEV_UWRK_UWRK8_B0_UDB11_MSK, 0x4000648b +.set CYDEV_UWRK_UWRK8_B0_UDB12_MSK, 0x4000648c +.set CYDEV_UWRK_UWRK8_B0_UDB13_MSK, 0x4000648d +.set CYDEV_UWRK_UWRK8_B0_UDB14_MSK, 0x4000648e +.set CYDEV_UWRK_UWRK8_B0_UDB15_MSK, 0x4000648f +.set CYDEV_UWRK_UWRK8_B0_UDB00_ACTL, 0x40006490 +.set CYDEV_UWRK_UWRK8_B0_UDB01_ACTL, 0x40006491 +.set CYDEV_UWRK_UWRK8_B0_UDB02_ACTL, 0x40006492 +.set CYDEV_UWRK_UWRK8_B0_UDB03_ACTL, 0x40006493 +.set CYDEV_UWRK_UWRK8_B0_UDB04_ACTL, 0x40006494 +.set CYDEV_UWRK_UWRK8_B0_UDB05_ACTL, 0x40006495 +.set CYDEV_UWRK_UWRK8_B0_UDB06_ACTL, 0x40006496 +.set CYDEV_UWRK_UWRK8_B0_UDB07_ACTL, 0x40006497 +.set CYDEV_UWRK_UWRK8_B0_UDB08_ACTL, 0x40006498 +.set CYDEV_UWRK_UWRK8_B0_UDB09_ACTL, 0x40006499 +.set CYDEV_UWRK_UWRK8_B0_UDB10_ACTL, 0x4000649a +.set CYDEV_UWRK_UWRK8_B0_UDB11_ACTL, 0x4000649b +.set CYDEV_UWRK_UWRK8_B0_UDB12_ACTL, 0x4000649c +.set CYDEV_UWRK_UWRK8_B0_UDB13_ACTL, 0x4000649d +.set CYDEV_UWRK_UWRK8_B0_UDB14_ACTL, 0x4000649e +.set CYDEV_UWRK_UWRK8_B0_UDB15_ACTL, 0x4000649f +.set CYDEV_UWRK_UWRK8_B0_UDB00_MC, 0x400064a0 +.set CYDEV_UWRK_UWRK8_B0_UDB01_MC, 0x400064a1 +.set CYDEV_UWRK_UWRK8_B0_UDB02_MC, 0x400064a2 +.set CYDEV_UWRK_UWRK8_B0_UDB03_MC, 0x400064a3 +.set CYDEV_UWRK_UWRK8_B0_UDB04_MC, 0x400064a4 +.set CYDEV_UWRK_UWRK8_B0_UDB05_MC, 0x400064a5 +.set CYDEV_UWRK_UWRK8_B0_UDB06_MC, 0x400064a6 +.set CYDEV_UWRK_UWRK8_B0_UDB07_MC, 0x400064a7 +.set CYDEV_UWRK_UWRK8_B0_UDB08_MC, 0x400064a8 +.set CYDEV_UWRK_UWRK8_B0_UDB09_MC, 0x400064a9 +.set CYDEV_UWRK_UWRK8_B0_UDB10_MC, 0x400064aa +.set CYDEV_UWRK_UWRK8_B0_UDB11_MC, 0x400064ab +.set CYDEV_UWRK_UWRK8_B0_UDB12_MC, 0x400064ac +.set CYDEV_UWRK_UWRK8_B0_UDB13_MC, 0x400064ad +.set CYDEV_UWRK_UWRK8_B0_UDB14_MC, 0x400064ae +.set CYDEV_UWRK_UWRK8_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYDEV_UWRK_UWRK8_B1_UDB04_A0, 0x40006504 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A0, 0x40006505 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A0, 0x40006506 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A0, 0x40006507 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A0, 0x40006508 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A0, 0x40006509 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A0, 0x4000650a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A0, 0x4000650b +.set CYDEV_UWRK_UWRK8_B1_UDB04_A1, 0x40006514 +.set CYDEV_UWRK_UWRK8_B1_UDB05_A1, 0x40006515 +.set CYDEV_UWRK_UWRK8_B1_UDB06_A1, 0x40006516 +.set CYDEV_UWRK_UWRK8_B1_UDB07_A1, 0x40006517 +.set CYDEV_UWRK_UWRK8_B1_UDB08_A1, 0x40006518 +.set CYDEV_UWRK_UWRK8_B1_UDB09_A1, 0x40006519 +.set CYDEV_UWRK_UWRK8_B1_UDB10_A1, 0x4000651a +.set CYDEV_UWRK_UWRK8_B1_UDB11_A1, 0x4000651b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D0, 0x40006524 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D0, 0x40006525 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D0, 0x40006526 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D0, 0x40006527 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D0, 0x40006528 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D0, 0x40006529 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D0, 0x4000652a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D0, 0x4000652b +.set CYDEV_UWRK_UWRK8_B1_UDB04_D1, 0x40006534 +.set CYDEV_UWRK_UWRK8_B1_UDB05_D1, 0x40006535 +.set CYDEV_UWRK_UWRK8_B1_UDB06_D1, 0x40006536 +.set CYDEV_UWRK_UWRK8_B1_UDB07_D1, 0x40006537 +.set CYDEV_UWRK_UWRK8_B1_UDB08_D1, 0x40006538 +.set CYDEV_UWRK_UWRK8_B1_UDB09_D1, 0x40006539 +.set CYDEV_UWRK_UWRK8_B1_UDB10_D1, 0x4000653a +.set CYDEV_UWRK_UWRK8_B1_UDB11_D1, 0x4000653b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F0, 0x40006544 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F0, 0x40006545 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F0, 0x40006546 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F0, 0x40006547 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F0, 0x40006548 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F0, 0x40006549 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F0, 0x4000654a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F0, 0x4000654b +.set CYDEV_UWRK_UWRK8_B1_UDB04_F1, 0x40006554 +.set CYDEV_UWRK_UWRK8_B1_UDB05_F1, 0x40006555 +.set CYDEV_UWRK_UWRK8_B1_UDB06_F1, 0x40006556 +.set CYDEV_UWRK_UWRK8_B1_UDB07_F1, 0x40006557 +.set CYDEV_UWRK_UWRK8_B1_UDB08_F1, 0x40006558 +.set CYDEV_UWRK_UWRK8_B1_UDB09_F1, 0x40006559 +.set CYDEV_UWRK_UWRK8_B1_UDB10_F1, 0x4000655a +.set CYDEV_UWRK_UWRK8_B1_UDB11_F1, 0x4000655b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ST, 0x40006564 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ST, 0x40006565 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ST, 0x40006566 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ST, 0x40006567 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ST, 0x40006568 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ST, 0x40006569 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ST, 0x4000656a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ST, 0x4000656b +.set CYDEV_UWRK_UWRK8_B1_UDB04_CTL, 0x40006574 +.set CYDEV_UWRK_UWRK8_B1_UDB05_CTL, 0x40006575 +.set CYDEV_UWRK_UWRK8_B1_UDB06_CTL, 0x40006576 +.set CYDEV_UWRK_UWRK8_B1_UDB07_CTL, 0x40006577 +.set CYDEV_UWRK_UWRK8_B1_UDB08_CTL, 0x40006578 +.set CYDEV_UWRK_UWRK8_B1_UDB09_CTL, 0x40006579 +.set CYDEV_UWRK_UWRK8_B1_UDB10_CTL, 0x4000657a +.set CYDEV_UWRK_UWRK8_B1_UDB11_CTL, 0x4000657b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MSK, 0x40006584 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MSK, 0x40006585 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MSK, 0x40006586 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MSK, 0x40006587 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MSK, 0x40006588 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MSK, 0x40006589 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MSK, 0x4000658a +.set CYDEV_UWRK_UWRK8_B1_UDB11_MSK, 0x4000658b +.set CYDEV_UWRK_UWRK8_B1_UDB04_ACTL, 0x40006594 +.set CYDEV_UWRK_UWRK8_B1_UDB05_ACTL, 0x40006595 +.set CYDEV_UWRK_UWRK8_B1_UDB06_ACTL, 0x40006596 +.set CYDEV_UWRK_UWRK8_B1_UDB07_ACTL, 0x40006597 +.set CYDEV_UWRK_UWRK8_B1_UDB08_ACTL, 0x40006598 +.set CYDEV_UWRK_UWRK8_B1_UDB09_ACTL, 0x40006599 +.set CYDEV_UWRK_UWRK8_B1_UDB10_ACTL, 0x4000659a +.set CYDEV_UWRK_UWRK8_B1_UDB11_ACTL, 0x4000659b +.set CYDEV_UWRK_UWRK8_B1_UDB04_MC, 0x400065a4 +.set CYDEV_UWRK_UWRK8_B1_UDB05_MC, 0x400065a5 +.set CYDEV_UWRK_UWRK8_B1_UDB06_MC, 0x400065a6 +.set CYDEV_UWRK_UWRK8_B1_UDB07_MC, 0x400065a7 +.set CYDEV_UWRK_UWRK8_B1_UDB08_MC, 0x400065a8 +.set CYDEV_UWRK_UWRK8_B1_UDB09_MC, 0x400065a9 +.set CYDEV_UWRK_UWRK8_B1_UDB10_MC, 0x400065aa +.set CYDEV_UWRK_UWRK8_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1, 0x40006802 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1, 0x40006804 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1, 0x40006806 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1, 0x40006808 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1, 0x4000680a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1, 0x4000680c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1, 0x4000680e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1, 0x40006810 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1, 0x40006812 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1, 0x40006814 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1, 0x40006816 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1, 0x40006818 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1, 0x4000681a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1, 0x4000681c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1, 0x4000681e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1, 0x40006840 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1, 0x40006842 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1, 0x40006844 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1, 0x40006846 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1, 0x40006848 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1, 0x4000684a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1, 0x4000684c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1, 0x4000684e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1, 0x40006850 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1, 0x40006852 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1, 0x40006854 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1, 0x40006856 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1, 0x40006858 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1, 0x4000685a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1, 0x4000685c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1, 0x4000685e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1, 0x40006880 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1, 0x40006882 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1, 0x40006884 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1, 0x40006886 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1, 0x40006888 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1, 0x4000688a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1, 0x4000688c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1, 0x4000688e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1, 0x40006890 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1, 0x40006892 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1, 0x40006894 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1, 0x40006896 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1, 0x40006898 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1, 0x4000689a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1, 0x4000689c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1, 0x4000689e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL, 0x400068c0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL, 0x400068c2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL, 0x400068c4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL, 0x400068c6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL, 0x400068c8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL, 0x400068ca +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL, 0x400068cc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL, 0x400068ce +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL, 0x400068d0 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL, 0x400068d2 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL, 0x400068d4 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL, 0x400068d6 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL, 0x400068d8 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL, 0x400068da +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL, 0x400068dc +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL, 0x400068de +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00, 0x40006940 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00, 0x40006942 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00, 0x40006944 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00, 0x40006946 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00, 0x40006948 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00, 0x4000694a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00, 0x4000694c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00, 0x4000694e +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00, 0x40006950 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00, 0x40006952 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00, 0x40006954 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00, 0x40006956 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00, 0x40006958 +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00, 0x4000695a +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00, 0x4000695c +.set CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1, 0x40006a08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1, 0x40006a0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1, 0x40006a0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1, 0x40006a0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1, 0x40006a10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1, 0x40006a12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1, 0x40006a14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1, 0x40006a16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1, 0x40006a48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1, 0x40006a4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1, 0x40006a4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1, 0x40006a4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1, 0x40006a50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1, 0x40006a52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1, 0x40006a54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1, 0x40006a56 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1, 0x40006a88 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1, 0x40006a8a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1, 0x40006a8c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1, 0x40006a8e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1, 0x40006a90 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1, 0x40006a92 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1, 0x40006a94 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1, 0x40006a96 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL, 0x40006aca +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL, 0x40006acc +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL, 0x40006ace +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00, 0x40006b48 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00, 0x40006b4a +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00, 0x40006b4c +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00, 0x40006b4e +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00, 0x40006b50 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00, 0x40006b52 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00, 0x40006b54 +.set CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0, 0x40006802 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0, 0x40006804 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0, 0x40006806 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0, 0x40006808 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0, 0x4000680a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0, 0x4000680c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0, 0x4000680e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0, 0x40006810 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0, 0x40006812 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0, 0x40006814 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0, 0x40006816 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0, 0x40006818 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0, 0x4000681a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0, 0x4000681c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1, 0x40006820 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1, 0x40006822 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1, 0x40006824 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1, 0x40006826 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1, 0x40006828 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1, 0x4000682a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1, 0x4000682c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1, 0x4000682e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1, 0x40006830 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1, 0x40006832 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1, 0x40006834 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1, 0x40006836 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1, 0x40006838 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1, 0x4000683a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1, 0x4000683c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0, 0x40006840 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0, 0x40006842 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0, 0x40006844 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0, 0x40006846 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0, 0x40006848 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0, 0x4000684a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0, 0x4000684c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0, 0x4000684e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0, 0x40006850 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0, 0x40006852 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0, 0x40006854 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0, 0x40006856 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0, 0x40006858 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0, 0x4000685a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0, 0x4000685c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1, 0x40006860 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1, 0x40006862 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1, 0x40006864 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1, 0x40006866 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1, 0x40006868 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1, 0x4000686a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1, 0x4000686c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1, 0x4000686e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1, 0x40006870 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1, 0x40006872 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1, 0x40006874 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1, 0x40006876 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1, 0x40006878 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1, 0x4000687a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1, 0x4000687c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0, 0x40006880 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0, 0x40006882 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0, 0x40006884 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0, 0x40006886 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0, 0x40006888 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0, 0x4000688a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0, 0x4000688c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0, 0x4000688e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0, 0x40006890 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0, 0x40006892 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0, 0x40006894 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0, 0x40006896 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0, 0x40006898 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0, 0x4000689a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0, 0x4000689c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1, 0x400068a0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1, 0x400068a2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1, 0x400068a4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1, 0x400068a6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1, 0x400068a8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1, 0x400068aa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1, 0x400068ac +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1, 0x400068ae +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1, 0x400068b0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1, 0x400068b2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1, 0x400068b4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1, 0x400068b6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1, 0x400068b8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1, 0x400068ba +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1, 0x400068bc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST, 0x400068c0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST, 0x400068c2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST, 0x400068c4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST, 0x400068c6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST, 0x400068c8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST, 0x400068ca +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST, 0x400068cc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST, 0x400068ce +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST, 0x400068d0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST, 0x400068d2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST, 0x400068d4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST, 0x400068d6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST, 0x400068d8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST, 0x400068da +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST, 0x400068dc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL, 0x400068e0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL, 0x400068e2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL, 0x400068e4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL, 0x400068e6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL, 0x400068e8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL, 0x400068ea +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL, 0x400068ec +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL, 0x400068ee +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL, 0x400068f0 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL, 0x400068f2 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL, 0x400068f4 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL, 0x400068f6 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL, 0x400068f8 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL, 0x400068fa +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL, 0x400068fc +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK, 0x40006900 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK, 0x40006902 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK, 0x40006904 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK, 0x40006906 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK, 0x40006908 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK, 0x4000690a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK, 0x4000690c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK, 0x4000690e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK, 0x40006910 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK, 0x40006912 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK, 0x40006914 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK, 0x40006916 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK, 0x40006918 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK, 0x4000691a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK, 0x4000691c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL, 0x40006920 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL, 0x40006922 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL, 0x40006924 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL, 0x40006926 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL, 0x40006928 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL, 0x4000692a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL, 0x4000692c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL, 0x4000692e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL, 0x40006930 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL, 0x40006932 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL, 0x40006934 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL, 0x40006936 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL, 0x40006938 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL, 0x4000693a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL, 0x4000693c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC, 0x40006940 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC, 0x40006942 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC, 0x40006944 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC, 0x40006946 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC, 0x40006948 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC, 0x4000694a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC, 0x4000694c +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC, 0x4000694e +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC, 0x40006950 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC, 0x40006952 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC, 0x40006954 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC, 0x40006956 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC, 0x40006958 +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC, 0x4000695a +.set CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0, 0x40006a08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0, 0x40006a0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0, 0x40006a0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0, 0x40006a0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0, 0x40006a10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0, 0x40006a12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0, 0x40006a14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0, 0x40006a16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1, 0x40006a28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1, 0x40006a2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1, 0x40006a2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1, 0x40006a2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1, 0x40006a30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1, 0x40006a32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1, 0x40006a34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1, 0x40006a36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0, 0x40006a48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0, 0x40006a4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0, 0x40006a4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0, 0x40006a4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0, 0x40006a50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0, 0x40006a52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0, 0x40006a54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0, 0x40006a56 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1, 0x40006a68 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1, 0x40006a6a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1, 0x40006a6c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1, 0x40006a6e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1, 0x40006a70 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1, 0x40006a72 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1, 0x40006a74 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1, 0x40006a76 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0, 0x40006a88 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0, 0x40006a8a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0, 0x40006a8c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0, 0x40006a8e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0, 0x40006a90 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0, 0x40006a92 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0, 0x40006a94 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0, 0x40006a96 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1, 0x40006aa8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1, 0x40006aaa +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1, 0x40006aac +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1, 0x40006aae +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1, 0x40006ab0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1, 0x40006ab2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1, 0x40006ab4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1, 0x40006ab6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST, 0x40006ac8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST, 0x40006aca +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST, 0x40006acc +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST, 0x40006ace +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST, 0x40006ad0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST, 0x40006ad2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST, 0x40006ad4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST, 0x40006ad6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL, 0x40006ae8 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL, 0x40006aea +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL, 0x40006aec +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL, 0x40006aee +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL, 0x40006af0 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL, 0x40006af2 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL, 0x40006af4 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL, 0x40006af6 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK, 0x40006b08 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK, 0x40006b0a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK, 0x40006b0c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK, 0x40006b0e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK, 0x40006b10 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK, 0x40006b12 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK, 0x40006b14 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK, 0x40006b16 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL, 0x40006b28 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL, 0x40006b2a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL, 0x40006b2c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL, 0x40006b2e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL, 0x40006b30 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL, 0x40006b32 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL, 0x40006b34 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL, 0x40006b36 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC, 0x40006b48 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC, 0x40006b4a +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC, 0x40006b4c +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC, 0x40006b4e +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC, 0x40006b50 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC, 0x40006b52 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC, 0x40006b54 +.set CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYDEV_PHUB_CFG, 0x40007000 +.set CYDEV_PHUB_ERR, 0x40007004 +.set CYDEV_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYDEV_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYDEV_PHUB_CH0_ACTION, 0x40007014 +.set CYDEV_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYDEV_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYDEV_PHUB_CH1_ACTION, 0x40007024 +.set CYDEV_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYDEV_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYDEV_PHUB_CH2_ACTION, 0x40007034 +.set CYDEV_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYDEV_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYDEV_PHUB_CH3_ACTION, 0x40007044 +.set CYDEV_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYDEV_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYDEV_PHUB_CH4_ACTION, 0x40007054 +.set CYDEV_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYDEV_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYDEV_PHUB_CH5_ACTION, 0x40007064 +.set CYDEV_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYDEV_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYDEV_PHUB_CH6_ACTION, 0x40007074 +.set CYDEV_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYDEV_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYDEV_PHUB_CH7_ACTION, 0x40007084 +.set CYDEV_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYDEV_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYDEV_PHUB_CH8_ACTION, 0x40007094 +.set CYDEV_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYDEV_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYDEV_PHUB_CH9_ACTION, 0x400070a4 +.set CYDEV_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYDEV_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYDEV_PHUB_CH10_ACTION, 0x400070b4 +.set CYDEV_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYDEV_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYDEV_PHUB_CH11_ACTION, 0x400070c4 +.set CYDEV_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYDEV_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYDEV_PHUB_CH12_ACTION, 0x400070d4 +.set CYDEV_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYDEV_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYDEV_PHUB_CH13_ACTION, 0x400070e4 +.set CYDEV_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYDEV_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYDEV_PHUB_CH14_ACTION, 0x400070f4 +.set CYDEV_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYDEV_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYDEV_PHUB_CH15_ACTION, 0x40007104 +.set CYDEV_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYDEV_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYDEV_PHUB_CH16_ACTION, 0x40007114 +.set CYDEV_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYDEV_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYDEV_PHUB_CH17_ACTION, 0x40007124 +.set CYDEV_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYDEV_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYDEV_PHUB_CH18_ACTION, 0x40007134 +.set CYDEV_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYDEV_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYDEV_PHUB_CH19_ACTION, 0x40007144 +.set CYDEV_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYDEV_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYDEV_PHUB_CH20_ACTION, 0x40007154 +.set CYDEV_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYDEV_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYDEV_PHUB_CH21_ACTION, 0x40007164 +.set CYDEV_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYDEV_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYDEV_PHUB_CH22_ACTION, 0x40007174 +.set CYDEV_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYDEV_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYDEV_PHUB_CH23_ACTION, 0x40007184 +.set CYDEV_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYDEV_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYDEV_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYDEV_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYDEV_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYDEV_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYDEV_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYDEV_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYDEV_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYDEV_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYDEV_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYDEV_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYDEV_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYDEV_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYDEV_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYDEV_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYDEV_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYDEV_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYDEV_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYDEV_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYDEV_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYDEV_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYDEV_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYDEV_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYDEV_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYDEV_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYDEV_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYDEV_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYDEV_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYDEV_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYDEV_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYDEV_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYDEV_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYDEV_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYDEV_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYDEV_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYDEV_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYDEV_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYDEV_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYDEV_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYDEV_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYDEV_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYDEV_EE_DATA_MBASE, 0x40008000 +.set CYDEV_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYDEV_CAN0_CSR_INT_SR, 0x4000a000 +.set CYDEV_CAN0_CSR_INT_EN, 0x4000a004 +.set CYDEV_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYDEV_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYDEV_CAN0_CSR_CMD, 0x4000a010 +.set CYDEV_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYDEV_CAN0_TX0_CMD, 0x4000a020 +.set CYDEV_CAN0_TX0_ID, 0x4000a024 +.set CYDEV_CAN0_TX0_DH, 0x4000a028 +.set CYDEV_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYDEV_CAN0_TX1_CMD, 0x4000a030 +.set CYDEV_CAN0_TX1_ID, 0x4000a034 +.set CYDEV_CAN0_TX1_DH, 0x4000a038 +.set CYDEV_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYDEV_CAN0_TX2_CMD, 0x4000a040 +.set CYDEV_CAN0_TX2_ID, 0x4000a044 +.set CYDEV_CAN0_TX2_DH, 0x4000a048 +.set CYDEV_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYDEV_CAN0_TX3_CMD, 0x4000a050 +.set CYDEV_CAN0_TX3_ID, 0x4000a054 +.set CYDEV_CAN0_TX3_DH, 0x4000a058 +.set CYDEV_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYDEV_CAN0_TX4_CMD, 0x4000a060 +.set CYDEV_CAN0_TX4_ID, 0x4000a064 +.set CYDEV_CAN0_TX4_DH, 0x4000a068 +.set CYDEV_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYDEV_CAN0_TX5_CMD, 0x4000a070 +.set CYDEV_CAN0_TX5_ID, 0x4000a074 +.set CYDEV_CAN0_TX5_DH, 0x4000a078 +.set CYDEV_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYDEV_CAN0_TX6_CMD, 0x4000a080 +.set CYDEV_CAN0_TX6_ID, 0x4000a084 +.set CYDEV_CAN0_TX6_DH, 0x4000a088 +.set CYDEV_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYDEV_CAN0_TX7_CMD, 0x4000a090 +.set CYDEV_CAN0_TX7_ID, 0x4000a094 +.set CYDEV_CAN0_TX7_DH, 0x4000a098 +.set CYDEV_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYDEV_CAN0_RX0_CMD, 0x4000a0a0 +.set CYDEV_CAN0_RX0_ID, 0x4000a0a4 +.set CYDEV_CAN0_RX0_DH, 0x4000a0a8 +.set CYDEV_CAN0_RX0_DL, 0x4000a0ac +.set CYDEV_CAN0_RX0_AMR, 0x4000a0b0 +.set CYDEV_CAN0_RX0_ACR, 0x4000a0b4 +.set CYDEV_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYDEV_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYDEV_CAN0_RX1_CMD, 0x4000a0c0 +.set CYDEV_CAN0_RX1_ID, 0x4000a0c4 +.set CYDEV_CAN0_RX1_DH, 0x4000a0c8 +.set CYDEV_CAN0_RX1_DL, 0x4000a0cc +.set CYDEV_CAN0_RX1_AMR, 0x4000a0d0 +.set CYDEV_CAN0_RX1_ACR, 0x4000a0d4 +.set CYDEV_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYDEV_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYDEV_CAN0_RX2_CMD, 0x4000a0e0 +.set CYDEV_CAN0_RX2_ID, 0x4000a0e4 +.set CYDEV_CAN0_RX2_DH, 0x4000a0e8 +.set CYDEV_CAN0_RX2_DL, 0x4000a0ec +.set CYDEV_CAN0_RX2_AMR, 0x4000a0f0 +.set CYDEV_CAN0_RX2_ACR, 0x4000a0f4 +.set CYDEV_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYDEV_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYDEV_CAN0_RX3_CMD, 0x4000a100 +.set CYDEV_CAN0_RX3_ID, 0x4000a104 +.set CYDEV_CAN0_RX3_DH, 0x4000a108 +.set CYDEV_CAN0_RX3_DL, 0x4000a10c +.set CYDEV_CAN0_RX3_AMR, 0x4000a110 +.set CYDEV_CAN0_RX3_ACR, 0x4000a114 +.set CYDEV_CAN0_RX3_AMRD, 0x4000a118 +.set CYDEV_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYDEV_CAN0_RX4_CMD, 0x4000a120 +.set CYDEV_CAN0_RX4_ID, 0x4000a124 +.set CYDEV_CAN0_RX4_DH, 0x4000a128 +.set CYDEV_CAN0_RX4_DL, 0x4000a12c +.set CYDEV_CAN0_RX4_AMR, 0x4000a130 +.set CYDEV_CAN0_RX4_ACR, 0x4000a134 +.set CYDEV_CAN0_RX4_AMRD, 0x4000a138 +.set CYDEV_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYDEV_CAN0_RX5_CMD, 0x4000a140 +.set CYDEV_CAN0_RX5_ID, 0x4000a144 +.set CYDEV_CAN0_RX5_DH, 0x4000a148 +.set CYDEV_CAN0_RX5_DL, 0x4000a14c +.set CYDEV_CAN0_RX5_AMR, 0x4000a150 +.set CYDEV_CAN0_RX5_ACR, 0x4000a154 +.set CYDEV_CAN0_RX5_AMRD, 0x4000a158 +.set CYDEV_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYDEV_CAN0_RX6_CMD, 0x4000a160 +.set CYDEV_CAN0_RX6_ID, 0x4000a164 +.set CYDEV_CAN0_RX6_DH, 0x4000a168 +.set CYDEV_CAN0_RX6_DL, 0x4000a16c +.set CYDEV_CAN0_RX6_AMR, 0x4000a170 +.set CYDEV_CAN0_RX6_ACR, 0x4000a174 +.set CYDEV_CAN0_RX6_AMRD, 0x4000a178 +.set CYDEV_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYDEV_CAN0_RX7_CMD, 0x4000a180 +.set CYDEV_CAN0_RX7_ID, 0x4000a184 +.set CYDEV_CAN0_RX7_DH, 0x4000a188 +.set CYDEV_CAN0_RX7_DL, 0x4000a18c +.set CYDEV_CAN0_RX7_AMR, 0x4000a190 +.set CYDEV_CAN0_RX7_ACR, 0x4000a194 +.set CYDEV_CAN0_RX7_AMRD, 0x4000a198 +.set CYDEV_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYDEV_CAN0_RX8_CMD, 0x4000a1a0 +.set CYDEV_CAN0_RX8_ID, 0x4000a1a4 +.set CYDEV_CAN0_RX8_DH, 0x4000a1a8 +.set CYDEV_CAN0_RX8_DL, 0x4000a1ac +.set CYDEV_CAN0_RX8_AMR, 0x4000a1b0 +.set CYDEV_CAN0_RX8_ACR, 0x4000a1b4 +.set CYDEV_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYDEV_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYDEV_CAN0_RX9_CMD, 0x4000a1c0 +.set CYDEV_CAN0_RX9_ID, 0x4000a1c4 +.set CYDEV_CAN0_RX9_DH, 0x4000a1c8 +.set CYDEV_CAN0_RX9_DL, 0x4000a1cc +.set CYDEV_CAN0_RX9_AMR, 0x4000a1d0 +.set CYDEV_CAN0_RX9_ACR, 0x4000a1d4 +.set CYDEV_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYDEV_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYDEV_CAN0_RX10_CMD, 0x4000a1e0 +.set CYDEV_CAN0_RX10_ID, 0x4000a1e4 +.set CYDEV_CAN0_RX10_DH, 0x4000a1e8 +.set CYDEV_CAN0_RX10_DL, 0x4000a1ec +.set CYDEV_CAN0_RX10_AMR, 0x4000a1f0 +.set CYDEV_CAN0_RX10_ACR, 0x4000a1f4 +.set CYDEV_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYDEV_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYDEV_CAN0_RX11_CMD, 0x4000a200 +.set CYDEV_CAN0_RX11_ID, 0x4000a204 +.set CYDEV_CAN0_RX11_DH, 0x4000a208 +.set CYDEV_CAN0_RX11_DL, 0x4000a20c +.set CYDEV_CAN0_RX11_AMR, 0x4000a210 +.set CYDEV_CAN0_RX11_ACR, 0x4000a214 +.set CYDEV_CAN0_RX11_AMRD, 0x4000a218 +.set CYDEV_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYDEV_CAN0_RX12_CMD, 0x4000a220 +.set CYDEV_CAN0_RX12_ID, 0x4000a224 +.set CYDEV_CAN0_RX12_DH, 0x4000a228 +.set CYDEV_CAN0_RX12_DL, 0x4000a22c +.set CYDEV_CAN0_RX12_AMR, 0x4000a230 +.set CYDEV_CAN0_RX12_ACR, 0x4000a234 +.set CYDEV_CAN0_RX12_AMRD, 0x4000a238 +.set CYDEV_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYDEV_CAN0_RX13_CMD, 0x4000a240 +.set CYDEV_CAN0_RX13_ID, 0x4000a244 +.set CYDEV_CAN0_RX13_DH, 0x4000a248 +.set CYDEV_CAN0_RX13_DL, 0x4000a24c +.set CYDEV_CAN0_RX13_AMR, 0x4000a250 +.set CYDEV_CAN0_RX13_ACR, 0x4000a254 +.set CYDEV_CAN0_RX13_AMRD, 0x4000a258 +.set CYDEV_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYDEV_CAN0_RX14_CMD, 0x4000a260 +.set CYDEV_CAN0_RX14_ID, 0x4000a264 +.set CYDEV_CAN0_RX14_DH, 0x4000a268 +.set CYDEV_CAN0_RX14_DL, 0x4000a26c +.set CYDEV_CAN0_RX14_AMR, 0x4000a270 +.set CYDEV_CAN0_RX14_ACR, 0x4000a274 +.set CYDEV_CAN0_RX14_AMRD, 0x4000a278 +.set CYDEV_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYDEV_CAN0_RX15_CMD, 0x4000a280 +.set CYDEV_CAN0_RX15_ID, 0x4000a284 +.set CYDEV_CAN0_RX15_DH, 0x4000a288 +.set CYDEV_CAN0_RX15_DL, 0x4000a28c +.set CYDEV_CAN0_RX15_AMR, 0x4000a290 +.set CYDEV_CAN0_RX15_ACR, 0x4000a294 +.set CYDEV_CAN0_RX15_AMRD, 0x4000a298 +.set CYDEV_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYDEV_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYDEV_DFB0_CR, 0x4000c780 +.set CYDEV_DFB0_SR, 0x4000c784 +.set CYDEV_DFB0_RAM_EN, 0x4000c788 +.set CYDEV_DFB0_RAM_DIR, 0x4000c78c +.set CYDEV_DFB0_SEMA, 0x4000c790 +.set CYDEV_DFB0_DSI_CTRL, 0x4000c794 +.set CYDEV_DFB0_INT_CTRL, 0x4000c798 +.set CYDEV_DFB0_DMA_CTRL, 0x4000c79c +.set CYDEV_DFB0_STAGEA, 0x4000c7a0 +.set CYDEV_DFB0_STAGEAM, 0x4000c7a1 +.set CYDEV_DFB0_STAGEAH, 0x4000c7a2 +.set CYDEV_DFB0_STAGEB, 0x4000c7a4 +.set CYDEV_DFB0_STAGEBM, 0x4000c7a5 +.set CYDEV_DFB0_STAGEBH, 0x4000c7a6 +.set CYDEV_DFB0_HOLDA, 0x4000c7a8 +.set CYDEV_DFB0_HOLDAM, 0x4000c7a9 +.set CYDEV_DFB0_HOLDAH, 0x4000c7aa +.set CYDEV_DFB0_HOLDAS, 0x4000c7ab +.set CYDEV_DFB0_HOLDB, 0x4000c7ac +.set CYDEV_DFB0_HOLDBM, 0x4000c7ad +.set CYDEV_DFB0_HOLDBH, 0x4000c7ae +.set CYDEV_DFB0_HOLDBS, 0x4000c7af +.set CYDEV_DFB0_COHER, 0x4000c7b0 +.set CYDEV_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYDEV_UCFG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYDEV_UCFG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYDEV_UCFG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYDEV_UCFG_B0_P0_U0_CFG0, 0x40010040 +.set CYDEV_UCFG_B0_P0_U0_CFG1, 0x40010041 +.set CYDEV_UCFG_B0_P0_U0_CFG2, 0x40010042 +.set CYDEV_UCFG_B0_P0_U0_CFG3, 0x40010043 +.set CYDEV_UCFG_B0_P0_U0_CFG4, 0x40010044 +.set CYDEV_UCFG_B0_P0_U0_CFG5, 0x40010045 +.set CYDEV_UCFG_B0_P0_U0_CFG6, 0x40010046 +.set CYDEV_UCFG_B0_P0_U0_CFG7, 0x40010047 +.set CYDEV_UCFG_B0_P0_U0_CFG8, 0x40010048 +.set CYDEV_UCFG_B0_P0_U0_CFG9, 0x40010049 +.set CYDEV_UCFG_B0_P0_U0_CFG10, 0x4001004a +.set CYDEV_UCFG_B0_P0_U0_CFG11, 0x4001004b +.set CYDEV_UCFG_B0_P0_U0_CFG12, 0x4001004c +.set CYDEV_UCFG_B0_P0_U0_CFG13, 0x4001004d +.set CYDEV_UCFG_B0_P0_U0_CFG14, 0x4001004e +.set CYDEV_UCFG_B0_P0_U0_CFG15, 0x4001004f +.set CYDEV_UCFG_B0_P0_U0_CFG16, 0x40010050 +.set CYDEV_UCFG_B0_P0_U0_CFG17, 0x40010051 +.set CYDEV_UCFG_B0_P0_U0_CFG18, 0x40010052 +.set CYDEV_UCFG_B0_P0_U0_CFG19, 0x40010053 +.set CYDEV_UCFG_B0_P0_U0_CFG20, 0x40010054 +.set CYDEV_UCFG_B0_P0_U0_CFG21, 0x40010055 +.set CYDEV_UCFG_B0_P0_U0_CFG22, 0x40010056 +.set CYDEV_UCFG_B0_P0_U0_CFG23, 0x40010057 +.set CYDEV_UCFG_B0_P0_U0_CFG24, 0x40010058 +.set CYDEV_UCFG_B0_P0_U0_CFG25, 0x40010059 +.set CYDEV_UCFG_B0_P0_U0_CFG26, 0x4001005a +.set CYDEV_UCFG_B0_P0_U0_CFG27, 0x4001005b +.set CYDEV_UCFG_B0_P0_U0_CFG28, 0x4001005c +.set CYDEV_UCFG_B0_P0_U0_CFG29, 0x4001005d +.set CYDEV_UCFG_B0_P0_U0_CFG30, 0x4001005e +.set CYDEV_UCFG_B0_P0_U0_CFG31, 0x4001005f +.set CYDEV_UCFG_B0_P0_U0_DCFG0, 0x40010060 +.set CYDEV_UCFG_B0_P0_U0_DCFG1, 0x40010062 +.set CYDEV_UCFG_B0_P0_U0_DCFG2, 0x40010064 +.set CYDEV_UCFG_B0_P0_U0_DCFG3, 0x40010066 +.set CYDEV_UCFG_B0_P0_U0_DCFG4, 0x40010068 +.set CYDEV_UCFG_B0_P0_U0_DCFG5, 0x4001006a +.set CYDEV_UCFG_B0_P0_U0_DCFG6, 0x4001006c +.set CYDEV_UCFG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYDEV_UCFG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYDEV_UCFG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYDEV_UCFG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYDEV_UCFG_B0_P0_U1_CFG0, 0x400100c0 +.set CYDEV_UCFG_B0_P0_U1_CFG1, 0x400100c1 +.set CYDEV_UCFG_B0_P0_U1_CFG2, 0x400100c2 +.set CYDEV_UCFG_B0_P0_U1_CFG3, 0x400100c3 +.set CYDEV_UCFG_B0_P0_U1_CFG4, 0x400100c4 +.set CYDEV_UCFG_B0_P0_U1_CFG5, 0x400100c5 +.set CYDEV_UCFG_B0_P0_U1_CFG6, 0x400100c6 +.set CYDEV_UCFG_B0_P0_U1_CFG7, 0x400100c7 +.set CYDEV_UCFG_B0_P0_U1_CFG8, 0x400100c8 +.set CYDEV_UCFG_B0_P0_U1_CFG9, 0x400100c9 +.set CYDEV_UCFG_B0_P0_U1_CFG10, 0x400100ca +.set CYDEV_UCFG_B0_P0_U1_CFG11, 0x400100cb +.set CYDEV_UCFG_B0_P0_U1_CFG12, 0x400100cc +.set CYDEV_UCFG_B0_P0_U1_CFG13, 0x400100cd +.set CYDEV_UCFG_B0_P0_U1_CFG14, 0x400100ce +.set CYDEV_UCFG_B0_P0_U1_CFG15, 0x400100cf +.set CYDEV_UCFG_B0_P0_U1_CFG16, 0x400100d0 +.set CYDEV_UCFG_B0_P0_U1_CFG17, 0x400100d1 +.set CYDEV_UCFG_B0_P0_U1_CFG18, 0x400100d2 +.set CYDEV_UCFG_B0_P0_U1_CFG19, 0x400100d3 +.set CYDEV_UCFG_B0_P0_U1_CFG20, 0x400100d4 +.set CYDEV_UCFG_B0_P0_U1_CFG21, 0x400100d5 +.set CYDEV_UCFG_B0_P0_U1_CFG22, 0x400100d6 +.set CYDEV_UCFG_B0_P0_U1_CFG23, 0x400100d7 +.set CYDEV_UCFG_B0_P0_U1_CFG24, 0x400100d8 +.set CYDEV_UCFG_B0_P0_U1_CFG25, 0x400100d9 +.set CYDEV_UCFG_B0_P0_U1_CFG26, 0x400100da +.set CYDEV_UCFG_B0_P0_U1_CFG27, 0x400100db +.set CYDEV_UCFG_B0_P0_U1_CFG28, 0x400100dc +.set CYDEV_UCFG_B0_P0_U1_CFG29, 0x400100dd +.set CYDEV_UCFG_B0_P0_U1_CFG30, 0x400100de +.set CYDEV_UCFG_B0_P0_U1_CFG31, 0x400100df +.set CYDEV_UCFG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYDEV_UCFG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYDEV_UCFG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYDEV_UCFG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYDEV_UCFG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYDEV_UCFG_B0_P0_U1_DCFG5, 0x400100ea +.set CYDEV_UCFG_B0_P0_U1_DCFG6, 0x400100ec +.set CYDEV_UCFG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYDEV_UCFG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYDEV_UCFG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYDEV_UCFG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYDEV_UCFG_B0_P1_U0_CFG0, 0x40010240 +.set CYDEV_UCFG_B0_P1_U0_CFG1, 0x40010241 +.set CYDEV_UCFG_B0_P1_U0_CFG2, 0x40010242 +.set CYDEV_UCFG_B0_P1_U0_CFG3, 0x40010243 +.set CYDEV_UCFG_B0_P1_U0_CFG4, 0x40010244 +.set CYDEV_UCFG_B0_P1_U0_CFG5, 0x40010245 +.set CYDEV_UCFG_B0_P1_U0_CFG6, 0x40010246 +.set CYDEV_UCFG_B0_P1_U0_CFG7, 0x40010247 +.set CYDEV_UCFG_B0_P1_U0_CFG8, 0x40010248 +.set CYDEV_UCFG_B0_P1_U0_CFG9, 0x40010249 +.set CYDEV_UCFG_B0_P1_U0_CFG10, 0x4001024a +.set CYDEV_UCFG_B0_P1_U0_CFG11, 0x4001024b +.set CYDEV_UCFG_B0_P1_U0_CFG12, 0x4001024c +.set CYDEV_UCFG_B0_P1_U0_CFG13, 0x4001024d +.set CYDEV_UCFG_B0_P1_U0_CFG14, 0x4001024e +.set CYDEV_UCFG_B0_P1_U0_CFG15, 0x4001024f +.set CYDEV_UCFG_B0_P1_U0_CFG16, 0x40010250 +.set CYDEV_UCFG_B0_P1_U0_CFG17, 0x40010251 +.set CYDEV_UCFG_B0_P1_U0_CFG18, 0x40010252 +.set CYDEV_UCFG_B0_P1_U0_CFG19, 0x40010253 +.set CYDEV_UCFG_B0_P1_U0_CFG20, 0x40010254 +.set CYDEV_UCFG_B0_P1_U0_CFG21, 0x40010255 +.set CYDEV_UCFG_B0_P1_U0_CFG22, 0x40010256 +.set CYDEV_UCFG_B0_P1_U0_CFG23, 0x40010257 +.set CYDEV_UCFG_B0_P1_U0_CFG24, 0x40010258 +.set CYDEV_UCFG_B0_P1_U0_CFG25, 0x40010259 +.set CYDEV_UCFG_B0_P1_U0_CFG26, 0x4001025a +.set CYDEV_UCFG_B0_P1_U0_CFG27, 0x4001025b +.set CYDEV_UCFG_B0_P1_U0_CFG28, 0x4001025c +.set CYDEV_UCFG_B0_P1_U0_CFG29, 0x4001025d +.set CYDEV_UCFG_B0_P1_U0_CFG30, 0x4001025e +.set CYDEV_UCFG_B0_P1_U0_CFG31, 0x4001025f +.set CYDEV_UCFG_B0_P1_U0_DCFG0, 0x40010260 +.set CYDEV_UCFG_B0_P1_U0_DCFG1, 0x40010262 +.set CYDEV_UCFG_B0_P1_U0_DCFG2, 0x40010264 +.set CYDEV_UCFG_B0_P1_U0_DCFG3, 0x40010266 +.set CYDEV_UCFG_B0_P1_U0_DCFG4, 0x40010268 +.set CYDEV_UCFG_B0_P1_U0_DCFG5, 0x4001026a +.set CYDEV_UCFG_B0_P1_U0_DCFG6, 0x4001026c +.set CYDEV_UCFG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYDEV_UCFG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYDEV_UCFG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYDEV_UCFG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYDEV_UCFG_B0_P1_U1_CFG0, 0x400102c0 +.set CYDEV_UCFG_B0_P1_U1_CFG1, 0x400102c1 +.set CYDEV_UCFG_B0_P1_U1_CFG2, 0x400102c2 +.set CYDEV_UCFG_B0_P1_U1_CFG3, 0x400102c3 +.set CYDEV_UCFG_B0_P1_U1_CFG4, 0x400102c4 +.set CYDEV_UCFG_B0_P1_U1_CFG5, 0x400102c5 +.set CYDEV_UCFG_B0_P1_U1_CFG6, 0x400102c6 +.set CYDEV_UCFG_B0_P1_U1_CFG7, 0x400102c7 +.set CYDEV_UCFG_B0_P1_U1_CFG8, 0x400102c8 +.set CYDEV_UCFG_B0_P1_U1_CFG9, 0x400102c9 +.set CYDEV_UCFG_B0_P1_U1_CFG10, 0x400102ca +.set CYDEV_UCFG_B0_P1_U1_CFG11, 0x400102cb +.set CYDEV_UCFG_B0_P1_U1_CFG12, 0x400102cc +.set CYDEV_UCFG_B0_P1_U1_CFG13, 0x400102cd +.set CYDEV_UCFG_B0_P1_U1_CFG14, 0x400102ce +.set CYDEV_UCFG_B0_P1_U1_CFG15, 0x400102cf +.set CYDEV_UCFG_B0_P1_U1_CFG16, 0x400102d0 +.set CYDEV_UCFG_B0_P1_U1_CFG17, 0x400102d1 +.set CYDEV_UCFG_B0_P1_U1_CFG18, 0x400102d2 +.set CYDEV_UCFG_B0_P1_U1_CFG19, 0x400102d3 +.set CYDEV_UCFG_B0_P1_U1_CFG20, 0x400102d4 +.set CYDEV_UCFG_B0_P1_U1_CFG21, 0x400102d5 +.set CYDEV_UCFG_B0_P1_U1_CFG22, 0x400102d6 +.set CYDEV_UCFG_B0_P1_U1_CFG23, 0x400102d7 +.set CYDEV_UCFG_B0_P1_U1_CFG24, 0x400102d8 +.set CYDEV_UCFG_B0_P1_U1_CFG25, 0x400102d9 +.set CYDEV_UCFG_B0_P1_U1_CFG26, 0x400102da +.set CYDEV_UCFG_B0_P1_U1_CFG27, 0x400102db +.set CYDEV_UCFG_B0_P1_U1_CFG28, 0x400102dc +.set CYDEV_UCFG_B0_P1_U1_CFG29, 0x400102dd +.set CYDEV_UCFG_B0_P1_U1_CFG30, 0x400102de +.set CYDEV_UCFG_B0_P1_U1_CFG31, 0x400102df +.set CYDEV_UCFG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYDEV_UCFG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYDEV_UCFG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYDEV_UCFG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYDEV_UCFG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYDEV_UCFG_B0_P1_U1_DCFG5, 0x400102ea +.set CYDEV_UCFG_B0_P1_U1_DCFG6, 0x400102ec +.set CYDEV_UCFG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYDEV_UCFG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYDEV_UCFG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYDEV_UCFG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYDEV_UCFG_B0_P2_U0_CFG0, 0x40010440 +.set CYDEV_UCFG_B0_P2_U0_CFG1, 0x40010441 +.set CYDEV_UCFG_B0_P2_U0_CFG2, 0x40010442 +.set CYDEV_UCFG_B0_P2_U0_CFG3, 0x40010443 +.set CYDEV_UCFG_B0_P2_U0_CFG4, 0x40010444 +.set CYDEV_UCFG_B0_P2_U0_CFG5, 0x40010445 +.set CYDEV_UCFG_B0_P2_U0_CFG6, 0x40010446 +.set CYDEV_UCFG_B0_P2_U0_CFG7, 0x40010447 +.set CYDEV_UCFG_B0_P2_U0_CFG8, 0x40010448 +.set CYDEV_UCFG_B0_P2_U0_CFG9, 0x40010449 +.set CYDEV_UCFG_B0_P2_U0_CFG10, 0x4001044a +.set CYDEV_UCFG_B0_P2_U0_CFG11, 0x4001044b +.set CYDEV_UCFG_B0_P2_U0_CFG12, 0x4001044c +.set CYDEV_UCFG_B0_P2_U0_CFG13, 0x4001044d +.set CYDEV_UCFG_B0_P2_U0_CFG14, 0x4001044e +.set CYDEV_UCFG_B0_P2_U0_CFG15, 0x4001044f +.set CYDEV_UCFG_B0_P2_U0_CFG16, 0x40010450 +.set CYDEV_UCFG_B0_P2_U0_CFG17, 0x40010451 +.set CYDEV_UCFG_B0_P2_U0_CFG18, 0x40010452 +.set CYDEV_UCFG_B0_P2_U0_CFG19, 0x40010453 +.set CYDEV_UCFG_B0_P2_U0_CFG20, 0x40010454 +.set CYDEV_UCFG_B0_P2_U0_CFG21, 0x40010455 +.set CYDEV_UCFG_B0_P2_U0_CFG22, 0x40010456 +.set CYDEV_UCFG_B0_P2_U0_CFG23, 0x40010457 +.set CYDEV_UCFG_B0_P2_U0_CFG24, 0x40010458 +.set CYDEV_UCFG_B0_P2_U0_CFG25, 0x40010459 +.set CYDEV_UCFG_B0_P2_U0_CFG26, 0x4001045a +.set CYDEV_UCFG_B0_P2_U0_CFG27, 0x4001045b +.set CYDEV_UCFG_B0_P2_U0_CFG28, 0x4001045c +.set CYDEV_UCFG_B0_P2_U0_CFG29, 0x4001045d +.set CYDEV_UCFG_B0_P2_U0_CFG30, 0x4001045e +.set CYDEV_UCFG_B0_P2_U0_CFG31, 0x4001045f +.set CYDEV_UCFG_B0_P2_U0_DCFG0, 0x40010460 +.set CYDEV_UCFG_B0_P2_U0_DCFG1, 0x40010462 +.set CYDEV_UCFG_B0_P2_U0_DCFG2, 0x40010464 +.set CYDEV_UCFG_B0_P2_U0_DCFG3, 0x40010466 +.set CYDEV_UCFG_B0_P2_U0_DCFG4, 0x40010468 +.set CYDEV_UCFG_B0_P2_U0_DCFG5, 0x4001046a +.set CYDEV_UCFG_B0_P2_U0_DCFG6, 0x4001046c +.set CYDEV_UCFG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYDEV_UCFG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYDEV_UCFG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYDEV_UCFG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYDEV_UCFG_B0_P2_U1_CFG0, 0x400104c0 +.set CYDEV_UCFG_B0_P2_U1_CFG1, 0x400104c1 +.set CYDEV_UCFG_B0_P2_U1_CFG2, 0x400104c2 +.set CYDEV_UCFG_B0_P2_U1_CFG3, 0x400104c3 +.set CYDEV_UCFG_B0_P2_U1_CFG4, 0x400104c4 +.set CYDEV_UCFG_B0_P2_U1_CFG5, 0x400104c5 +.set CYDEV_UCFG_B0_P2_U1_CFG6, 0x400104c6 +.set CYDEV_UCFG_B0_P2_U1_CFG7, 0x400104c7 +.set CYDEV_UCFG_B0_P2_U1_CFG8, 0x400104c8 +.set CYDEV_UCFG_B0_P2_U1_CFG9, 0x400104c9 +.set CYDEV_UCFG_B0_P2_U1_CFG10, 0x400104ca +.set CYDEV_UCFG_B0_P2_U1_CFG11, 0x400104cb +.set CYDEV_UCFG_B0_P2_U1_CFG12, 0x400104cc +.set CYDEV_UCFG_B0_P2_U1_CFG13, 0x400104cd +.set CYDEV_UCFG_B0_P2_U1_CFG14, 0x400104ce +.set CYDEV_UCFG_B0_P2_U1_CFG15, 0x400104cf +.set CYDEV_UCFG_B0_P2_U1_CFG16, 0x400104d0 +.set CYDEV_UCFG_B0_P2_U1_CFG17, 0x400104d1 +.set CYDEV_UCFG_B0_P2_U1_CFG18, 0x400104d2 +.set CYDEV_UCFG_B0_P2_U1_CFG19, 0x400104d3 +.set CYDEV_UCFG_B0_P2_U1_CFG20, 0x400104d4 +.set CYDEV_UCFG_B0_P2_U1_CFG21, 0x400104d5 +.set CYDEV_UCFG_B0_P2_U1_CFG22, 0x400104d6 +.set CYDEV_UCFG_B0_P2_U1_CFG23, 0x400104d7 +.set CYDEV_UCFG_B0_P2_U1_CFG24, 0x400104d8 +.set CYDEV_UCFG_B0_P2_U1_CFG25, 0x400104d9 +.set CYDEV_UCFG_B0_P2_U1_CFG26, 0x400104da +.set CYDEV_UCFG_B0_P2_U1_CFG27, 0x400104db +.set CYDEV_UCFG_B0_P2_U1_CFG28, 0x400104dc +.set CYDEV_UCFG_B0_P2_U1_CFG29, 0x400104dd +.set CYDEV_UCFG_B0_P2_U1_CFG30, 0x400104de +.set CYDEV_UCFG_B0_P2_U1_CFG31, 0x400104df +.set CYDEV_UCFG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYDEV_UCFG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYDEV_UCFG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYDEV_UCFG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYDEV_UCFG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYDEV_UCFG_B0_P2_U1_DCFG5, 0x400104ea +.set CYDEV_UCFG_B0_P2_U1_DCFG6, 0x400104ec +.set CYDEV_UCFG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYDEV_UCFG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYDEV_UCFG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYDEV_UCFG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYDEV_UCFG_B0_P3_U0_CFG0, 0x40010640 +.set CYDEV_UCFG_B0_P3_U0_CFG1, 0x40010641 +.set CYDEV_UCFG_B0_P3_U0_CFG2, 0x40010642 +.set CYDEV_UCFG_B0_P3_U0_CFG3, 0x40010643 +.set CYDEV_UCFG_B0_P3_U0_CFG4, 0x40010644 +.set CYDEV_UCFG_B0_P3_U0_CFG5, 0x40010645 +.set CYDEV_UCFG_B0_P3_U0_CFG6, 0x40010646 +.set CYDEV_UCFG_B0_P3_U0_CFG7, 0x40010647 +.set CYDEV_UCFG_B0_P3_U0_CFG8, 0x40010648 +.set CYDEV_UCFG_B0_P3_U0_CFG9, 0x40010649 +.set CYDEV_UCFG_B0_P3_U0_CFG10, 0x4001064a +.set CYDEV_UCFG_B0_P3_U0_CFG11, 0x4001064b +.set CYDEV_UCFG_B0_P3_U0_CFG12, 0x4001064c +.set CYDEV_UCFG_B0_P3_U0_CFG13, 0x4001064d +.set CYDEV_UCFG_B0_P3_U0_CFG14, 0x4001064e +.set CYDEV_UCFG_B0_P3_U0_CFG15, 0x4001064f +.set CYDEV_UCFG_B0_P3_U0_CFG16, 0x40010650 +.set CYDEV_UCFG_B0_P3_U0_CFG17, 0x40010651 +.set CYDEV_UCFG_B0_P3_U0_CFG18, 0x40010652 +.set CYDEV_UCFG_B0_P3_U0_CFG19, 0x40010653 +.set CYDEV_UCFG_B0_P3_U0_CFG20, 0x40010654 +.set CYDEV_UCFG_B0_P3_U0_CFG21, 0x40010655 +.set CYDEV_UCFG_B0_P3_U0_CFG22, 0x40010656 +.set CYDEV_UCFG_B0_P3_U0_CFG23, 0x40010657 +.set CYDEV_UCFG_B0_P3_U0_CFG24, 0x40010658 +.set CYDEV_UCFG_B0_P3_U0_CFG25, 0x40010659 +.set CYDEV_UCFG_B0_P3_U0_CFG26, 0x4001065a +.set CYDEV_UCFG_B0_P3_U0_CFG27, 0x4001065b +.set CYDEV_UCFG_B0_P3_U0_CFG28, 0x4001065c +.set CYDEV_UCFG_B0_P3_U0_CFG29, 0x4001065d +.set CYDEV_UCFG_B0_P3_U0_CFG30, 0x4001065e +.set CYDEV_UCFG_B0_P3_U0_CFG31, 0x4001065f +.set CYDEV_UCFG_B0_P3_U0_DCFG0, 0x40010660 +.set CYDEV_UCFG_B0_P3_U0_DCFG1, 0x40010662 +.set CYDEV_UCFG_B0_P3_U0_DCFG2, 0x40010664 +.set CYDEV_UCFG_B0_P3_U0_DCFG3, 0x40010666 +.set CYDEV_UCFG_B0_P3_U0_DCFG4, 0x40010668 +.set CYDEV_UCFG_B0_P3_U0_DCFG5, 0x4001066a +.set CYDEV_UCFG_B0_P3_U0_DCFG6, 0x4001066c +.set CYDEV_UCFG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYDEV_UCFG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYDEV_UCFG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYDEV_UCFG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYDEV_UCFG_B0_P3_U1_CFG0, 0x400106c0 +.set CYDEV_UCFG_B0_P3_U1_CFG1, 0x400106c1 +.set CYDEV_UCFG_B0_P3_U1_CFG2, 0x400106c2 +.set CYDEV_UCFG_B0_P3_U1_CFG3, 0x400106c3 +.set CYDEV_UCFG_B0_P3_U1_CFG4, 0x400106c4 +.set CYDEV_UCFG_B0_P3_U1_CFG5, 0x400106c5 +.set CYDEV_UCFG_B0_P3_U1_CFG6, 0x400106c6 +.set CYDEV_UCFG_B0_P3_U1_CFG7, 0x400106c7 +.set CYDEV_UCFG_B0_P3_U1_CFG8, 0x400106c8 +.set CYDEV_UCFG_B0_P3_U1_CFG9, 0x400106c9 +.set CYDEV_UCFG_B0_P3_U1_CFG10, 0x400106ca +.set CYDEV_UCFG_B0_P3_U1_CFG11, 0x400106cb +.set CYDEV_UCFG_B0_P3_U1_CFG12, 0x400106cc +.set CYDEV_UCFG_B0_P3_U1_CFG13, 0x400106cd +.set CYDEV_UCFG_B0_P3_U1_CFG14, 0x400106ce +.set CYDEV_UCFG_B0_P3_U1_CFG15, 0x400106cf +.set CYDEV_UCFG_B0_P3_U1_CFG16, 0x400106d0 +.set CYDEV_UCFG_B0_P3_U1_CFG17, 0x400106d1 +.set CYDEV_UCFG_B0_P3_U1_CFG18, 0x400106d2 +.set CYDEV_UCFG_B0_P3_U1_CFG19, 0x400106d3 +.set CYDEV_UCFG_B0_P3_U1_CFG20, 0x400106d4 +.set CYDEV_UCFG_B0_P3_U1_CFG21, 0x400106d5 +.set CYDEV_UCFG_B0_P3_U1_CFG22, 0x400106d6 +.set CYDEV_UCFG_B0_P3_U1_CFG23, 0x400106d7 +.set CYDEV_UCFG_B0_P3_U1_CFG24, 0x400106d8 +.set CYDEV_UCFG_B0_P3_U1_CFG25, 0x400106d9 +.set CYDEV_UCFG_B0_P3_U1_CFG26, 0x400106da +.set CYDEV_UCFG_B0_P3_U1_CFG27, 0x400106db +.set CYDEV_UCFG_B0_P3_U1_CFG28, 0x400106dc +.set CYDEV_UCFG_B0_P3_U1_CFG29, 0x400106dd +.set CYDEV_UCFG_B0_P3_U1_CFG30, 0x400106de +.set CYDEV_UCFG_B0_P3_U1_CFG31, 0x400106df +.set CYDEV_UCFG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYDEV_UCFG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYDEV_UCFG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYDEV_UCFG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYDEV_UCFG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYDEV_UCFG_B0_P3_U1_DCFG5, 0x400106ea +.set CYDEV_UCFG_B0_P3_U1_DCFG6, 0x400106ec +.set CYDEV_UCFG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYDEV_UCFG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYDEV_UCFG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYDEV_UCFG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYDEV_UCFG_B0_P4_U0_CFG0, 0x40010840 +.set CYDEV_UCFG_B0_P4_U0_CFG1, 0x40010841 +.set CYDEV_UCFG_B0_P4_U0_CFG2, 0x40010842 +.set CYDEV_UCFG_B0_P4_U0_CFG3, 0x40010843 +.set CYDEV_UCFG_B0_P4_U0_CFG4, 0x40010844 +.set CYDEV_UCFG_B0_P4_U0_CFG5, 0x40010845 +.set CYDEV_UCFG_B0_P4_U0_CFG6, 0x40010846 +.set CYDEV_UCFG_B0_P4_U0_CFG7, 0x40010847 +.set CYDEV_UCFG_B0_P4_U0_CFG8, 0x40010848 +.set CYDEV_UCFG_B0_P4_U0_CFG9, 0x40010849 +.set CYDEV_UCFG_B0_P4_U0_CFG10, 0x4001084a +.set CYDEV_UCFG_B0_P4_U0_CFG11, 0x4001084b +.set CYDEV_UCFG_B0_P4_U0_CFG12, 0x4001084c +.set CYDEV_UCFG_B0_P4_U0_CFG13, 0x4001084d +.set CYDEV_UCFG_B0_P4_U0_CFG14, 0x4001084e +.set CYDEV_UCFG_B0_P4_U0_CFG15, 0x4001084f +.set CYDEV_UCFG_B0_P4_U0_CFG16, 0x40010850 +.set CYDEV_UCFG_B0_P4_U0_CFG17, 0x40010851 +.set CYDEV_UCFG_B0_P4_U0_CFG18, 0x40010852 +.set CYDEV_UCFG_B0_P4_U0_CFG19, 0x40010853 +.set CYDEV_UCFG_B0_P4_U0_CFG20, 0x40010854 +.set CYDEV_UCFG_B0_P4_U0_CFG21, 0x40010855 +.set CYDEV_UCFG_B0_P4_U0_CFG22, 0x40010856 +.set CYDEV_UCFG_B0_P4_U0_CFG23, 0x40010857 +.set CYDEV_UCFG_B0_P4_U0_CFG24, 0x40010858 +.set CYDEV_UCFG_B0_P4_U0_CFG25, 0x40010859 +.set CYDEV_UCFG_B0_P4_U0_CFG26, 0x4001085a +.set CYDEV_UCFG_B0_P4_U0_CFG27, 0x4001085b +.set CYDEV_UCFG_B0_P4_U0_CFG28, 0x4001085c +.set CYDEV_UCFG_B0_P4_U0_CFG29, 0x4001085d +.set CYDEV_UCFG_B0_P4_U0_CFG30, 0x4001085e +.set CYDEV_UCFG_B0_P4_U0_CFG31, 0x4001085f +.set CYDEV_UCFG_B0_P4_U0_DCFG0, 0x40010860 +.set CYDEV_UCFG_B0_P4_U0_DCFG1, 0x40010862 +.set CYDEV_UCFG_B0_P4_U0_DCFG2, 0x40010864 +.set CYDEV_UCFG_B0_P4_U0_DCFG3, 0x40010866 +.set CYDEV_UCFG_B0_P4_U0_DCFG4, 0x40010868 +.set CYDEV_UCFG_B0_P4_U0_DCFG5, 0x4001086a +.set CYDEV_UCFG_B0_P4_U0_DCFG6, 0x4001086c +.set CYDEV_UCFG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYDEV_UCFG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYDEV_UCFG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYDEV_UCFG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYDEV_UCFG_B0_P4_U1_CFG0, 0x400108c0 +.set CYDEV_UCFG_B0_P4_U1_CFG1, 0x400108c1 +.set CYDEV_UCFG_B0_P4_U1_CFG2, 0x400108c2 +.set CYDEV_UCFG_B0_P4_U1_CFG3, 0x400108c3 +.set CYDEV_UCFG_B0_P4_U1_CFG4, 0x400108c4 +.set CYDEV_UCFG_B0_P4_U1_CFG5, 0x400108c5 +.set CYDEV_UCFG_B0_P4_U1_CFG6, 0x400108c6 +.set CYDEV_UCFG_B0_P4_U1_CFG7, 0x400108c7 +.set CYDEV_UCFG_B0_P4_U1_CFG8, 0x400108c8 +.set CYDEV_UCFG_B0_P4_U1_CFG9, 0x400108c9 +.set CYDEV_UCFG_B0_P4_U1_CFG10, 0x400108ca +.set CYDEV_UCFG_B0_P4_U1_CFG11, 0x400108cb +.set CYDEV_UCFG_B0_P4_U1_CFG12, 0x400108cc +.set CYDEV_UCFG_B0_P4_U1_CFG13, 0x400108cd +.set CYDEV_UCFG_B0_P4_U1_CFG14, 0x400108ce +.set CYDEV_UCFG_B0_P4_U1_CFG15, 0x400108cf +.set CYDEV_UCFG_B0_P4_U1_CFG16, 0x400108d0 +.set CYDEV_UCFG_B0_P4_U1_CFG17, 0x400108d1 +.set CYDEV_UCFG_B0_P4_U1_CFG18, 0x400108d2 +.set CYDEV_UCFG_B0_P4_U1_CFG19, 0x400108d3 +.set CYDEV_UCFG_B0_P4_U1_CFG20, 0x400108d4 +.set CYDEV_UCFG_B0_P4_U1_CFG21, 0x400108d5 +.set CYDEV_UCFG_B0_P4_U1_CFG22, 0x400108d6 +.set CYDEV_UCFG_B0_P4_U1_CFG23, 0x400108d7 +.set CYDEV_UCFG_B0_P4_U1_CFG24, 0x400108d8 +.set CYDEV_UCFG_B0_P4_U1_CFG25, 0x400108d9 +.set CYDEV_UCFG_B0_P4_U1_CFG26, 0x400108da +.set CYDEV_UCFG_B0_P4_U1_CFG27, 0x400108db +.set CYDEV_UCFG_B0_P4_U1_CFG28, 0x400108dc +.set CYDEV_UCFG_B0_P4_U1_CFG29, 0x400108dd +.set CYDEV_UCFG_B0_P4_U1_CFG30, 0x400108de +.set CYDEV_UCFG_B0_P4_U1_CFG31, 0x400108df +.set CYDEV_UCFG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYDEV_UCFG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYDEV_UCFG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYDEV_UCFG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYDEV_UCFG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYDEV_UCFG_B0_P4_U1_DCFG5, 0x400108ea +.set CYDEV_UCFG_B0_P4_U1_DCFG6, 0x400108ec +.set CYDEV_UCFG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYDEV_UCFG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYDEV_UCFG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYDEV_UCFG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYDEV_UCFG_B0_P5_U0_CFG0, 0x40010a40 +.set CYDEV_UCFG_B0_P5_U0_CFG1, 0x40010a41 +.set CYDEV_UCFG_B0_P5_U0_CFG2, 0x40010a42 +.set CYDEV_UCFG_B0_P5_U0_CFG3, 0x40010a43 +.set CYDEV_UCFG_B0_P5_U0_CFG4, 0x40010a44 +.set CYDEV_UCFG_B0_P5_U0_CFG5, 0x40010a45 +.set CYDEV_UCFG_B0_P5_U0_CFG6, 0x40010a46 +.set CYDEV_UCFG_B0_P5_U0_CFG7, 0x40010a47 +.set CYDEV_UCFG_B0_P5_U0_CFG8, 0x40010a48 +.set CYDEV_UCFG_B0_P5_U0_CFG9, 0x40010a49 +.set CYDEV_UCFG_B0_P5_U0_CFG10, 0x40010a4a +.set CYDEV_UCFG_B0_P5_U0_CFG11, 0x40010a4b +.set CYDEV_UCFG_B0_P5_U0_CFG12, 0x40010a4c +.set CYDEV_UCFG_B0_P5_U0_CFG13, 0x40010a4d +.set CYDEV_UCFG_B0_P5_U0_CFG14, 0x40010a4e +.set CYDEV_UCFG_B0_P5_U0_CFG15, 0x40010a4f +.set CYDEV_UCFG_B0_P5_U0_CFG16, 0x40010a50 +.set CYDEV_UCFG_B0_P5_U0_CFG17, 0x40010a51 +.set CYDEV_UCFG_B0_P5_U0_CFG18, 0x40010a52 +.set CYDEV_UCFG_B0_P5_U0_CFG19, 0x40010a53 +.set CYDEV_UCFG_B0_P5_U0_CFG20, 0x40010a54 +.set CYDEV_UCFG_B0_P5_U0_CFG21, 0x40010a55 +.set CYDEV_UCFG_B0_P5_U0_CFG22, 0x40010a56 +.set CYDEV_UCFG_B0_P5_U0_CFG23, 0x40010a57 +.set CYDEV_UCFG_B0_P5_U0_CFG24, 0x40010a58 +.set CYDEV_UCFG_B0_P5_U0_CFG25, 0x40010a59 +.set CYDEV_UCFG_B0_P5_U0_CFG26, 0x40010a5a +.set CYDEV_UCFG_B0_P5_U0_CFG27, 0x40010a5b +.set CYDEV_UCFG_B0_P5_U0_CFG28, 0x40010a5c +.set CYDEV_UCFG_B0_P5_U0_CFG29, 0x40010a5d +.set CYDEV_UCFG_B0_P5_U0_CFG30, 0x40010a5e +.set CYDEV_UCFG_B0_P5_U0_CFG31, 0x40010a5f +.set CYDEV_UCFG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYDEV_UCFG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYDEV_UCFG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYDEV_UCFG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYDEV_UCFG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYDEV_UCFG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYDEV_UCFG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYDEV_UCFG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYDEV_UCFG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYDEV_UCFG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYDEV_UCFG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYDEV_UCFG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYDEV_UCFG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYDEV_UCFG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYDEV_UCFG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYDEV_UCFG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYDEV_UCFG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYDEV_UCFG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYDEV_UCFG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYDEV_UCFG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYDEV_UCFG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYDEV_UCFG_B0_P5_U1_CFG10, 0x40010aca +.set CYDEV_UCFG_B0_P5_U1_CFG11, 0x40010acb +.set CYDEV_UCFG_B0_P5_U1_CFG12, 0x40010acc +.set CYDEV_UCFG_B0_P5_U1_CFG13, 0x40010acd +.set CYDEV_UCFG_B0_P5_U1_CFG14, 0x40010ace +.set CYDEV_UCFG_B0_P5_U1_CFG15, 0x40010acf +.set CYDEV_UCFG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYDEV_UCFG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYDEV_UCFG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYDEV_UCFG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYDEV_UCFG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYDEV_UCFG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYDEV_UCFG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYDEV_UCFG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYDEV_UCFG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYDEV_UCFG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYDEV_UCFG_B0_P5_U1_CFG26, 0x40010ada +.set CYDEV_UCFG_B0_P5_U1_CFG27, 0x40010adb +.set CYDEV_UCFG_B0_P5_U1_CFG28, 0x40010adc +.set CYDEV_UCFG_B0_P5_U1_CFG29, 0x40010add +.set CYDEV_UCFG_B0_P5_U1_CFG30, 0x40010ade +.set CYDEV_UCFG_B0_P5_U1_CFG31, 0x40010adf +.set CYDEV_UCFG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYDEV_UCFG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYDEV_UCFG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYDEV_UCFG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYDEV_UCFG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYDEV_UCFG_B0_P5_U1_DCFG5, 0x40010aea +.set CYDEV_UCFG_B0_P5_U1_DCFG6, 0x40010aec +.set CYDEV_UCFG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYDEV_UCFG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYDEV_UCFG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYDEV_UCFG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYDEV_UCFG_B0_P6_U0_CFG0, 0x40010c40 +.set CYDEV_UCFG_B0_P6_U0_CFG1, 0x40010c41 +.set CYDEV_UCFG_B0_P6_U0_CFG2, 0x40010c42 +.set CYDEV_UCFG_B0_P6_U0_CFG3, 0x40010c43 +.set CYDEV_UCFG_B0_P6_U0_CFG4, 0x40010c44 +.set CYDEV_UCFG_B0_P6_U0_CFG5, 0x40010c45 +.set CYDEV_UCFG_B0_P6_U0_CFG6, 0x40010c46 +.set CYDEV_UCFG_B0_P6_U0_CFG7, 0x40010c47 +.set CYDEV_UCFG_B0_P6_U0_CFG8, 0x40010c48 +.set CYDEV_UCFG_B0_P6_U0_CFG9, 0x40010c49 +.set CYDEV_UCFG_B0_P6_U0_CFG10, 0x40010c4a +.set CYDEV_UCFG_B0_P6_U0_CFG11, 0x40010c4b +.set CYDEV_UCFG_B0_P6_U0_CFG12, 0x40010c4c +.set CYDEV_UCFG_B0_P6_U0_CFG13, 0x40010c4d +.set CYDEV_UCFG_B0_P6_U0_CFG14, 0x40010c4e +.set CYDEV_UCFG_B0_P6_U0_CFG15, 0x40010c4f +.set CYDEV_UCFG_B0_P6_U0_CFG16, 0x40010c50 +.set CYDEV_UCFG_B0_P6_U0_CFG17, 0x40010c51 +.set CYDEV_UCFG_B0_P6_U0_CFG18, 0x40010c52 +.set CYDEV_UCFG_B0_P6_U0_CFG19, 0x40010c53 +.set CYDEV_UCFG_B0_P6_U0_CFG20, 0x40010c54 +.set CYDEV_UCFG_B0_P6_U0_CFG21, 0x40010c55 +.set CYDEV_UCFG_B0_P6_U0_CFG22, 0x40010c56 +.set CYDEV_UCFG_B0_P6_U0_CFG23, 0x40010c57 +.set CYDEV_UCFG_B0_P6_U0_CFG24, 0x40010c58 +.set CYDEV_UCFG_B0_P6_U0_CFG25, 0x40010c59 +.set CYDEV_UCFG_B0_P6_U0_CFG26, 0x40010c5a +.set CYDEV_UCFG_B0_P6_U0_CFG27, 0x40010c5b +.set CYDEV_UCFG_B0_P6_U0_CFG28, 0x40010c5c +.set CYDEV_UCFG_B0_P6_U0_CFG29, 0x40010c5d +.set CYDEV_UCFG_B0_P6_U0_CFG30, 0x40010c5e +.set CYDEV_UCFG_B0_P6_U0_CFG31, 0x40010c5f +.set CYDEV_UCFG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYDEV_UCFG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYDEV_UCFG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYDEV_UCFG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYDEV_UCFG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYDEV_UCFG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYDEV_UCFG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYDEV_UCFG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYDEV_UCFG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYDEV_UCFG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYDEV_UCFG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYDEV_UCFG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYDEV_UCFG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYDEV_UCFG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYDEV_UCFG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYDEV_UCFG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYDEV_UCFG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYDEV_UCFG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYDEV_UCFG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYDEV_UCFG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYDEV_UCFG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYDEV_UCFG_B0_P6_U1_CFG10, 0x40010cca +.set CYDEV_UCFG_B0_P6_U1_CFG11, 0x40010ccb +.set CYDEV_UCFG_B0_P6_U1_CFG12, 0x40010ccc +.set CYDEV_UCFG_B0_P6_U1_CFG13, 0x40010ccd +.set CYDEV_UCFG_B0_P6_U1_CFG14, 0x40010cce +.set CYDEV_UCFG_B0_P6_U1_CFG15, 0x40010ccf +.set CYDEV_UCFG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYDEV_UCFG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYDEV_UCFG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYDEV_UCFG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYDEV_UCFG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYDEV_UCFG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYDEV_UCFG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYDEV_UCFG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYDEV_UCFG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYDEV_UCFG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYDEV_UCFG_B0_P6_U1_CFG26, 0x40010cda +.set CYDEV_UCFG_B0_P6_U1_CFG27, 0x40010cdb +.set CYDEV_UCFG_B0_P6_U1_CFG28, 0x40010cdc +.set CYDEV_UCFG_B0_P6_U1_CFG29, 0x40010cdd +.set CYDEV_UCFG_B0_P6_U1_CFG30, 0x40010cde +.set CYDEV_UCFG_B0_P6_U1_CFG31, 0x40010cdf +.set CYDEV_UCFG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYDEV_UCFG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYDEV_UCFG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYDEV_UCFG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYDEV_UCFG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYDEV_UCFG_B0_P6_U1_DCFG5, 0x40010cea +.set CYDEV_UCFG_B0_P6_U1_DCFG6, 0x40010cec +.set CYDEV_UCFG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYDEV_UCFG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYDEV_UCFG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYDEV_UCFG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYDEV_UCFG_B0_P7_U0_CFG0, 0x40010e40 +.set CYDEV_UCFG_B0_P7_U0_CFG1, 0x40010e41 +.set CYDEV_UCFG_B0_P7_U0_CFG2, 0x40010e42 +.set CYDEV_UCFG_B0_P7_U0_CFG3, 0x40010e43 +.set CYDEV_UCFG_B0_P7_U0_CFG4, 0x40010e44 +.set CYDEV_UCFG_B0_P7_U0_CFG5, 0x40010e45 +.set CYDEV_UCFG_B0_P7_U0_CFG6, 0x40010e46 +.set CYDEV_UCFG_B0_P7_U0_CFG7, 0x40010e47 +.set CYDEV_UCFG_B0_P7_U0_CFG8, 0x40010e48 +.set CYDEV_UCFG_B0_P7_U0_CFG9, 0x40010e49 +.set CYDEV_UCFG_B0_P7_U0_CFG10, 0x40010e4a +.set CYDEV_UCFG_B0_P7_U0_CFG11, 0x40010e4b +.set CYDEV_UCFG_B0_P7_U0_CFG12, 0x40010e4c +.set CYDEV_UCFG_B0_P7_U0_CFG13, 0x40010e4d +.set CYDEV_UCFG_B0_P7_U0_CFG14, 0x40010e4e +.set CYDEV_UCFG_B0_P7_U0_CFG15, 0x40010e4f +.set CYDEV_UCFG_B0_P7_U0_CFG16, 0x40010e50 +.set CYDEV_UCFG_B0_P7_U0_CFG17, 0x40010e51 +.set CYDEV_UCFG_B0_P7_U0_CFG18, 0x40010e52 +.set CYDEV_UCFG_B0_P7_U0_CFG19, 0x40010e53 +.set CYDEV_UCFG_B0_P7_U0_CFG20, 0x40010e54 +.set CYDEV_UCFG_B0_P7_U0_CFG21, 0x40010e55 +.set CYDEV_UCFG_B0_P7_U0_CFG22, 0x40010e56 +.set CYDEV_UCFG_B0_P7_U0_CFG23, 0x40010e57 +.set CYDEV_UCFG_B0_P7_U0_CFG24, 0x40010e58 +.set CYDEV_UCFG_B0_P7_U0_CFG25, 0x40010e59 +.set CYDEV_UCFG_B0_P7_U0_CFG26, 0x40010e5a +.set CYDEV_UCFG_B0_P7_U0_CFG27, 0x40010e5b +.set CYDEV_UCFG_B0_P7_U0_CFG28, 0x40010e5c +.set CYDEV_UCFG_B0_P7_U0_CFG29, 0x40010e5d +.set CYDEV_UCFG_B0_P7_U0_CFG30, 0x40010e5e +.set CYDEV_UCFG_B0_P7_U0_CFG31, 0x40010e5f +.set CYDEV_UCFG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYDEV_UCFG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYDEV_UCFG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYDEV_UCFG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYDEV_UCFG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYDEV_UCFG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYDEV_UCFG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYDEV_UCFG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYDEV_UCFG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYDEV_UCFG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYDEV_UCFG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYDEV_UCFG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYDEV_UCFG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYDEV_UCFG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYDEV_UCFG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYDEV_UCFG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYDEV_UCFG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYDEV_UCFG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYDEV_UCFG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYDEV_UCFG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYDEV_UCFG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYDEV_UCFG_B0_P7_U1_CFG10, 0x40010eca +.set CYDEV_UCFG_B0_P7_U1_CFG11, 0x40010ecb +.set CYDEV_UCFG_B0_P7_U1_CFG12, 0x40010ecc +.set CYDEV_UCFG_B0_P7_U1_CFG13, 0x40010ecd +.set CYDEV_UCFG_B0_P7_U1_CFG14, 0x40010ece +.set CYDEV_UCFG_B0_P7_U1_CFG15, 0x40010ecf +.set CYDEV_UCFG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYDEV_UCFG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYDEV_UCFG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYDEV_UCFG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYDEV_UCFG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYDEV_UCFG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYDEV_UCFG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYDEV_UCFG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYDEV_UCFG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYDEV_UCFG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYDEV_UCFG_B0_P7_U1_CFG26, 0x40010eda +.set CYDEV_UCFG_B0_P7_U1_CFG27, 0x40010edb +.set CYDEV_UCFG_B0_P7_U1_CFG28, 0x40010edc +.set CYDEV_UCFG_B0_P7_U1_CFG29, 0x40010edd +.set CYDEV_UCFG_B0_P7_U1_CFG30, 0x40010ede +.set CYDEV_UCFG_B0_P7_U1_CFG31, 0x40010edf +.set CYDEV_UCFG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYDEV_UCFG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYDEV_UCFG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYDEV_UCFG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYDEV_UCFG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYDEV_UCFG_B0_P7_U1_DCFG5, 0x40010eea +.set CYDEV_UCFG_B0_P7_U1_DCFG6, 0x40010eec +.set CYDEV_UCFG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYDEV_UCFG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYDEV_UCFG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYDEV_UCFG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYDEV_UCFG_B1_P2_U0_CFG0, 0x40011440 +.set CYDEV_UCFG_B1_P2_U0_CFG1, 0x40011441 +.set CYDEV_UCFG_B1_P2_U0_CFG2, 0x40011442 +.set CYDEV_UCFG_B1_P2_U0_CFG3, 0x40011443 +.set CYDEV_UCFG_B1_P2_U0_CFG4, 0x40011444 +.set CYDEV_UCFG_B1_P2_U0_CFG5, 0x40011445 +.set CYDEV_UCFG_B1_P2_U0_CFG6, 0x40011446 +.set CYDEV_UCFG_B1_P2_U0_CFG7, 0x40011447 +.set CYDEV_UCFG_B1_P2_U0_CFG8, 0x40011448 +.set CYDEV_UCFG_B1_P2_U0_CFG9, 0x40011449 +.set CYDEV_UCFG_B1_P2_U0_CFG10, 0x4001144a +.set CYDEV_UCFG_B1_P2_U0_CFG11, 0x4001144b +.set CYDEV_UCFG_B1_P2_U0_CFG12, 0x4001144c +.set CYDEV_UCFG_B1_P2_U0_CFG13, 0x4001144d +.set CYDEV_UCFG_B1_P2_U0_CFG14, 0x4001144e +.set CYDEV_UCFG_B1_P2_U0_CFG15, 0x4001144f +.set CYDEV_UCFG_B1_P2_U0_CFG16, 0x40011450 +.set CYDEV_UCFG_B1_P2_U0_CFG17, 0x40011451 +.set CYDEV_UCFG_B1_P2_U0_CFG18, 0x40011452 +.set CYDEV_UCFG_B1_P2_U0_CFG19, 0x40011453 +.set CYDEV_UCFG_B1_P2_U0_CFG20, 0x40011454 +.set CYDEV_UCFG_B1_P2_U0_CFG21, 0x40011455 +.set CYDEV_UCFG_B1_P2_U0_CFG22, 0x40011456 +.set CYDEV_UCFG_B1_P2_U0_CFG23, 0x40011457 +.set CYDEV_UCFG_B1_P2_U0_CFG24, 0x40011458 +.set CYDEV_UCFG_B1_P2_U0_CFG25, 0x40011459 +.set CYDEV_UCFG_B1_P2_U0_CFG26, 0x4001145a +.set CYDEV_UCFG_B1_P2_U0_CFG27, 0x4001145b +.set CYDEV_UCFG_B1_P2_U0_CFG28, 0x4001145c +.set CYDEV_UCFG_B1_P2_U0_CFG29, 0x4001145d +.set CYDEV_UCFG_B1_P2_U0_CFG30, 0x4001145e +.set CYDEV_UCFG_B1_P2_U0_CFG31, 0x4001145f +.set CYDEV_UCFG_B1_P2_U0_DCFG0, 0x40011460 +.set CYDEV_UCFG_B1_P2_U0_DCFG1, 0x40011462 +.set CYDEV_UCFG_B1_P2_U0_DCFG2, 0x40011464 +.set CYDEV_UCFG_B1_P2_U0_DCFG3, 0x40011466 +.set CYDEV_UCFG_B1_P2_U0_DCFG4, 0x40011468 +.set CYDEV_UCFG_B1_P2_U0_DCFG5, 0x4001146a +.set CYDEV_UCFG_B1_P2_U0_DCFG6, 0x4001146c +.set CYDEV_UCFG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYDEV_UCFG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYDEV_UCFG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYDEV_UCFG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYDEV_UCFG_B1_P2_U1_CFG0, 0x400114c0 +.set CYDEV_UCFG_B1_P2_U1_CFG1, 0x400114c1 +.set CYDEV_UCFG_B1_P2_U1_CFG2, 0x400114c2 +.set CYDEV_UCFG_B1_P2_U1_CFG3, 0x400114c3 +.set CYDEV_UCFG_B1_P2_U1_CFG4, 0x400114c4 +.set CYDEV_UCFG_B1_P2_U1_CFG5, 0x400114c5 +.set CYDEV_UCFG_B1_P2_U1_CFG6, 0x400114c6 +.set CYDEV_UCFG_B1_P2_U1_CFG7, 0x400114c7 +.set CYDEV_UCFG_B1_P2_U1_CFG8, 0x400114c8 +.set CYDEV_UCFG_B1_P2_U1_CFG9, 0x400114c9 +.set CYDEV_UCFG_B1_P2_U1_CFG10, 0x400114ca +.set CYDEV_UCFG_B1_P2_U1_CFG11, 0x400114cb +.set CYDEV_UCFG_B1_P2_U1_CFG12, 0x400114cc +.set CYDEV_UCFG_B1_P2_U1_CFG13, 0x400114cd +.set CYDEV_UCFG_B1_P2_U1_CFG14, 0x400114ce +.set CYDEV_UCFG_B1_P2_U1_CFG15, 0x400114cf +.set CYDEV_UCFG_B1_P2_U1_CFG16, 0x400114d0 +.set CYDEV_UCFG_B1_P2_U1_CFG17, 0x400114d1 +.set CYDEV_UCFG_B1_P2_U1_CFG18, 0x400114d2 +.set CYDEV_UCFG_B1_P2_U1_CFG19, 0x400114d3 +.set CYDEV_UCFG_B1_P2_U1_CFG20, 0x400114d4 +.set CYDEV_UCFG_B1_P2_U1_CFG21, 0x400114d5 +.set CYDEV_UCFG_B1_P2_U1_CFG22, 0x400114d6 +.set CYDEV_UCFG_B1_P2_U1_CFG23, 0x400114d7 +.set CYDEV_UCFG_B1_P2_U1_CFG24, 0x400114d8 +.set CYDEV_UCFG_B1_P2_U1_CFG25, 0x400114d9 +.set CYDEV_UCFG_B1_P2_U1_CFG26, 0x400114da +.set CYDEV_UCFG_B1_P2_U1_CFG27, 0x400114db +.set CYDEV_UCFG_B1_P2_U1_CFG28, 0x400114dc +.set CYDEV_UCFG_B1_P2_U1_CFG29, 0x400114dd +.set CYDEV_UCFG_B1_P2_U1_CFG30, 0x400114de +.set CYDEV_UCFG_B1_P2_U1_CFG31, 0x400114df +.set CYDEV_UCFG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYDEV_UCFG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYDEV_UCFG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYDEV_UCFG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYDEV_UCFG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYDEV_UCFG_B1_P2_U1_DCFG5, 0x400114ea +.set CYDEV_UCFG_B1_P2_U1_DCFG6, 0x400114ec +.set CYDEV_UCFG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYDEV_UCFG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYDEV_UCFG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYDEV_UCFG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYDEV_UCFG_B1_P3_U0_CFG0, 0x40011640 +.set CYDEV_UCFG_B1_P3_U0_CFG1, 0x40011641 +.set CYDEV_UCFG_B1_P3_U0_CFG2, 0x40011642 +.set CYDEV_UCFG_B1_P3_U0_CFG3, 0x40011643 +.set CYDEV_UCFG_B1_P3_U0_CFG4, 0x40011644 +.set CYDEV_UCFG_B1_P3_U0_CFG5, 0x40011645 +.set CYDEV_UCFG_B1_P3_U0_CFG6, 0x40011646 +.set CYDEV_UCFG_B1_P3_U0_CFG7, 0x40011647 +.set CYDEV_UCFG_B1_P3_U0_CFG8, 0x40011648 +.set CYDEV_UCFG_B1_P3_U0_CFG9, 0x40011649 +.set CYDEV_UCFG_B1_P3_U0_CFG10, 0x4001164a +.set CYDEV_UCFG_B1_P3_U0_CFG11, 0x4001164b +.set CYDEV_UCFG_B1_P3_U0_CFG12, 0x4001164c +.set CYDEV_UCFG_B1_P3_U0_CFG13, 0x4001164d +.set CYDEV_UCFG_B1_P3_U0_CFG14, 0x4001164e +.set CYDEV_UCFG_B1_P3_U0_CFG15, 0x4001164f +.set CYDEV_UCFG_B1_P3_U0_CFG16, 0x40011650 +.set CYDEV_UCFG_B1_P3_U0_CFG17, 0x40011651 +.set CYDEV_UCFG_B1_P3_U0_CFG18, 0x40011652 +.set CYDEV_UCFG_B1_P3_U0_CFG19, 0x40011653 +.set CYDEV_UCFG_B1_P3_U0_CFG20, 0x40011654 +.set CYDEV_UCFG_B1_P3_U0_CFG21, 0x40011655 +.set CYDEV_UCFG_B1_P3_U0_CFG22, 0x40011656 +.set CYDEV_UCFG_B1_P3_U0_CFG23, 0x40011657 +.set CYDEV_UCFG_B1_P3_U0_CFG24, 0x40011658 +.set CYDEV_UCFG_B1_P3_U0_CFG25, 0x40011659 +.set CYDEV_UCFG_B1_P3_U0_CFG26, 0x4001165a +.set CYDEV_UCFG_B1_P3_U0_CFG27, 0x4001165b +.set CYDEV_UCFG_B1_P3_U0_CFG28, 0x4001165c +.set CYDEV_UCFG_B1_P3_U0_CFG29, 0x4001165d +.set CYDEV_UCFG_B1_P3_U0_CFG30, 0x4001165e +.set CYDEV_UCFG_B1_P3_U0_CFG31, 0x4001165f +.set CYDEV_UCFG_B1_P3_U0_DCFG0, 0x40011660 +.set CYDEV_UCFG_B1_P3_U0_DCFG1, 0x40011662 +.set CYDEV_UCFG_B1_P3_U0_DCFG2, 0x40011664 +.set CYDEV_UCFG_B1_P3_U0_DCFG3, 0x40011666 +.set CYDEV_UCFG_B1_P3_U0_DCFG4, 0x40011668 +.set CYDEV_UCFG_B1_P3_U0_DCFG5, 0x4001166a +.set CYDEV_UCFG_B1_P3_U0_DCFG6, 0x4001166c +.set CYDEV_UCFG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYDEV_UCFG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYDEV_UCFG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYDEV_UCFG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYDEV_UCFG_B1_P3_U1_CFG0, 0x400116c0 +.set CYDEV_UCFG_B1_P3_U1_CFG1, 0x400116c1 +.set CYDEV_UCFG_B1_P3_U1_CFG2, 0x400116c2 +.set CYDEV_UCFG_B1_P3_U1_CFG3, 0x400116c3 +.set CYDEV_UCFG_B1_P3_U1_CFG4, 0x400116c4 +.set CYDEV_UCFG_B1_P3_U1_CFG5, 0x400116c5 +.set CYDEV_UCFG_B1_P3_U1_CFG6, 0x400116c6 +.set CYDEV_UCFG_B1_P3_U1_CFG7, 0x400116c7 +.set CYDEV_UCFG_B1_P3_U1_CFG8, 0x400116c8 +.set CYDEV_UCFG_B1_P3_U1_CFG9, 0x400116c9 +.set CYDEV_UCFG_B1_P3_U1_CFG10, 0x400116ca +.set CYDEV_UCFG_B1_P3_U1_CFG11, 0x400116cb +.set CYDEV_UCFG_B1_P3_U1_CFG12, 0x400116cc +.set CYDEV_UCFG_B1_P3_U1_CFG13, 0x400116cd +.set CYDEV_UCFG_B1_P3_U1_CFG14, 0x400116ce +.set CYDEV_UCFG_B1_P3_U1_CFG15, 0x400116cf +.set CYDEV_UCFG_B1_P3_U1_CFG16, 0x400116d0 +.set CYDEV_UCFG_B1_P3_U1_CFG17, 0x400116d1 +.set CYDEV_UCFG_B1_P3_U1_CFG18, 0x400116d2 +.set CYDEV_UCFG_B1_P3_U1_CFG19, 0x400116d3 +.set CYDEV_UCFG_B1_P3_U1_CFG20, 0x400116d4 +.set CYDEV_UCFG_B1_P3_U1_CFG21, 0x400116d5 +.set CYDEV_UCFG_B1_P3_U1_CFG22, 0x400116d6 +.set CYDEV_UCFG_B1_P3_U1_CFG23, 0x400116d7 +.set CYDEV_UCFG_B1_P3_U1_CFG24, 0x400116d8 +.set CYDEV_UCFG_B1_P3_U1_CFG25, 0x400116d9 +.set CYDEV_UCFG_B1_P3_U1_CFG26, 0x400116da +.set CYDEV_UCFG_B1_P3_U1_CFG27, 0x400116db +.set CYDEV_UCFG_B1_P3_U1_CFG28, 0x400116dc +.set CYDEV_UCFG_B1_P3_U1_CFG29, 0x400116dd +.set CYDEV_UCFG_B1_P3_U1_CFG30, 0x400116de +.set CYDEV_UCFG_B1_P3_U1_CFG31, 0x400116df +.set CYDEV_UCFG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYDEV_UCFG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYDEV_UCFG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYDEV_UCFG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYDEV_UCFG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYDEV_UCFG_B1_P3_U1_DCFG5, 0x400116ea +.set CYDEV_UCFG_B1_P3_U1_DCFG6, 0x400116ec +.set CYDEV_UCFG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYDEV_UCFG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYDEV_UCFG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYDEV_UCFG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYDEV_UCFG_B1_P4_U0_CFG0, 0x40011840 +.set CYDEV_UCFG_B1_P4_U0_CFG1, 0x40011841 +.set CYDEV_UCFG_B1_P4_U0_CFG2, 0x40011842 +.set CYDEV_UCFG_B1_P4_U0_CFG3, 0x40011843 +.set CYDEV_UCFG_B1_P4_U0_CFG4, 0x40011844 +.set CYDEV_UCFG_B1_P4_U0_CFG5, 0x40011845 +.set CYDEV_UCFG_B1_P4_U0_CFG6, 0x40011846 +.set CYDEV_UCFG_B1_P4_U0_CFG7, 0x40011847 +.set CYDEV_UCFG_B1_P4_U0_CFG8, 0x40011848 +.set CYDEV_UCFG_B1_P4_U0_CFG9, 0x40011849 +.set CYDEV_UCFG_B1_P4_U0_CFG10, 0x4001184a +.set CYDEV_UCFG_B1_P4_U0_CFG11, 0x4001184b +.set CYDEV_UCFG_B1_P4_U0_CFG12, 0x4001184c +.set CYDEV_UCFG_B1_P4_U0_CFG13, 0x4001184d +.set CYDEV_UCFG_B1_P4_U0_CFG14, 0x4001184e +.set CYDEV_UCFG_B1_P4_U0_CFG15, 0x4001184f +.set CYDEV_UCFG_B1_P4_U0_CFG16, 0x40011850 +.set CYDEV_UCFG_B1_P4_U0_CFG17, 0x40011851 +.set CYDEV_UCFG_B1_P4_U0_CFG18, 0x40011852 +.set CYDEV_UCFG_B1_P4_U0_CFG19, 0x40011853 +.set CYDEV_UCFG_B1_P4_U0_CFG20, 0x40011854 +.set CYDEV_UCFG_B1_P4_U0_CFG21, 0x40011855 +.set CYDEV_UCFG_B1_P4_U0_CFG22, 0x40011856 +.set CYDEV_UCFG_B1_P4_U0_CFG23, 0x40011857 +.set CYDEV_UCFG_B1_P4_U0_CFG24, 0x40011858 +.set CYDEV_UCFG_B1_P4_U0_CFG25, 0x40011859 +.set CYDEV_UCFG_B1_P4_U0_CFG26, 0x4001185a +.set CYDEV_UCFG_B1_P4_U0_CFG27, 0x4001185b +.set CYDEV_UCFG_B1_P4_U0_CFG28, 0x4001185c +.set CYDEV_UCFG_B1_P4_U0_CFG29, 0x4001185d +.set CYDEV_UCFG_B1_P4_U0_CFG30, 0x4001185e +.set CYDEV_UCFG_B1_P4_U0_CFG31, 0x4001185f +.set CYDEV_UCFG_B1_P4_U0_DCFG0, 0x40011860 +.set CYDEV_UCFG_B1_P4_U0_DCFG1, 0x40011862 +.set CYDEV_UCFG_B1_P4_U0_DCFG2, 0x40011864 +.set CYDEV_UCFG_B1_P4_U0_DCFG3, 0x40011866 +.set CYDEV_UCFG_B1_P4_U0_DCFG4, 0x40011868 +.set CYDEV_UCFG_B1_P4_U0_DCFG5, 0x4001186a +.set CYDEV_UCFG_B1_P4_U0_DCFG6, 0x4001186c +.set CYDEV_UCFG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYDEV_UCFG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYDEV_UCFG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYDEV_UCFG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYDEV_UCFG_B1_P4_U1_CFG0, 0x400118c0 +.set CYDEV_UCFG_B1_P4_U1_CFG1, 0x400118c1 +.set CYDEV_UCFG_B1_P4_U1_CFG2, 0x400118c2 +.set CYDEV_UCFG_B1_P4_U1_CFG3, 0x400118c3 +.set CYDEV_UCFG_B1_P4_U1_CFG4, 0x400118c4 +.set CYDEV_UCFG_B1_P4_U1_CFG5, 0x400118c5 +.set CYDEV_UCFG_B1_P4_U1_CFG6, 0x400118c6 +.set CYDEV_UCFG_B1_P4_U1_CFG7, 0x400118c7 +.set CYDEV_UCFG_B1_P4_U1_CFG8, 0x400118c8 +.set CYDEV_UCFG_B1_P4_U1_CFG9, 0x400118c9 +.set CYDEV_UCFG_B1_P4_U1_CFG10, 0x400118ca +.set CYDEV_UCFG_B1_P4_U1_CFG11, 0x400118cb +.set CYDEV_UCFG_B1_P4_U1_CFG12, 0x400118cc +.set CYDEV_UCFG_B1_P4_U1_CFG13, 0x400118cd +.set CYDEV_UCFG_B1_P4_U1_CFG14, 0x400118ce +.set CYDEV_UCFG_B1_P4_U1_CFG15, 0x400118cf +.set CYDEV_UCFG_B1_P4_U1_CFG16, 0x400118d0 +.set CYDEV_UCFG_B1_P4_U1_CFG17, 0x400118d1 +.set CYDEV_UCFG_B1_P4_U1_CFG18, 0x400118d2 +.set CYDEV_UCFG_B1_P4_U1_CFG19, 0x400118d3 +.set CYDEV_UCFG_B1_P4_U1_CFG20, 0x400118d4 +.set CYDEV_UCFG_B1_P4_U1_CFG21, 0x400118d5 +.set CYDEV_UCFG_B1_P4_U1_CFG22, 0x400118d6 +.set CYDEV_UCFG_B1_P4_U1_CFG23, 0x400118d7 +.set CYDEV_UCFG_B1_P4_U1_CFG24, 0x400118d8 +.set CYDEV_UCFG_B1_P4_U1_CFG25, 0x400118d9 +.set CYDEV_UCFG_B1_P4_U1_CFG26, 0x400118da +.set CYDEV_UCFG_B1_P4_U1_CFG27, 0x400118db +.set CYDEV_UCFG_B1_P4_U1_CFG28, 0x400118dc +.set CYDEV_UCFG_B1_P4_U1_CFG29, 0x400118dd +.set CYDEV_UCFG_B1_P4_U1_CFG30, 0x400118de +.set CYDEV_UCFG_B1_P4_U1_CFG31, 0x400118df +.set CYDEV_UCFG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYDEV_UCFG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYDEV_UCFG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYDEV_UCFG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYDEV_UCFG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYDEV_UCFG_B1_P4_U1_DCFG5, 0x400118ea +.set CYDEV_UCFG_B1_P4_U1_DCFG6, 0x400118ec +.set CYDEV_UCFG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYDEV_UCFG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYDEV_UCFG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYDEV_UCFG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYDEV_UCFG_B1_P5_U0_CFG0, 0x40011a40 +.set CYDEV_UCFG_B1_P5_U0_CFG1, 0x40011a41 +.set CYDEV_UCFG_B1_P5_U0_CFG2, 0x40011a42 +.set CYDEV_UCFG_B1_P5_U0_CFG3, 0x40011a43 +.set CYDEV_UCFG_B1_P5_U0_CFG4, 0x40011a44 +.set CYDEV_UCFG_B1_P5_U0_CFG5, 0x40011a45 +.set CYDEV_UCFG_B1_P5_U0_CFG6, 0x40011a46 +.set CYDEV_UCFG_B1_P5_U0_CFG7, 0x40011a47 +.set CYDEV_UCFG_B1_P5_U0_CFG8, 0x40011a48 +.set CYDEV_UCFG_B1_P5_U0_CFG9, 0x40011a49 +.set CYDEV_UCFG_B1_P5_U0_CFG10, 0x40011a4a +.set CYDEV_UCFG_B1_P5_U0_CFG11, 0x40011a4b +.set CYDEV_UCFG_B1_P5_U0_CFG12, 0x40011a4c +.set CYDEV_UCFG_B1_P5_U0_CFG13, 0x40011a4d +.set CYDEV_UCFG_B1_P5_U0_CFG14, 0x40011a4e +.set CYDEV_UCFG_B1_P5_U0_CFG15, 0x40011a4f +.set CYDEV_UCFG_B1_P5_U0_CFG16, 0x40011a50 +.set CYDEV_UCFG_B1_P5_U0_CFG17, 0x40011a51 +.set CYDEV_UCFG_B1_P5_U0_CFG18, 0x40011a52 +.set CYDEV_UCFG_B1_P5_U0_CFG19, 0x40011a53 +.set CYDEV_UCFG_B1_P5_U0_CFG20, 0x40011a54 +.set CYDEV_UCFG_B1_P5_U0_CFG21, 0x40011a55 +.set CYDEV_UCFG_B1_P5_U0_CFG22, 0x40011a56 +.set CYDEV_UCFG_B1_P5_U0_CFG23, 0x40011a57 +.set CYDEV_UCFG_B1_P5_U0_CFG24, 0x40011a58 +.set CYDEV_UCFG_B1_P5_U0_CFG25, 0x40011a59 +.set CYDEV_UCFG_B1_P5_U0_CFG26, 0x40011a5a +.set CYDEV_UCFG_B1_P5_U0_CFG27, 0x40011a5b +.set CYDEV_UCFG_B1_P5_U0_CFG28, 0x40011a5c +.set CYDEV_UCFG_B1_P5_U0_CFG29, 0x40011a5d +.set CYDEV_UCFG_B1_P5_U0_CFG30, 0x40011a5e +.set CYDEV_UCFG_B1_P5_U0_CFG31, 0x40011a5f +.set CYDEV_UCFG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYDEV_UCFG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYDEV_UCFG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYDEV_UCFG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYDEV_UCFG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYDEV_UCFG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYDEV_UCFG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYDEV_UCFG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYDEV_UCFG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYDEV_UCFG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYDEV_UCFG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYDEV_UCFG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYDEV_UCFG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYDEV_UCFG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYDEV_UCFG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYDEV_UCFG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYDEV_UCFG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYDEV_UCFG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYDEV_UCFG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYDEV_UCFG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYDEV_UCFG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYDEV_UCFG_B1_P5_U1_CFG10, 0x40011aca +.set CYDEV_UCFG_B1_P5_U1_CFG11, 0x40011acb +.set CYDEV_UCFG_B1_P5_U1_CFG12, 0x40011acc +.set CYDEV_UCFG_B1_P5_U1_CFG13, 0x40011acd +.set CYDEV_UCFG_B1_P5_U1_CFG14, 0x40011ace +.set CYDEV_UCFG_B1_P5_U1_CFG15, 0x40011acf +.set CYDEV_UCFG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYDEV_UCFG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYDEV_UCFG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYDEV_UCFG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYDEV_UCFG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYDEV_UCFG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYDEV_UCFG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYDEV_UCFG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYDEV_UCFG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYDEV_UCFG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYDEV_UCFG_B1_P5_U1_CFG26, 0x40011ada +.set CYDEV_UCFG_B1_P5_U1_CFG27, 0x40011adb +.set CYDEV_UCFG_B1_P5_U1_CFG28, 0x40011adc +.set CYDEV_UCFG_B1_P5_U1_CFG29, 0x40011add +.set CYDEV_UCFG_B1_P5_U1_CFG30, 0x40011ade +.set CYDEV_UCFG_B1_P5_U1_CFG31, 0x40011adf +.set CYDEV_UCFG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYDEV_UCFG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYDEV_UCFG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYDEV_UCFG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYDEV_UCFG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYDEV_UCFG_B1_P5_U1_DCFG5, 0x40011aea +.set CYDEV_UCFG_B1_P5_U1_DCFG6, 0x40011aec +.set CYDEV_UCFG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL0_MDCLK_EN, 0x40015000 +.set CYDEV_UCFG_BCTL0_MBCLK_EN, 0x40015001 +.set CYDEV_UCFG_BCTL0_WAIT_CFG, 0x40015002 +.set CYDEV_UCFG_BCTL0_BANK_CTL, 0x40015003 +.set CYDEV_UCFG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYDEV_UCFG_BCTL0_DCLK_EN0, 0x40015008 +.set CYDEV_UCFG_BCTL0_BCLK_EN0, 0x40015009 +.set CYDEV_UCFG_BCTL0_DCLK_EN1, 0x4001500a +.set CYDEV_UCFG_BCTL0_BCLK_EN1, 0x4001500b +.set CYDEV_UCFG_BCTL0_DCLK_EN2, 0x4001500c +.set CYDEV_UCFG_BCTL0_BCLK_EN2, 0x4001500d +.set CYDEV_UCFG_BCTL0_DCLK_EN3, 0x4001500e +.set CYDEV_UCFG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYDEV_UCFG_BCTL1_MDCLK_EN, 0x40015010 +.set CYDEV_UCFG_BCTL1_MBCLK_EN, 0x40015011 +.set CYDEV_UCFG_BCTL1_WAIT_CFG, 0x40015012 +.set CYDEV_UCFG_BCTL1_BANK_CTL, 0x40015013 +.set CYDEV_UCFG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYDEV_UCFG_BCTL1_DCLK_EN0, 0x40015018 +.set CYDEV_UCFG_BCTL1_BCLK_EN0, 0x40015019 +.set CYDEV_UCFG_BCTL1_DCLK_EN1, 0x4001501a +.set CYDEV_UCFG_BCTL1_BCLK_EN1, 0x4001501b +.set CYDEV_UCFG_BCTL1_DCLK_EN2, 0x4001501c +.set CYDEV_UCFG_BCTL1_BCLK_EN2, 0x4001501d +.set CYDEV_UCFG_BCTL1_DCLK_EN3, 0x4001501e +.set CYDEV_UCFG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYDEV_IDMUX_IRQ_CTL0, 0x40015100 +.set CYDEV_IDMUX_IRQ_CTL1, 0x40015101 +.set CYDEV_IDMUX_IRQ_CTL2, 0x40015102 +.set CYDEV_IDMUX_IRQ_CTL3, 0x40015103 +.set CYDEV_IDMUX_IRQ_CTL4, 0x40015104 +.set CYDEV_IDMUX_IRQ_CTL5, 0x40015105 +.set CYDEV_IDMUX_IRQ_CTL6, 0x40015106 +.set CYDEV_IDMUX_IRQ_CTL7, 0x40015107 +.set CYDEV_IDMUX_DRQ_CTL0, 0x40015110 +.set CYDEV_IDMUX_DRQ_CTL1, 0x40015111 +.set CYDEV_IDMUX_DRQ_CTL2, 0x40015112 +.set CYDEV_IDMUX_DRQ_CTL3, 0x40015113 +.set CYDEV_IDMUX_DRQ_CTL4, 0x40015114 +.set CYDEV_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYDEV_CACHERAM_DATA_MBASE, 0x40030000 +.set CYDEV_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYDEV_SFR_GPIO0, 0x40050180 +.set CYDEV_SFR_GPIRD0, 0x40050189 +.set CYDEV_SFR_GPIO0_SEL, 0x4005018a +.set CYDEV_SFR_GPIO1, 0x40050190 +.set CYDEV_SFR_GPIRD1, 0x40050191 +.set CYDEV_SFR_GPIO2, 0x40050198 +.set CYDEV_SFR_GPIRD2, 0x40050199 +.set CYDEV_SFR_GPIO2_SEL, 0x4005019a +.set CYDEV_SFR_GPIO1_SEL, 0x400501a2 +.set CYDEV_SFR_GPIO3, 0x400501b0 +.set CYDEV_SFR_GPIRD3, 0x400501b1 +.set CYDEV_SFR_GPIO3_SEL, 0x400501b2 +.set CYDEV_SFR_GPIO4, 0x400501c0 +.set CYDEV_SFR_GPIRD4, 0x400501c1 +.set CYDEV_SFR_GPIO4_SEL, 0x400501c2 +.set CYDEV_SFR_GPIO5, 0x400501c8 +.set CYDEV_SFR_GPIRD5, 0x400501c9 +.set CYDEV_SFR_GPIO5_SEL, 0x400501ca +.set CYDEV_SFR_GPIO6, 0x400501d8 +.set CYDEV_SFR_GPIRD6, 0x400501d9 +.set CYDEV_SFR_GPIO6_SEL, 0x400501da +.set CYDEV_SFR_GPIO12, 0x400501e8 +.set CYDEV_SFR_GPIRD12, 0x400501e9 +.set CYDEV_SFR_GPIO12_SEL, 0x400501f2 +.set CYDEV_SFR_GPIO15, 0x400501f8 +.set CYDEV_SFR_GPIRD15, 0x400501f9 +.set CYDEV_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYDEV_P3BA_Y_START, 0x40050300 +.set CYDEV_P3BA_YROLL, 0x40050301 +.set CYDEV_P3BA_YCFG, 0x40050302 +.set CYDEV_P3BA_X_START1, 0x40050303 +.set CYDEV_P3BA_X_START2, 0x40050304 +.set CYDEV_P3BA_XROLL1, 0x40050305 +.set CYDEV_P3BA_XROLL2, 0x40050306 +.set CYDEV_P3BA_XINC, 0x40050307 +.set CYDEV_P3BA_XCFG, 0x40050308 +.set CYDEV_P3BA_OFFSETADDR1, 0x40050309 +.set CYDEV_P3BA_OFFSETADDR2, 0x4005030a +.set CYDEV_P3BA_OFFSETADDR3, 0x4005030b +.set CYDEV_P3BA_ABSADDR1, 0x4005030c +.set CYDEV_P3BA_ABSADDR2, 0x4005030d +.set CYDEV_P3BA_ABSADDR3, 0x4005030e +.set CYDEV_P3BA_ABSADDR4, 0x4005030f +.set CYDEV_P3BA_DATCFG1, 0x40050310 +.set CYDEV_P3BA_DATCFG2, 0x40050311 +.set CYDEV_P3BA_CMP_RSLT1, 0x40050314 +.set CYDEV_P3BA_CMP_RSLT2, 0x40050315 +.set CYDEV_P3BA_CMP_RSLT3, 0x40050316 +.set CYDEV_P3BA_CMP_RSLT4, 0x40050317 +.set CYDEV_P3BA_DATA_REG1, 0x40050318 +.set CYDEV_P3BA_DATA_REG2, 0x40050319 +.set CYDEV_P3BA_DATA_REG3, 0x4005031a +.set CYDEV_P3BA_DATA_REG4, 0x4005031b +.set CYDEV_P3BA_EXP_DATA1, 0x4005031c +.set CYDEV_P3BA_EXP_DATA2, 0x4005031d +.set CYDEV_P3BA_EXP_DATA3, 0x4005031e +.set CYDEV_P3BA_EXP_DATA4, 0x4005031f +.set CYDEV_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYDEV_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYDEV_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYDEV_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYDEV_P3BA_BIST_EN, 0x40050324 +.set CYDEV_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYDEV_P3BA_SEQCFG1, 0x40050326 +.set CYDEV_P3BA_SEQCFG2, 0x40050327 +.set CYDEV_P3BA_Y_CURR, 0x40050328 +.set CYDEV_P3BA_X_CURR1, 0x40050329 +.set CYDEV_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYDEV_PANTHER_STCALIB_CFG, 0x40080000 +.set CYDEV_PANTHER_WAITPIPE, 0x40080004 +.set CYDEV_PANTHER_TRACE_CFG, 0x40080008 +.set CYDEV_PANTHER_DBG_CFG, 0x4008000c +.set CYDEV_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYDEV_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYDEV_FLSECC_DATA_MBASE, 0x48000000 +.set CYDEV_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYDEV_FLSHID_RSVD_MBASE, 0x49000000 +.set CYDEV_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYDEV_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYDEV_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYDEV_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYDEV_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYDEV_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYDEV_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYDEV_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYDEV_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYDEV_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYDEV_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYDEV_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYDEV_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYDEV_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYDEV_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYDEV_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYDEV_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYDEV_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYDEV_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYDEV_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYDEV_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYDEV_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYDEV_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYDEV_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYDEV_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYDEV_EXTMEM_DATA_MBASE, 0x60000000 +.set CYDEV_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYDEV_ITM_TRACE_EN, 0xe0000e00 +.set CYDEV_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYDEV_ITM_TRACE_CTRL, 0xe0000e80 +.set CYDEV_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYDEV_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYDEV_ITM_PID4, 0xe0000fd0 +.set CYDEV_ITM_PID5, 0xe0000fd4 +.set CYDEV_ITM_PID6, 0xe0000fd8 +.set CYDEV_ITM_PID7, 0xe0000fdc +.set CYDEV_ITM_PID0, 0xe0000fe0 +.set CYDEV_ITM_PID1, 0xe0000fe4 +.set CYDEV_ITM_PID2, 0xe0000fe8 +.set CYDEV_ITM_PID3, 0xe0000fec +.set CYDEV_ITM_CID0, 0xe0000ff0 +.set CYDEV_ITM_CID1, 0xe0000ff4 +.set CYDEV_ITM_CID2, 0xe0000ff8 +.set CYDEV_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYDEV_DWT_CTRL, 0xe0001000 +.set CYDEV_DWT_CYCLE_COUNT, 0xe0001004 +.set CYDEV_DWT_CPI_COUNT, 0xe0001008 +.set CYDEV_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYDEV_DWT_SLEEP_COUNT, 0xe0001010 +.set CYDEV_DWT_LSU_COUNT, 0xe0001014 +.set CYDEV_DWT_FOLD_COUNT, 0xe0001018 +.set CYDEV_DWT_PC_SAMPLE, 0xe000101c +.set CYDEV_DWT_COMP_0, 0xe0001020 +.set CYDEV_DWT_MASK_0, 0xe0001024 +.set CYDEV_DWT_FUNCTION_0, 0xe0001028 +.set CYDEV_DWT_COMP_1, 0xe0001030 +.set CYDEV_DWT_MASK_1, 0xe0001034 +.set CYDEV_DWT_FUNCTION_1, 0xe0001038 +.set CYDEV_DWT_COMP_2, 0xe0001040 +.set CYDEV_DWT_MASK_2, 0xe0001044 +.set CYDEV_DWT_FUNCTION_2, 0xe0001048 +.set CYDEV_DWT_COMP_3, 0xe0001050 +.set CYDEV_DWT_MASK_3, 0xe0001054 +.set CYDEV_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYDEV_FPB_CTRL, 0xe0002000 +.set CYDEV_FPB_REMAP, 0xe0002004 +.set CYDEV_FPB_FP_COMP_0, 0xe0002008 +.set CYDEV_FPB_FP_COMP_1, 0xe000200c +.set CYDEV_FPB_FP_COMP_2, 0xe0002010 +.set CYDEV_FPB_FP_COMP_3, 0xe0002014 +.set CYDEV_FPB_FP_COMP_4, 0xe0002018 +.set CYDEV_FPB_FP_COMP_5, 0xe000201c +.set CYDEV_FPB_FP_COMP_6, 0xe0002020 +.set CYDEV_FPB_FP_COMP_7, 0xe0002024 +.set CYDEV_FPB_PID4, 0xe0002fd0 +.set CYDEV_FPB_PID5, 0xe0002fd4 +.set CYDEV_FPB_PID6, 0xe0002fd8 +.set CYDEV_FPB_PID7, 0xe0002fdc +.set CYDEV_FPB_PID0, 0xe0002fe0 +.set CYDEV_FPB_PID1, 0xe0002fe4 +.set CYDEV_FPB_PID2, 0xe0002fe8 +.set CYDEV_FPB_PID3, 0xe0002fec +.set CYDEV_FPB_CID0, 0xe0002ff0 +.set CYDEV_FPB_CID1, 0xe0002ff4 +.set CYDEV_FPB_CID2, 0xe0002ff8 +.set CYDEV_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYDEV_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYDEV_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYDEV_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYDEV_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYDEV_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYDEV_NVIC_SETENA0, 0xe000e100 +.set CYDEV_NVIC_CLRENA0, 0xe000e180 +.set CYDEV_NVIC_SETPEND0, 0xe000e200 +.set CYDEV_NVIC_CLRPEND0, 0xe000e280 +.set CYDEV_NVIC_ACTIVE0, 0xe000e300 +.set CYDEV_NVIC_PRI_0, 0xe000e400 +.set CYDEV_NVIC_PRI_1, 0xe000e401 +.set CYDEV_NVIC_PRI_2, 0xe000e402 +.set CYDEV_NVIC_PRI_3, 0xe000e403 +.set CYDEV_NVIC_PRI_4, 0xe000e404 +.set CYDEV_NVIC_PRI_5, 0xe000e405 +.set CYDEV_NVIC_PRI_6, 0xe000e406 +.set CYDEV_NVIC_PRI_7, 0xe000e407 +.set CYDEV_NVIC_PRI_8, 0xe000e408 +.set CYDEV_NVIC_PRI_9, 0xe000e409 +.set CYDEV_NVIC_PRI_10, 0xe000e40a +.set CYDEV_NVIC_PRI_11, 0xe000e40b +.set CYDEV_NVIC_PRI_12, 0xe000e40c +.set CYDEV_NVIC_PRI_13, 0xe000e40d +.set CYDEV_NVIC_PRI_14, 0xe000e40e +.set CYDEV_NVIC_PRI_15, 0xe000e40f +.set CYDEV_NVIC_PRI_16, 0xe000e410 +.set CYDEV_NVIC_PRI_17, 0xe000e411 +.set CYDEV_NVIC_PRI_18, 0xe000e412 +.set CYDEV_NVIC_PRI_19, 0xe000e413 +.set CYDEV_NVIC_PRI_20, 0xe000e414 +.set CYDEV_NVIC_PRI_21, 0xe000e415 +.set CYDEV_NVIC_PRI_22, 0xe000e416 +.set CYDEV_NVIC_PRI_23, 0xe000e417 +.set CYDEV_NVIC_PRI_24, 0xe000e418 +.set CYDEV_NVIC_PRI_25, 0xe000e419 +.set CYDEV_NVIC_PRI_26, 0xe000e41a +.set CYDEV_NVIC_PRI_27, 0xe000e41b +.set CYDEV_NVIC_PRI_28, 0xe000e41c +.set CYDEV_NVIC_PRI_29, 0xe000e41d +.set CYDEV_NVIC_PRI_30, 0xe000e41e +.set CYDEV_NVIC_PRI_31, 0xe000e41f +.set CYDEV_NVIC_CPUID_BASE, 0xe000ed00 +.set CYDEV_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYDEV_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYDEV_NVIC_APPLN_INTR, 0xe000ed0c +.set CYDEV_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYDEV_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYDEV_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYDEV_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYDEV_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYDEV_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYDEV_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYDEV_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYDEV_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYDEV_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYDEV_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYDEV_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYDEV_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYDEV_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYDEV_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYDEV_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYDEV_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYDEV_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYDEV_TPIU_PROTOCOL, 0xe00400f0 +.set CYDEV_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYDEV_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYDEV_TPIU_TRIGGER, 0xe0040ee8 +.set CYDEV_TPIU_ITETMDATA, 0xe0040eec +.set CYDEV_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYDEV_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYDEV_TPIU_ITITMDATA, 0xe0040efc +.set CYDEV_TPIU_ITCTRL, 0xe0040f00 +.set CYDEV_TPIU_DEVID, 0xe0040fc8 +.set CYDEV_TPIU_DEVTYPE, 0xe0040fcc +.set CYDEV_TPIU_PID4, 0xe0040fd0 +.set CYDEV_TPIU_PID5, 0xe0040fd4 +.set CYDEV_TPIU_PID6, 0xe0040fd8 +.set CYDEV_TPIU_PID7, 0xe0040fdc +.set CYDEV_TPIU_PID0, 0xe0040fe0 +.set CYDEV_TPIU_PID1, 0xe0040fe4 +.set CYDEV_TPIU_PID2, 0xe0040fe8 +.set CYDEV_TPIU_PID3, 0xe0040fec +.set CYDEV_TPIU_CID0, 0xe0040ff0 +.set CYDEV_TPIU_CID1, 0xe0040ff4 +.set CYDEV_TPIU_CID2, 0xe0040ff8 +.set CYDEV_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYDEV_ETM_CTL, 0xe0041000 +.set CYDEV_ETM_CFG_CODE, 0xe0041004 +.set CYDEV_ETM_TRIG_EVENT, 0xe0041008 +.set CYDEV_ETM_STATUS, 0xe0041010 +.set CYDEV_ETM_SYS_CFG, 0xe0041014 +.set CYDEV_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYDEV_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYDEV_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYDEV_ETM_SYNC_FREQ, 0xe00411e0 +.set CYDEV_ETM_ETM_ID, 0xe00411e4 +.set CYDEV_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYDEV_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYDEV_ETM_CS_TRACE_ID, 0xe0041200 +.set CYDEV_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYDEV_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYDEV_ETM_PDSR, 0xe0041314 +.set CYDEV_ETM_ITMISCIN, 0xe0041ee0 +.set CYDEV_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYDEV_ETM_ITATBCTR2, 0xe0041ef0 +.set CYDEV_ETM_ITATBCTR0, 0xe0041ef8 +.set CYDEV_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYDEV_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYDEV_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYDEV_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYDEV_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYDEV_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYDEV_ETM_DEV_TYPE, 0xe0041fcc +.set CYDEV_ETM_PID4, 0xe0041fd0 +.set CYDEV_ETM_PID5, 0xe0041fd4 +.set CYDEV_ETM_PID6, 0xe0041fd8 +.set CYDEV_ETM_PID7, 0xe0041fdc +.set CYDEV_ETM_PID0, 0xe0041fe0 +.set CYDEV_ETM_PID1, 0xe0041fe4 +.set CYDEV_ETM_PID2, 0xe0041fe8 +.set CYDEV_ETM_PID3, 0xe0041fec +.set CYDEV_ETM_CID0, 0xe0041ff0 +.set CYDEV_ETM_CID1, 0xe0041ff4 +.set CYDEV_ETM_CID2, 0xe0041ff8 +.set CYDEV_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYDEV_ROM_TABLE_NVIC, 0xe00ff000 +.set CYDEV_ROM_TABLE_DWT, 0xe00ff004 +.set CYDEV_ROM_TABLE_FPB, 0xe00ff008 +.set CYDEV_ROM_TABLE_ITM, 0xe00ff00c +.set CYDEV_ROM_TABLE_TPIU, 0xe00ff010 +.set CYDEV_ROM_TABLE_ETM, 0xe00ff014 +.set CYDEV_ROM_TABLE_END, 0xe00ff018 +.set CYDEV_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYDEV_ROM_TABLE_PID4, 0xe00fffd0 +.set CYDEV_ROM_TABLE_PID5, 0xe00fffd4 +.set CYDEV_ROM_TABLE_PID6, 0xe00fffd8 +.set CYDEV_ROM_TABLE_PID7, 0xe00fffdc +.set CYDEV_ROM_TABLE_PID0, 0xe00fffe0 +.set CYDEV_ROM_TABLE_PID1, 0xe00fffe4 +.set CYDEV_ROM_TABLE_PID2, 0xe00fffe8 +.set CYDEV_ROM_TABLE_PID3, 0xe00fffec +.set CYDEV_ROM_TABLE_CID0, 0xe00ffff0 +.set CYDEV_ROM_TABLE_CID1, 0xe00ffff4 +.set CYDEV_ROM_TABLE_CID2, 0xe00ffff8 +.set CYDEV_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc new file mode 100644 index 0000000..e2e2aa7 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc @@ -0,0 +1,5357 @@ +/******************************************************************************* +* File Name: cydevicegnu_trm.inc +* +* PSoC Creator 4.2 +* +* Description: +* This file provides all of the address values for the entire PSoC device. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.set CYDEV_FLASH_BASE, 0x00000000 +.set CYDEV_FLASH_SIZE, 0x00020000 +.set CYREG_FLASH_DATA_MBASE, 0x00000000 +.set CYREG_FLASH_DATA_MSIZE, 0x00020000 +.set CYDEV_SRAM_BASE, 0x1fffc000 +.set CYDEV_SRAM_SIZE, 0x00008000 +.set CYREG_SRAM_CODE64K_MBASE, 0x1fff8000 +.set CYREG_SRAM_CODE64K_MSIZE, 0x00004000 +.set CYREG_SRAM_CODE32K_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE32K_MSIZE, 0x00002000 +.set CYREG_SRAM_CODE16K_MBASE, 0x1fffe000 +.set CYREG_SRAM_CODE16K_MSIZE, 0x00001000 +.set CYREG_SRAM_CODE_MBASE, 0x1fffc000 +.set CYREG_SRAM_CODE_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA_MBASE, 0x20000000 +.set CYREG_SRAM_DATA_MSIZE, 0x00004000 +.set CYREG_SRAM_DATA16K_MBASE, 0x20001000 +.set CYREG_SRAM_DATA16K_MSIZE, 0x00001000 +.set CYREG_SRAM_DATA32K_MBASE, 0x20002000 +.set CYREG_SRAM_DATA32K_MSIZE, 0x00002000 +.set CYREG_SRAM_DATA64K_MBASE, 0x20004000 +.set CYREG_SRAM_DATA64K_MSIZE, 0x00004000 +.set CYDEV_DMA_BASE, 0x20008000 +.set CYDEV_DMA_SIZE, 0x00008000 +.set CYREG_DMA_SRAM64K_MBASE, 0x20008000 +.set CYREG_DMA_SRAM64K_MSIZE, 0x00004000 +.set CYREG_DMA_SRAM32K_MBASE, 0x2000c000 +.set CYREG_DMA_SRAM32K_MSIZE, 0x00002000 +.set CYREG_DMA_SRAM16K_MBASE, 0x2000e000 +.set CYREG_DMA_SRAM16K_MSIZE, 0x00001000 +.set CYREG_DMA_SRAM_MBASE, 0x2000f000 +.set CYREG_DMA_SRAM_MSIZE, 0x00001000 +.set CYDEV_CLKDIST_BASE, 0x40004000 +.set CYDEV_CLKDIST_SIZE, 0x00000110 +.set CYREG_CLKDIST_CR, 0x40004000 +.set CYREG_CLKDIST_LD, 0x40004001 +.set CYREG_CLKDIST_WRK0, 0x40004002 +.set CYREG_CLKDIST_WRK1, 0x40004003 +.set CYREG_CLKDIST_MSTR0, 0x40004004 +.set CYREG_CLKDIST_MSTR1, 0x40004005 +.set CYREG_CLKDIST_BCFG0, 0x40004006 +.set CYREG_CLKDIST_BCFG1, 0x40004007 +.set CYREG_CLKDIST_BCFG2, 0x40004008 +.set CYREG_CLKDIST_UCFG, 0x40004009 +.set CYREG_CLKDIST_DLY0, 0x4000400a +.set CYREG_CLKDIST_DLY1, 0x4000400b +.set CYREG_CLKDIST_DMASK, 0x40004010 +.set CYREG_CLKDIST_AMASK, 0x40004014 +.set CYDEV_CLKDIST_DCFG0_BASE, 0x40004080 +.set CYDEV_CLKDIST_DCFG0_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG0_CFG0, 0x40004080 +.set CYREG_CLKDIST_DCFG0_CFG1, 0x40004081 +.set CYREG_CLKDIST_DCFG0_CFG2, 0x40004082 +.set CYDEV_CLKDIST_DCFG1_BASE, 0x40004084 +.set CYDEV_CLKDIST_DCFG1_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG1_CFG0, 0x40004084 +.set CYREG_CLKDIST_DCFG1_CFG1, 0x40004085 +.set CYREG_CLKDIST_DCFG1_CFG2, 0x40004086 +.set CYDEV_CLKDIST_DCFG2_BASE, 0x40004088 +.set CYDEV_CLKDIST_DCFG2_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG2_CFG0, 0x40004088 +.set CYREG_CLKDIST_DCFG2_CFG1, 0x40004089 +.set CYREG_CLKDIST_DCFG2_CFG2, 0x4000408a +.set CYDEV_CLKDIST_DCFG3_BASE, 0x4000408c +.set CYDEV_CLKDIST_DCFG3_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG3_CFG0, 0x4000408c +.set CYREG_CLKDIST_DCFG3_CFG1, 0x4000408d +.set CYREG_CLKDIST_DCFG3_CFG2, 0x4000408e +.set CYDEV_CLKDIST_DCFG4_BASE, 0x40004090 +.set CYDEV_CLKDIST_DCFG4_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG4_CFG0, 0x40004090 +.set CYREG_CLKDIST_DCFG4_CFG1, 0x40004091 +.set CYREG_CLKDIST_DCFG4_CFG2, 0x40004092 +.set CYDEV_CLKDIST_DCFG5_BASE, 0x40004094 +.set CYDEV_CLKDIST_DCFG5_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG5_CFG0, 0x40004094 +.set CYREG_CLKDIST_DCFG5_CFG1, 0x40004095 +.set CYREG_CLKDIST_DCFG5_CFG2, 0x40004096 +.set CYDEV_CLKDIST_DCFG6_BASE, 0x40004098 +.set CYDEV_CLKDIST_DCFG6_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG6_CFG0, 0x40004098 +.set CYREG_CLKDIST_DCFG6_CFG1, 0x40004099 +.set CYREG_CLKDIST_DCFG6_CFG2, 0x4000409a +.set CYDEV_CLKDIST_DCFG7_BASE, 0x4000409c +.set CYDEV_CLKDIST_DCFG7_SIZE, 0x00000003 +.set CYREG_CLKDIST_DCFG7_CFG0, 0x4000409c +.set CYREG_CLKDIST_DCFG7_CFG1, 0x4000409d +.set CYREG_CLKDIST_DCFG7_CFG2, 0x4000409e +.set CYDEV_CLKDIST_ACFG0_BASE, 0x40004100 +.set CYDEV_CLKDIST_ACFG0_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG0_CFG0, 0x40004100 +.set CYREG_CLKDIST_ACFG0_CFG1, 0x40004101 +.set CYREG_CLKDIST_ACFG0_CFG2, 0x40004102 +.set CYREG_CLKDIST_ACFG0_CFG3, 0x40004103 +.set CYDEV_CLKDIST_ACFG1_BASE, 0x40004104 +.set CYDEV_CLKDIST_ACFG1_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG1_CFG0, 0x40004104 +.set CYREG_CLKDIST_ACFG1_CFG1, 0x40004105 +.set CYREG_CLKDIST_ACFG1_CFG2, 0x40004106 +.set CYREG_CLKDIST_ACFG1_CFG3, 0x40004107 +.set CYDEV_CLKDIST_ACFG2_BASE, 0x40004108 +.set CYDEV_CLKDIST_ACFG2_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG2_CFG0, 0x40004108 +.set CYREG_CLKDIST_ACFG2_CFG1, 0x40004109 +.set CYREG_CLKDIST_ACFG2_CFG2, 0x4000410a +.set CYREG_CLKDIST_ACFG2_CFG3, 0x4000410b +.set CYDEV_CLKDIST_ACFG3_BASE, 0x4000410c +.set CYDEV_CLKDIST_ACFG3_SIZE, 0x00000004 +.set CYREG_CLKDIST_ACFG3_CFG0, 0x4000410c +.set CYREG_CLKDIST_ACFG3_CFG1, 0x4000410d +.set CYREG_CLKDIST_ACFG3_CFG2, 0x4000410e +.set CYREG_CLKDIST_ACFG3_CFG3, 0x4000410f +.set CYDEV_FASTCLK_BASE, 0x40004200 +.set CYDEV_FASTCLK_SIZE, 0x00000026 +.set CYDEV_FASTCLK_IMO_BASE, 0x40004200 +.set CYDEV_FASTCLK_IMO_SIZE, 0x00000001 +.set CYREG_FASTCLK_IMO_CR, 0x40004200 +.set CYDEV_FASTCLK_XMHZ_BASE, 0x40004210 +.set CYDEV_FASTCLK_XMHZ_SIZE, 0x00000004 +.set CYREG_FASTCLK_XMHZ_CSR, 0x40004210 +.set CYREG_FASTCLK_XMHZ_CFG0, 0x40004212 +.set CYREG_FASTCLK_XMHZ_CFG1, 0x40004213 +.set CYDEV_FASTCLK_PLL_BASE, 0x40004220 +.set CYDEV_FASTCLK_PLL_SIZE, 0x00000006 +.set CYREG_FASTCLK_PLL_CFG0, 0x40004220 +.set CYREG_FASTCLK_PLL_CFG1, 0x40004221 +.set CYREG_FASTCLK_PLL_P, 0x40004222 +.set CYREG_FASTCLK_PLL_Q, 0x40004223 +.set CYREG_FASTCLK_PLL_SR, 0x40004225 +.set CYDEV_SLOWCLK_BASE, 0x40004300 +.set CYDEV_SLOWCLK_SIZE, 0x0000000b +.set CYDEV_SLOWCLK_ILO_BASE, 0x40004300 +.set CYDEV_SLOWCLK_ILO_SIZE, 0x00000002 +.set CYREG_SLOWCLK_ILO_CR0, 0x40004300 +.set CYREG_SLOWCLK_ILO_CR1, 0x40004301 +.set CYDEV_SLOWCLK_X32_BASE, 0x40004308 +.set CYDEV_SLOWCLK_X32_SIZE, 0x00000003 +.set CYREG_SLOWCLK_X32_CR, 0x40004308 +.set CYREG_SLOWCLK_X32_CFG, 0x40004309 +.set CYREG_SLOWCLK_X32_TST, 0x4000430a +.set CYDEV_BOOST_BASE, 0x40004320 +.set CYDEV_BOOST_SIZE, 0x00000007 +.set CYREG_BOOST_CR0, 0x40004320 +.set CYREG_BOOST_CR1, 0x40004321 +.set CYREG_BOOST_CR2, 0x40004322 +.set CYREG_BOOST_CR3, 0x40004323 +.set CYREG_BOOST_SR, 0x40004324 +.set CYREG_BOOST_CR4, 0x40004325 +.set CYREG_BOOST_SR2, 0x40004326 +.set CYDEV_PWRSYS_BASE, 0x40004330 +.set CYDEV_PWRSYS_SIZE, 0x00000002 +.set CYREG_PWRSYS_CR0, 0x40004330 +.set CYREG_PWRSYS_CR1, 0x40004331 +.set CYDEV_PM_BASE, 0x40004380 +.set CYDEV_PM_SIZE, 0x00000057 +.set CYREG_PM_TW_CFG0, 0x40004380 +.set CYREG_PM_TW_CFG1, 0x40004381 +.set CYREG_PM_TW_CFG2, 0x40004382 +.set CYREG_PM_WDT_CFG, 0x40004383 +.set CYREG_PM_WDT_CR, 0x40004384 +.set CYREG_PM_INT_SR, 0x40004390 +.set CYREG_PM_MODE_CFG0, 0x40004391 +.set CYREG_PM_MODE_CFG1, 0x40004392 +.set CYREG_PM_MODE_CSR, 0x40004393 +.set CYREG_PM_USB_CR0, 0x40004394 +.set CYREG_PM_WAKEUP_CFG0, 0x40004398 +.set CYREG_PM_WAKEUP_CFG1, 0x40004399 +.set CYREG_PM_WAKEUP_CFG2, 0x4000439a +.set CYDEV_PM_ACT_BASE, 0x400043a0 +.set CYDEV_PM_ACT_SIZE, 0x0000000e +.set CYREG_PM_ACT_CFG0, 0x400043a0 +.set CYREG_PM_ACT_CFG1, 0x400043a1 +.set CYREG_PM_ACT_CFG2, 0x400043a2 +.set CYREG_PM_ACT_CFG3, 0x400043a3 +.set CYREG_PM_ACT_CFG4, 0x400043a4 +.set CYREG_PM_ACT_CFG5, 0x400043a5 +.set CYREG_PM_ACT_CFG6, 0x400043a6 +.set CYREG_PM_ACT_CFG7, 0x400043a7 +.set CYREG_PM_ACT_CFG8, 0x400043a8 +.set CYREG_PM_ACT_CFG9, 0x400043a9 +.set CYREG_PM_ACT_CFG10, 0x400043aa +.set CYREG_PM_ACT_CFG11, 0x400043ab +.set CYREG_PM_ACT_CFG12, 0x400043ac +.set CYREG_PM_ACT_CFG13, 0x400043ad +.set CYDEV_PM_STBY_BASE, 0x400043b0 +.set CYDEV_PM_STBY_SIZE, 0x0000000e +.set CYREG_PM_STBY_CFG0, 0x400043b0 +.set CYREG_PM_STBY_CFG1, 0x400043b1 +.set CYREG_PM_STBY_CFG2, 0x400043b2 +.set CYREG_PM_STBY_CFG3, 0x400043b3 +.set CYREG_PM_STBY_CFG4, 0x400043b4 +.set CYREG_PM_STBY_CFG5, 0x400043b5 +.set CYREG_PM_STBY_CFG6, 0x400043b6 +.set CYREG_PM_STBY_CFG7, 0x400043b7 +.set CYREG_PM_STBY_CFG8, 0x400043b8 +.set CYREG_PM_STBY_CFG9, 0x400043b9 +.set CYREG_PM_STBY_CFG10, 0x400043ba +.set CYREG_PM_STBY_CFG11, 0x400043bb +.set CYREG_PM_STBY_CFG12, 0x400043bc +.set CYREG_PM_STBY_CFG13, 0x400043bd +.set CYDEV_PM_AVAIL_BASE, 0x400043c0 +.set CYDEV_PM_AVAIL_SIZE, 0x00000017 +.set CYREG_PM_AVAIL_CR0, 0x400043c0 +.set CYREG_PM_AVAIL_CR1, 0x400043c1 +.set CYREG_PM_AVAIL_CR2, 0x400043c2 +.set CYREG_PM_AVAIL_CR3, 0x400043c3 +.set CYREG_PM_AVAIL_CR4, 0x400043c4 +.set CYREG_PM_AVAIL_CR5, 0x400043c5 +.set CYREG_PM_AVAIL_CR6, 0x400043c6 +.set CYREG_PM_AVAIL_SR0, 0x400043d0 +.set CYREG_PM_AVAIL_SR1, 0x400043d1 +.set CYREG_PM_AVAIL_SR2, 0x400043d2 +.set CYREG_PM_AVAIL_SR3, 0x400043d3 +.set CYREG_PM_AVAIL_SR4, 0x400043d4 +.set CYREG_PM_AVAIL_SR5, 0x400043d5 +.set CYREG_PM_AVAIL_SR6, 0x400043d6 +.set CYDEV_PICU_BASE, 0x40004500 +.set CYDEV_PICU_SIZE, 0x000000b0 +.set CYDEV_PICU_INTTYPE_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_SIZE, 0x00000080 +.set CYDEV_PICU_INTTYPE_PICU0_BASE, 0x40004500 +.set CYDEV_PICU_INTTYPE_PICU0_SIZE, 0x00000008 +.set CYREG_PICU0_INTTYPE0, 0x40004500 +.set CYREG_PICU0_INTTYPE1, 0x40004501 +.set CYREG_PICU0_INTTYPE2, 0x40004502 +.set CYREG_PICU0_INTTYPE3, 0x40004503 +.set CYREG_PICU0_INTTYPE4, 0x40004504 +.set CYREG_PICU0_INTTYPE5, 0x40004505 +.set CYREG_PICU0_INTTYPE6, 0x40004506 +.set CYREG_PICU0_INTTYPE7, 0x40004507 +.set CYDEV_PICU_INTTYPE_PICU1_BASE, 0x40004508 +.set CYDEV_PICU_INTTYPE_PICU1_SIZE, 0x00000008 +.set CYREG_PICU1_INTTYPE0, 0x40004508 +.set CYREG_PICU1_INTTYPE1, 0x40004509 +.set CYREG_PICU1_INTTYPE2, 0x4000450a +.set CYREG_PICU1_INTTYPE3, 0x4000450b +.set CYREG_PICU1_INTTYPE4, 0x4000450c +.set CYREG_PICU1_INTTYPE5, 0x4000450d +.set CYREG_PICU1_INTTYPE6, 0x4000450e +.set CYREG_PICU1_INTTYPE7, 0x4000450f +.set CYDEV_PICU_INTTYPE_PICU2_BASE, 0x40004510 +.set CYDEV_PICU_INTTYPE_PICU2_SIZE, 0x00000008 +.set CYREG_PICU2_INTTYPE0, 0x40004510 +.set CYREG_PICU2_INTTYPE1, 0x40004511 +.set CYREG_PICU2_INTTYPE2, 0x40004512 +.set CYREG_PICU2_INTTYPE3, 0x40004513 +.set CYREG_PICU2_INTTYPE4, 0x40004514 +.set CYREG_PICU2_INTTYPE5, 0x40004515 +.set CYREG_PICU2_INTTYPE6, 0x40004516 +.set CYREG_PICU2_INTTYPE7, 0x40004517 +.set CYDEV_PICU_INTTYPE_PICU3_BASE, 0x40004518 +.set CYDEV_PICU_INTTYPE_PICU3_SIZE, 0x00000008 +.set CYREG_PICU3_INTTYPE0, 0x40004518 +.set CYREG_PICU3_INTTYPE1, 0x40004519 +.set CYREG_PICU3_INTTYPE2, 0x4000451a +.set CYREG_PICU3_INTTYPE3, 0x4000451b +.set CYREG_PICU3_INTTYPE4, 0x4000451c +.set CYREG_PICU3_INTTYPE5, 0x4000451d +.set CYREG_PICU3_INTTYPE6, 0x4000451e +.set CYREG_PICU3_INTTYPE7, 0x4000451f +.set CYDEV_PICU_INTTYPE_PICU4_BASE, 0x40004520 +.set CYDEV_PICU_INTTYPE_PICU4_SIZE, 0x00000008 +.set CYREG_PICU4_INTTYPE0, 0x40004520 +.set CYREG_PICU4_INTTYPE1, 0x40004521 +.set CYREG_PICU4_INTTYPE2, 0x40004522 +.set CYREG_PICU4_INTTYPE3, 0x40004523 +.set CYREG_PICU4_INTTYPE4, 0x40004524 +.set CYREG_PICU4_INTTYPE5, 0x40004525 +.set CYREG_PICU4_INTTYPE6, 0x40004526 +.set CYREG_PICU4_INTTYPE7, 0x40004527 +.set CYDEV_PICU_INTTYPE_PICU5_BASE, 0x40004528 +.set CYDEV_PICU_INTTYPE_PICU5_SIZE, 0x00000008 +.set CYREG_PICU5_INTTYPE0, 0x40004528 +.set CYREG_PICU5_INTTYPE1, 0x40004529 +.set CYREG_PICU5_INTTYPE2, 0x4000452a +.set CYREG_PICU5_INTTYPE3, 0x4000452b +.set CYREG_PICU5_INTTYPE4, 0x4000452c +.set CYREG_PICU5_INTTYPE5, 0x4000452d +.set CYREG_PICU5_INTTYPE6, 0x4000452e +.set CYREG_PICU5_INTTYPE7, 0x4000452f +.set CYDEV_PICU_INTTYPE_PICU6_BASE, 0x40004530 +.set CYDEV_PICU_INTTYPE_PICU6_SIZE, 0x00000008 +.set CYREG_PICU6_INTTYPE0, 0x40004530 +.set CYREG_PICU6_INTTYPE1, 0x40004531 +.set CYREG_PICU6_INTTYPE2, 0x40004532 +.set CYREG_PICU6_INTTYPE3, 0x40004533 +.set CYREG_PICU6_INTTYPE4, 0x40004534 +.set CYREG_PICU6_INTTYPE5, 0x40004535 +.set CYREG_PICU6_INTTYPE6, 0x40004536 +.set CYREG_PICU6_INTTYPE7, 0x40004537 +.set CYDEV_PICU_INTTYPE_PICU12_BASE, 0x40004560 +.set CYDEV_PICU_INTTYPE_PICU12_SIZE, 0x00000008 +.set CYREG_PICU12_INTTYPE0, 0x40004560 +.set CYREG_PICU12_INTTYPE1, 0x40004561 +.set CYREG_PICU12_INTTYPE2, 0x40004562 +.set CYREG_PICU12_INTTYPE3, 0x40004563 +.set CYREG_PICU12_INTTYPE4, 0x40004564 +.set CYREG_PICU12_INTTYPE5, 0x40004565 +.set CYREG_PICU12_INTTYPE6, 0x40004566 +.set CYREG_PICU12_INTTYPE7, 0x40004567 +.set CYDEV_PICU_INTTYPE_PICU15_BASE, 0x40004578 +.set CYDEV_PICU_INTTYPE_PICU15_SIZE, 0x00000008 +.set CYREG_PICU15_INTTYPE0, 0x40004578 +.set CYREG_PICU15_INTTYPE1, 0x40004579 +.set CYREG_PICU15_INTTYPE2, 0x4000457a +.set CYREG_PICU15_INTTYPE3, 0x4000457b +.set CYREG_PICU15_INTTYPE4, 0x4000457c +.set CYREG_PICU15_INTTYPE5, 0x4000457d +.set CYREG_PICU15_INTTYPE6, 0x4000457e +.set CYREG_PICU15_INTTYPE7, 0x4000457f +.set CYDEV_PICU_STAT_BASE, 0x40004580 +.set CYDEV_PICU_STAT_SIZE, 0x00000010 +.set CYDEV_PICU_STAT_PICU0_BASE, 0x40004580 +.set CYDEV_PICU_STAT_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_INTSTAT, 0x40004580 +.set CYDEV_PICU_STAT_PICU1_BASE, 0x40004581 +.set CYDEV_PICU_STAT_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_INTSTAT, 0x40004581 +.set CYDEV_PICU_STAT_PICU2_BASE, 0x40004582 +.set CYDEV_PICU_STAT_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_INTSTAT, 0x40004582 +.set CYDEV_PICU_STAT_PICU3_BASE, 0x40004583 +.set CYDEV_PICU_STAT_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_INTSTAT, 0x40004583 +.set CYDEV_PICU_STAT_PICU4_BASE, 0x40004584 +.set CYDEV_PICU_STAT_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_INTSTAT, 0x40004584 +.set CYDEV_PICU_STAT_PICU5_BASE, 0x40004585 +.set CYDEV_PICU_STAT_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_INTSTAT, 0x40004585 +.set CYDEV_PICU_STAT_PICU6_BASE, 0x40004586 +.set CYDEV_PICU_STAT_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_INTSTAT, 0x40004586 +.set CYDEV_PICU_STAT_PICU12_BASE, 0x4000458c +.set CYDEV_PICU_STAT_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_INTSTAT, 0x4000458c +.set CYDEV_PICU_STAT_PICU15_BASE, 0x4000458f +.set CYDEV_PICU_STAT_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_INTSTAT, 0x4000458f +.set CYDEV_PICU_SNAP_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_SIZE, 0x00000010 +.set CYDEV_PICU_SNAP_PICU0_BASE, 0x40004590 +.set CYDEV_PICU_SNAP_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_SNAP, 0x40004590 +.set CYDEV_PICU_SNAP_PICU1_BASE, 0x40004591 +.set CYDEV_PICU_SNAP_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_SNAP, 0x40004591 +.set CYDEV_PICU_SNAP_PICU2_BASE, 0x40004592 +.set CYDEV_PICU_SNAP_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_SNAP, 0x40004592 +.set CYDEV_PICU_SNAP_PICU3_BASE, 0x40004593 +.set CYDEV_PICU_SNAP_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_SNAP, 0x40004593 +.set CYDEV_PICU_SNAP_PICU4_BASE, 0x40004594 +.set CYDEV_PICU_SNAP_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_SNAP, 0x40004594 +.set CYDEV_PICU_SNAP_PICU5_BASE, 0x40004595 +.set CYDEV_PICU_SNAP_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_SNAP, 0x40004595 +.set CYDEV_PICU_SNAP_PICU6_BASE, 0x40004596 +.set CYDEV_PICU_SNAP_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_SNAP, 0x40004596 +.set CYDEV_PICU_SNAP_PICU12_BASE, 0x4000459c +.set CYDEV_PICU_SNAP_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_SNAP, 0x4000459c +.set CYDEV_PICU_SNAP_PICU_15_BASE, 0x4000459f +.set CYDEV_PICU_SNAP_PICU_15_SIZE, 0x00000001 +.set CYREG_PICU_15_SNAP_15, 0x4000459f +.set CYDEV_PICU_DISABLE_COR_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_SIZE, 0x00000010 +.set CYDEV_PICU_DISABLE_COR_PICU0_BASE, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU0_SIZE, 0x00000001 +.set CYREG_PICU0_DISABLE_COR, 0x400045a0 +.set CYDEV_PICU_DISABLE_COR_PICU1_BASE, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU1_SIZE, 0x00000001 +.set CYREG_PICU1_DISABLE_COR, 0x400045a1 +.set CYDEV_PICU_DISABLE_COR_PICU2_BASE, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU2_SIZE, 0x00000001 +.set CYREG_PICU2_DISABLE_COR, 0x400045a2 +.set CYDEV_PICU_DISABLE_COR_PICU3_BASE, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU3_SIZE, 0x00000001 +.set CYREG_PICU3_DISABLE_COR, 0x400045a3 +.set CYDEV_PICU_DISABLE_COR_PICU4_BASE, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU4_SIZE, 0x00000001 +.set CYREG_PICU4_DISABLE_COR, 0x400045a4 +.set CYDEV_PICU_DISABLE_COR_PICU5_BASE, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU5_SIZE, 0x00000001 +.set CYREG_PICU5_DISABLE_COR, 0x400045a5 +.set CYDEV_PICU_DISABLE_COR_PICU6_BASE, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU6_SIZE, 0x00000001 +.set CYREG_PICU6_DISABLE_COR, 0x400045a6 +.set CYDEV_PICU_DISABLE_COR_PICU12_BASE, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU12_SIZE, 0x00000001 +.set CYREG_PICU12_DISABLE_COR, 0x400045ac +.set CYDEV_PICU_DISABLE_COR_PICU15_BASE, 0x400045af +.set CYDEV_PICU_DISABLE_COR_PICU15_SIZE, 0x00000001 +.set CYREG_PICU15_DISABLE_COR, 0x400045af +.set CYDEV_MFGCFG_BASE, 0x40004600 +.set CYDEV_MFGCFG_SIZE, 0x000000ed +.set CYDEV_MFGCFG_ANAIF_BASE, 0x40004600 +.set CYDEV_MFGCFG_ANAIF_SIZE, 0x00000038 +.set CYDEV_MFGCFG_ANAIF_DAC0_BASE, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_TR, 0x40004608 +.set CYDEV_MFGCFG_ANAIF_DAC1_BASE, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_TR, 0x40004609 +.set CYDEV_MFGCFG_ANAIF_DAC2_BASE, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_TR, 0x4000460a +.set CYDEV_MFGCFG_ANAIF_DAC3_BASE, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_TR, 0x4000460b +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE, 0x00000001 +.set CYREG_NPUMP_DSM_TR0, 0x40004610 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE, 0x00000001 +.set CYREG_NPUMP_SC_TR0, 0x40004611 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE, 0x00000001 +.set CYREG_NPUMP_OPAMP_TR0, 0x40004612 +.set CYDEV_MFGCFG_ANAIF_SAR0_BASE, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR0_SIZE, 0x00000001 +.set CYREG_SAR0_TR0, 0x40004614 +.set CYDEV_MFGCFG_ANAIF_SAR1_BASE, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_SAR1_SIZE, 0x00000001 +.set CYREG_SAR1_TR0, 0x40004616 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_BASE, 0x40004620 +.set CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_TR0, 0x40004620 +.set CYREG_OPAMP0_TR1, 0x40004621 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_BASE, 0x40004622 +.set CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_TR0, 0x40004622 +.set CYREG_OPAMP1_TR1, 0x40004623 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_BASE, 0x40004624 +.set CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_TR0, 0x40004624 +.set CYREG_OPAMP2_TR1, 0x40004625 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_BASE, 0x40004626 +.set CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_TR0, 0x40004626 +.set CYREG_OPAMP3_TR1, 0x40004627 +.set CYDEV_MFGCFG_ANAIF_CMP0_BASE, 0x40004630 +.set CYDEV_MFGCFG_ANAIF_CMP0_SIZE, 0x00000002 +.set CYREG_CMP0_TR0, 0x40004630 +.set CYREG_CMP0_TR1, 0x40004631 +.set CYDEV_MFGCFG_ANAIF_CMP1_BASE, 0x40004632 +.set CYDEV_MFGCFG_ANAIF_CMP1_SIZE, 0x00000002 +.set CYREG_CMP1_TR0, 0x40004632 +.set CYREG_CMP1_TR1, 0x40004633 +.set CYDEV_MFGCFG_ANAIF_CMP2_BASE, 0x40004634 +.set CYDEV_MFGCFG_ANAIF_CMP2_SIZE, 0x00000002 +.set CYREG_CMP2_TR0, 0x40004634 +.set CYREG_CMP2_TR1, 0x40004635 +.set CYDEV_MFGCFG_ANAIF_CMP3_BASE, 0x40004636 +.set CYDEV_MFGCFG_ANAIF_CMP3_SIZE, 0x00000002 +.set CYREG_CMP3_TR0, 0x40004636 +.set CYREG_CMP3_TR1, 0x40004637 +.set CYDEV_MFGCFG_PWRSYS_BASE, 0x40004680 +.set CYDEV_MFGCFG_PWRSYS_SIZE, 0x0000000b +.set CYREG_PWRSYS_HIB_TR0, 0x40004680 +.set CYREG_PWRSYS_HIB_TR1, 0x40004681 +.set CYREG_PWRSYS_I2C_TR, 0x40004682 +.set CYREG_PWRSYS_SLP_TR, 0x40004683 +.set CYREG_PWRSYS_BUZZ_TR, 0x40004684 +.set CYREG_PWRSYS_WAKE_TR0, 0x40004685 +.set CYREG_PWRSYS_WAKE_TR1, 0x40004686 +.set CYREG_PWRSYS_BREF_TR, 0x40004687 +.set CYREG_PWRSYS_BG_TR, 0x40004688 +.set CYREG_PWRSYS_WAKE_TR2, 0x40004689 +.set CYREG_PWRSYS_WAKE_TR3, 0x4000468a +.set CYDEV_MFGCFG_ILO_BASE, 0x40004690 +.set CYDEV_MFGCFG_ILO_SIZE, 0x00000002 +.set CYREG_ILO_TR0, 0x40004690 +.set CYREG_ILO_TR1, 0x40004691 +.set CYDEV_MFGCFG_X32_BASE, 0x40004698 +.set CYDEV_MFGCFG_X32_SIZE, 0x00000001 +.set CYREG_X32_TR, 0x40004698 +.set CYDEV_MFGCFG_IMO_BASE, 0x400046a0 +.set CYDEV_MFGCFG_IMO_SIZE, 0x00000005 +.set CYREG_IMO_TR0, 0x400046a0 +.set CYREG_IMO_TR1, 0x400046a1 +.set CYREG_IMO_GAIN, 0x400046a2 +.set CYREG_IMO_C36M, 0x400046a3 +.set CYREG_IMO_TR2, 0x400046a4 +.set CYDEV_MFGCFG_XMHZ_BASE, 0x400046a8 +.set CYDEV_MFGCFG_XMHZ_SIZE, 0x00000001 +.set CYREG_XMHZ_TR, 0x400046a8 +.set CYREG_MFGCFG_DLY, 0x400046c0 +.set CYDEV_MFGCFG_MLOGIC_BASE, 0x400046e0 +.set CYDEV_MFGCFG_MLOGIC_SIZE, 0x0000000d +.set CYREG_MLOGIC_DMPSTR, 0x400046e2 +.set CYDEV_MFGCFG_MLOGIC_SEG_BASE, 0x400046e4 +.set CYDEV_MFGCFG_MLOGIC_SEG_SIZE, 0x00000002 +.set CYREG_MLOGIC_SEG_CR, 0x400046e4 +.set CYREG_MLOGIC_SEG_CFG0, 0x400046e5 +.set CYREG_MLOGIC_DEBUG, 0x400046e8 +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE, 0x400046ea +.set CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE, 0x00000001 +.set CYREG_MLOGIC_CPU_SCR_CPU_SCR, 0x400046ea +.set CYREG_MLOGIC_REV_ID, 0x400046ec +.set CYDEV_RESET_BASE, 0x400046f0 +.set CYDEV_RESET_SIZE, 0x0000000f +.set CYREG_RESET_IPOR_CR0, 0x400046f0 +.set CYREG_RESET_IPOR_CR1, 0x400046f1 +.set CYREG_RESET_IPOR_CR2, 0x400046f2 +.set CYREG_RESET_IPOR_CR3, 0x400046f3 +.set CYREG_RESET_CR0, 0x400046f4 +.set CYREG_RESET_CR1, 0x400046f5 +.set CYREG_RESET_CR2, 0x400046f6 +.set CYREG_RESET_CR3, 0x400046f7 +.set CYREG_RESET_CR4, 0x400046f8 +.set CYREG_RESET_CR5, 0x400046f9 +.set CYREG_RESET_SR0, 0x400046fa +.set CYREG_RESET_SR1, 0x400046fb +.set CYREG_RESET_SR2, 0x400046fc +.set CYREG_RESET_SR3, 0x400046fd +.set CYREG_RESET_TR, 0x400046fe +.set CYDEV_SPC_BASE, 0x40004700 +.set CYDEV_SPC_SIZE, 0x00000100 +.set CYREG_SPC_FM_EE_CR, 0x40004700 +.set CYREG_SPC_FM_EE_WAKE_CNT, 0x40004701 +.set CYREG_SPC_EE_SCR, 0x40004702 +.set CYREG_SPC_EE_ERR, 0x40004703 +.set CYREG_SPC_CPU_DATA, 0x40004720 +.set CYREG_SPC_DMA_DATA, 0x40004721 +.set CYREG_SPC_SR, 0x40004722 +.set CYREG_SPC_CR, 0x40004723 +.set CYDEV_SPC_DMM_MAP_BASE, 0x40004780 +.set CYDEV_SPC_DMM_MAP_SIZE, 0x00000080 +.set CYREG_SPC_DMM_MAP_SRAM_MBASE, 0x40004780 +.set CYREG_SPC_DMM_MAP_SRAM_MSIZE, 0x00000080 +.set CYDEV_CACHE_BASE, 0x40004800 +.set CYDEV_CACHE_SIZE, 0x0000009c +.set CYREG_CACHE_CC_CTL, 0x40004800 +.set CYREG_CACHE_ECC_CORR, 0x40004880 +.set CYREG_CACHE_ECC_ERR, 0x40004888 +.set CYREG_CACHE_FLASH_ERR, 0x40004890 +.set CYREG_CACHE_HITMISS, 0x40004898 +.set CYDEV_I2C_BASE, 0x40004900 +.set CYDEV_I2C_SIZE, 0x000000e1 +.set CYREG_I2C_XCFG, 0x400049c8 +.set CYREG_I2C_ADR, 0x400049ca +.set CYREG_I2C_CFG, 0x400049d6 +.set CYREG_I2C_CSR, 0x400049d7 +.set CYREG_I2C_D, 0x400049d8 +.set CYREG_I2C_MCSR, 0x400049d9 +.set CYREG_I2C_CLK_DIV1, 0x400049db +.set CYREG_I2C_CLK_DIV2, 0x400049dc +.set CYREG_I2C_TMOUT_CSR, 0x400049dd +.set CYREG_I2C_TMOUT_SR, 0x400049de +.set CYREG_I2C_TMOUT_CFG0, 0x400049df +.set CYREG_I2C_TMOUT_CFG1, 0x400049e0 +.set CYDEV_DEC_BASE, 0x40004e00 +.set CYDEV_DEC_SIZE, 0x00000015 +.set CYREG_DEC_CR, 0x40004e00 +.set CYREG_DEC_SR, 0x40004e01 +.set CYREG_DEC_SHIFT1, 0x40004e02 +.set CYREG_DEC_SHIFT2, 0x40004e03 +.set CYREG_DEC_DR2, 0x40004e04 +.set CYREG_DEC_DR2H, 0x40004e05 +.set CYREG_DEC_DR1, 0x40004e06 +.set CYREG_DEC_OCOR, 0x40004e08 +.set CYREG_DEC_OCORM, 0x40004e09 +.set CYREG_DEC_OCORH, 0x40004e0a +.set CYREG_DEC_GCOR, 0x40004e0c +.set CYREG_DEC_GCORH, 0x40004e0d +.set CYREG_DEC_GVAL, 0x40004e0e +.set CYREG_DEC_OUTSAMP, 0x40004e10 +.set CYREG_DEC_OUTSAMPM, 0x40004e11 +.set CYREG_DEC_OUTSAMPH, 0x40004e12 +.set CYREG_DEC_OUTSAMPS, 0x40004e13 +.set CYREG_DEC_COHER, 0x40004e14 +.set CYDEV_TMR0_BASE, 0x40004f00 +.set CYDEV_TMR0_SIZE, 0x0000000c +.set CYREG_TMR0_CFG0, 0x40004f00 +.set CYREG_TMR0_CFG1, 0x40004f01 +.set CYREG_TMR0_CFG2, 0x40004f02 +.set CYREG_TMR0_SR0, 0x40004f03 +.set CYREG_TMR0_PER0, 0x40004f04 +.set CYREG_TMR0_PER1, 0x40004f05 +.set CYREG_TMR0_CNT_CMP0, 0x40004f06 +.set CYREG_TMR0_CNT_CMP1, 0x40004f07 +.set CYREG_TMR0_CAP0, 0x40004f08 +.set CYREG_TMR0_CAP1, 0x40004f09 +.set CYREG_TMR0_RT0, 0x40004f0a +.set CYREG_TMR0_RT1, 0x40004f0b +.set CYDEV_TMR1_BASE, 0x40004f0c +.set CYDEV_TMR1_SIZE, 0x0000000c +.set CYREG_TMR1_CFG0, 0x40004f0c +.set CYREG_TMR1_CFG1, 0x40004f0d +.set CYREG_TMR1_CFG2, 0x40004f0e +.set CYREG_TMR1_SR0, 0x40004f0f +.set CYREG_TMR1_PER0, 0x40004f10 +.set CYREG_TMR1_PER1, 0x40004f11 +.set CYREG_TMR1_CNT_CMP0, 0x40004f12 +.set CYREG_TMR1_CNT_CMP1, 0x40004f13 +.set CYREG_TMR1_CAP0, 0x40004f14 +.set CYREG_TMR1_CAP1, 0x40004f15 +.set CYREG_TMR1_RT0, 0x40004f16 +.set CYREG_TMR1_RT1, 0x40004f17 +.set CYDEV_TMR2_BASE, 0x40004f18 +.set CYDEV_TMR2_SIZE, 0x0000000c +.set CYREG_TMR2_CFG0, 0x40004f18 +.set CYREG_TMR2_CFG1, 0x40004f19 +.set CYREG_TMR2_CFG2, 0x40004f1a +.set CYREG_TMR2_SR0, 0x40004f1b +.set CYREG_TMR2_PER0, 0x40004f1c +.set CYREG_TMR2_PER1, 0x40004f1d +.set CYREG_TMR2_CNT_CMP0, 0x40004f1e +.set CYREG_TMR2_CNT_CMP1, 0x40004f1f +.set CYREG_TMR2_CAP0, 0x40004f20 +.set CYREG_TMR2_CAP1, 0x40004f21 +.set CYREG_TMR2_RT0, 0x40004f22 +.set CYREG_TMR2_RT1, 0x40004f23 +.set CYDEV_TMR3_BASE, 0x40004f24 +.set CYDEV_TMR3_SIZE, 0x0000000c +.set CYREG_TMR3_CFG0, 0x40004f24 +.set CYREG_TMR3_CFG1, 0x40004f25 +.set CYREG_TMR3_CFG2, 0x40004f26 +.set CYREG_TMR3_SR0, 0x40004f27 +.set CYREG_TMR3_PER0, 0x40004f28 +.set CYREG_TMR3_PER1, 0x40004f29 +.set CYREG_TMR3_CNT_CMP0, 0x40004f2a +.set CYREG_TMR3_CNT_CMP1, 0x40004f2b +.set CYREG_TMR3_CAP0, 0x40004f2c +.set CYREG_TMR3_CAP1, 0x40004f2d +.set CYREG_TMR3_RT0, 0x40004f2e +.set CYREG_TMR3_RT1, 0x40004f2f +.set CYDEV_IO_BASE, 0x40005000 +.set CYDEV_IO_SIZE, 0x00000200 +.set CYDEV_IO_PC_BASE, 0x40005000 +.set CYDEV_IO_PC_SIZE, 0x00000080 +.set CYDEV_IO_PC_PRT0_BASE, 0x40005000 +.set CYDEV_IO_PC_PRT0_SIZE, 0x00000008 +.set CYREG_PRT0_PC0, 0x40005000 +.set CYREG_PRT0_PC1, 0x40005001 +.set CYREG_PRT0_PC2, 0x40005002 +.set CYREG_PRT0_PC3, 0x40005003 +.set CYREG_PRT0_PC4, 0x40005004 +.set CYREG_PRT0_PC5, 0x40005005 +.set CYREG_PRT0_PC6, 0x40005006 +.set CYREG_PRT0_PC7, 0x40005007 +.set CYDEV_IO_PC_PRT1_BASE, 0x40005008 +.set CYDEV_IO_PC_PRT1_SIZE, 0x00000008 +.set CYREG_PRT1_PC0, 0x40005008 +.set CYREG_PRT1_PC1, 0x40005009 +.set CYREG_PRT1_PC2, 0x4000500a +.set CYREG_PRT1_PC3, 0x4000500b +.set CYREG_PRT1_PC4, 0x4000500c +.set CYREG_PRT1_PC5, 0x4000500d +.set CYREG_PRT1_PC6, 0x4000500e +.set CYREG_PRT1_PC7, 0x4000500f +.set CYDEV_IO_PC_PRT2_BASE, 0x40005010 +.set CYDEV_IO_PC_PRT2_SIZE, 0x00000008 +.set CYREG_PRT2_PC0, 0x40005010 +.set CYREG_PRT2_PC1, 0x40005011 +.set CYREG_PRT2_PC2, 0x40005012 +.set CYREG_PRT2_PC3, 0x40005013 +.set CYREG_PRT2_PC4, 0x40005014 +.set CYREG_PRT2_PC5, 0x40005015 +.set CYREG_PRT2_PC6, 0x40005016 +.set CYREG_PRT2_PC7, 0x40005017 +.set CYDEV_IO_PC_PRT3_BASE, 0x40005018 +.set CYDEV_IO_PC_PRT3_SIZE, 0x00000008 +.set CYREG_PRT3_PC0, 0x40005018 +.set CYREG_PRT3_PC1, 0x40005019 +.set CYREG_PRT3_PC2, 0x4000501a +.set CYREG_PRT3_PC3, 0x4000501b +.set CYREG_PRT3_PC4, 0x4000501c +.set CYREG_PRT3_PC5, 0x4000501d +.set CYREG_PRT3_PC6, 0x4000501e +.set CYREG_PRT3_PC7, 0x4000501f +.set CYDEV_IO_PC_PRT4_BASE, 0x40005020 +.set CYDEV_IO_PC_PRT4_SIZE, 0x00000008 +.set CYREG_PRT4_PC0, 0x40005020 +.set CYREG_PRT4_PC1, 0x40005021 +.set CYREG_PRT4_PC2, 0x40005022 +.set CYREG_PRT4_PC3, 0x40005023 +.set CYREG_PRT4_PC4, 0x40005024 +.set CYREG_PRT4_PC5, 0x40005025 +.set CYREG_PRT4_PC6, 0x40005026 +.set CYREG_PRT4_PC7, 0x40005027 +.set CYDEV_IO_PC_PRT5_BASE, 0x40005028 +.set CYDEV_IO_PC_PRT5_SIZE, 0x00000008 +.set CYREG_PRT5_PC0, 0x40005028 +.set CYREG_PRT5_PC1, 0x40005029 +.set CYREG_PRT5_PC2, 0x4000502a +.set CYREG_PRT5_PC3, 0x4000502b +.set CYREG_PRT5_PC4, 0x4000502c +.set CYREG_PRT5_PC5, 0x4000502d +.set CYREG_PRT5_PC6, 0x4000502e +.set CYREG_PRT5_PC7, 0x4000502f +.set CYDEV_IO_PC_PRT6_BASE, 0x40005030 +.set CYDEV_IO_PC_PRT6_SIZE, 0x00000008 +.set CYREG_PRT6_PC0, 0x40005030 +.set CYREG_PRT6_PC1, 0x40005031 +.set CYREG_PRT6_PC2, 0x40005032 +.set CYREG_PRT6_PC3, 0x40005033 +.set CYREG_PRT6_PC4, 0x40005034 +.set CYREG_PRT6_PC5, 0x40005035 +.set CYREG_PRT6_PC6, 0x40005036 +.set CYREG_PRT6_PC7, 0x40005037 +.set CYDEV_IO_PC_PRT12_BASE, 0x40005060 +.set CYDEV_IO_PC_PRT12_SIZE, 0x00000008 +.set CYREG_PRT12_PC0, 0x40005060 +.set CYREG_PRT12_PC1, 0x40005061 +.set CYREG_PRT12_PC2, 0x40005062 +.set CYREG_PRT12_PC3, 0x40005063 +.set CYREG_PRT12_PC4, 0x40005064 +.set CYREG_PRT12_PC5, 0x40005065 +.set CYREG_PRT12_PC6, 0x40005066 +.set CYREG_PRT12_PC7, 0x40005067 +.set CYDEV_IO_PC_PRT15_BASE, 0x40005078 +.set CYDEV_IO_PC_PRT15_SIZE, 0x00000006 +.set CYREG_IO_PC_PRT15_PC0, 0x40005078 +.set CYREG_IO_PC_PRT15_PC1, 0x40005079 +.set CYREG_IO_PC_PRT15_PC2, 0x4000507a +.set CYREG_IO_PC_PRT15_PC3, 0x4000507b +.set CYREG_IO_PC_PRT15_PC4, 0x4000507c +.set CYREG_IO_PC_PRT15_PC5, 0x4000507d +.set CYDEV_IO_PC_PRT15_7_6_BASE, 0x4000507e +.set CYDEV_IO_PC_PRT15_7_6_SIZE, 0x00000002 +.set CYREG_IO_PC_PRT15_7_6_PC0, 0x4000507e +.set CYREG_IO_PC_PRT15_7_6_PC1, 0x4000507f +.set CYDEV_IO_DR_BASE, 0x40005080 +.set CYDEV_IO_DR_SIZE, 0x00000010 +.set CYDEV_IO_DR_PRT0_BASE, 0x40005080 +.set CYDEV_IO_DR_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_DR_ALIAS, 0x40005080 +.set CYDEV_IO_DR_PRT1_BASE, 0x40005081 +.set CYDEV_IO_DR_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_DR_ALIAS, 0x40005081 +.set CYDEV_IO_DR_PRT2_BASE, 0x40005082 +.set CYDEV_IO_DR_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_DR_ALIAS, 0x40005082 +.set CYDEV_IO_DR_PRT3_BASE, 0x40005083 +.set CYDEV_IO_DR_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_DR_ALIAS, 0x40005083 +.set CYDEV_IO_DR_PRT4_BASE, 0x40005084 +.set CYDEV_IO_DR_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_DR_ALIAS, 0x40005084 +.set CYDEV_IO_DR_PRT5_BASE, 0x40005085 +.set CYDEV_IO_DR_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_DR_ALIAS, 0x40005085 +.set CYDEV_IO_DR_PRT6_BASE, 0x40005086 +.set CYDEV_IO_DR_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_DR_ALIAS, 0x40005086 +.set CYDEV_IO_DR_PRT12_BASE, 0x4000508c +.set CYDEV_IO_DR_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_DR_ALIAS, 0x4000508c +.set CYDEV_IO_DR_PRT15_BASE, 0x4000508f +.set CYDEV_IO_DR_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_DR_15_ALIAS, 0x4000508f +.set CYDEV_IO_PS_BASE, 0x40005090 +.set CYDEV_IO_PS_SIZE, 0x00000010 +.set CYDEV_IO_PS_PRT0_BASE, 0x40005090 +.set CYDEV_IO_PS_PRT0_SIZE, 0x00000001 +.set CYREG_PRT0_PS_ALIAS, 0x40005090 +.set CYDEV_IO_PS_PRT1_BASE, 0x40005091 +.set CYDEV_IO_PS_PRT1_SIZE, 0x00000001 +.set CYREG_PRT1_PS_ALIAS, 0x40005091 +.set CYDEV_IO_PS_PRT2_BASE, 0x40005092 +.set CYDEV_IO_PS_PRT2_SIZE, 0x00000001 +.set CYREG_PRT2_PS_ALIAS, 0x40005092 +.set CYDEV_IO_PS_PRT3_BASE, 0x40005093 +.set CYDEV_IO_PS_PRT3_SIZE, 0x00000001 +.set CYREG_PRT3_PS_ALIAS, 0x40005093 +.set CYDEV_IO_PS_PRT4_BASE, 0x40005094 +.set CYDEV_IO_PS_PRT4_SIZE, 0x00000001 +.set CYREG_PRT4_PS_ALIAS, 0x40005094 +.set CYDEV_IO_PS_PRT5_BASE, 0x40005095 +.set CYDEV_IO_PS_PRT5_SIZE, 0x00000001 +.set CYREG_PRT5_PS_ALIAS, 0x40005095 +.set CYDEV_IO_PS_PRT6_BASE, 0x40005096 +.set CYDEV_IO_PS_PRT6_SIZE, 0x00000001 +.set CYREG_PRT6_PS_ALIAS, 0x40005096 +.set CYDEV_IO_PS_PRT12_BASE, 0x4000509c +.set CYDEV_IO_PS_PRT12_SIZE, 0x00000001 +.set CYREG_PRT12_PS_ALIAS, 0x4000509c +.set CYDEV_IO_PS_PRT15_BASE, 0x4000509f +.set CYDEV_IO_PS_PRT15_SIZE, 0x00000001 +.set CYREG_PRT15_PS15_ALIAS, 0x4000509f +.set CYDEV_IO_PRT_BASE, 0x40005100 +.set CYDEV_IO_PRT_SIZE, 0x00000100 +.set CYDEV_IO_PRT_PRT0_BASE, 0x40005100 +.set CYDEV_IO_PRT_PRT0_SIZE, 0x00000010 +.set CYREG_PRT0_DR, 0x40005100 +.set CYREG_PRT0_PS, 0x40005101 +.set CYREG_PRT0_DM0, 0x40005102 +.set CYREG_PRT0_DM1, 0x40005103 +.set CYREG_PRT0_DM2, 0x40005104 +.set CYREG_PRT0_SLW, 0x40005105 +.set CYREG_PRT0_BYP, 0x40005106 +.set CYREG_PRT0_BIE, 0x40005107 +.set CYREG_PRT0_INP_DIS, 0x40005108 +.set CYREG_PRT0_CTL, 0x40005109 +.set CYREG_PRT0_PRT, 0x4000510a +.set CYREG_PRT0_BIT_MASK, 0x4000510b +.set CYREG_PRT0_AMUX, 0x4000510c +.set CYREG_PRT0_AG, 0x4000510d +.set CYREG_PRT0_LCD_COM_SEG, 0x4000510e +.set CYREG_PRT0_LCD_EN, 0x4000510f +.set CYDEV_IO_PRT_PRT1_BASE, 0x40005110 +.set CYDEV_IO_PRT_PRT1_SIZE, 0x00000010 +.set CYREG_PRT1_DR, 0x40005110 +.set CYREG_PRT1_PS, 0x40005111 +.set CYREG_PRT1_DM0, 0x40005112 +.set CYREG_PRT1_DM1, 0x40005113 +.set CYREG_PRT1_DM2, 0x40005114 +.set CYREG_PRT1_SLW, 0x40005115 +.set CYREG_PRT1_BYP, 0x40005116 +.set CYREG_PRT1_BIE, 0x40005117 +.set CYREG_PRT1_INP_DIS, 0x40005118 +.set CYREG_PRT1_CTL, 0x40005119 +.set CYREG_PRT1_PRT, 0x4000511a +.set CYREG_PRT1_BIT_MASK, 0x4000511b +.set CYREG_PRT1_AMUX, 0x4000511c +.set CYREG_PRT1_AG, 0x4000511d +.set CYREG_PRT1_LCD_COM_SEG, 0x4000511e +.set CYREG_PRT1_LCD_EN, 0x4000511f +.set CYDEV_IO_PRT_PRT2_BASE, 0x40005120 +.set CYDEV_IO_PRT_PRT2_SIZE, 0x00000010 +.set CYREG_PRT2_DR, 0x40005120 +.set CYREG_PRT2_PS, 0x40005121 +.set CYREG_PRT2_DM0, 0x40005122 +.set CYREG_PRT2_DM1, 0x40005123 +.set CYREG_PRT2_DM2, 0x40005124 +.set CYREG_PRT2_SLW, 0x40005125 +.set CYREG_PRT2_BYP, 0x40005126 +.set CYREG_PRT2_BIE, 0x40005127 +.set CYREG_PRT2_INP_DIS, 0x40005128 +.set CYREG_PRT2_CTL, 0x40005129 +.set CYREG_PRT2_PRT, 0x4000512a +.set CYREG_PRT2_BIT_MASK, 0x4000512b +.set CYREG_PRT2_AMUX, 0x4000512c +.set CYREG_PRT2_AG, 0x4000512d +.set CYREG_PRT2_LCD_COM_SEG, 0x4000512e +.set CYREG_PRT2_LCD_EN, 0x4000512f +.set CYDEV_IO_PRT_PRT3_BASE, 0x40005130 +.set CYDEV_IO_PRT_PRT3_SIZE, 0x00000010 +.set CYREG_PRT3_DR, 0x40005130 +.set CYREG_PRT3_PS, 0x40005131 +.set CYREG_PRT3_DM0, 0x40005132 +.set CYREG_PRT3_DM1, 0x40005133 +.set CYREG_PRT3_DM2, 0x40005134 +.set CYREG_PRT3_SLW, 0x40005135 +.set CYREG_PRT3_BYP, 0x40005136 +.set CYREG_PRT3_BIE, 0x40005137 +.set CYREG_PRT3_INP_DIS, 0x40005138 +.set CYREG_PRT3_CTL, 0x40005139 +.set CYREG_PRT3_PRT, 0x4000513a +.set CYREG_PRT3_BIT_MASK, 0x4000513b +.set CYREG_PRT3_AMUX, 0x4000513c +.set CYREG_PRT3_AG, 0x4000513d +.set CYREG_PRT3_LCD_COM_SEG, 0x4000513e +.set CYREG_PRT3_LCD_EN, 0x4000513f +.set CYDEV_IO_PRT_PRT4_BASE, 0x40005140 +.set CYDEV_IO_PRT_PRT4_SIZE, 0x00000010 +.set CYREG_PRT4_DR, 0x40005140 +.set CYREG_PRT4_PS, 0x40005141 +.set CYREG_PRT4_DM0, 0x40005142 +.set CYREG_PRT4_DM1, 0x40005143 +.set CYREG_PRT4_DM2, 0x40005144 +.set CYREG_PRT4_SLW, 0x40005145 +.set CYREG_PRT4_BYP, 0x40005146 +.set CYREG_PRT4_BIE, 0x40005147 +.set CYREG_PRT4_INP_DIS, 0x40005148 +.set CYREG_PRT4_CTL, 0x40005149 +.set CYREG_PRT4_PRT, 0x4000514a +.set CYREG_PRT4_BIT_MASK, 0x4000514b +.set CYREG_PRT4_AMUX, 0x4000514c +.set CYREG_PRT4_AG, 0x4000514d +.set CYREG_PRT4_LCD_COM_SEG, 0x4000514e +.set CYREG_PRT4_LCD_EN, 0x4000514f +.set CYDEV_IO_PRT_PRT5_BASE, 0x40005150 +.set CYDEV_IO_PRT_PRT5_SIZE, 0x00000010 +.set CYREG_PRT5_DR, 0x40005150 +.set CYREG_PRT5_PS, 0x40005151 +.set CYREG_PRT5_DM0, 0x40005152 +.set CYREG_PRT5_DM1, 0x40005153 +.set CYREG_PRT5_DM2, 0x40005154 +.set CYREG_PRT5_SLW, 0x40005155 +.set CYREG_PRT5_BYP, 0x40005156 +.set CYREG_PRT5_BIE, 0x40005157 +.set CYREG_PRT5_INP_DIS, 0x40005158 +.set CYREG_PRT5_CTL, 0x40005159 +.set CYREG_PRT5_PRT, 0x4000515a +.set CYREG_PRT5_BIT_MASK, 0x4000515b +.set CYREG_PRT5_AMUX, 0x4000515c +.set CYREG_PRT5_AG, 0x4000515d +.set CYREG_PRT5_LCD_COM_SEG, 0x4000515e +.set CYREG_PRT5_LCD_EN, 0x4000515f +.set CYDEV_IO_PRT_PRT6_BASE, 0x40005160 +.set CYDEV_IO_PRT_PRT6_SIZE, 0x00000010 +.set CYREG_PRT6_DR, 0x40005160 +.set CYREG_PRT6_PS, 0x40005161 +.set CYREG_PRT6_DM0, 0x40005162 +.set CYREG_PRT6_DM1, 0x40005163 +.set CYREG_PRT6_DM2, 0x40005164 +.set CYREG_PRT6_SLW, 0x40005165 +.set CYREG_PRT6_BYP, 0x40005166 +.set CYREG_PRT6_BIE, 0x40005167 +.set CYREG_PRT6_INP_DIS, 0x40005168 +.set CYREG_PRT6_CTL, 0x40005169 +.set CYREG_PRT6_PRT, 0x4000516a +.set CYREG_PRT6_BIT_MASK, 0x4000516b +.set CYREG_PRT6_AMUX, 0x4000516c +.set CYREG_PRT6_AG, 0x4000516d +.set CYREG_PRT6_LCD_COM_SEG, 0x4000516e +.set CYREG_PRT6_LCD_EN, 0x4000516f +.set CYDEV_IO_PRT_PRT12_BASE, 0x400051c0 +.set CYDEV_IO_PRT_PRT12_SIZE, 0x00000010 +.set CYREG_PRT12_DR, 0x400051c0 +.set CYREG_PRT12_PS, 0x400051c1 +.set CYREG_PRT12_DM0, 0x400051c2 +.set CYREG_PRT12_DM1, 0x400051c3 +.set CYREG_PRT12_DM2, 0x400051c4 +.set CYREG_PRT12_SLW, 0x400051c5 +.set CYREG_PRT12_BYP, 0x400051c6 +.set CYREG_PRT12_BIE, 0x400051c7 +.set CYREG_PRT12_INP_DIS, 0x400051c8 +.set CYREG_PRT12_SIO_HYST_EN, 0x400051c9 +.set CYREG_PRT12_PRT, 0x400051ca +.set CYREG_PRT12_BIT_MASK, 0x400051cb +.set CYREG_PRT12_SIO_REG_HIFREQ, 0x400051cc +.set CYREG_PRT12_AG, 0x400051cd +.set CYREG_PRT12_SIO_CFG, 0x400051ce +.set CYREG_PRT12_SIO_DIFF, 0x400051cf +.set CYDEV_IO_PRT_PRT15_BASE, 0x400051f0 +.set CYDEV_IO_PRT_PRT15_SIZE, 0x00000010 +.set CYREG_PRT15_DR, 0x400051f0 +.set CYREG_PRT15_PS, 0x400051f1 +.set CYREG_PRT15_DM0, 0x400051f2 +.set CYREG_PRT15_DM1, 0x400051f3 +.set CYREG_PRT15_DM2, 0x400051f4 +.set CYREG_PRT15_SLW, 0x400051f5 +.set CYREG_PRT15_BYP, 0x400051f6 +.set CYREG_PRT15_BIE, 0x400051f7 +.set CYREG_PRT15_INP_DIS, 0x400051f8 +.set CYREG_PRT15_CTL, 0x400051f9 +.set CYREG_PRT15_PRT, 0x400051fa +.set CYREG_PRT15_BIT_MASK, 0x400051fb +.set CYREG_PRT15_AMUX, 0x400051fc +.set CYREG_PRT15_AG, 0x400051fd +.set CYREG_PRT15_LCD_COM_SEG, 0x400051fe +.set CYREG_PRT15_LCD_EN, 0x400051ff +.set CYDEV_PRTDSI_BASE, 0x40005200 +.set CYDEV_PRTDSI_SIZE, 0x0000007f +.set CYDEV_PRTDSI_PRT0_BASE, 0x40005200 +.set CYDEV_PRTDSI_PRT0_SIZE, 0x00000007 +.set CYREG_PRT0_OUT_SEL0, 0x40005200 +.set CYREG_PRT0_OUT_SEL1, 0x40005201 +.set CYREG_PRT0_OE_SEL0, 0x40005202 +.set CYREG_PRT0_OE_SEL1, 0x40005203 +.set CYREG_PRT0_DBL_SYNC_IN, 0x40005204 +.set CYREG_PRT0_SYNC_OUT, 0x40005205 +.set CYREG_PRT0_CAPS_SEL, 0x40005206 +.set CYDEV_PRTDSI_PRT1_BASE, 0x40005208 +.set CYDEV_PRTDSI_PRT1_SIZE, 0x00000007 +.set CYREG_PRT1_OUT_SEL0, 0x40005208 +.set CYREG_PRT1_OUT_SEL1, 0x40005209 +.set CYREG_PRT1_OE_SEL0, 0x4000520a +.set CYREG_PRT1_OE_SEL1, 0x4000520b +.set CYREG_PRT1_DBL_SYNC_IN, 0x4000520c +.set CYREG_PRT1_SYNC_OUT, 0x4000520d +.set CYREG_PRT1_CAPS_SEL, 0x4000520e +.set CYDEV_PRTDSI_PRT2_BASE, 0x40005210 +.set CYDEV_PRTDSI_PRT2_SIZE, 0x00000007 +.set CYREG_PRT2_OUT_SEL0, 0x40005210 +.set CYREG_PRT2_OUT_SEL1, 0x40005211 +.set CYREG_PRT2_OE_SEL0, 0x40005212 +.set CYREG_PRT2_OE_SEL1, 0x40005213 +.set CYREG_PRT2_DBL_SYNC_IN, 0x40005214 +.set CYREG_PRT2_SYNC_OUT, 0x40005215 +.set CYREG_PRT2_CAPS_SEL, 0x40005216 +.set CYDEV_PRTDSI_PRT3_BASE, 0x40005218 +.set CYDEV_PRTDSI_PRT3_SIZE, 0x00000007 +.set CYREG_PRT3_OUT_SEL0, 0x40005218 +.set CYREG_PRT3_OUT_SEL1, 0x40005219 +.set CYREG_PRT3_OE_SEL0, 0x4000521a +.set CYREG_PRT3_OE_SEL1, 0x4000521b +.set CYREG_PRT3_DBL_SYNC_IN, 0x4000521c +.set CYREG_PRT3_SYNC_OUT, 0x4000521d +.set CYREG_PRT3_CAPS_SEL, 0x4000521e +.set CYDEV_PRTDSI_PRT4_BASE, 0x40005220 +.set CYDEV_PRTDSI_PRT4_SIZE, 0x00000007 +.set CYREG_PRT4_OUT_SEL0, 0x40005220 +.set CYREG_PRT4_OUT_SEL1, 0x40005221 +.set CYREG_PRT4_OE_SEL0, 0x40005222 +.set CYREG_PRT4_OE_SEL1, 0x40005223 +.set CYREG_PRT4_DBL_SYNC_IN, 0x40005224 +.set CYREG_PRT4_SYNC_OUT, 0x40005225 +.set CYREG_PRT4_CAPS_SEL, 0x40005226 +.set CYDEV_PRTDSI_PRT5_BASE, 0x40005228 +.set CYDEV_PRTDSI_PRT5_SIZE, 0x00000007 +.set CYREG_PRT5_OUT_SEL0, 0x40005228 +.set CYREG_PRT5_OUT_SEL1, 0x40005229 +.set CYREG_PRT5_OE_SEL0, 0x4000522a +.set CYREG_PRT5_OE_SEL1, 0x4000522b +.set CYREG_PRT5_DBL_SYNC_IN, 0x4000522c +.set CYREG_PRT5_SYNC_OUT, 0x4000522d +.set CYREG_PRT5_CAPS_SEL, 0x4000522e +.set CYDEV_PRTDSI_PRT6_BASE, 0x40005230 +.set CYDEV_PRTDSI_PRT6_SIZE, 0x00000007 +.set CYREG_PRT6_OUT_SEL0, 0x40005230 +.set CYREG_PRT6_OUT_SEL1, 0x40005231 +.set CYREG_PRT6_OE_SEL0, 0x40005232 +.set CYREG_PRT6_OE_SEL1, 0x40005233 +.set CYREG_PRT6_DBL_SYNC_IN, 0x40005234 +.set CYREG_PRT6_SYNC_OUT, 0x40005235 +.set CYREG_PRT6_CAPS_SEL, 0x40005236 +.set CYDEV_PRTDSI_PRT12_BASE, 0x40005260 +.set CYDEV_PRTDSI_PRT12_SIZE, 0x00000006 +.set CYREG_PRT12_OUT_SEL0, 0x40005260 +.set CYREG_PRT12_OUT_SEL1, 0x40005261 +.set CYREG_PRT12_OE_SEL0, 0x40005262 +.set CYREG_PRT12_OE_SEL1, 0x40005263 +.set CYREG_PRT12_DBL_SYNC_IN, 0x40005264 +.set CYREG_PRT12_SYNC_OUT, 0x40005265 +.set CYDEV_PRTDSI_PRT15_BASE, 0x40005278 +.set CYDEV_PRTDSI_PRT15_SIZE, 0x00000007 +.set CYREG_PRT15_OUT_SEL0, 0x40005278 +.set CYREG_PRT15_OUT_SEL1, 0x40005279 +.set CYREG_PRT15_OE_SEL0, 0x4000527a +.set CYREG_PRT15_OE_SEL1, 0x4000527b +.set CYREG_PRT15_DBL_SYNC_IN, 0x4000527c +.set CYREG_PRT15_SYNC_OUT, 0x4000527d +.set CYREG_PRT15_CAPS_SEL, 0x4000527e +.set CYDEV_EMIF_BASE, 0x40005400 +.set CYDEV_EMIF_SIZE, 0x00000007 +.set CYREG_EMIF_NO_UDB, 0x40005400 +.set CYREG_EMIF_RP_WAIT_STATES, 0x40005401 +.set CYREG_EMIF_MEM_DWN, 0x40005402 +.set CYREG_EMIF_MEMCLK_DIV, 0x40005403 +.set CYREG_EMIF_CLOCK_EN, 0x40005404 +.set CYREG_EMIF_EM_TYPE, 0x40005405 +.set CYREG_EMIF_WP_WAIT_STATES, 0x40005406 +.set CYDEV_ANAIF_BASE, 0x40005800 +.set CYDEV_ANAIF_SIZE, 0x000003a9 +.set CYDEV_ANAIF_CFG_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SIZE, 0x0000010f +.set CYDEV_ANAIF_CFG_SC0_BASE, 0x40005800 +.set CYDEV_ANAIF_CFG_SC0_SIZE, 0x00000003 +.set CYREG_SC0_CR0, 0x40005800 +.set CYREG_SC0_CR1, 0x40005801 +.set CYREG_SC0_CR2, 0x40005802 +.set CYDEV_ANAIF_CFG_SC1_BASE, 0x40005804 +.set CYDEV_ANAIF_CFG_SC1_SIZE, 0x00000003 +.set CYREG_SC1_CR0, 0x40005804 +.set CYREG_SC1_CR1, 0x40005805 +.set CYREG_SC1_CR2, 0x40005806 +.set CYDEV_ANAIF_CFG_SC2_BASE, 0x40005808 +.set CYDEV_ANAIF_CFG_SC2_SIZE, 0x00000003 +.set CYREG_SC2_CR0, 0x40005808 +.set CYREG_SC2_CR1, 0x40005809 +.set CYREG_SC2_CR2, 0x4000580a +.set CYDEV_ANAIF_CFG_SC3_BASE, 0x4000580c +.set CYDEV_ANAIF_CFG_SC3_SIZE, 0x00000003 +.set CYREG_SC3_CR0, 0x4000580c +.set CYREG_SC3_CR1, 0x4000580d +.set CYREG_SC3_CR2, 0x4000580e +.set CYDEV_ANAIF_CFG_DAC0_BASE, 0x40005820 +.set CYDEV_ANAIF_CFG_DAC0_SIZE, 0x00000003 +.set CYREG_DAC0_CR0, 0x40005820 +.set CYREG_DAC0_CR1, 0x40005821 +.set CYREG_DAC0_TST, 0x40005822 +.set CYDEV_ANAIF_CFG_DAC1_BASE, 0x40005824 +.set CYDEV_ANAIF_CFG_DAC1_SIZE, 0x00000003 +.set CYREG_DAC1_CR0, 0x40005824 +.set CYREG_DAC1_CR1, 0x40005825 +.set CYREG_DAC1_TST, 0x40005826 +.set CYDEV_ANAIF_CFG_DAC2_BASE, 0x40005828 +.set CYDEV_ANAIF_CFG_DAC2_SIZE, 0x00000003 +.set CYREG_DAC2_CR0, 0x40005828 +.set CYREG_DAC2_CR1, 0x40005829 +.set CYREG_DAC2_TST, 0x4000582a +.set CYDEV_ANAIF_CFG_DAC3_BASE, 0x4000582c +.set CYDEV_ANAIF_CFG_DAC3_SIZE, 0x00000003 +.set CYREG_DAC3_CR0, 0x4000582c +.set CYREG_DAC3_CR1, 0x4000582d +.set CYREG_DAC3_TST, 0x4000582e +.set CYDEV_ANAIF_CFG_CMP0_BASE, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP0_SIZE, 0x00000001 +.set CYREG_CMP0_CR, 0x40005840 +.set CYDEV_ANAIF_CFG_CMP1_BASE, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP1_SIZE, 0x00000001 +.set CYREG_CMP1_CR, 0x40005841 +.set CYDEV_ANAIF_CFG_CMP2_BASE, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP2_SIZE, 0x00000001 +.set CYREG_CMP2_CR, 0x40005842 +.set CYDEV_ANAIF_CFG_CMP3_BASE, 0x40005843 +.set CYDEV_ANAIF_CFG_CMP3_SIZE, 0x00000001 +.set CYREG_CMP3_CR, 0x40005843 +.set CYDEV_ANAIF_CFG_LUT0_BASE, 0x40005848 +.set CYDEV_ANAIF_CFG_LUT0_SIZE, 0x00000002 +.set CYREG_LUT0_CR, 0x40005848 +.set CYREG_LUT0_MX, 0x40005849 +.set CYDEV_ANAIF_CFG_LUT1_BASE, 0x4000584a +.set CYDEV_ANAIF_CFG_LUT1_SIZE, 0x00000002 +.set CYREG_LUT1_CR, 0x4000584a +.set CYREG_LUT1_MX, 0x4000584b +.set CYDEV_ANAIF_CFG_LUT2_BASE, 0x4000584c +.set CYDEV_ANAIF_CFG_LUT2_SIZE, 0x00000002 +.set CYREG_LUT2_CR, 0x4000584c +.set CYREG_LUT2_MX, 0x4000584d +.set CYDEV_ANAIF_CFG_LUT3_BASE, 0x4000584e +.set CYDEV_ANAIF_CFG_LUT3_SIZE, 0x00000002 +.set CYREG_LUT3_CR, 0x4000584e +.set CYREG_LUT3_MX, 0x4000584f +.set CYDEV_ANAIF_CFG_OPAMP0_BASE, 0x40005858 +.set CYDEV_ANAIF_CFG_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_CR, 0x40005858 +.set CYREG_OPAMP0_RSVD, 0x40005859 +.set CYDEV_ANAIF_CFG_OPAMP1_BASE, 0x4000585a +.set CYDEV_ANAIF_CFG_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_CR, 0x4000585a +.set CYREG_OPAMP1_RSVD, 0x4000585b +.set CYDEV_ANAIF_CFG_OPAMP2_BASE, 0x4000585c +.set CYDEV_ANAIF_CFG_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_CR, 0x4000585c +.set CYREG_OPAMP2_RSVD, 0x4000585d +.set CYDEV_ANAIF_CFG_OPAMP3_BASE, 0x4000585e +.set CYDEV_ANAIF_CFG_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_CR, 0x4000585e +.set CYREG_OPAMP3_RSVD, 0x4000585f +.set CYDEV_ANAIF_CFG_LCDDAC_BASE, 0x40005868 +.set CYDEV_ANAIF_CFG_LCDDAC_SIZE, 0x00000002 +.set CYREG_LCDDAC_CR0, 0x40005868 +.set CYREG_LCDDAC_CR1, 0x40005869 +.set CYDEV_ANAIF_CFG_LCDDRV_BASE, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDDRV_SIZE, 0x00000001 +.set CYREG_LCDDRV_CR, 0x4000586a +.set CYDEV_ANAIF_CFG_LCDTMR_BASE, 0x4000586b +.set CYDEV_ANAIF_CFG_LCDTMR_SIZE, 0x00000001 +.set CYREG_LCDTMR_CFG, 0x4000586b +.set CYDEV_ANAIF_CFG_BG_BASE, 0x4000586c +.set CYDEV_ANAIF_CFG_BG_SIZE, 0x00000004 +.set CYREG_BG_CR0, 0x4000586c +.set CYREG_BG_RSVD, 0x4000586d +.set CYREG_BG_DFT0, 0x4000586e +.set CYREG_BG_DFT1, 0x4000586f +.set CYDEV_ANAIF_CFG_CAPSL_BASE, 0x40005870 +.set CYDEV_ANAIF_CFG_CAPSL_SIZE, 0x00000002 +.set CYREG_CAPSL_CFG0, 0x40005870 +.set CYREG_CAPSL_CFG1, 0x40005871 +.set CYDEV_ANAIF_CFG_CAPSR_BASE, 0x40005872 +.set CYDEV_ANAIF_CFG_CAPSR_SIZE, 0x00000002 +.set CYREG_CAPSR_CFG0, 0x40005872 +.set CYREG_CAPSR_CFG1, 0x40005873 +.set CYDEV_ANAIF_CFG_PUMP_BASE, 0x40005876 +.set CYDEV_ANAIF_CFG_PUMP_SIZE, 0x00000002 +.set CYREG_PUMP_CR0, 0x40005876 +.set CYREG_PUMP_CR1, 0x40005877 +.set CYDEV_ANAIF_CFG_LPF0_BASE, 0x40005878 +.set CYDEV_ANAIF_CFG_LPF0_SIZE, 0x00000002 +.set CYREG_LPF0_CR0, 0x40005878 +.set CYREG_LPF0_RSVD, 0x40005879 +.set CYDEV_ANAIF_CFG_LPF1_BASE, 0x4000587a +.set CYDEV_ANAIF_CFG_LPF1_SIZE, 0x00000002 +.set CYREG_LPF1_CR0, 0x4000587a +.set CYREG_LPF1_RSVD, 0x4000587b +.set CYDEV_ANAIF_CFG_MISC_BASE, 0x4000587c +.set CYDEV_ANAIF_CFG_MISC_SIZE, 0x00000001 +.set CYREG_ANAIF_CFG_MISC_CR0, 0x4000587c +.set CYDEV_ANAIF_CFG_DSM0_BASE, 0x40005880 +.set CYDEV_ANAIF_CFG_DSM0_SIZE, 0x00000020 +.set CYREG_DSM0_CR0, 0x40005880 +.set CYREG_DSM0_CR1, 0x40005881 +.set CYREG_DSM0_CR2, 0x40005882 +.set CYREG_DSM0_CR3, 0x40005883 +.set CYREG_DSM0_CR4, 0x40005884 +.set CYREG_DSM0_CR5, 0x40005885 +.set CYREG_DSM0_CR6, 0x40005886 +.set CYREG_DSM0_CR7, 0x40005887 +.set CYREG_DSM0_CR8, 0x40005888 +.set CYREG_DSM0_CR9, 0x40005889 +.set CYREG_DSM0_CR10, 0x4000588a +.set CYREG_DSM0_CR11, 0x4000588b +.set CYREG_DSM0_CR12, 0x4000588c +.set CYREG_DSM0_CR13, 0x4000588d +.set CYREG_DSM0_CR14, 0x4000588e +.set CYREG_DSM0_CR15, 0x4000588f +.set CYREG_DSM0_CR16, 0x40005890 +.set CYREG_DSM0_CR17, 0x40005891 +.set CYREG_DSM0_REF0, 0x40005892 +.set CYREG_DSM0_REF1, 0x40005893 +.set CYREG_DSM0_REF2, 0x40005894 +.set CYREG_DSM0_REF3, 0x40005895 +.set CYREG_DSM0_DEM0, 0x40005896 +.set CYREG_DSM0_DEM1, 0x40005897 +.set CYREG_DSM0_TST0, 0x40005898 +.set CYREG_DSM0_TST1, 0x40005899 +.set CYREG_DSM0_BUF0, 0x4000589a +.set CYREG_DSM0_BUF1, 0x4000589b +.set CYREG_DSM0_BUF2, 0x4000589c +.set CYREG_DSM0_BUF3, 0x4000589d +.set CYREG_DSM0_MISC, 0x4000589e +.set CYREG_DSM0_RSVD1, 0x4000589f +.set CYDEV_ANAIF_CFG_SAR0_BASE, 0x40005900 +.set CYDEV_ANAIF_CFG_SAR0_SIZE, 0x00000007 +.set CYREG_SAR0_CSR0, 0x40005900 +.set CYREG_SAR0_CSR1, 0x40005901 +.set CYREG_SAR0_CSR2, 0x40005902 +.set CYREG_SAR0_CSR3, 0x40005903 +.set CYREG_SAR0_CSR4, 0x40005904 +.set CYREG_SAR0_CSR5, 0x40005905 +.set CYREG_SAR0_CSR6, 0x40005906 +.set CYDEV_ANAIF_CFG_SAR1_BASE, 0x40005908 +.set CYDEV_ANAIF_CFG_SAR1_SIZE, 0x00000007 +.set CYREG_SAR1_CSR0, 0x40005908 +.set CYREG_SAR1_CSR1, 0x40005909 +.set CYREG_SAR1_CSR2, 0x4000590a +.set CYREG_SAR1_CSR3, 0x4000590b +.set CYREG_SAR1_CSR4, 0x4000590c +.set CYREG_SAR1_CSR5, 0x4000590d +.set CYREG_SAR1_CSR6, 0x4000590e +.set CYDEV_ANAIF_RT_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SIZE, 0x00000162 +.set CYDEV_ANAIF_RT_SC0_BASE, 0x40005a00 +.set CYDEV_ANAIF_RT_SC0_SIZE, 0x0000000d +.set CYREG_SC0_SW0, 0x40005a00 +.set CYREG_SC0_SW2, 0x40005a02 +.set CYREG_SC0_SW3, 0x40005a03 +.set CYREG_SC0_SW4, 0x40005a04 +.set CYREG_SC0_SW6, 0x40005a06 +.set CYREG_SC0_SW7, 0x40005a07 +.set CYREG_SC0_SW8, 0x40005a08 +.set CYREG_SC0_SW10, 0x40005a0a +.set CYREG_SC0_CLK, 0x40005a0b +.set CYREG_SC0_BST, 0x40005a0c +.set CYDEV_ANAIF_RT_SC1_BASE, 0x40005a10 +.set CYDEV_ANAIF_RT_SC1_SIZE, 0x0000000d +.set CYREG_SC1_SW0, 0x40005a10 +.set CYREG_SC1_SW2, 0x40005a12 +.set CYREG_SC1_SW3, 0x40005a13 +.set CYREG_SC1_SW4, 0x40005a14 +.set CYREG_SC1_SW6, 0x40005a16 +.set CYREG_SC1_SW7, 0x40005a17 +.set CYREG_SC1_SW8, 0x40005a18 +.set CYREG_SC1_SW10, 0x40005a1a +.set CYREG_SC1_CLK, 0x40005a1b +.set CYREG_SC1_BST, 0x40005a1c +.set CYDEV_ANAIF_RT_SC2_BASE, 0x40005a20 +.set CYDEV_ANAIF_RT_SC2_SIZE, 0x0000000d +.set CYREG_SC2_SW0, 0x40005a20 +.set CYREG_SC2_SW2, 0x40005a22 +.set CYREG_SC2_SW3, 0x40005a23 +.set CYREG_SC2_SW4, 0x40005a24 +.set CYREG_SC2_SW6, 0x40005a26 +.set CYREG_SC2_SW7, 0x40005a27 +.set CYREG_SC2_SW8, 0x40005a28 +.set CYREG_SC2_SW10, 0x40005a2a +.set CYREG_SC2_CLK, 0x40005a2b +.set CYREG_SC2_BST, 0x40005a2c +.set CYDEV_ANAIF_RT_SC3_BASE, 0x40005a30 +.set CYDEV_ANAIF_RT_SC3_SIZE, 0x0000000d +.set CYREG_SC3_SW0, 0x40005a30 +.set CYREG_SC3_SW2, 0x40005a32 +.set CYREG_SC3_SW3, 0x40005a33 +.set CYREG_SC3_SW4, 0x40005a34 +.set CYREG_SC3_SW6, 0x40005a36 +.set CYREG_SC3_SW7, 0x40005a37 +.set CYREG_SC3_SW8, 0x40005a38 +.set CYREG_SC3_SW10, 0x40005a3a +.set CYREG_SC3_CLK, 0x40005a3b +.set CYREG_SC3_BST, 0x40005a3c +.set CYDEV_ANAIF_RT_DAC0_BASE, 0x40005a80 +.set CYDEV_ANAIF_RT_DAC0_SIZE, 0x00000008 +.set CYREG_DAC0_SW0, 0x40005a80 +.set CYREG_DAC0_SW2, 0x40005a82 +.set CYREG_DAC0_SW3, 0x40005a83 +.set CYREG_DAC0_SW4, 0x40005a84 +.set CYREG_DAC0_STROBE, 0x40005a87 +.set CYDEV_ANAIF_RT_DAC1_BASE, 0x40005a88 +.set CYDEV_ANAIF_RT_DAC1_SIZE, 0x00000008 +.set CYREG_DAC1_SW0, 0x40005a88 +.set CYREG_DAC1_SW2, 0x40005a8a +.set CYREG_DAC1_SW3, 0x40005a8b +.set CYREG_DAC1_SW4, 0x40005a8c +.set CYREG_DAC1_STROBE, 0x40005a8f +.set CYDEV_ANAIF_RT_DAC2_BASE, 0x40005a90 +.set CYDEV_ANAIF_RT_DAC2_SIZE, 0x00000008 +.set CYREG_DAC2_SW0, 0x40005a90 +.set CYREG_DAC2_SW2, 0x40005a92 +.set CYREG_DAC2_SW3, 0x40005a93 +.set CYREG_DAC2_SW4, 0x40005a94 +.set CYREG_DAC2_STROBE, 0x40005a97 +.set CYDEV_ANAIF_RT_DAC3_BASE, 0x40005a98 +.set CYDEV_ANAIF_RT_DAC3_SIZE, 0x00000008 +.set CYREG_DAC3_SW0, 0x40005a98 +.set CYREG_DAC3_SW2, 0x40005a9a +.set CYREG_DAC3_SW3, 0x40005a9b +.set CYREG_DAC3_SW4, 0x40005a9c +.set CYREG_DAC3_STROBE, 0x40005a9f +.set CYDEV_ANAIF_RT_CMP0_BASE, 0x40005ac0 +.set CYDEV_ANAIF_RT_CMP0_SIZE, 0x00000008 +.set CYREG_CMP0_SW0, 0x40005ac0 +.set CYREG_CMP0_SW2, 0x40005ac2 +.set CYREG_CMP0_SW3, 0x40005ac3 +.set CYREG_CMP0_SW4, 0x40005ac4 +.set CYREG_CMP0_SW6, 0x40005ac6 +.set CYREG_CMP0_CLK, 0x40005ac7 +.set CYDEV_ANAIF_RT_CMP1_BASE, 0x40005ac8 +.set CYDEV_ANAIF_RT_CMP1_SIZE, 0x00000008 +.set CYREG_CMP1_SW0, 0x40005ac8 +.set CYREG_CMP1_SW2, 0x40005aca +.set CYREG_CMP1_SW3, 0x40005acb +.set CYREG_CMP1_SW4, 0x40005acc +.set CYREG_CMP1_SW6, 0x40005ace +.set CYREG_CMP1_CLK, 0x40005acf +.set CYDEV_ANAIF_RT_CMP2_BASE, 0x40005ad0 +.set CYDEV_ANAIF_RT_CMP2_SIZE, 0x00000008 +.set CYREG_CMP2_SW0, 0x40005ad0 +.set CYREG_CMP2_SW2, 0x40005ad2 +.set CYREG_CMP2_SW3, 0x40005ad3 +.set CYREG_CMP2_SW4, 0x40005ad4 +.set CYREG_CMP2_SW6, 0x40005ad6 +.set CYREG_CMP2_CLK, 0x40005ad7 +.set CYDEV_ANAIF_RT_CMP3_BASE, 0x40005ad8 +.set CYDEV_ANAIF_RT_CMP3_SIZE, 0x00000008 +.set CYREG_CMP3_SW0, 0x40005ad8 +.set CYREG_CMP3_SW2, 0x40005ada +.set CYREG_CMP3_SW3, 0x40005adb +.set CYREG_CMP3_SW4, 0x40005adc +.set CYREG_CMP3_SW6, 0x40005ade +.set CYREG_CMP3_CLK, 0x40005adf +.set CYDEV_ANAIF_RT_DSM0_BASE, 0x40005b00 +.set CYDEV_ANAIF_RT_DSM0_SIZE, 0x00000008 +.set CYREG_DSM0_SW0, 0x40005b00 +.set CYREG_DSM0_SW2, 0x40005b02 +.set CYREG_DSM0_SW3, 0x40005b03 +.set CYREG_DSM0_SW4, 0x40005b04 +.set CYREG_DSM0_SW6, 0x40005b06 +.set CYREG_DSM0_CLK, 0x40005b07 +.set CYDEV_ANAIF_RT_SAR0_BASE, 0x40005b20 +.set CYDEV_ANAIF_RT_SAR0_SIZE, 0x00000008 +.set CYREG_SAR0_SW0, 0x40005b20 +.set CYREG_SAR0_SW2, 0x40005b22 +.set CYREG_SAR0_SW3, 0x40005b23 +.set CYREG_SAR0_SW4, 0x40005b24 +.set CYREG_SAR0_SW6, 0x40005b26 +.set CYREG_SAR0_CLK, 0x40005b27 +.set CYDEV_ANAIF_RT_SAR1_BASE, 0x40005b28 +.set CYDEV_ANAIF_RT_SAR1_SIZE, 0x00000008 +.set CYREG_SAR1_SW0, 0x40005b28 +.set CYREG_SAR1_SW2, 0x40005b2a +.set CYREG_SAR1_SW3, 0x40005b2b +.set CYREG_SAR1_SW4, 0x40005b2c +.set CYREG_SAR1_SW6, 0x40005b2e +.set CYREG_SAR1_CLK, 0x40005b2f +.set CYDEV_ANAIF_RT_OPAMP0_BASE, 0x40005b40 +.set CYDEV_ANAIF_RT_OPAMP0_SIZE, 0x00000002 +.set CYREG_OPAMP0_MX, 0x40005b40 +.set CYREG_OPAMP0_SW, 0x40005b41 +.set CYDEV_ANAIF_RT_OPAMP1_BASE, 0x40005b42 +.set CYDEV_ANAIF_RT_OPAMP1_SIZE, 0x00000002 +.set CYREG_OPAMP1_MX, 0x40005b42 +.set CYREG_OPAMP1_SW, 0x40005b43 +.set CYDEV_ANAIF_RT_OPAMP2_BASE, 0x40005b44 +.set CYDEV_ANAIF_RT_OPAMP2_SIZE, 0x00000002 +.set CYREG_OPAMP2_MX, 0x40005b44 +.set CYREG_OPAMP2_SW, 0x40005b45 +.set CYDEV_ANAIF_RT_OPAMP3_BASE, 0x40005b46 +.set CYDEV_ANAIF_RT_OPAMP3_SIZE, 0x00000002 +.set CYREG_OPAMP3_MX, 0x40005b46 +.set CYREG_OPAMP3_SW, 0x40005b47 +.set CYDEV_ANAIF_RT_LCDDAC_BASE, 0x40005b50 +.set CYDEV_ANAIF_RT_LCDDAC_SIZE, 0x00000005 +.set CYREG_LCDDAC_SW0, 0x40005b50 +.set CYREG_LCDDAC_SW1, 0x40005b51 +.set CYREG_LCDDAC_SW2, 0x40005b52 +.set CYREG_LCDDAC_SW3, 0x40005b53 +.set CYREG_LCDDAC_SW4, 0x40005b54 +.set CYDEV_ANAIF_RT_SC_BASE, 0x40005b56 +.set CYDEV_ANAIF_RT_SC_SIZE, 0x00000001 +.set CYREG_SC_MISC, 0x40005b56 +.set CYDEV_ANAIF_RT_BUS_BASE, 0x40005b58 +.set CYDEV_ANAIF_RT_BUS_SIZE, 0x00000004 +.set CYREG_BUS_SW0, 0x40005b58 +.set CYREG_BUS_SW2, 0x40005b5a +.set CYREG_BUS_SW3, 0x40005b5b +.set CYDEV_ANAIF_RT_DFT_BASE, 0x40005b5c +.set CYDEV_ANAIF_RT_DFT_SIZE, 0x00000006 +.set CYREG_DFT_CR0, 0x40005b5c +.set CYREG_DFT_CR1, 0x40005b5d +.set CYREG_DFT_CR2, 0x40005b5e +.set CYREG_DFT_CR3, 0x40005b5f +.set CYREG_DFT_CR4, 0x40005b60 +.set CYREG_DFT_CR5, 0x40005b61 +.set CYDEV_ANAIF_WRK_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_SIZE, 0x00000029 +.set CYDEV_ANAIF_WRK_DAC0_BASE, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC0_SIZE, 0x00000001 +.set CYREG_DAC0_D, 0x40005b80 +.set CYDEV_ANAIF_WRK_DAC1_BASE, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC1_SIZE, 0x00000001 +.set CYREG_DAC1_D, 0x40005b81 +.set CYDEV_ANAIF_WRK_DAC2_BASE, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC2_SIZE, 0x00000001 +.set CYREG_DAC2_D, 0x40005b82 +.set CYDEV_ANAIF_WRK_DAC3_BASE, 0x40005b83 +.set CYDEV_ANAIF_WRK_DAC3_SIZE, 0x00000001 +.set CYREG_DAC3_D, 0x40005b83 +.set CYDEV_ANAIF_WRK_DSM0_BASE, 0x40005b88 +.set CYDEV_ANAIF_WRK_DSM0_SIZE, 0x00000002 +.set CYREG_DSM0_OUT0, 0x40005b88 +.set CYREG_DSM0_OUT1, 0x40005b89 +.set CYDEV_ANAIF_WRK_LUT_BASE, 0x40005b90 +.set CYDEV_ANAIF_WRK_LUT_SIZE, 0x00000005 +.set CYREG_LUT_SR, 0x40005b90 +.set CYREG_LUT_WRK1, 0x40005b91 +.set CYREG_LUT_MSK, 0x40005b92 +.set CYREG_LUT_CLK, 0x40005b93 +.set CYREG_LUT_CPTR, 0x40005b94 +.set CYDEV_ANAIF_WRK_CMP_BASE, 0x40005b96 +.set CYDEV_ANAIF_WRK_CMP_SIZE, 0x00000002 +.set CYREG_CMP_WRK, 0x40005b96 +.set CYREG_CMP_TST, 0x40005b97 +.set CYDEV_ANAIF_WRK_SC_BASE, 0x40005b98 +.set CYDEV_ANAIF_WRK_SC_SIZE, 0x00000005 +.set CYREG_SC_SR, 0x40005b98 +.set CYREG_SC_WRK1, 0x40005b99 +.set CYREG_SC_MSK, 0x40005b9a +.set CYREG_SC_CMPINV, 0x40005b9b +.set CYREG_SC_CPTR, 0x40005b9c +.set CYDEV_ANAIF_WRK_SAR0_BASE, 0x40005ba0 +.set CYDEV_ANAIF_WRK_SAR0_SIZE, 0x00000002 +.set CYREG_SAR0_WRK0, 0x40005ba0 +.set CYREG_SAR0_WRK1, 0x40005ba1 +.set CYDEV_ANAIF_WRK_SAR1_BASE, 0x40005ba2 +.set CYDEV_ANAIF_WRK_SAR1_SIZE, 0x00000002 +.set CYREG_SAR1_WRK0, 0x40005ba2 +.set CYREG_SAR1_WRK1, 0x40005ba3 +.set CYDEV_ANAIF_WRK_SARS_BASE, 0x40005ba8 +.set CYDEV_ANAIF_WRK_SARS_SIZE, 0x00000001 +.set CYREG_ANAIF_WRK_SARS_SOF, 0x40005ba8 +.set CYDEV_USB_BASE, 0x40006000 +.set CYDEV_USB_SIZE, 0x00000300 +.set CYREG_USB_EP0_DR0, 0x40006000 +.set CYREG_USB_EP0_DR1, 0x40006001 +.set CYREG_USB_EP0_DR2, 0x40006002 +.set CYREG_USB_EP0_DR3, 0x40006003 +.set CYREG_USB_EP0_DR4, 0x40006004 +.set CYREG_USB_EP0_DR5, 0x40006005 +.set CYREG_USB_EP0_DR6, 0x40006006 +.set CYREG_USB_EP0_DR7, 0x40006007 +.set CYREG_USB_CR0, 0x40006008 +.set CYREG_USB_CR1, 0x40006009 +.set CYREG_USB_SIE_EP_INT_EN, 0x4000600a +.set CYREG_USB_SIE_EP_INT_SR, 0x4000600b +.set CYDEV_USB_SIE_EP1_BASE, 0x4000600c +.set CYDEV_USB_SIE_EP1_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP1_CNT0, 0x4000600c +.set CYREG_USB_SIE_EP1_CNT1, 0x4000600d +.set CYREG_USB_SIE_EP1_CR0, 0x4000600e +.set CYREG_USB_USBIO_CR0, 0x40006010 +.set CYREG_USB_USBIO_CR1, 0x40006012 +.set CYREG_USB_DYN_RECONFIG, 0x40006014 +.set CYREG_USB_SOF0, 0x40006018 +.set CYREG_USB_SOF1, 0x40006019 +.set CYDEV_USB_SIE_EP2_BASE, 0x4000601c +.set CYDEV_USB_SIE_EP2_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP2_CNT0, 0x4000601c +.set CYREG_USB_SIE_EP2_CNT1, 0x4000601d +.set CYREG_USB_SIE_EP2_CR0, 0x4000601e +.set CYREG_USB_EP0_CR, 0x40006028 +.set CYREG_USB_EP0_CNT, 0x40006029 +.set CYDEV_USB_SIE_EP3_BASE, 0x4000602c +.set CYDEV_USB_SIE_EP3_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP3_CNT0, 0x4000602c +.set CYREG_USB_SIE_EP3_CNT1, 0x4000602d +.set CYREG_USB_SIE_EP3_CR0, 0x4000602e +.set CYDEV_USB_SIE_EP4_BASE, 0x4000603c +.set CYDEV_USB_SIE_EP4_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP4_CNT0, 0x4000603c +.set CYREG_USB_SIE_EP4_CNT1, 0x4000603d +.set CYREG_USB_SIE_EP4_CR0, 0x4000603e +.set CYDEV_USB_SIE_EP5_BASE, 0x4000604c +.set CYDEV_USB_SIE_EP5_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP5_CNT0, 0x4000604c +.set CYREG_USB_SIE_EP5_CNT1, 0x4000604d +.set CYREG_USB_SIE_EP5_CR0, 0x4000604e +.set CYDEV_USB_SIE_EP6_BASE, 0x4000605c +.set CYDEV_USB_SIE_EP6_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP6_CNT0, 0x4000605c +.set CYREG_USB_SIE_EP6_CNT1, 0x4000605d +.set CYREG_USB_SIE_EP6_CR0, 0x4000605e +.set CYDEV_USB_SIE_EP7_BASE, 0x4000606c +.set CYDEV_USB_SIE_EP7_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP7_CNT0, 0x4000606c +.set CYREG_USB_SIE_EP7_CNT1, 0x4000606d +.set CYREG_USB_SIE_EP7_CR0, 0x4000606e +.set CYDEV_USB_SIE_EP8_BASE, 0x4000607c +.set CYDEV_USB_SIE_EP8_SIZE, 0x00000003 +.set CYREG_USB_SIE_EP8_CNT0, 0x4000607c +.set CYREG_USB_SIE_EP8_CNT1, 0x4000607d +.set CYREG_USB_SIE_EP8_CR0, 0x4000607e +.set CYDEV_USB_ARB_EP1_BASE, 0x40006080 +.set CYDEV_USB_ARB_EP1_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP1_CFG, 0x40006080 +.set CYREG_USB_ARB_EP1_INT_EN, 0x40006081 +.set CYREG_USB_ARB_EP1_SR, 0x40006082 +.set CYDEV_USB_ARB_RW1_BASE, 0x40006084 +.set CYDEV_USB_ARB_RW1_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW1_WA, 0x40006084 +.set CYREG_USB_ARB_RW1_WA_MSB, 0x40006085 +.set CYREG_USB_ARB_RW1_RA, 0x40006086 +.set CYREG_USB_ARB_RW1_RA_MSB, 0x40006087 +.set CYREG_USB_ARB_RW1_DR, 0x40006088 +.set CYREG_USB_BUF_SIZE, 0x4000608c +.set CYREG_USB_EP_ACTIVE, 0x4000608e +.set CYREG_USB_EP_TYPE, 0x4000608f +.set CYDEV_USB_ARB_EP2_BASE, 0x40006090 +.set CYDEV_USB_ARB_EP2_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP2_CFG, 0x40006090 +.set CYREG_USB_ARB_EP2_INT_EN, 0x40006091 +.set CYREG_USB_ARB_EP2_SR, 0x40006092 +.set CYDEV_USB_ARB_RW2_BASE, 0x40006094 +.set CYDEV_USB_ARB_RW2_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW2_WA, 0x40006094 +.set CYREG_USB_ARB_RW2_WA_MSB, 0x40006095 +.set CYREG_USB_ARB_RW2_RA, 0x40006096 +.set CYREG_USB_ARB_RW2_RA_MSB, 0x40006097 +.set CYREG_USB_ARB_RW2_DR, 0x40006098 +.set CYREG_USB_ARB_CFG, 0x4000609c +.set CYREG_USB_USB_CLK_EN, 0x4000609d +.set CYREG_USB_ARB_INT_EN, 0x4000609e +.set CYREG_USB_ARB_INT_SR, 0x4000609f +.set CYDEV_USB_ARB_EP3_BASE, 0x400060a0 +.set CYDEV_USB_ARB_EP3_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP3_CFG, 0x400060a0 +.set CYREG_USB_ARB_EP3_INT_EN, 0x400060a1 +.set CYREG_USB_ARB_EP3_SR, 0x400060a2 +.set CYDEV_USB_ARB_RW3_BASE, 0x400060a4 +.set CYDEV_USB_ARB_RW3_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW3_WA, 0x400060a4 +.set CYREG_USB_ARB_RW3_WA_MSB, 0x400060a5 +.set CYREG_USB_ARB_RW3_RA, 0x400060a6 +.set CYREG_USB_ARB_RW3_RA_MSB, 0x400060a7 +.set CYREG_USB_ARB_RW3_DR, 0x400060a8 +.set CYREG_USB_CWA, 0x400060ac +.set CYREG_USB_CWA_MSB, 0x400060ad +.set CYDEV_USB_ARB_EP4_BASE, 0x400060b0 +.set CYDEV_USB_ARB_EP4_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP4_CFG, 0x400060b0 +.set CYREG_USB_ARB_EP4_INT_EN, 0x400060b1 +.set CYREG_USB_ARB_EP4_SR, 0x400060b2 +.set CYDEV_USB_ARB_RW4_BASE, 0x400060b4 +.set CYDEV_USB_ARB_RW4_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW4_WA, 0x400060b4 +.set CYREG_USB_ARB_RW4_WA_MSB, 0x400060b5 +.set CYREG_USB_ARB_RW4_RA, 0x400060b6 +.set CYREG_USB_ARB_RW4_RA_MSB, 0x400060b7 +.set CYREG_USB_ARB_RW4_DR, 0x400060b8 +.set CYREG_USB_DMA_THRES, 0x400060bc +.set CYREG_USB_DMA_THRES_MSB, 0x400060bd +.set CYDEV_USB_ARB_EP5_BASE, 0x400060c0 +.set CYDEV_USB_ARB_EP5_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP5_CFG, 0x400060c0 +.set CYREG_USB_ARB_EP5_INT_EN, 0x400060c1 +.set CYREG_USB_ARB_EP5_SR, 0x400060c2 +.set CYDEV_USB_ARB_RW5_BASE, 0x400060c4 +.set CYDEV_USB_ARB_RW5_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW5_WA, 0x400060c4 +.set CYREG_USB_ARB_RW5_WA_MSB, 0x400060c5 +.set CYREG_USB_ARB_RW5_RA, 0x400060c6 +.set CYREG_USB_ARB_RW5_RA_MSB, 0x400060c7 +.set CYREG_USB_ARB_RW5_DR, 0x400060c8 +.set CYREG_USB_BUS_RST_CNT, 0x400060cc +.set CYDEV_USB_ARB_EP6_BASE, 0x400060d0 +.set CYDEV_USB_ARB_EP6_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP6_CFG, 0x400060d0 +.set CYREG_USB_ARB_EP6_INT_EN, 0x400060d1 +.set CYREG_USB_ARB_EP6_SR, 0x400060d2 +.set CYDEV_USB_ARB_RW6_BASE, 0x400060d4 +.set CYDEV_USB_ARB_RW6_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW6_WA, 0x400060d4 +.set CYREG_USB_ARB_RW6_WA_MSB, 0x400060d5 +.set CYREG_USB_ARB_RW6_RA, 0x400060d6 +.set CYREG_USB_ARB_RW6_RA_MSB, 0x400060d7 +.set CYREG_USB_ARB_RW6_DR, 0x400060d8 +.set CYDEV_USB_ARB_EP7_BASE, 0x400060e0 +.set CYDEV_USB_ARB_EP7_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP7_CFG, 0x400060e0 +.set CYREG_USB_ARB_EP7_INT_EN, 0x400060e1 +.set CYREG_USB_ARB_EP7_SR, 0x400060e2 +.set CYDEV_USB_ARB_RW7_BASE, 0x400060e4 +.set CYDEV_USB_ARB_RW7_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW7_WA, 0x400060e4 +.set CYREG_USB_ARB_RW7_WA_MSB, 0x400060e5 +.set CYREG_USB_ARB_RW7_RA, 0x400060e6 +.set CYREG_USB_ARB_RW7_RA_MSB, 0x400060e7 +.set CYREG_USB_ARB_RW7_DR, 0x400060e8 +.set CYDEV_USB_ARB_EP8_BASE, 0x400060f0 +.set CYDEV_USB_ARB_EP8_SIZE, 0x00000003 +.set CYREG_USB_ARB_EP8_CFG, 0x400060f0 +.set CYREG_USB_ARB_EP8_INT_EN, 0x400060f1 +.set CYREG_USB_ARB_EP8_SR, 0x400060f2 +.set CYDEV_USB_ARB_RW8_BASE, 0x400060f4 +.set CYDEV_USB_ARB_RW8_SIZE, 0x00000005 +.set CYREG_USB_ARB_RW8_WA, 0x400060f4 +.set CYREG_USB_ARB_RW8_WA_MSB, 0x400060f5 +.set CYREG_USB_ARB_RW8_RA, 0x400060f6 +.set CYREG_USB_ARB_RW8_RA_MSB, 0x400060f7 +.set CYREG_USB_ARB_RW8_DR, 0x400060f8 +.set CYDEV_USB_MEM_BASE, 0x40006100 +.set CYDEV_USB_MEM_SIZE, 0x00000200 +.set CYREG_USB_MEM_DATA_MBASE, 0x40006100 +.set CYREG_USB_MEM_DATA_MSIZE, 0x00000200 +.set CYDEV_UWRK_BASE, 0x40006400 +.set CYDEV_UWRK_SIZE, 0x00000b60 +.set CYDEV_UWRK_UWRK8_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_SIZE, 0x000003b0 +.set CYDEV_UWRK_UWRK8_B0_BASE, 0x40006400 +.set CYDEV_UWRK_UWRK8_B0_SIZE, 0x000000b0 +.set CYREG_B0_UDB00_A0, 0x40006400 +.set CYREG_B0_UDB01_A0, 0x40006401 +.set CYREG_B0_UDB02_A0, 0x40006402 +.set CYREG_B0_UDB03_A0, 0x40006403 +.set CYREG_B0_UDB04_A0, 0x40006404 +.set CYREG_B0_UDB05_A0, 0x40006405 +.set CYREG_B0_UDB06_A0, 0x40006406 +.set CYREG_B0_UDB07_A0, 0x40006407 +.set CYREG_B0_UDB08_A0, 0x40006408 +.set CYREG_B0_UDB09_A0, 0x40006409 +.set CYREG_B0_UDB10_A0, 0x4000640a +.set CYREG_B0_UDB11_A0, 0x4000640b +.set CYREG_B0_UDB12_A0, 0x4000640c +.set CYREG_B0_UDB13_A0, 0x4000640d +.set CYREG_B0_UDB14_A0, 0x4000640e +.set CYREG_B0_UDB15_A0, 0x4000640f +.set CYREG_B0_UDB00_A1, 0x40006410 +.set CYREG_B0_UDB01_A1, 0x40006411 +.set CYREG_B0_UDB02_A1, 0x40006412 +.set CYREG_B0_UDB03_A1, 0x40006413 +.set CYREG_B0_UDB04_A1, 0x40006414 +.set CYREG_B0_UDB05_A1, 0x40006415 +.set CYREG_B0_UDB06_A1, 0x40006416 +.set CYREG_B0_UDB07_A1, 0x40006417 +.set CYREG_B0_UDB08_A1, 0x40006418 +.set CYREG_B0_UDB09_A1, 0x40006419 +.set CYREG_B0_UDB10_A1, 0x4000641a +.set CYREG_B0_UDB11_A1, 0x4000641b +.set CYREG_B0_UDB12_A1, 0x4000641c +.set CYREG_B0_UDB13_A1, 0x4000641d +.set CYREG_B0_UDB14_A1, 0x4000641e +.set CYREG_B0_UDB15_A1, 0x4000641f +.set CYREG_B0_UDB00_D0, 0x40006420 +.set CYREG_B0_UDB01_D0, 0x40006421 +.set CYREG_B0_UDB02_D0, 0x40006422 +.set CYREG_B0_UDB03_D0, 0x40006423 +.set CYREG_B0_UDB04_D0, 0x40006424 +.set CYREG_B0_UDB05_D0, 0x40006425 +.set CYREG_B0_UDB06_D0, 0x40006426 +.set CYREG_B0_UDB07_D0, 0x40006427 +.set CYREG_B0_UDB08_D0, 0x40006428 +.set CYREG_B0_UDB09_D0, 0x40006429 +.set CYREG_B0_UDB10_D0, 0x4000642a +.set CYREG_B0_UDB11_D0, 0x4000642b +.set CYREG_B0_UDB12_D0, 0x4000642c +.set CYREG_B0_UDB13_D0, 0x4000642d +.set CYREG_B0_UDB14_D0, 0x4000642e +.set CYREG_B0_UDB15_D0, 0x4000642f +.set CYREG_B0_UDB00_D1, 0x40006430 +.set CYREG_B0_UDB01_D1, 0x40006431 +.set CYREG_B0_UDB02_D1, 0x40006432 +.set CYREG_B0_UDB03_D1, 0x40006433 +.set CYREG_B0_UDB04_D1, 0x40006434 +.set CYREG_B0_UDB05_D1, 0x40006435 +.set CYREG_B0_UDB06_D1, 0x40006436 +.set CYREG_B0_UDB07_D1, 0x40006437 +.set CYREG_B0_UDB08_D1, 0x40006438 +.set CYREG_B0_UDB09_D1, 0x40006439 +.set CYREG_B0_UDB10_D1, 0x4000643a +.set CYREG_B0_UDB11_D1, 0x4000643b +.set CYREG_B0_UDB12_D1, 0x4000643c +.set CYREG_B0_UDB13_D1, 0x4000643d +.set CYREG_B0_UDB14_D1, 0x4000643e +.set CYREG_B0_UDB15_D1, 0x4000643f +.set CYREG_B0_UDB00_F0, 0x40006440 +.set CYREG_B0_UDB01_F0, 0x40006441 +.set CYREG_B0_UDB02_F0, 0x40006442 +.set CYREG_B0_UDB03_F0, 0x40006443 +.set CYREG_B0_UDB04_F0, 0x40006444 +.set CYREG_B0_UDB05_F0, 0x40006445 +.set CYREG_B0_UDB06_F0, 0x40006446 +.set CYREG_B0_UDB07_F0, 0x40006447 +.set CYREG_B0_UDB08_F0, 0x40006448 +.set CYREG_B0_UDB09_F0, 0x40006449 +.set CYREG_B0_UDB10_F0, 0x4000644a +.set CYREG_B0_UDB11_F0, 0x4000644b +.set CYREG_B0_UDB12_F0, 0x4000644c +.set CYREG_B0_UDB13_F0, 0x4000644d +.set CYREG_B0_UDB14_F0, 0x4000644e +.set CYREG_B0_UDB15_F0, 0x4000644f +.set CYREG_B0_UDB00_F1, 0x40006450 +.set CYREG_B0_UDB01_F1, 0x40006451 +.set CYREG_B0_UDB02_F1, 0x40006452 +.set CYREG_B0_UDB03_F1, 0x40006453 +.set CYREG_B0_UDB04_F1, 0x40006454 +.set CYREG_B0_UDB05_F1, 0x40006455 +.set CYREG_B0_UDB06_F1, 0x40006456 +.set CYREG_B0_UDB07_F1, 0x40006457 +.set CYREG_B0_UDB08_F1, 0x40006458 +.set CYREG_B0_UDB09_F1, 0x40006459 +.set CYREG_B0_UDB10_F1, 0x4000645a +.set CYREG_B0_UDB11_F1, 0x4000645b +.set CYREG_B0_UDB12_F1, 0x4000645c +.set CYREG_B0_UDB13_F1, 0x4000645d +.set CYREG_B0_UDB14_F1, 0x4000645e +.set CYREG_B0_UDB15_F1, 0x4000645f +.set CYREG_B0_UDB00_ST, 0x40006460 +.set CYREG_B0_UDB01_ST, 0x40006461 +.set CYREG_B0_UDB02_ST, 0x40006462 +.set CYREG_B0_UDB03_ST, 0x40006463 +.set CYREG_B0_UDB04_ST, 0x40006464 +.set CYREG_B0_UDB05_ST, 0x40006465 +.set CYREG_B0_UDB06_ST, 0x40006466 +.set CYREG_B0_UDB07_ST, 0x40006467 +.set CYREG_B0_UDB08_ST, 0x40006468 +.set CYREG_B0_UDB09_ST, 0x40006469 +.set CYREG_B0_UDB10_ST, 0x4000646a +.set CYREG_B0_UDB11_ST, 0x4000646b +.set CYREG_B0_UDB12_ST, 0x4000646c +.set CYREG_B0_UDB13_ST, 0x4000646d +.set CYREG_B0_UDB14_ST, 0x4000646e +.set CYREG_B0_UDB15_ST, 0x4000646f +.set CYREG_B0_UDB00_CTL, 0x40006470 +.set CYREG_B0_UDB01_CTL, 0x40006471 +.set CYREG_B0_UDB02_CTL, 0x40006472 +.set CYREG_B0_UDB03_CTL, 0x40006473 +.set CYREG_B0_UDB04_CTL, 0x40006474 +.set CYREG_B0_UDB05_CTL, 0x40006475 +.set CYREG_B0_UDB06_CTL, 0x40006476 +.set CYREG_B0_UDB07_CTL, 0x40006477 +.set CYREG_B0_UDB08_CTL, 0x40006478 +.set CYREG_B0_UDB09_CTL, 0x40006479 +.set CYREG_B0_UDB10_CTL, 0x4000647a +.set CYREG_B0_UDB11_CTL, 0x4000647b +.set CYREG_B0_UDB12_CTL, 0x4000647c +.set CYREG_B0_UDB13_CTL, 0x4000647d +.set CYREG_B0_UDB14_CTL, 0x4000647e +.set CYREG_B0_UDB15_CTL, 0x4000647f +.set CYREG_B0_UDB00_MSK, 0x40006480 +.set CYREG_B0_UDB01_MSK, 0x40006481 +.set CYREG_B0_UDB02_MSK, 0x40006482 +.set CYREG_B0_UDB03_MSK, 0x40006483 +.set CYREG_B0_UDB04_MSK, 0x40006484 +.set CYREG_B0_UDB05_MSK, 0x40006485 +.set CYREG_B0_UDB06_MSK, 0x40006486 +.set CYREG_B0_UDB07_MSK, 0x40006487 +.set CYREG_B0_UDB08_MSK, 0x40006488 +.set CYREG_B0_UDB09_MSK, 0x40006489 +.set CYREG_B0_UDB10_MSK, 0x4000648a +.set CYREG_B0_UDB11_MSK, 0x4000648b +.set CYREG_B0_UDB12_MSK, 0x4000648c +.set CYREG_B0_UDB13_MSK, 0x4000648d +.set CYREG_B0_UDB14_MSK, 0x4000648e +.set CYREG_B0_UDB15_MSK, 0x4000648f +.set CYREG_B0_UDB00_ACTL, 0x40006490 +.set CYREG_B0_UDB01_ACTL, 0x40006491 +.set CYREG_B0_UDB02_ACTL, 0x40006492 +.set CYREG_B0_UDB03_ACTL, 0x40006493 +.set CYREG_B0_UDB04_ACTL, 0x40006494 +.set CYREG_B0_UDB05_ACTL, 0x40006495 +.set CYREG_B0_UDB06_ACTL, 0x40006496 +.set CYREG_B0_UDB07_ACTL, 0x40006497 +.set CYREG_B0_UDB08_ACTL, 0x40006498 +.set CYREG_B0_UDB09_ACTL, 0x40006499 +.set CYREG_B0_UDB10_ACTL, 0x4000649a +.set CYREG_B0_UDB11_ACTL, 0x4000649b +.set CYREG_B0_UDB12_ACTL, 0x4000649c +.set CYREG_B0_UDB13_ACTL, 0x4000649d +.set CYREG_B0_UDB14_ACTL, 0x4000649e +.set CYREG_B0_UDB15_ACTL, 0x4000649f +.set CYREG_B0_UDB00_MC, 0x400064a0 +.set CYREG_B0_UDB01_MC, 0x400064a1 +.set CYREG_B0_UDB02_MC, 0x400064a2 +.set CYREG_B0_UDB03_MC, 0x400064a3 +.set CYREG_B0_UDB04_MC, 0x400064a4 +.set CYREG_B0_UDB05_MC, 0x400064a5 +.set CYREG_B0_UDB06_MC, 0x400064a6 +.set CYREG_B0_UDB07_MC, 0x400064a7 +.set CYREG_B0_UDB08_MC, 0x400064a8 +.set CYREG_B0_UDB09_MC, 0x400064a9 +.set CYREG_B0_UDB10_MC, 0x400064aa +.set CYREG_B0_UDB11_MC, 0x400064ab +.set CYREG_B0_UDB12_MC, 0x400064ac +.set CYREG_B0_UDB13_MC, 0x400064ad +.set CYREG_B0_UDB14_MC, 0x400064ae +.set CYREG_B0_UDB15_MC, 0x400064af +.set CYDEV_UWRK_UWRK8_B1_BASE, 0x40006500 +.set CYDEV_UWRK_UWRK8_B1_SIZE, 0x000000b0 +.set CYREG_B1_UDB04_A0, 0x40006504 +.set CYREG_B1_UDB05_A0, 0x40006505 +.set CYREG_B1_UDB06_A0, 0x40006506 +.set CYREG_B1_UDB07_A0, 0x40006507 +.set CYREG_B1_UDB08_A0, 0x40006508 +.set CYREG_B1_UDB09_A0, 0x40006509 +.set CYREG_B1_UDB10_A0, 0x4000650a +.set CYREG_B1_UDB11_A0, 0x4000650b +.set CYREG_B1_UDB04_A1, 0x40006514 +.set CYREG_B1_UDB05_A1, 0x40006515 +.set CYREG_B1_UDB06_A1, 0x40006516 +.set CYREG_B1_UDB07_A1, 0x40006517 +.set CYREG_B1_UDB08_A1, 0x40006518 +.set CYREG_B1_UDB09_A1, 0x40006519 +.set CYREG_B1_UDB10_A1, 0x4000651a +.set CYREG_B1_UDB11_A1, 0x4000651b +.set CYREG_B1_UDB04_D0, 0x40006524 +.set CYREG_B1_UDB05_D0, 0x40006525 +.set CYREG_B1_UDB06_D0, 0x40006526 +.set CYREG_B1_UDB07_D0, 0x40006527 +.set CYREG_B1_UDB08_D0, 0x40006528 +.set CYREG_B1_UDB09_D0, 0x40006529 +.set CYREG_B1_UDB10_D0, 0x4000652a +.set CYREG_B1_UDB11_D0, 0x4000652b +.set CYREG_B1_UDB04_D1, 0x40006534 +.set CYREG_B1_UDB05_D1, 0x40006535 +.set CYREG_B1_UDB06_D1, 0x40006536 +.set CYREG_B1_UDB07_D1, 0x40006537 +.set CYREG_B1_UDB08_D1, 0x40006538 +.set CYREG_B1_UDB09_D1, 0x40006539 +.set CYREG_B1_UDB10_D1, 0x4000653a +.set CYREG_B1_UDB11_D1, 0x4000653b +.set CYREG_B1_UDB04_F0, 0x40006544 +.set CYREG_B1_UDB05_F0, 0x40006545 +.set CYREG_B1_UDB06_F0, 0x40006546 +.set CYREG_B1_UDB07_F0, 0x40006547 +.set CYREG_B1_UDB08_F0, 0x40006548 +.set CYREG_B1_UDB09_F0, 0x40006549 +.set CYREG_B1_UDB10_F0, 0x4000654a +.set CYREG_B1_UDB11_F0, 0x4000654b +.set CYREG_B1_UDB04_F1, 0x40006554 +.set CYREG_B1_UDB05_F1, 0x40006555 +.set CYREG_B1_UDB06_F1, 0x40006556 +.set CYREG_B1_UDB07_F1, 0x40006557 +.set CYREG_B1_UDB08_F1, 0x40006558 +.set CYREG_B1_UDB09_F1, 0x40006559 +.set CYREG_B1_UDB10_F1, 0x4000655a +.set CYREG_B1_UDB11_F1, 0x4000655b +.set CYREG_B1_UDB04_ST, 0x40006564 +.set CYREG_B1_UDB05_ST, 0x40006565 +.set CYREG_B1_UDB06_ST, 0x40006566 +.set CYREG_B1_UDB07_ST, 0x40006567 +.set CYREG_B1_UDB08_ST, 0x40006568 +.set CYREG_B1_UDB09_ST, 0x40006569 +.set CYREG_B1_UDB10_ST, 0x4000656a +.set CYREG_B1_UDB11_ST, 0x4000656b +.set CYREG_B1_UDB04_CTL, 0x40006574 +.set CYREG_B1_UDB05_CTL, 0x40006575 +.set CYREG_B1_UDB06_CTL, 0x40006576 +.set CYREG_B1_UDB07_CTL, 0x40006577 +.set CYREG_B1_UDB08_CTL, 0x40006578 +.set CYREG_B1_UDB09_CTL, 0x40006579 +.set CYREG_B1_UDB10_CTL, 0x4000657a +.set CYREG_B1_UDB11_CTL, 0x4000657b +.set CYREG_B1_UDB04_MSK, 0x40006584 +.set CYREG_B1_UDB05_MSK, 0x40006585 +.set CYREG_B1_UDB06_MSK, 0x40006586 +.set CYREG_B1_UDB07_MSK, 0x40006587 +.set CYREG_B1_UDB08_MSK, 0x40006588 +.set CYREG_B1_UDB09_MSK, 0x40006589 +.set CYREG_B1_UDB10_MSK, 0x4000658a +.set CYREG_B1_UDB11_MSK, 0x4000658b +.set CYREG_B1_UDB04_ACTL, 0x40006594 +.set CYREG_B1_UDB05_ACTL, 0x40006595 +.set CYREG_B1_UDB06_ACTL, 0x40006596 +.set CYREG_B1_UDB07_ACTL, 0x40006597 +.set CYREG_B1_UDB08_ACTL, 0x40006598 +.set CYREG_B1_UDB09_ACTL, 0x40006599 +.set CYREG_B1_UDB10_ACTL, 0x4000659a +.set CYREG_B1_UDB11_ACTL, 0x4000659b +.set CYREG_B1_UDB04_MC, 0x400065a4 +.set CYREG_B1_UDB05_MC, 0x400065a5 +.set CYREG_B1_UDB06_MC, 0x400065a6 +.set CYREG_B1_UDB07_MC, 0x400065a7 +.set CYREG_B1_UDB08_MC, 0x400065a8 +.set CYREG_B1_UDB09_MC, 0x400065a9 +.set CYREG_B1_UDB10_MC, 0x400065aa +.set CYREG_B1_UDB11_MC, 0x400065ab +.set CYDEV_UWRK_UWRK16_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_SIZE, 0x00000760 +.set CYDEV_UWRK_UWRK16_CAT_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_CAT_B0_SIZE, 0x00000160 +.set CYREG_B0_UDB00_A0_A1, 0x40006800 +.set CYREG_B0_UDB01_A0_A1, 0x40006802 +.set CYREG_B0_UDB02_A0_A1, 0x40006804 +.set CYREG_B0_UDB03_A0_A1, 0x40006806 +.set CYREG_B0_UDB04_A0_A1, 0x40006808 +.set CYREG_B0_UDB05_A0_A1, 0x4000680a +.set CYREG_B0_UDB06_A0_A1, 0x4000680c +.set CYREG_B0_UDB07_A0_A1, 0x4000680e +.set CYREG_B0_UDB08_A0_A1, 0x40006810 +.set CYREG_B0_UDB09_A0_A1, 0x40006812 +.set CYREG_B0_UDB10_A0_A1, 0x40006814 +.set CYREG_B0_UDB11_A0_A1, 0x40006816 +.set CYREG_B0_UDB12_A0_A1, 0x40006818 +.set CYREG_B0_UDB13_A0_A1, 0x4000681a +.set CYREG_B0_UDB14_A0_A1, 0x4000681c +.set CYREG_B0_UDB15_A0_A1, 0x4000681e +.set CYREG_B0_UDB00_D0_D1, 0x40006840 +.set CYREG_B0_UDB01_D0_D1, 0x40006842 +.set CYREG_B0_UDB02_D0_D1, 0x40006844 +.set CYREG_B0_UDB03_D0_D1, 0x40006846 +.set CYREG_B0_UDB04_D0_D1, 0x40006848 +.set CYREG_B0_UDB05_D0_D1, 0x4000684a +.set CYREG_B0_UDB06_D0_D1, 0x4000684c +.set CYREG_B0_UDB07_D0_D1, 0x4000684e +.set CYREG_B0_UDB08_D0_D1, 0x40006850 +.set CYREG_B0_UDB09_D0_D1, 0x40006852 +.set CYREG_B0_UDB10_D0_D1, 0x40006854 +.set CYREG_B0_UDB11_D0_D1, 0x40006856 +.set CYREG_B0_UDB12_D0_D1, 0x40006858 +.set CYREG_B0_UDB13_D0_D1, 0x4000685a +.set CYREG_B0_UDB14_D0_D1, 0x4000685c +.set CYREG_B0_UDB15_D0_D1, 0x4000685e +.set CYREG_B0_UDB00_F0_F1, 0x40006880 +.set CYREG_B0_UDB01_F0_F1, 0x40006882 +.set CYREG_B0_UDB02_F0_F1, 0x40006884 +.set CYREG_B0_UDB03_F0_F1, 0x40006886 +.set CYREG_B0_UDB04_F0_F1, 0x40006888 +.set CYREG_B0_UDB05_F0_F1, 0x4000688a +.set CYREG_B0_UDB06_F0_F1, 0x4000688c +.set CYREG_B0_UDB07_F0_F1, 0x4000688e +.set CYREG_B0_UDB08_F0_F1, 0x40006890 +.set CYREG_B0_UDB09_F0_F1, 0x40006892 +.set CYREG_B0_UDB10_F0_F1, 0x40006894 +.set CYREG_B0_UDB11_F0_F1, 0x40006896 +.set CYREG_B0_UDB12_F0_F1, 0x40006898 +.set CYREG_B0_UDB13_F0_F1, 0x4000689a +.set CYREG_B0_UDB14_F0_F1, 0x4000689c +.set CYREG_B0_UDB15_F0_F1, 0x4000689e +.set CYREG_B0_UDB00_ST_CTL, 0x400068c0 +.set CYREG_B0_UDB01_ST_CTL, 0x400068c2 +.set CYREG_B0_UDB02_ST_CTL, 0x400068c4 +.set CYREG_B0_UDB03_ST_CTL, 0x400068c6 +.set CYREG_B0_UDB04_ST_CTL, 0x400068c8 +.set CYREG_B0_UDB05_ST_CTL, 0x400068ca +.set CYREG_B0_UDB06_ST_CTL, 0x400068cc +.set CYREG_B0_UDB07_ST_CTL, 0x400068ce +.set CYREG_B0_UDB08_ST_CTL, 0x400068d0 +.set CYREG_B0_UDB09_ST_CTL, 0x400068d2 +.set CYREG_B0_UDB10_ST_CTL, 0x400068d4 +.set CYREG_B0_UDB11_ST_CTL, 0x400068d6 +.set CYREG_B0_UDB12_ST_CTL, 0x400068d8 +.set CYREG_B0_UDB13_ST_CTL, 0x400068da +.set CYREG_B0_UDB14_ST_CTL, 0x400068dc +.set CYREG_B0_UDB15_ST_CTL, 0x400068de +.set CYREG_B0_UDB00_MSK_ACTL, 0x40006900 +.set CYREG_B0_UDB01_MSK_ACTL, 0x40006902 +.set CYREG_B0_UDB02_MSK_ACTL, 0x40006904 +.set CYREG_B0_UDB03_MSK_ACTL, 0x40006906 +.set CYREG_B0_UDB04_MSK_ACTL, 0x40006908 +.set CYREG_B0_UDB05_MSK_ACTL, 0x4000690a +.set CYREG_B0_UDB06_MSK_ACTL, 0x4000690c +.set CYREG_B0_UDB07_MSK_ACTL, 0x4000690e +.set CYREG_B0_UDB08_MSK_ACTL, 0x40006910 +.set CYREG_B0_UDB09_MSK_ACTL, 0x40006912 +.set CYREG_B0_UDB10_MSK_ACTL, 0x40006914 +.set CYREG_B0_UDB11_MSK_ACTL, 0x40006916 +.set CYREG_B0_UDB12_MSK_ACTL, 0x40006918 +.set CYREG_B0_UDB13_MSK_ACTL, 0x4000691a +.set CYREG_B0_UDB14_MSK_ACTL, 0x4000691c +.set CYREG_B0_UDB15_MSK_ACTL, 0x4000691e +.set CYREG_B0_UDB00_MC_00, 0x40006940 +.set CYREG_B0_UDB01_MC_00, 0x40006942 +.set CYREG_B0_UDB02_MC_00, 0x40006944 +.set CYREG_B0_UDB03_MC_00, 0x40006946 +.set CYREG_B0_UDB04_MC_00, 0x40006948 +.set CYREG_B0_UDB05_MC_00, 0x4000694a +.set CYREG_B0_UDB06_MC_00, 0x4000694c +.set CYREG_B0_UDB07_MC_00, 0x4000694e +.set CYREG_B0_UDB08_MC_00, 0x40006950 +.set CYREG_B0_UDB09_MC_00, 0x40006952 +.set CYREG_B0_UDB10_MC_00, 0x40006954 +.set CYREG_B0_UDB11_MC_00, 0x40006956 +.set CYREG_B0_UDB12_MC_00, 0x40006958 +.set CYREG_B0_UDB13_MC_00, 0x4000695a +.set CYREG_B0_UDB14_MC_00, 0x4000695c +.set CYREG_B0_UDB15_MC_00, 0x4000695e +.set CYDEV_UWRK_UWRK16_CAT_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_CAT_B1_SIZE, 0x00000160 +.set CYREG_B1_UDB04_A0_A1, 0x40006a08 +.set CYREG_B1_UDB05_A0_A1, 0x40006a0a +.set CYREG_B1_UDB06_A0_A1, 0x40006a0c +.set CYREG_B1_UDB07_A0_A1, 0x40006a0e +.set CYREG_B1_UDB08_A0_A1, 0x40006a10 +.set CYREG_B1_UDB09_A0_A1, 0x40006a12 +.set CYREG_B1_UDB10_A0_A1, 0x40006a14 +.set CYREG_B1_UDB11_A0_A1, 0x40006a16 +.set CYREG_B1_UDB04_D0_D1, 0x40006a48 +.set CYREG_B1_UDB05_D0_D1, 0x40006a4a +.set CYREG_B1_UDB06_D0_D1, 0x40006a4c +.set CYREG_B1_UDB07_D0_D1, 0x40006a4e +.set CYREG_B1_UDB08_D0_D1, 0x40006a50 +.set CYREG_B1_UDB09_D0_D1, 0x40006a52 +.set CYREG_B1_UDB10_D0_D1, 0x40006a54 +.set CYREG_B1_UDB11_D0_D1, 0x40006a56 +.set CYREG_B1_UDB04_F0_F1, 0x40006a88 +.set CYREG_B1_UDB05_F0_F1, 0x40006a8a +.set CYREG_B1_UDB06_F0_F1, 0x40006a8c +.set CYREG_B1_UDB07_F0_F1, 0x40006a8e +.set CYREG_B1_UDB08_F0_F1, 0x40006a90 +.set CYREG_B1_UDB09_F0_F1, 0x40006a92 +.set CYREG_B1_UDB10_F0_F1, 0x40006a94 +.set CYREG_B1_UDB11_F0_F1, 0x40006a96 +.set CYREG_B1_UDB04_ST_CTL, 0x40006ac8 +.set CYREG_B1_UDB05_ST_CTL, 0x40006aca +.set CYREG_B1_UDB06_ST_CTL, 0x40006acc +.set CYREG_B1_UDB07_ST_CTL, 0x40006ace +.set CYREG_B1_UDB08_ST_CTL, 0x40006ad0 +.set CYREG_B1_UDB09_ST_CTL, 0x40006ad2 +.set CYREG_B1_UDB10_ST_CTL, 0x40006ad4 +.set CYREG_B1_UDB11_ST_CTL, 0x40006ad6 +.set CYREG_B1_UDB04_MSK_ACTL, 0x40006b08 +.set CYREG_B1_UDB05_MSK_ACTL, 0x40006b0a +.set CYREG_B1_UDB06_MSK_ACTL, 0x40006b0c +.set CYREG_B1_UDB07_MSK_ACTL, 0x40006b0e +.set CYREG_B1_UDB08_MSK_ACTL, 0x40006b10 +.set CYREG_B1_UDB09_MSK_ACTL, 0x40006b12 +.set CYREG_B1_UDB10_MSK_ACTL, 0x40006b14 +.set CYREG_B1_UDB11_MSK_ACTL, 0x40006b16 +.set CYREG_B1_UDB04_MC_00, 0x40006b48 +.set CYREG_B1_UDB05_MC_00, 0x40006b4a +.set CYREG_B1_UDB06_MC_00, 0x40006b4c +.set CYREG_B1_UDB07_MC_00, 0x40006b4e +.set CYREG_B1_UDB08_MC_00, 0x40006b50 +.set CYREG_B1_UDB09_MC_00, 0x40006b52 +.set CYREG_B1_UDB10_MC_00, 0x40006b54 +.set CYREG_B1_UDB11_MC_00, 0x40006b56 +.set CYDEV_UWRK_UWRK16_DEF_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_SIZE, 0x0000075e +.set CYDEV_UWRK_UWRK16_DEF_B0_BASE, 0x40006800 +.set CYDEV_UWRK_UWRK16_DEF_B0_SIZE, 0x0000015e +.set CYREG_B0_UDB00_01_A0, 0x40006800 +.set CYREG_B0_UDB01_02_A0, 0x40006802 +.set CYREG_B0_UDB02_03_A0, 0x40006804 +.set CYREG_B0_UDB03_04_A0, 0x40006806 +.set CYREG_B0_UDB04_05_A0, 0x40006808 +.set CYREG_B0_UDB05_06_A0, 0x4000680a +.set CYREG_B0_UDB06_07_A0, 0x4000680c +.set CYREG_B0_UDB07_08_A0, 0x4000680e +.set CYREG_B0_UDB08_09_A0, 0x40006810 +.set CYREG_B0_UDB09_10_A0, 0x40006812 +.set CYREG_B0_UDB10_11_A0, 0x40006814 +.set CYREG_B0_UDB11_12_A0, 0x40006816 +.set CYREG_B0_UDB12_13_A0, 0x40006818 +.set CYREG_B0_UDB13_14_A0, 0x4000681a +.set CYREG_B0_UDB14_15_A0, 0x4000681c +.set CYREG_B0_UDB00_01_A1, 0x40006820 +.set CYREG_B0_UDB01_02_A1, 0x40006822 +.set CYREG_B0_UDB02_03_A1, 0x40006824 +.set CYREG_B0_UDB03_04_A1, 0x40006826 +.set CYREG_B0_UDB04_05_A1, 0x40006828 +.set CYREG_B0_UDB05_06_A1, 0x4000682a +.set CYREG_B0_UDB06_07_A1, 0x4000682c +.set CYREG_B0_UDB07_08_A1, 0x4000682e +.set CYREG_B0_UDB08_09_A1, 0x40006830 +.set CYREG_B0_UDB09_10_A1, 0x40006832 +.set CYREG_B0_UDB10_11_A1, 0x40006834 +.set CYREG_B0_UDB11_12_A1, 0x40006836 +.set CYREG_B0_UDB12_13_A1, 0x40006838 +.set CYREG_B0_UDB13_14_A1, 0x4000683a +.set CYREG_B0_UDB14_15_A1, 0x4000683c +.set CYREG_B0_UDB00_01_D0, 0x40006840 +.set CYREG_B0_UDB01_02_D0, 0x40006842 +.set CYREG_B0_UDB02_03_D0, 0x40006844 +.set CYREG_B0_UDB03_04_D0, 0x40006846 +.set CYREG_B0_UDB04_05_D0, 0x40006848 +.set CYREG_B0_UDB05_06_D0, 0x4000684a +.set CYREG_B0_UDB06_07_D0, 0x4000684c +.set CYREG_B0_UDB07_08_D0, 0x4000684e +.set CYREG_B0_UDB08_09_D0, 0x40006850 +.set CYREG_B0_UDB09_10_D0, 0x40006852 +.set CYREG_B0_UDB10_11_D0, 0x40006854 +.set CYREG_B0_UDB11_12_D0, 0x40006856 +.set CYREG_B0_UDB12_13_D0, 0x40006858 +.set CYREG_B0_UDB13_14_D0, 0x4000685a +.set CYREG_B0_UDB14_15_D0, 0x4000685c +.set CYREG_B0_UDB00_01_D1, 0x40006860 +.set CYREG_B0_UDB01_02_D1, 0x40006862 +.set CYREG_B0_UDB02_03_D1, 0x40006864 +.set CYREG_B0_UDB03_04_D1, 0x40006866 +.set CYREG_B0_UDB04_05_D1, 0x40006868 +.set CYREG_B0_UDB05_06_D1, 0x4000686a +.set CYREG_B0_UDB06_07_D1, 0x4000686c +.set CYREG_B0_UDB07_08_D1, 0x4000686e +.set CYREG_B0_UDB08_09_D1, 0x40006870 +.set CYREG_B0_UDB09_10_D1, 0x40006872 +.set CYREG_B0_UDB10_11_D1, 0x40006874 +.set CYREG_B0_UDB11_12_D1, 0x40006876 +.set CYREG_B0_UDB12_13_D1, 0x40006878 +.set CYREG_B0_UDB13_14_D1, 0x4000687a +.set CYREG_B0_UDB14_15_D1, 0x4000687c +.set CYREG_B0_UDB00_01_F0, 0x40006880 +.set CYREG_B0_UDB01_02_F0, 0x40006882 +.set CYREG_B0_UDB02_03_F0, 0x40006884 +.set CYREG_B0_UDB03_04_F0, 0x40006886 +.set CYREG_B0_UDB04_05_F0, 0x40006888 +.set CYREG_B0_UDB05_06_F0, 0x4000688a +.set CYREG_B0_UDB06_07_F0, 0x4000688c +.set CYREG_B0_UDB07_08_F0, 0x4000688e +.set CYREG_B0_UDB08_09_F0, 0x40006890 +.set CYREG_B0_UDB09_10_F0, 0x40006892 +.set CYREG_B0_UDB10_11_F0, 0x40006894 +.set CYREG_B0_UDB11_12_F0, 0x40006896 +.set CYREG_B0_UDB12_13_F0, 0x40006898 +.set CYREG_B0_UDB13_14_F0, 0x4000689a +.set CYREG_B0_UDB14_15_F0, 0x4000689c +.set CYREG_B0_UDB00_01_F1, 0x400068a0 +.set CYREG_B0_UDB01_02_F1, 0x400068a2 +.set CYREG_B0_UDB02_03_F1, 0x400068a4 +.set CYREG_B0_UDB03_04_F1, 0x400068a6 +.set CYREG_B0_UDB04_05_F1, 0x400068a8 +.set CYREG_B0_UDB05_06_F1, 0x400068aa +.set CYREG_B0_UDB06_07_F1, 0x400068ac +.set CYREG_B0_UDB07_08_F1, 0x400068ae +.set CYREG_B0_UDB08_09_F1, 0x400068b0 +.set CYREG_B0_UDB09_10_F1, 0x400068b2 +.set CYREG_B0_UDB10_11_F1, 0x400068b4 +.set CYREG_B0_UDB11_12_F1, 0x400068b6 +.set CYREG_B0_UDB12_13_F1, 0x400068b8 +.set CYREG_B0_UDB13_14_F1, 0x400068ba +.set CYREG_B0_UDB14_15_F1, 0x400068bc +.set CYREG_B0_UDB00_01_ST, 0x400068c0 +.set CYREG_B0_UDB01_02_ST, 0x400068c2 +.set CYREG_B0_UDB02_03_ST, 0x400068c4 +.set CYREG_B0_UDB03_04_ST, 0x400068c6 +.set CYREG_B0_UDB04_05_ST, 0x400068c8 +.set CYREG_B0_UDB05_06_ST, 0x400068ca +.set CYREG_B0_UDB06_07_ST, 0x400068cc +.set CYREG_B0_UDB07_08_ST, 0x400068ce +.set CYREG_B0_UDB08_09_ST, 0x400068d0 +.set CYREG_B0_UDB09_10_ST, 0x400068d2 +.set CYREG_B0_UDB10_11_ST, 0x400068d4 +.set CYREG_B0_UDB11_12_ST, 0x400068d6 +.set CYREG_B0_UDB12_13_ST, 0x400068d8 +.set CYREG_B0_UDB13_14_ST, 0x400068da +.set CYREG_B0_UDB14_15_ST, 0x400068dc +.set CYREG_B0_UDB00_01_CTL, 0x400068e0 +.set CYREG_B0_UDB01_02_CTL, 0x400068e2 +.set CYREG_B0_UDB02_03_CTL, 0x400068e4 +.set CYREG_B0_UDB03_04_CTL, 0x400068e6 +.set CYREG_B0_UDB04_05_CTL, 0x400068e8 +.set CYREG_B0_UDB05_06_CTL, 0x400068ea +.set CYREG_B0_UDB06_07_CTL, 0x400068ec +.set CYREG_B0_UDB07_08_CTL, 0x400068ee +.set CYREG_B0_UDB08_09_CTL, 0x400068f0 +.set CYREG_B0_UDB09_10_CTL, 0x400068f2 +.set CYREG_B0_UDB10_11_CTL, 0x400068f4 +.set CYREG_B0_UDB11_12_CTL, 0x400068f6 +.set CYREG_B0_UDB12_13_CTL, 0x400068f8 +.set CYREG_B0_UDB13_14_CTL, 0x400068fa +.set CYREG_B0_UDB14_15_CTL, 0x400068fc +.set CYREG_B0_UDB00_01_MSK, 0x40006900 +.set CYREG_B0_UDB01_02_MSK, 0x40006902 +.set CYREG_B0_UDB02_03_MSK, 0x40006904 +.set CYREG_B0_UDB03_04_MSK, 0x40006906 +.set CYREG_B0_UDB04_05_MSK, 0x40006908 +.set CYREG_B0_UDB05_06_MSK, 0x4000690a +.set CYREG_B0_UDB06_07_MSK, 0x4000690c +.set CYREG_B0_UDB07_08_MSK, 0x4000690e +.set CYREG_B0_UDB08_09_MSK, 0x40006910 +.set CYREG_B0_UDB09_10_MSK, 0x40006912 +.set CYREG_B0_UDB10_11_MSK, 0x40006914 +.set CYREG_B0_UDB11_12_MSK, 0x40006916 +.set CYREG_B0_UDB12_13_MSK, 0x40006918 +.set CYREG_B0_UDB13_14_MSK, 0x4000691a +.set CYREG_B0_UDB14_15_MSK, 0x4000691c +.set CYREG_B0_UDB00_01_ACTL, 0x40006920 +.set CYREG_B0_UDB01_02_ACTL, 0x40006922 +.set CYREG_B0_UDB02_03_ACTL, 0x40006924 +.set CYREG_B0_UDB03_04_ACTL, 0x40006926 +.set CYREG_B0_UDB04_05_ACTL, 0x40006928 +.set CYREG_B0_UDB05_06_ACTL, 0x4000692a +.set CYREG_B0_UDB06_07_ACTL, 0x4000692c +.set CYREG_B0_UDB07_08_ACTL, 0x4000692e +.set CYREG_B0_UDB08_09_ACTL, 0x40006930 +.set CYREG_B0_UDB09_10_ACTL, 0x40006932 +.set CYREG_B0_UDB10_11_ACTL, 0x40006934 +.set CYREG_B0_UDB11_12_ACTL, 0x40006936 +.set CYREG_B0_UDB12_13_ACTL, 0x40006938 +.set CYREG_B0_UDB13_14_ACTL, 0x4000693a +.set CYREG_B0_UDB14_15_ACTL, 0x4000693c +.set CYREG_B0_UDB00_01_MC, 0x40006940 +.set CYREG_B0_UDB01_02_MC, 0x40006942 +.set CYREG_B0_UDB02_03_MC, 0x40006944 +.set CYREG_B0_UDB03_04_MC, 0x40006946 +.set CYREG_B0_UDB04_05_MC, 0x40006948 +.set CYREG_B0_UDB05_06_MC, 0x4000694a +.set CYREG_B0_UDB06_07_MC, 0x4000694c +.set CYREG_B0_UDB07_08_MC, 0x4000694e +.set CYREG_B0_UDB08_09_MC, 0x40006950 +.set CYREG_B0_UDB09_10_MC, 0x40006952 +.set CYREG_B0_UDB10_11_MC, 0x40006954 +.set CYREG_B0_UDB11_12_MC, 0x40006956 +.set CYREG_B0_UDB12_13_MC, 0x40006958 +.set CYREG_B0_UDB13_14_MC, 0x4000695a +.set CYREG_B0_UDB14_15_MC, 0x4000695c +.set CYDEV_UWRK_UWRK16_DEF_B1_BASE, 0x40006a00 +.set CYDEV_UWRK_UWRK16_DEF_B1_SIZE, 0x0000015e +.set CYREG_B1_UDB04_05_A0, 0x40006a08 +.set CYREG_B1_UDB05_06_A0, 0x40006a0a +.set CYREG_B1_UDB06_07_A0, 0x40006a0c +.set CYREG_B1_UDB07_08_A0, 0x40006a0e +.set CYREG_B1_UDB08_09_A0, 0x40006a10 +.set CYREG_B1_UDB09_10_A0, 0x40006a12 +.set CYREG_B1_UDB10_11_A0, 0x40006a14 +.set CYREG_B1_UDB11_12_A0, 0x40006a16 +.set CYREG_B1_UDB04_05_A1, 0x40006a28 +.set CYREG_B1_UDB05_06_A1, 0x40006a2a +.set CYREG_B1_UDB06_07_A1, 0x40006a2c +.set CYREG_B1_UDB07_08_A1, 0x40006a2e +.set CYREG_B1_UDB08_09_A1, 0x40006a30 +.set CYREG_B1_UDB09_10_A1, 0x40006a32 +.set CYREG_B1_UDB10_11_A1, 0x40006a34 +.set CYREG_B1_UDB11_12_A1, 0x40006a36 +.set CYREG_B1_UDB04_05_D0, 0x40006a48 +.set CYREG_B1_UDB05_06_D0, 0x40006a4a +.set CYREG_B1_UDB06_07_D0, 0x40006a4c +.set CYREG_B1_UDB07_08_D0, 0x40006a4e +.set CYREG_B1_UDB08_09_D0, 0x40006a50 +.set CYREG_B1_UDB09_10_D0, 0x40006a52 +.set CYREG_B1_UDB10_11_D0, 0x40006a54 +.set CYREG_B1_UDB11_12_D0, 0x40006a56 +.set CYREG_B1_UDB04_05_D1, 0x40006a68 +.set CYREG_B1_UDB05_06_D1, 0x40006a6a +.set CYREG_B1_UDB06_07_D1, 0x40006a6c +.set CYREG_B1_UDB07_08_D1, 0x40006a6e +.set CYREG_B1_UDB08_09_D1, 0x40006a70 +.set CYREG_B1_UDB09_10_D1, 0x40006a72 +.set CYREG_B1_UDB10_11_D1, 0x40006a74 +.set CYREG_B1_UDB11_12_D1, 0x40006a76 +.set CYREG_B1_UDB04_05_F0, 0x40006a88 +.set CYREG_B1_UDB05_06_F0, 0x40006a8a +.set CYREG_B1_UDB06_07_F0, 0x40006a8c +.set CYREG_B1_UDB07_08_F0, 0x40006a8e +.set CYREG_B1_UDB08_09_F0, 0x40006a90 +.set CYREG_B1_UDB09_10_F0, 0x40006a92 +.set CYREG_B1_UDB10_11_F0, 0x40006a94 +.set CYREG_B1_UDB11_12_F0, 0x40006a96 +.set CYREG_B1_UDB04_05_F1, 0x40006aa8 +.set CYREG_B1_UDB05_06_F1, 0x40006aaa +.set CYREG_B1_UDB06_07_F1, 0x40006aac +.set CYREG_B1_UDB07_08_F1, 0x40006aae +.set CYREG_B1_UDB08_09_F1, 0x40006ab0 +.set CYREG_B1_UDB09_10_F1, 0x40006ab2 +.set CYREG_B1_UDB10_11_F1, 0x40006ab4 +.set CYREG_B1_UDB11_12_F1, 0x40006ab6 +.set CYREG_B1_UDB04_05_ST, 0x40006ac8 +.set CYREG_B1_UDB05_06_ST, 0x40006aca +.set CYREG_B1_UDB06_07_ST, 0x40006acc +.set CYREG_B1_UDB07_08_ST, 0x40006ace +.set CYREG_B1_UDB08_09_ST, 0x40006ad0 +.set CYREG_B1_UDB09_10_ST, 0x40006ad2 +.set CYREG_B1_UDB10_11_ST, 0x40006ad4 +.set CYREG_B1_UDB11_12_ST, 0x40006ad6 +.set CYREG_B1_UDB04_05_CTL, 0x40006ae8 +.set CYREG_B1_UDB05_06_CTL, 0x40006aea +.set CYREG_B1_UDB06_07_CTL, 0x40006aec +.set CYREG_B1_UDB07_08_CTL, 0x40006aee +.set CYREG_B1_UDB08_09_CTL, 0x40006af0 +.set CYREG_B1_UDB09_10_CTL, 0x40006af2 +.set CYREG_B1_UDB10_11_CTL, 0x40006af4 +.set CYREG_B1_UDB11_12_CTL, 0x40006af6 +.set CYREG_B1_UDB04_05_MSK, 0x40006b08 +.set CYREG_B1_UDB05_06_MSK, 0x40006b0a +.set CYREG_B1_UDB06_07_MSK, 0x40006b0c +.set CYREG_B1_UDB07_08_MSK, 0x40006b0e +.set CYREG_B1_UDB08_09_MSK, 0x40006b10 +.set CYREG_B1_UDB09_10_MSK, 0x40006b12 +.set CYREG_B1_UDB10_11_MSK, 0x40006b14 +.set CYREG_B1_UDB11_12_MSK, 0x40006b16 +.set CYREG_B1_UDB04_05_ACTL, 0x40006b28 +.set CYREG_B1_UDB05_06_ACTL, 0x40006b2a +.set CYREG_B1_UDB06_07_ACTL, 0x40006b2c +.set CYREG_B1_UDB07_08_ACTL, 0x40006b2e +.set CYREG_B1_UDB08_09_ACTL, 0x40006b30 +.set CYREG_B1_UDB09_10_ACTL, 0x40006b32 +.set CYREG_B1_UDB10_11_ACTL, 0x40006b34 +.set CYREG_B1_UDB11_12_ACTL, 0x40006b36 +.set CYREG_B1_UDB04_05_MC, 0x40006b48 +.set CYREG_B1_UDB05_06_MC, 0x40006b4a +.set CYREG_B1_UDB06_07_MC, 0x40006b4c +.set CYREG_B1_UDB07_08_MC, 0x40006b4e +.set CYREG_B1_UDB08_09_MC, 0x40006b50 +.set CYREG_B1_UDB09_10_MC, 0x40006b52 +.set CYREG_B1_UDB10_11_MC, 0x40006b54 +.set CYREG_B1_UDB11_12_MC, 0x40006b56 +.set CYDEV_PHUB_BASE, 0x40007000 +.set CYDEV_PHUB_SIZE, 0x00000c00 +.set CYREG_PHUB_CFG, 0x40007000 +.set CYREG_PHUB_ERR, 0x40007004 +.set CYREG_PHUB_ERR_ADR, 0x40007008 +.set CYDEV_PHUB_CH0_BASE, 0x40007010 +.set CYDEV_PHUB_CH0_SIZE, 0x0000000c +.set CYREG_PHUB_CH0_BASIC_CFG, 0x40007010 +.set CYREG_PHUB_CH0_ACTION, 0x40007014 +.set CYREG_PHUB_CH0_BASIC_STATUS, 0x40007018 +.set CYDEV_PHUB_CH1_BASE, 0x40007020 +.set CYDEV_PHUB_CH1_SIZE, 0x0000000c +.set CYREG_PHUB_CH1_BASIC_CFG, 0x40007020 +.set CYREG_PHUB_CH1_ACTION, 0x40007024 +.set CYREG_PHUB_CH1_BASIC_STATUS, 0x40007028 +.set CYDEV_PHUB_CH2_BASE, 0x40007030 +.set CYDEV_PHUB_CH2_SIZE, 0x0000000c +.set CYREG_PHUB_CH2_BASIC_CFG, 0x40007030 +.set CYREG_PHUB_CH2_ACTION, 0x40007034 +.set CYREG_PHUB_CH2_BASIC_STATUS, 0x40007038 +.set CYDEV_PHUB_CH3_BASE, 0x40007040 +.set CYDEV_PHUB_CH3_SIZE, 0x0000000c +.set CYREG_PHUB_CH3_BASIC_CFG, 0x40007040 +.set CYREG_PHUB_CH3_ACTION, 0x40007044 +.set CYREG_PHUB_CH3_BASIC_STATUS, 0x40007048 +.set CYDEV_PHUB_CH4_BASE, 0x40007050 +.set CYDEV_PHUB_CH4_SIZE, 0x0000000c +.set CYREG_PHUB_CH4_BASIC_CFG, 0x40007050 +.set CYREG_PHUB_CH4_ACTION, 0x40007054 +.set CYREG_PHUB_CH4_BASIC_STATUS, 0x40007058 +.set CYDEV_PHUB_CH5_BASE, 0x40007060 +.set CYDEV_PHUB_CH5_SIZE, 0x0000000c +.set CYREG_PHUB_CH5_BASIC_CFG, 0x40007060 +.set CYREG_PHUB_CH5_ACTION, 0x40007064 +.set CYREG_PHUB_CH5_BASIC_STATUS, 0x40007068 +.set CYDEV_PHUB_CH6_BASE, 0x40007070 +.set CYDEV_PHUB_CH6_SIZE, 0x0000000c +.set CYREG_PHUB_CH6_BASIC_CFG, 0x40007070 +.set CYREG_PHUB_CH6_ACTION, 0x40007074 +.set CYREG_PHUB_CH6_BASIC_STATUS, 0x40007078 +.set CYDEV_PHUB_CH7_BASE, 0x40007080 +.set CYDEV_PHUB_CH7_SIZE, 0x0000000c +.set CYREG_PHUB_CH7_BASIC_CFG, 0x40007080 +.set CYREG_PHUB_CH7_ACTION, 0x40007084 +.set CYREG_PHUB_CH7_BASIC_STATUS, 0x40007088 +.set CYDEV_PHUB_CH8_BASE, 0x40007090 +.set CYDEV_PHUB_CH8_SIZE, 0x0000000c +.set CYREG_PHUB_CH8_BASIC_CFG, 0x40007090 +.set CYREG_PHUB_CH8_ACTION, 0x40007094 +.set CYREG_PHUB_CH8_BASIC_STATUS, 0x40007098 +.set CYDEV_PHUB_CH9_BASE, 0x400070a0 +.set CYDEV_PHUB_CH9_SIZE, 0x0000000c +.set CYREG_PHUB_CH9_BASIC_CFG, 0x400070a0 +.set CYREG_PHUB_CH9_ACTION, 0x400070a4 +.set CYREG_PHUB_CH9_BASIC_STATUS, 0x400070a8 +.set CYDEV_PHUB_CH10_BASE, 0x400070b0 +.set CYDEV_PHUB_CH10_SIZE, 0x0000000c +.set CYREG_PHUB_CH10_BASIC_CFG, 0x400070b0 +.set CYREG_PHUB_CH10_ACTION, 0x400070b4 +.set CYREG_PHUB_CH10_BASIC_STATUS, 0x400070b8 +.set CYDEV_PHUB_CH11_BASE, 0x400070c0 +.set CYDEV_PHUB_CH11_SIZE, 0x0000000c +.set CYREG_PHUB_CH11_BASIC_CFG, 0x400070c0 +.set CYREG_PHUB_CH11_ACTION, 0x400070c4 +.set CYREG_PHUB_CH11_BASIC_STATUS, 0x400070c8 +.set CYDEV_PHUB_CH12_BASE, 0x400070d0 +.set CYDEV_PHUB_CH12_SIZE, 0x0000000c +.set CYREG_PHUB_CH12_BASIC_CFG, 0x400070d0 +.set CYREG_PHUB_CH12_ACTION, 0x400070d4 +.set CYREG_PHUB_CH12_BASIC_STATUS, 0x400070d8 +.set CYDEV_PHUB_CH13_BASE, 0x400070e0 +.set CYDEV_PHUB_CH13_SIZE, 0x0000000c +.set CYREG_PHUB_CH13_BASIC_CFG, 0x400070e0 +.set CYREG_PHUB_CH13_ACTION, 0x400070e4 +.set CYREG_PHUB_CH13_BASIC_STATUS, 0x400070e8 +.set CYDEV_PHUB_CH14_BASE, 0x400070f0 +.set CYDEV_PHUB_CH14_SIZE, 0x0000000c +.set CYREG_PHUB_CH14_BASIC_CFG, 0x400070f0 +.set CYREG_PHUB_CH14_ACTION, 0x400070f4 +.set CYREG_PHUB_CH14_BASIC_STATUS, 0x400070f8 +.set CYDEV_PHUB_CH15_BASE, 0x40007100 +.set CYDEV_PHUB_CH15_SIZE, 0x0000000c +.set CYREG_PHUB_CH15_BASIC_CFG, 0x40007100 +.set CYREG_PHUB_CH15_ACTION, 0x40007104 +.set CYREG_PHUB_CH15_BASIC_STATUS, 0x40007108 +.set CYDEV_PHUB_CH16_BASE, 0x40007110 +.set CYDEV_PHUB_CH16_SIZE, 0x0000000c +.set CYREG_PHUB_CH16_BASIC_CFG, 0x40007110 +.set CYREG_PHUB_CH16_ACTION, 0x40007114 +.set CYREG_PHUB_CH16_BASIC_STATUS, 0x40007118 +.set CYDEV_PHUB_CH17_BASE, 0x40007120 +.set CYDEV_PHUB_CH17_SIZE, 0x0000000c +.set CYREG_PHUB_CH17_BASIC_CFG, 0x40007120 +.set CYREG_PHUB_CH17_ACTION, 0x40007124 +.set CYREG_PHUB_CH17_BASIC_STATUS, 0x40007128 +.set CYDEV_PHUB_CH18_BASE, 0x40007130 +.set CYDEV_PHUB_CH18_SIZE, 0x0000000c +.set CYREG_PHUB_CH18_BASIC_CFG, 0x40007130 +.set CYREG_PHUB_CH18_ACTION, 0x40007134 +.set CYREG_PHUB_CH18_BASIC_STATUS, 0x40007138 +.set CYDEV_PHUB_CH19_BASE, 0x40007140 +.set CYDEV_PHUB_CH19_SIZE, 0x0000000c +.set CYREG_PHUB_CH19_BASIC_CFG, 0x40007140 +.set CYREG_PHUB_CH19_ACTION, 0x40007144 +.set CYREG_PHUB_CH19_BASIC_STATUS, 0x40007148 +.set CYDEV_PHUB_CH20_BASE, 0x40007150 +.set CYDEV_PHUB_CH20_SIZE, 0x0000000c +.set CYREG_PHUB_CH20_BASIC_CFG, 0x40007150 +.set CYREG_PHUB_CH20_ACTION, 0x40007154 +.set CYREG_PHUB_CH20_BASIC_STATUS, 0x40007158 +.set CYDEV_PHUB_CH21_BASE, 0x40007160 +.set CYDEV_PHUB_CH21_SIZE, 0x0000000c +.set CYREG_PHUB_CH21_BASIC_CFG, 0x40007160 +.set CYREG_PHUB_CH21_ACTION, 0x40007164 +.set CYREG_PHUB_CH21_BASIC_STATUS, 0x40007168 +.set CYDEV_PHUB_CH22_BASE, 0x40007170 +.set CYDEV_PHUB_CH22_SIZE, 0x0000000c +.set CYREG_PHUB_CH22_BASIC_CFG, 0x40007170 +.set CYREG_PHUB_CH22_ACTION, 0x40007174 +.set CYREG_PHUB_CH22_BASIC_STATUS, 0x40007178 +.set CYDEV_PHUB_CH23_BASE, 0x40007180 +.set CYDEV_PHUB_CH23_SIZE, 0x0000000c +.set CYREG_PHUB_CH23_BASIC_CFG, 0x40007180 +.set CYREG_PHUB_CH23_ACTION, 0x40007184 +.set CYREG_PHUB_CH23_BASIC_STATUS, 0x40007188 +.set CYDEV_PHUB_CFGMEM0_BASE, 0x40007600 +.set CYDEV_PHUB_CFGMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM0_CFG0, 0x40007600 +.set CYREG_PHUB_CFGMEM0_CFG1, 0x40007604 +.set CYDEV_PHUB_CFGMEM1_BASE, 0x40007608 +.set CYDEV_PHUB_CFGMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM1_CFG0, 0x40007608 +.set CYREG_PHUB_CFGMEM1_CFG1, 0x4000760c +.set CYDEV_PHUB_CFGMEM2_BASE, 0x40007610 +.set CYDEV_PHUB_CFGMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM2_CFG0, 0x40007610 +.set CYREG_PHUB_CFGMEM2_CFG1, 0x40007614 +.set CYDEV_PHUB_CFGMEM3_BASE, 0x40007618 +.set CYDEV_PHUB_CFGMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM3_CFG0, 0x40007618 +.set CYREG_PHUB_CFGMEM3_CFG1, 0x4000761c +.set CYDEV_PHUB_CFGMEM4_BASE, 0x40007620 +.set CYDEV_PHUB_CFGMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM4_CFG0, 0x40007620 +.set CYREG_PHUB_CFGMEM4_CFG1, 0x40007624 +.set CYDEV_PHUB_CFGMEM5_BASE, 0x40007628 +.set CYDEV_PHUB_CFGMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM5_CFG0, 0x40007628 +.set CYREG_PHUB_CFGMEM5_CFG1, 0x4000762c +.set CYDEV_PHUB_CFGMEM6_BASE, 0x40007630 +.set CYDEV_PHUB_CFGMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM6_CFG0, 0x40007630 +.set CYREG_PHUB_CFGMEM6_CFG1, 0x40007634 +.set CYDEV_PHUB_CFGMEM7_BASE, 0x40007638 +.set CYDEV_PHUB_CFGMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM7_CFG0, 0x40007638 +.set CYREG_PHUB_CFGMEM7_CFG1, 0x4000763c +.set CYDEV_PHUB_CFGMEM8_BASE, 0x40007640 +.set CYDEV_PHUB_CFGMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM8_CFG0, 0x40007640 +.set CYREG_PHUB_CFGMEM8_CFG1, 0x40007644 +.set CYDEV_PHUB_CFGMEM9_BASE, 0x40007648 +.set CYDEV_PHUB_CFGMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM9_CFG0, 0x40007648 +.set CYREG_PHUB_CFGMEM9_CFG1, 0x4000764c +.set CYDEV_PHUB_CFGMEM10_BASE, 0x40007650 +.set CYDEV_PHUB_CFGMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM10_CFG0, 0x40007650 +.set CYREG_PHUB_CFGMEM10_CFG1, 0x40007654 +.set CYDEV_PHUB_CFGMEM11_BASE, 0x40007658 +.set CYDEV_PHUB_CFGMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM11_CFG0, 0x40007658 +.set CYREG_PHUB_CFGMEM11_CFG1, 0x4000765c +.set CYDEV_PHUB_CFGMEM12_BASE, 0x40007660 +.set CYDEV_PHUB_CFGMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM12_CFG0, 0x40007660 +.set CYREG_PHUB_CFGMEM12_CFG1, 0x40007664 +.set CYDEV_PHUB_CFGMEM13_BASE, 0x40007668 +.set CYDEV_PHUB_CFGMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM13_CFG0, 0x40007668 +.set CYREG_PHUB_CFGMEM13_CFG1, 0x4000766c +.set CYDEV_PHUB_CFGMEM14_BASE, 0x40007670 +.set CYDEV_PHUB_CFGMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM14_CFG0, 0x40007670 +.set CYREG_PHUB_CFGMEM14_CFG1, 0x40007674 +.set CYDEV_PHUB_CFGMEM15_BASE, 0x40007678 +.set CYDEV_PHUB_CFGMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM15_CFG0, 0x40007678 +.set CYREG_PHUB_CFGMEM15_CFG1, 0x4000767c +.set CYDEV_PHUB_CFGMEM16_BASE, 0x40007680 +.set CYDEV_PHUB_CFGMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM16_CFG0, 0x40007680 +.set CYREG_PHUB_CFGMEM16_CFG1, 0x40007684 +.set CYDEV_PHUB_CFGMEM17_BASE, 0x40007688 +.set CYDEV_PHUB_CFGMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM17_CFG0, 0x40007688 +.set CYREG_PHUB_CFGMEM17_CFG1, 0x4000768c +.set CYDEV_PHUB_CFGMEM18_BASE, 0x40007690 +.set CYDEV_PHUB_CFGMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM18_CFG0, 0x40007690 +.set CYREG_PHUB_CFGMEM18_CFG1, 0x40007694 +.set CYDEV_PHUB_CFGMEM19_BASE, 0x40007698 +.set CYDEV_PHUB_CFGMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM19_CFG0, 0x40007698 +.set CYREG_PHUB_CFGMEM19_CFG1, 0x4000769c +.set CYDEV_PHUB_CFGMEM20_BASE, 0x400076a0 +.set CYDEV_PHUB_CFGMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM20_CFG0, 0x400076a0 +.set CYREG_PHUB_CFGMEM20_CFG1, 0x400076a4 +.set CYDEV_PHUB_CFGMEM21_BASE, 0x400076a8 +.set CYDEV_PHUB_CFGMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM21_CFG0, 0x400076a8 +.set CYREG_PHUB_CFGMEM21_CFG1, 0x400076ac +.set CYDEV_PHUB_CFGMEM22_BASE, 0x400076b0 +.set CYDEV_PHUB_CFGMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM22_CFG0, 0x400076b0 +.set CYREG_PHUB_CFGMEM22_CFG1, 0x400076b4 +.set CYDEV_PHUB_CFGMEM23_BASE, 0x400076b8 +.set CYDEV_PHUB_CFGMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_CFGMEM23_CFG0, 0x400076b8 +.set CYREG_PHUB_CFGMEM23_CFG1, 0x400076bc +.set CYDEV_PHUB_TDMEM0_BASE, 0x40007800 +.set CYDEV_PHUB_TDMEM0_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM0_ORIG_TD0, 0x40007800 +.set CYREG_PHUB_TDMEM0_ORIG_TD1, 0x40007804 +.set CYDEV_PHUB_TDMEM1_BASE, 0x40007808 +.set CYDEV_PHUB_TDMEM1_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM1_ORIG_TD0, 0x40007808 +.set CYREG_PHUB_TDMEM1_ORIG_TD1, 0x4000780c +.set CYDEV_PHUB_TDMEM2_BASE, 0x40007810 +.set CYDEV_PHUB_TDMEM2_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM2_ORIG_TD0, 0x40007810 +.set CYREG_PHUB_TDMEM2_ORIG_TD1, 0x40007814 +.set CYDEV_PHUB_TDMEM3_BASE, 0x40007818 +.set CYDEV_PHUB_TDMEM3_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM3_ORIG_TD0, 0x40007818 +.set CYREG_PHUB_TDMEM3_ORIG_TD1, 0x4000781c +.set CYDEV_PHUB_TDMEM4_BASE, 0x40007820 +.set CYDEV_PHUB_TDMEM4_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM4_ORIG_TD0, 0x40007820 +.set CYREG_PHUB_TDMEM4_ORIG_TD1, 0x40007824 +.set CYDEV_PHUB_TDMEM5_BASE, 0x40007828 +.set CYDEV_PHUB_TDMEM5_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM5_ORIG_TD0, 0x40007828 +.set CYREG_PHUB_TDMEM5_ORIG_TD1, 0x4000782c +.set CYDEV_PHUB_TDMEM6_BASE, 0x40007830 +.set CYDEV_PHUB_TDMEM6_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM6_ORIG_TD0, 0x40007830 +.set CYREG_PHUB_TDMEM6_ORIG_TD1, 0x40007834 +.set CYDEV_PHUB_TDMEM7_BASE, 0x40007838 +.set CYDEV_PHUB_TDMEM7_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM7_ORIG_TD0, 0x40007838 +.set CYREG_PHUB_TDMEM7_ORIG_TD1, 0x4000783c +.set CYDEV_PHUB_TDMEM8_BASE, 0x40007840 +.set CYDEV_PHUB_TDMEM8_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM8_ORIG_TD0, 0x40007840 +.set CYREG_PHUB_TDMEM8_ORIG_TD1, 0x40007844 +.set CYDEV_PHUB_TDMEM9_BASE, 0x40007848 +.set CYDEV_PHUB_TDMEM9_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM9_ORIG_TD0, 0x40007848 +.set CYREG_PHUB_TDMEM9_ORIG_TD1, 0x4000784c +.set CYDEV_PHUB_TDMEM10_BASE, 0x40007850 +.set CYDEV_PHUB_TDMEM10_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM10_ORIG_TD0, 0x40007850 +.set CYREG_PHUB_TDMEM10_ORIG_TD1, 0x40007854 +.set CYDEV_PHUB_TDMEM11_BASE, 0x40007858 +.set CYDEV_PHUB_TDMEM11_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM11_ORIG_TD0, 0x40007858 +.set CYREG_PHUB_TDMEM11_ORIG_TD1, 0x4000785c +.set CYDEV_PHUB_TDMEM12_BASE, 0x40007860 +.set CYDEV_PHUB_TDMEM12_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM12_ORIG_TD0, 0x40007860 +.set CYREG_PHUB_TDMEM12_ORIG_TD1, 0x40007864 +.set CYDEV_PHUB_TDMEM13_BASE, 0x40007868 +.set CYDEV_PHUB_TDMEM13_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM13_ORIG_TD0, 0x40007868 +.set CYREG_PHUB_TDMEM13_ORIG_TD1, 0x4000786c +.set CYDEV_PHUB_TDMEM14_BASE, 0x40007870 +.set CYDEV_PHUB_TDMEM14_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM14_ORIG_TD0, 0x40007870 +.set CYREG_PHUB_TDMEM14_ORIG_TD1, 0x40007874 +.set CYDEV_PHUB_TDMEM15_BASE, 0x40007878 +.set CYDEV_PHUB_TDMEM15_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM15_ORIG_TD0, 0x40007878 +.set CYREG_PHUB_TDMEM15_ORIG_TD1, 0x4000787c +.set CYDEV_PHUB_TDMEM16_BASE, 0x40007880 +.set CYDEV_PHUB_TDMEM16_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM16_ORIG_TD0, 0x40007880 +.set CYREG_PHUB_TDMEM16_ORIG_TD1, 0x40007884 +.set CYDEV_PHUB_TDMEM17_BASE, 0x40007888 +.set CYDEV_PHUB_TDMEM17_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM17_ORIG_TD0, 0x40007888 +.set CYREG_PHUB_TDMEM17_ORIG_TD1, 0x4000788c +.set CYDEV_PHUB_TDMEM18_BASE, 0x40007890 +.set CYDEV_PHUB_TDMEM18_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM18_ORIG_TD0, 0x40007890 +.set CYREG_PHUB_TDMEM18_ORIG_TD1, 0x40007894 +.set CYDEV_PHUB_TDMEM19_BASE, 0x40007898 +.set CYDEV_PHUB_TDMEM19_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM19_ORIG_TD0, 0x40007898 +.set CYREG_PHUB_TDMEM19_ORIG_TD1, 0x4000789c +.set CYDEV_PHUB_TDMEM20_BASE, 0x400078a0 +.set CYDEV_PHUB_TDMEM20_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM20_ORIG_TD0, 0x400078a0 +.set CYREG_PHUB_TDMEM20_ORIG_TD1, 0x400078a4 +.set CYDEV_PHUB_TDMEM21_BASE, 0x400078a8 +.set CYDEV_PHUB_TDMEM21_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM21_ORIG_TD0, 0x400078a8 +.set CYREG_PHUB_TDMEM21_ORIG_TD1, 0x400078ac +.set CYDEV_PHUB_TDMEM22_BASE, 0x400078b0 +.set CYDEV_PHUB_TDMEM22_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM22_ORIG_TD0, 0x400078b0 +.set CYREG_PHUB_TDMEM22_ORIG_TD1, 0x400078b4 +.set CYDEV_PHUB_TDMEM23_BASE, 0x400078b8 +.set CYDEV_PHUB_TDMEM23_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM23_ORIG_TD0, 0x400078b8 +.set CYREG_PHUB_TDMEM23_ORIG_TD1, 0x400078bc +.set CYDEV_PHUB_TDMEM24_BASE, 0x400078c0 +.set CYDEV_PHUB_TDMEM24_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM24_ORIG_TD0, 0x400078c0 +.set CYREG_PHUB_TDMEM24_ORIG_TD1, 0x400078c4 +.set CYDEV_PHUB_TDMEM25_BASE, 0x400078c8 +.set CYDEV_PHUB_TDMEM25_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM25_ORIG_TD0, 0x400078c8 +.set CYREG_PHUB_TDMEM25_ORIG_TD1, 0x400078cc +.set CYDEV_PHUB_TDMEM26_BASE, 0x400078d0 +.set CYDEV_PHUB_TDMEM26_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM26_ORIG_TD0, 0x400078d0 +.set CYREG_PHUB_TDMEM26_ORIG_TD1, 0x400078d4 +.set CYDEV_PHUB_TDMEM27_BASE, 0x400078d8 +.set CYDEV_PHUB_TDMEM27_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM27_ORIG_TD0, 0x400078d8 +.set CYREG_PHUB_TDMEM27_ORIG_TD1, 0x400078dc +.set CYDEV_PHUB_TDMEM28_BASE, 0x400078e0 +.set CYDEV_PHUB_TDMEM28_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM28_ORIG_TD0, 0x400078e0 +.set CYREG_PHUB_TDMEM28_ORIG_TD1, 0x400078e4 +.set CYDEV_PHUB_TDMEM29_BASE, 0x400078e8 +.set CYDEV_PHUB_TDMEM29_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM29_ORIG_TD0, 0x400078e8 +.set CYREG_PHUB_TDMEM29_ORIG_TD1, 0x400078ec +.set CYDEV_PHUB_TDMEM30_BASE, 0x400078f0 +.set CYDEV_PHUB_TDMEM30_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM30_ORIG_TD0, 0x400078f0 +.set CYREG_PHUB_TDMEM30_ORIG_TD1, 0x400078f4 +.set CYDEV_PHUB_TDMEM31_BASE, 0x400078f8 +.set CYDEV_PHUB_TDMEM31_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM31_ORIG_TD0, 0x400078f8 +.set CYREG_PHUB_TDMEM31_ORIG_TD1, 0x400078fc +.set CYDEV_PHUB_TDMEM32_BASE, 0x40007900 +.set CYDEV_PHUB_TDMEM32_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM32_ORIG_TD0, 0x40007900 +.set CYREG_PHUB_TDMEM32_ORIG_TD1, 0x40007904 +.set CYDEV_PHUB_TDMEM33_BASE, 0x40007908 +.set CYDEV_PHUB_TDMEM33_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM33_ORIG_TD0, 0x40007908 +.set CYREG_PHUB_TDMEM33_ORIG_TD1, 0x4000790c +.set CYDEV_PHUB_TDMEM34_BASE, 0x40007910 +.set CYDEV_PHUB_TDMEM34_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM34_ORIG_TD0, 0x40007910 +.set CYREG_PHUB_TDMEM34_ORIG_TD1, 0x40007914 +.set CYDEV_PHUB_TDMEM35_BASE, 0x40007918 +.set CYDEV_PHUB_TDMEM35_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM35_ORIG_TD0, 0x40007918 +.set CYREG_PHUB_TDMEM35_ORIG_TD1, 0x4000791c +.set CYDEV_PHUB_TDMEM36_BASE, 0x40007920 +.set CYDEV_PHUB_TDMEM36_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM36_ORIG_TD0, 0x40007920 +.set CYREG_PHUB_TDMEM36_ORIG_TD1, 0x40007924 +.set CYDEV_PHUB_TDMEM37_BASE, 0x40007928 +.set CYDEV_PHUB_TDMEM37_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM37_ORIG_TD0, 0x40007928 +.set CYREG_PHUB_TDMEM37_ORIG_TD1, 0x4000792c +.set CYDEV_PHUB_TDMEM38_BASE, 0x40007930 +.set CYDEV_PHUB_TDMEM38_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM38_ORIG_TD0, 0x40007930 +.set CYREG_PHUB_TDMEM38_ORIG_TD1, 0x40007934 +.set CYDEV_PHUB_TDMEM39_BASE, 0x40007938 +.set CYDEV_PHUB_TDMEM39_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM39_ORIG_TD0, 0x40007938 +.set CYREG_PHUB_TDMEM39_ORIG_TD1, 0x4000793c +.set CYDEV_PHUB_TDMEM40_BASE, 0x40007940 +.set CYDEV_PHUB_TDMEM40_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM40_ORIG_TD0, 0x40007940 +.set CYREG_PHUB_TDMEM40_ORIG_TD1, 0x40007944 +.set CYDEV_PHUB_TDMEM41_BASE, 0x40007948 +.set CYDEV_PHUB_TDMEM41_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM41_ORIG_TD0, 0x40007948 +.set CYREG_PHUB_TDMEM41_ORIG_TD1, 0x4000794c +.set CYDEV_PHUB_TDMEM42_BASE, 0x40007950 +.set CYDEV_PHUB_TDMEM42_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM42_ORIG_TD0, 0x40007950 +.set CYREG_PHUB_TDMEM42_ORIG_TD1, 0x40007954 +.set CYDEV_PHUB_TDMEM43_BASE, 0x40007958 +.set CYDEV_PHUB_TDMEM43_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM43_ORIG_TD0, 0x40007958 +.set CYREG_PHUB_TDMEM43_ORIG_TD1, 0x4000795c +.set CYDEV_PHUB_TDMEM44_BASE, 0x40007960 +.set CYDEV_PHUB_TDMEM44_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM44_ORIG_TD0, 0x40007960 +.set CYREG_PHUB_TDMEM44_ORIG_TD1, 0x40007964 +.set CYDEV_PHUB_TDMEM45_BASE, 0x40007968 +.set CYDEV_PHUB_TDMEM45_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM45_ORIG_TD0, 0x40007968 +.set CYREG_PHUB_TDMEM45_ORIG_TD1, 0x4000796c +.set CYDEV_PHUB_TDMEM46_BASE, 0x40007970 +.set CYDEV_PHUB_TDMEM46_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM46_ORIG_TD0, 0x40007970 +.set CYREG_PHUB_TDMEM46_ORIG_TD1, 0x40007974 +.set CYDEV_PHUB_TDMEM47_BASE, 0x40007978 +.set CYDEV_PHUB_TDMEM47_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM47_ORIG_TD0, 0x40007978 +.set CYREG_PHUB_TDMEM47_ORIG_TD1, 0x4000797c +.set CYDEV_PHUB_TDMEM48_BASE, 0x40007980 +.set CYDEV_PHUB_TDMEM48_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM48_ORIG_TD0, 0x40007980 +.set CYREG_PHUB_TDMEM48_ORIG_TD1, 0x40007984 +.set CYDEV_PHUB_TDMEM49_BASE, 0x40007988 +.set CYDEV_PHUB_TDMEM49_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM49_ORIG_TD0, 0x40007988 +.set CYREG_PHUB_TDMEM49_ORIG_TD1, 0x4000798c +.set CYDEV_PHUB_TDMEM50_BASE, 0x40007990 +.set CYDEV_PHUB_TDMEM50_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM50_ORIG_TD0, 0x40007990 +.set CYREG_PHUB_TDMEM50_ORIG_TD1, 0x40007994 +.set CYDEV_PHUB_TDMEM51_BASE, 0x40007998 +.set CYDEV_PHUB_TDMEM51_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM51_ORIG_TD0, 0x40007998 +.set CYREG_PHUB_TDMEM51_ORIG_TD1, 0x4000799c +.set CYDEV_PHUB_TDMEM52_BASE, 0x400079a0 +.set CYDEV_PHUB_TDMEM52_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM52_ORIG_TD0, 0x400079a0 +.set CYREG_PHUB_TDMEM52_ORIG_TD1, 0x400079a4 +.set CYDEV_PHUB_TDMEM53_BASE, 0x400079a8 +.set CYDEV_PHUB_TDMEM53_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM53_ORIG_TD0, 0x400079a8 +.set CYREG_PHUB_TDMEM53_ORIG_TD1, 0x400079ac +.set CYDEV_PHUB_TDMEM54_BASE, 0x400079b0 +.set CYDEV_PHUB_TDMEM54_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM54_ORIG_TD0, 0x400079b0 +.set CYREG_PHUB_TDMEM54_ORIG_TD1, 0x400079b4 +.set CYDEV_PHUB_TDMEM55_BASE, 0x400079b8 +.set CYDEV_PHUB_TDMEM55_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM55_ORIG_TD0, 0x400079b8 +.set CYREG_PHUB_TDMEM55_ORIG_TD1, 0x400079bc +.set CYDEV_PHUB_TDMEM56_BASE, 0x400079c0 +.set CYDEV_PHUB_TDMEM56_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM56_ORIG_TD0, 0x400079c0 +.set CYREG_PHUB_TDMEM56_ORIG_TD1, 0x400079c4 +.set CYDEV_PHUB_TDMEM57_BASE, 0x400079c8 +.set CYDEV_PHUB_TDMEM57_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM57_ORIG_TD0, 0x400079c8 +.set CYREG_PHUB_TDMEM57_ORIG_TD1, 0x400079cc +.set CYDEV_PHUB_TDMEM58_BASE, 0x400079d0 +.set CYDEV_PHUB_TDMEM58_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM58_ORIG_TD0, 0x400079d0 +.set CYREG_PHUB_TDMEM58_ORIG_TD1, 0x400079d4 +.set CYDEV_PHUB_TDMEM59_BASE, 0x400079d8 +.set CYDEV_PHUB_TDMEM59_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM59_ORIG_TD0, 0x400079d8 +.set CYREG_PHUB_TDMEM59_ORIG_TD1, 0x400079dc +.set CYDEV_PHUB_TDMEM60_BASE, 0x400079e0 +.set CYDEV_PHUB_TDMEM60_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM60_ORIG_TD0, 0x400079e0 +.set CYREG_PHUB_TDMEM60_ORIG_TD1, 0x400079e4 +.set CYDEV_PHUB_TDMEM61_BASE, 0x400079e8 +.set CYDEV_PHUB_TDMEM61_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM61_ORIG_TD0, 0x400079e8 +.set CYREG_PHUB_TDMEM61_ORIG_TD1, 0x400079ec +.set CYDEV_PHUB_TDMEM62_BASE, 0x400079f0 +.set CYDEV_PHUB_TDMEM62_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM62_ORIG_TD0, 0x400079f0 +.set CYREG_PHUB_TDMEM62_ORIG_TD1, 0x400079f4 +.set CYDEV_PHUB_TDMEM63_BASE, 0x400079f8 +.set CYDEV_PHUB_TDMEM63_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM63_ORIG_TD0, 0x400079f8 +.set CYREG_PHUB_TDMEM63_ORIG_TD1, 0x400079fc +.set CYDEV_PHUB_TDMEM64_BASE, 0x40007a00 +.set CYDEV_PHUB_TDMEM64_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM64_ORIG_TD0, 0x40007a00 +.set CYREG_PHUB_TDMEM64_ORIG_TD1, 0x40007a04 +.set CYDEV_PHUB_TDMEM65_BASE, 0x40007a08 +.set CYDEV_PHUB_TDMEM65_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM65_ORIG_TD0, 0x40007a08 +.set CYREG_PHUB_TDMEM65_ORIG_TD1, 0x40007a0c +.set CYDEV_PHUB_TDMEM66_BASE, 0x40007a10 +.set CYDEV_PHUB_TDMEM66_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM66_ORIG_TD0, 0x40007a10 +.set CYREG_PHUB_TDMEM66_ORIG_TD1, 0x40007a14 +.set CYDEV_PHUB_TDMEM67_BASE, 0x40007a18 +.set CYDEV_PHUB_TDMEM67_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM67_ORIG_TD0, 0x40007a18 +.set CYREG_PHUB_TDMEM67_ORIG_TD1, 0x40007a1c +.set CYDEV_PHUB_TDMEM68_BASE, 0x40007a20 +.set CYDEV_PHUB_TDMEM68_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM68_ORIG_TD0, 0x40007a20 +.set CYREG_PHUB_TDMEM68_ORIG_TD1, 0x40007a24 +.set CYDEV_PHUB_TDMEM69_BASE, 0x40007a28 +.set CYDEV_PHUB_TDMEM69_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM69_ORIG_TD0, 0x40007a28 +.set CYREG_PHUB_TDMEM69_ORIG_TD1, 0x40007a2c +.set CYDEV_PHUB_TDMEM70_BASE, 0x40007a30 +.set CYDEV_PHUB_TDMEM70_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM70_ORIG_TD0, 0x40007a30 +.set CYREG_PHUB_TDMEM70_ORIG_TD1, 0x40007a34 +.set CYDEV_PHUB_TDMEM71_BASE, 0x40007a38 +.set CYDEV_PHUB_TDMEM71_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM71_ORIG_TD0, 0x40007a38 +.set CYREG_PHUB_TDMEM71_ORIG_TD1, 0x40007a3c +.set CYDEV_PHUB_TDMEM72_BASE, 0x40007a40 +.set CYDEV_PHUB_TDMEM72_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM72_ORIG_TD0, 0x40007a40 +.set CYREG_PHUB_TDMEM72_ORIG_TD1, 0x40007a44 +.set CYDEV_PHUB_TDMEM73_BASE, 0x40007a48 +.set CYDEV_PHUB_TDMEM73_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM73_ORIG_TD0, 0x40007a48 +.set CYREG_PHUB_TDMEM73_ORIG_TD1, 0x40007a4c +.set CYDEV_PHUB_TDMEM74_BASE, 0x40007a50 +.set CYDEV_PHUB_TDMEM74_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM74_ORIG_TD0, 0x40007a50 +.set CYREG_PHUB_TDMEM74_ORIG_TD1, 0x40007a54 +.set CYDEV_PHUB_TDMEM75_BASE, 0x40007a58 +.set CYDEV_PHUB_TDMEM75_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM75_ORIG_TD0, 0x40007a58 +.set CYREG_PHUB_TDMEM75_ORIG_TD1, 0x40007a5c +.set CYDEV_PHUB_TDMEM76_BASE, 0x40007a60 +.set CYDEV_PHUB_TDMEM76_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM76_ORIG_TD0, 0x40007a60 +.set CYREG_PHUB_TDMEM76_ORIG_TD1, 0x40007a64 +.set CYDEV_PHUB_TDMEM77_BASE, 0x40007a68 +.set CYDEV_PHUB_TDMEM77_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM77_ORIG_TD0, 0x40007a68 +.set CYREG_PHUB_TDMEM77_ORIG_TD1, 0x40007a6c +.set CYDEV_PHUB_TDMEM78_BASE, 0x40007a70 +.set CYDEV_PHUB_TDMEM78_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM78_ORIG_TD0, 0x40007a70 +.set CYREG_PHUB_TDMEM78_ORIG_TD1, 0x40007a74 +.set CYDEV_PHUB_TDMEM79_BASE, 0x40007a78 +.set CYDEV_PHUB_TDMEM79_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM79_ORIG_TD0, 0x40007a78 +.set CYREG_PHUB_TDMEM79_ORIG_TD1, 0x40007a7c +.set CYDEV_PHUB_TDMEM80_BASE, 0x40007a80 +.set CYDEV_PHUB_TDMEM80_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM80_ORIG_TD0, 0x40007a80 +.set CYREG_PHUB_TDMEM80_ORIG_TD1, 0x40007a84 +.set CYDEV_PHUB_TDMEM81_BASE, 0x40007a88 +.set CYDEV_PHUB_TDMEM81_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM81_ORIG_TD0, 0x40007a88 +.set CYREG_PHUB_TDMEM81_ORIG_TD1, 0x40007a8c +.set CYDEV_PHUB_TDMEM82_BASE, 0x40007a90 +.set CYDEV_PHUB_TDMEM82_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM82_ORIG_TD0, 0x40007a90 +.set CYREG_PHUB_TDMEM82_ORIG_TD1, 0x40007a94 +.set CYDEV_PHUB_TDMEM83_BASE, 0x40007a98 +.set CYDEV_PHUB_TDMEM83_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM83_ORIG_TD0, 0x40007a98 +.set CYREG_PHUB_TDMEM83_ORIG_TD1, 0x40007a9c +.set CYDEV_PHUB_TDMEM84_BASE, 0x40007aa0 +.set CYDEV_PHUB_TDMEM84_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM84_ORIG_TD0, 0x40007aa0 +.set CYREG_PHUB_TDMEM84_ORIG_TD1, 0x40007aa4 +.set CYDEV_PHUB_TDMEM85_BASE, 0x40007aa8 +.set CYDEV_PHUB_TDMEM85_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM85_ORIG_TD0, 0x40007aa8 +.set CYREG_PHUB_TDMEM85_ORIG_TD1, 0x40007aac +.set CYDEV_PHUB_TDMEM86_BASE, 0x40007ab0 +.set CYDEV_PHUB_TDMEM86_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM86_ORIG_TD0, 0x40007ab0 +.set CYREG_PHUB_TDMEM86_ORIG_TD1, 0x40007ab4 +.set CYDEV_PHUB_TDMEM87_BASE, 0x40007ab8 +.set CYDEV_PHUB_TDMEM87_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM87_ORIG_TD0, 0x40007ab8 +.set CYREG_PHUB_TDMEM87_ORIG_TD1, 0x40007abc +.set CYDEV_PHUB_TDMEM88_BASE, 0x40007ac0 +.set CYDEV_PHUB_TDMEM88_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM88_ORIG_TD0, 0x40007ac0 +.set CYREG_PHUB_TDMEM88_ORIG_TD1, 0x40007ac4 +.set CYDEV_PHUB_TDMEM89_BASE, 0x40007ac8 +.set CYDEV_PHUB_TDMEM89_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM89_ORIG_TD0, 0x40007ac8 +.set CYREG_PHUB_TDMEM89_ORIG_TD1, 0x40007acc +.set CYDEV_PHUB_TDMEM90_BASE, 0x40007ad0 +.set CYDEV_PHUB_TDMEM90_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM90_ORIG_TD0, 0x40007ad0 +.set CYREG_PHUB_TDMEM90_ORIG_TD1, 0x40007ad4 +.set CYDEV_PHUB_TDMEM91_BASE, 0x40007ad8 +.set CYDEV_PHUB_TDMEM91_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM91_ORIG_TD0, 0x40007ad8 +.set CYREG_PHUB_TDMEM91_ORIG_TD1, 0x40007adc +.set CYDEV_PHUB_TDMEM92_BASE, 0x40007ae0 +.set CYDEV_PHUB_TDMEM92_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM92_ORIG_TD0, 0x40007ae0 +.set CYREG_PHUB_TDMEM92_ORIG_TD1, 0x40007ae4 +.set CYDEV_PHUB_TDMEM93_BASE, 0x40007ae8 +.set CYDEV_PHUB_TDMEM93_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM93_ORIG_TD0, 0x40007ae8 +.set CYREG_PHUB_TDMEM93_ORIG_TD1, 0x40007aec +.set CYDEV_PHUB_TDMEM94_BASE, 0x40007af0 +.set CYDEV_PHUB_TDMEM94_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM94_ORIG_TD0, 0x40007af0 +.set CYREG_PHUB_TDMEM94_ORIG_TD1, 0x40007af4 +.set CYDEV_PHUB_TDMEM95_BASE, 0x40007af8 +.set CYDEV_PHUB_TDMEM95_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM95_ORIG_TD0, 0x40007af8 +.set CYREG_PHUB_TDMEM95_ORIG_TD1, 0x40007afc +.set CYDEV_PHUB_TDMEM96_BASE, 0x40007b00 +.set CYDEV_PHUB_TDMEM96_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM96_ORIG_TD0, 0x40007b00 +.set CYREG_PHUB_TDMEM96_ORIG_TD1, 0x40007b04 +.set CYDEV_PHUB_TDMEM97_BASE, 0x40007b08 +.set CYDEV_PHUB_TDMEM97_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM97_ORIG_TD0, 0x40007b08 +.set CYREG_PHUB_TDMEM97_ORIG_TD1, 0x40007b0c +.set CYDEV_PHUB_TDMEM98_BASE, 0x40007b10 +.set CYDEV_PHUB_TDMEM98_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM98_ORIG_TD0, 0x40007b10 +.set CYREG_PHUB_TDMEM98_ORIG_TD1, 0x40007b14 +.set CYDEV_PHUB_TDMEM99_BASE, 0x40007b18 +.set CYDEV_PHUB_TDMEM99_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM99_ORIG_TD0, 0x40007b18 +.set CYREG_PHUB_TDMEM99_ORIG_TD1, 0x40007b1c +.set CYDEV_PHUB_TDMEM100_BASE, 0x40007b20 +.set CYDEV_PHUB_TDMEM100_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM100_ORIG_TD0, 0x40007b20 +.set CYREG_PHUB_TDMEM100_ORIG_TD1, 0x40007b24 +.set CYDEV_PHUB_TDMEM101_BASE, 0x40007b28 +.set CYDEV_PHUB_TDMEM101_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM101_ORIG_TD0, 0x40007b28 +.set CYREG_PHUB_TDMEM101_ORIG_TD1, 0x40007b2c +.set CYDEV_PHUB_TDMEM102_BASE, 0x40007b30 +.set CYDEV_PHUB_TDMEM102_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM102_ORIG_TD0, 0x40007b30 +.set CYREG_PHUB_TDMEM102_ORIG_TD1, 0x40007b34 +.set CYDEV_PHUB_TDMEM103_BASE, 0x40007b38 +.set CYDEV_PHUB_TDMEM103_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM103_ORIG_TD0, 0x40007b38 +.set CYREG_PHUB_TDMEM103_ORIG_TD1, 0x40007b3c +.set CYDEV_PHUB_TDMEM104_BASE, 0x40007b40 +.set CYDEV_PHUB_TDMEM104_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM104_ORIG_TD0, 0x40007b40 +.set CYREG_PHUB_TDMEM104_ORIG_TD1, 0x40007b44 +.set CYDEV_PHUB_TDMEM105_BASE, 0x40007b48 +.set CYDEV_PHUB_TDMEM105_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM105_ORIG_TD0, 0x40007b48 +.set CYREG_PHUB_TDMEM105_ORIG_TD1, 0x40007b4c +.set CYDEV_PHUB_TDMEM106_BASE, 0x40007b50 +.set CYDEV_PHUB_TDMEM106_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM106_ORIG_TD0, 0x40007b50 +.set CYREG_PHUB_TDMEM106_ORIG_TD1, 0x40007b54 +.set CYDEV_PHUB_TDMEM107_BASE, 0x40007b58 +.set CYDEV_PHUB_TDMEM107_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM107_ORIG_TD0, 0x40007b58 +.set CYREG_PHUB_TDMEM107_ORIG_TD1, 0x40007b5c +.set CYDEV_PHUB_TDMEM108_BASE, 0x40007b60 +.set CYDEV_PHUB_TDMEM108_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM108_ORIG_TD0, 0x40007b60 +.set CYREG_PHUB_TDMEM108_ORIG_TD1, 0x40007b64 +.set CYDEV_PHUB_TDMEM109_BASE, 0x40007b68 +.set CYDEV_PHUB_TDMEM109_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM109_ORIG_TD0, 0x40007b68 +.set CYREG_PHUB_TDMEM109_ORIG_TD1, 0x40007b6c +.set CYDEV_PHUB_TDMEM110_BASE, 0x40007b70 +.set CYDEV_PHUB_TDMEM110_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM110_ORIG_TD0, 0x40007b70 +.set CYREG_PHUB_TDMEM110_ORIG_TD1, 0x40007b74 +.set CYDEV_PHUB_TDMEM111_BASE, 0x40007b78 +.set CYDEV_PHUB_TDMEM111_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM111_ORIG_TD0, 0x40007b78 +.set CYREG_PHUB_TDMEM111_ORIG_TD1, 0x40007b7c +.set CYDEV_PHUB_TDMEM112_BASE, 0x40007b80 +.set CYDEV_PHUB_TDMEM112_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM112_ORIG_TD0, 0x40007b80 +.set CYREG_PHUB_TDMEM112_ORIG_TD1, 0x40007b84 +.set CYDEV_PHUB_TDMEM113_BASE, 0x40007b88 +.set CYDEV_PHUB_TDMEM113_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM113_ORIG_TD0, 0x40007b88 +.set CYREG_PHUB_TDMEM113_ORIG_TD1, 0x40007b8c +.set CYDEV_PHUB_TDMEM114_BASE, 0x40007b90 +.set CYDEV_PHUB_TDMEM114_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM114_ORIG_TD0, 0x40007b90 +.set CYREG_PHUB_TDMEM114_ORIG_TD1, 0x40007b94 +.set CYDEV_PHUB_TDMEM115_BASE, 0x40007b98 +.set CYDEV_PHUB_TDMEM115_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM115_ORIG_TD0, 0x40007b98 +.set CYREG_PHUB_TDMEM115_ORIG_TD1, 0x40007b9c +.set CYDEV_PHUB_TDMEM116_BASE, 0x40007ba0 +.set CYDEV_PHUB_TDMEM116_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM116_ORIG_TD0, 0x40007ba0 +.set CYREG_PHUB_TDMEM116_ORIG_TD1, 0x40007ba4 +.set CYDEV_PHUB_TDMEM117_BASE, 0x40007ba8 +.set CYDEV_PHUB_TDMEM117_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM117_ORIG_TD0, 0x40007ba8 +.set CYREG_PHUB_TDMEM117_ORIG_TD1, 0x40007bac +.set CYDEV_PHUB_TDMEM118_BASE, 0x40007bb0 +.set CYDEV_PHUB_TDMEM118_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM118_ORIG_TD0, 0x40007bb0 +.set CYREG_PHUB_TDMEM118_ORIG_TD1, 0x40007bb4 +.set CYDEV_PHUB_TDMEM119_BASE, 0x40007bb8 +.set CYDEV_PHUB_TDMEM119_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM119_ORIG_TD0, 0x40007bb8 +.set CYREG_PHUB_TDMEM119_ORIG_TD1, 0x40007bbc +.set CYDEV_PHUB_TDMEM120_BASE, 0x40007bc0 +.set CYDEV_PHUB_TDMEM120_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM120_ORIG_TD0, 0x40007bc0 +.set CYREG_PHUB_TDMEM120_ORIG_TD1, 0x40007bc4 +.set CYDEV_PHUB_TDMEM121_BASE, 0x40007bc8 +.set CYDEV_PHUB_TDMEM121_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM121_ORIG_TD0, 0x40007bc8 +.set CYREG_PHUB_TDMEM121_ORIG_TD1, 0x40007bcc +.set CYDEV_PHUB_TDMEM122_BASE, 0x40007bd0 +.set CYDEV_PHUB_TDMEM122_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM122_ORIG_TD0, 0x40007bd0 +.set CYREG_PHUB_TDMEM122_ORIG_TD1, 0x40007bd4 +.set CYDEV_PHUB_TDMEM123_BASE, 0x40007bd8 +.set CYDEV_PHUB_TDMEM123_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM123_ORIG_TD0, 0x40007bd8 +.set CYREG_PHUB_TDMEM123_ORIG_TD1, 0x40007bdc +.set CYDEV_PHUB_TDMEM124_BASE, 0x40007be0 +.set CYDEV_PHUB_TDMEM124_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM124_ORIG_TD0, 0x40007be0 +.set CYREG_PHUB_TDMEM124_ORIG_TD1, 0x40007be4 +.set CYDEV_PHUB_TDMEM125_BASE, 0x40007be8 +.set CYDEV_PHUB_TDMEM125_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM125_ORIG_TD0, 0x40007be8 +.set CYREG_PHUB_TDMEM125_ORIG_TD1, 0x40007bec +.set CYDEV_PHUB_TDMEM126_BASE, 0x40007bf0 +.set CYDEV_PHUB_TDMEM126_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM126_ORIG_TD0, 0x40007bf0 +.set CYREG_PHUB_TDMEM126_ORIG_TD1, 0x40007bf4 +.set CYDEV_PHUB_TDMEM127_BASE, 0x40007bf8 +.set CYDEV_PHUB_TDMEM127_SIZE, 0x00000008 +.set CYREG_PHUB_TDMEM127_ORIG_TD0, 0x40007bf8 +.set CYREG_PHUB_TDMEM127_ORIG_TD1, 0x40007bfc +.set CYDEV_EE_BASE, 0x40008000 +.set CYDEV_EE_SIZE, 0x00000800 +.set CYREG_EE_DATA_MBASE, 0x40008000 +.set CYREG_EE_DATA_MSIZE, 0x00000800 +.set CYDEV_CAN0_BASE, 0x4000a000 +.set CYDEV_CAN0_SIZE, 0x000002a0 +.set CYDEV_CAN0_CSR_BASE, 0x4000a000 +.set CYDEV_CAN0_CSR_SIZE, 0x00000018 +.set CYREG_CAN0_CSR_INT_SR, 0x4000a000 +.set CYREG_CAN0_CSR_INT_EN, 0x4000a004 +.set CYREG_CAN0_CSR_BUF_SR, 0x4000a008 +.set CYREG_CAN0_CSR_ERR_SR, 0x4000a00c +.set CYREG_CAN0_CSR_CMD, 0x4000a010 +.set CYREG_CAN0_CSR_CFG, 0x4000a014 +.set CYDEV_CAN0_TX0_BASE, 0x4000a020 +.set CYDEV_CAN0_TX0_SIZE, 0x00000010 +.set CYREG_CAN0_TX0_CMD, 0x4000a020 +.set CYREG_CAN0_TX0_ID, 0x4000a024 +.set CYREG_CAN0_TX0_DH, 0x4000a028 +.set CYREG_CAN0_TX0_DL, 0x4000a02c +.set CYDEV_CAN0_TX1_BASE, 0x4000a030 +.set CYDEV_CAN0_TX1_SIZE, 0x00000010 +.set CYREG_CAN0_TX1_CMD, 0x4000a030 +.set CYREG_CAN0_TX1_ID, 0x4000a034 +.set CYREG_CAN0_TX1_DH, 0x4000a038 +.set CYREG_CAN0_TX1_DL, 0x4000a03c +.set CYDEV_CAN0_TX2_BASE, 0x4000a040 +.set CYDEV_CAN0_TX2_SIZE, 0x00000010 +.set CYREG_CAN0_TX2_CMD, 0x4000a040 +.set CYREG_CAN0_TX2_ID, 0x4000a044 +.set CYREG_CAN0_TX2_DH, 0x4000a048 +.set CYREG_CAN0_TX2_DL, 0x4000a04c +.set CYDEV_CAN0_TX3_BASE, 0x4000a050 +.set CYDEV_CAN0_TX3_SIZE, 0x00000010 +.set CYREG_CAN0_TX3_CMD, 0x4000a050 +.set CYREG_CAN0_TX3_ID, 0x4000a054 +.set CYREG_CAN0_TX3_DH, 0x4000a058 +.set CYREG_CAN0_TX3_DL, 0x4000a05c +.set CYDEV_CAN0_TX4_BASE, 0x4000a060 +.set CYDEV_CAN0_TX4_SIZE, 0x00000010 +.set CYREG_CAN0_TX4_CMD, 0x4000a060 +.set CYREG_CAN0_TX4_ID, 0x4000a064 +.set CYREG_CAN0_TX4_DH, 0x4000a068 +.set CYREG_CAN0_TX4_DL, 0x4000a06c +.set CYDEV_CAN0_TX5_BASE, 0x4000a070 +.set CYDEV_CAN0_TX5_SIZE, 0x00000010 +.set CYREG_CAN0_TX5_CMD, 0x4000a070 +.set CYREG_CAN0_TX5_ID, 0x4000a074 +.set CYREG_CAN0_TX5_DH, 0x4000a078 +.set CYREG_CAN0_TX5_DL, 0x4000a07c +.set CYDEV_CAN0_TX6_BASE, 0x4000a080 +.set CYDEV_CAN0_TX6_SIZE, 0x00000010 +.set CYREG_CAN0_TX6_CMD, 0x4000a080 +.set CYREG_CAN0_TX6_ID, 0x4000a084 +.set CYREG_CAN0_TX6_DH, 0x4000a088 +.set CYREG_CAN0_TX6_DL, 0x4000a08c +.set CYDEV_CAN0_TX7_BASE, 0x4000a090 +.set CYDEV_CAN0_TX7_SIZE, 0x00000010 +.set CYREG_CAN0_TX7_CMD, 0x4000a090 +.set CYREG_CAN0_TX7_ID, 0x4000a094 +.set CYREG_CAN0_TX7_DH, 0x4000a098 +.set CYREG_CAN0_TX7_DL, 0x4000a09c +.set CYDEV_CAN0_RX0_BASE, 0x4000a0a0 +.set CYDEV_CAN0_RX0_SIZE, 0x00000020 +.set CYREG_CAN0_RX0_CMD, 0x4000a0a0 +.set CYREG_CAN0_RX0_ID, 0x4000a0a4 +.set CYREG_CAN0_RX0_DH, 0x4000a0a8 +.set CYREG_CAN0_RX0_DL, 0x4000a0ac +.set CYREG_CAN0_RX0_AMR, 0x4000a0b0 +.set CYREG_CAN0_RX0_ACR, 0x4000a0b4 +.set CYREG_CAN0_RX0_AMRD, 0x4000a0b8 +.set CYREG_CAN0_RX0_ACRD, 0x4000a0bc +.set CYDEV_CAN0_RX1_BASE, 0x4000a0c0 +.set CYDEV_CAN0_RX1_SIZE, 0x00000020 +.set CYREG_CAN0_RX1_CMD, 0x4000a0c0 +.set CYREG_CAN0_RX1_ID, 0x4000a0c4 +.set CYREG_CAN0_RX1_DH, 0x4000a0c8 +.set CYREG_CAN0_RX1_DL, 0x4000a0cc +.set CYREG_CAN0_RX1_AMR, 0x4000a0d0 +.set CYREG_CAN0_RX1_ACR, 0x4000a0d4 +.set CYREG_CAN0_RX1_AMRD, 0x4000a0d8 +.set CYREG_CAN0_RX1_ACRD, 0x4000a0dc +.set CYDEV_CAN0_RX2_BASE, 0x4000a0e0 +.set CYDEV_CAN0_RX2_SIZE, 0x00000020 +.set CYREG_CAN0_RX2_CMD, 0x4000a0e0 +.set CYREG_CAN0_RX2_ID, 0x4000a0e4 +.set CYREG_CAN0_RX2_DH, 0x4000a0e8 +.set CYREG_CAN0_RX2_DL, 0x4000a0ec +.set CYREG_CAN0_RX2_AMR, 0x4000a0f0 +.set CYREG_CAN0_RX2_ACR, 0x4000a0f4 +.set CYREG_CAN0_RX2_AMRD, 0x4000a0f8 +.set CYREG_CAN0_RX2_ACRD, 0x4000a0fc +.set CYDEV_CAN0_RX3_BASE, 0x4000a100 +.set CYDEV_CAN0_RX3_SIZE, 0x00000020 +.set CYREG_CAN0_RX3_CMD, 0x4000a100 +.set CYREG_CAN0_RX3_ID, 0x4000a104 +.set CYREG_CAN0_RX3_DH, 0x4000a108 +.set CYREG_CAN0_RX3_DL, 0x4000a10c +.set CYREG_CAN0_RX3_AMR, 0x4000a110 +.set CYREG_CAN0_RX3_ACR, 0x4000a114 +.set CYREG_CAN0_RX3_AMRD, 0x4000a118 +.set CYREG_CAN0_RX3_ACRD, 0x4000a11c +.set CYDEV_CAN0_RX4_BASE, 0x4000a120 +.set CYDEV_CAN0_RX4_SIZE, 0x00000020 +.set CYREG_CAN0_RX4_CMD, 0x4000a120 +.set CYREG_CAN0_RX4_ID, 0x4000a124 +.set CYREG_CAN0_RX4_DH, 0x4000a128 +.set CYREG_CAN0_RX4_DL, 0x4000a12c +.set CYREG_CAN0_RX4_AMR, 0x4000a130 +.set CYREG_CAN0_RX4_ACR, 0x4000a134 +.set CYREG_CAN0_RX4_AMRD, 0x4000a138 +.set CYREG_CAN0_RX4_ACRD, 0x4000a13c +.set CYDEV_CAN0_RX5_BASE, 0x4000a140 +.set CYDEV_CAN0_RX5_SIZE, 0x00000020 +.set CYREG_CAN0_RX5_CMD, 0x4000a140 +.set CYREG_CAN0_RX5_ID, 0x4000a144 +.set CYREG_CAN0_RX5_DH, 0x4000a148 +.set CYREG_CAN0_RX5_DL, 0x4000a14c +.set CYREG_CAN0_RX5_AMR, 0x4000a150 +.set CYREG_CAN0_RX5_ACR, 0x4000a154 +.set CYREG_CAN0_RX5_AMRD, 0x4000a158 +.set CYREG_CAN0_RX5_ACRD, 0x4000a15c +.set CYDEV_CAN0_RX6_BASE, 0x4000a160 +.set CYDEV_CAN0_RX6_SIZE, 0x00000020 +.set CYREG_CAN0_RX6_CMD, 0x4000a160 +.set CYREG_CAN0_RX6_ID, 0x4000a164 +.set CYREG_CAN0_RX6_DH, 0x4000a168 +.set CYREG_CAN0_RX6_DL, 0x4000a16c +.set CYREG_CAN0_RX6_AMR, 0x4000a170 +.set CYREG_CAN0_RX6_ACR, 0x4000a174 +.set CYREG_CAN0_RX6_AMRD, 0x4000a178 +.set CYREG_CAN0_RX6_ACRD, 0x4000a17c +.set CYDEV_CAN0_RX7_BASE, 0x4000a180 +.set CYDEV_CAN0_RX7_SIZE, 0x00000020 +.set CYREG_CAN0_RX7_CMD, 0x4000a180 +.set CYREG_CAN0_RX7_ID, 0x4000a184 +.set CYREG_CAN0_RX7_DH, 0x4000a188 +.set CYREG_CAN0_RX7_DL, 0x4000a18c +.set CYREG_CAN0_RX7_AMR, 0x4000a190 +.set CYREG_CAN0_RX7_ACR, 0x4000a194 +.set CYREG_CAN0_RX7_AMRD, 0x4000a198 +.set CYREG_CAN0_RX7_ACRD, 0x4000a19c +.set CYDEV_CAN0_RX8_BASE, 0x4000a1a0 +.set CYDEV_CAN0_RX8_SIZE, 0x00000020 +.set CYREG_CAN0_RX8_CMD, 0x4000a1a0 +.set CYREG_CAN0_RX8_ID, 0x4000a1a4 +.set CYREG_CAN0_RX8_DH, 0x4000a1a8 +.set CYREG_CAN0_RX8_DL, 0x4000a1ac +.set CYREG_CAN0_RX8_AMR, 0x4000a1b0 +.set CYREG_CAN0_RX8_ACR, 0x4000a1b4 +.set CYREG_CAN0_RX8_AMRD, 0x4000a1b8 +.set CYREG_CAN0_RX8_ACRD, 0x4000a1bc +.set CYDEV_CAN0_RX9_BASE, 0x4000a1c0 +.set CYDEV_CAN0_RX9_SIZE, 0x00000020 +.set CYREG_CAN0_RX9_CMD, 0x4000a1c0 +.set CYREG_CAN0_RX9_ID, 0x4000a1c4 +.set CYREG_CAN0_RX9_DH, 0x4000a1c8 +.set CYREG_CAN0_RX9_DL, 0x4000a1cc +.set CYREG_CAN0_RX9_AMR, 0x4000a1d0 +.set CYREG_CAN0_RX9_ACR, 0x4000a1d4 +.set CYREG_CAN0_RX9_AMRD, 0x4000a1d8 +.set CYREG_CAN0_RX9_ACRD, 0x4000a1dc +.set CYDEV_CAN0_RX10_BASE, 0x4000a1e0 +.set CYDEV_CAN0_RX10_SIZE, 0x00000020 +.set CYREG_CAN0_RX10_CMD, 0x4000a1e0 +.set CYREG_CAN0_RX10_ID, 0x4000a1e4 +.set CYREG_CAN0_RX10_DH, 0x4000a1e8 +.set CYREG_CAN0_RX10_DL, 0x4000a1ec +.set CYREG_CAN0_RX10_AMR, 0x4000a1f0 +.set CYREG_CAN0_RX10_ACR, 0x4000a1f4 +.set CYREG_CAN0_RX10_AMRD, 0x4000a1f8 +.set CYREG_CAN0_RX10_ACRD, 0x4000a1fc +.set CYDEV_CAN0_RX11_BASE, 0x4000a200 +.set CYDEV_CAN0_RX11_SIZE, 0x00000020 +.set CYREG_CAN0_RX11_CMD, 0x4000a200 +.set CYREG_CAN0_RX11_ID, 0x4000a204 +.set CYREG_CAN0_RX11_DH, 0x4000a208 +.set CYREG_CAN0_RX11_DL, 0x4000a20c +.set CYREG_CAN0_RX11_AMR, 0x4000a210 +.set CYREG_CAN0_RX11_ACR, 0x4000a214 +.set CYREG_CAN0_RX11_AMRD, 0x4000a218 +.set CYREG_CAN0_RX11_ACRD, 0x4000a21c +.set CYDEV_CAN0_RX12_BASE, 0x4000a220 +.set CYDEV_CAN0_RX12_SIZE, 0x00000020 +.set CYREG_CAN0_RX12_CMD, 0x4000a220 +.set CYREG_CAN0_RX12_ID, 0x4000a224 +.set CYREG_CAN0_RX12_DH, 0x4000a228 +.set CYREG_CAN0_RX12_DL, 0x4000a22c +.set CYREG_CAN0_RX12_AMR, 0x4000a230 +.set CYREG_CAN0_RX12_ACR, 0x4000a234 +.set CYREG_CAN0_RX12_AMRD, 0x4000a238 +.set CYREG_CAN0_RX12_ACRD, 0x4000a23c +.set CYDEV_CAN0_RX13_BASE, 0x4000a240 +.set CYDEV_CAN0_RX13_SIZE, 0x00000020 +.set CYREG_CAN0_RX13_CMD, 0x4000a240 +.set CYREG_CAN0_RX13_ID, 0x4000a244 +.set CYREG_CAN0_RX13_DH, 0x4000a248 +.set CYREG_CAN0_RX13_DL, 0x4000a24c +.set CYREG_CAN0_RX13_AMR, 0x4000a250 +.set CYREG_CAN0_RX13_ACR, 0x4000a254 +.set CYREG_CAN0_RX13_AMRD, 0x4000a258 +.set CYREG_CAN0_RX13_ACRD, 0x4000a25c +.set CYDEV_CAN0_RX14_BASE, 0x4000a260 +.set CYDEV_CAN0_RX14_SIZE, 0x00000020 +.set CYREG_CAN0_RX14_CMD, 0x4000a260 +.set CYREG_CAN0_RX14_ID, 0x4000a264 +.set CYREG_CAN0_RX14_DH, 0x4000a268 +.set CYREG_CAN0_RX14_DL, 0x4000a26c +.set CYREG_CAN0_RX14_AMR, 0x4000a270 +.set CYREG_CAN0_RX14_ACR, 0x4000a274 +.set CYREG_CAN0_RX14_AMRD, 0x4000a278 +.set CYREG_CAN0_RX14_ACRD, 0x4000a27c +.set CYDEV_CAN0_RX15_BASE, 0x4000a280 +.set CYDEV_CAN0_RX15_SIZE, 0x00000020 +.set CYREG_CAN0_RX15_CMD, 0x4000a280 +.set CYREG_CAN0_RX15_ID, 0x4000a284 +.set CYREG_CAN0_RX15_DH, 0x4000a288 +.set CYREG_CAN0_RX15_DL, 0x4000a28c +.set CYREG_CAN0_RX15_AMR, 0x4000a290 +.set CYREG_CAN0_RX15_ACR, 0x4000a294 +.set CYREG_CAN0_RX15_AMRD, 0x4000a298 +.set CYREG_CAN0_RX15_ACRD, 0x4000a29c +.set CYDEV_DFB0_BASE, 0x4000c000 +.set CYDEV_DFB0_SIZE, 0x000007b5 +.set CYDEV_DFB0_DPA_SRAM_BASE, 0x4000c000 +.set CYDEV_DFB0_DPA_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPA_SRAM_DATA_MBASE, 0x4000c000 +.set CYREG_DFB0_DPA_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_DPB_SRAM_BASE, 0x4000c200 +.set CYDEV_DFB0_DPB_SRAM_SIZE, 0x00000200 +.set CYREG_DFB0_DPB_SRAM_DATA_MBASE, 0x4000c200 +.set CYREG_DFB0_DPB_SRAM_DATA_MSIZE, 0x00000200 +.set CYDEV_DFB0_CSA_SRAM_BASE, 0x4000c400 +.set CYDEV_DFB0_CSA_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSA_SRAM_DATA_MBASE, 0x4000c400 +.set CYREG_DFB0_CSA_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_CSB_SRAM_BASE, 0x4000c500 +.set CYDEV_DFB0_CSB_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_CSB_SRAM_DATA_MBASE, 0x4000c500 +.set CYREG_DFB0_CSB_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_FSM_SRAM_BASE, 0x4000c600 +.set CYDEV_DFB0_FSM_SRAM_SIZE, 0x00000100 +.set CYREG_DFB0_FSM_SRAM_DATA_MBASE, 0x4000c600 +.set CYREG_DFB0_FSM_SRAM_DATA_MSIZE, 0x00000100 +.set CYDEV_DFB0_ACU_SRAM_BASE, 0x4000c700 +.set CYDEV_DFB0_ACU_SRAM_SIZE, 0x00000040 +.set CYREG_DFB0_ACU_SRAM_DATA_MBASE, 0x4000c700 +.set CYREG_DFB0_ACU_SRAM_DATA_MSIZE, 0x00000040 +.set CYREG_DFB0_CR, 0x4000c780 +.set CYREG_DFB0_SR, 0x4000c784 +.set CYREG_DFB0_RAM_EN, 0x4000c788 +.set CYREG_DFB0_RAM_DIR, 0x4000c78c +.set CYREG_DFB0_SEMA, 0x4000c790 +.set CYREG_DFB0_DSI_CTRL, 0x4000c794 +.set CYREG_DFB0_INT_CTRL, 0x4000c798 +.set CYREG_DFB0_DMA_CTRL, 0x4000c79c +.set CYREG_DFB0_STAGEA, 0x4000c7a0 +.set CYREG_DFB0_STAGEAM, 0x4000c7a1 +.set CYREG_DFB0_STAGEAH, 0x4000c7a2 +.set CYREG_DFB0_STAGEB, 0x4000c7a4 +.set CYREG_DFB0_STAGEBM, 0x4000c7a5 +.set CYREG_DFB0_STAGEBH, 0x4000c7a6 +.set CYREG_DFB0_HOLDA, 0x4000c7a8 +.set CYREG_DFB0_HOLDAM, 0x4000c7a9 +.set CYREG_DFB0_HOLDAH, 0x4000c7aa +.set CYREG_DFB0_HOLDAS, 0x4000c7ab +.set CYREG_DFB0_HOLDB, 0x4000c7ac +.set CYREG_DFB0_HOLDBM, 0x4000c7ad +.set CYREG_DFB0_HOLDBH, 0x4000c7ae +.set CYREG_DFB0_HOLDBS, 0x4000c7af +.set CYREG_DFB0_COHER, 0x4000c7b0 +.set CYREG_DFB0_DALIGN, 0x4000c7b4 +.set CYDEV_UCFG_BASE, 0x40010000 +.set CYDEV_UCFG_SIZE, 0x00005040 +.set CYDEV_UCFG_B0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_SIZE, 0x00000fef +.set CYDEV_UCFG_B0_P0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P0_U0_BASE, 0x40010000 +.set CYDEV_UCFG_B0_P0_U0_SIZE, 0x00000070 +.set CYREG_B0_P0_U0_PLD_IT0, 0x40010000 +.set CYREG_B0_P0_U0_PLD_IT1, 0x40010004 +.set CYREG_B0_P0_U0_PLD_IT2, 0x40010008 +.set CYREG_B0_P0_U0_PLD_IT3, 0x4001000c +.set CYREG_B0_P0_U0_PLD_IT4, 0x40010010 +.set CYREG_B0_P0_U0_PLD_IT5, 0x40010014 +.set CYREG_B0_P0_U0_PLD_IT6, 0x40010018 +.set CYREG_B0_P0_U0_PLD_IT7, 0x4001001c +.set CYREG_B0_P0_U0_PLD_IT8, 0x40010020 +.set CYREG_B0_P0_U0_PLD_IT9, 0x40010024 +.set CYREG_B0_P0_U0_PLD_IT10, 0x40010028 +.set CYREG_B0_P0_U0_PLD_IT11, 0x4001002c +.set CYREG_B0_P0_U0_PLD_ORT0, 0x40010030 +.set CYREG_B0_P0_U0_PLD_ORT1, 0x40010032 +.set CYREG_B0_P0_U0_PLD_ORT2, 0x40010034 +.set CYREG_B0_P0_U0_PLD_ORT3, 0x40010036 +.set CYREG_B0_P0_U0_MC_CFG_CEN_CONST, 0x40010038 +.set CYREG_B0_P0_U0_MC_CFG_XORFB, 0x4001003a +.set CYREG_B0_P0_U0_MC_CFG_SET_RESET, 0x4001003c +.set CYREG_B0_P0_U0_MC_CFG_BYPASS, 0x4001003e +.set CYREG_B0_P0_U0_CFG0, 0x40010040 +.set CYREG_B0_P0_U0_CFG1, 0x40010041 +.set CYREG_B0_P0_U0_CFG2, 0x40010042 +.set CYREG_B0_P0_U0_CFG3, 0x40010043 +.set CYREG_B0_P0_U0_CFG4, 0x40010044 +.set CYREG_B0_P0_U0_CFG5, 0x40010045 +.set CYREG_B0_P0_U0_CFG6, 0x40010046 +.set CYREG_B0_P0_U0_CFG7, 0x40010047 +.set CYREG_B0_P0_U0_CFG8, 0x40010048 +.set CYREG_B0_P0_U0_CFG9, 0x40010049 +.set CYREG_B0_P0_U0_CFG10, 0x4001004a +.set CYREG_B0_P0_U0_CFG11, 0x4001004b +.set CYREG_B0_P0_U0_CFG12, 0x4001004c +.set CYREG_B0_P0_U0_CFG13, 0x4001004d +.set CYREG_B0_P0_U0_CFG14, 0x4001004e +.set CYREG_B0_P0_U0_CFG15, 0x4001004f +.set CYREG_B0_P0_U0_CFG16, 0x40010050 +.set CYREG_B0_P0_U0_CFG17, 0x40010051 +.set CYREG_B0_P0_U0_CFG18, 0x40010052 +.set CYREG_B0_P0_U0_CFG19, 0x40010053 +.set CYREG_B0_P0_U0_CFG20, 0x40010054 +.set CYREG_B0_P0_U0_CFG21, 0x40010055 +.set CYREG_B0_P0_U0_CFG22, 0x40010056 +.set CYREG_B0_P0_U0_CFG23, 0x40010057 +.set CYREG_B0_P0_U0_CFG24, 0x40010058 +.set CYREG_B0_P0_U0_CFG25, 0x40010059 +.set CYREG_B0_P0_U0_CFG26, 0x4001005a +.set CYREG_B0_P0_U0_CFG27, 0x4001005b +.set CYREG_B0_P0_U0_CFG28, 0x4001005c +.set CYREG_B0_P0_U0_CFG29, 0x4001005d +.set CYREG_B0_P0_U0_CFG30, 0x4001005e +.set CYREG_B0_P0_U0_CFG31, 0x4001005f +.set CYREG_B0_P0_U0_DCFG0, 0x40010060 +.set CYREG_B0_P0_U0_DCFG1, 0x40010062 +.set CYREG_B0_P0_U0_DCFG2, 0x40010064 +.set CYREG_B0_P0_U0_DCFG3, 0x40010066 +.set CYREG_B0_P0_U0_DCFG4, 0x40010068 +.set CYREG_B0_P0_U0_DCFG5, 0x4001006a +.set CYREG_B0_P0_U0_DCFG6, 0x4001006c +.set CYREG_B0_P0_U0_DCFG7, 0x4001006e +.set CYDEV_UCFG_B0_P0_U1_BASE, 0x40010080 +.set CYDEV_UCFG_B0_P0_U1_SIZE, 0x00000070 +.set CYREG_B0_P0_U1_PLD_IT0, 0x40010080 +.set CYREG_B0_P0_U1_PLD_IT1, 0x40010084 +.set CYREG_B0_P0_U1_PLD_IT2, 0x40010088 +.set CYREG_B0_P0_U1_PLD_IT3, 0x4001008c +.set CYREG_B0_P0_U1_PLD_IT4, 0x40010090 +.set CYREG_B0_P0_U1_PLD_IT5, 0x40010094 +.set CYREG_B0_P0_U1_PLD_IT6, 0x40010098 +.set CYREG_B0_P0_U1_PLD_IT7, 0x4001009c +.set CYREG_B0_P0_U1_PLD_IT8, 0x400100a0 +.set CYREG_B0_P0_U1_PLD_IT9, 0x400100a4 +.set CYREG_B0_P0_U1_PLD_IT10, 0x400100a8 +.set CYREG_B0_P0_U1_PLD_IT11, 0x400100ac +.set CYREG_B0_P0_U1_PLD_ORT0, 0x400100b0 +.set CYREG_B0_P0_U1_PLD_ORT1, 0x400100b2 +.set CYREG_B0_P0_U1_PLD_ORT2, 0x400100b4 +.set CYREG_B0_P0_U1_PLD_ORT3, 0x400100b6 +.set CYREG_B0_P0_U1_MC_CFG_CEN_CONST, 0x400100b8 +.set CYREG_B0_P0_U1_MC_CFG_XORFB, 0x400100ba +.set CYREG_B0_P0_U1_MC_CFG_SET_RESET, 0x400100bc +.set CYREG_B0_P0_U1_MC_CFG_BYPASS, 0x400100be +.set CYREG_B0_P0_U1_CFG0, 0x400100c0 +.set CYREG_B0_P0_U1_CFG1, 0x400100c1 +.set CYREG_B0_P0_U1_CFG2, 0x400100c2 +.set CYREG_B0_P0_U1_CFG3, 0x400100c3 +.set CYREG_B0_P0_U1_CFG4, 0x400100c4 +.set CYREG_B0_P0_U1_CFG5, 0x400100c5 +.set CYREG_B0_P0_U1_CFG6, 0x400100c6 +.set CYREG_B0_P0_U1_CFG7, 0x400100c7 +.set CYREG_B0_P0_U1_CFG8, 0x400100c8 +.set CYREG_B0_P0_U1_CFG9, 0x400100c9 +.set CYREG_B0_P0_U1_CFG10, 0x400100ca +.set CYREG_B0_P0_U1_CFG11, 0x400100cb +.set CYREG_B0_P0_U1_CFG12, 0x400100cc +.set CYREG_B0_P0_U1_CFG13, 0x400100cd +.set CYREG_B0_P0_U1_CFG14, 0x400100ce +.set CYREG_B0_P0_U1_CFG15, 0x400100cf +.set CYREG_B0_P0_U1_CFG16, 0x400100d0 +.set CYREG_B0_P0_U1_CFG17, 0x400100d1 +.set CYREG_B0_P0_U1_CFG18, 0x400100d2 +.set CYREG_B0_P0_U1_CFG19, 0x400100d3 +.set CYREG_B0_P0_U1_CFG20, 0x400100d4 +.set CYREG_B0_P0_U1_CFG21, 0x400100d5 +.set CYREG_B0_P0_U1_CFG22, 0x400100d6 +.set CYREG_B0_P0_U1_CFG23, 0x400100d7 +.set CYREG_B0_P0_U1_CFG24, 0x400100d8 +.set CYREG_B0_P0_U1_CFG25, 0x400100d9 +.set CYREG_B0_P0_U1_CFG26, 0x400100da +.set CYREG_B0_P0_U1_CFG27, 0x400100db +.set CYREG_B0_P0_U1_CFG28, 0x400100dc +.set CYREG_B0_P0_U1_CFG29, 0x400100dd +.set CYREG_B0_P0_U1_CFG30, 0x400100de +.set CYREG_B0_P0_U1_CFG31, 0x400100df +.set CYREG_B0_P0_U1_DCFG0, 0x400100e0 +.set CYREG_B0_P0_U1_DCFG1, 0x400100e2 +.set CYREG_B0_P0_U1_DCFG2, 0x400100e4 +.set CYREG_B0_P0_U1_DCFG3, 0x400100e6 +.set CYREG_B0_P0_U1_DCFG4, 0x400100e8 +.set CYREG_B0_P0_U1_DCFG5, 0x400100ea +.set CYREG_B0_P0_U1_DCFG6, 0x400100ec +.set CYREG_B0_P0_U1_DCFG7, 0x400100ee +.set CYDEV_UCFG_B0_P0_ROUTE_BASE, 0x40010100 +.set CYDEV_UCFG_B0_P0_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P1_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P1_U0_BASE, 0x40010200 +.set CYDEV_UCFG_B0_P1_U0_SIZE, 0x00000070 +.set CYREG_B0_P1_U0_PLD_IT0, 0x40010200 +.set CYREG_B0_P1_U0_PLD_IT1, 0x40010204 +.set CYREG_B0_P1_U0_PLD_IT2, 0x40010208 +.set CYREG_B0_P1_U0_PLD_IT3, 0x4001020c +.set CYREG_B0_P1_U0_PLD_IT4, 0x40010210 +.set CYREG_B0_P1_U0_PLD_IT5, 0x40010214 +.set CYREG_B0_P1_U0_PLD_IT6, 0x40010218 +.set CYREG_B0_P1_U0_PLD_IT7, 0x4001021c +.set CYREG_B0_P1_U0_PLD_IT8, 0x40010220 +.set CYREG_B0_P1_U0_PLD_IT9, 0x40010224 +.set CYREG_B0_P1_U0_PLD_IT10, 0x40010228 +.set CYREG_B0_P1_U0_PLD_IT11, 0x4001022c +.set CYREG_B0_P1_U0_PLD_ORT0, 0x40010230 +.set CYREG_B0_P1_U0_PLD_ORT1, 0x40010232 +.set CYREG_B0_P1_U0_PLD_ORT2, 0x40010234 +.set CYREG_B0_P1_U0_PLD_ORT3, 0x40010236 +.set CYREG_B0_P1_U0_MC_CFG_CEN_CONST, 0x40010238 +.set CYREG_B0_P1_U0_MC_CFG_XORFB, 0x4001023a +.set CYREG_B0_P1_U0_MC_CFG_SET_RESET, 0x4001023c +.set CYREG_B0_P1_U0_MC_CFG_BYPASS, 0x4001023e +.set CYREG_B0_P1_U0_CFG0, 0x40010240 +.set CYREG_B0_P1_U0_CFG1, 0x40010241 +.set CYREG_B0_P1_U0_CFG2, 0x40010242 +.set CYREG_B0_P1_U0_CFG3, 0x40010243 +.set CYREG_B0_P1_U0_CFG4, 0x40010244 +.set CYREG_B0_P1_U0_CFG5, 0x40010245 +.set CYREG_B0_P1_U0_CFG6, 0x40010246 +.set CYREG_B0_P1_U0_CFG7, 0x40010247 +.set CYREG_B0_P1_U0_CFG8, 0x40010248 +.set CYREG_B0_P1_U0_CFG9, 0x40010249 +.set CYREG_B0_P1_U0_CFG10, 0x4001024a +.set CYREG_B0_P1_U0_CFG11, 0x4001024b +.set CYREG_B0_P1_U0_CFG12, 0x4001024c +.set CYREG_B0_P1_U0_CFG13, 0x4001024d +.set CYREG_B0_P1_U0_CFG14, 0x4001024e +.set CYREG_B0_P1_U0_CFG15, 0x4001024f +.set CYREG_B0_P1_U0_CFG16, 0x40010250 +.set CYREG_B0_P1_U0_CFG17, 0x40010251 +.set CYREG_B0_P1_U0_CFG18, 0x40010252 +.set CYREG_B0_P1_U0_CFG19, 0x40010253 +.set CYREG_B0_P1_U0_CFG20, 0x40010254 +.set CYREG_B0_P1_U0_CFG21, 0x40010255 +.set CYREG_B0_P1_U0_CFG22, 0x40010256 +.set CYREG_B0_P1_U0_CFG23, 0x40010257 +.set CYREG_B0_P1_U0_CFG24, 0x40010258 +.set CYREG_B0_P1_U0_CFG25, 0x40010259 +.set CYREG_B0_P1_U0_CFG26, 0x4001025a +.set CYREG_B0_P1_U0_CFG27, 0x4001025b +.set CYREG_B0_P1_U0_CFG28, 0x4001025c +.set CYREG_B0_P1_U0_CFG29, 0x4001025d +.set CYREG_B0_P1_U0_CFG30, 0x4001025e +.set CYREG_B0_P1_U0_CFG31, 0x4001025f +.set CYREG_B0_P1_U0_DCFG0, 0x40010260 +.set CYREG_B0_P1_U0_DCFG1, 0x40010262 +.set CYREG_B0_P1_U0_DCFG2, 0x40010264 +.set CYREG_B0_P1_U0_DCFG3, 0x40010266 +.set CYREG_B0_P1_U0_DCFG4, 0x40010268 +.set CYREG_B0_P1_U0_DCFG5, 0x4001026a +.set CYREG_B0_P1_U0_DCFG6, 0x4001026c +.set CYREG_B0_P1_U0_DCFG7, 0x4001026e +.set CYDEV_UCFG_B0_P1_U1_BASE, 0x40010280 +.set CYDEV_UCFG_B0_P1_U1_SIZE, 0x00000070 +.set CYREG_B0_P1_U1_PLD_IT0, 0x40010280 +.set CYREG_B0_P1_U1_PLD_IT1, 0x40010284 +.set CYREG_B0_P1_U1_PLD_IT2, 0x40010288 +.set CYREG_B0_P1_U1_PLD_IT3, 0x4001028c +.set CYREG_B0_P1_U1_PLD_IT4, 0x40010290 +.set CYREG_B0_P1_U1_PLD_IT5, 0x40010294 +.set CYREG_B0_P1_U1_PLD_IT6, 0x40010298 +.set CYREG_B0_P1_U1_PLD_IT7, 0x4001029c +.set CYREG_B0_P1_U1_PLD_IT8, 0x400102a0 +.set CYREG_B0_P1_U1_PLD_IT9, 0x400102a4 +.set CYREG_B0_P1_U1_PLD_IT10, 0x400102a8 +.set CYREG_B0_P1_U1_PLD_IT11, 0x400102ac +.set CYREG_B0_P1_U1_PLD_ORT0, 0x400102b0 +.set CYREG_B0_P1_U1_PLD_ORT1, 0x400102b2 +.set CYREG_B0_P1_U1_PLD_ORT2, 0x400102b4 +.set CYREG_B0_P1_U1_PLD_ORT3, 0x400102b6 +.set CYREG_B0_P1_U1_MC_CFG_CEN_CONST, 0x400102b8 +.set CYREG_B0_P1_U1_MC_CFG_XORFB, 0x400102ba +.set CYREG_B0_P1_U1_MC_CFG_SET_RESET, 0x400102bc +.set CYREG_B0_P1_U1_MC_CFG_BYPASS, 0x400102be +.set CYREG_B0_P1_U1_CFG0, 0x400102c0 +.set CYREG_B0_P1_U1_CFG1, 0x400102c1 +.set CYREG_B0_P1_U1_CFG2, 0x400102c2 +.set CYREG_B0_P1_U1_CFG3, 0x400102c3 +.set CYREG_B0_P1_U1_CFG4, 0x400102c4 +.set CYREG_B0_P1_U1_CFG5, 0x400102c5 +.set CYREG_B0_P1_U1_CFG6, 0x400102c6 +.set CYREG_B0_P1_U1_CFG7, 0x400102c7 +.set CYREG_B0_P1_U1_CFG8, 0x400102c8 +.set CYREG_B0_P1_U1_CFG9, 0x400102c9 +.set CYREG_B0_P1_U1_CFG10, 0x400102ca +.set CYREG_B0_P1_U1_CFG11, 0x400102cb +.set CYREG_B0_P1_U1_CFG12, 0x400102cc +.set CYREG_B0_P1_U1_CFG13, 0x400102cd +.set CYREG_B0_P1_U1_CFG14, 0x400102ce +.set CYREG_B0_P1_U1_CFG15, 0x400102cf +.set CYREG_B0_P1_U1_CFG16, 0x400102d0 +.set CYREG_B0_P1_U1_CFG17, 0x400102d1 +.set CYREG_B0_P1_U1_CFG18, 0x400102d2 +.set CYREG_B0_P1_U1_CFG19, 0x400102d3 +.set CYREG_B0_P1_U1_CFG20, 0x400102d4 +.set CYREG_B0_P1_U1_CFG21, 0x400102d5 +.set CYREG_B0_P1_U1_CFG22, 0x400102d6 +.set CYREG_B0_P1_U1_CFG23, 0x400102d7 +.set CYREG_B0_P1_U1_CFG24, 0x400102d8 +.set CYREG_B0_P1_U1_CFG25, 0x400102d9 +.set CYREG_B0_P1_U1_CFG26, 0x400102da +.set CYREG_B0_P1_U1_CFG27, 0x400102db +.set CYREG_B0_P1_U1_CFG28, 0x400102dc +.set CYREG_B0_P1_U1_CFG29, 0x400102dd +.set CYREG_B0_P1_U1_CFG30, 0x400102de +.set CYREG_B0_P1_U1_CFG31, 0x400102df +.set CYREG_B0_P1_U1_DCFG0, 0x400102e0 +.set CYREG_B0_P1_U1_DCFG1, 0x400102e2 +.set CYREG_B0_P1_U1_DCFG2, 0x400102e4 +.set CYREG_B0_P1_U1_DCFG3, 0x400102e6 +.set CYREG_B0_P1_U1_DCFG4, 0x400102e8 +.set CYREG_B0_P1_U1_DCFG5, 0x400102ea +.set CYREG_B0_P1_U1_DCFG6, 0x400102ec +.set CYREG_B0_P1_U1_DCFG7, 0x400102ee +.set CYDEV_UCFG_B0_P1_ROUTE_BASE, 0x40010300 +.set CYDEV_UCFG_B0_P1_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P2_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P2_U0_BASE, 0x40010400 +.set CYDEV_UCFG_B0_P2_U0_SIZE, 0x00000070 +.set CYREG_B0_P2_U0_PLD_IT0, 0x40010400 +.set CYREG_B0_P2_U0_PLD_IT1, 0x40010404 +.set CYREG_B0_P2_U0_PLD_IT2, 0x40010408 +.set CYREG_B0_P2_U0_PLD_IT3, 0x4001040c +.set CYREG_B0_P2_U0_PLD_IT4, 0x40010410 +.set CYREG_B0_P2_U0_PLD_IT5, 0x40010414 +.set CYREG_B0_P2_U0_PLD_IT6, 0x40010418 +.set CYREG_B0_P2_U0_PLD_IT7, 0x4001041c +.set CYREG_B0_P2_U0_PLD_IT8, 0x40010420 +.set CYREG_B0_P2_U0_PLD_IT9, 0x40010424 +.set CYREG_B0_P2_U0_PLD_IT10, 0x40010428 +.set CYREG_B0_P2_U0_PLD_IT11, 0x4001042c +.set CYREG_B0_P2_U0_PLD_ORT0, 0x40010430 +.set CYREG_B0_P2_U0_PLD_ORT1, 0x40010432 +.set CYREG_B0_P2_U0_PLD_ORT2, 0x40010434 +.set CYREG_B0_P2_U0_PLD_ORT3, 0x40010436 +.set CYREG_B0_P2_U0_MC_CFG_CEN_CONST, 0x40010438 +.set CYREG_B0_P2_U0_MC_CFG_XORFB, 0x4001043a +.set CYREG_B0_P2_U0_MC_CFG_SET_RESET, 0x4001043c +.set CYREG_B0_P2_U0_MC_CFG_BYPASS, 0x4001043e +.set CYREG_B0_P2_U0_CFG0, 0x40010440 +.set CYREG_B0_P2_U0_CFG1, 0x40010441 +.set CYREG_B0_P2_U0_CFG2, 0x40010442 +.set CYREG_B0_P2_U0_CFG3, 0x40010443 +.set CYREG_B0_P2_U0_CFG4, 0x40010444 +.set CYREG_B0_P2_U0_CFG5, 0x40010445 +.set CYREG_B0_P2_U0_CFG6, 0x40010446 +.set CYREG_B0_P2_U0_CFG7, 0x40010447 +.set CYREG_B0_P2_U0_CFG8, 0x40010448 +.set CYREG_B0_P2_U0_CFG9, 0x40010449 +.set CYREG_B0_P2_U0_CFG10, 0x4001044a +.set CYREG_B0_P2_U0_CFG11, 0x4001044b +.set CYREG_B0_P2_U0_CFG12, 0x4001044c +.set CYREG_B0_P2_U0_CFG13, 0x4001044d +.set CYREG_B0_P2_U0_CFG14, 0x4001044e +.set CYREG_B0_P2_U0_CFG15, 0x4001044f +.set CYREG_B0_P2_U0_CFG16, 0x40010450 +.set CYREG_B0_P2_U0_CFG17, 0x40010451 +.set CYREG_B0_P2_U0_CFG18, 0x40010452 +.set CYREG_B0_P2_U0_CFG19, 0x40010453 +.set CYREG_B0_P2_U0_CFG20, 0x40010454 +.set CYREG_B0_P2_U0_CFG21, 0x40010455 +.set CYREG_B0_P2_U0_CFG22, 0x40010456 +.set CYREG_B0_P2_U0_CFG23, 0x40010457 +.set CYREG_B0_P2_U0_CFG24, 0x40010458 +.set CYREG_B0_P2_U0_CFG25, 0x40010459 +.set CYREG_B0_P2_U0_CFG26, 0x4001045a +.set CYREG_B0_P2_U0_CFG27, 0x4001045b +.set CYREG_B0_P2_U0_CFG28, 0x4001045c +.set CYREG_B0_P2_U0_CFG29, 0x4001045d +.set CYREG_B0_P2_U0_CFG30, 0x4001045e +.set CYREG_B0_P2_U0_CFG31, 0x4001045f +.set CYREG_B0_P2_U0_DCFG0, 0x40010460 +.set CYREG_B0_P2_U0_DCFG1, 0x40010462 +.set CYREG_B0_P2_U0_DCFG2, 0x40010464 +.set CYREG_B0_P2_U0_DCFG3, 0x40010466 +.set CYREG_B0_P2_U0_DCFG4, 0x40010468 +.set CYREG_B0_P2_U0_DCFG5, 0x4001046a +.set CYREG_B0_P2_U0_DCFG6, 0x4001046c +.set CYREG_B0_P2_U0_DCFG7, 0x4001046e +.set CYDEV_UCFG_B0_P2_U1_BASE, 0x40010480 +.set CYDEV_UCFG_B0_P2_U1_SIZE, 0x00000070 +.set CYREG_B0_P2_U1_PLD_IT0, 0x40010480 +.set CYREG_B0_P2_U1_PLD_IT1, 0x40010484 +.set CYREG_B0_P2_U1_PLD_IT2, 0x40010488 +.set CYREG_B0_P2_U1_PLD_IT3, 0x4001048c +.set CYREG_B0_P2_U1_PLD_IT4, 0x40010490 +.set CYREG_B0_P2_U1_PLD_IT5, 0x40010494 +.set CYREG_B0_P2_U1_PLD_IT6, 0x40010498 +.set CYREG_B0_P2_U1_PLD_IT7, 0x4001049c +.set CYREG_B0_P2_U1_PLD_IT8, 0x400104a0 +.set CYREG_B0_P2_U1_PLD_IT9, 0x400104a4 +.set CYREG_B0_P2_U1_PLD_IT10, 0x400104a8 +.set CYREG_B0_P2_U1_PLD_IT11, 0x400104ac +.set CYREG_B0_P2_U1_PLD_ORT0, 0x400104b0 +.set CYREG_B0_P2_U1_PLD_ORT1, 0x400104b2 +.set CYREG_B0_P2_U1_PLD_ORT2, 0x400104b4 +.set CYREG_B0_P2_U1_PLD_ORT3, 0x400104b6 +.set CYREG_B0_P2_U1_MC_CFG_CEN_CONST, 0x400104b8 +.set CYREG_B0_P2_U1_MC_CFG_XORFB, 0x400104ba +.set CYREG_B0_P2_U1_MC_CFG_SET_RESET, 0x400104bc +.set CYREG_B0_P2_U1_MC_CFG_BYPASS, 0x400104be +.set CYREG_B0_P2_U1_CFG0, 0x400104c0 +.set CYREG_B0_P2_U1_CFG1, 0x400104c1 +.set CYREG_B0_P2_U1_CFG2, 0x400104c2 +.set CYREG_B0_P2_U1_CFG3, 0x400104c3 +.set CYREG_B0_P2_U1_CFG4, 0x400104c4 +.set CYREG_B0_P2_U1_CFG5, 0x400104c5 +.set CYREG_B0_P2_U1_CFG6, 0x400104c6 +.set CYREG_B0_P2_U1_CFG7, 0x400104c7 +.set CYREG_B0_P2_U1_CFG8, 0x400104c8 +.set CYREG_B0_P2_U1_CFG9, 0x400104c9 +.set CYREG_B0_P2_U1_CFG10, 0x400104ca +.set CYREG_B0_P2_U1_CFG11, 0x400104cb +.set CYREG_B0_P2_U1_CFG12, 0x400104cc +.set CYREG_B0_P2_U1_CFG13, 0x400104cd +.set CYREG_B0_P2_U1_CFG14, 0x400104ce +.set CYREG_B0_P2_U1_CFG15, 0x400104cf +.set CYREG_B0_P2_U1_CFG16, 0x400104d0 +.set CYREG_B0_P2_U1_CFG17, 0x400104d1 +.set CYREG_B0_P2_U1_CFG18, 0x400104d2 +.set CYREG_B0_P2_U1_CFG19, 0x400104d3 +.set CYREG_B0_P2_U1_CFG20, 0x400104d4 +.set CYREG_B0_P2_U1_CFG21, 0x400104d5 +.set CYREG_B0_P2_U1_CFG22, 0x400104d6 +.set CYREG_B0_P2_U1_CFG23, 0x400104d7 +.set CYREG_B0_P2_U1_CFG24, 0x400104d8 +.set CYREG_B0_P2_U1_CFG25, 0x400104d9 +.set CYREG_B0_P2_U1_CFG26, 0x400104da +.set CYREG_B0_P2_U1_CFG27, 0x400104db +.set CYREG_B0_P2_U1_CFG28, 0x400104dc +.set CYREG_B0_P2_U1_CFG29, 0x400104dd +.set CYREG_B0_P2_U1_CFG30, 0x400104de +.set CYREG_B0_P2_U1_CFG31, 0x400104df +.set CYREG_B0_P2_U1_DCFG0, 0x400104e0 +.set CYREG_B0_P2_U1_DCFG1, 0x400104e2 +.set CYREG_B0_P2_U1_DCFG2, 0x400104e4 +.set CYREG_B0_P2_U1_DCFG3, 0x400104e6 +.set CYREG_B0_P2_U1_DCFG4, 0x400104e8 +.set CYREG_B0_P2_U1_DCFG5, 0x400104ea +.set CYREG_B0_P2_U1_DCFG6, 0x400104ec +.set CYREG_B0_P2_U1_DCFG7, 0x400104ee +.set CYDEV_UCFG_B0_P2_ROUTE_BASE, 0x40010500 +.set CYDEV_UCFG_B0_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P3_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P3_U0_BASE, 0x40010600 +.set CYDEV_UCFG_B0_P3_U0_SIZE, 0x00000070 +.set CYREG_B0_P3_U0_PLD_IT0, 0x40010600 +.set CYREG_B0_P3_U0_PLD_IT1, 0x40010604 +.set CYREG_B0_P3_U0_PLD_IT2, 0x40010608 +.set CYREG_B0_P3_U0_PLD_IT3, 0x4001060c +.set CYREG_B0_P3_U0_PLD_IT4, 0x40010610 +.set CYREG_B0_P3_U0_PLD_IT5, 0x40010614 +.set CYREG_B0_P3_U0_PLD_IT6, 0x40010618 +.set CYREG_B0_P3_U0_PLD_IT7, 0x4001061c +.set CYREG_B0_P3_U0_PLD_IT8, 0x40010620 +.set CYREG_B0_P3_U0_PLD_IT9, 0x40010624 +.set CYREG_B0_P3_U0_PLD_IT10, 0x40010628 +.set CYREG_B0_P3_U0_PLD_IT11, 0x4001062c +.set CYREG_B0_P3_U0_PLD_ORT0, 0x40010630 +.set CYREG_B0_P3_U0_PLD_ORT1, 0x40010632 +.set CYREG_B0_P3_U0_PLD_ORT2, 0x40010634 +.set CYREG_B0_P3_U0_PLD_ORT3, 0x40010636 +.set CYREG_B0_P3_U0_MC_CFG_CEN_CONST, 0x40010638 +.set CYREG_B0_P3_U0_MC_CFG_XORFB, 0x4001063a +.set CYREG_B0_P3_U0_MC_CFG_SET_RESET, 0x4001063c +.set CYREG_B0_P3_U0_MC_CFG_BYPASS, 0x4001063e +.set CYREG_B0_P3_U0_CFG0, 0x40010640 +.set CYREG_B0_P3_U0_CFG1, 0x40010641 +.set CYREG_B0_P3_U0_CFG2, 0x40010642 +.set CYREG_B0_P3_U0_CFG3, 0x40010643 +.set CYREG_B0_P3_U0_CFG4, 0x40010644 +.set CYREG_B0_P3_U0_CFG5, 0x40010645 +.set CYREG_B0_P3_U0_CFG6, 0x40010646 +.set CYREG_B0_P3_U0_CFG7, 0x40010647 +.set CYREG_B0_P3_U0_CFG8, 0x40010648 +.set CYREG_B0_P3_U0_CFG9, 0x40010649 +.set CYREG_B0_P3_U0_CFG10, 0x4001064a +.set CYREG_B0_P3_U0_CFG11, 0x4001064b +.set CYREG_B0_P3_U0_CFG12, 0x4001064c +.set CYREG_B0_P3_U0_CFG13, 0x4001064d +.set CYREG_B0_P3_U0_CFG14, 0x4001064e +.set CYREG_B0_P3_U0_CFG15, 0x4001064f +.set CYREG_B0_P3_U0_CFG16, 0x40010650 +.set CYREG_B0_P3_U0_CFG17, 0x40010651 +.set CYREG_B0_P3_U0_CFG18, 0x40010652 +.set CYREG_B0_P3_U0_CFG19, 0x40010653 +.set CYREG_B0_P3_U0_CFG20, 0x40010654 +.set CYREG_B0_P3_U0_CFG21, 0x40010655 +.set CYREG_B0_P3_U0_CFG22, 0x40010656 +.set CYREG_B0_P3_U0_CFG23, 0x40010657 +.set CYREG_B0_P3_U0_CFG24, 0x40010658 +.set CYREG_B0_P3_U0_CFG25, 0x40010659 +.set CYREG_B0_P3_U0_CFG26, 0x4001065a +.set CYREG_B0_P3_U0_CFG27, 0x4001065b +.set CYREG_B0_P3_U0_CFG28, 0x4001065c +.set CYREG_B0_P3_U0_CFG29, 0x4001065d +.set CYREG_B0_P3_U0_CFG30, 0x4001065e +.set CYREG_B0_P3_U0_CFG31, 0x4001065f +.set CYREG_B0_P3_U0_DCFG0, 0x40010660 +.set CYREG_B0_P3_U0_DCFG1, 0x40010662 +.set CYREG_B0_P3_U0_DCFG2, 0x40010664 +.set CYREG_B0_P3_U0_DCFG3, 0x40010666 +.set CYREG_B0_P3_U0_DCFG4, 0x40010668 +.set CYREG_B0_P3_U0_DCFG5, 0x4001066a +.set CYREG_B0_P3_U0_DCFG6, 0x4001066c +.set CYREG_B0_P3_U0_DCFG7, 0x4001066e +.set CYDEV_UCFG_B0_P3_U1_BASE, 0x40010680 +.set CYDEV_UCFG_B0_P3_U1_SIZE, 0x00000070 +.set CYREG_B0_P3_U1_PLD_IT0, 0x40010680 +.set CYREG_B0_P3_U1_PLD_IT1, 0x40010684 +.set CYREG_B0_P3_U1_PLD_IT2, 0x40010688 +.set CYREG_B0_P3_U1_PLD_IT3, 0x4001068c +.set CYREG_B0_P3_U1_PLD_IT4, 0x40010690 +.set CYREG_B0_P3_U1_PLD_IT5, 0x40010694 +.set CYREG_B0_P3_U1_PLD_IT6, 0x40010698 +.set CYREG_B0_P3_U1_PLD_IT7, 0x4001069c +.set CYREG_B0_P3_U1_PLD_IT8, 0x400106a0 +.set CYREG_B0_P3_U1_PLD_IT9, 0x400106a4 +.set CYREG_B0_P3_U1_PLD_IT10, 0x400106a8 +.set CYREG_B0_P3_U1_PLD_IT11, 0x400106ac +.set CYREG_B0_P3_U1_PLD_ORT0, 0x400106b0 +.set CYREG_B0_P3_U1_PLD_ORT1, 0x400106b2 +.set CYREG_B0_P3_U1_PLD_ORT2, 0x400106b4 +.set CYREG_B0_P3_U1_PLD_ORT3, 0x400106b6 +.set CYREG_B0_P3_U1_MC_CFG_CEN_CONST, 0x400106b8 +.set CYREG_B0_P3_U1_MC_CFG_XORFB, 0x400106ba +.set CYREG_B0_P3_U1_MC_CFG_SET_RESET, 0x400106bc +.set CYREG_B0_P3_U1_MC_CFG_BYPASS, 0x400106be +.set CYREG_B0_P3_U1_CFG0, 0x400106c0 +.set CYREG_B0_P3_U1_CFG1, 0x400106c1 +.set CYREG_B0_P3_U1_CFG2, 0x400106c2 +.set CYREG_B0_P3_U1_CFG3, 0x400106c3 +.set CYREG_B0_P3_U1_CFG4, 0x400106c4 +.set CYREG_B0_P3_U1_CFG5, 0x400106c5 +.set CYREG_B0_P3_U1_CFG6, 0x400106c6 +.set CYREG_B0_P3_U1_CFG7, 0x400106c7 +.set CYREG_B0_P3_U1_CFG8, 0x400106c8 +.set CYREG_B0_P3_U1_CFG9, 0x400106c9 +.set CYREG_B0_P3_U1_CFG10, 0x400106ca +.set CYREG_B0_P3_U1_CFG11, 0x400106cb +.set CYREG_B0_P3_U1_CFG12, 0x400106cc +.set CYREG_B0_P3_U1_CFG13, 0x400106cd +.set CYREG_B0_P3_U1_CFG14, 0x400106ce +.set CYREG_B0_P3_U1_CFG15, 0x400106cf +.set CYREG_B0_P3_U1_CFG16, 0x400106d0 +.set CYREG_B0_P3_U1_CFG17, 0x400106d1 +.set CYREG_B0_P3_U1_CFG18, 0x400106d2 +.set CYREG_B0_P3_U1_CFG19, 0x400106d3 +.set CYREG_B0_P3_U1_CFG20, 0x400106d4 +.set CYREG_B0_P3_U1_CFG21, 0x400106d5 +.set CYREG_B0_P3_U1_CFG22, 0x400106d6 +.set CYREG_B0_P3_U1_CFG23, 0x400106d7 +.set CYREG_B0_P3_U1_CFG24, 0x400106d8 +.set CYREG_B0_P3_U1_CFG25, 0x400106d9 +.set CYREG_B0_P3_U1_CFG26, 0x400106da +.set CYREG_B0_P3_U1_CFG27, 0x400106db +.set CYREG_B0_P3_U1_CFG28, 0x400106dc +.set CYREG_B0_P3_U1_CFG29, 0x400106dd +.set CYREG_B0_P3_U1_CFG30, 0x400106de +.set CYREG_B0_P3_U1_CFG31, 0x400106df +.set CYREG_B0_P3_U1_DCFG0, 0x400106e0 +.set CYREG_B0_P3_U1_DCFG1, 0x400106e2 +.set CYREG_B0_P3_U1_DCFG2, 0x400106e4 +.set CYREG_B0_P3_U1_DCFG3, 0x400106e6 +.set CYREG_B0_P3_U1_DCFG4, 0x400106e8 +.set CYREG_B0_P3_U1_DCFG5, 0x400106ea +.set CYREG_B0_P3_U1_DCFG6, 0x400106ec +.set CYREG_B0_P3_U1_DCFG7, 0x400106ee +.set CYDEV_UCFG_B0_P3_ROUTE_BASE, 0x40010700 +.set CYDEV_UCFG_B0_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P4_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P4_U0_BASE, 0x40010800 +.set CYDEV_UCFG_B0_P4_U0_SIZE, 0x00000070 +.set CYREG_B0_P4_U0_PLD_IT0, 0x40010800 +.set CYREG_B0_P4_U0_PLD_IT1, 0x40010804 +.set CYREG_B0_P4_U0_PLD_IT2, 0x40010808 +.set CYREG_B0_P4_U0_PLD_IT3, 0x4001080c +.set CYREG_B0_P4_U0_PLD_IT4, 0x40010810 +.set CYREG_B0_P4_U0_PLD_IT5, 0x40010814 +.set CYREG_B0_P4_U0_PLD_IT6, 0x40010818 +.set CYREG_B0_P4_U0_PLD_IT7, 0x4001081c +.set CYREG_B0_P4_U0_PLD_IT8, 0x40010820 +.set CYREG_B0_P4_U0_PLD_IT9, 0x40010824 +.set CYREG_B0_P4_U0_PLD_IT10, 0x40010828 +.set CYREG_B0_P4_U0_PLD_IT11, 0x4001082c +.set CYREG_B0_P4_U0_PLD_ORT0, 0x40010830 +.set CYREG_B0_P4_U0_PLD_ORT1, 0x40010832 +.set CYREG_B0_P4_U0_PLD_ORT2, 0x40010834 +.set CYREG_B0_P4_U0_PLD_ORT3, 0x40010836 +.set CYREG_B0_P4_U0_MC_CFG_CEN_CONST, 0x40010838 +.set CYREG_B0_P4_U0_MC_CFG_XORFB, 0x4001083a +.set CYREG_B0_P4_U0_MC_CFG_SET_RESET, 0x4001083c +.set CYREG_B0_P4_U0_MC_CFG_BYPASS, 0x4001083e +.set CYREG_B0_P4_U0_CFG0, 0x40010840 +.set CYREG_B0_P4_U0_CFG1, 0x40010841 +.set CYREG_B0_P4_U0_CFG2, 0x40010842 +.set CYREG_B0_P4_U0_CFG3, 0x40010843 +.set CYREG_B0_P4_U0_CFG4, 0x40010844 +.set CYREG_B0_P4_U0_CFG5, 0x40010845 +.set CYREG_B0_P4_U0_CFG6, 0x40010846 +.set CYREG_B0_P4_U0_CFG7, 0x40010847 +.set CYREG_B0_P4_U0_CFG8, 0x40010848 +.set CYREG_B0_P4_U0_CFG9, 0x40010849 +.set CYREG_B0_P4_U0_CFG10, 0x4001084a +.set CYREG_B0_P4_U0_CFG11, 0x4001084b +.set CYREG_B0_P4_U0_CFG12, 0x4001084c +.set CYREG_B0_P4_U0_CFG13, 0x4001084d +.set CYREG_B0_P4_U0_CFG14, 0x4001084e +.set CYREG_B0_P4_U0_CFG15, 0x4001084f +.set CYREG_B0_P4_U0_CFG16, 0x40010850 +.set CYREG_B0_P4_U0_CFG17, 0x40010851 +.set CYREG_B0_P4_U0_CFG18, 0x40010852 +.set CYREG_B0_P4_U0_CFG19, 0x40010853 +.set CYREG_B0_P4_U0_CFG20, 0x40010854 +.set CYREG_B0_P4_U0_CFG21, 0x40010855 +.set CYREG_B0_P4_U0_CFG22, 0x40010856 +.set CYREG_B0_P4_U0_CFG23, 0x40010857 +.set CYREG_B0_P4_U0_CFG24, 0x40010858 +.set CYREG_B0_P4_U0_CFG25, 0x40010859 +.set CYREG_B0_P4_U0_CFG26, 0x4001085a +.set CYREG_B0_P4_U0_CFG27, 0x4001085b +.set CYREG_B0_P4_U0_CFG28, 0x4001085c +.set CYREG_B0_P4_U0_CFG29, 0x4001085d +.set CYREG_B0_P4_U0_CFG30, 0x4001085e +.set CYREG_B0_P4_U0_CFG31, 0x4001085f +.set CYREG_B0_P4_U0_DCFG0, 0x40010860 +.set CYREG_B0_P4_U0_DCFG1, 0x40010862 +.set CYREG_B0_P4_U0_DCFG2, 0x40010864 +.set CYREG_B0_P4_U0_DCFG3, 0x40010866 +.set CYREG_B0_P4_U0_DCFG4, 0x40010868 +.set CYREG_B0_P4_U0_DCFG5, 0x4001086a +.set CYREG_B0_P4_U0_DCFG6, 0x4001086c +.set CYREG_B0_P4_U0_DCFG7, 0x4001086e +.set CYDEV_UCFG_B0_P4_U1_BASE, 0x40010880 +.set CYDEV_UCFG_B0_P4_U1_SIZE, 0x00000070 +.set CYREG_B0_P4_U1_PLD_IT0, 0x40010880 +.set CYREG_B0_P4_U1_PLD_IT1, 0x40010884 +.set CYREG_B0_P4_U1_PLD_IT2, 0x40010888 +.set CYREG_B0_P4_U1_PLD_IT3, 0x4001088c +.set CYREG_B0_P4_U1_PLD_IT4, 0x40010890 +.set CYREG_B0_P4_U1_PLD_IT5, 0x40010894 +.set CYREG_B0_P4_U1_PLD_IT6, 0x40010898 +.set CYREG_B0_P4_U1_PLD_IT7, 0x4001089c +.set CYREG_B0_P4_U1_PLD_IT8, 0x400108a0 +.set CYREG_B0_P4_U1_PLD_IT9, 0x400108a4 +.set CYREG_B0_P4_U1_PLD_IT10, 0x400108a8 +.set CYREG_B0_P4_U1_PLD_IT11, 0x400108ac +.set CYREG_B0_P4_U1_PLD_ORT0, 0x400108b0 +.set CYREG_B0_P4_U1_PLD_ORT1, 0x400108b2 +.set CYREG_B0_P4_U1_PLD_ORT2, 0x400108b4 +.set CYREG_B0_P4_U1_PLD_ORT3, 0x400108b6 +.set CYREG_B0_P4_U1_MC_CFG_CEN_CONST, 0x400108b8 +.set CYREG_B0_P4_U1_MC_CFG_XORFB, 0x400108ba +.set CYREG_B0_P4_U1_MC_CFG_SET_RESET, 0x400108bc +.set CYREG_B0_P4_U1_MC_CFG_BYPASS, 0x400108be +.set CYREG_B0_P4_U1_CFG0, 0x400108c0 +.set CYREG_B0_P4_U1_CFG1, 0x400108c1 +.set CYREG_B0_P4_U1_CFG2, 0x400108c2 +.set CYREG_B0_P4_U1_CFG3, 0x400108c3 +.set CYREG_B0_P4_U1_CFG4, 0x400108c4 +.set CYREG_B0_P4_U1_CFG5, 0x400108c5 +.set CYREG_B0_P4_U1_CFG6, 0x400108c6 +.set CYREG_B0_P4_U1_CFG7, 0x400108c7 +.set CYREG_B0_P4_U1_CFG8, 0x400108c8 +.set CYREG_B0_P4_U1_CFG9, 0x400108c9 +.set CYREG_B0_P4_U1_CFG10, 0x400108ca +.set CYREG_B0_P4_U1_CFG11, 0x400108cb +.set CYREG_B0_P4_U1_CFG12, 0x400108cc +.set CYREG_B0_P4_U1_CFG13, 0x400108cd +.set CYREG_B0_P4_U1_CFG14, 0x400108ce +.set CYREG_B0_P4_U1_CFG15, 0x400108cf +.set CYREG_B0_P4_U1_CFG16, 0x400108d0 +.set CYREG_B0_P4_U1_CFG17, 0x400108d1 +.set CYREG_B0_P4_U1_CFG18, 0x400108d2 +.set CYREG_B0_P4_U1_CFG19, 0x400108d3 +.set CYREG_B0_P4_U1_CFG20, 0x400108d4 +.set CYREG_B0_P4_U1_CFG21, 0x400108d5 +.set CYREG_B0_P4_U1_CFG22, 0x400108d6 +.set CYREG_B0_P4_U1_CFG23, 0x400108d7 +.set CYREG_B0_P4_U1_CFG24, 0x400108d8 +.set CYREG_B0_P4_U1_CFG25, 0x400108d9 +.set CYREG_B0_P4_U1_CFG26, 0x400108da +.set CYREG_B0_P4_U1_CFG27, 0x400108db +.set CYREG_B0_P4_U1_CFG28, 0x400108dc +.set CYREG_B0_P4_U1_CFG29, 0x400108dd +.set CYREG_B0_P4_U1_CFG30, 0x400108de +.set CYREG_B0_P4_U1_CFG31, 0x400108df +.set CYREG_B0_P4_U1_DCFG0, 0x400108e0 +.set CYREG_B0_P4_U1_DCFG1, 0x400108e2 +.set CYREG_B0_P4_U1_DCFG2, 0x400108e4 +.set CYREG_B0_P4_U1_DCFG3, 0x400108e6 +.set CYREG_B0_P4_U1_DCFG4, 0x400108e8 +.set CYREG_B0_P4_U1_DCFG5, 0x400108ea +.set CYREG_B0_P4_U1_DCFG6, 0x400108ec +.set CYREG_B0_P4_U1_DCFG7, 0x400108ee +.set CYDEV_UCFG_B0_P4_ROUTE_BASE, 0x40010900 +.set CYDEV_UCFG_B0_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P5_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P5_U0_BASE, 0x40010a00 +.set CYDEV_UCFG_B0_P5_U0_SIZE, 0x00000070 +.set CYREG_B0_P5_U0_PLD_IT0, 0x40010a00 +.set CYREG_B0_P5_U0_PLD_IT1, 0x40010a04 +.set CYREG_B0_P5_U0_PLD_IT2, 0x40010a08 +.set CYREG_B0_P5_U0_PLD_IT3, 0x40010a0c +.set CYREG_B0_P5_U0_PLD_IT4, 0x40010a10 +.set CYREG_B0_P5_U0_PLD_IT5, 0x40010a14 +.set CYREG_B0_P5_U0_PLD_IT6, 0x40010a18 +.set CYREG_B0_P5_U0_PLD_IT7, 0x40010a1c +.set CYREG_B0_P5_U0_PLD_IT8, 0x40010a20 +.set CYREG_B0_P5_U0_PLD_IT9, 0x40010a24 +.set CYREG_B0_P5_U0_PLD_IT10, 0x40010a28 +.set CYREG_B0_P5_U0_PLD_IT11, 0x40010a2c +.set CYREG_B0_P5_U0_PLD_ORT0, 0x40010a30 +.set CYREG_B0_P5_U0_PLD_ORT1, 0x40010a32 +.set CYREG_B0_P5_U0_PLD_ORT2, 0x40010a34 +.set CYREG_B0_P5_U0_PLD_ORT3, 0x40010a36 +.set CYREG_B0_P5_U0_MC_CFG_CEN_CONST, 0x40010a38 +.set CYREG_B0_P5_U0_MC_CFG_XORFB, 0x40010a3a +.set CYREG_B0_P5_U0_MC_CFG_SET_RESET, 0x40010a3c +.set CYREG_B0_P5_U0_MC_CFG_BYPASS, 0x40010a3e +.set CYREG_B0_P5_U0_CFG0, 0x40010a40 +.set CYREG_B0_P5_U0_CFG1, 0x40010a41 +.set CYREG_B0_P5_U0_CFG2, 0x40010a42 +.set CYREG_B0_P5_U0_CFG3, 0x40010a43 +.set CYREG_B0_P5_U0_CFG4, 0x40010a44 +.set CYREG_B0_P5_U0_CFG5, 0x40010a45 +.set CYREG_B0_P5_U0_CFG6, 0x40010a46 +.set CYREG_B0_P5_U0_CFG7, 0x40010a47 +.set CYREG_B0_P5_U0_CFG8, 0x40010a48 +.set CYREG_B0_P5_U0_CFG9, 0x40010a49 +.set CYREG_B0_P5_U0_CFG10, 0x40010a4a +.set CYREG_B0_P5_U0_CFG11, 0x40010a4b +.set CYREG_B0_P5_U0_CFG12, 0x40010a4c +.set CYREG_B0_P5_U0_CFG13, 0x40010a4d +.set CYREG_B0_P5_U0_CFG14, 0x40010a4e +.set CYREG_B0_P5_U0_CFG15, 0x40010a4f +.set CYREG_B0_P5_U0_CFG16, 0x40010a50 +.set CYREG_B0_P5_U0_CFG17, 0x40010a51 +.set CYREG_B0_P5_U0_CFG18, 0x40010a52 +.set CYREG_B0_P5_U0_CFG19, 0x40010a53 +.set CYREG_B0_P5_U0_CFG20, 0x40010a54 +.set CYREG_B0_P5_U0_CFG21, 0x40010a55 +.set CYREG_B0_P5_U0_CFG22, 0x40010a56 +.set CYREG_B0_P5_U0_CFG23, 0x40010a57 +.set CYREG_B0_P5_U0_CFG24, 0x40010a58 +.set CYREG_B0_P5_U0_CFG25, 0x40010a59 +.set CYREG_B0_P5_U0_CFG26, 0x40010a5a +.set CYREG_B0_P5_U0_CFG27, 0x40010a5b +.set CYREG_B0_P5_U0_CFG28, 0x40010a5c +.set CYREG_B0_P5_U0_CFG29, 0x40010a5d +.set CYREG_B0_P5_U0_CFG30, 0x40010a5e +.set CYREG_B0_P5_U0_CFG31, 0x40010a5f +.set CYREG_B0_P5_U0_DCFG0, 0x40010a60 +.set CYREG_B0_P5_U0_DCFG1, 0x40010a62 +.set CYREG_B0_P5_U0_DCFG2, 0x40010a64 +.set CYREG_B0_P5_U0_DCFG3, 0x40010a66 +.set CYREG_B0_P5_U0_DCFG4, 0x40010a68 +.set CYREG_B0_P5_U0_DCFG5, 0x40010a6a +.set CYREG_B0_P5_U0_DCFG6, 0x40010a6c +.set CYREG_B0_P5_U0_DCFG7, 0x40010a6e +.set CYDEV_UCFG_B0_P5_U1_BASE, 0x40010a80 +.set CYDEV_UCFG_B0_P5_U1_SIZE, 0x00000070 +.set CYREG_B0_P5_U1_PLD_IT0, 0x40010a80 +.set CYREG_B0_P5_U1_PLD_IT1, 0x40010a84 +.set CYREG_B0_P5_U1_PLD_IT2, 0x40010a88 +.set CYREG_B0_P5_U1_PLD_IT3, 0x40010a8c +.set CYREG_B0_P5_U1_PLD_IT4, 0x40010a90 +.set CYREG_B0_P5_U1_PLD_IT5, 0x40010a94 +.set CYREG_B0_P5_U1_PLD_IT6, 0x40010a98 +.set CYREG_B0_P5_U1_PLD_IT7, 0x40010a9c +.set CYREG_B0_P5_U1_PLD_IT8, 0x40010aa0 +.set CYREG_B0_P5_U1_PLD_IT9, 0x40010aa4 +.set CYREG_B0_P5_U1_PLD_IT10, 0x40010aa8 +.set CYREG_B0_P5_U1_PLD_IT11, 0x40010aac +.set CYREG_B0_P5_U1_PLD_ORT0, 0x40010ab0 +.set CYREG_B0_P5_U1_PLD_ORT1, 0x40010ab2 +.set CYREG_B0_P5_U1_PLD_ORT2, 0x40010ab4 +.set CYREG_B0_P5_U1_PLD_ORT3, 0x40010ab6 +.set CYREG_B0_P5_U1_MC_CFG_CEN_CONST, 0x40010ab8 +.set CYREG_B0_P5_U1_MC_CFG_XORFB, 0x40010aba +.set CYREG_B0_P5_U1_MC_CFG_SET_RESET, 0x40010abc +.set CYREG_B0_P5_U1_MC_CFG_BYPASS, 0x40010abe +.set CYREG_B0_P5_U1_CFG0, 0x40010ac0 +.set CYREG_B0_P5_U1_CFG1, 0x40010ac1 +.set CYREG_B0_P5_U1_CFG2, 0x40010ac2 +.set CYREG_B0_P5_U1_CFG3, 0x40010ac3 +.set CYREG_B0_P5_U1_CFG4, 0x40010ac4 +.set CYREG_B0_P5_U1_CFG5, 0x40010ac5 +.set CYREG_B0_P5_U1_CFG6, 0x40010ac6 +.set CYREG_B0_P5_U1_CFG7, 0x40010ac7 +.set CYREG_B0_P5_U1_CFG8, 0x40010ac8 +.set CYREG_B0_P5_U1_CFG9, 0x40010ac9 +.set CYREG_B0_P5_U1_CFG10, 0x40010aca +.set CYREG_B0_P5_U1_CFG11, 0x40010acb +.set CYREG_B0_P5_U1_CFG12, 0x40010acc +.set CYREG_B0_P5_U1_CFG13, 0x40010acd +.set CYREG_B0_P5_U1_CFG14, 0x40010ace +.set CYREG_B0_P5_U1_CFG15, 0x40010acf +.set CYREG_B0_P5_U1_CFG16, 0x40010ad0 +.set CYREG_B0_P5_U1_CFG17, 0x40010ad1 +.set CYREG_B0_P5_U1_CFG18, 0x40010ad2 +.set CYREG_B0_P5_U1_CFG19, 0x40010ad3 +.set CYREG_B0_P5_U1_CFG20, 0x40010ad4 +.set CYREG_B0_P5_U1_CFG21, 0x40010ad5 +.set CYREG_B0_P5_U1_CFG22, 0x40010ad6 +.set CYREG_B0_P5_U1_CFG23, 0x40010ad7 +.set CYREG_B0_P5_U1_CFG24, 0x40010ad8 +.set CYREG_B0_P5_U1_CFG25, 0x40010ad9 +.set CYREG_B0_P5_U1_CFG26, 0x40010ada +.set CYREG_B0_P5_U1_CFG27, 0x40010adb +.set CYREG_B0_P5_U1_CFG28, 0x40010adc +.set CYREG_B0_P5_U1_CFG29, 0x40010add +.set CYREG_B0_P5_U1_CFG30, 0x40010ade +.set CYREG_B0_P5_U1_CFG31, 0x40010adf +.set CYREG_B0_P5_U1_DCFG0, 0x40010ae0 +.set CYREG_B0_P5_U1_DCFG1, 0x40010ae2 +.set CYREG_B0_P5_U1_DCFG2, 0x40010ae4 +.set CYREG_B0_P5_U1_DCFG3, 0x40010ae6 +.set CYREG_B0_P5_U1_DCFG4, 0x40010ae8 +.set CYREG_B0_P5_U1_DCFG5, 0x40010aea +.set CYREG_B0_P5_U1_DCFG6, 0x40010aec +.set CYREG_B0_P5_U1_DCFG7, 0x40010aee +.set CYDEV_UCFG_B0_P5_ROUTE_BASE, 0x40010b00 +.set CYDEV_UCFG_B0_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P6_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P6_U0_BASE, 0x40010c00 +.set CYDEV_UCFG_B0_P6_U0_SIZE, 0x00000070 +.set CYREG_B0_P6_U0_PLD_IT0, 0x40010c00 +.set CYREG_B0_P6_U0_PLD_IT1, 0x40010c04 +.set CYREG_B0_P6_U0_PLD_IT2, 0x40010c08 +.set CYREG_B0_P6_U0_PLD_IT3, 0x40010c0c +.set CYREG_B0_P6_U0_PLD_IT4, 0x40010c10 +.set CYREG_B0_P6_U0_PLD_IT5, 0x40010c14 +.set CYREG_B0_P6_U0_PLD_IT6, 0x40010c18 +.set CYREG_B0_P6_U0_PLD_IT7, 0x40010c1c +.set CYREG_B0_P6_U0_PLD_IT8, 0x40010c20 +.set CYREG_B0_P6_U0_PLD_IT9, 0x40010c24 +.set CYREG_B0_P6_U0_PLD_IT10, 0x40010c28 +.set CYREG_B0_P6_U0_PLD_IT11, 0x40010c2c +.set CYREG_B0_P6_U0_PLD_ORT0, 0x40010c30 +.set CYREG_B0_P6_U0_PLD_ORT1, 0x40010c32 +.set CYREG_B0_P6_U0_PLD_ORT2, 0x40010c34 +.set CYREG_B0_P6_U0_PLD_ORT3, 0x40010c36 +.set CYREG_B0_P6_U0_MC_CFG_CEN_CONST, 0x40010c38 +.set CYREG_B0_P6_U0_MC_CFG_XORFB, 0x40010c3a +.set CYREG_B0_P6_U0_MC_CFG_SET_RESET, 0x40010c3c +.set CYREG_B0_P6_U0_MC_CFG_BYPASS, 0x40010c3e +.set CYREG_B0_P6_U0_CFG0, 0x40010c40 +.set CYREG_B0_P6_U0_CFG1, 0x40010c41 +.set CYREG_B0_P6_U0_CFG2, 0x40010c42 +.set CYREG_B0_P6_U0_CFG3, 0x40010c43 +.set CYREG_B0_P6_U0_CFG4, 0x40010c44 +.set CYREG_B0_P6_U0_CFG5, 0x40010c45 +.set CYREG_B0_P6_U0_CFG6, 0x40010c46 +.set CYREG_B0_P6_U0_CFG7, 0x40010c47 +.set CYREG_B0_P6_U0_CFG8, 0x40010c48 +.set CYREG_B0_P6_U0_CFG9, 0x40010c49 +.set CYREG_B0_P6_U0_CFG10, 0x40010c4a +.set CYREG_B0_P6_U0_CFG11, 0x40010c4b +.set CYREG_B0_P6_U0_CFG12, 0x40010c4c +.set CYREG_B0_P6_U0_CFG13, 0x40010c4d +.set CYREG_B0_P6_U0_CFG14, 0x40010c4e +.set CYREG_B0_P6_U0_CFG15, 0x40010c4f +.set CYREG_B0_P6_U0_CFG16, 0x40010c50 +.set CYREG_B0_P6_U0_CFG17, 0x40010c51 +.set CYREG_B0_P6_U0_CFG18, 0x40010c52 +.set CYREG_B0_P6_U0_CFG19, 0x40010c53 +.set CYREG_B0_P6_U0_CFG20, 0x40010c54 +.set CYREG_B0_P6_U0_CFG21, 0x40010c55 +.set CYREG_B0_P6_U0_CFG22, 0x40010c56 +.set CYREG_B0_P6_U0_CFG23, 0x40010c57 +.set CYREG_B0_P6_U0_CFG24, 0x40010c58 +.set CYREG_B0_P6_U0_CFG25, 0x40010c59 +.set CYREG_B0_P6_U0_CFG26, 0x40010c5a +.set CYREG_B0_P6_U0_CFG27, 0x40010c5b +.set CYREG_B0_P6_U0_CFG28, 0x40010c5c +.set CYREG_B0_P6_U0_CFG29, 0x40010c5d +.set CYREG_B0_P6_U0_CFG30, 0x40010c5e +.set CYREG_B0_P6_U0_CFG31, 0x40010c5f +.set CYREG_B0_P6_U0_DCFG0, 0x40010c60 +.set CYREG_B0_P6_U0_DCFG1, 0x40010c62 +.set CYREG_B0_P6_U0_DCFG2, 0x40010c64 +.set CYREG_B0_P6_U0_DCFG3, 0x40010c66 +.set CYREG_B0_P6_U0_DCFG4, 0x40010c68 +.set CYREG_B0_P6_U0_DCFG5, 0x40010c6a +.set CYREG_B0_P6_U0_DCFG6, 0x40010c6c +.set CYREG_B0_P6_U0_DCFG7, 0x40010c6e +.set CYDEV_UCFG_B0_P6_U1_BASE, 0x40010c80 +.set CYDEV_UCFG_B0_P6_U1_SIZE, 0x00000070 +.set CYREG_B0_P6_U1_PLD_IT0, 0x40010c80 +.set CYREG_B0_P6_U1_PLD_IT1, 0x40010c84 +.set CYREG_B0_P6_U1_PLD_IT2, 0x40010c88 +.set CYREG_B0_P6_U1_PLD_IT3, 0x40010c8c +.set CYREG_B0_P6_U1_PLD_IT4, 0x40010c90 +.set CYREG_B0_P6_U1_PLD_IT5, 0x40010c94 +.set CYREG_B0_P6_U1_PLD_IT6, 0x40010c98 +.set CYREG_B0_P6_U1_PLD_IT7, 0x40010c9c +.set CYREG_B0_P6_U1_PLD_IT8, 0x40010ca0 +.set CYREG_B0_P6_U1_PLD_IT9, 0x40010ca4 +.set CYREG_B0_P6_U1_PLD_IT10, 0x40010ca8 +.set CYREG_B0_P6_U1_PLD_IT11, 0x40010cac +.set CYREG_B0_P6_U1_PLD_ORT0, 0x40010cb0 +.set CYREG_B0_P6_U1_PLD_ORT1, 0x40010cb2 +.set CYREG_B0_P6_U1_PLD_ORT2, 0x40010cb4 +.set CYREG_B0_P6_U1_PLD_ORT3, 0x40010cb6 +.set CYREG_B0_P6_U1_MC_CFG_CEN_CONST, 0x40010cb8 +.set CYREG_B0_P6_U1_MC_CFG_XORFB, 0x40010cba +.set CYREG_B0_P6_U1_MC_CFG_SET_RESET, 0x40010cbc +.set CYREG_B0_P6_U1_MC_CFG_BYPASS, 0x40010cbe +.set CYREG_B0_P6_U1_CFG0, 0x40010cc0 +.set CYREG_B0_P6_U1_CFG1, 0x40010cc1 +.set CYREG_B0_P6_U1_CFG2, 0x40010cc2 +.set CYREG_B0_P6_U1_CFG3, 0x40010cc3 +.set CYREG_B0_P6_U1_CFG4, 0x40010cc4 +.set CYREG_B0_P6_U1_CFG5, 0x40010cc5 +.set CYREG_B0_P6_U1_CFG6, 0x40010cc6 +.set CYREG_B0_P6_U1_CFG7, 0x40010cc7 +.set CYREG_B0_P6_U1_CFG8, 0x40010cc8 +.set CYREG_B0_P6_U1_CFG9, 0x40010cc9 +.set CYREG_B0_P6_U1_CFG10, 0x40010cca +.set CYREG_B0_P6_U1_CFG11, 0x40010ccb +.set CYREG_B0_P6_U1_CFG12, 0x40010ccc +.set CYREG_B0_P6_U1_CFG13, 0x40010ccd +.set CYREG_B0_P6_U1_CFG14, 0x40010cce +.set CYREG_B0_P6_U1_CFG15, 0x40010ccf +.set CYREG_B0_P6_U1_CFG16, 0x40010cd0 +.set CYREG_B0_P6_U1_CFG17, 0x40010cd1 +.set CYREG_B0_P6_U1_CFG18, 0x40010cd2 +.set CYREG_B0_P6_U1_CFG19, 0x40010cd3 +.set CYREG_B0_P6_U1_CFG20, 0x40010cd4 +.set CYREG_B0_P6_U1_CFG21, 0x40010cd5 +.set CYREG_B0_P6_U1_CFG22, 0x40010cd6 +.set CYREG_B0_P6_U1_CFG23, 0x40010cd7 +.set CYREG_B0_P6_U1_CFG24, 0x40010cd8 +.set CYREG_B0_P6_U1_CFG25, 0x40010cd9 +.set CYREG_B0_P6_U1_CFG26, 0x40010cda +.set CYREG_B0_P6_U1_CFG27, 0x40010cdb +.set CYREG_B0_P6_U1_CFG28, 0x40010cdc +.set CYREG_B0_P6_U1_CFG29, 0x40010cdd +.set CYREG_B0_P6_U1_CFG30, 0x40010cde +.set CYREG_B0_P6_U1_CFG31, 0x40010cdf +.set CYREG_B0_P6_U1_DCFG0, 0x40010ce0 +.set CYREG_B0_P6_U1_DCFG1, 0x40010ce2 +.set CYREG_B0_P6_U1_DCFG2, 0x40010ce4 +.set CYREG_B0_P6_U1_DCFG3, 0x40010ce6 +.set CYREG_B0_P6_U1_DCFG4, 0x40010ce8 +.set CYREG_B0_P6_U1_DCFG5, 0x40010cea +.set CYREG_B0_P6_U1_DCFG6, 0x40010cec +.set CYREG_B0_P6_U1_DCFG7, 0x40010cee +.set CYDEV_UCFG_B0_P6_ROUTE_BASE, 0x40010d00 +.set CYDEV_UCFG_B0_P6_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B0_P7_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_SIZE, 0x000001ef +.set CYDEV_UCFG_B0_P7_U0_BASE, 0x40010e00 +.set CYDEV_UCFG_B0_P7_U0_SIZE, 0x00000070 +.set CYREG_B0_P7_U0_PLD_IT0, 0x40010e00 +.set CYREG_B0_P7_U0_PLD_IT1, 0x40010e04 +.set CYREG_B0_P7_U0_PLD_IT2, 0x40010e08 +.set CYREG_B0_P7_U0_PLD_IT3, 0x40010e0c +.set CYREG_B0_P7_U0_PLD_IT4, 0x40010e10 +.set CYREG_B0_P7_U0_PLD_IT5, 0x40010e14 +.set CYREG_B0_P7_U0_PLD_IT6, 0x40010e18 +.set CYREG_B0_P7_U0_PLD_IT7, 0x40010e1c +.set CYREG_B0_P7_U0_PLD_IT8, 0x40010e20 +.set CYREG_B0_P7_U0_PLD_IT9, 0x40010e24 +.set CYREG_B0_P7_U0_PLD_IT10, 0x40010e28 +.set CYREG_B0_P7_U0_PLD_IT11, 0x40010e2c +.set CYREG_B0_P7_U0_PLD_ORT0, 0x40010e30 +.set CYREG_B0_P7_U0_PLD_ORT1, 0x40010e32 +.set CYREG_B0_P7_U0_PLD_ORT2, 0x40010e34 +.set CYREG_B0_P7_U0_PLD_ORT3, 0x40010e36 +.set CYREG_B0_P7_U0_MC_CFG_CEN_CONST, 0x40010e38 +.set CYREG_B0_P7_U0_MC_CFG_XORFB, 0x40010e3a +.set CYREG_B0_P7_U0_MC_CFG_SET_RESET, 0x40010e3c +.set CYREG_B0_P7_U0_MC_CFG_BYPASS, 0x40010e3e +.set CYREG_B0_P7_U0_CFG0, 0x40010e40 +.set CYREG_B0_P7_U0_CFG1, 0x40010e41 +.set CYREG_B0_P7_U0_CFG2, 0x40010e42 +.set CYREG_B0_P7_U0_CFG3, 0x40010e43 +.set CYREG_B0_P7_U0_CFG4, 0x40010e44 +.set CYREG_B0_P7_U0_CFG5, 0x40010e45 +.set CYREG_B0_P7_U0_CFG6, 0x40010e46 +.set CYREG_B0_P7_U0_CFG7, 0x40010e47 +.set CYREG_B0_P7_U0_CFG8, 0x40010e48 +.set CYREG_B0_P7_U0_CFG9, 0x40010e49 +.set CYREG_B0_P7_U0_CFG10, 0x40010e4a +.set CYREG_B0_P7_U0_CFG11, 0x40010e4b +.set CYREG_B0_P7_U0_CFG12, 0x40010e4c +.set CYREG_B0_P7_U0_CFG13, 0x40010e4d +.set CYREG_B0_P7_U0_CFG14, 0x40010e4e +.set CYREG_B0_P7_U0_CFG15, 0x40010e4f +.set CYREG_B0_P7_U0_CFG16, 0x40010e50 +.set CYREG_B0_P7_U0_CFG17, 0x40010e51 +.set CYREG_B0_P7_U0_CFG18, 0x40010e52 +.set CYREG_B0_P7_U0_CFG19, 0x40010e53 +.set CYREG_B0_P7_U0_CFG20, 0x40010e54 +.set CYREG_B0_P7_U0_CFG21, 0x40010e55 +.set CYREG_B0_P7_U0_CFG22, 0x40010e56 +.set CYREG_B0_P7_U0_CFG23, 0x40010e57 +.set CYREG_B0_P7_U0_CFG24, 0x40010e58 +.set CYREG_B0_P7_U0_CFG25, 0x40010e59 +.set CYREG_B0_P7_U0_CFG26, 0x40010e5a +.set CYREG_B0_P7_U0_CFG27, 0x40010e5b +.set CYREG_B0_P7_U0_CFG28, 0x40010e5c +.set CYREG_B0_P7_U0_CFG29, 0x40010e5d +.set CYREG_B0_P7_U0_CFG30, 0x40010e5e +.set CYREG_B0_P7_U0_CFG31, 0x40010e5f +.set CYREG_B0_P7_U0_DCFG0, 0x40010e60 +.set CYREG_B0_P7_U0_DCFG1, 0x40010e62 +.set CYREG_B0_P7_U0_DCFG2, 0x40010e64 +.set CYREG_B0_P7_U0_DCFG3, 0x40010e66 +.set CYREG_B0_P7_U0_DCFG4, 0x40010e68 +.set CYREG_B0_P7_U0_DCFG5, 0x40010e6a +.set CYREG_B0_P7_U0_DCFG6, 0x40010e6c +.set CYREG_B0_P7_U0_DCFG7, 0x40010e6e +.set CYDEV_UCFG_B0_P7_U1_BASE, 0x40010e80 +.set CYDEV_UCFG_B0_P7_U1_SIZE, 0x00000070 +.set CYREG_B0_P7_U1_PLD_IT0, 0x40010e80 +.set CYREG_B0_P7_U1_PLD_IT1, 0x40010e84 +.set CYREG_B0_P7_U1_PLD_IT2, 0x40010e88 +.set CYREG_B0_P7_U1_PLD_IT3, 0x40010e8c +.set CYREG_B0_P7_U1_PLD_IT4, 0x40010e90 +.set CYREG_B0_P7_U1_PLD_IT5, 0x40010e94 +.set CYREG_B0_P7_U1_PLD_IT6, 0x40010e98 +.set CYREG_B0_P7_U1_PLD_IT7, 0x40010e9c +.set CYREG_B0_P7_U1_PLD_IT8, 0x40010ea0 +.set CYREG_B0_P7_U1_PLD_IT9, 0x40010ea4 +.set CYREG_B0_P7_U1_PLD_IT10, 0x40010ea8 +.set CYREG_B0_P7_U1_PLD_IT11, 0x40010eac +.set CYREG_B0_P7_U1_PLD_ORT0, 0x40010eb0 +.set CYREG_B0_P7_U1_PLD_ORT1, 0x40010eb2 +.set CYREG_B0_P7_U1_PLD_ORT2, 0x40010eb4 +.set CYREG_B0_P7_U1_PLD_ORT3, 0x40010eb6 +.set CYREG_B0_P7_U1_MC_CFG_CEN_CONST, 0x40010eb8 +.set CYREG_B0_P7_U1_MC_CFG_XORFB, 0x40010eba +.set CYREG_B0_P7_U1_MC_CFG_SET_RESET, 0x40010ebc +.set CYREG_B0_P7_U1_MC_CFG_BYPASS, 0x40010ebe +.set CYREG_B0_P7_U1_CFG0, 0x40010ec0 +.set CYREG_B0_P7_U1_CFG1, 0x40010ec1 +.set CYREG_B0_P7_U1_CFG2, 0x40010ec2 +.set CYREG_B0_P7_U1_CFG3, 0x40010ec3 +.set CYREG_B0_P7_U1_CFG4, 0x40010ec4 +.set CYREG_B0_P7_U1_CFG5, 0x40010ec5 +.set CYREG_B0_P7_U1_CFG6, 0x40010ec6 +.set CYREG_B0_P7_U1_CFG7, 0x40010ec7 +.set CYREG_B0_P7_U1_CFG8, 0x40010ec8 +.set CYREG_B0_P7_U1_CFG9, 0x40010ec9 +.set CYREG_B0_P7_U1_CFG10, 0x40010eca +.set CYREG_B0_P7_U1_CFG11, 0x40010ecb +.set CYREG_B0_P7_U1_CFG12, 0x40010ecc +.set CYREG_B0_P7_U1_CFG13, 0x40010ecd +.set CYREG_B0_P7_U1_CFG14, 0x40010ece +.set CYREG_B0_P7_U1_CFG15, 0x40010ecf +.set CYREG_B0_P7_U1_CFG16, 0x40010ed0 +.set CYREG_B0_P7_U1_CFG17, 0x40010ed1 +.set CYREG_B0_P7_U1_CFG18, 0x40010ed2 +.set CYREG_B0_P7_U1_CFG19, 0x40010ed3 +.set CYREG_B0_P7_U1_CFG20, 0x40010ed4 +.set CYREG_B0_P7_U1_CFG21, 0x40010ed5 +.set CYREG_B0_P7_U1_CFG22, 0x40010ed6 +.set CYREG_B0_P7_U1_CFG23, 0x40010ed7 +.set CYREG_B0_P7_U1_CFG24, 0x40010ed8 +.set CYREG_B0_P7_U1_CFG25, 0x40010ed9 +.set CYREG_B0_P7_U1_CFG26, 0x40010eda +.set CYREG_B0_P7_U1_CFG27, 0x40010edb +.set CYREG_B0_P7_U1_CFG28, 0x40010edc +.set CYREG_B0_P7_U1_CFG29, 0x40010edd +.set CYREG_B0_P7_U1_CFG30, 0x40010ede +.set CYREG_B0_P7_U1_CFG31, 0x40010edf +.set CYREG_B0_P7_U1_DCFG0, 0x40010ee0 +.set CYREG_B0_P7_U1_DCFG1, 0x40010ee2 +.set CYREG_B0_P7_U1_DCFG2, 0x40010ee4 +.set CYREG_B0_P7_U1_DCFG3, 0x40010ee6 +.set CYREG_B0_P7_U1_DCFG4, 0x40010ee8 +.set CYREG_B0_P7_U1_DCFG5, 0x40010eea +.set CYREG_B0_P7_U1_DCFG6, 0x40010eec +.set CYREG_B0_P7_U1_DCFG7, 0x40010eee +.set CYDEV_UCFG_B0_P7_ROUTE_BASE, 0x40010f00 +.set CYDEV_UCFG_B0_P7_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_BASE, 0x40011000 +.set CYDEV_UCFG_B1_SIZE, 0x00000fef +.set CYDEV_UCFG_B1_P2_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P2_U0_BASE, 0x40011400 +.set CYDEV_UCFG_B1_P2_U0_SIZE, 0x00000070 +.set CYREG_B1_P2_U0_PLD_IT0, 0x40011400 +.set CYREG_B1_P2_U0_PLD_IT1, 0x40011404 +.set CYREG_B1_P2_U0_PLD_IT2, 0x40011408 +.set CYREG_B1_P2_U0_PLD_IT3, 0x4001140c +.set CYREG_B1_P2_U0_PLD_IT4, 0x40011410 +.set CYREG_B1_P2_U0_PLD_IT5, 0x40011414 +.set CYREG_B1_P2_U0_PLD_IT6, 0x40011418 +.set CYREG_B1_P2_U0_PLD_IT7, 0x4001141c +.set CYREG_B1_P2_U0_PLD_IT8, 0x40011420 +.set CYREG_B1_P2_U0_PLD_IT9, 0x40011424 +.set CYREG_B1_P2_U0_PLD_IT10, 0x40011428 +.set CYREG_B1_P2_U0_PLD_IT11, 0x4001142c +.set CYREG_B1_P2_U0_PLD_ORT0, 0x40011430 +.set CYREG_B1_P2_U0_PLD_ORT1, 0x40011432 +.set CYREG_B1_P2_U0_PLD_ORT2, 0x40011434 +.set CYREG_B1_P2_U0_PLD_ORT3, 0x40011436 +.set CYREG_B1_P2_U0_MC_CFG_CEN_CONST, 0x40011438 +.set CYREG_B1_P2_U0_MC_CFG_XORFB, 0x4001143a +.set CYREG_B1_P2_U0_MC_CFG_SET_RESET, 0x4001143c +.set CYREG_B1_P2_U0_MC_CFG_BYPASS, 0x4001143e +.set CYREG_B1_P2_U0_CFG0, 0x40011440 +.set CYREG_B1_P2_U0_CFG1, 0x40011441 +.set CYREG_B1_P2_U0_CFG2, 0x40011442 +.set CYREG_B1_P2_U0_CFG3, 0x40011443 +.set CYREG_B1_P2_U0_CFG4, 0x40011444 +.set CYREG_B1_P2_U0_CFG5, 0x40011445 +.set CYREG_B1_P2_U0_CFG6, 0x40011446 +.set CYREG_B1_P2_U0_CFG7, 0x40011447 +.set CYREG_B1_P2_U0_CFG8, 0x40011448 +.set CYREG_B1_P2_U0_CFG9, 0x40011449 +.set CYREG_B1_P2_U0_CFG10, 0x4001144a +.set CYREG_B1_P2_U0_CFG11, 0x4001144b +.set CYREG_B1_P2_U0_CFG12, 0x4001144c +.set CYREG_B1_P2_U0_CFG13, 0x4001144d +.set CYREG_B1_P2_U0_CFG14, 0x4001144e +.set CYREG_B1_P2_U0_CFG15, 0x4001144f +.set CYREG_B1_P2_U0_CFG16, 0x40011450 +.set CYREG_B1_P2_U0_CFG17, 0x40011451 +.set CYREG_B1_P2_U0_CFG18, 0x40011452 +.set CYREG_B1_P2_U0_CFG19, 0x40011453 +.set CYREG_B1_P2_U0_CFG20, 0x40011454 +.set CYREG_B1_P2_U0_CFG21, 0x40011455 +.set CYREG_B1_P2_U0_CFG22, 0x40011456 +.set CYREG_B1_P2_U0_CFG23, 0x40011457 +.set CYREG_B1_P2_U0_CFG24, 0x40011458 +.set CYREG_B1_P2_U0_CFG25, 0x40011459 +.set CYREG_B1_P2_U0_CFG26, 0x4001145a +.set CYREG_B1_P2_U0_CFG27, 0x4001145b +.set CYREG_B1_P2_U0_CFG28, 0x4001145c +.set CYREG_B1_P2_U0_CFG29, 0x4001145d +.set CYREG_B1_P2_U0_CFG30, 0x4001145e +.set CYREG_B1_P2_U0_CFG31, 0x4001145f +.set CYREG_B1_P2_U0_DCFG0, 0x40011460 +.set CYREG_B1_P2_U0_DCFG1, 0x40011462 +.set CYREG_B1_P2_U0_DCFG2, 0x40011464 +.set CYREG_B1_P2_U0_DCFG3, 0x40011466 +.set CYREG_B1_P2_U0_DCFG4, 0x40011468 +.set CYREG_B1_P2_U0_DCFG5, 0x4001146a +.set CYREG_B1_P2_U0_DCFG6, 0x4001146c +.set CYREG_B1_P2_U0_DCFG7, 0x4001146e +.set CYDEV_UCFG_B1_P2_U1_BASE, 0x40011480 +.set CYDEV_UCFG_B1_P2_U1_SIZE, 0x00000070 +.set CYREG_B1_P2_U1_PLD_IT0, 0x40011480 +.set CYREG_B1_P2_U1_PLD_IT1, 0x40011484 +.set CYREG_B1_P2_U1_PLD_IT2, 0x40011488 +.set CYREG_B1_P2_U1_PLD_IT3, 0x4001148c +.set CYREG_B1_P2_U1_PLD_IT4, 0x40011490 +.set CYREG_B1_P2_U1_PLD_IT5, 0x40011494 +.set CYREG_B1_P2_U1_PLD_IT6, 0x40011498 +.set CYREG_B1_P2_U1_PLD_IT7, 0x4001149c +.set CYREG_B1_P2_U1_PLD_IT8, 0x400114a0 +.set CYREG_B1_P2_U1_PLD_IT9, 0x400114a4 +.set CYREG_B1_P2_U1_PLD_IT10, 0x400114a8 +.set CYREG_B1_P2_U1_PLD_IT11, 0x400114ac +.set CYREG_B1_P2_U1_PLD_ORT0, 0x400114b0 +.set CYREG_B1_P2_U1_PLD_ORT1, 0x400114b2 +.set CYREG_B1_P2_U1_PLD_ORT2, 0x400114b4 +.set CYREG_B1_P2_U1_PLD_ORT3, 0x400114b6 +.set CYREG_B1_P2_U1_MC_CFG_CEN_CONST, 0x400114b8 +.set CYREG_B1_P2_U1_MC_CFG_XORFB, 0x400114ba +.set CYREG_B1_P2_U1_MC_CFG_SET_RESET, 0x400114bc +.set CYREG_B1_P2_U1_MC_CFG_BYPASS, 0x400114be +.set CYREG_B1_P2_U1_CFG0, 0x400114c0 +.set CYREG_B1_P2_U1_CFG1, 0x400114c1 +.set CYREG_B1_P2_U1_CFG2, 0x400114c2 +.set CYREG_B1_P2_U1_CFG3, 0x400114c3 +.set CYREG_B1_P2_U1_CFG4, 0x400114c4 +.set CYREG_B1_P2_U1_CFG5, 0x400114c5 +.set CYREG_B1_P2_U1_CFG6, 0x400114c6 +.set CYREG_B1_P2_U1_CFG7, 0x400114c7 +.set CYREG_B1_P2_U1_CFG8, 0x400114c8 +.set CYREG_B1_P2_U1_CFG9, 0x400114c9 +.set CYREG_B1_P2_U1_CFG10, 0x400114ca +.set CYREG_B1_P2_U1_CFG11, 0x400114cb +.set CYREG_B1_P2_U1_CFG12, 0x400114cc +.set CYREG_B1_P2_U1_CFG13, 0x400114cd +.set CYREG_B1_P2_U1_CFG14, 0x400114ce +.set CYREG_B1_P2_U1_CFG15, 0x400114cf +.set CYREG_B1_P2_U1_CFG16, 0x400114d0 +.set CYREG_B1_P2_U1_CFG17, 0x400114d1 +.set CYREG_B1_P2_U1_CFG18, 0x400114d2 +.set CYREG_B1_P2_U1_CFG19, 0x400114d3 +.set CYREG_B1_P2_U1_CFG20, 0x400114d4 +.set CYREG_B1_P2_U1_CFG21, 0x400114d5 +.set CYREG_B1_P2_U1_CFG22, 0x400114d6 +.set CYREG_B1_P2_U1_CFG23, 0x400114d7 +.set CYREG_B1_P2_U1_CFG24, 0x400114d8 +.set CYREG_B1_P2_U1_CFG25, 0x400114d9 +.set CYREG_B1_P2_U1_CFG26, 0x400114da +.set CYREG_B1_P2_U1_CFG27, 0x400114db +.set CYREG_B1_P2_U1_CFG28, 0x400114dc +.set CYREG_B1_P2_U1_CFG29, 0x400114dd +.set CYREG_B1_P2_U1_CFG30, 0x400114de +.set CYREG_B1_P2_U1_CFG31, 0x400114df +.set CYREG_B1_P2_U1_DCFG0, 0x400114e0 +.set CYREG_B1_P2_U1_DCFG1, 0x400114e2 +.set CYREG_B1_P2_U1_DCFG2, 0x400114e4 +.set CYREG_B1_P2_U1_DCFG3, 0x400114e6 +.set CYREG_B1_P2_U1_DCFG4, 0x400114e8 +.set CYREG_B1_P2_U1_DCFG5, 0x400114ea +.set CYREG_B1_P2_U1_DCFG6, 0x400114ec +.set CYREG_B1_P2_U1_DCFG7, 0x400114ee +.set CYDEV_UCFG_B1_P2_ROUTE_BASE, 0x40011500 +.set CYDEV_UCFG_B1_P2_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P3_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P3_U0_BASE, 0x40011600 +.set CYDEV_UCFG_B1_P3_U0_SIZE, 0x00000070 +.set CYREG_B1_P3_U0_PLD_IT0, 0x40011600 +.set CYREG_B1_P3_U0_PLD_IT1, 0x40011604 +.set CYREG_B1_P3_U0_PLD_IT2, 0x40011608 +.set CYREG_B1_P3_U0_PLD_IT3, 0x4001160c +.set CYREG_B1_P3_U0_PLD_IT4, 0x40011610 +.set CYREG_B1_P3_U0_PLD_IT5, 0x40011614 +.set CYREG_B1_P3_U0_PLD_IT6, 0x40011618 +.set CYREG_B1_P3_U0_PLD_IT7, 0x4001161c +.set CYREG_B1_P3_U0_PLD_IT8, 0x40011620 +.set CYREG_B1_P3_U0_PLD_IT9, 0x40011624 +.set CYREG_B1_P3_U0_PLD_IT10, 0x40011628 +.set CYREG_B1_P3_U0_PLD_IT11, 0x4001162c +.set CYREG_B1_P3_U0_PLD_ORT0, 0x40011630 +.set CYREG_B1_P3_U0_PLD_ORT1, 0x40011632 +.set CYREG_B1_P3_U0_PLD_ORT2, 0x40011634 +.set CYREG_B1_P3_U0_PLD_ORT3, 0x40011636 +.set CYREG_B1_P3_U0_MC_CFG_CEN_CONST, 0x40011638 +.set CYREG_B1_P3_U0_MC_CFG_XORFB, 0x4001163a +.set CYREG_B1_P3_U0_MC_CFG_SET_RESET, 0x4001163c +.set CYREG_B1_P3_U0_MC_CFG_BYPASS, 0x4001163e +.set CYREG_B1_P3_U0_CFG0, 0x40011640 +.set CYREG_B1_P3_U0_CFG1, 0x40011641 +.set CYREG_B1_P3_U0_CFG2, 0x40011642 +.set CYREG_B1_P3_U0_CFG3, 0x40011643 +.set CYREG_B1_P3_U0_CFG4, 0x40011644 +.set CYREG_B1_P3_U0_CFG5, 0x40011645 +.set CYREG_B1_P3_U0_CFG6, 0x40011646 +.set CYREG_B1_P3_U0_CFG7, 0x40011647 +.set CYREG_B1_P3_U0_CFG8, 0x40011648 +.set CYREG_B1_P3_U0_CFG9, 0x40011649 +.set CYREG_B1_P3_U0_CFG10, 0x4001164a +.set CYREG_B1_P3_U0_CFG11, 0x4001164b +.set CYREG_B1_P3_U0_CFG12, 0x4001164c +.set CYREG_B1_P3_U0_CFG13, 0x4001164d +.set CYREG_B1_P3_U0_CFG14, 0x4001164e +.set CYREG_B1_P3_U0_CFG15, 0x4001164f +.set CYREG_B1_P3_U0_CFG16, 0x40011650 +.set CYREG_B1_P3_U0_CFG17, 0x40011651 +.set CYREG_B1_P3_U0_CFG18, 0x40011652 +.set CYREG_B1_P3_U0_CFG19, 0x40011653 +.set CYREG_B1_P3_U0_CFG20, 0x40011654 +.set CYREG_B1_P3_U0_CFG21, 0x40011655 +.set CYREG_B1_P3_U0_CFG22, 0x40011656 +.set CYREG_B1_P3_U0_CFG23, 0x40011657 +.set CYREG_B1_P3_U0_CFG24, 0x40011658 +.set CYREG_B1_P3_U0_CFG25, 0x40011659 +.set CYREG_B1_P3_U0_CFG26, 0x4001165a +.set CYREG_B1_P3_U0_CFG27, 0x4001165b +.set CYREG_B1_P3_U0_CFG28, 0x4001165c +.set CYREG_B1_P3_U0_CFG29, 0x4001165d +.set CYREG_B1_P3_U0_CFG30, 0x4001165e +.set CYREG_B1_P3_U0_CFG31, 0x4001165f +.set CYREG_B1_P3_U0_DCFG0, 0x40011660 +.set CYREG_B1_P3_U0_DCFG1, 0x40011662 +.set CYREG_B1_P3_U0_DCFG2, 0x40011664 +.set CYREG_B1_P3_U0_DCFG3, 0x40011666 +.set CYREG_B1_P3_U0_DCFG4, 0x40011668 +.set CYREG_B1_P3_U0_DCFG5, 0x4001166a +.set CYREG_B1_P3_U0_DCFG6, 0x4001166c +.set CYREG_B1_P3_U0_DCFG7, 0x4001166e +.set CYDEV_UCFG_B1_P3_U1_BASE, 0x40011680 +.set CYDEV_UCFG_B1_P3_U1_SIZE, 0x00000070 +.set CYREG_B1_P3_U1_PLD_IT0, 0x40011680 +.set CYREG_B1_P3_U1_PLD_IT1, 0x40011684 +.set CYREG_B1_P3_U1_PLD_IT2, 0x40011688 +.set CYREG_B1_P3_U1_PLD_IT3, 0x4001168c +.set CYREG_B1_P3_U1_PLD_IT4, 0x40011690 +.set CYREG_B1_P3_U1_PLD_IT5, 0x40011694 +.set CYREG_B1_P3_U1_PLD_IT6, 0x40011698 +.set CYREG_B1_P3_U1_PLD_IT7, 0x4001169c +.set CYREG_B1_P3_U1_PLD_IT8, 0x400116a0 +.set CYREG_B1_P3_U1_PLD_IT9, 0x400116a4 +.set CYREG_B1_P3_U1_PLD_IT10, 0x400116a8 +.set CYREG_B1_P3_U1_PLD_IT11, 0x400116ac +.set CYREG_B1_P3_U1_PLD_ORT0, 0x400116b0 +.set CYREG_B1_P3_U1_PLD_ORT1, 0x400116b2 +.set CYREG_B1_P3_U1_PLD_ORT2, 0x400116b4 +.set CYREG_B1_P3_U1_PLD_ORT3, 0x400116b6 +.set CYREG_B1_P3_U1_MC_CFG_CEN_CONST, 0x400116b8 +.set CYREG_B1_P3_U1_MC_CFG_XORFB, 0x400116ba +.set CYREG_B1_P3_U1_MC_CFG_SET_RESET, 0x400116bc +.set CYREG_B1_P3_U1_MC_CFG_BYPASS, 0x400116be +.set CYREG_B1_P3_U1_CFG0, 0x400116c0 +.set CYREG_B1_P3_U1_CFG1, 0x400116c1 +.set CYREG_B1_P3_U1_CFG2, 0x400116c2 +.set CYREG_B1_P3_U1_CFG3, 0x400116c3 +.set CYREG_B1_P3_U1_CFG4, 0x400116c4 +.set CYREG_B1_P3_U1_CFG5, 0x400116c5 +.set CYREG_B1_P3_U1_CFG6, 0x400116c6 +.set CYREG_B1_P3_U1_CFG7, 0x400116c7 +.set CYREG_B1_P3_U1_CFG8, 0x400116c8 +.set CYREG_B1_P3_U1_CFG9, 0x400116c9 +.set CYREG_B1_P3_U1_CFG10, 0x400116ca +.set CYREG_B1_P3_U1_CFG11, 0x400116cb +.set CYREG_B1_P3_U1_CFG12, 0x400116cc +.set CYREG_B1_P3_U1_CFG13, 0x400116cd +.set CYREG_B1_P3_U1_CFG14, 0x400116ce +.set CYREG_B1_P3_U1_CFG15, 0x400116cf +.set CYREG_B1_P3_U1_CFG16, 0x400116d0 +.set CYREG_B1_P3_U1_CFG17, 0x400116d1 +.set CYREG_B1_P3_U1_CFG18, 0x400116d2 +.set CYREG_B1_P3_U1_CFG19, 0x400116d3 +.set CYREG_B1_P3_U1_CFG20, 0x400116d4 +.set CYREG_B1_P3_U1_CFG21, 0x400116d5 +.set CYREG_B1_P3_U1_CFG22, 0x400116d6 +.set CYREG_B1_P3_U1_CFG23, 0x400116d7 +.set CYREG_B1_P3_U1_CFG24, 0x400116d8 +.set CYREG_B1_P3_U1_CFG25, 0x400116d9 +.set CYREG_B1_P3_U1_CFG26, 0x400116da +.set CYREG_B1_P3_U1_CFG27, 0x400116db +.set CYREG_B1_P3_U1_CFG28, 0x400116dc +.set CYREG_B1_P3_U1_CFG29, 0x400116dd +.set CYREG_B1_P3_U1_CFG30, 0x400116de +.set CYREG_B1_P3_U1_CFG31, 0x400116df +.set CYREG_B1_P3_U1_DCFG0, 0x400116e0 +.set CYREG_B1_P3_U1_DCFG1, 0x400116e2 +.set CYREG_B1_P3_U1_DCFG2, 0x400116e4 +.set CYREG_B1_P3_U1_DCFG3, 0x400116e6 +.set CYREG_B1_P3_U1_DCFG4, 0x400116e8 +.set CYREG_B1_P3_U1_DCFG5, 0x400116ea +.set CYREG_B1_P3_U1_DCFG6, 0x400116ec +.set CYREG_B1_P3_U1_DCFG7, 0x400116ee +.set CYDEV_UCFG_B1_P3_ROUTE_BASE, 0x40011700 +.set CYDEV_UCFG_B1_P3_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P4_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P4_U0_BASE, 0x40011800 +.set CYDEV_UCFG_B1_P4_U0_SIZE, 0x00000070 +.set CYREG_B1_P4_U0_PLD_IT0, 0x40011800 +.set CYREG_B1_P4_U0_PLD_IT1, 0x40011804 +.set CYREG_B1_P4_U0_PLD_IT2, 0x40011808 +.set CYREG_B1_P4_U0_PLD_IT3, 0x4001180c +.set CYREG_B1_P4_U0_PLD_IT4, 0x40011810 +.set CYREG_B1_P4_U0_PLD_IT5, 0x40011814 +.set CYREG_B1_P4_U0_PLD_IT6, 0x40011818 +.set CYREG_B1_P4_U0_PLD_IT7, 0x4001181c +.set CYREG_B1_P4_U0_PLD_IT8, 0x40011820 +.set CYREG_B1_P4_U0_PLD_IT9, 0x40011824 +.set CYREG_B1_P4_U0_PLD_IT10, 0x40011828 +.set CYREG_B1_P4_U0_PLD_IT11, 0x4001182c +.set CYREG_B1_P4_U0_PLD_ORT0, 0x40011830 +.set CYREG_B1_P4_U0_PLD_ORT1, 0x40011832 +.set CYREG_B1_P4_U0_PLD_ORT2, 0x40011834 +.set CYREG_B1_P4_U0_PLD_ORT3, 0x40011836 +.set CYREG_B1_P4_U0_MC_CFG_CEN_CONST, 0x40011838 +.set CYREG_B1_P4_U0_MC_CFG_XORFB, 0x4001183a +.set CYREG_B1_P4_U0_MC_CFG_SET_RESET, 0x4001183c +.set CYREG_B1_P4_U0_MC_CFG_BYPASS, 0x4001183e +.set CYREG_B1_P4_U0_CFG0, 0x40011840 +.set CYREG_B1_P4_U0_CFG1, 0x40011841 +.set CYREG_B1_P4_U0_CFG2, 0x40011842 +.set CYREG_B1_P4_U0_CFG3, 0x40011843 +.set CYREG_B1_P4_U0_CFG4, 0x40011844 +.set CYREG_B1_P4_U0_CFG5, 0x40011845 +.set CYREG_B1_P4_U0_CFG6, 0x40011846 +.set CYREG_B1_P4_U0_CFG7, 0x40011847 +.set CYREG_B1_P4_U0_CFG8, 0x40011848 +.set CYREG_B1_P4_U0_CFG9, 0x40011849 +.set CYREG_B1_P4_U0_CFG10, 0x4001184a +.set CYREG_B1_P4_U0_CFG11, 0x4001184b +.set CYREG_B1_P4_U0_CFG12, 0x4001184c +.set CYREG_B1_P4_U0_CFG13, 0x4001184d +.set CYREG_B1_P4_U0_CFG14, 0x4001184e +.set CYREG_B1_P4_U0_CFG15, 0x4001184f +.set CYREG_B1_P4_U0_CFG16, 0x40011850 +.set CYREG_B1_P4_U0_CFG17, 0x40011851 +.set CYREG_B1_P4_U0_CFG18, 0x40011852 +.set CYREG_B1_P4_U0_CFG19, 0x40011853 +.set CYREG_B1_P4_U0_CFG20, 0x40011854 +.set CYREG_B1_P4_U0_CFG21, 0x40011855 +.set CYREG_B1_P4_U0_CFG22, 0x40011856 +.set CYREG_B1_P4_U0_CFG23, 0x40011857 +.set CYREG_B1_P4_U0_CFG24, 0x40011858 +.set CYREG_B1_P4_U0_CFG25, 0x40011859 +.set CYREG_B1_P4_U0_CFG26, 0x4001185a +.set CYREG_B1_P4_U0_CFG27, 0x4001185b +.set CYREG_B1_P4_U0_CFG28, 0x4001185c +.set CYREG_B1_P4_U0_CFG29, 0x4001185d +.set CYREG_B1_P4_U0_CFG30, 0x4001185e +.set CYREG_B1_P4_U0_CFG31, 0x4001185f +.set CYREG_B1_P4_U0_DCFG0, 0x40011860 +.set CYREG_B1_P4_U0_DCFG1, 0x40011862 +.set CYREG_B1_P4_U0_DCFG2, 0x40011864 +.set CYREG_B1_P4_U0_DCFG3, 0x40011866 +.set CYREG_B1_P4_U0_DCFG4, 0x40011868 +.set CYREG_B1_P4_U0_DCFG5, 0x4001186a +.set CYREG_B1_P4_U0_DCFG6, 0x4001186c +.set CYREG_B1_P4_U0_DCFG7, 0x4001186e +.set CYDEV_UCFG_B1_P4_U1_BASE, 0x40011880 +.set CYDEV_UCFG_B1_P4_U1_SIZE, 0x00000070 +.set CYREG_B1_P4_U1_PLD_IT0, 0x40011880 +.set CYREG_B1_P4_U1_PLD_IT1, 0x40011884 +.set CYREG_B1_P4_U1_PLD_IT2, 0x40011888 +.set CYREG_B1_P4_U1_PLD_IT3, 0x4001188c +.set CYREG_B1_P4_U1_PLD_IT4, 0x40011890 +.set CYREG_B1_P4_U1_PLD_IT5, 0x40011894 +.set CYREG_B1_P4_U1_PLD_IT6, 0x40011898 +.set CYREG_B1_P4_U1_PLD_IT7, 0x4001189c +.set CYREG_B1_P4_U1_PLD_IT8, 0x400118a0 +.set CYREG_B1_P4_U1_PLD_IT9, 0x400118a4 +.set CYREG_B1_P4_U1_PLD_IT10, 0x400118a8 +.set CYREG_B1_P4_U1_PLD_IT11, 0x400118ac +.set CYREG_B1_P4_U1_PLD_ORT0, 0x400118b0 +.set CYREG_B1_P4_U1_PLD_ORT1, 0x400118b2 +.set CYREG_B1_P4_U1_PLD_ORT2, 0x400118b4 +.set CYREG_B1_P4_U1_PLD_ORT3, 0x400118b6 +.set CYREG_B1_P4_U1_MC_CFG_CEN_CONST, 0x400118b8 +.set CYREG_B1_P4_U1_MC_CFG_XORFB, 0x400118ba +.set CYREG_B1_P4_U1_MC_CFG_SET_RESET, 0x400118bc +.set CYREG_B1_P4_U1_MC_CFG_BYPASS, 0x400118be +.set CYREG_B1_P4_U1_CFG0, 0x400118c0 +.set CYREG_B1_P4_U1_CFG1, 0x400118c1 +.set CYREG_B1_P4_U1_CFG2, 0x400118c2 +.set CYREG_B1_P4_U1_CFG3, 0x400118c3 +.set CYREG_B1_P4_U1_CFG4, 0x400118c4 +.set CYREG_B1_P4_U1_CFG5, 0x400118c5 +.set CYREG_B1_P4_U1_CFG6, 0x400118c6 +.set CYREG_B1_P4_U1_CFG7, 0x400118c7 +.set CYREG_B1_P4_U1_CFG8, 0x400118c8 +.set CYREG_B1_P4_U1_CFG9, 0x400118c9 +.set CYREG_B1_P4_U1_CFG10, 0x400118ca +.set CYREG_B1_P4_U1_CFG11, 0x400118cb +.set CYREG_B1_P4_U1_CFG12, 0x400118cc +.set CYREG_B1_P4_U1_CFG13, 0x400118cd +.set CYREG_B1_P4_U1_CFG14, 0x400118ce +.set CYREG_B1_P4_U1_CFG15, 0x400118cf +.set CYREG_B1_P4_U1_CFG16, 0x400118d0 +.set CYREG_B1_P4_U1_CFG17, 0x400118d1 +.set CYREG_B1_P4_U1_CFG18, 0x400118d2 +.set CYREG_B1_P4_U1_CFG19, 0x400118d3 +.set CYREG_B1_P4_U1_CFG20, 0x400118d4 +.set CYREG_B1_P4_U1_CFG21, 0x400118d5 +.set CYREG_B1_P4_U1_CFG22, 0x400118d6 +.set CYREG_B1_P4_U1_CFG23, 0x400118d7 +.set CYREG_B1_P4_U1_CFG24, 0x400118d8 +.set CYREG_B1_P4_U1_CFG25, 0x400118d9 +.set CYREG_B1_P4_U1_CFG26, 0x400118da +.set CYREG_B1_P4_U1_CFG27, 0x400118db +.set CYREG_B1_P4_U1_CFG28, 0x400118dc +.set CYREG_B1_P4_U1_CFG29, 0x400118dd +.set CYREG_B1_P4_U1_CFG30, 0x400118de +.set CYREG_B1_P4_U1_CFG31, 0x400118df +.set CYREG_B1_P4_U1_DCFG0, 0x400118e0 +.set CYREG_B1_P4_U1_DCFG1, 0x400118e2 +.set CYREG_B1_P4_U1_DCFG2, 0x400118e4 +.set CYREG_B1_P4_U1_DCFG3, 0x400118e6 +.set CYREG_B1_P4_U1_DCFG4, 0x400118e8 +.set CYREG_B1_P4_U1_DCFG5, 0x400118ea +.set CYREG_B1_P4_U1_DCFG6, 0x400118ec +.set CYREG_B1_P4_U1_DCFG7, 0x400118ee +.set CYDEV_UCFG_B1_P4_ROUTE_BASE, 0x40011900 +.set CYDEV_UCFG_B1_P4_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_B1_P5_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_SIZE, 0x000001ef +.set CYDEV_UCFG_B1_P5_U0_BASE, 0x40011a00 +.set CYDEV_UCFG_B1_P5_U0_SIZE, 0x00000070 +.set CYREG_B1_P5_U0_PLD_IT0, 0x40011a00 +.set CYREG_B1_P5_U0_PLD_IT1, 0x40011a04 +.set CYREG_B1_P5_U0_PLD_IT2, 0x40011a08 +.set CYREG_B1_P5_U0_PLD_IT3, 0x40011a0c +.set CYREG_B1_P5_U0_PLD_IT4, 0x40011a10 +.set CYREG_B1_P5_U0_PLD_IT5, 0x40011a14 +.set CYREG_B1_P5_U0_PLD_IT6, 0x40011a18 +.set CYREG_B1_P5_U0_PLD_IT7, 0x40011a1c +.set CYREG_B1_P5_U0_PLD_IT8, 0x40011a20 +.set CYREG_B1_P5_U0_PLD_IT9, 0x40011a24 +.set CYREG_B1_P5_U0_PLD_IT10, 0x40011a28 +.set CYREG_B1_P5_U0_PLD_IT11, 0x40011a2c +.set CYREG_B1_P5_U0_PLD_ORT0, 0x40011a30 +.set CYREG_B1_P5_U0_PLD_ORT1, 0x40011a32 +.set CYREG_B1_P5_U0_PLD_ORT2, 0x40011a34 +.set CYREG_B1_P5_U0_PLD_ORT3, 0x40011a36 +.set CYREG_B1_P5_U0_MC_CFG_CEN_CONST, 0x40011a38 +.set CYREG_B1_P5_U0_MC_CFG_XORFB, 0x40011a3a +.set CYREG_B1_P5_U0_MC_CFG_SET_RESET, 0x40011a3c +.set CYREG_B1_P5_U0_MC_CFG_BYPASS, 0x40011a3e +.set CYREG_B1_P5_U0_CFG0, 0x40011a40 +.set CYREG_B1_P5_U0_CFG1, 0x40011a41 +.set CYREG_B1_P5_U0_CFG2, 0x40011a42 +.set CYREG_B1_P5_U0_CFG3, 0x40011a43 +.set CYREG_B1_P5_U0_CFG4, 0x40011a44 +.set CYREG_B1_P5_U0_CFG5, 0x40011a45 +.set CYREG_B1_P5_U0_CFG6, 0x40011a46 +.set CYREG_B1_P5_U0_CFG7, 0x40011a47 +.set CYREG_B1_P5_U0_CFG8, 0x40011a48 +.set CYREG_B1_P5_U0_CFG9, 0x40011a49 +.set CYREG_B1_P5_U0_CFG10, 0x40011a4a +.set CYREG_B1_P5_U0_CFG11, 0x40011a4b +.set CYREG_B1_P5_U0_CFG12, 0x40011a4c +.set CYREG_B1_P5_U0_CFG13, 0x40011a4d +.set CYREG_B1_P5_U0_CFG14, 0x40011a4e +.set CYREG_B1_P5_U0_CFG15, 0x40011a4f +.set CYREG_B1_P5_U0_CFG16, 0x40011a50 +.set CYREG_B1_P5_U0_CFG17, 0x40011a51 +.set CYREG_B1_P5_U0_CFG18, 0x40011a52 +.set CYREG_B1_P5_U0_CFG19, 0x40011a53 +.set CYREG_B1_P5_U0_CFG20, 0x40011a54 +.set CYREG_B1_P5_U0_CFG21, 0x40011a55 +.set CYREG_B1_P5_U0_CFG22, 0x40011a56 +.set CYREG_B1_P5_U0_CFG23, 0x40011a57 +.set CYREG_B1_P5_U0_CFG24, 0x40011a58 +.set CYREG_B1_P5_U0_CFG25, 0x40011a59 +.set CYREG_B1_P5_U0_CFG26, 0x40011a5a +.set CYREG_B1_P5_U0_CFG27, 0x40011a5b +.set CYREG_B1_P5_U0_CFG28, 0x40011a5c +.set CYREG_B1_P5_U0_CFG29, 0x40011a5d +.set CYREG_B1_P5_U0_CFG30, 0x40011a5e +.set CYREG_B1_P5_U0_CFG31, 0x40011a5f +.set CYREG_B1_P5_U0_DCFG0, 0x40011a60 +.set CYREG_B1_P5_U0_DCFG1, 0x40011a62 +.set CYREG_B1_P5_U0_DCFG2, 0x40011a64 +.set CYREG_B1_P5_U0_DCFG3, 0x40011a66 +.set CYREG_B1_P5_U0_DCFG4, 0x40011a68 +.set CYREG_B1_P5_U0_DCFG5, 0x40011a6a +.set CYREG_B1_P5_U0_DCFG6, 0x40011a6c +.set CYREG_B1_P5_U0_DCFG7, 0x40011a6e +.set CYDEV_UCFG_B1_P5_U1_BASE, 0x40011a80 +.set CYDEV_UCFG_B1_P5_U1_SIZE, 0x00000070 +.set CYREG_B1_P5_U1_PLD_IT0, 0x40011a80 +.set CYREG_B1_P5_U1_PLD_IT1, 0x40011a84 +.set CYREG_B1_P5_U1_PLD_IT2, 0x40011a88 +.set CYREG_B1_P5_U1_PLD_IT3, 0x40011a8c +.set CYREG_B1_P5_U1_PLD_IT4, 0x40011a90 +.set CYREG_B1_P5_U1_PLD_IT5, 0x40011a94 +.set CYREG_B1_P5_U1_PLD_IT6, 0x40011a98 +.set CYREG_B1_P5_U1_PLD_IT7, 0x40011a9c +.set CYREG_B1_P5_U1_PLD_IT8, 0x40011aa0 +.set CYREG_B1_P5_U1_PLD_IT9, 0x40011aa4 +.set CYREG_B1_P5_U1_PLD_IT10, 0x40011aa8 +.set CYREG_B1_P5_U1_PLD_IT11, 0x40011aac +.set CYREG_B1_P5_U1_PLD_ORT0, 0x40011ab0 +.set CYREG_B1_P5_U1_PLD_ORT1, 0x40011ab2 +.set CYREG_B1_P5_U1_PLD_ORT2, 0x40011ab4 +.set CYREG_B1_P5_U1_PLD_ORT3, 0x40011ab6 +.set CYREG_B1_P5_U1_MC_CFG_CEN_CONST, 0x40011ab8 +.set CYREG_B1_P5_U1_MC_CFG_XORFB, 0x40011aba +.set CYREG_B1_P5_U1_MC_CFG_SET_RESET, 0x40011abc +.set CYREG_B1_P5_U1_MC_CFG_BYPASS, 0x40011abe +.set CYREG_B1_P5_U1_CFG0, 0x40011ac0 +.set CYREG_B1_P5_U1_CFG1, 0x40011ac1 +.set CYREG_B1_P5_U1_CFG2, 0x40011ac2 +.set CYREG_B1_P5_U1_CFG3, 0x40011ac3 +.set CYREG_B1_P5_U1_CFG4, 0x40011ac4 +.set CYREG_B1_P5_U1_CFG5, 0x40011ac5 +.set CYREG_B1_P5_U1_CFG6, 0x40011ac6 +.set CYREG_B1_P5_U1_CFG7, 0x40011ac7 +.set CYREG_B1_P5_U1_CFG8, 0x40011ac8 +.set CYREG_B1_P5_U1_CFG9, 0x40011ac9 +.set CYREG_B1_P5_U1_CFG10, 0x40011aca +.set CYREG_B1_P5_U1_CFG11, 0x40011acb +.set CYREG_B1_P5_U1_CFG12, 0x40011acc +.set CYREG_B1_P5_U1_CFG13, 0x40011acd +.set CYREG_B1_P5_U1_CFG14, 0x40011ace +.set CYREG_B1_P5_U1_CFG15, 0x40011acf +.set CYREG_B1_P5_U1_CFG16, 0x40011ad0 +.set CYREG_B1_P5_U1_CFG17, 0x40011ad1 +.set CYREG_B1_P5_U1_CFG18, 0x40011ad2 +.set CYREG_B1_P5_U1_CFG19, 0x40011ad3 +.set CYREG_B1_P5_U1_CFG20, 0x40011ad4 +.set CYREG_B1_P5_U1_CFG21, 0x40011ad5 +.set CYREG_B1_P5_U1_CFG22, 0x40011ad6 +.set CYREG_B1_P5_U1_CFG23, 0x40011ad7 +.set CYREG_B1_P5_U1_CFG24, 0x40011ad8 +.set CYREG_B1_P5_U1_CFG25, 0x40011ad9 +.set CYREG_B1_P5_U1_CFG26, 0x40011ada +.set CYREG_B1_P5_U1_CFG27, 0x40011adb +.set CYREG_B1_P5_U1_CFG28, 0x40011adc +.set CYREG_B1_P5_U1_CFG29, 0x40011add +.set CYREG_B1_P5_U1_CFG30, 0x40011ade +.set CYREG_B1_P5_U1_CFG31, 0x40011adf +.set CYREG_B1_P5_U1_DCFG0, 0x40011ae0 +.set CYREG_B1_P5_U1_DCFG1, 0x40011ae2 +.set CYREG_B1_P5_U1_DCFG2, 0x40011ae4 +.set CYREG_B1_P5_U1_DCFG3, 0x40011ae6 +.set CYREG_B1_P5_U1_DCFG4, 0x40011ae8 +.set CYREG_B1_P5_U1_DCFG5, 0x40011aea +.set CYREG_B1_P5_U1_DCFG6, 0x40011aec +.set CYREG_B1_P5_U1_DCFG7, 0x40011aee +.set CYDEV_UCFG_B1_P5_ROUTE_BASE, 0x40011b00 +.set CYDEV_UCFG_B1_P5_ROUTE_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI0_BASE, 0x40014000 +.set CYDEV_UCFG_DSI0_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI1_BASE, 0x40014100 +.set CYDEV_UCFG_DSI1_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI2_BASE, 0x40014200 +.set CYDEV_UCFG_DSI2_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI3_BASE, 0x40014300 +.set CYDEV_UCFG_DSI3_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI4_BASE, 0x40014400 +.set CYDEV_UCFG_DSI4_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI5_BASE, 0x40014500 +.set CYDEV_UCFG_DSI5_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI6_BASE, 0x40014600 +.set CYDEV_UCFG_DSI6_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI7_BASE, 0x40014700 +.set CYDEV_UCFG_DSI7_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI8_BASE, 0x40014800 +.set CYDEV_UCFG_DSI8_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI9_BASE, 0x40014900 +.set CYDEV_UCFG_DSI9_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI12_BASE, 0x40014c00 +.set CYDEV_UCFG_DSI12_SIZE, 0x000000ef +.set CYDEV_UCFG_DSI13_BASE, 0x40014d00 +.set CYDEV_UCFG_DSI13_SIZE, 0x000000ef +.set CYDEV_UCFG_BCTL0_BASE, 0x40015000 +.set CYDEV_UCFG_BCTL0_SIZE, 0x00000010 +.set CYREG_BCTL0_MDCLK_EN, 0x40015000 +.set CYREG_BCTL0_MBCLK_EN, 0x40015001 +.set CYREG_BCTL0_WAIT_CFG, 0x40015002 +.set CYREG_BCTL0_BANK_CTL, 0x40015003 +.set CYREG_BCTL0_UDB_TEST_3, 0x40015007 +.set CYREG_BCTL0_DCLK_EN0, 0x40015008 +.set CYREG_BCTL0_BCLK_EN0, 0x40015009 +.set CYREG_BCTL0_DCLK_EN1, 0x4001500a +.set CYREG_BCTL0_BCLK_EN1, 0x4001500b +.set CYREG_BCTL0_DCLK_EN2, 0x4001500c +.set CYREG_BCTL0_BCLK_EN2, 0x4001500d +.set CYREG_BCTL0_DCLK_EN3, 0x4001500e +.set CYREG_BCTL0_BCLK_EN3, 0x4001500f +.set CYDEV_UCFG_BCTL1_BASE, 0x40015010 +.set CYDEV_UCFG_BCTL1_SIZE, 0x00000010 +.set CYREG_BCTL1_MDCLK_EN, 0x40015010 +.set CYREG_BCTL1_MBCLK_EN, 0x40015011 +.set CYREG_BCTL1_WAIT_CFG, 0x40015012 +.set CYREG_BCTL1_BANK_CTL, 0x40015013 +.set CYREG_BCTL1_UDB_TEST_3, 0x40015017 +.set CYREG_BCTL1_DCLK_EN0, 0x40015018 +.set CYREG_BCTL1_BCLK_EN0, 0x40015019 +.set CYREG_BCTL1_DCLK_EN1, 0x4001501a +.set CYREG_BCTL1_BCLK_EN1, 0x4001501b +.set CYREG_BCTL1_DCLK_EN2, 0x4001501c +.set CYREG_BCTL1_BCLK_EN2, 0x4001501d +.set CYREG_BCTL1_DCLK_EN3, 0x4001501e +.set CYREG_BCTL1_BCLK_EN3, 0x4001501f +.set CYDEV_IDMUX_BASE, 0x40015100 +.set CYDEV_IDMUX_SIZE, 0x00000016 +.set CYREG_IDMUX_IRQ_CTL0, 0x40015100 +.set CYREG_IDMUX_IRQ_CTL1, 0x40015101 +.set CYREG_IDMUX_IRQ_CTL2, 0x40015102 +.set CYREG_IDMUX_IRQ_CTL3, 0x40015103 +.set CYREG_IDMUX_IRQ_CTL4, 0x40015104 +.set CYREG_IDMUX_IRQ_CTL5, 0x40015105 +.set CYREG_IDMUX_IRQ_CTL6, 0x40015106 +.set CYREG_IDMUX_IRQ_CTL7, 0x40015107 +.set CYREG_IDMUX_DRQ_CTL0, 0x40015110 +.set CYREG_IDMUX_DRQ_CTL1, 0x40015111 +.set CYREG_IDMUX_DRQ_CTL2, 0x40015112 +.set CYREG_IDMUX_DRQ_CTL3, 0x40015113 +.set CYREG_IDMUX_DRQ_CTL4, 0x40015114 +.set CYREG_IDMUX_DRQ_CTL5, 0x40015115 +.set CYDEV_CACHERAM_BASE, 0x40030000 +.set CYDEV_CACHERAM_SIZE, 0x00000400 +.set CYREG_CACHERAM_DATA_MBASE, 0x40030000 +.set CYREG_CACHERAM_DATA_MSIZE, 0x00000400 +.set CYDEV_SFR_BASE, 0x40050100 +.set CYDEV_SFR_SIZE, 0x000000fb +.set CYREG_SFR_GPIO0, 0x40050180 +.set CYREG_SFR_GPIRD0, 0x40050189 +.set CYREG_SFR_GPIO0_SEL, 0x4005018a +.set CYREG_SFR_GPIO1, 0x40050190 +.set CYREG_SFR_GPIRD1, 0x40050191 +.set CYREG_SFR_GPIO2, 0x40050198 +.set CYREG_SFR_GPIRD2, 0x40050199 +.set CYREG_SFR_GPIO2_SEL, 0x4005019a +.set CYREG_SFR_GPIO1_SEL, 0x400501a2 +.set CYREG_SFR_GPIO3, 0x400501b0 +.set CYREG_SFR_GPIRD3, 0x400501b1 +.set CYREG_SFR_GPIO3_SEL, 0x400501b2 +.set CYREG_SFR_GPIO4, 0x400501c0 +.set CYREG_SFR_GPIRD4, 0x400501c1 +.set CYREG_SFR_GPIO4_SEL, 0x400501c2 +.set CYREG_SFR_GPIO5, 0x400501c8 +.set CYREG_SFR_GPIRD5, 0x400501c9 +.set CYREG_SFR_GPIO5_SEL, 0x400501ca +.set CYREG_SFR_GPIO6, 0x400501d8 +.set CYREG_SFR_GPIRD6, 0x400501d9 +.set CYREG_SFR_GPIO6_SEL, 0x400501da +.set CYREG_SFR_GPIO12, 0x400501e8 +.set CYREG_SFR_GPIRD12, 0x400501e9 +.set CYREG_SFR_GPIO12_SEL, 0x400501f2 +.set CYREG_SFR_GPIO15, 0x400501f8 +.set CYREG_SFR_GPIRD15, 0x400501f9 +.set CYREG_SFR_GPIO15_SEL, 0x400501fa +.set CYDEV_P3BA_BASE, 0x40050300 +.set CYDEV_P3BA_SIZE, 0x0000002b +.set CYREG_P3BA_Y_START, 0x40050300 +.set CYREG_P3BA_YROLL, 0x40050301 +.set CYREG_P3BA_YCFG, 0x40050302 +.set CYREG_P3BA_X_START1, 0x40050303 +.set CYREG_P3BA_X_START2, 0x40050304 +.set CYREG_P3BA_XROLL1, 0x40050305 +.set CYREG_P3BA_XROLL2, 0x40050306 +.set CYREG_P3BA_XINC, 0x40050307 +.set CYREG_P3BA_XCFG, 0x40050308 +.set CYREG_P3BA_OFFSETADDR1, 0x40050309 +.set CYREG_P3BA_OFFSETADDR2, 0x4005030a +.set CYREG_P3BA_OFFSETADDR3, 0x4005030b +.set CYREG_P3BA_ABSADDR1, 0x4005030c +.set CYREG_P3BA_ABSADDR2, 0x4005030d +.set CYREG_P3BA_ABSADDR3, 0x4005030e +.set CYREG_P3BA_ABSADDR4, 0x4005030f +.set CYREG_P3BA_DATCFG1, 0x40050310 +.set CYREG_P3BA_DATCFG2, 0x40050311 +.set CYREG_P3BA_CMP_RSLT1, 0x40050314 +.set CYREG_P3BA_CMP_RSLT2, 0x40050315 +.set CYREG_P3BA_CMP_RSLT3, 0x40050316 +.set CYREG_P3BA_CMP_RSLT4, 0x40050317 +.set CYREG_P3BA_DATA_REG1, 0x40050318 +.set CYREG_P3BA_DATA_REG2, 0x40050319 +.set CYREG_P3BA_DATA_REG3, 0x4005031a +.set CYREG_P3BA_DATA_REG4, 0x4005031b +.set CYREG_P3BA_EXP_DATA1, 0x4005031c +.set CYREG_P3BA_EXP_DATA2, 0x4005031d +.set CYREG_P3BA_EXP_DATA3, 0x4005031e +.set CYREG_P3BA_EXP_DATA4, 0x4005031f +.set CYREG_P3BA_MSTR_HRDATA1, 0x40050320 +.set CYREG_P3BA_MSTR_HRDATA2, 0x40050321 +.set CYREG_P3BA_MSTR_HRDATA3, 0x40050322 +.set CYREG_P3BA_MSTR_HRDATA4, 0x40050323 +.set CYREG_P3BA_BIST_EN, 0x40050324 +.set CYREG_P3BA_PHUB_MASTER_SSR, 0x40050325 +.set CYREG_P3BA_SEQCFG1, 0x40050326 +.set CYREG_P3BA_SEQCFG2, 0x40050327 +.set CYREG_P3BA_Y_CURR, 0x40050328 +.set CYREG_P3BA_X_CURR1, 0x40050329 +.set CYREG_P3BA_X_CURR2, 0x4005032a +.set CYDEV_PANTHER_BASE, 0x40080000 +.set CYDEV_PANTHER_SIZE, 0x00000020 +.set CYREG_PANTHER_STCALIB_CFG, 0x40080000 +.set CYREG_PANTHER_WAITPIPE, 0x40080004 +.set CYREG_PANTHER_TRACE_CFG, 0x40080008 +.set CYREG_PANTHER_DBG_CFG, 0x4008000c +.set CYREG_PANTHER_CM3_LCKRST_STAT, 0x40080018 +.set CYREG_PANTHER_DEVICE_ID, 0x4008001c +.set CYDEV_FLSECC_BASE, 0x48000000 +.set CYDEV_FLSECC_SIZE, 0x00008000 +.set CYREG_FLSECC_DATA_MBASE, 0x48000000 +.set CYREG_FLSECC_DATA_MSIZE, 0x00008000 +.set CYDEV_FLSHID_BASE, 0x49000000 +.set CYDEV_FLSHID_SIZE, 0x00000200 +.set CYREG_FLSHID_RSVD_MBASE, 0x49000000 +.set CYREG_FLSHID_RSVD_MSIZE, 0x00000080 +.set CYREG_FLSHID_CUST_MDATA_MBASE, 0x49000080 +.set CYREG_FLSHID_CUST_MDATA_MSIZE, 0x00000080 +.set CYDEV_FLSHID_CUST_TABLES_BASE, 0x49000100 +.set CYDEV_FLSHID_CUST_TABLES_SIZE, 0x00000040 +.set CYREG_FLSHID_CUST_TABLES_Y_LOC, 0x49000100 +.set CYREG_FLSHID_CUST_TABLES_X_LOC, 0x49000101 +.set CYREG_FLSHID_CUST_TABLES_WAFER_NUM, 0x49000102 +.set CYREG_FLSHID_CUST_TABLES_LOT_LSB, 0x49000103 +.set CYREG_FLSHID_CUST_TABLES_LOT_MSB, 0x49000104 +.set CYREG_FLSHID_CUST_TABLES_WRK_WK, 0x49000105 +.set CYREG_FLSHID_CUST_TABLES_FAB_YR, 0x49000106 +.set CYREG_FLSHID_CUST_TABLES_MINOR, 0x49000107 +.set CYREG_FLSHID_CUST_TABLES_IMO_3MHZ, 0x49000108 +.set CYREG_FLSHID_CUST_TABLES_IMO_6MHZ, 0x49000109 +.set CYREG_FLSHID_CUST_TABLES_IMO_12MHZ, 0x4900010a +.set CYREG_FLSHID_CUST_TABLES_IMO_24MHZ, 0x4900010b +.set CYREG_FLSHID_CUST_TABLES_IMO_67MHZ, 0x4900010c +.set CYREG_FLSHID_CUST_TABLES_IMO_80MHZ, 0x4900010d +.set CYREG_FLSHID_CUST_TABLES_IMO_92MHZ, 0x4900010e +.set CYREG_FLSHID_CUST_TABLES_IMO_USB, 0x4900010f +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS, 0x49000110 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS, 0x49000111 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS, 0x49000112 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS, 0x49000113 +.set CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS, 0x49000114 +.set CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS, 0x49000115 +.set CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS, 0x49000116 +.set CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS, 0x49000117 +.set CYREG_FLSHID_CUST_TABLES_DEC_M1, 0x49000118 +.set CYREG_FLSHID_CUST_TABLES_DEC_M2, 0x49000119 +.set CYREG_FLSHID_CUST_TABLES_DEC_M3, 0x4900011a +.set CYREG_FLSHID_CUST_TABLES_DEC_M4, 0x4900011b +.set CYREG_FLSHID_CUST_TABLES_DEC_M5, 0x4900011c +.set CYREG_FLSHID_CUST_TABLES_DEC_M6, 0x4900011d +.set CYREG_FLSHID_CUST_TABLES_DEC_M7, 0x4900011e +.set CYREG_FLSHID_CUST_TABLES_DEC_M8, 0x4900011f +.set CYREG_FLSHID_CUST_TABLES_DAC0_M1, 0x49000120 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M2, 0x49000121 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M3, 0x49000122 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M4, 0x49000123 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M5, 0x49000124 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M6, 0x49000125 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M7, 0x49000126 +.set CYREG_FLSHID_CUST_TABLES_DAC0_M8, 0x49000127 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M1, 0x49000128 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M2, 0x49000129 +.set CYREG_FLSHID_CUST_TABLES_DAC2_M3, 0x4900012a +.set CYREG_FLSHID_CUST_TABLES_DAC2_M4, 0x4900012b +.set CYREG_FLSHID_CUST_TABLES_DAC2_M5, 0x4900012c +.set CYREG_FLSHID_CUST_TABLES_DAC2_M6, 0x4900012d +.set CYREG_FLSHID_CUST_TABLES_DAC2_M7, 0x4900012e +.set CYREG_FLSHID_CUST_TABLES_DAC2_M8, 0x4900012f +.set CYREG_FLSHID_CUST_TABLES_DAC1_M1, 0x49000130 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M2, 0x49000131 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M3, 0x49000132 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M4, 0x49000133 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M5, 0x49000134 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M6, 0x49000135 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M7, 0x49000136 +.set CYREG_FLSHID_CUST_TABLES_DAC1_M8, 0x49000137 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M1, 0x49000138 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M2, 0x49000139 +.set CYREG_FLSHID_CUST_TABLES_DAC3_M3, 0x4900013a +.set CYREG_FLSHID_CUST_TABLES_DAC3_M4, 0x4900013b +.set CYREG_FLSHID_CUST_TABLES_DAC3_M5, 0x4900013c +.set CYREG_FLSHID_CUST_TABLES_DAC3_M6, 0x4900013d +.set CYREG_FLSHID_CUST_TABLES_DAC3_M7, 0x4900013e +.set CYREG_FLSHID_CUST_TABLES_DAC3_M8, 0x4900013f +.set CYDEV_FLSHID_MFG_CFG_BASE, 0x49000180 +.set CYDEV_FLSHID_MFG_CFG_SIZE, 0x00000080 +.set CYREG_FLSHID_MFG_CFG_IMO_TR1, 0x49000188 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR0, 0x490001ac +.set CYREG_FLSHID_MFG_CFG_CMP1_TR0, 0x490001ae +.set CYREG_FLSHID_MFG_CFG_CMP2_TR0, 0x490001b0 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR0, 0x490001b2 +.set CYREG_FLSHID_MFG_CFG_CMP0_TR1, 0x490001b4 +.set CYREG_FLSHID_MFG_CFG_CMP1_TR1, 0x490001b6 +.set CYREG_FLSHID_MFG_CFG_CMP2_TR1, 0x490001b8 +.set CYREG_FLSHID_MFG_CFG_CMP3_TR1, 0x490001ba +.set CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM, 0x490001ce +.set CYDEV_EXTMEM_BASE, 0x60000000 +.set CYDEV_EXTMEM_SIZE, 0x00800000 +.set CYREG_EXTMEM_DATA_MBASE, 0x60000000 +.set CYREG_EXTMEM_DATA_MSIZE, 0x00800000 +.set CYDEV_ITM_BASE, 0xe0000000 +.set CYDEV_ITM_SIZE, 0x00001000 +.set CYREG_ITM_TRACE_EN, 0xe0000e00 +.set CYREG_ITM_TRACE_PRIVILEGE, 0xe0000e40 +.set CYREG_ITM_TRACE_CTRL, 0xe0000e80 +.set CYREG_ITM_LOCK_ACCESS, 0xe0000fb0 +.set CYREG_ITM_LOCK_STATUS, 0xe0000fb4 +.set CYREG_ITM_PID4, 0xe0000fd0 +.set CYREG_ITM_PID5, 0xe0000fd4 +.set CYREG_ITM_PID6, 0xe0000fd8 +.set CYREG_ITM_PID7, 0xe0000fdc +.set CYREG_ITM_PID0, 0xe0000fe0 +.set CYREG_ITM_PID1, 0xe0000fe4 +.set CYREG_ITM_PID2, 0xe0000fe8 +.set CYREG_ITM_PID3, 0xe0000fec +.set CYREG_ITM_CID0, 0xe0000ff0 +.set CYREG_ITM_CID1, 0xe0000ff4 +.set CYREG_ITM_CID2, 0xe0000ff8 +.set CYREG_ITM_CID3, 0xe0000ffc +.set CYDEV_DWT_BASE, 0xe0001000 +.set CYDEV_DWT_SIZE, 0x0000005c +.set CYREG_DWT_CTRL, 0xe0001000 +.set CYREG_DWT_CYCLE_COUNT, 0xe0001004 +.set CYREG_DWT_CPI_COUNT, 0xe0001008 +.set CYREG_DWT_EXC_OVHD_COUNT, 0xe000100c +.set CYREG_DWT_SLEEP_COUNT, 0xe0001010 +.set CYREG_DWT_LSU_COUNT, 0xe0001014 +.set CYREG_DWT_FOLD_COUNT, 0xe0001018 +.set CYREG_DWT_PC_SAMPLE, 0xe000101c +.set CYREG_DWT_COMP_0, 0xe0001020 +.set CYREG_DWT_MASK_0, 0xe0001024 +.set CYREG_DWT_FUNCTION_0, 0xe0001028 +.set CYREG_DWT_COMP_1, 0xe0001030 +.set CYREG_DWT_MASK_1, 0xe0001034 +.set CYREG_DWT_FUNCTION_1, 0xe0001038 +.set CYREG_DWT_COMP_2, 0xe0001040 +.set CYREG_DWT_MASK_2, 0xe0001044 +.set CYREG_DWT_FUNCTION_2, 0xe0001048 +.set CYREG_DWT_COMP_3, 0xe0001050 +.set CYREG_DWT_MASK_3, 0xe0001054 +.set CYREG_DWT_FUNCTION_3, 0xe0001058 +.set CYDEV_FPB_BASE, 0xe0002000 +.set CYDEV_FPB_SIZE, 0x00001000 +.set CYREG_FPB_CTRL, 0xe0002000 +.set CYREG_FPB_REMAP, 0xe0002004 +.set CYREG_FPB_FP_COMP_0, 0xe0002008 +.set CYREG_FPB_FP_COMP_1, 0xe000200c +.set CYREG_FPB_FP_COMP_2, 0xe0002010 +.set CYREG_FPB_FP_COMP_3, 0xe0002014 +.set CYREG_FPB_FP_COMP_4, 0xe0002018 +.set CYREG_FPB_FP_COMP_5, 0xe000201c +.set CYREG_FPB_FP_COMP_6, 0xe0002020 +.set CYREG_FPB_FP_COMP_7, 0xe0002024 +.set CYREG_FPB_PID4, 0xe0002fd0 +.set CYREG_FPB_PID5, 0xe0002fd4 +.set CYREG_FPB_PID6, 0xe0002fd8 +.set CYREG_FPB_PID7, 0xe0002fdc +.set CYREG_FPB_PID0, 0xe0002fe0 +.set CYREG_FPB_PID1, 0xe0002fe4 +.set CYREG_FPB_PID2, 0xe0002fe8 +.set CYREG_FPB_PID3, 0xe0002fec +.set CYREG_FPB_CID0, 0xe0002ff0 +.set CYREG_FPB_CID1, 0xe0002ff4 +.set CYREG_FPB_CID2, 0xe0002ff8 +.set CYREG_FPB_CID3, 0xe0002ffc +.set CYDEV_NVIC_BASE, 0xe000e000 +.set CYDEV_NVIC_SIZE, 0x00000d3c +.set CYREG_NVIC_INT_CTL_TYPE, 0xe000e004 +.set CYREG_NVIC_SYSTICK_CTL, 0xe000e010 +.set CYREG_NVIC_SYSTICK_RELOAD, 0xe000e014 +.set CYREG_NVIC_SYSTICK_CURRENT, 0xe000e018 +.set CYREG_NVIC_SYSTICK_CAL, 0xe000e01c +.set CYREG_NVIC_SETENA0, 0xe000e100 +.set CYREG_NVIC_CLRENA0, 0xe000e180 +.set CYREG_NVIC_SETPEND0, 0xe000e200 +.set CYREG_NVIC_CLRPEND0, 0xe000e280 +.set CYREG_NVIC_ACTIVE0, 0xe000e300 +.set CYREG_NVIC_PRI_0, 0xe000e400 +.set CYREG_NVIC_PRI_1, 0xe000e401 +.set CYREG_NVIC_PRI_2, 0xe000e402 +.set CYREG_NVIC_PRI_3, 0xe000e403 +.set CYREG_NVIC_PRI_4, 0xe000e404 +.set CYREG_NVIC_PRI_5, 0xe000e405 +.set CYREG_NVIC_PRI_6, 0xe000e406 +.set CYREG_NVIC_PRI_7, 0xe000e407 +.set CYREG_NVIC_PRI_8, 0xe000e408 +.set CYREG_NVIC_PRI_9, 0xe000e409 +.set CYREG_NVIC_PRI_10, 0xe000e40a +.set CYREG_NVIC_PRI_11, 0xe000e40b +.set CYREG_NVIC_PRI_12, 0xe000e40c +.set CYREG_NVIC_PRI_13, 0xe000e40d +.set CYREG_NVIC_PRI_14, 0xe000e40e +.set CYREG_NVIC_PRI_15, 0xe000e40f +.set CYREG_NVIC_PRI_16, 0xe000e410 +.set CYREG_NVIC_PRI_17, 0xe000e411 +.set CYREG_NVIC_PRI_18, 0xe000e412 +.set CYREG_NVIC_PRI_19, 0xe000e413 +.set CYREG_NVIC_PRI_20, 0xe000e414 +.set CYREG_NVIC_PRI_21, 0xe000e415 +.set CYREG_NVIC_PRI_22, 0xe000e416 +.set CYREG_NVIC_PRI_23, 0xe000e417 +.set CYREG_NVIC_PRI_24, 0xe000e418 +.set CYREG_NVIC_PRI_25, 0xe000e419 +.set CYREG_NVIC_PRI_26, 0xe000e41a +.set CYREG_NVIC_PRI_27, 0xe000e41b +.set CYREG_NVIC_PRI_28, 0xe000e41c +.set CYREG_NVIC_PRI_29, 0xe000e41d +.set CYREG_NVIC_PRI_30, 0xe000e41e +.set CYREG_NVIC_PRI_31, 0xe000e41f +.set CYREG_NVIC_CPUID_BASE, 0xe000ed00 +.set CYREG_NVIC_INTR_CTRL_STATE, 0xe000ed04 +.set CYREG_NVIC_VECT_OFFSET, 0xe000ed08 +.set CYREG_NVIC_APPLN_INTR, 0xe000ed0c +.set CYREG_NVIC_SYSTEM_CONTROL, 0xe000ed10 +.set CYREG_NVIC_CFG_CONTROL, 0xe000ed14 +.set CYREG_NVIC_SYS_PRIO_HANDLER_4_7, 0xe000ed18 +.set CYREG_NVIC_SYS_PRIO_HANDLER_8_11, 0xe000ed1c +.set CYREG_NVIC_SYS_PRIO_HANDLER_12_15, 0xe000ed20 +.set CYREG_NVIC_SYS_HANDLER_CSR, 0xe000ed24 +.set CYREG_NVIC_MEMMAN_FAULT_STATUS, 0xe000ed28 +.set CYREG_NVIC_BUS_FAULT_STATUS, 0xe000ed29 +.set CYREG_NVIC_USAGE_FAULT_STATUS, 0xe000ed2a +.set CYREG_NVIC_HARD_FAULT_STATUS, 0xe000ed2c +.set CYREG_NVIC_DEBUG_FAULT_STATUS, 0xe000ed30 +.set CYREG_NVIC_MEMMAN_FAULT_ADD, 0xe000ed34 +.set CYREG_NVIC_BUS_FAULT_ADD, 0xe000ed38 +.set CYDEV_CORE_DBG_BASE, 0xe000edf0 +.set CYDEV_CORE_DBG_SIZE, 0x00000010 +.set CYREG_CORE_DBG_DBG_HLT_CS, 0xe000edf0 +.set CYREG_CORE_DBG_DBG_REG_SEL, 0xe000edf4 +.set CYREG_CORE_DBG_DBG_REG_DATA, 0xe000edf8 +.set CYREG_CORE_DBG_EXC_MON_CTL, 0xe000edfc +.set CYDEV_TPIU_BASE, 0xe0040000 +.set CYDEV_TPIU_SIZE, 0x00001000 +.set CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ, 0xe0040000 +.set CYREG_TPIU_CURRENT_SYNC_PRT_SZ, 0xe0040004 +.set CYREG_TPIU_ASYNC_CLK_PRESCALER, 0xe0040010 +.set CYREG_TPIU_PROTOCOL, 0xe00400f0 +.set CYREG_TPIU_FORM_FLUSH_STAT, 0xe0040300 +.set CYREG_TPIU_FORM_FLUSH_CTRL, 0xe0040304 +.set CYREG_TPIU_TRIGGER, 0xe0040ee8 +.set CYREG_TPIU_ITETMDATA, 0xe0040eec +.set CYREG_TPIU_ITATBCTR2, 0xe0040ef0 +.set CYREG_TPIU_ITATBCTR0, 0xe0040ef8 +.set CYREG_TPIU_ITITMDATA, 0xe0040efc +.set CYREG_TPIU_ITCTRL, 0xe0040f00 +.set CYREG_TPIU_DEVID, 0xe0040fc8 +.set CYREG_TPIU_DEVTYPE, 0xe0040fcc +.set CYREG_TPIU_PID4, 0xe0040fd0 +.set CYREG_TPIU_PID5, 0xe0040fd4 +.set CYREG_TPIU_PID6, 0xe0040fd8 +.set CYREG_TPIU_PID7, 0xe0040fdc +.set CYREG_TPIU_PID0, 0xe0040fe0 +.set CYREG_TPIU_PID1, 0xe0040fe4 +.set CYREG_TPIU_PID2, 0xe0040fe8 +.set CYREG_TPIU_PID3, 0xe0040fec +.set CYREG_TPIU_CID0, 0xe0040ff0 +.set CYREG_TPIU_CID1, 0xe0040ff4 +.set CYREG_TPIU_CID2, 0xe0040ff8 +.set CYREG_TPIU_CID3, 0xe0040ffc +.set CYDEV_ETM_BASE, 0xe0041000 +.set CYDEV_ETM_SIZE, 0x00001000 +.set CYREG_ETM_CTL, 0xe0041000 +.set CYREG_ETM_CFG_CODE, 0xe0041004 +.set CYREG_ETM_TRIG_EVENT, 0xe0041008 +.set CYREG_ETM_STATUS, 0xe0041010 +.set CYREG_ETM_SYS_CFG, 0xe0041014 +.set CYREG_ETM_TRACE_ENB_EVENT, 0xe0041020 +.set CYREG_ETM_TRACE_EN_CTRL1, 0xe0041024 +.set CYREG_ETM_FIFOFULL_LEVEL, 0xe004102c +.set CYREG_ETM_SYNC_FREQ, 0xe00411e0 +.set CYREG_ETM_ETM_ID, 0xe00411e4 +.set CYREG_ETM_CFG_CODE_EXT, 0xe00411e8 +.set CYREG_ETM_TR_SS_EMBICE_CTRL, 0xe00411f0 +.set CYREG_ETM_CS_TRACE_ID, 0xe0041200 +.set CYREG_ETM_OS_LOCK_ACCESS, 0xe0041300 +.set CYREG_ETM_OS_LOCK_STATUS, 0xe0041304 +.set CYREG_ETM_PDSR, 0xe0041314 +.set CYREG_ETM_ITMISCIN, 0xe0041ee0 +.set CYREG_ETM_ITTRIGOUT, 0xe0041ee8 +.set CYREG_ETM_ITATBCTR2, 0xe0041ef0 +.set CYREG_ETM_ITATBCTR0, 0xe0041ef8 +.set CYREG_ETM_INT_MODE_CTRL, 0xe0041f00 +.set CYREG_ETM_CLM_TAG_SET, 0xe0041fa0 +.set CYREG_ETM_CLM_TAG_CLR, 0xe0041fa4 +.set CYREG_ETM_LOCK_ACCESS, 0xe0041fb0 +.set CYREG_ETM_LOCK_STATUS, 0xe0041fb4 +.set CYREG_ETM_AUTH_STATUS, 0xe0041fb8 +.set CYREG_ETM_DEV_TYPE, 0xe0041fcc +.set CYREG_ETM_PID4, 0xe0041fd0 +.set CYREG_ETM_PID5, 0xe0041fd4 +.set CYREG_ETM_PID6, 0xe0041fd8 +.set CYREG_ETM_PID7, 0xe0041fdc +.set CYREG_ETM_PID0, 0xe0041fe0 +.set CYREG_ETM_PID1, 0xe0041fe4 +.set CYREG_ETM_PID2, 0xe0041fe8 +.set CYREG_ETM_PID3, 0xe0041fec +.set CYREG_ETM_CID0, 0xe0041ff0 +.set CYREG_ETM_CID1, 0xe0041ff4 +.set CYREG_ETM_CID2, 0xe0041ff8 +.set CYREG_ETM_CID3, 0xe0041ffc +.set CYDEV_ROM_TABLE_BASE, 0xe00ff000 +.set CYDEV_ROM_TABLE_SIZE, 0x00001000 +.set CYREG_ROM_TABLE_NVIC, 0xe00ff000 +.set CYREG_ROM_TABLE_DWT, 0xe00ff004 +.set CYREG_ROM_TABLE_FPB, 0xe00ff008 +.set CYREG_ROM_TABLE_ITM, 0xe00ff00c +.set CYREG_ROM_TABLE_TPIU, 0xe00ff010 +.set CYREG_ROM_TABLE_ETM, 0xe00ff014 +.set CYREG_ROM_TABLE_END, 0xe00ff018 +.set CYREG_ROM_TABLE_MEMTYPE, 0xe00fffcc +.set CYREG_ROM_TABLE_PID4, 0xe00fffd0 +.set CYREG_ROM_TABLE_PID5, 0xe00fffd4 +.set CYREG_ROM_TABLE_PID6, 0xe00fffd8 +.set CYREG_ROM_TABLE_PID7, 0xe00fffdc +.set CYREG_ROM_TABLE_PID0, 0xe00fffe0 +.set CYREG_ROM_TABLE_PID1, 0xe00fffe4 +.set CYREG_ROM_TABLE_PID2, 0xe00fffe8 +.set CYREG_ROM_TABLE_PID3, 0xe00fffec +.set CYREG_ROM_TABLE_CID0, 0xe00ffff0 +.set CYREG_ROM_TABLE_CID1, 0xe00ffff4 +.set CYREG_ROM_TABLE_CID2, 0xe00ffff8 +.set CYREG_ROM_TABLE_CID3, 0xe00ffffc +.set CYDEV_FLS_SIZE, CYDEV_FLASH_SIZE +.set CYDEV_ECC_BASE, CYDEV_FLSECC_BASE +.set CYDEV_FLS_SECTOR_SIZE, 0x00010000 +.set CYDEV_FLS_ROW_SIZE, 0x00000100 +.set CYDEV_ECC_SECTOR_SIZE, 0x00002000 +.set CYDEV_ECC_ROW_SIZE, 0x00000020 +.set CYDEV_EEPROM_SECTOR_SIZE, 0x00000400 +.set CYDEV_EEPROM_ROW_SIZE, 0x00000010 +.set CYDEV_PERIPH_BASE, CYDEV_CLKDIST_BASE +.set CYCLK_LD_DISABLE, 0x00000004 +.set CYCLK_LD_SYNC_EN, 0x00000002 +.set CYCLK_LD_LOAD, 0x00000001 +.set CYCLK_PIPE, 0x00000080 +.set CYCLK_SSS, 0x00000040 +.set CYCLK_EARLY, 0x00000020 +.set CYCLK_DUTY, 0x00000010 +.set CYCLK_SYNC, 0x00000008 +.set CYCLK_SRC_SEL_CLK_SYNC_D, 0 +.set CYCLK_SRC_SEL_SYNC_DIG, 0 +.set CYCLK_SRC_SEL_IMO, 1 +.set CYCLK_SRC_SEL_XTAL_MHZ, 2 +.set CYCLK_SRC_SEL_XTALM, 2 +.set CYCLK_SRC_SEL_ILO, 3 +.set CYCLK_SRC_SEL_PLL, 4 +.set CYCLK_SRC_SEL_XTAL_KHZ, 5 +.set CYCLK_SRC_SEL_XTALK, 5 +.set CYCLK_SRC_SEL_DSI_G, 6 +.set CYCLK_SRC_SEL_DSI_D, 7 +.set CYCLK_SRC_SEL_CLK_SYNC_A, 0 +.set CYCLK_SRC_SEL_DSI_A, 7 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc new file mode 100644 index 0000000..147a861 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar.inc @@ -0,0 +1,5356 @@ +; +; File Name: cydeviceiar.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYDEV_FLASH_DATA_MBASE 0x00000000 +#define CYDEV_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYDEV_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYDEV_SRAM_CODE64K_MSIZE 0x00004000 +#define CYDEV_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE32K_MSIZE 0x00002000 +#define CYDEV_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYDEV_SRAM_CODE16K_MSIZE 0x00001000 +#define CYDEV_SRAM_CODE_MBASE 0x1fffc000 +#define CYDEV_SRAM_CODE_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA_MBASE 0x20000000 +#define CYDEV_SRAM_DATA_MSIZE 0x00004000 +#define CYDEV_SRAM_DATA16K_MBASE 0x20001000 +#define CYDEV_SRAM_DATA16K_MSIZE 0x00001000 +#define CYDEV_SRAM_DATA32K_MBASE 0x20002000 +#define CYDEV_SRAM_DATA32K_MSIZE 0x00002000 +#define CYDEV_SRAM_DATA64K_MBASE 0x20004000 +#define CYDEV_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYDEV_DMA_SRAM64K_MBASE 0x20008000 +#define CYDEV_DMA_SRAM64K_MSIZE 0x00004000 +#define CYDEV_DMA_SRAM32K_MBASE 0x2000c000 +#define CYDEV_DMA_SRAM32K_MSIZE 0x00002000 +#define CYDEV_DMA_SRAM16K_MBASE 0x2000e000 +#define CYDEV_DMA_SRAM16K_MSIZE 0x00001000 +#define CYDEV_DMA_SRAM_MBASE 0x2000f000 +#define CYDEV_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYDEV_CLKDIST_CR 0x40004000 +#define CYDEV_CLKDIST_LD 0x40004001 +#define CYDEV_CLKDIST_WRK0 0x40004002 +#define CYDEV_CLKDIST_WRK1 0x40004003 +#define CYDEV_CLKDIST_MSTR0 0x40004004 +#define CYDEV_CLKDIST_MSTR1 0x40004005 +#define CYDEV_CLKDIST_BCFG0 0x40004006 +#define CYDEV_CLKDIST_BCFG1 0x40004007 +#define CYDEV_CLKDIST_BCFG2 0x40004008 +#define CYDEV_CLKDIST_UCFG 0x40004009 +#define CYDEV_CLKDIST_DLY0 0x4000400a +#define CYDEV_CLKDIST_DLY1 0x4000400b +#define CYDEV_CLKDIST_DMASK 0x40004010 +#define CYDEV_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYDEV_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYDEV_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYDEV_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYDEV_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYDEV_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYDEV_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYDEV_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYDEV_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYDEV_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYDEV_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYDEV_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYDEV_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYDEV_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYDEV_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYDEV_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYDEV_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYDEV_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYDEV_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYDEV_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYDEV_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYDEV_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYDEV_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYDEV_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYDEV_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYDEV_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYDEV_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYDEV_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYDEV_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYDEV_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYDEV_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYDEV_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYDEV_FASTCLK_XMHZ_CSR 0x40004210 +#define CYDEV_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYDEV_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYDEV_FASTCLK_PLL_CFG0 0x40004220 +#define CYDEV_FASTCLK_PLL_CFG1 0x40004221 +#define CYDEV_FASTCLK_PLL_P 0x40004222 +#define CYDEV_FASTCLK_PLL_Q 0x40004223 +#define CYDEV_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYDEV_SLOWCLK_ILO_CR0 0x40004300 +#define CYDEV_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYDEV_SLOWCLK_X32_CR 0x40004308 +#define CYDEV_SLOWCLK_X32_CFG 0x40004309 +#define CYDEV_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYDEV_BOOST_CR0 0x40004320 +#define CYDEV_BOOST_CR1 0x40004321 +#define CYDEV_BOOST_CR2 0x40004322 +#define CYDEV_BOOST_CR3 0x40004323 +#define CYDEV_BOOST_SR 0x40004324 +#define CYDEV_BOOST_CR4 0x40004325 +#define CYDEV_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYDEV_PWRSYS_CR0 0x40004330 +#define CYDEV_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYDEV_PM_TW_CFG0 0x40004380 +#define CYDEV_PM_TW_CFG1 0x40004381 +#define CYDEV_PM_TW_CFG2 0x40004382 +#define CYDEV_PM_WDT_CFG 0x40004383 +#define CYDEV_PM_WDT_CR 0x40004384 +#define CYDEV_PM_INT_SR 0x40004390 +#define CYDEV_PM_MODE_CFG0 0x40004391 +#define CYDEV_PM_MODE_CFG1 0x40004392 +#define CYDEV_PM_MODE_CSR 0x40004393 +#define CYDEV_PM_USB_CR0 0x40004394 +#define CYDEV_PM_WAKEUP_CFG0 0x40004398 +#define CYDEV_PM_WAKEUP_CFG1 0x40004399 +#define CYDEV_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYDEV_PM_ACT_CFG0 0x400043a0 +#define CYDEV_PM_ACT_CFG1 0x400043a1 +#define CYDEV_PM_ACT_CFG2 0x400043a2 +#define CYDEV_PM_ACT_CFG3 0x400043a3 +#define CYDEV_PM_ACT_CFG4 0x400043a4 +#define CYDEV_PM_ACT_CFG5 0x400043a5 +#define CYDEV_PM_ACT_CFG6 0x400043a6 +#define CYDEV_PM_ACT_CFG7 0x400043a7 +#define CYDEV_PM_ACT_CFG8 0x400043a8 +#define CYDEV_PM_ACT_CFG9 0x400043a9 +#define CYDEV_PM_ACT_CFG10 0x400043aa +#define CYDEV_PM_ACT_CFG11 0x400043ab +#define CYDEV_PM_ACT_CFG12 0x400043ac +#define CYDEV_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYDEV_PM_STBY_CFG0 0x400043b0 +#define CYDEV_PM_STBY_CFG1 0x400043b1 +#define CYDEV_PM_STBY_CFG2 0x400043b2 +#define CYDEV_PM_STBY_CFG3 0x400043b3 +#define CYDEV_PM_STBY_CFG4 0x400043b4 +#define CYDEV_PM_STBY_CFG5 0x400043b5 +#define CYDEV_PM_STBY_CFG6 0x400043b6 +#define CYDEV_PM_STBY_CFG7 0x400043b7 +#define CYDEV_PM_STBY_CFG8 0x400043b8 +#define CYDEV_PM_STBY_CFG9 0x400043b9 +#define CYDEV_PM_STBY_CFG10 0x400043ba +#define CYDEV_PM_STBY_CFG11 0x400043bb +#define CYDEV_PM_STBY_CFG12 0x400043bc +#define CYDEV_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYDEV_PM_AVAIL_CR0 0x400043c0 +#define CYDEV_PM_AVAIL_CR1 0x400043c1 +#define CYDEV_PM_AVAIL_CR2 0x400043c2 +#define CYDEV_PM_AVAIL_CR3 0x400043c3 +#define CYDEV_PM_AVAIL_CR4 0x400043c4 +#define CYDEV_PM_AVAIL_CR5 0x400043c5 +#define CYDEV_PM_AVAIL_CR6 0x400043c6 +#define CYDEV_PM_AVAIL_SR0 0x400043d0 +#define CYDEV_PM_AVAIL_SR1 0x400043d1 +#define CYDEV_PM_AVAIL_SR2 0x400043d2 +#define CYDEV_PM_AVAIL_SR3 0x400043d3 +#define CYDEV_PM_AVAIL_SR4 0x400043d4 +#define CYDEV_PM_AVAIL_SR5 0x400043d5 +#define CYDEV_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 0x40004501 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 0x40004502 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 0x40004503 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 0x40004504 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 0x40004505 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 0x40004506 +#define CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 0x40004509 +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 0x4000450a +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 0x4000450b +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 0x4000450c +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 0x4000450d +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 0x4000450e +#define CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 0x40004511 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 0x40004512 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 0x40004513 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 0x40004514 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 0x40004515 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 0x40004516 +#define CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 0x40004519 +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 0x4000451a +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 0x4000451b +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 0x4000451c +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 0x4000451d +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 0x4000451e +#define CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 0x40004521 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 0x40004522 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 0x40004523 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 0x40004524 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 0x40004525 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 0x40004526 +#define CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 0x40004529 +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 0x4000452a +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 0x4000452b +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 0x4000452c +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 0x4000452d +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 0x4000452e +#define CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 0x40004531 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 0x40004532 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 0x40004533 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 0x40004534 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 0x40004535 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 0x40004536 +#define CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 0x40004561 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 0x40004562 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 0x40004563 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 0x40004564 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 0x40004565 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 0x40004566 +#define CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 0x40004579 +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 0x4000457a +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 0x4000457b +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 0x4000457c +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 0x4000457d +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 0x4000457e +#define CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_STAT_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYDEV_PICU_SNAP_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYDEV_MFGCFG_ANAIF_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR0 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR0 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR0 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR0 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYDEV_MFGCFG_PWRSYS_HIB_TR0 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_HIB_TR1 0x40004681 +#define CYDEV_MFGCFG_PWRSYS_I2C_TR 0x40004682 +#define CYDEV_MFGCFG_PWRSYS_SLP_TR 0x40004683 +#define CYDEV_MFGCFG_PWRSYS_BUZZ_TR 0x40004684 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR0 0x40004685 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR1 0x40004686 +#define CYDEV_MFGCFG_PWRSYS_BREF_TR 0x40004687 +#define CYDEV_MFGCFG_PWRSYS_BG_TR 0x40004688 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR2 0x40004689 +#define CYDEV_MFGCFG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYDEV_MFGCFG_ILO_TR0 0x40004690 +#define CYDEV_MFGCFG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYDEV_MFGCFG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYDEV_MFGCFG_IMO_TR0 0x400046a0 +#define CYDEV_MFGCFG_IMO_TR1 0x400046a1 +#define CYDEV_MFGCFG_IMO_GAIN 0x400046a2 +#define CYDEV_MFGCFG_IMO_C36M 0x400046a3 +#define CYDEV_MFGCFG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYDEV_MFGCFG_XMHZ_TR 0x400046a8 +#define CYDEV_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYDEV_MFGCFG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYDEV_MFGCFG_MLOGIC_SEG_CR 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYDEV_MFGCFG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYDEV_RESET_IPOR_CR0 0x400046f0 +#define CYDEV_RESET_IPOR_CR1 0x400046f1 +#define CYDEV_RESET_IPOR_CR2 0x400046f2 +#define CYDEV_RESET_IPOR_CR3 0x400046f3 +#define CYDEV_RESET_CR0 0x400046f4 +#define CYDEV_RESET_CR1 0x400046f5 +#define CYDEV_RESET_CR2 0x400046f6 +#define CYDEV_RESET_CR3 0x400046f7 +#define CYDEV_RESET_CR4 0x400046f8 +#define CYDEV_RESET_CR5 0x400046f9 +#define CYDEV_RESET_SR0 0x400046fa +#define CYDEV_RESET_SR1 0x400046fb +#define CYDEV_RESET_SR2 0x400046fc +#define CYDEV_RESET_SR3 0x400046fd +#define CYDEV_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYDEV_SPC_FM_EE_CR 0x40004700 +#define CYDEV_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYDEV_SPC_EE_SCR 0x40004702 +#define CYDEV_SPC_EE_ERR 0x40004703 +#define CYDEV_SPC_CPU_DATA 0x40004720 +#define CYDEV_SPC_DMA_DATA 0x40004721 +#define CYDEV_SPC_SR 0x40004722 +#define CYDEV_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYDEV_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYDEV_CACHE_CC_CTL 0x40004800 +#define CYDEV_CACHE_ECC_CORR 0x40004880 +#define CYDEV_CACHE_ECC_ERR 0x40004888 +#define CYDEV_CACHE_FLASH_ERR 0x40004890 +#define CYDEV_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYDEV_I2C_XCFG 0x400049c8 +#define CYDEV_I2C_ADR 0x400049ca +#define CYDEV_I2C_CFG 0x400049d6 +#define CYDEV_I2C_CSR 0x400049d7 +#define CYDEV_I2C_D 0x400049d8 +#define CYDEV_I2C_MCSR 0x400049d9 +#define CYDEV_I2C_CLK_DIV1 0x400049db +#define CYDEV_I2C_CLK_DIV2 0x400049dc +#define CYDEV_I2C_TMOUT_CSR 0x400049dd +#define CYDEV_I2C_TMOUT_SR 0x400049de +#define CYDEV_I2C_TMOUT_CFG0 0x400049df +#define CYDEV_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYDEV_DEC_CR 0x40004e00 +#define CYDEV_DEC_SR 0x40004e01 +#define CYDEV_DEC_SHIFT1 0x40004e02 +#define CYDEV_DEC_SHIFT2 0x40004e03 +#define CYDEV_DEC_DR2 0x40004e04 +#define CYDEV_DEC_DR2H 0x40004e05 +#define CYDEV_DEC_DR1 0x40004e06 +#define CYDEV_DEC_OCOR 0x40004e08 +#define CYDEV_DEC_OCORM 0x40004e09 +#define CYDEV_DEC_OCORH 0x40004e0a +#define CYDEV_DEC_GCOR 0x40004e0c +#define CYDEV_DEC_GCORH 0x40004e0d +#define CYDEV_DEC_GVAL 0x40004e0e +#define CYDEV_DEC_OUTSAMP 0x40004e10 +#define CYDEV_DEC_OUTSAMPM 0x40004e11 +#define CYDEV_DEC_OUTSAMPH 0x40004e12 +#define CYDEV_DEC_OUTSAMPS 0x40004e13 +#define CYDEV_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYDEV_TMR0_CFG0 0x40004f00 +#define CYDEV_TMR0_CFG1 0x40004f01 +#define CYDEV_TMR0_CFG2 0x40004f02 +#define CYDEV_TMR0_SR0 0x40004f03 +#define CYDEV_TMR0_PER0 0x40004f04 +#define CYDEV_TMR0_PER1 0x40004f05 +#define CYDEV_TMR0_CNT_CMP0 0x40004f06 +#define CYDEV_TMR0_CNT_CMP1 0x40004f07 +#define CYDEV_TMR0_CAP0 0x40004f08 +#define CYDEV_TMR0_CAP1 0x40004f09 +#define CYDEV_TMR0_RT0 0x40004f0a +#define CYDEV_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYDEV_TMR1_CFG0 0x40004f0c +#define CYDEV_TMR1_CFG1 0x40004f0d +#define CYDEV_TMR1_CFG2 0x40004f0e +#define CYDEV_TMR1_SR0 0x40004f0f +#define CYDEV_TMR1_PER0 0x40004f10 +#define CYDEV_TMR1_PER1 0x40004f11 +#define CYDEV_TMR1_CNT_CMP0 0x40004f12 +#define CYDEV_TMR1_CNT_CMP1 0x40004f13 +#define CYDEV_TMR1_CAP0 0x40004f14 +#define CYDEV_TMR1_CAP1 0x40004f15 +#define CYDEV_TMR1_RT0 0x40004f16 +#define CYDEV_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYDEV_TMR2_CFG0 0x40004f18 +#define CYDEV_TMR2_CFG1 0x40004f19 +#define CYDEV_TMR2_CFG2 0x40004f1a +#define CYDEV_TMR2_SR0 0x40004f1b +#define CYDEV_TMR2_PER0 0x40004f1c +#define CYDEV_TMR2_PER1 0x40004f1d +#define CYDEV_TMR2_CNT_CMP0 0x40004f1e +#define CYDEV_TMR2_CNT_CMP1 0x40004f1f +#define CYDEV_TMR2_CAP0 0x40004f20 +#define CYDEV_TMR2_CAP1 0x40004f21 +#define CYDEV_TMR2_RT0 0x40004f22 +#define CYDEV_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYDEV_TMR3_CFG0 0x40004f24 +#define CYDEV_TMR3_CFG1 0x40004f25 +#define CYDEV_TMR3_CFG2 0x40004f26 +#define CYDEV_TMR3_SR0 0x40004f27 +#define CYDEV_TMR3_PER0 0x40004f28 +#define CYDEV_TMR3_PER1 0x40004f29 +#define CYDEV_TMR3_CNT_CMP0 0x40004f2a +#define CYDEV_TMR3_CNT_CMP1 0x40004f2b +#define CYDEV_TMR3_CAP0 0x40004f2c +#define CYDEV_TMR3_CAP1 0x40004f2d +#define CYDEV_TMR3_RT0 0x40004f2e +#define CYDEV_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT0_PC0 0x40005000 +#define CYDEV_IO_PC_PRT0_PC1 0x40005001 +#define CYDEV_IO_PC_PRT0_PC2 0x40005002 +#define CYDEV_IO_PC_PRT0_PC3 0x40005003 +#define CYDEV_IO_PC_PRT0_PC4 0x40005004 +#define CYDEV_IO_PC_PRT0_PC5 0x40005005 +#define CYDEV_IO_PC_PRT0_PC6 0x40005006 +#define CYDEV_IO_PC_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT1_PC0 0x40005008 +#define CYDEV_IO_PC_PRT1_PC1 0x40005009 +#define CYDEV_IO_PC_PRT1_PC2 0x4000500a +#define CYDEV_IO_PC_PRT1_PC3 0x4000500b +#define CYDEV_IO_PC_PRT1_PC4 0x4000500c +#define CYDEV_IO_PC_PRT1_PC5 0x4000500d +#define CYDEV_IO_PC_PRT1_PC6 0x4000500e +#define CYDEV_IO_PC_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT2_PC0 0x40005010 +#define CYDEV_IO_PC_PRT2_PC1 0x40005011 +#define CYDEV_IO_PC_PRT2_PC2 0x40005012 +#define CYDEV_IO_PC_PRT2_PC3 0x40005013 +#define CYDEV_IO_PC_PRT2_PC4 0x40005014 +#define CYDEV_IO_PC_PRT2_PC5 0x40005015 +#define CYDEV_IO_PC_PRT2_PC6 0x40005016 +#define CYDEV_IO_PC_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT3_PC0 0x40005018 +#define CYDEV_IO_PC_PRT3_PC1 0x40005019 +#define CYDEV_IO_PC_PRT3_PC2 0x4000501a +#define CYDEV_IO_PC_PRT3_PC3 0x4000501b +#define CYDEV_IO_PC_PRT3_PC4 0x4000501c +#define CYDEV_IO_PC_PRT3_PC5 0x4000501d +#define CYDEV_IO_PC_PRT3_PC6 0x4000501e +#define CYDEV_IO_PC_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT4_PC0 0x40005020 +#define CYDEV_IO_PC_PRT4_PC1 0x40005021 +#define CYDEV_IO_PC_PRT4_PC2 0x40005022 +#define CYDEV_IO_PC_PRT4_PC3 0x40005023 +#define CYDEV_IO_PC_PRT4_PC4 0x40005024 +#define CYDEV_IO_PC_PRT4_PC5 0x40005025 +#define CYDEV_IO_PC_PRT4_PC6 0x40005026 +#define CYDEV_IO_PC_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT5_PC0 0x40005028 +#define CYDEV_IO_PC_PRT5_PC1 0x40005029 +#define CYDEV_IO_PC_PRT5_PC2 0x4000502a +#define CYDEV_IO_PC_PRT5_PC3 0x4000502b +#define CYDEV_IO_PC_PRT5_PC4 0x4000502c +#define CYDEV_IO_PC_PRT5_PC5 0x4000502d +#define CYDEV_IO_PC_PRT5_PC6 0x4000502e +#define CYDEV_IO_PC_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT6_PC0 0x40005030 +#define CYDEV_IO_PC_PRT6_PC1 0x40005031 +#define CYDEV_IO_PC_PRT6_PC2 0x40005032 +#define CYDEV_IO_PC_PRT6_PC3 0x40005033 +#define CYDEV_IO_PC_PRT6_PC4 0x40005034 +#define CYDEV_IO_PC_PRT6_PC5 0x40005035 +#define CYDEV_IO_PC_PRT6_PC6 0x40005036 +#define CYDEV_IO_PC_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYDEV_IO_PC_PRT12_PC0 0x40005060 +#define CYDEV_IO_PC_PRT12_PC1 0x40005061 +#define CYDEV_IO_PC_PRT12_PC2 0x40005062 +#define CYDEV_IO_PC_PRT12_PC3 0x40005063 +#define CYDEV_IO_PC_PRT12_PC4 0x40005064 +#define CYDEV_IO_PC_PRT12_PC5 0x40005065 +#define CYDEV_IO_PC_PRT12_PC6 0x40005066 +#define CYDEV_IO_PC_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYDEV_IO_PC_PRT15_PC0 0x40005078 +#define CYDEV_IO_PC_PRT15_PC1 0x40005079 +#define CYDEV_IO_PC_PRT15_PC2 0x4000507a +#define CYDEV_IO_PC_PRT15_PC3 0x4000507b +#define CYDEV_IO_PC_PRT15_PC4 0x4000507c +#define CYDEV_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYDEV_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYDEV_IO_DR_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYDEV_IO_PS_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT0_DR 0x40005100 +#define CYDEV_IO_PRT_PRT0_PS 0x40005101 +#define CYDEV_IO_PRT_PRT0_DM0 0x40005102 +#define CYDEV_IO_PRT_PRT0_DM1 0x40005103 +#define CYDEV_IO_PRT_PRT0_DM2 0x40005104 +#define CYDEV_IO_PRT_PRT0_SLW 0x40005105 +#define CYDEV_IO_PRT_PRT0_BYP 0x40005106 +#define CYDEV_IO_PRT_PRT0_BIE 0x40005107 +#define CYDEV_IO_PRT_PRT0_INP_DIS 0x40005108 +#define CYDEV_IO_PRT_PRT0_CTL 0x40005109 +#define CYDEV_IO_PRT_PRT0_PRT 0x4000510a +#define CYDEV_IO_PRT_PRT0_BIT_MASK 0x4000510b +#define CYDEV_IO_PRT_PRT0_AMUX 0x4000510c +#define CYDEV_IO_PRT_PRT0_AG 0x4000510d +#define CYDEV_IO_PRT_PRT0_LCD_COM_SEG 0x4000510e +#define CYDEV_IO_PRT_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT1_DR 0x40005110 +#define CYDEV_IO_PRT_PRT1_PS 0x40005111 +#define CYDEV_IO_PRT_PRT1_DM0 0x40005112 +#define CYDEV_IO_PRT_PRT1_DM1 0x40005113 +#define CYDEV_IO_PRT_PRT1_DM2 0x40005114 +#define CYDEV_IO_PRT_PRT1_SLW 0x40005115 +#define CYDEV_IO_PRT_PRT1_BYP 0x40005116 +#define CYDEV_IO_PRT_PRT1_BIE 0x40005117 +#define CYDEV_IO_PRT_PRT1_INP_DIS 0x40005118 +#define CYDEV_IO_PRT_PRT1_CTL 0x40005119 +#define CYDEV_IO_PRT_PRT1_PRT 0x4000511a +#define CYDEV_IO_PRT_PRT1_BIT_MASK 0x4000511b +#define CYDEV_IO_PRT_PRT1_AMUX 0x4000511c +#define CYDEV_IO_PRT_PRT1_AG 0x4000511d +#define CYDEV_IO_PRT_PRT1_LCD_COM_SEG 0x4000511e +#define CYDEV_IO_PRT_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT2_DR 0x40005120 +#define CYDEV_IO_PRT_PRT2_PS 0x40005121 +#define CYDEV_IO_PRT_PRT2_DM0 0x40005122 +#define CYDEV_IO_PRT_PRT2_DM1 0x40005123 +#define CYDEV_IO_PRT_PRT2_DM2 0x40005124 +#define CYDEV_IO_PRT_PRT2_SLW 0x40005125 +#define CYDEV_IO_PRT_PRT2_BYP 0x40005126 +#define CYDEV_IO_PRT_PRT2_BIE 0x40005127 +#define CYDEV_IO_PRT_PRT2_INP_DIS 0x40005128 +#define CYDEV_IO_PRT_PRT2_CTL 0x40005129 +#define CYDEV_IO_PRT_PRT2_PRT 0x4000512a +#define CYDEV_IO_PRT_PRT2_BIT_MASK 0x4000512b +#define CYDEV_IO_PRT_PRT2_AMUX 0x4000512c +#define CYDEV_IO_PRT_PRT2_AG 0x4000512d +#define CYDEV_IO_PRT_PRT2_LCD_COM_SEG 0x4000512e +#define CYDEV_IO_PRT_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT3_DR 0x40005130 +#define CYDEV_IO_PRT_PRT3_PS 0x40005131 +#define CYDEV_IO_PRT_PRT3_DM0 0x40005132 +#define CYDEV_IO_PRT_PRT3_DM1 0x40005133 +#define CYDEV_IO_PRT_PRT3_DM2 0x40005134 +#define CYDEV_IO_PRT_PRT3_SLW 0x40005135 +#define CYDEV_IO_PRT_PRT3_BYP 0x40005136 +#define CYDEV_IO_PRT_PRT3_BIE 0x40005137 +#define CYDEV_IO_PRT_PRT3_INP_DIS 0x40005138 +#define CYDEV_IO_PRT_PRT3_CTL 0x40005139 +#define CYDEV_IO_PRT_PRT3_PRT 0x4000513a +#define CYDEV_IO_PRT_PRT3_BIT_MASK 0x4000513b +#define CYDEV_IO_PRT_PRT3_AMUX 0x4000513c +#define CYDEV_IO_PRT_PRT3_AG 0x4000513d +#define CYDEV_IO_PRT_PRT3_LCD_COM_SEG 0x4000513e +#define CYDEV_IO_PRT_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT4_DR 0x40005140 +#define CYDEV_IO_PRT_PRT4_PS 0x40005141 +#define CYDEV_IO_PRT_PRT4_DM0 0x40005142 +#define CYDEV_IO_PRT_PRT4_DM1 0x40005143 +#define CYDEV_IO_PRT_PRT4_DM2 0x40005144 +#define CYDEV_IO_PRT_PRT4_SLW 0x40005145 +#define CYDEV_IO_PRT_PRT4_BYP 0x40005146 +#define CYDEV_IO_PRT_PRT4_BIE 0x40005147 +#define CYDEV_IO_PRT_PRT4_INP_DIS 0x40005148 +#define CYDEV_IO_PRT_PRT4_CTL 0x40005149 +#define CYDEV_IO_PRT_PRT4_PRT 0x4000514a +#define CYDEV_IO_PRT_PRT4_BIT_MASK 0x4000514b +#define CYDEV_IO_PRT_PRT4_AMUX 0x4000514c +#define CYDEV_IO_PRT_PRT4_AG 0x4000514d +#define CYDEV_IO_PRT_PRT4_LCD_COM_SEG 0x4000514e +#define CYDEV_IO_PRT_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT5_DR 0x40005150 +#define CYDEV_IO_PRT_PRT5_PS 0x40005151 +#define CYDEV_IO_PRT_PRT5_DM0 0x40005152 +#define CYDEV_IO_PRT_PRT5_DM1 0x40005153 +#define CYDEV_IO_PRT_PRT5_DM2 0x40005154 +#define CYDEV_IO_PRT_PRT5_SLW 0x40005155 +#define CYDEV_IO_PRT_PRT5_BYP 0x40005156 +#define CYDEV_IO_PRT_PRT5_BIE 0x40005157 +#define CYDEV_IO_PRT_PRT5_INP_DIS 0x40005158 +#define CYDEV_IO_PRT_PRT5_CTL 0x40005159 +#define CYDEV_IO_PRT_PRT5_PRT 0x4000515a +#define CYDEV_IO_PRT_PRT5_BIT_MASK 0x4000515b +#define CYDEV_IO_PRT_PRT5_AMUX 0x4000515c +#define CYDEV_IO_PRT_PRT5_AG 0x4000515d +#define CYDEV_IO_PRT_PRT5_LCD_COM_SEG 0x4000515e +#define CYDEV_IO_PRT_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT6_DR 0x40005160 +#define CYDEV_IO_PRT_PRT6_PS 0x40005161 +#define CYDEV_IO_PRT_PRT6_DM0 0x40005162 +#define CYDEV_IO_PRT_PRT6_DM1 0x40005163 +#define CYDEV_IO_PRT_PRT6_DM2 0x40005164 +#define CYDEV_IO_PRT_PRT6_SLW 0x40005165 +#define CYDEV_IO_PRT_PRT6_BYP 0x40005166 +#define CYDEV_IO_PRT_PRT6_BIE 0x40005167 +#define CYDEV_IO_PRT_PRT6_INP_DIS 0x40005168 +#define CYDEV_IO_PRT_PRT6_CTL 0x40005169 +#define CYDEV_IO_PRT_PRT6_PRT 0x4000516a +#define CYDEV_IO_PRT_PRT6_BIT_MASK 0x4000516b +#define CYDEV_IO_PRT_PRT6_AMUX 0x4000516c +#define CYDEV_IO_PRT_PRT6_AG 0x4000516d +#define CYDEV_IO_PRT_PRT6_LCD_COM_SEG 0x4000516e +#define CYDEV_IO_PRT_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT12_DR 0x400051c0 +#define CYDEV_IO_PRT_PRT12_PS 0x400051c1 +#define CYDEV_IO_PRT_PRT12_DM0 0x400051c2 +#define CYDEV_IO_PRT_PRT12_DM1 0x400051c3 +#define CYDEV_IO_PRT_PRT12_DM2 0x400051c4 +#define CYDEV_IO_PRT_PRT12_SLW 0x400051c5 +#define CYDEV_IO_PRT_PRT12_BYP 0x400051c6 +#define CYDEV_IO_PRT_PRT12_BIE 0x400051c7 +#define CYDEV_IO_PRT_PRT12_INP_DIS 0x400051c8 +#define CYDEV_IO_PRT_PRT12_SIO_HYST_EN 0x400051c9 +#define CYDEV_IO_PRT_PRT12_PRT 0x400051ca +#define CYDEV_IO_PRT_PRT12_BIT_MASK 0x400051cb +#define CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYDEV_IO_PRT_PRT12_AG 0x400051cd +#define CYDEV_IO_PRT_PRT12_SIO_CFG 0x400051ce +#define CYDEV_IO_PRT_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYDEV_IO_PRT_PRT15_DR 0x400051f0 +#define CYDEV_IO_PRT_PRT15_PS 0x400051f1 +#define CYDEV_IO_PRT_PRT15_DM0 0x400051f2 +#define CYDEV_IO_PRT_PRT15_DM1 0x400051f3 +#define CYDEV_IO_PRT_PRT15_DM2 0x400051f4 +#define CYDEV_IO_PRT_PRT15_SLW 0x400051f5 +#define CYDEV_IO_PRT_PRT15_BYP 0x400051f6 +#define CYDEV_IO_PRT_PRT15_BIE 0x400051f7 +#define CYDEV_IO_PRT_PRT15_INP_DIS 0x400051f8 +#define CYDEV_IO_PRT_PRT15_CTL 0x400051f9 +#define CYDEV_IO_PRT_PRT15_PRT 0x400051fa +#define CYDEV_IO_PRT_PRT15_BIT_MASK 0x400051fb +#define CYDEV_IO_PRT_PRT15_AMUX 0x400051fc +#define CYDEV_IO_PRT_PRT15_AG 0x400051fd +#define CYDEV_IO_PRT_PRT15_LCD_COM_SEG 0x400051fe +#define CYDEV_IO_PRT_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT0_OUT_SEL0 0x40005200 +#define CYDEV_PRTDSI_PRT0_OUT_SEL1 0x40005201 +#define CYDEV_PRTDSI_PRT0_OE_SEL0 0x40005202 +#define CYDEV_PRTDSI_PRT0_OE_SEL1 0x40005203 +#define CYDEV_PRTDSI_PRT0_DBL_SYNC_IN 0x40005204 +#define CYDEV_PRTDSI_PRT0_SYNC_OUT 0x40005205 +#define CYDEV_PRTDSI_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT1_OUT_SEL0 0x40005208 +#define CYDEV_PRTDSI_PRT1_OUT_SEL1 0x40005209 +#define CYDEV_PRTDSI_PRT1_OE_SEL0 0x4000520a +#define CYDEV_PRTDSI_PRT1_OE_SEL1 0x4000520b +#define CYDEV_PRTDSI_PRT1_DBL_SYNC_IN 0x4000520c +#define CYDEV_PRTDSI_PRT1_SYNC_OUT 0x4000520d +#define CYDEV_PRTDSI_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT2_OUT_SEL0 0x40005210 +#define CYDEV_PRTDSI_PRT2_OUT_SEL1 0x40005211 +#define CYDEV_PRTDSI_PRT2_OE_SEL0 0x40005212 +#define CYDEV_PRTDSI_PRT2_OE_SEL1 0x40005213 +#define CYDEV_PRTDSI_PRT2_DBL_SYNC_IN 0x40005214 +#define CYDEV_PRTDSI_PRT2_SYNC_OUT 0x40005215 +#define CYDEV_PRTDSI_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT3_OUT_SEL0 0x40005218 +#define CYDEV_PRTDSI_PRT3_OUT_SEL1 0x40005219 +#define CYDEV_PRTDSI_PRT3_OE_SEL0 0x4000521a +#define CYDEV_PRTDSI_PRT3_OE_SEL1 0x4000521b +#define CYDEV_PRTDSI_PRT3_DBL_SYNC_IN 0x4000521c +#define CYDEV_PRTDSI_PRT3_SYNC_OUT 0x4000521d +#define CYDEV_PRTDSI_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT4_OUT_SEL0 0x40005220 +#define CYDEV_PRTDSI_PRT4_OUT_SEL1 0x40005221 +#define CYDEV_PRTDSI_PRT4_OE_SEL0 0x40005222 +#define CYDEV_PRTDSI_PRT4_OE_SEL1 0x40005223 +#define CYDEV_PRTDSI_PRT4_DBL_SYNC_IN 0x40005224 +#define CYDEV_PRTDSI_PRT4_SYNC_OUT 0x40005225 +#define CYDEV_PRTDSI_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT5_OUT_SEL0 0x40005228 +#define CYDEV_PRTDSI_PRT5_OUT_SEL1 0x40005229 +#define CYDEV_PRTDSI_PRT5_OE_SEL0 0x4000522a +#define CYDEV_PRTDSI_PRT5_OE_SEL1 0x4000522b +#define CYDEV_PRTDSI_PRT5_DBL_SYNC_IN 0x4000522c +#define CYDEV_PRTDSI_PRT5_SYNC_OUT 0x4000522d +#define CYDEV_PRTDSI_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT6_OUT_SEL0 0x40005230 +#define CYDEV_PRTDSI_PRT6_OUT_SEL1 0x40005231 +#define CYDEV_PRTDSI_PRT6_OE_SEL0 0x40005232 +#define CYDEV_PRTDSI_PRT6_OE_SEL1 0x40005233 +#define CYDEV_PRTDSI_PRT6_DBL_SYNC_IN 0x40005234 +#define CYDEV_PRTDSI_PRT6_SYNC_OUT 0x40005235 +#define CYDEV_PRTDSI_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYDEV_PRTDSI_PRT12_OUT_SEL0 0x40005260 +#define CYDEV_PRTDSI_PRT12_OUT_SEL1 0x40005261 +#define CYDEV_PRTDSI_PRT12_OE_SEL0 0x40005262 +#define CYDEV_PRTDSI_PRT12_OE_SEL1 0x40005263 +#define CYDEV_PRTDSI_PRT12_DBL_SYNC_IN 0x40005264 +#define CYDEV_PRTDSI_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYDEV_PRTDSI_PRT15_OUT_SEL0 0x40005278 +#define CYDEV_PRTDSI_PRT15_OUT_SEL1 0x40005279 +#define CYDEV_PRTDSI_PRT15_OE_SEL0 0x4000527a +#define CYDEV_PRTDSI_PRT15_OE_SEL1 0x4000527b +#define CYDEV_PRTDSI_PRT15_DBL_SYNC_IN 0x4000527c +#define CYDEV_PRTDSI_PRT15_SYNC_OUT 0x4000527d +#define CYDEV_PRTDSI_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYDEV_EMIF_NO_UDB 0x40005400 +#define CYDEV_EMIF_RP_WAIT_STATES 0x40005401 +#define CYDEV_EMIF_MEM_DWN 0x40005402 +#define CYDEV_EMIF_MEMCLK_DIV 0x40005403 +#define CYDEV_EMIF_CLOCK_EN 0x40005404 +#define CYDEV_EMIF_EM_TYPE 0x40005405 +#define CYDEV_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC0_CR0 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_CR1 0x40005801 +#define CYDEV_ANAIF_CFG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC1_CR0 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_CR1 0x40005805 +#define CYDEV_ANAIF_CFG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC2_CR0 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_CR1 0x40005809 +#define CYDEV_ANAIF_CFG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_SC3_CR0 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_CR1 0x4000580d +#define CYDEV_ANAIF_CFG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC0_CR0 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_CR1 0x40005821 +#define CYDEV_ANAIF_CFG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC1_CR0 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_CR1 0x40005825 +#define CYDEV_ANAIF_CFG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC2_CR0 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_CR1 0x40005829 +#define CYDEV_ANAIF_CFG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYDEV_ANAIF_CFG_DAC3_CR0 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_CR1 0x4000582d +#define CYDEV_ANAIF_CFG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT0_CR 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT1_CR 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT2_CR 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LUT3_CR 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP0_CR 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP1_CR 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP2_CR 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_OPAMP3_CR 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LCDDAC_CR0 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYDEV_ANAIF_CFG_BG_CR0 0x4000586c +#define CYDEV_ANAIF_CFG_BG_RSVD 0x4000586d +#define CYDEV_ANAIF_CFG_BG_DFT0 0x4000586e +#define CYDEV_ANAIF_CFG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSL_CFG0 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_CAPSR_CFG0 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_PUMP_CR0 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF0_CR0 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYDEV_ANAIF_CFG_LPF1_CR0 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYDEV_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYDEV_ANAIF_CFG_DSM0_CR0 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_CR1 0x40005881 +#define CYDEV_ANAIF_CFG_DSM0_CR2 0x40005882 +#define CYDEV_ANAIF_CFG_DSM0_CR3 0x40005883 +#define CYDEV_ANAIF_CFG_DSM0_CR4 0x40005884 +#define CYDEV_ANAIF_CFG_DSM0_CR5 0x40005885 +#define CYDEV_ANAIF_CFG_DSM0_CR6 0x40005886 +#define CYDEV_ANAIF_CFG_DSM0_CR7 0x40005887 +#define CYDEV_ANAIF_CFG_DSM0_CR8 0x40005888 +#define CYDEV_ANAIF_CFG_DSM0_CR9 0x40005889 +#define CYDEV_ANAIF_CFG_DSM0_CR10 0x4000588a +#define CYDEV_ANAIF_CFG_DSM0_CR11 0x4000588b +#define CYDEV_ANAIF_CFG_DSM0_CR12 0x4000588c +#define CYDEV_ANAIF_CFG_DSM0_CR13 0x4000588d +#define CYDEV_ANAIF_CFG_DSM0_CR14 0x4000588e +#define CYDEV_ANAIF_CFG_DSM0_CR15 0x4000588f +#define CYDEV_ANAIF_CFG_DSM0_CR16 0x40005890 +#define CYDEV_ANAIF_CFG_DSM0_CR17 0x40005891 +#define CYDEV_ANAIF_CFG_DSM0_REF0 0x40005892 +#define CYDEV_ANAIF_CFG_DSM0_REF1 0x40005893 +#define CYDEV_ANAIF_CFG_DSM0_REF2 0x40005894 +#define CYDEV_ANAIF_CFG_DSM0_REF3 0x40005895 +#define CYDEV_ANAIF_CFG_DSM0_DEM0 0x40005896 +#define CYDEV_ANAIF_CFG_DSM0_DEM1 0x40005897 +#define CYDEV_ANAIF_CFG_DSM0_TST0 0x40005898 +#define CYDEV_ANAIF_CFG_DSM0_TST1 0x40005899 +#define CYDEV_ANAIF_CFG_DSM0_BUF0 0x4000589a +#define CYDEV_ANAIF_CFG_DSM0_BUF1 0x4000589b +#define CYDEV_ANAIF_CFG_DSM0_BUF2 0x4000589c +#define CYDEV_ANAIF_CFG_DSM0_BUF3 0x4000589d +#define CYDEV_ANAIF_CFG_DSM0_MISC 0x4000589e +#define CYDEV_ANAIF_CFG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR0_CSR0 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_CSR1 0x40005901 +#define CYDEV_ANAIF_CFG_SAR0_CSR2 0x40005902 +#define CYDEV_ANAIF_CFG_SAR0_CSR3 0x40005903 +#define CYDEV_ANAIF_CFG_SAR0_CSR4 0x40005904 +#define CYDEV_ANAIF_CFG_SAR0_CSR5 0x40005905 +#define CYDEV_ANAIF_CFG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYDEV_ANAIF_CFG_SAR1_CSR0 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_CSR1 0x40005909 +#define CYDEV_ANAIF_CFG_SAR1_CSR2 0x4000590a +#define CYDEV_ANAIF_CFG_SAR1_CSR3 0x4000590b +#define CYDEV_ANAIF_CFG_SAR1_CSR4 0x4000590c +#define CYDEV_ANAIF_CFG_SAR1_CSR5 0x4000590d +#define CYDEV_ANAIF_CFG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC0_SW0 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SW2 0x40005a02 +#define CYDEV_ANAIF_RT_SC0_SW3 0x40005a03 +#define CYDEV_ANAIF_RT_SC0_SW4 0x40005a04 +#define CYDEV_ANAIF_RT_SC0_SW6 0x40005a06 +#define CYDEV_ANAIF_RT_SC0_SW7 0x40005a07 +#define CYDEV_ANAIF_RT_SC0_SW8 0x40005a08 +#define CYDEV_ANAIF_RT_SC0_SW10 0x40005a0a +#define CYDEV_ANAIF_RT_SC0_CLK 0x40005a0b +#define CYDEV_ANAIF_RT_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC1_SW0 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SW2 0x40005a12 +#define CYDEV_ANAIF_RT_SC1_SW3 0x40005a13 +#define CYDEV_ANAIF_RT_SC1_SW4 0x40005a14 +#define CYDEV_ANAIF_RT_SC1_SW6 0x40005a16 +#define CYDEV_ANAIF_RT_SC1_SW7 0x40005a17 +#define CYDEV_ANAIF_RT_SC1_SW8 0x40005a18 +#define CYDEV_ANAIF_RT_SC1_SW10 0x40005a1a +#define CYDEV_ANAIF_RT_SC1_CLK 0x40005a1b +#define CYDEV_ANAIF_RT_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC2_SW0 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SW2 0x40005a22 +#define CYDEV_ANAIF_RT_SC2_SW3 0x40005a23 +#define CYDEV_ANAIF_RT_SC2_SW4 0x40005a24 +#define CYDEV_ANAIF_RT_SC2_SW6 0x40005a26 +#define CYDEV_ANAIF_RT_SC2_SW7 0x40005a27 +#define CYDEV_ANAIF_RT_SC2_SW8 0x40005a28 +#define CYDEV_ANAIF_RT_SC2_SW10 0x40005a2a +#define CYDEV_ANAIF_RT_SC2_CLK 0x40005a2b +#define CYDEV_ANAIF_RT_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYDEV_ANAIF_RT_SC3_SW0 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SW2 0x40005a32 +#define CYDEV_ANAIF_RT_SC3_SW3 0x40005a33 +#define CYDEV_ANAIF_RT_SC3_SW4 0x40005a34 +#define CYDEV_ANAIF_RT_SC3_SW6 0x40005a36 +#define CYDEV_ANAIF_RT_SC3_SW7 0x40005a37 +#define CYDEV_ANAIF_RT_SC3_SW8 0x40005a38 +#define CYDEV_ANAIF_RT_SC3_SW10 0x40005a3a +#define CYDEV_ANAIF_RT_SC3_CLK 0x40005a3b +#define CYDEV_ANAIF_RT_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC0_SW0 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SW2 0x40005a82 +#define CYDEV_ANAIF_RT_DAC0_SW3 0x40005a83 +#define CYDEV_ANAIF_RT_DAC0_SW4 0x40005a84 +#define CYDEV_ANAIF_RT_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC1_SW0 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SW2 0x40005a8a +#define CYDEV_ANAIF_RT_DAC1_SW3 0x40005a8b +#define CYDEV_ANAIF_RT_DAC1_SW4 0x40005a8c +#define CYDEV_ANAIF_RT_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC2_SW0 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SW2 0x40005a92 +#define CYDEV_ANAIF_RT_DAC2_SW3 0x40005a93 +#define CYDEV_ANAIF_RT_DAC2_SW4 0x40005a94 +#define CYDEV_ANAIF_RT_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DAC3_SW0 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SW2 0x40005a9a +#define CYDEV_ANAIF_RT_DAC3_SW3 0x40005a9b +#define CYDEV_ANAIF_RT_DAC3_SW4 0x40005a9c +#define CYDEV_ANAIF_RT_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP0_SW0 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SW2 0x40005ac2 +#define CYDEV_ANAIF_RT_CMP0_SW3 0x40005ac3 +#define CYDEV_ANAIF_RT_CMP0_SW4 0x40005ac4 +#define CYDEV_ANAIF_RT_CMP0_SW6 0x40005ac6 +#define CYDEV_ANAIF_RT_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP1_SW0 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SW2 0x40005aca +#define CYDEV_ANAIF_RT_CMP1_SW3 0x40005acb +#define CYDEV_ANAIF_RT_CMP1_SW4 0x40005acc +#define CYDEV_ANAIF_RT_CMP1_SW6 0x40005ace +#define CYDEV_ANAIF_RT_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP2_SW0 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SW2 0x40005ad2 +#define CYDEV_ANAIF_RT_CMP2_SW3 0x40005ad3 +#define CYDEV_ANAIF_RT_CMP2_SW4 0x40005ad4 +#define CYDEV_ANAIF_RT_CMP2_SW6 0x40005ad6 +#define CYDEV_ANAIF_RT_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_CMP3_SW0 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SW2 0x40005ada +#define CYDEV_ANAIF_RT_CMP3_SW3 0x40005adb +#define CYDEV_ANAIF_RT_CMP3_SW4 0x40005adc +#define CYDEV_ANAIF_RT_CMP3_SW6 0x40005ade +#define CYDEV_ANAIF_RT_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_DSM0_SW0 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SW2 0x40005b02 +#define CYDEV_ANAIF_RT_DSM0_SW3 0x40005b03 +#define CYDEV_ANAIF_RT_DSM0_SW4 0x40005b04 +#define CYDEV_ANAIF_RT_DSM0_SW6 0x40005b06 +#define CYDEV_ANAIF_RT_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR0_SW0 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SW2 0x40005b22 +#define CYDEV_ANAIF_RT_SAR0_SW3 0x40005b23 +#define CYDEV_ANAIF_RT_SAR0_SW4 0x40005b24 +#define CYDEV_ANAIF_RT_SAR0_SW6 0x40005b26 +#define CYDEV_ANAIF_RT_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYDEV_ANAIF_RT_SAR1_SW0 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SW2 0x40005b2a +#define CYDEV_ANAIF_RT_SAR1_SW3 0x40005b2b +#define CYDEV_ANAIF_RT_SAR1_SW4 0x40005b2c +#define CYDEV_ANAIF_RT_SAR1_SW6 0x40005b2e +#define CYDEV_ANAIF_RT_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP0_MX 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP1_MX 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP2_MX 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYDEV_ANAIF_RT_OPAMP3_MX 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYDEV_ANAIF_RT_LCDDAC_SW0 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SW1 0x40005b51 +#define CYDEV_ANAIF_RT_LCDDAC_SW2 0x40005b52 +#define CYDEV_ANAIF_RT_LCDDAC_SW3 0x40005b53 +#define CYDEV_ANAIF_RT_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYDEV_ANAIF_RT_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYDEV_ANAIF_RT_BUS_SW0 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SW2 0x40005b5a +#define CYDEV_ANAIF_RT_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYDEV_ANAIF_RT_DFT_CR0 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_CR1 0x40005b5d +#define CYDEV_ANAIF_RT_DFT_CR2 0x40005b5e +#define CYDEV_ANAIF_RT_DFT_CR3 0x40005b5f +#define CYDEV_ANAIF_RT_DFT_CR4 0x40005b60 +#define CYDEV_ANAIF_RT_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_DSM0_OUT0 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_LUT_SR 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_WRK1 0x40005b91 +#define CYDEV_ANAIF_WRK_LUT_MSK 0x40005b92 +#define CYDEV_ANAIF_WRK_LUT_CLK 0x40005b93 +#define CYDEV_ANAIF_WRK_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_CMP_WRK 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYDEV_ANAIF_WRK_SC_SR 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_WRK1 0x40005b99 +#define CYDEV_ANAIF_WRK_SC_MSK 0x40005b9a +#define CYDEV_ANAIF_WRK_SC_CMPINV 0x40005b9b +#define CYDEV_ANAIF_WRK_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR0_WRK0 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYDEV_ANAIF_WRK_SAR1_WRK0 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYDEV_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYDEV_USB_EP0_DR0 0x40006000 +#define CYDEV_USB_EP0_DR1 0x40006001 +#define CYDEV_USB_EP0_DR2 0x40006002 +#define CYDEV_USB_EP0_DR3 0x40006003 +#define CYDEV_USB_EP0_DR4 0x40006004 +#define CYDEV_USB_EP0_DR5 0x40006005 +#define CYDEV_USB_EP0_DR6 0x40006006 +#define CYDEV_USB_EP0_DR7 0x40006007 +#define CYDEV_USB_CR0 0x40006008 +#define CYDEV_USB_CR1 0x40006009 +#define CYDEV_USB_SIE_EP_INT_EN 0x4000600a +#define CYDEV_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP1_CNT0 0x4000600c +#define CYDEV_USB_SIE_EP1_CNT1 0x4000600d +#define CYDEV_USB_SIE_EP1_CR0 0x4000600e +#define CYDEV_USB_USBIO_CR0 0x40006010 +#define CYDEV_USB_USBIO_CR1 0x40006012 +#define CYDEV_USB_DYN_RECONFIG 0x40006014 +#define CYDEV_USB_SOF0 0x40006018 +#define CYDEV_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP2_CNT0 0x4000601c +#define CYDEV_USB_SIE_EP2_CNT1 0x4000601d +#define CYDEV_USB_SIE_EP2_CR0 0x4000601e +#define CYDEV_USB_EP0_CR 0x40006028 +#define CYDEV_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP3_CNT0 0x4000602c +#define CYDEV_USB_SIE_EP3_CNT1 0x4000602d +#define CYDEV_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP4_CNT0 0x4000603c +#define CYDEV_USB_SIE_EP4_CNT1 0x4000603d +#define CYDEV_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP5_CNT0 0x4000604c +#define CYDEV_USB_SIE_EP5_CNT1 0x4000604d +#define CYDEV_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP6_CNT0 0x4000605c +#define CYDEV_USB_SIE_EP6_CNT1 0x4000605d +#define CYDEV_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP7_CNT0 0x4000606c +#define CYDEV_USB_SIE_EP7_CNT1 0x4000606d +#define CYDEV_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYDEV_USB_SIE_EP8_CNT0 0x4000607c +#define CYDEV_USB_SIE_EP8_CNT1 0x4000607d +#define CYDEV_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP1_CFG 0x40006080 +#define CYDEV_USB_ARB_EP1_INT_EN 0x40006081 +#define CYDEV_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW1_WA 0x40006084 +#define CYDEV_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYDEV_USB_ARB_RW1_RA 0x40006086 +#define CYDEV_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYDEV_USB_ARB_RW1_DR 0x40006088 +#define CYDEV_USB_BUF_SIZE 0x4000608c +#define CYDEV_USB_EP_ACTIVE 0x4000608e +#define CYDEV_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP2_CFG 0x40006090 +#define CYDEV_USB_ARB_EP2_INT_EN 0x40006091 +#define CYDEV_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW2_WA 0x40006094 +#define CYDEV_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYDEV_USB_ARB_RW2_RA 0x40006096 +#define CYDEV_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYDEV_USB_ARB_RW2_DR 0x40006098 +#define CYDEV_USB_ARB_CFG 0x4000609c +#define CYDEV_USB_USB_CLK_EN 0x4000609d +#define CYDEV_USB_ARB_INT_EN 0x4000609e +#define CYDEV_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP3_CFG 0x400060a0 +#define CYDEV_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYDEV_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW3_WA 0x400060a4 +#define CYDEV_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYDEV_USB_ARB_RW3_RA 0x400060a6 +#define CYDEV_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYDEV_USB_ARB_RW3_DR 0x400060a8 +#define CYDEV_USB_CWA 0x400060ac +#define CYDEV_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP4_CFG 0x400060b0 +#define CYDEV_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYDEV_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW4_WA 0x400060b4 +#define CYDEV_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYDEV_USB_ARB_RW4_RA 0x400060b6 +#define CYDEV_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYDEV_USB_ARB_RW4_DR 0x400060b8 +#define CYDEV_USB_DMA_THRES 0x400060bc +#define CYDEV_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP5_CFG 0x400060c0 +#define CYDEV_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYDEV_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW5_WA 0x400060c4 +#define CYDEV_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYDEV_USB_ARB_RW5_RA 0x400060c6 +#define CYDEV_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYDEV_USB_ARB_RW5_DR 0x400060c8 +#define CYDEV_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP6_CFG 0x400060d0 +#define CYDEV_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYDEV_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW6_WA 0x400060d4 +#define CYDEV_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYDEV_USB_ARB_RW6_RA 0x400060d6 +#define CYDEV_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYDEV_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP7_CFG 0x400060e0 +#define CYDEV_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYDEV_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW7_WA 0x400060e4 +#define CYDEV_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYDEV_USB_ARB_RW7_RA 0x400060e6 +#define CYDEV_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYDEV_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYDEV_USB_ARB_EP8_CFG 0x400060f0 +#define CYDEV_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYDEV_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYDEV_USB_ARB_RW8_WA 0x400060f4 +#define CYDEV_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYDEV_USB_ARB_RW8_RA 0x400060f6 +#define CYDEV_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYDEV_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYDEV_USB_MEM_DATA_MBASE 0x40006100 +#define CYDEV_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B0_UDB00_A0 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A0 0x40006401 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A0 0x40006402 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A0 0x40006403 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A0 0x40006404 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A0 0x40006405 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A0 0x40006406 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A0 0x40006407 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A0 0x40006408 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A0 0x40006409 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A0 0x4000640a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A0 0x4000640b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A0 0x4000640c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A0 0x4000640d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A0 0x4000640e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A0 0x4000640f +#define CYDEV_UWRK_UWRK8_B0_UDB00_A1 0x40006410 +#define CYDEV_UWRK_UWRK8_B0_UDB01_A1 0x40006411 +#define CYDEV_UWRK_UWRK8_B0_UDB02_A1 0x40006412 +#define CYDEV_UWRK_UWRK8_B0_UDB03_A1 0x40006413 +#define CYDEV_UWRK_UWRK8_B0_UDB04_A1 0x40006414 +#define CYDEV_UWRK_UWRK8_B0_UDB05_A1 0x40006415 +#define CYDEV_UWRK_UWRK8_B0_UDB06_A1 0x40006416 +#define CYDEV_UWRK_UWRK8_B0_UDB07_A1 0x40006417 +#define CYDEV_UWRK_UWRK8_B0_UDB08_A1 0x40006418 +#define CYDEV_UWRK_UWRK8_B0_UDB09_A1 0x40006419 +#define CYDEV_UWRK_UWRK8_B0_UDB10_A1 0x4000641a +#define CYDEV_UWRK_UWRK8_B0_UDB11_A1 0x4000641b +#define CYDEV_UWRK_UWRK8_B0_UDB12_A1 0x4000641c +#define CYDEV_UWRK_UWRK8_B0_UDB13_A1 0x4000641d +#define CYDEV_UWRK_UWRK8_B0_UDB14_A1 0x4000641e +#define CYDEV_UWRK_UWRK8_B0_UDB15_A1 0x4000641f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D0 0x40006420 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D0 0x40006421 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D0 0x40006422 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D0 0x40006423 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D0 0x40006424 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D0 0x40006425 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D0 0x40006426 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D0 0x40006427 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D0 0x40006428 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D0 0x40006429 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D0 0x4000642a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D0 0x4000642b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D0 0x4000642c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D0 0x4000642d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D0 0x4000642e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D0 0x4000642f +#define CYDEV_UWRK_UWRK8_B0_UDB00_D1 0x40006430 +#define CYDEV_UWRK_UWRK8_B0_UDB01_D1 0x40006431 +#define CYDEV_UWRK_UWRK8_B0_UDB02_D1 0x40006432 +#define CYDEV_UWRK_UWRK8_B0_UDB03_D1 0x40006433 +#define CYDEV_UWRK_UWRK8_B0_UDB04_D1 0x40006434 +#define CYDEV_UWRK_UWRK8_B0_UDB05_D1 0x40006435 +#define CYDEV_UWRK_UWRK8_B0_UDB06_D1 0x40006436 +#define CYDEV_UWRK_UWRK8_B0_UDB07_D1 0x40006437 +#define CYDEV_UWRK_UWRK8_B0_UDB08_D1 0x40006438 +#define CYDEV_UWRK_UWRK8_B0_UDB09_D1 0x40006439 +#define CYDEV_UWRK_UWRK8_B0_UDB10_D1 0x4000643a +#define CYDEV_UWRK_UWRK8_B0_UDB11_D1 0x4000643b +#define CYDEV_UWRK_UWRK8_B0_UDB12_D1 0x4000643c +#define CYDEV_UWRK_UWRK8_B0_UDB13_D1 0x4000643d +#define CYDEV_UWRK_UWRK8_B0_UDB14_D1 0x4000643e +#define CYDEV_UWRK_UWRK8_B0_UDB15_D1 0x4000643f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F0 0x40006440 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F0 0x40006441 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F0 0x40006442 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F0 0x40006443 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F0 0x40006444 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F0 0x40006445 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F0 0x40006446 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F0 0x40006447 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F0 0x40006448 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F0 0x40006449 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F0 0x4000644a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F0 0x4000644b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F0 0x4000644c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F0 0x4000644d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F0 0x4000644e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F0 0x4000644f +#define CYDEV_UWRK_UWRK8_B0_UDB00_F1 0x40006450 +#define CYDEV_UWRK_UWRK8_B0_UDB01_F1 0x40006451 +#define CYDEV_UWRK_UWRK8_B0_UDB02_F1 0x40006452 +#define CYDEV_UWRK_UWRK8_B0_UDB03_F1 0x40006453 +#define CYDEV_UWRK_UWRK8_B0_UDB04_F1 0x40006454 +#define CYDEV_UWRK_UWRK8_B0_UDB05_F1 0x40006455 +#define CYDEV_UWRK_UWRK8_B0_UDB06_F1 0x40006456 +#define CYDEV_UWRK_UWRK8_B0_UDB07_F1 0x40006457 +#define CYDEV_UWRK_UWRK8_B0_UDB08_F1 0x40006458 +#define CYDEV_UWRK_UWRK8_B0_UDB09_F1 0x40006459 +#define CYDEV_UWRK_UWRK8_B0_UDB10_F1 0x4000645a +#define CYDEV_UWRK_UWRK8_B0_UDB11_F1 0x4000645b +#define CYDEV_UWRK_UWRK8_B0_UDB12_F1 0x4000645c +#define CYDEV_UWRK_UWRK8_B0_UDB13_F1 0x4000645d +#define CYDEV_UWRK_UWRK8_B0_UDB14_F1 0x4000645e +#define CYDEV_UWRK_UWRK8_B0_UDB15_F1 0x4000645f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ST 0x40006460 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ST 0x40006461 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ST 0x40006462 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ST 0x40006463 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ST 0x40006464 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ST 0x40006465 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ST 0x40006466 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ST 0x40006467 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ST 0x40006468 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ST 0x40006469 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ST 0x4000646a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ST 0x4000646b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ST 0x4000646c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ST 0x4000646d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ST 0x4000646e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ST 0x4000646f +#define CYDEV_UWRK_UWRK8_B0_UDB00_CTL 0x40006470 +#define CYDEV_UWRK_UWRK8_B0_UDB01_CTL 0x40006471 +#define CYDEV_UWRK_UWRK8_B0_UDB02_CTL 0x40006472 +#define CYDEV_UWRK_UWRK8_B0_UDB03_CTL 0x40006473 +#define CYDEV_UWRK_UWRK8_B0_UDB04_CTL 0x40006474 +#define CYDEV_UWRK_UWRK8_B0_UDB05_CTL 0x40006475 +#define CYDEV_UWRK_UWRK8_B0_UDB06_CTL 0x40006476 +#define CYDEV_UWRK_UWRK8_B0_UDB07_CTL 0x40006477 +#define CYDEV_UWRK_UWRK8_B0_UDB08_CTL 0x40006478 +#define CYDEV_UWRK_UWRK8_B0_UDB09_CTL 0x40006479 +#define CYDEV_UWRK_UWRK8_B0_UDB10_CTL 0x4000647a +#define CYDEV_UWRK_UWRK8_B0_UDB11_CTL 0x4000647b +#define CYDEV_UWRK_UWRK8_B0_UDB12_CTL 0x4000647c +#define CYDEV_UWRK_UWRK8_B0_UDB13_CTL 0x4000647d +#define CYDEV_UWRK_UWRK8_B0_UDB14_CTL 0x4000647e +#define CYDEV_UWRK_UWRK8_B0_UDB15_CTL 0x4000647f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MSK 0x40006480 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MSK 0x40006481 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MSK 0x40006482 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MSK 0x40006483 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MSK 0x40006484 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MSK 0x40006485 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MSK 0x40006486 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MSK 0x40006487 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MSK 0x40006488 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MSK 0x40006489 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MSK 0x4000648a +#define CYDEV_UWRK_UWRK8_B0_UDB11_MSK 0x4000648b +#define CYDEV_UWRK_UWRK8_B0_UDB12_MSK 0x4000648c +#define CYDEV_UWRK_UWRK8_B0_UDB13_MSK 0x4000648d +#define CYDEV_UWRK_UWRK8_B0_UDB14_MSK 0x4000648e +#define CYDEV_UWRK_UWRK8_B0_UDB15_MSK 0x4000648f +#define CYDEV_UWRK_UWRK8_B0_UDB00_ACTL 0x40006490 +#define CYDEV_UWRK_UWRK8_B0_UDB01_ACTL 0x40006491 +#define CYDEV_UWRK_UWRK8_B0_UDB02_ACTL 0x40006492 +#define CYDEV_UWRK_UWRK8_B0_UDB03_ACTL 0x40006493 +#define CYDEV_UWRK_UWRK8_B0_UDB04_ACTL 0x40006494 +#define CYDEV_UWRK_UWRK8_B0_UDB05_ACTL 0x40006495 +#define CYDEV_UWRK_UWRK8_B0_UDB06_ACTL 0x40006496 +#define CYDEV_UWRK_UWRK8_B0_UDB07_ACTL 0x40006497 +#define CYDEV_UWRK_UWRK8_B0_UDB08_ACTL 0x40006498 +#define CYDEV_UWRK_UWRK8_B0_UDB09_ACTL 0x40006499 +#define CYDEV_UWRK_UWRK8_B0_UDB10_ACTL 0x4000649a +#define CYDEV_UWRK_UWRK8_B0_UDB11_ACTL 0x4000649b +#define CYDEV_UWRK_UWRK8_B0_UDB12_ACTL 0x4000649c +#define CYDEV_UWRK_UWRK8_B0_UDB13_ACTL 0x4000649d +#define CYDEV_UWRK_UWRK8_B0_UDB14_ACTL 0x4000649e +#define CYDEV_UWRK_UWRK8_B0_UDB15_ACTL 0x4000649f +#define CYDEV_UWRK_UWRK8_B0_UDB00_MC 0x400064a0 +#define CYDEV_UWRK_UWRK8_B0_UDB01_MC 0x400064a1 +#define CYDEV_UWRK_UWRK8_B0_UDB02_MC 0x400064a2 +#define CYDEV_UWRK_UWRK8_B0_UDB03_MC 0x400064a3 +#define CYDEV_UWRK_UWRK8_B0_UDB04_MC 0x400064a4 +#define CYDEV_UWRK_UWRK8_B0_UDB05_MC 0x400064a5 +#define CYDEV_UWRK_UWRK8_B0_UDB06_MC 0x400064a6 +#define CYDEV_UWRK_UWRK8_B0_UDB07_MC 0x400064a7 +#define CYDEV_UWRK_UWRK8_B0_UDB08_MC 0x400064a8 +#define CYDEV_UWRK_UWRK8_B0_UDB09_MC 0x400064a9 +#define CYDEV_UWRK_UWRK8_B0_UDB10_MC 0x400064aa +#define CYDEV_UWRK_UWRK8_B0_UDB11_MC 0x400064ab +#define CYDEV_UWRK_UWRK8_B0_UDB12_MC 0x400064ac +#define CYDEV_UWRK_UWRK8_B0_UDB13_MC 0x400064ad +#define CYDEV_UWRK_UWRK8_B0_UDB14_MC 0x400064ae +#define CYDEV_UWRK_UWRK8_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYDEV_UWRK_UWRK8_B1_UDB04_A0 0x40006504 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A0 0x40006505 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A0 0x40006506 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A0 0x40006507 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A0 0x40006508 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A0 0x40006509 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A0 0x4000650a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A0 0x4000650b +#define CYDEV_UWRK_UWRK8_B1_UDB04_A1 0x40006514 +#define CYDEV_UWRK_UWRK8_B1_UDB05_A1 0x40006515 +#define CYDEV_UWRK_UWRK8_B1_UDB06_A1 0x40006516 +#define CYDEV_UWRK_UWRK8_B1_UDB07_A1 0x40006517 +#define CYDEV_UWRK_UWRK8_B1_UDB08_A1 0x40006518 +#define CYDEV_UWRK_UWRK8_B1_UDB09_A1 0x40006519 +#define CYDEV_UWRK_UWRK8_B1_UDB10_A1 0x4000651a +#define CYDEV_UWRK_UWRK8_B1_UDB11_A1 0x4000651b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D0 0x40006524 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D0 0x40006525 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D0 0x40006526 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D0 0x40006527 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D0 0x40006528 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D0 0x40006529 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D0 0x4000652a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D0 0x4000652b +#define CYDEV_UWRK_UWRK8_B1_UDB04_D1 0x40006534 +#define CYDEV_UWRK_UWRK8_B1_UDB05_D1 0x40006535 +#define CYDEV_UWRK_UWRK8_B1_UDB06_D1 0x40006536 +#define CYDEV_UWRK_UWRK8_B1_UDB07_D1 0x40006537 +#define CYDEV_UWRK_UWRK8_B1_UDB08_D1 0x40006538 +#define CYDEV_UWRK_UWRK8_B1_UDB09_D1 0x40006539 +#define CYDEV_UWRK_UWRK8_B1_UDB10_D1 0x4000653a +#define CYDEV_UWRK_UWRK8_B1_UDB11_D1 0x4000653b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F0 0x40006544 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F0 0x40006545 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F0 0x40006546 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F0 0x40006547 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F0 0x40006548 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F0 0x40006549 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F0 0x4000654a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F0 0x4000654b +#define CYDEV_UWRK_UWRK8_B1_UDB04_F1 0x40006554 +#define CYDEV_UWRK_UWRK8_B1_UDB05_F1 0x40006555 +#define CYDEV_UWRK_UWRK8_B1_UDB06_F1 0x40006556 +#define CYDEV_UWRK_UWRK8_B1_UDB07_F1 0x40006557 +#define CYDEV_UWRK_UWRK8_B1_UDB08_F1 0x40006558 +#define CYDEV_UWRK_UWRK8_B1_UDB09_F1 0x40006559 +#define CYDEV_UWRK_UWRK8_B1_UDB10_F1 0x4000655a +#define CYDEV_UWRK_UWRK8_B1_UDB11_F1 0x4000655b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ST 0x40006564 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ST 0x40006565 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ST 0x40006566 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ST 0x40006567 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ST 0x40006568 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ST 0x40006569 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ST 0x4000656a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ST 0x4000656b +#define CYDEV_UWRK_UWRK8_B1_UDB04_CTL 0x40006574 +#define CYDEV_UWRK_UWRK8_B1_UDB05_CTL 0x40006575 +#define CYDEV_UWRK_UWRK8_B1_UDB06_CTL 0x40006576 +#define CYDEV_UWRK_UWRK8_B1_UDB07_CTL 0x40006577 +#define CYDEV_UWRK_UWRK8_B1_UDB08_CTL 0x40006578 +#define CYDEV_UWRK_UWRK8_B1_UDB09_CTL 0x40006579 +#define CYDEV_UWRK_UWRK8_B1_UDB10_CTL 0x4000657a +#define CYDEV_UWRK_UWRK8_B1_UDB11_CTL 0x4000657b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MSK 0x40006584 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MSK 0x40006585 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MSK 0x40006586 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MSK 0x40006587 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MSK 0x40006588 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MSK 0x40006589 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MSK 0x4000658a +#define CYDEV_UWRK_UWRK8_B1_UDB11_MSK 0x4000658b +#define CYDEV_UWRK_UWRK8_B1_UDB04_ACTL 0x40006594 +#define CYDEV_UWRK_UWRK8_B1_UDB05_ACTL 0x40006595 +#define CYDEV_UWRK_UWRK8_B1_UDB06_ACTL 0x40006596 +#define CYDEV_UWRK_UWRK8_B1_UDB07_ACTL 0x40006597 +#define CYDEV_UWRK_UWRK8_B1_UDB08_ACTL 0x40006598 +#define CYDEV_UWRK_UWRK8_B1_UDB09_ACTL 0x40006599 +#define CYDEV_UWRK_UWRK8_B1_UDB10_ACTL 0x4000659a +#define CYDEV_UWRK_UWRK8_B1_UDB11_ACTL 0x4000659b +#define CYDEV_UWRK_UWRK8_B1_UDB04_MC 0x400065a4 +#define CYDEV_UWRK_UWRK8_B1_UDB05_MC 0x400065a5 +#define CYDEV_UWRK_UWRK8_B1_UDB06_MC 0x400065a6 +#define CYDEV_UWRK_UWRK8_B1_UDB07_MC 0x400065a7 +#define CYDEV_UWRK_UWRK8_B1_UDB08_MC 0x400065a8 +#define CYDEV_UWRK_UWRK8_B1_UDB09_MC 0x400065a9 +#define CYDEV_UWRK_UWRK8_B1_UDB10_MC 0x400065aa +#define CYDEV_UWRK_UWRK8_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 0x40006802 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 0x40006804 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 0x40006806 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 0x40006808 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 0x4000680a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 0x4000680c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 0x4000680e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 0x40006810 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 0x40006812 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 0x40006814 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 0x40006816 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 0x40006818 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 0x4000681a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 0x4000681c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 0x4000681e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 0x40006840 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 0x40006842 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 0x40006844 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 0x40006846 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 0x40006848 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 0x4000684a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 0x4000684c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 0x4000684e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 0x40006850 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 0x40006852 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 0x40006854 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 0x40006856 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 0x40006858 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 0x4000685a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 0x4000685c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 0x4000685e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 0x40006880 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 0x40006882 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 0x40006884 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 0x40006886 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 0x40006888 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 0x4000688a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 0x4000688c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 0x4000688e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 0x40006890 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 0x40006892 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 0x40006894 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 0x40006896 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 0x40006898 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 0x4000689a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 0x4000689c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 0x4000689e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL 0x400068c0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL 0x400068c2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL 0x400068c4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL 0x400068c6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL 0x400068c8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL 0x400068ca +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL 0x400068cc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL 0x400068ce +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL 0x400068d0 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL 0x400068d2 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL 0x400068d4 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL 0x400068d6 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL 0x400068d8 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL 0x400068da +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL 0x400068dc +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL 0x400068de +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL 0x40006900 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL 0x40006902 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL 0x40006904 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL 0x40006906 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL 0x40006908 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL 0x4000690a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL 0x4000690c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL 0x4000690e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL 0x40006910 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL 0x40006912 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL 0x40006914 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL 0x40006916 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL 0x40006918 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL 0x4000691a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL 0x4000691c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL 0x4000691e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 0x40006940 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 0x40006942 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 0x40006944 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 0x40006946 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 0x40006948 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 0x4000694a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 0x4000694c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 0x4000694e +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 0x40006950 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 0x40006952 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 0x40006954 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 0x40006956 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 0x40006958 +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 0x4000695a +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 0x4000695c +#define CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 0x40006a08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 0x40006a0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 0x40006a0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 0x40006a0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 0x40006a10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 0x40006a12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 0x40006a14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 0x40006a16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 0x40006a48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 0x40006a4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 0x40006a4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 0x40006a4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 0x40006a50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 0x40006a52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 0x40006a54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 0x40006a56 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 0x40006a88 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 0x40006a8a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 0x40006a8c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 0x40006a8e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 0x40006a90 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 0x40006a92 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 0x40006a94 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 0x40006a96 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL 0x40006ac8 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL 0x40006aca +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL 0x40006acc +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL 0x40006ace +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL 0x40006ad0 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL 0x40006ad2 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL 0x40006ad4 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL 0x40006ad6 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 0x40006b48 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 0x40006b4a +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 0x40006b4c +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 0x40006b4e +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 0x40006b50 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 0x40006b52 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 0x40006b54 +#define CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 0x40006802 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 0x40006804 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 0x40006806 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 0x40006808 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 0x4000680a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 0x4000680c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 0x4000680e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 0x40006810 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 0x40006812 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 0x40006814 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 0x40006816 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 0x40006818 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 0x4000681a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 0x4000681c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 0x40006820 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 0x40006822 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 0x40006824 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 0x40006826 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 0x40006828 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 0x4000682a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 0x4000682c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 0x4000682e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 0x40006830 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 0x40006832 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 0x40006834 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 0x40006836 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 0x40006838 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 0x4000683a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 0x4000683c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 0x40006840 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 0x40006842 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 0x40006844 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 0x40006846 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 0x40006848 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 0x4000684a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 0x4000684c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 0x4000684e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 0x40006850 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 0x40006852 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 0x40006854 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 0x40006856 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 0x40006858 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 0x4000685a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 0x4000685c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 0x40006860 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 0x40006862 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 0x40006864 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 0x40006866 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 0x40006868 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 0x4000686a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 0x4000686c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 0x4000686e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 0x40006870 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 0x40006872 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 0x40006874 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 0x40006876 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 0x40006878 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 0x4000687a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 0x4000687c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 0x40006880 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 0x40006882 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 0x40006884 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 0x40006886 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 0x40006888 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 0x4000688a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 0x4000688c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 0x4000688e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 0x40006890 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 0x40006892 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 0x40006894 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 0x40006896 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 0x40006898 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 0x4000689a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 0x4000689c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 0x400068a0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 0x400068a2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 0x400068a4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 0x400068a6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 0x400068a8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 0x400068aa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 0x400068ac +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 0x400068ae +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 0x400068b0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 0x400068b2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 0x400068b4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 0x400068b6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 0x400068b8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 0x400068ba +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 0x400068bc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST 0x400068c0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST 0x400068c2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST 0x400068c4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST 0x400068c6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST 0x400068c8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST 0x400068ca +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST 0x400068cc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST 0x400068ce +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST 0x400068d0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST 0x400068d2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST 0x400068d4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST 0x400068d6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST 0x400068d8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST 0x400068da +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST 0x400068dc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL 0x400068e0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL 0x400068e2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL 0x400068e4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL 0x400068e6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL 0x400068e8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL 0x400068ea +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL 0x400068ec +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL 0x400068ee +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL 0x400068f0 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL 0x400068f2 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL 0x400068f4 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL 0x400068f6 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL 0x400068f8 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL 0x400068fa +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL 0x400068fc +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK 0x40006900 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK 0x40006902 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK 0x40006904 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK 0x40006906 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK 0x40006908 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK 0x4000690a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK 0x4000690c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK 0x4000690e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK 0x40006910 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK 0x40006912 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK 0x40006914 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK 0x40006916 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK 0x40006918 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK 0x4000691a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK 0x4000691c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL 0x40006920 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL 0x40006922 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL 0x40006924 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL 0x40006926 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL 0x40006928 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL 0x4000692a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL 0x4000692c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL 0x4000692e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL 0x40006930 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL 0x40006932 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL 0x40006934 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL 0x40006936 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL 0x40006938 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL 0x4000693a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL 0x4000693c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC 0x40006940 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC 0x40006942 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC 0x40006944 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC 0x40006946 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC 0x40006948 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC 0x4000694a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC 0x4000694c +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC 0x4000694e +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC 0x40006950 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC 0x40006952 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC 0x40006954 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC 0x40006956 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC 0x40006958 +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC 0x4000695a +#define CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 0x40006a08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 0x40006a0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 0x40006a0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 0x40006a0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 0x40006a10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 0x40006a12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 0x40006a14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 0x40006a16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 0x40006a28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 0x40006a2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 0x40006a2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 0x40006a2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 0x40006a30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 0x40006a32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 0x40006a34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 0x40006a36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 0x40006a48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 0x40006a4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 0x40006a4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 0x40006a4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 0x40006a50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 0x40006a52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 0x40006a54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 0x40006a56 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 0x40006a68 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 0x40006a6a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 0x40006a6c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 0x40006a6e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 0x40006a70 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 0x40006a72 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 0x40006a74 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 0x40006a76 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 0x40006a88 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 0x40006a8a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 0x40006a8c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 0x40006a8e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 0x40006a90 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 0x40006a92 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 0x40006a94 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 0x40006a96 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 0x40006aa8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 0x40006aaa +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 0x40006aac +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 0x40006aae +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 0x40006ab0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 0x40006ab2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 0x40006ab4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 0x40006ab6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST 0x40006ac8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST 0x40006aca +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST 0x40006acc +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST 0x40006ace +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST 0x40006ad0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST 0x40006ad2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST 0x40006ad4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST 0x40006ad6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL 0x40006ae8 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL 0x40006aea +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL 0x40006aec +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL 0x40006aee +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL 0x40006af0 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL 0x40006af2 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL 0x40006af4 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL 0x40006af6 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK 0x40006b08 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK 0x40006b0a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK 0x40006b0c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK 0x40006b0e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK 0x40006b10 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK 0x40006b12 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK 0x40006b14 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK 0x40006b16 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL 0x40006b28 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL 0x40006b2a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL 0x40006b2c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL 0x40006b2e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL 0x40006b30 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL 0x40006b32 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL 0x40006b34 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL 0x40006b36 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC 0x40006b48 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC 0x40006b4a +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC 0x40006b4c +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC 0x40006b4e +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC 0x40006b50 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC 0x40006b52 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC 0x40006b54 +#define CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYDEV_PHUB_CFG 0x40007000 +#define CYDEV_PHUB_ERR 0x40007004 +#define CYDEV_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYDEV_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYDEV_PHUB_CH0_ACTION 0x40007014 +#define CYDEV_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYDEV_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYDEV_PHUB_CH1_ACTION 0x40007024 +#define CYDEV_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYDEV_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYDEV_PHUB_CH2_ACTION 0x40007034 +#define CYDEV_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYDEV_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYDEV_PHUB_CH3_ACTION 0x40007044 +#define CYDEV_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYDEV_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYDEV_PHUB_CH4_ACTION 0x40007054 +#define CYDEV_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYDEV_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYDEV_PHUB_CH5_ACTION 0x40007064 +#define CYDEV_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYDEV_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYDEV_PHUB_CH6_ACTION 0x40007074 +#define CYDEV_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYDEV_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYDEV_PHUB_CH7_ACTION 0x40007084 +#define CYDEV_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYDEV_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYDEV_PHUB_CH8_ACTION 0x40007094 +#define CYDEV_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYDEV_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYDEV_PHUB_CH9_ACTION 0x400070a4 +#define CYDEV_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYDEV_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYDEV_PHUB_CH10_ACTION 0x400070b4 +#define CYDEV_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYDEV_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYDEV_PHUB_CH11_ACTION 0x400070c4 +#define CYDEV_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYDEV_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYDEV_PHUB_CH12_ACTION 0x400070d4 +#define CYDEV_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYDEV_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYDEV_PHUB_CH13_ACTION 0x400070e4 +#define CYDEV_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYDEV_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYDEV_PHUB_CH14_ACTION 0x400070f4 +#define CYDEV_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYDEV_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYDEV_PHUB_CH15_ACTION 0x40007104 +#define CYDEV_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYDEV_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYDEV_PHUB_CH16_ACTION 0x40007114 +#define CYDEV_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYDEV_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYDEV_PHUB_CH17_ACTION 0x40007124 +#define CYDEV_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYDEV_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYDEV_PHUB_CH18_ACTION 0x40007134 +#define CYDEV_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYDEV_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYDEV_PHUB_CH19_ACTION 0x40007144 +#define CYDEV_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYDEV_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYDEV_PHUB_CH20_ACTION 0x40007154 +#define CYDEV_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYDEV_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYDEV_PHUB_CH21_ACTION 0x40007164 +#define CYDEV_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYDEV_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYDEV_PHUB_CH22_ACTION 0x40007174 +#define CYDEV_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYDEV_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYDEV_PHUB_CH23_ACTION 0x40007184 +#define CYDEV_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYDEV_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYDEV_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYDEV_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYDEV_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYDEV_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYDEV_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYDEV_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYDEV_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYDEV_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYDEV_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYDEV_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYDEV_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYDEV_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYDEV_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYDEV_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYDEV_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYDEV_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYDEV_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYDEV_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYDEV_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYDEV_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYDEV_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYDEV_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYDEV_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYDEV_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYDEV_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYDEV_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYDEV_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYDEV_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYDEV_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYDEV_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYDEV_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYDEV_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYDEV_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYDEV_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYDEV_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYDEV_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYDEV_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYDEV_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYDEV_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYDEV_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYDEV_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYDEV_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYDEV_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYDEV_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYDEV_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYDEV_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYDEV_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYDEV_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYDEV_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYDEV_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYDEV_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYDEV_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYDEV_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYDEV_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYDEV_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYDEV_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYDEV_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYDEV_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYDEV_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYDEV_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYDEV_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYDEV_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYDEV_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYDEV_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYDEV_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYDEV_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYDEV_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYDEV_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYDEV_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYDEV_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYDEV_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYDEV_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYDEV_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYDEV_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYDEV_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYDEV_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYDEV_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYDEV_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYDEV_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYDEV_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYDEV_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYDEV_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYDEV_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYDEV_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYDEV_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYDEV_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYDEV_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYDEV_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYDEV_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYDEV_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYDEV_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYDEV_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYDEV_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYDEV_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYDEV_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYDEV_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYDEV_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYDEV_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYDEV_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYDEV_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYDEV_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYDEV_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYDEV_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYDEV_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYDEV_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYDEV_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYDEV_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYDEV_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYDEV_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYDEV_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYDEV_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYDEV_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYDEV_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYDEV_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYDEV_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYDEV_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYDEV_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYDEV_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYDEV_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYDEV_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYDEV_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYDEV_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYDEV_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYDEV_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYDEV_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYDEV_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYDEV_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYDEV_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYDEV_EE_DATA_MBASE 0x40008000 +#define CYDEV_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYDEV_CAN0_CSR_INT_SR 0x4000a000 +#define CYDEV_CAN0_CSR_INT_EN 0x4000a004 +#define CYDEV_CAN0_CSR_BUF_SR 0x4000a008 +#define CYDEV_CAN0_CSR_ERR_SR 0x4000a00c +#define CYDEV_CAN0_CSR_CMD 0x4000a010 +#define CYDEV_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYDEV_CAN0_TX0_CMD 0x4000a020 +#define CYDEV_CAN0_TX0_ID 0x4000a024 +#define CYDEV_CAN0_TX0_DH 0x4000a028 +#define CYDEV_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYDEV_CAN0_TX1_CMD 0x4000a030 +#define CYDEV_CAN0_TX1_ID 0x4000a034 +#define CYDEV_CAN0_TX1_DH 0x4000a038 +#define CYDEV_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYDEV_CAN0_TX2_CMD 0x4000a040 +#define CYDEV_CAN0_TX2_ID 0x4000a044 +#define CYDEV_CAN0_TX2_DH 0x4000a048 +#define CYDEV_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYDEV_CAN0_TX3_CMD 0x4000a050 +#define CYDEV_CAN0_TX3_ID 0x4000a054 +#define CYDEV_CAN0_TX3_DH 0x4000a058 +#define CYDEV_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYDEV_CAN0_TX4_CMD 0x4000a060 +#define CYDEV_CAN0_TX4_ID 0x4000a064 +#define CYDEV_CAN0_TX4_DH 0x4000a068 +#define CYDEV_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYDEV_CAN0_TX5_CMD 0x4000a070 +#define CYDEV_CAN0_TX5_ID 0x4000a074 +#define CYDEV_CAN0_TX5_DH 0x4000a078 +#define CYDEV_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYDEV_CAN0_TX6_CMD 0x4000a080 +#define CYDEV_CAN0_TX6_ID 0x4000a084 +#define CYDEV_CAN0_TX6_DH 0x4000a088 +#define CYDEV_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYDEV_CAN0_TX7_CMD 0x4000a090 +#define CYDEV_CAN0_TX7_ID 0x4000a094 +#define CYDEV_CAN0_TX7_DH 0x4000a098 +#define CYDEV_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYDEV_CAN0_RX0_CMD 0x4000a0a0 +#define CYDEV_CAN0_RX0_ID 0x4000a0a4 +#define CYDEV_CAN0_RX0_DH 0x4000a0a8 +#define CYDEV_CAN0_RX0_DL 0x4000a0ac +#define CYDEV_CAN0_RX0_AMR 0x4000a0b0 +#define CYDEV_CAN0_RX0_ACR 0x4000a0b4 +#define CYDEV_CAN0_RX0_AMRD 0x4000a0b8 +#define CYDEV_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYDEV_CAN0_RX1_CMD 0x4000a0c0 +#define CYDEV_CAN0_RX1_ID 0x4000a0c4 +#define CYDEV_CAN0_RX1_DH 0x4000a0c8 +#define CYDEV_CAN0_RX1_DL 0x4000a0cc +#define CYDEV_CAN0_RX1_AMR 0x4000a0d0 +#define CYDEV_CAN0_RX1_ACR 0x4000a0d4 +#define CYDEV_CAN0_RX1_AMRD 0x4000a0d8 +#define CYDEV_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYDEV_CAN0_RX2_CMD 0x4000a0e0 +#define CYDEV_CAN0_RX2_ID 0x4000a0e4 +#define CYDEV_CAN0_RX2_DH 0x4000a0e8 +#define CYDEV_CAN0_RX2_DL 0x4000a0ec +#define CYDEV_CAN0_RX2_AMR 0x4000a0f0 +#define CYDEV_CAN0_RX2_ACR 0x4000a0f4 +#define CYDEV_CAN0_RX2_AMRD 0x4000a0f8 +#define CYDEV_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYDEV_CAN0_RX3_CMD 0x4000a100 +#define CYDEV_CAN0_RX3_ID 0x4000a104 +#define CYDEV_CAN0_RX3_DH 0x4000a108 +#define CYDEV_CAN0_RX3_DL 0x4000a10c +#define CYDEV_CAN0_RX3_AMR 0x4000a110 +#define CYDEV_CAN0_RX3_ACR 0x4000a114 +#define CYDEV_CAN0_RX3_AMRD 0x4000a118 +#define CYDEV_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYDEV_CAN0_RX4_CMD 0x4000a120 +#define CYDEV_CAN0_RX4_ID 0x4000a124 +#define CYDEV_CAN0_RX4_DH 0x4000a128 +#define CYDEV_CAN0_RX4_DL 0x4000a12c +#define CYDEV_CAN0_RX4_AMR 0x4000a130 +#define CYDEV_CAN0_RX4_ACR 0x4000a134 +#define CYDEV_CAN0_RX4_AMRD 0x4000a138 +#define CYDEV_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYDEV_CAN0_RX5_CMD 0x4000a140 +#define CYDEV_CAN0_RX5_ID 0x4000a144 +#define CYDEV_CAN0_RX5_DH 0x4000a148 +#define CYDEV_CAN0_RX5_DL 0x4000a14c +#define CYDEV_CAN0_RX5_AMR 0x4000a150 +#define CYDEV_CAN0_RX5_ACR 0x4000a154 +#define CYDEV_CAN0_RX5_AMRD 0x4000a158 +#define CYDEV_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYDEV_CAN0_RX6_CMD 0x4000a160 +#define CYDEV_CAN0_RX6_ID 0x4000a164 +#define CYDEV_CAN0_RX6_DH 0x4000a168 +#define CYDEV_CAN0_RX6_DL 0x4000a16c +#define CYDEV_CAN0_RX6_AMR 0x4000a170 +#define CYDEV_CAN0_RX6_ACR 0x4000a174 +#define CYDEV_CAN0_RX6_AMRD 0x4000a178 +#define CYDEV_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYDEV_CAN0_RX7_CMD 0x4000a180 +#define CYDEV_CAN0_RX7_ID 0x4000a184 +#define CYDEV_CAN0_RX7_DH 0x4000a188 +#define CYDEV_CAN0_RX7_DL 0x4000a18c +#define CYDEV_CAN0_RX7_AMR 0x4000a190 +#define CYDEV_CAN0_RX7_ACR 0x4000a194 +#define CYDEV_CAN0_RX7_AMRD 0x4000a198 +#define CYDEV_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYDEV_CAN0_RX8_CMD 0x4000a1a0 +#define CYDEV_CAN0_RX8_ID 0x4000a1a4 +#define CYDEV_CAN0_RX8_DH 0x4000a1a8 +#define CYDEV_CAN0_RX8_DL 0x4000a1ac +#define CYDEV_CAN0_RX8_AMR 0x4000a1b0 +#define CYDEV_CAN0_RX8_ACR 0x4000a1b4 +#define CYDEV_CAN0_RX8_AMRD 0x4000a1b8 +#define CYDEV_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYDEV_CAN0_RX9_CMD 0x4000a1c0 +#define CYDEV_CAN0_RX9_ID 0x4000a1c4 +#define CYDEV_CAN0_RX9_DH 0x4000a1c8 +#define CYDEV_CAN0_RX9_DL 0x4000a1cc +#define CYDEV_CAN0_RX9_AMR 0x4000a1d0 +#define CYDEV_CAN0_RX9_ACR 0x4000a1d4 +#define CYDEV_CAN0_RX9_AMRD 0x4000a1d8 +#define CYDEV_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYDEV_CAN0_RX10_CMD 0x4000a1e0 +#define CYDEV_CAN0_RX10_ID 0x4000a1e4 +#define CYDEV_CAN0_RX10_DH 0x4000a1e8 +#define CYDEV_CAN0_RX10_DL 0x4000a1ec +#define CYDEV_CAN0_RX10_AMR 0x4000a1f0 +#define CYDEV_CAN0_RX10_ACR 0x4000a1f4 +#define CYDEV_CAN0_RX10_AMRD 0x4000a1f8 +#define CYDEV_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYDEV_CAN0_RX11_CMD 0x4000a200 +#define CYDEV_CAN0_RX11_ID 0x4000a204 +#define CYDEV_CAN0_RX11_DH 0x4000a208 +#define CYDEV_CAN0_RX11_DL 0x4000a20c +#define CYDEV_CAN0_RX11_AMR 0x4000a210 +#define CYDEV_CAN0_RX11_ACR 0x4000a214 +#define CYDEV_CAN0_RX11_AMRD 0x4000a218 +#define CYDEV_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYDEV_CAN0_RX12_CMD 0x4000a220 +#define CYDEV_CAN0_RX12_ID 0x4000a224 +#define CYDEV_CAN0_RX12_DH 0x4000a228 +#define CYDEV_CAN0_RX12_DL 0x4000a22c +#define CYDEV_CAN0_RX12_AMR 0x4000a230 +#define CYDEV_CAN0_RX12_ACR 0x4000a234 +#define CYDEV_CAN0_RX12_AMRD 0x4000a238 +#define CYDEV_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYDEV_CAN0_RX13_CMD 0x4000a240 +#define CYDEV_CAN0_RX13_ID 0x4000a244 +#define CYDEV_CAN0_RX13_DH 0x4000a248 +#define CYDEV_CAN0_RX13_DL 0x4000a24c +#define CYDEV_CAN0_RX13_AMR 0x4000a250 +#define CYDEV_CAN0_RX13_ACR 0x4000a254 +#define CYDEV_CAN0_RX13_AMRD 0x4000a258 +#define CYDEV_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYDEV_CAN0_RX14_CMD 0x4000a260 +#define CYDEV_CAN0_RX14_ID 0x4000a264 +#define CYDEV_CAN0_RX14_DH 0x4000a268 +#define CYDEV_CAN0_RX14_DL 0x4000a26c +#define CYDEV_CAN0_RX14_AMR 0x4000a270 +#define CYDEV_CAN0_RX14_ACR 0x4000a274 +#define CYDEV_CAN0_RX14_AMRD 0x4000a278 +#define CYDEV_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYDEV_CAN0_RX15_CMD 0x4000a280 +#define CYDEV_CAN0_RX15_ID 0x4000a284 +#define CYDEV_CAN0_RX15_DH 0x4000a288 +#define CYDEV_CAN0_RX15_DL 0x4000a28c +#define CYDEV_CAN0_RX15_AMR 0x4000a290 +#define CYDEV_CAN0_RX15_ACR 0x4000a294 +#define CYDEV_CAN0_RX15_AMRD 0x4000a298 +#define CYDEV_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYDEV_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYDEV_DFB0_CR 0x4000c780 +#define CYDEV_DFB0_SR 0x4000c784 +#define CYDEV_DFB0_RAM_EN 0x4000c788 +#define CYDEV_DFB0_RAM_DIR 0x4000c78c +#define CYDEV_DFB0_SEMA 0x4000c790 +#define CYDEV_DFB0_DSI_CTRL 0x4000c794 +#define CYDEV_DFB0_INT_CTRL 0x4000c798 +#define CYDEV_DFB0_DMA_CTRL 0x4000c79c +#define CYDEV_DFB0_STAGEA 0x4000c7a0 +#define CYDEV_DFB0_STAGEAM 0x4000c7a1 +#define CYDEV_DFB0_STAGEAH 0x4000c7a2 +#define CYDEV_DFB0_STAGEB 0x4000c7a4 +#define CYDEV_DFB0_STAGEBM 0x4000c7a5 +#define CYDEV_DFB0_STAGEBH 0x4000c7a6 +#define CYDEV_DFB0_HOLDA 0x4000c7a8 +#define CYDEV_DFB0_HOLDAM 0x4000c7a9 +#define CYDEV_DFB0_HOLDAH 0x4000c7aa +#define CYDEV_DFB0_HOLDAS 0x4000c7ab +#define CYDEV_DFB0_HOLDB 0x4000c7ac +#define CYDEV_DFB0_HOLDBM 0x4000c7ad +#define CYDEV_DFB0_HOLDBH 0x4000c7ae +#define CYDEV_DFB0_HOLDBS 0x4000c7af +#define CYDEV_DFB0_COHER 0x4000c7b0 +#define CYDEV_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYDEV_UCFG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYDEV_UCFG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYDEV_UCFG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYDEV_UCFG_B0_P0_U0_CFG0 0x40010040 +#define CYDEV_UCFG_B0_P0_U0_CFG1 0x40010041 +#define CYDEV_UCFG_B0_P0_U0_CFG2 0x40010042 +#define CYDEV_UCFG_B0_P0_U0_CFG3 0x40010043 +#define CYDEV_UCFG_B0_P0_U0_CFG4 0x40010044 +#define CYDEV_UCFG_B0_P0_U0_CFG5 0x40010045 +#define CYDEV_UCFG_B0_P0_U0_CFG6 0x40010046 +#define CYDEV_UCFG_B0_P0_U0_CFG7 0x40010047 +#define CYDEV_UCFG_B0_P0_U0_CFG8 0x40010048 +#define CYDEV_UCFG_B0_P0_U0_CFG9 0x40010049 +#define CYDEV_UCFG_B0_P0_U0_CFG10 0x4001004a +#define CYDEV_UCFG_B0_P0_U0_CFG11 0x4001004b +#define CYDEV_UCFG_B0_P0_U0_CFG12 0x4001004c +#define CYDEV_UCFG_B0_P0_U0_CFG13 0x4001004d +#define CYDEV_UCFG_B0_P0_U0_CFG14 0x4001004e +#define CYDEV_UCFG_B0_P0_U0_CFG15 0x4001004f +#define CYDEV_UCFG_B0_P0_U0_CFG16 0x40010050 +#define CYDEV_UCFG_B0_P0_U0_CFG17 0x40010051 +#define CYDEV_UCFG_B0_P0_U0_CFG18 0x40010052 +#define CYDEV_UCFG_B0_P0_U0_CFG19 0x40010053 +#define CYDEV_UCFG_B0_P0_U0_CFG20 0x40010054 +#define CYDEV_UCFG_B0_P0_U0_CFG21 0x40010055 +#define CYDEV_UCFG_B0_P0_U0_CFG22 0x40010056 +#define CYDEV_UCFG_B0_P0_U0_CFG23 0x40010057 +#define CYDEV_UCFG_B0_P0_U0_CFG24 0x40010058 +#define CYDEV_UCFG_B0_P0_U0_CFG25 0x40010059 +#define CYDEV_UCFG_B0_P0_U0_CFG26 0x4001005a +#define CYDEV_UCFG_B0_P0_U0_CFG27 0x4001005b +#define CYDEV_UCFG_B0_P0_U0_CFG28 0x4001005c +#define CYDEV_UCFG_B0_P0_U0_CFG29 0x4001005d +#define CYDEV_UCFG_B0_P0_U0_CFG30 0x4001005e +#define CYDEV_UCFG_B0_P0_U0_CFG31 0x4001005f +#define CYDEV_UCFG_B0_P0_U0_DCFG0 0x40010060 +#define CYDEV_UCFG_B0_P0_U0_DCFG1 0x40010062 +#define CYDEV_UCFG_B0_P0_U0_DCFG2 0x40010064 +#define CYDEV_UCFG_B0_P0_U0_DCFG3 0x40010066 +#define CYDEV_UCFG_B0_P0_U0_DCFG4 0x40010068 +#define CYDEV_UCFG_B0_P0_U0_DCFG5 0x4001006a +#define CYDEV_UCFG_B0_P0_U0_DCFG6 0x4001006c +#define CYDEV_UCFG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYDEV_UCFG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYDEV_UCFG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYDEV_UCFG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYDEV_UCFG_B0_P0_U1_CFG0 0x400100c0 +#define CYDEV_UCFG_B0_P0_U1_CFG1 0x400100c1 +#define CYDEV_UCFG_B0_P0_U1_CFG2 0x400100c2 +#define CYDEV_UCFG_B0_P0_U1_CFG3 0x400100c3 +#define CYDEV_UCFG_B0_P0_U1_CFG4 0x400100c4 +#define CYDEV_UCFG_B0_P0_U1_CFG5 0x400100c5 +#define CYDEV_UCFG_B0_P0_U1_CFG6 0x400100c6 +#define CYDEV_UCFG_B0_P0_U1_CFG7 0x400100c7 +#define CYDEV_UCFG_B0_P0_U1_CFG8 0x400100c8 +#define CYDEV_UCFG_B0_P0_U1_CFG9 0x400100c9 +#define CYDEV_UCFG_B0_P0_U1_CFG10 0x400100ca +#define CYDEV_UCFG_B0_P0_U1_CFG11 0x400100cb +#define CYDEV_UCFG_B0_P0_U1_CFG12 0x400100cc +#define CYDEV_UCFG_B0_P0_U1_CFG13 0x400100cd +#define CYDEV_UCFG_B0_P0_U1_CFG14 0x400100ce +#define CYDEV_UCFG_B0_P0_U1_CFG15 0x400100cf +#define CYDEV_UCFG_B0_P0_U1_CFG16 0x400100d0 +#define CYDEV_UCFG_B0_P0_U1_CFG17 0x400100d1 +#define CYDEV_UCFG_B0_P0_U1_CFG18 0x400100d2 +#define CYDEV_UCFG_B0_P0_U1_CFG19 0x400100d3 +#define CYDEV_UCFG_B0_P0_U1_CFG20 0x400100d4 +#define CYDEV_UCFG_B0_P0_U1_CFG21 0x400100d5 +#define CYDEV_UCFG_B0_P0_U1_CFG22 0x400100d6 +#define CYDEV_UCFG_B0_P0_U1_CFG23 0x400100d7 +#define CYDEV_UCFG_B0_P0_U1_CFG24 0x400100d8 +#define CYDEV_UCFG_B0_P0_U1_CFG25 0x400100d9 +#define CYDEV_UCFG_B0_P0_U1_CFG26 0x400100da +#define CYDEV_UCFG_B0_P0_U1_CFG27 0x400100db +#define CYDEV_UCFG_B0_P0_U1_CFG28 0x400100dc +#define CYDEV_UCFG_B0_P0_U1_CFG29 0x400100dd +#define CYDEV_UCFG_B0_P0_U1_CFG30 0x400100de +#define CYDEV_UCFG_B0_P0_U1_CFG31 0x400100df +#define CYDEV_UCFG_B0_P0_U1_DCFG0 0x400100e0 +#define CYDEV_UCFG_B0_P0_U1_DCFG1 0x400100e2 +#define CYDEV_UCFG_B0_P0_U1_DCFG2 0x400100e4 +#define CYDEV_UCFG_B0_P0_U1_DCFG3 0x400100e6 +#define CYDEV_UCFG_B0_P0_U1_DCFG4 0x400100e8 +#define CYDEV_UCFG_B0_P0_U1_DCFG5 0x400100ea +#define CYDEV_UCFG_B0_P0_U1_DCFG6 0x400100ec +#define CYDEV_UCFG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYDEV_UCFG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYDEV_UCFG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYDEV_UCFG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYDEV_UCFG_B0_P1_U0_CFG0 0x40010240 +#define CYDEV_UCFG_B0_P1_U0_CFG1 0x40010241 +#define CYDEV_UCFG_B0_P1_U0_CFG2 0x40010242 +#define CYDEV_UCFG_B0_P1_U0_CFG3 0x40010243 +#define CYDEV_UCFG_B0_P1_U0_CFG4 0x40010244 +#define CYDEV_UCFG_B0_P1_U0_CFG5 0x40010245 +#define CYDEV_UCFG_B0_P1_U0_CFG6 0x40010246 +#define CYDEV_UCFG_B0_P1_U0_CFG7 0x40010247 +#define CYDEV_UCFG_B0_P1_U0_CFG8 0x40010248 +#define CYDEV_UCFG_B0_P1_U0_CFG9 0x40010249 +#define CYDEV_UCFG_B0_P1_U0_CFG10 0x4001024a +#define CYDEV_UCFG_B0_P1_U0_CFG11 0x4001024b +#define CYDEV_UCFG_B0_P1_U0_CFG12 0x4001024c +#define CYDEV_UCFG_B0_P1_U0_CFG13 0x4001024d +#define CYDEV_UCFG_B0_P1_U0_CFG14 0x4001024e +#define CYDEV_UCFG_B0_P1_U0_CFG15 0x4001024f +#define CYDEV_UCFG_B0_P1_U0_CFG16 0x40010250 +#define CYDEV_UCFG_B0_P1_U0_CFG17 0x40010251 +#define CYDEV_UCFG_B0_P1_U0_CFG18 0x40010252 +#define CYDEV_UCFG_B0_P1_U0_CFG19 0x40010253 +#define CYDEV_UCFG_B0_P1_U0_CFG20 0x40010254 +#define CYDEV_UCFG_B0_P1_U0_CFG21 0x40010255 +#define CYDEV_UCFG_B0_P1_U0_CFG22 0x40010256 +#define CYDEV_UCFG_B0_P1_U0_CFG23 0x40010257 +#define CYDEV_UCFG_B0_P1_U0_CFG24 0x40010258 +#define CYDEV_UCFG_B0_P1_U0_CFG25 0x40010259 +#define CYDEV_UCFG_B0_P1_U0_CFG26 0x4001025a +#define CYDEV_UCFG_B0_P1_U0_CFG27 0x4001025b +#define CYDEV_UCFG_B0_P1_U0_CFG28 0x4001025c +#define CYDEV_UCFG_B0_P1_U0_CFG29 0x4001025d +#define CYDEV_UCFG_B0_P1_U0_CFG30 0x4001025e +#define CYDEV_UCFG_B0_P1_U0_CFG31 0x4001025f +#define CYDEV_UCFG_B0_P1_U0_DCFG0 0x40010260 +#define CYDEV_UCFG_B0_P1_U0_DCFG1 0x40010262 +#define CYDEV_UCFG_B0_P1_U0_DCFG2 0x40010264 +#define CYDEV_UCFG_B0_P1_U0_DCFG3 0x40010266 +#define CYDEV_UCFG_B0_P1_U0_DCFG4 0x40010268 +#define CYDEV_UCFG_B0_P1_U0_DCFG5 0x4001026a +#define CYDEV_UCFG_B0_P1_U0_DCFG6 0x4001026c +#define CYDEV_UCFG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYDEV_UCFG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYDEV_UCFG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYDEV_UCFG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYDEV_UCFG_B0_P1_U1_CFG0 0x400102c0 +#define CYDEV_UCFG_B0_P1_U1_CFG1 0x400102c1 +#define CYDEV_UCFG_B0_P1_U1_CFG2 0x400102c2 +#define CYDEV_UCFG_B0_P1_U1_CFG3 0x400102c3 +#define CYDEV_UCFG_B0_P1_U1_CFG4 0x400102c4 +#define CYDEV_UCFG_B0_P1_U1_CFG5 0x400102c5 +#define CYDEV_UCFG_B0_P1_U1_CFG6 0x400102c6 +#define CYDEV_UCFG_B0_P1_U1_CFG7 0x400102c7 +#define CYDEV_UCFG_B0_P1_U1_CFG8 0x400102c8 +#define CYDEV_UCFG_B0_P1_U1_CFG9 0x400102c9 +#define CYDEV_UCFG_B0_P1_U1_CFG10 0x400102ca +#define CYDEV_UCFG_B0_P1_U1_CFG11 0x400102cb +#define CYDEV_UCFG_B0_P1_U1_CFG12 0x400102cc +#define CYDEV_UCFG_B0_P1_U1_CFG13 0x400102cd +#define CYDEV_UCFG_B0_P1_U1_CFG14 0x400102ce +#define CYDEV_UCFG_B0_P1_U1_CFG15 0x400102cf +#define CYDEV_UCFG_B0_P1_U1_CFG16 0x400102d0 +#define CYDEV_UCFG_B0_P1_U1_CFG17 0x400102d1 +#define CYDEV_UCFG_B0_P1_U1_CFG18 0x400102d2 +#define CYDEV_UCFG_B0_P1_U1_CFG19 0x400102d3 +#define CYDEV_UCFG_B0_P1_U1_CFG20 0x400102d4 +#define CYDEV_UCFG_B0_P1_U1_CFG21 0x400102d5 +#define CYDEV_UCFG_B0_P1_U1_CFG22 0x400102d6 +#define CYDEV_UCFG_B0_P1_U1_CFG23 0x400102d7 +#define CYDEV_UCFG_B0_P1_U1_CFG24 0x400102d8 +#define CYDEV_UCFG_B0_P1_U1_CFG25 0x400102d9 +#define CYDEV_UCFG_B0_P1_U1_CFG26 0x400102da +#define CYDEV_UCFG_B0_P1_U1_CFG27 0x400102db +#define CYDEV_UCFG_B0_P1_U1_CFG28 0x400102dc +#define CYDEV_UCFG_B0_P1_U1_CFG29 0x400102dd +#define CYDEV_UCFG_B0_P1_U1_CFG30 0x400102de +#define CYDEV_UCFG_B0_P1_U1_CFG31 0x400102df +#define CYDEV_UCFG_B0_P1_U1_DCFG0 0x400102e0 +#define CYDEV_UCFG_B0_P1_U1_DCFG1 0x400102e2 +#define CYDEV_UCFG_B0_P1_U1_DCFG2 0x400102e4 +#define CYDEV_UCFG_B0_P1_U1_DCFG3 0x400102e6 +#define CYDEV_UCFG_B0_P1_U1_DCFG4 0x400102e8 +#define CYDEV_UCFG_B0_P1_U1_DCFG5 0x400102ea +#define CYDEV_UCFG_B0_P1_U1_DCFG6 0x400102ec +#define CYDEV_UCFG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYDEV_UCFG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYDEV_UCFG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYDEV_UCFG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYDEV_UCFG_B0_P2_U0_CFG0 0x40010440 +#define CYDEV_UCFG_B0_P2_U0_CFG1 0x40010441 +#define CYDEV_UCFG_B0_P2_U0_CFG2 0x40010442 +#define CYDEV_UCFG_B0_P2_U0_CFG3 0x40010443 +#define CYDEV_UCFG_B0_P2_U0_CFG4 0x40010444 +#define CYDEV_UCFG_B0_P2_U0_CFG5 0x40010445 +#define CYDEV_UCFG_B0_P2_U0_CFG6 0x40010446 +#define CYDEV_UCFG_B0_P2_U0_CFG7 0x40010447 +#define CYDEV_UCFG_B0_P2_U0_CFG8 0x40010448 +#define CYDEV_UCFG_B0_P2_U0_CFG9 0x40010449 +#define CYDEV_UCFG_B0_P2_U0_CFG10 0x4001044a +#define CYDEV_UCFG_B0_P2_U0_CFG11 0x4001044b +#define CYDEV_UCFG_B0_P2_U0_CFG12 0x4001044c +#define CYDEV_UCFG_B0_P2_U0_CFG13 0x4001044d +#define CYDEV_UCFG_B0_P2_U0_CFG14 0x4001044e +#define CYDEV_UCFG_B0_P2_U0_CFG15 0x4001044f +#define CYDEV_UCFG_B0_P2_U0_CFG16 0x40010450 +#define CYDEV_UCFG_B0_P2_U0_CFG17 0x40010451 +#define CYDEV_UCFG_B0_P2_U0_CFG18 0x40010452 +#define CYDEV_UCFG_B0_P2_U0_CFG19 0x40010453 +#define CYDEV_UCFG_B0_P2_U0_CFG20 0x40010454 +#define CYDEV_UCFG_B0_P2_U0_CFG21 0x40010455 +#define CYDEV_UCFG_B0_P2_U0_CFG22 0x40010456 +#define CYDEV_UCFG_B0_P2_U0_CFG23 0x40010457 +#define CYDEV_UCFG_B0_P2_U0_CFG24 0x40010458 +#define CYDEV_UCFG_B0_P2_U0_CFG25 0x40010459 +#define CYDEV_UCFG_B0_P2_U0_CFG26 0x4001045a +#define CYDEV_UCFG_B0_P2_U0_CFG27 0x4001045b +#define CYDEV_UCFG_B0_P2_U0_CFG28 0x4001045c +#define CYDEV_UCFG_B0_P2_U0_CFG29 0x4001045d +#define CYDEV_UCFG_B0_P2_U0_CFG30 0x4001045e +#define CYDEV_UCFG_B0_P2_U0_CFG31 0x4001045f +#define CYDEV_UCFG_B0_P2_U0_DCFG0 0x40010460 +#define CYDEV_UCFG_B0_P2_U0_DCFG1 0x40010462 +#define CYDEV_UCFG_B0_P2_U0_DCFG2 0x40010464 +#define CYDEV_UCFG_B0_P2_U0_DCFG3 0x40010466 +#define CYDEV_UCFG_B0_P2_U0_DCFG4 0x40010468 +#define CYDEV_UCFG_B0_P2_U0_DCFG5 0x4001046a +#define CYDEV_UCFG_B0_P2_U0_DCFG6 0x4001046c +#define CYDEV_UCFG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYDEV_UCFG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYDEV_UCFG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYDEV_UCFG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYDEV_UCFG_B0_P2_U1_CFG0 0x400104c0 +#define CYDEV_UCFG_B0_P2_U1_CFG1 0x400104c1 +#define CYDEV_UCFG_B0_P2_U1_CFG2 0x400104c2 +#define CYDEV_UCFG_B0_P2_U1_CFG3 0x400104c3 +#define CYDEV_UCFG_B0_P2_U1_CFG4 0x400104c4 +#define CYDEV_UCFG_B0_P2_U1_CFG5 0x400104c5 +#define CYDEV_UCFG_B0_P2_U1_CFG6 0x400104c6 +#define CYDEV_UCFG_B0_P2_U1_CFG7 0x400104c7 +#define CYDEV_UCFG_B0_P2_U1_CFG8 0x400104c8 +#define CYDEV_UCFG_B0_P2_U1_CFG9 0x400104c9 +#define CYDEV_UCFG_B0_P2_U1_CFG10 0x400104ca +#define CYDEV_UCFG_B0_P2_U1_CFG11 0x400104cb +#define CYDEV_UCFG_B0_P2_U1_CFG12 0x400104cc +#define CYDEV_UCFG_B0_P2_U1_CFG13 0x400104cd +#define CYDEV_UCFG_B0_P2_U1_CFG14 0x400104ce +#define CYDEV_UCFG_B0_P2_U1_CFG15 0x400104cf +#define CYDEV_UCFG_B0_P2_U1_CFG16 0x400104d0 +#define CYDEV_UCFG_B0_P2_U1_CFG17 0x400104d1 +#define CYDEV_UCFG_B0_P2_U1_CFG18 0x400104d2 +#define CYDEV_UCFG_B0_P2_U1_CFG19 0x400104d3 +#define CYDEV_UCFG_B0_P2_U1_CFG20 0x400104d4 +#define CYDEV_UCFG_B0_P2_U1_CFG21 0x400104d5 +#define CYDEV_UCFG_B0_P2_U1_CFG22 0x400104d6 +#define CYDEV_UCFG_B0_P2_U1_CFG23 0x400104d7 +#define CYDEV_UCFG_B0_P2_U1_CFG24 0x400104d8 +#define CYDEV_UCFG_B0_P2_U1_CFG25 0x400104d9 +#define CYDEV_UCFG_B0_P2_U1_CFG26 0x400104da +#define CYDEV_UCFG_B0_P2_U1_CFG27 0x400104db +#define CYDEV_UCFG_B0_P2_U1_CFG28 0x400104dc +#define CYDEV_UCFG_B0_P2_U1_CFG29 0x400104dd +#define CYDEV_UCFG_B0_P2_U1_CFG30 0x400104de +#define CYDEV_UCFG_B0_P2_U1_CFG31 0x400104df +#define CYDEV_UCFG_B0_P2_U1_DCFG0 0x400104e0 +#define CYDEV_UCFG_B0_P2_U1_DCFG1 0x400104e2 +#define CYDEV_UCFG_B0_P2_U1_DCFG2 0x400104e4 +#define CYDEV_UCFG_B0_P2_U1_DCFG3 0x400104e6 +#define CYDEV_UCFG_B0_P2_U1_DCFG4 0x400104e8 +#define CYDEV_UCFG_B0_P2_U1_DCFG5 0x400104ea +#define CYDEV_UCFG_B0_P2_U1_DCFG6 0x400104ec +#define CYDEV_UCFG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYDEV_UCFG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYDEV_UCFG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYDEV_UCFG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYDEV_UCFG_B0_P3_U0_CFG0 0x40010640 +#define CYDEV_UCFG_B0_P3_U0_CFG1 0x40010641 +#define CYDEV_UCFG_B0_P3_U0_CFG2 0x40010642 +#define CYDEV_UCFG_B0_P3_U0_CFG3 0x40010643 +#define CYDEV_UCFG_B0_P3_U0_CFG4 0x40010644 +#define CYDEV_UCFG_B0_P3_U0_CFG5 0x40010645 +#define CYDEV_UCFG_B0_P3_U0_CFG6 0x40010646 +#define CYDEV_UCFG_B0_P3_U0_CFG7 0x40010647 +#define CYDEV_UCFG_B0_P3_U0_CFG8 0x40010648 +#define CYDEV_UCFG_B0_P3_U0_CFG9 0x40010649 +#define CYDEV_UCFG_B0_P3_U0_CFG10 0x4001064a +#define CYDEV_UCFG_B0_P3_U0_CFG11 0x4001064b +#define CYDEV_UCFG_B0_P3_U0_CFG12 0x4001064c +#define CYDEV_UCFG_B0_P3_U0_CFG13 0x4001064d +#define CYDEV_UCFG_B0_P3_U0_CFG14 0x4001064e +#define CYDEV_UCFG_B0_P3_U0_CFG15 0x4001064f +#define CYDEV_UCFG_B0_P3_U0_CFG16 0x40010650 +#define CYDEV_UCFG_B0_P3_U0_CFG17 0x40010651 +#define CYDEV_UCFG_B0_P3_U0_CFG18 0x40010652 +#define CYDEV_UCFG_B0_P3_U0_CFG19 0x40010653 +#define CYDEV_UCFG_B0_P3_U0_CFG20 0x40010654 +#define CYDEV_UCFG_B0_P3_U0_CFG21 0x40010655 +#define CYDEV_UCFG_B0_P3_U0_CFG22 0x40010656 +#define CYDEV_UCFG_B0_P3_U0_CFG23 0x40010657 +#define CYDEV_UCFG_B0_P3_U0_CFG24 0x40010658 +#define CYDEV_UCFG_B0_P3_U0_CFG25 0x40010659 +#define CYDEV_UCFG_B0_P3_U0_CFG26 0x4001065a +#define CYDEV_UCFG_B0_P3_U0_CFG27 0x4001065b +#define CYDEV_UCFG_B0_P3_U0_CFG28 0x4001065c +#define CYDEV_UCFG_B0_P3_U0_CFG29 0x4001065d +#define CYDEV_UCFG_B0_P3_U0_CFG30 0x4001065e +#define CYDEV_UCFG_B0_P3_U0_CFG31 0x4001065f +#define CYDEV_UCFG_B0_P3_U0_DCFG0 0x40010660 +#define CYDEV_UCFG_B0_P3_U0_DCFG1 0x40010662 +#define CYDEV_UCFG_B0_P3_U0_DCFG2 0x40010664 +#define CYDEV_UCFG_B0_P3_U0_DCFG3 0x40010666 +#define CYDEV_UCFG_B0_P3_U0_DCFG4 0x40010668 +#define CYDEV_UCFG_B0_P3_U0_DCFG5 0x4001066a +#define CYDEV_UCFG_B0_P3_U0_DCFG6 0x4001066c +#define CYDEV_UCFG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYDEV_UCFG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYDEV_UCFG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYDEV_UCFG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYDEV_UCFG_B0_P3_U1_CFG0 0x400106c0 +#define CYDEV_UCFG_B0_P3_U1_CFG1 0x400106c1 +#define CYDEV_UCFG_B0_P3_U1_CFG2 0x400106c2 +#define CYDEV_UCFG_B0_P3_U1_CFG3 0x400106c3 +#define CYDEV_UCFG_B0_P3_U1_CFG4 0x400106c4 +#define CYDEV_UCFG_B0_P3_U1_CFG5 0x400106c5 +#define CYDEV_UCFG_B0_P3_U1_CFG6 0x400106c6 +#define CYDEV_UCFG_B0_P3_U1_CFG7 0x400106c7 +#define CYDEV_UCFG_B0_P3_U1_CFG8 0x400106c8 +#define CYDEV_UCFG_B0_P3_U1_CFG9 0x400106c9 +#define CYDEV_UCFG_B0_P3_U1_CFG10 0x400106ca +#define CYDEV_UCFG_B0_P3_U1_CFG11 0x400106cb +#define CYDEV_UCFG_B0_P3_U1_CFG12 0x400106cc +#define CYDEV_UCFG_B0_P3_U1_CFG13 0x400106cd +#define CYDEV_UCFG_B0_P3_U1_CFG14 0x400106ce +#define CYDEV_UCFG_B0_P3_U1_CFG15 0x400106cf +#define CYDEV_UCFG_B0_P3_U1_CFG16 0x400106d0 +#define CYDEV_UCFG_B0_P3_U1_CFG17 0x400106d1 +#define CYDEV_UCFG_B0_P3_U1_CFG18 0x400106d2 +#define CYDEV_UCFG_B0_P3_U1_CFG19 0x400106d3 +#define CYDEV_UCFG_B0_P3_U1_CFG20 0x400106d4 +#define CYDEV_UCFG_B0_P3_U1_CFG21 0x400106d5 +#define CYDEV_UCFG_B0_P3_U1_CFG22 0x400106d6 +#define CYDEV_UCFG_B0_P3_U1_CFG23 0x400106d7 +#define CYDEV_UCFG_B0_P3_U1_CFG24 0x400106d8 +#define CYDEV_UCFG_B0_P3_U1_CFG25 0x400106d9 +#define CYDEV_UCFG_B0_P3_U1_CFG26 0x400106da +#define CYDEV_UCFG_B0_P3_U1_CFG27 0x400106db +#define CYDEV_UCFG_B0_P3_U1_CFG28 0x400106dc +#define CYDEV_UCFG_B0_P3_U1_CFG29 0x400106dd +#define CYDEV_UCFG_B0_P3_U1_CFG30 0x400106de +#define CYDEV_UCFG_B0_P3_U1_CFG31 0x400106df +#define CYDEV_UCFG_B0_P3_U1_DCFG0 0x400106e0 +#define CYDEV_UCFG_B0_P3_U1_DCFG1 0x400106e2 +#define CYDEV_UCFG_B0_P3_U1_DCFG2 0x400106e4 +#define CYDEV_UCFG_B0_P3_U1_DCFG3 0x400106e6 +#define CYDEV_UCFG_B0_P3_U1_DCFG4 0x400106e8 +#define CYDEV_UCFG_B0_P3_U1_DCFG5 0x400106ea +#define CYDEV_UCFG_B0_P3_U1_DCFG6 0x400106ec +#define CYDEV_UCFG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYDEV_UCFG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYDEV_UCFG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYDEV_UCFG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYDEV_UCFG_B0_P4_U0_CFG0 0x40010840 +#define CYDEV_UCFG_B0_P4_U0_CFG1 0x40010841 +#define CYDEV_UCFG_B0_P4_U0_CFG2 0x40010842 +#define CYDEV_UCFG_B0_P4_U0_CFG3 0x40010843 +#define CYDEV_UCFG_B0_P4_U0_CFG4 0x40010844 +#define CYDEV_UCFG_B0_P4_U0_CFG5 0x40010845 +#define CYDEV_UCFG_B0_P4_U0_CFG6 0x40010846 +#define CYDEV_UCFG_B0_P4_U0_CFG7 0x40010847 +#define CYDEV_UCFG_B0_P4_U0_CFG8 0x40010848 +#define CYDEV_UCFG_B0_P4_U0_CFG9 0x40010849 +#define CYDEV_UCFG_B0_P4_U0_CFG10 0x4001084a +#define CYDEV_UCFG_B0_P4_U0_CFG11 0x4001084b +#define CYDEV_UCFG_B0_P4_U0_CFG12 0x4001084c +#define CYDEV_UCFG_B0_P4_U0_CFG13 0x4001084d +#define CYDEV_UCFG_B0_P4_U0_CFG14 0x4001084e +#define CYDEV_UCFG_B0_P4_U0_CFG15 0x4001084f +#define CYDEV_UCFG_B0_P4_U0_CFG16 0x40010850 +#define CYDEV_UCFG_B0_P4_U0_CFG17 0x40010851 +#define CYDEV_UCFG_B0_P4_U0_CFG18 0x40010852 +#define CYDEV_UCFG_B0_P4_U0_CFG19 0x40010853 +#define CYDEV_UCFG_B0_P4_U0_CFG20 0x40010854 +#define CYDEV_UCFG_B0_P4_U0_CFG21 0x40010855 +#define CYDEV_UCFG_B0_P4_U0_CFG22 0x40010856 +#define CYDEV_UCFG_B0_P4_U0_CFG23 0x40010857 +#define CYDEV_UCFG_B0_P4_U0_CFG24 0x40010858 +#define CYDEV_UCFG_B0_P4_U0_CFG25 0x40010859 +#define CYDEV_UCFG_B0_P4_U0_CFG26 0x4001085a +#define CYDEV_UCFG_B0_P4_U0_CFG27 0x4001085b +#define CYDEV_UCFG_B0_P4_U0_CFG28 0x4001085c +#define CYDEV_UCFG_B0_P4_U0_CFG29 0x4001085d +#define CYDEV_UCFG_B0_P4_U0_CFG30 0x4001085e +#define CYDEV_UCFG_B0_P4_U0_CFG31 0x4001085f +#define CYDEV_UCFG_B0_P4_U0_DCFG0 0x40010860 +#define CYDEV_UCFG_B0_P4_U0_DCFG1 0x40010862 +#define CYDEV_UCFG_B0_P4_U0_DCFG2 0x40010864 +#define CYDEV_UCFG_B0_P4_U0_DCFG3 0x40010866 +#define CYDEV_UCFG_B0_P4_U0_DCFG4 0x40010868 +#define CYDEV_UCFG_B0_P4_U0_DCFG5 0x4001086a +#define CYDEV_UCFG_B0_P4_U0_DCFG6 0x4001086c +#define CYDEV_UCFG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYDEV_UCFG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYDEV_UCFG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYDEV_UCFG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYDEV_UCFG_B0_P4_U1_CFG0 0x400108c0 +#define CYDEV_UCFG_B0_P4_U1_CFG1 0x400108c1 +#define CYDEV_UCFG_B0_P4_U1_CFG2 0x400108c2 +#define CYDEV_UCFG_B0_P4_U1_CFG3 0x400108c3 +#define CYDEV_UCFG_B0_P4_U1_CFG4 0x400108c4 +#define CYDEV_UCFG_B0_P4_U1_CFG5 0x400108c5 +#define CYDEV_UCFG_B0_P4_U1_CFG6 0x400108c6 +#define CYDEV_UCFG_B0_P4_U1_CFG7 0x400108c7 +#define CYDEV_UCFG_B0_P4_U1_CFG8 0x400108c8 +#define CYDEV_UCFG_B0_P4_U1_CFG9 0x400108c9 +#define CYDEV_UCFG_B0_P4_U1_CFG10 0x400108ca +#define CYDEV_UCFG_B0_P4_U1_CFG11 0x400108cb +#define CYDEV_UCFG_B0_P4_U1_CFG12 0x400108cc +#define CYDEV_UCFG_B0_P4_U1_CFG13 0x400108cd +#define CYDEV_UCFG_B0_P4_U1_CFG14 0x400108ce +#define CYDEV_UCFG_B0_P4_U1_CFG15 0x400108cf +#define CYDEV_UCFG_B0_P4_U1_CFG16 0x400108d0 +#define CYDEV_UCFG_B0_P4_U1_CFG17 0x400108d1 +#define CYDEV_UCFG_B0_P4_U1_CFG18 0x400108d2 +#define CYDEV_UCFG_B0_P4_U1_CFG19 0x400108d3 +#define CYDEV_UCFG_B0_P4_U1_CFG20 0x400108d4 +#define CYDEV_UCFG_B0_P4_U1_CFG21 0x400108d5 +#define CYDEV_UCFG_B0_P4_U1_CFG22 0x400108d6 +#define CYDEV_UCFG_B0_P4_U1_CFG23 0x400108d7 +#define CYDEV_UCFG_B0_P4_U1_CFG24 0x400108d8 +#define CYDEV_UCFG_B0_P4_U1_CFG25 0x400108d9 +#define CYDEV_UCFG_B0_P4_U1_CFG26 0x400108da +#define CYDEV_UCFG_B0_P4_U1_CFG27 0x400108db +#define CYDEV_UCFG_B0_P4_U1_CFG28 0x400108dc +#define CYDEV_UCFG_B0_P4_U1_CFG29 0x400108dd +#define CYDEV_UCFG_B0_P4_U1_CFG30 0x400108de +#define CYDEV_UCFG_B0_P4_U1_CFG31 0x400108df +#define CYDEV_UCFG_B0_P4_U1_DCFG0 0x400108e0 +#define CYDEV_UCFG_B0_P4_U1_DCFG1 0x400108e2 +#define CYDEV_UCFG_B0_P4_U1_DCFG2 0x400108e4 +#define CYDEV_UCFG_B0_P4_U1_DCFG3 0x400108e6 +#define CYDEV_UCFG_B0_P4_U1_DCFG4 0x400108e8 +#define CYDEV_UCFG_B0_P4_U1_DCFG5 0x400108ea +#define CYDEV_UCFG_B0_P4_U1_DCFG6 0x400108ec +#define CYDEV_UCFG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYDEV_UCFG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYDEV_UCFG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYDEV_UCFG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYDEV_UCFG_B0_P5_U0_CFG0 0x40010a40 +#define CYDEV_UCFG_B0_P5_U0_CFG1 0x40010a41 +#define CYDEV_UCFG_B0_P5_U0_CFG2 0x40010a42 +#define CYDEV_UCFG_B0_P5_U0_CFG3 0x40010a43 +#define CYDEV_UCFG_B0_P5_U0_CFG4 0x40010a44 +#define CYDEV_UCFG_B0_P5_U0_CFG5 0x40010a45 +#define CYDEV_UCFG_B0_P5_U0_CFG6 0x40010a46 +#define CYDEV_UCFG_B0_P5_U0_CFG7 0x40010a47 +#define CYDEV_UCFG_B0_P5_U0_CFG8 0x40010a48 +#define CYDEV_UCFG_B0_P5_U0_CFG9 0x40010a49 +#define CYDEV_UCFG_B0_P5_U0_CFG10 0x40010a4a +#define CYDEV_UCFG_B0_P5_U0_CFG11 0x40010a4b +#define CYDEV_UCFG_B0_P5_U0_CFG12 0x40010a4c +#define CYDEV_UCFG_B0_P5_U0_CFG13 0x40010a4d +#define CYDEV_UCFG_B0_P5_U0_CFG14 0x40010a4e +#define CYDEV_UCFG_B0_P5_U0_CFG15 0x40010a4f +#define CYDEV_UCFG_B0_P5_U0_CFG16 0x40010a50 +#define CYDEV_UCFG_B0_P5_U0_CFG17 0x40010a51 +#define CYDEV_UCFG_B0_P5_U0_CFG18 0x40010a52 +#define CYDEV_UCFG_B0_P5_U0_CFG19 0x40010a53 +#define CYDEV_UCFG_B0_P5_U0_CFG20 0x40010a54 +#define CYDEV_UCFG_B0_P5_U0_CFG21 0x40010a55 +#define CYDEV_UCFG_B0_P5_U0_CFG22 0x40010a56 +#define CYDEV_UCFG_B0_P5_U0_CFG23 0x40010a57 +#define CYDEV_UCFG_B0_P5_U0_CFG24 0x40010a58 +#define CYDEV_UCFG_B0_P5_U0_CFG25 0x40010a59 +#define CYDEV_UCFG_B0_P5_U0_CFG26 0x40010a5a +#define CYDEV_UCFG_B0_P5_U0_CFG27 0x40010a5b +#define CYDEV_UCFG_B0_P5_U0_CFG28 0x40010a5c +#define CYDEV_UCFG_B0_P5_U0_CFG29 0x40010a5d +#define CYDEV_UCFG_B0_P5_U0_CFG30 0x40010a5e +#define CYDEV_UCFG_B0_P5_U0_CFG31 0x40010a5f +#define CYDEV_UCFG_B0_P5_U0_DCFG0 0x40010a60 +#define CYDEV_UCFG_B0_P5_U0_DCFG1 0x40010a62 +#define CYDEV_UCFG_B0_P5_U0_DCFG2 0x40010a64 +#define CYDEV_UCFG_B0_P5_U0_DCFG3 0x40010a66 +#define CYDEV_UCFG_B0_P5_U0_DCFG4 0x40010a68 +#define CYDEV_UCFG_B0_P5_U0_DCFG5 0x40010a6a +#define CYDEV_UCFG_B0_P5_U0_DCFG6 0x40010a6c +#define CYDEV_UCFG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYDEV_UCFG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYDEV_UCFG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYDEV_UCFG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYDEV_UCFG_B0_P5_U1_CFG0 0x40010ac0 +#define CYDEV_UCFG_B0_P5_U1_CFG1 0x40010ac1 +#define CYDEV_UCFG_B0_P5_U1_CFG2 0x40010ac2 +#define CYDEV_UCFG_B0_P5_U1_CFG3 0x40010ac3 +#define CYDEV_UCFG_B0_P5_U1_CFG4 0x40010ac4 +#define CYDEV_UCFG_B0_P5_U1_CFG5 0x40010ac5 +#define CYDEV_UCFG_B0_P5_U1_CFG6 0x40010ac6 +#define CYDEV_UCFG_B0_P5_U1_CFG7 0x40010ac7 +#define CYDEV_UCFG_B0_P5_U1_CFG8 0x40010ac8 +#define CYDEV_UCFG_B0_P5_U1_CFG9 0x40010ac9 +#define CYDEV_UCFG_B0_P5_U1_CFG10 0x40010aca +#define CYDEV_UCFG_B0_P5_U1_CFG11 0x40010acb +#define CYDEV_UCFG_B0_P5_U1_CFG12 0x40010acc +#define CYDEV_UCFG_B0_P5_U1_CFG13 0x40010acd +#define CYDEV_UCFG_B0_P5_U1_CFG14 0x40010ace +#define CYDEV_UCFG_B0_P5_U1_CFG15 0x40010acf +#define CYDEV_UCFG_B0_P5_U1_CFG16 0x40010ad0 +#define CYDEV_UCFG_B0_P5_U1_CFG17 0x40010ad1 +#define CYDEV_UCFG_B0_P5_U1_CFG18 0x40010ad2 +#define CYDEV_UCFG_B0_P5_U1_CFG19 0x40010ad3 +#define CYDEV_UCFG_B0_P5_U1_CFG20 0x40010ad4 +#define CYDEV_UCFG_B0_P5_U1_CFG21 0x40010ad5 +#define CYDEV_UCFG_B0_P5_U1_CFG22 0x40010ad6 +#define CYDEV_UCFG_B0_P5_U1_CFG23 0x40010ad7 +#define CYDEV_UCFG_B0_P5_U1_CFG24 0x40010ad8 +#define CYDEV_UCFG_B0_P5_U1_CFG25 0x40010ad9 +#define CYDEV_UCFG_B0_P5_U1_CFG26 0x40010ada +#define CYDEV_UCFG_B0_P5_U1_CFG27 0x40010adb +#define CYDEV_UCFG_B0_P5_U1_CFG28 0x40010adc +#define CYDEV_UCFG_B0_P5_U1_CFG29 0x40010add +#define CYDEV_UCFG_B0_P5_U1_CFG30 0x40010ade +#define CYDEV_UCFG_B0_P5_U1_CFG31 0x40010adf +#define CYDEV_UCFG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYDEV_UCFG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYDEV_UCFG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYDEV_UCFG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYDEV_UCFG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYDEV_UCFG_B0_P5_U1_DCFG5 0x40010aea +#define CYDEV_UCFG_B0_P5_U1_DCFG6 0x40010aec +#define CYDEV_UCFG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYDEV_UCFG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYDEV_UCFG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYDEV_UCFG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYDEV_UCFG_B0_P6_U0_CFG0 0x40010c40 +#define CYDEV_UCFG_B0_P6_U0_CFG1 0x40010c41 +#define CYDEV_UCFG_B0_P6_U0_CFG2 0x40010c42 +#define CYDEV_UCFG_B0_P6_U0_CFG3 0x40010c43 +#define CYDEV_UCFG_B0_P6_U0_CFG4 0x40010c44 +#define CYDEV_UCFG_B0_P6_U0_CFG5 0x40010c45 +#define CYDEV_UCFG_B0_P6_U0_CFG6 0x40010c46 +#define CYDEV_UCFG_B0_P6_U0_CFG7 0x40010c47 +#define CYDEV_UCFG_B0_P6_U0_CFG8 0x40010c48 +#define CYDEV_UCFG_B0_P6_U0_CFG9 0x40010c49 +#define CYDEV_UCFG_B0_P6_U0_CFG10 0x40010c4a +#define CYDEV_UCFG_B0_P6_U0_CFG11 0x40010c4b +#define CYDEV_UCFG_B0_P6_U0_CFG12 0x40010c4c +#define CYDEV_UCFG_B0_P6_U0_CFG13 0x40010c4d +#define CYDEV_UCFG_B0_P6_U0_CFG14 0x40010c4e +#define CYDEV_UCFG_B0_P6_U0_CFG15 0x40010c4f +#define CYDEV_UCFG_B0_P6_U0_CFG16 0x40010c50 +#define CYDEV_UCFG_B0_P6_U0_CFG17 0x40010c51 +#define CYDEV_UCFG_B0_P6_U0_CFG18 0x40010c52 +#define CYDEV_UCFG_B0_P6_U0_CFG19 0x40010c53 +#define CYDEV_UCFG_B0_P6_U0_CFG20 0x40010c54 +#define CYDEV_UCFG_B0_P6_U0_CFG21 0x40010c55 +#define CYDEV_UCFG_B0_P6_U0_CFG22 0x40010c56 +#define CYDEV_UCFG_B0_P6_U0_CFG23 0x40010c57 +#define CYDEV_UCFG_B0_P6_U0_CFG24 0x40010c58 +#define CYDEV_UCFG_B0_P6_U0_CFG25 0x40010c59 +#define CYDEV_UCFG_B0_P6_U0_CFG26 0x40010c5a +#define CYDEV_UCFG_B0_P6_U0_CFG27 0x40010c5b +#define CYDEV_UCFG_B0_P6_U0_CFG28 0x40010c5c +#define CYDEV_UCFG_B0_P6_U0_CFG29 0x40010c5d +#define CYDEV_UCFG_B0_P6_U0_CFG30 0x40010c5e +#define CYDEV_UCFG_B0_P6_U0_CFG31 0x40010c5f +#define CYDEV_UCFG_B0_P6_U0_DCFG0 0x40010c60 +#define CYDEV_UCFG_B0_P6_U0_DCFG1 0x40010c62 +#define CYDEV_UCFG_B0_P6_U0_DCFG2 0x40010c64 +#define CYDEV_UCFG_B0_P6_U0_DCFG3 0x40010c66 +#define CYDEV_UCFG_B0_P6_U0_DCFG4 0x40010c68 +#define CYDEV_UCFG_B0_P6_U0_DCFG5 0x40010c6a +#define CYDEV_UCFG_B0_P6_U0_DCFG6 0x40010c6c +#define CYDEV_UCFG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYDEV_UCFG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYDEV_UCFG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYDEV_UCFG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYDEV_UCFG_B0_P6_U1_CFG0 0x40010cc0 +#define CYDEV_UCFG_B0_P6_U1_CFG1 0x40010cc1 +#define CYDEV_UCFG_B0_P6_U1_CFG2 0x40010cc2 +#define CYDEV_UCFG_B0_P6_U1_CFG3 0x40010cc3 +#define CYDEV_UCFG_B0_P6_U1_CFG4 0x40010cc4 +#define CYDEV_UCFG_B0_P6_U1_CFG5 0x40010cc5 +#define CYDEV_UCFG_B0_P6_U1_CFG6 0x40010cc6 +#define CYDEV_UCFG_B0_P6_U1_CFG7 0x40010cc7 +#define CYDEV_UCFG_B0_P6_U1_CFG8 0x40010cc8 +#define CYDEV_UCFG_B0_P6_U1_CFG9 0x40010cc9 +#define CYDEV_UCFG_B0_P6_U1_CFG10 0x40010cca +#define CYDEV_UCFG_B0_P6_U1_CFG11 0x40010ccb +#define CYDEV_UCFG_B0_P6_U1_CFG12 0x40010ccc +#define CYDEV_UCFG_B0_P6_U1_CFG13 0x40010ccd +#define CYDEV_UCFG_B0_P6_U1_CFG14 0x40010cce +#define CYDEV_UCFG_B0_P6_U1_CFG15 0x40010ccf +#define CYDEV_UCFG_B0_P6_U1_CFG16 0x40010cd0 +#define CYDEV_UCFG_B0_P6_U1_CFG17 0x40010cd1 +#define CYDEV_UCFG_B0_P6_U1_CFG18 0x40010cd2 +#define CYDEV_UCFG_B0_P6_U1_CFG19 0x40010cd3 +#define CYDEV_UCFG_B0_P6_U1_CFG20 0x40010cd4 +#define CYDEV_UCFG_B0_P6_U1_CFG21 0x40010cd5 +#define CYDEV_UCFG_B0_P6_U1_CFG22 0x40010cd6 +#define CYDEV_UCFG_B0_P6_U1_CFG23 0x40010cd7 +#define CYDEV_UCFG_B0_P6_U1_CFG24 0x40010cd8 +#define CYDEV_UCFG_B0_P6_U1_CFG25 0x40010cd9 +#define CYDEV_UCFG_B0_P6_U1_CFG26 0x40010cda +#define CYDEV_UCFG_B0_P6_U1_CFG27 0x40010cdb +#define CYDEV_UCFG_B0_P6_U1_CFG28 0x40010cdc +#define CYDEV_UCFG_B0_P6_U1_CFG29 0x40010cdd +#define CYDEV_UCFG_B0_P6_U1_CFG30 0x40010cde +#define CYDEV_UCFG_B0_P6_U1_CFG31 0x40010cdf +#define CYDEV_UCFG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYDEV_UCFG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYDEV_UCFG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYDEV_UCFG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYDEV_UCFG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYDEV_UCFG_B0_P6_U1_DCFG5 0x40010cea +#define CYDEV_UCFG_B0_P6_U1_DCFG6 0x40010cec +#define CYDEV_UCFG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYDEV_UCFG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYDEV_UCFG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYDEV_UCFG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYDEV_UCFG_B0_P7_U0_CFG0 0x40010e40 +#define CYDEV_UCFG_B0_P7_U0_CFG1 0x40010e41 +#define CYDEV_UCFG_B0_P7_U0_CFG2 0x40010e42 +#define CYDEV_UCFG_B0_P7_U0_CFG3 0x40010e43 +#define CYDEV_UCFG_B0_P7_U0_CFG4 0x40010e44 +#define CYDEV_UCFG_B0_P7_U0_CFG5 0x40010e45 +#define CYDEV_UCFG_B0_P7_U0_CFG6 0x40010e46 +#define CYDEV_UCFG_B0_P7_U0_CFG7 0x40010e47 +#define CYDEV_UCFG_B0_P7_U0_CFG8 0x40010e48 +#define CYDEV_UCFG_B0_P7_U0_CFG9 0x40010e49 +#define CYDEV_UCFG_B0_P7_U0_CFG10 0x40010e4a +#define CYDEV_UCFG_B0_P7_U0_CFG11 0x40010e4b +#define CYDEV_UCFG_B0_P7_U0_CFG12 0x40010e4c +#define CYDEV_UCFG_B0_P7_U0_CFG13 0x40010e4d +#define CYDEV_UCFG_B0_P7_U0_CFG14 0x40010e4e +#define CYDEV_UCFG_B0_P7_U0_CFG15 0x40010e4f +#define CYDEV_UCFG_B0_P7_U0_CFG16 0x40010e50 +#define CYDEV_UCFG_B0_P7_U0_CFG17 0x40010e51 +#define CYDEV_UCFG_B0_P7_U0_CFG18 0x40010e52 +#define CYDEV_UCFG_B0_P7_U0_CFG19 0x40010e53 +#define CYDEV_UCFG_B0_P7_U0_CFG20 0x40010e54 +#define CYDEV_UCFG_B0_P7_U0_CFG21 0x40010e55 +#define CYDEV_UCFG_B0_P7_U0_CFG22 0x40010e56 +#define CYDEV_UCFG_B0_P7_U0_CFG23 0x40010e57 +#define CYDEV_UCFG_B0_P7_U0_CFG24 0x40010e58 +#define CYDEV_UCFG_B0_P7_U0_CFG25 0x40010e59 +#define CYDEV_UCFG_B0_P7_U0_CFG26 0x40010e5a +#define CYDEV_UCFG_B0_P7_U0_CFG27 0x40010e5b +#define CYDEV_UCFG_B0_P7_U0_CFG28 0x40010e5c +#define CYDEV_UCFG_B0_P7_U0_CFG29 0x40010e5d +#define CYDEV_UCFG_B0_P7_U0_CFG30 0x40010e5e +#define CYDEV_UCFG_B0_P7_U0_CFG31 0x40010e5f +#define CYDEV_UCFG_B0_P7_U0_DCFG0 0x40010e60 +#define CYDEV_UCFG_B0_P7_U0_DCFG1 0x40010e62 +#define CYDEV_UCFG_B0_P7_U0_DCFG2 0x40010e64 +#define CYDEV_UCFG_B0_P7_U0_DCFG3 0x40010e66 +#define CYDEV_UCFG_B0_P7_U0_DCFG4 0x40010e68 +#define CYDEV_UCFG_B0_P7_U0_DCFG5 0x40010e6a +#define CYDEV_UCFG_B0_P7_U0_DCFG6 0x40010e6c +#define CYDEV_UCFG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYDEV_UCFG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYDEV_UCFG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYDEV_UCFG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYDEV_UCFG_B0_P7_U1_CFG0 0x40010ec0 +#define CYDEV_UCFG_B0_P7_U1_CFG1 0x40010ec1 +#define CYDEV_UCFG_B0_P7_U1_CFG2 0x40010ec2 +#define CYDEV_UCFG_B0_P7_U1_CFG3 0x40010ec3 +#define CYDEV_UCFG_B0_P7_U1_CFG4 0x40010ec4 +#define CYDEV_UCFG_B0_P7_U1_CFG5 0x40010ec5 +#define CYDEV_UCFG_B0_P7_U1_CFG6 0x40010ec6 +#define CYDEV_UCFG_B0_P7_U1_CFG7 0x40010ec7 +#define CYDEV_UCFG_B0_P7_U1_CFG8 0x40010ec8 +#define CYDEV_UCFG_B0_P7_U1_CFG9 0x40010ec9 +#define CYDEV_UCFG_B0_P7_U1_CFG10 0x40010eca +#define CYDEV_UCFG_B0_P7_U1_CFG11 0x40010ecb +#define CYDEV_UCFG_B0_P7_U1_CFG12 0x40010ecc +#define CYDEV_UCFG_B0_P7_U1_CFG13 0x40010ecd +#define CYDEV_UCFG_B0_P7_U1_CFG14 0x40010ece +#define CYDEV_UCFG_B0_P7_U1_CFG15 0x40010ecf +#define CYDEV_UCFG_B0_P7_U1_CFG16 0x40010ed0 +#define CYDEV_UCFG_B0_P7_U1_CFG17 0x40010ed1 +#define CYDEV_UCFG_B0_P7_U1_CFG18 0x40010ed2 +#define CYDEV_UCFG_B0_P7_U1_CFG19 0x40010ed3 +#define CYDEV_UCFG_B0_P7_U1_CFG20 0x40010ed4 +#define CYDEV_UCFG_B0_P7_U1_CFG21 0x40010ed5 +#define CYDEV_UCFG_B0_P7_U1_CFG22 0x40010ed6 +#define CYDEV_UCFG_B0_P7_U1_CFG23 0x40010ed7 +#define CYDEV_UCFG_B0_P7_U1_CFG24 0x40010ed8 +#define CYDEV_UCFG_B0_P7_U1_CFG25 0x40010ed9 +#define CYDEV_UCFG_B0_P7_U1_CFG26 0x40010eda +#define CYDEV_UCFG_B0_P7_U1_CFG27 0x40010edb +#define CYDEV_UCFG_B0_P7_U1_CFG28 0x40010edc +#define CYDEV_UCFG_B0_P7_U1_CFG29 0x40010edd +#define CYDEV_UCFG_B0_P7_U1_CFG30 0x40010ede +#define CYDEV_UCFG_B0_P7_U1_CFG31 0x40010edf +#define CYDEV_UCFG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYDEV_UCFG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYDEV_UCFG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYDEV_UCFG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYDEV_UCFG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYDEV_UCFG_B0_P7_U1_DCFG5 0x40010eea +#define CYDEV_UCFG_B0_P7_U1_DCFG6 0x40010eec +#define CYDEV_UCFG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYDEV_UCFG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYDEV_UCFG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYDEV_UCFG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYDEV_UCFG_B1_P2_U0_CFG0 0x40011440 +#define CYDEV_UCFG_B1_P2_U0_CFG1 0x40011441 +#define CYDEV_UCFG_B1_P2_U0_CFG2 0x40011442 +#define CYDEV_UCFG_B1_P2_U0_CFG3 0x40011443 +#define CYDEV_UCFG_B1_P2_U0_CFG4 0x40011444 +#define CYDEV_UCFG_B1_P2_U0_CFG5 0x40011445 +#define CYDEV_UCFG_B1_P2_U0_CFG6 0x40011446 +#define CYDEV_UCFG_B1_P2_U0_CFG7 0x40011447 +#define CYDEV_UCFG_B1_P2_U0_CFG8 0x40011448 +#define CYDEV_UCFG_B1_P2_U0_CFG9 0x40011449 +#define CYDEV_UCFG_B1_P2_U0_CFG10 0x4001144a +#define CYDEV_UCFG_B1_P2_U0_CFG11 0x4001144b +#define CYDEV_UCFG_B1_P2_U0_CFG12 0x4001144c +#define CYDEV_UCFG_B1_P2_U0_CFG13 0x4001144d +#define CYDEV_UCFG_B1_P2_U0_CFG14 0x4001144e +#define CYDEV_UCFG_B1_P2_U0_CFG15 0x4001144f +#define CYDEV_UCFG_B1_P2_U0_CFG16 0x40011450 +#define CYDEV_UCFG_B1_P2_U0_CFG17 0x40011451 +#define CYDEV_UCFG_B1_P2_U0_CFG18 0x40011452 +#define CYDEV_UCFG_B1_P2_U0_CFG19 0x40011453 +#define CYDEV_UCFG_B1_P2_U0_CFG20 0x40011454 +#define CYDEV_UCFG_B1_P2_U0_CFG21 0x40011455 +#define CYDEV_UCFG_B1_P2_U0_CFG22 0x40011456 +#define CYDEV_UCFG_B1_P2_U0_CFG23 0x40011457 +#define CYDEV_UCFG_B1_P2_U0_CFG24 0x40011458 +#define CYDEV_UCFG_B1_P2_U0_CFG25 0x40011459 +#define CYDEV_UCFG_B1_P2_U0_CFG26 0x4001145a +#define CYDEV_UCFG_B1_P2_U0_CFG27 0x4001145b +#define CYDEV_UCFG_B1_P2_U0_CFG28 0x4001145c +#define CYDEV_UCFG_B1_P2_U0_CFG29 0x4001145d +#define CYDEV_UCFG_B1_P2_U0_CFG30 0x4001145e +#define CYDEV_UCFG_B1_P2_U0_CFG31 0x4001145f +#define CYDEV_UCFG_B1_P2_U0_DCFG0 0x40011460 +#define CYDEV_UCFG_B1_P2_U0_DCFG1 0x40011462 +#define CYDEV_UCFG_B1_P2_U0_DCFG2 0x40011464 +#define CYDEV_UCFG_B1_P2_U0_DCFG3 0x40011466 +#define CYDEV_UCFG_B1_P2_U0_DCFG4 0x40011468 +#define CYDEV_UCFG_B1_P2_U0_DCFG5 0x4001146a +#define CYDEV_UCFG_B1_P2_U0_DCFG6 0x4001146c +#define CYDEV_UCFG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYDEV_UCFG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYDEV_UCFG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYDEV_UCFG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYDEV_UCFG_B1_P2_U1_CFG0 0x400114c0 +#define CYDEV_UCFG_B1_P2_U1_CFG1 0x400114c1 +#define CYDEV_UCFG_B1_P2_U1_CFG2 0x400114c2 +#define CYDEV_UCFG_B1_P2_U1_CFG3 0x400114c3 +#define CYDEV_UCFG_B1_P2_U1_CFG4 0x400114c4 +#define CYDEV_UCFG_B1_P2_U1_CFG5 0x400114c5 +#define CYDEV_UCFG_B1_P2_U1_CFG6 0x400114c6 +#define CYDEV_UCFG_B1_P2_U1_CFG7 0x400114c7 +#define CYDEV_UCFG_B1_P2_U1_CFG8 0x400114c8 +#define CYDEV_UCFG_B1_P2_U1_CFG9 0x400114c9 +#define CYDEV_UCFG_B1_P2_U1_CFG10 0x400114ca +#define CYDEV_UCFG_B1_P2_U1_CFG11 0x400114cb +#define CYDEV_UCFG_B1_P2_U1_CFG12 0x400114cc +#define CYDEV_UCFG_B1_P2_U1_CFG13 0x400114cd +#define CYDEV_UCFG_B1_P2_U1_CFG14 0x400114ce +#define CYDEV_UCFG_B1_P2_U1_CFG15 0x400114cf +#define CYDEV_UCFG_B1_P2_U1_CFG16 0x400114d0 +#define CYDEV_UCFG_B1_P2_U1_CFG17 0x400114d1 +#define CYDEV_UCFG_B1_P2_U1_CFG18 0x400114d2 +#define CYDEV_UCFG_B1_P2_U1_CFG19 0x400114d3 +#define CYDEV_UCFG_B1_P2_U1_CFG20 0x400114d4 +#define CYDEV_UCFG_B1_P2_U1_CFG21 0x400114d5 +#define CYDEV_UCFG_B1_P2_U1_CFG22 0x400114d6 +#define CYDEV_UCFG_B1_P2_U1_CFG23 0x400114d7 +#define CYDEV_UCFG_B1_P2_U1_CFG24 0x400114d8 +#define CYDEV_UCFG_B1_P2_U1_CFG25 0x400114d9 +#define CYDEV_UCFG_B1_P2_U1_CFG26 0x400114da +#define CYDEV_UCFG_B1_P2_U1_CFG27 0x400114db +#define CYDEV_UCFG_B1_P2_U1_CFG28 0x400114dc +#define CYDEV_UCFG_B1_P2_U1_CFG29 0x400114dd +#define CYDEV_UCFG_B1_P2_U1_CFG30 0x400114de +#define CYDEV_UCFG_B1_P2_U1_CFG31 0x400114df +#define CYDEV_UCFG_B1_P2_U1_DCFG0 0x400114e0 +#define CYDEV_UCFG_B1_P2_U1_DCFG1 0x400114e2 +#define CYDEV_UCFG_B1_P2_U1_DCFG2 0x400114e4 +#define CYDEV_UCFG_B1_P2_U1_DCFG3 0x400114e6 +#define CYDEV_UCFG_B1_P2_U1_DCFG4 0x400114e8 +#define CYDEV_UCFG_B1_P2_U1_DCFG5 0x400114ea +#define CYDEV_UCFG_B1_P2_U1_DCFG6 0x400114ec +#define CYDEV_UCFG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYDEV_UCFG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYDEV_UCFG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYDEV_UCFG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYDEV_UCFG_B1_P3_U0_CFG0 0x40011640 +#define CYDEV_UCFG_B1_P3_U0_CFG1 0x40011641 +#define CYDEV_UCFG_B1_P3_U0_CFG2 0x40011642 +#define CYDEV_UCFG_B1_P3_U0_CFG3 0x40011643 +#define CYDEV_UCFG_B1_P3_U0_CFG4 0x40011644 +#define CYDEV_UCFG_B1_P3_U0_CFG5 0x40011645 +#define CYDEV_UCFG_B1_P3_U0_CFG6 0x40011646 +#define CYDEV_UCFG_B1_P3_U0_CFG7 0x40011647 +#define CYDEV_UCFG_B1_P3_U0_CFG8 0x40011648 +#define CYDEV_UCFG_B1_P3_U0_CFG9 0x40011649 +#define CYDEV_UCFG_B1_P3_U0_CFG10 0x4001164a +#define CYDEV_UCFG_B1_P3_U0_CFG11 0x4001164b +#define CYDEV_UCFG_B1_P3_U0_CFG12 0x4001164c +#define CYDEV_UCFG_B1_P3_U0_CFG13 0x4001164d +#define CYDEV_UCFG_B1_P3_U0_CFG14 0x4001164e +#define CYDEV_UCFG_B1_P3_U0_CFG15 0x4001164f +#define CYDEV_UCFG_B1_P3_U0_CFG16 0x40011650 +#define CYDEV_UCFG_B1_P3_U0_CFG17 0x40011651 +#define CYDEV_UCFG_B1_P3_U0_CFG18 0x40011652 +#define CYDEV_UCFG_B1_P3_U0_CFG19 0x40011653 +#define CYDEV_UCFG_B1_P3_U0_CFG20 0x40011654 +#define CYDEV_UCFG_B1_P3_U0_CFG21 0x40011655 +#define CYDEV_UCFG_B1_P3_U0_CFG22 0x40011656 +#define CYDEV_UCFG_B1_P3_U0_CFG23 0x40011657 +#define CYDEV_UCFG_B1_P3_U0_CFG24 0x40011658 +#define CYDEV_UCFG_B1_P3_U0_CFG25 0x40011659 +#define CYDEV_UCFG_B1_P3_U0_CFG26 0x4001165a +#define CYDEV_UCFG_B1_P3_U0_CFG27 0x4001165b +#define CYDEV_UCFG_B1_P3_U0_CFG28 0x4001165c +#define CYDEV_UCFG_B1_P3_U0_CFG29 0x4001165d +#define CYDEV_UCFG_B1_P3_U0_CFG30 0x4001165e +#define CYDEV_UCFG_B1_P3_U0_CFG31 0x4001165f +#define CYDEV_UCFG_B1_P3_U0_DCFG0 0x40011660 +#define CYDEV_UCFG_B1_P3_U0_DCFG1 0x40011662 +#define CYDEV_UCFG_B1_P3_U0_DCFG2 0x40011664 +#define CYDEV_UCFG_B1_P3_U0_DCFG3 0x40011666 +#define CYDEV_UCFG_B1_P3_U0_DCFG4 0x40011668 +#define CYDEV_UCFG_B1_P3_U0_DCFG5 0x4001166a +#define CYDEV_UCFG_B1_P3_U0_DCFG6 0x4001166c +#define CYDEV_UCFG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYDEV_UCFG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYDEV_UCFG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYDEV_UCFG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYDEV_UCFG_B1_P3_U1_CFG0 0x400116c0 +#define CYDEV_UCFG_B1_P3_U1_CFG1 0x400116c1 +#define CYDEV_UCFG_B1_P3_U1_CFG2 0x400116c2 +#define CYDEV_UCFG_B1_P3_U1_CFG3 0x400116c3 +#define CYDEV_UCFG_B1_P3_U1_CFG4 0x400116c4 +#define CYDEV_UCFG_B1_P3_U1_CFG5 0x400116c5 +#define CYDEV_UCFG_B1_P3_U1_CFG6 0x400116c6 +#define CYDEV_UCFG_B1_P3_U1_CFG7 0x400116c7 +#define CYDEV_UCFG_B1_P3_U1_CFG8 0x400116c8 +#define CYDEV_UCFG_B1_P3_U1_CFG9 0x400116c9 +#define CYDEV_UCFG_B1_P3_U1_CFG10 0x400116ca +#define CYDEV_UCFG_B1_P3_U1_CFG11 0x400116cb +#define CYDEV_UCFG_B1_P3_U1_CFG12 0x400116cc +#define CYDEV_UCFG_B1_P3_U1_CFG13 0x400116cd +#define CYDEV_UCFG_B1_P3_U1_CFG14 0x400116ce +#define CYDEV_UCFG_B1_P3_U1_CFG15 0x400116cf +#define CYDEV_UCFG_B1_P3_U1_CFG16 0x400116d0 +#define CYDEV_UCFG_B1_P3_U1_CFG17 0x400116d1 +#define CYDEV_UCFG_B1_P3_U1_CFG18 0x400116d2 +#define CYDEV_UCFG_B1_P3_U1_CFG19 0x400116d3 +#define CYDEV_UCFG_B1_P3_U1_CFG20 0x400116d4 +#define CYDEV_UCFG_B1_P3_U1_CFG21 0x400116d5 +#define CYDEV_UCFG_B1_P3_U1_CFG22 0x400116d6 +#define CYDEV_UCFG_B1_P3_U1_CFG23 0x400116d7 +#define CYDEV_UCFG_B1_P3_U1_CFG24 0x400116d8 +#define CYDEV_UCFG_B1_P3_U1_CFG25 0x400116d9 +#define CYDEV_UCFG_B1_P3_U1_CFG26 0x400116da +#define CYDEV_UCFG_B1_P3_U1_CFG27 0x400116db +#define CYDEV_UCFG_B1_P3_U1_CFG28 0x400116dc +#define CYDEV_UCFG_B1_P3_U1_CFG29 0x400116dd +#define CYDEV_UCFG_B1_P3_U1_CFG30 0x400116de +#define CYDEV_UCFG_B1_P3_U1_CFG31 0x400116df +#define CYDEV_UCFG_B1_P3_U1_DCFG0 0x400116e0 +#define CYDEV_UCFG_B1_P3_U1_DCFG1 0x400116e2 +#define CYDEV_UCFG_B1_P3_U1_DCFG2 0x400116e4 +#define CYDEV_UCFG_B1_P3_U1_DCFG3 0x400116e6 +#define CYDEV_UCFG_B1_P3_U1_DCFG4 0x400116e8 +#define CYDEV_UCFG_B1_P3_U1_DCFG5 0x400116ea +#define CYDEV_UCFG_B1_P3_U1_DCFG6 0x400116ec +#define CYDEV_UCFG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYDEV_UCFG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYDEV_UCFG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYDEV_UCFG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYDEV_UCFG_B1_P4_U0_CFG0 0x40011840 +#define CYDEV_UCFG_B1_P4_U0_CFG1 0x40011841 +#define CYDEV_UCFG_B1_P4_U0_CFG2 0x40011842 +#define CYDEV_UCFG_B1_P4_U0_CFG3 0x40011843 +#define CYDEV_UCFG_B1_P4_U0_CFG4 0x40011844 +#define CYDEV_UCFG_B1_P4_U0_CFG5 0x40011845 +#define CYDEV_UCFG_B1_P4_U0_CFG6 0x40011846 +#define CYDEV_UCFG_B1_P4_U0_CFG7 0x40011847 +#define CYDEV_UCFG_B1_P4_U0_CFG8 0x40011848 +#define CYDEV_UCFG_B1_P4_U0_CFG9 0x40011849 +#define CYDEV_UCFG_B1_P4_U0_CFG10 0x4001184a +#define CYDEV_UCFG_B1_P4_U0_CFG11 0x4001184b +#define CYDEV_UCFG_B1_P4_U0_CFG12 0x4001184c +#define CYDEV_UCFG_B1_P4_U0_CFG13 0x4001184d +#define CYDEV_UCFG_B1_P4_U0_CFG14 0x4001184e +#define CYDEV_UCFG_B1_P4_U0_CFG15 0x4001184f +#define CYDEV_UCFG_B1_P4_U0_CFG16 0x40011850 +#define CYDEV_UCFG_B1_P4_U0_CFG17 0x40011851 +#define CYDEV_UCFG_B1_P4_U0_CFG18 0x40011852 +#define CYDEV_UCFG_B1_P4_U0_CFG19 0x40011853 +#define CYDEV_UCFG_B1_P4_U0_CFG20 0x40011854 +#define CYDEV_UCFG_B1_P4_U0_CFG21 0x40011855 +#define CYDEV_UCFG_B1_P4_U0_CFG22 0x40011856 +#define CYDEV_UCFG_B1_P4_U0_CFG23 0x40011857 +#define CYDEV_UCFG_B1_P4_U0_CFG24 0x40011858 +#define CYDEV_UCFG_B1_P4_U0_CFG25 0x40011859 +#define CYDEV_UCFG_B1_P4_U0_CFG26 0x4001185a +#define CYDEV_UCFG_B1_P4_U0_CFG27 0x4001185b +#define CYDEV_UCFG_B1_P4_U0_CFG28 0x4001185c +#define CYDEV_UCFG_B1_P4_U0_CFG29 0x4001185d +#define CYDEV_UCFG_B1_P4_U0_CFG30 0x4001185e +#define CYDEV_UCFG_B1_P4_U0_CFG31 0x4001185f +#define CYDEV_UCFG_B1_P4_U0_DCFG0 0x40011860 +#define CYDEV_UCFG_B1_P4_U0_DCFG1 0x40011862 +#define CYDEV_UCFG_B1_P4_U0_DCFG2 0x40011864 +#define CYDEV_UCFG_B1_P4_U0_DCFG3 0x40011866 +#define CYDEV_UCFG_B1_P4_U0_DCFG4 0x40011868 +#define CYDEV_UCFG_B1_P4_U0_DCFG5 0x4001186a +#define CYDEV_UCFG_B1_P4_U0_DCFG6 0x4001186c +#define CYDEV_UCFG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYDEV_UCFG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYDEV_UCFG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYDEV_UCFG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYDEV_UCFG_B1_P4_U1_CFG0 0x400118c0 +#define CYDEV_UCFG_B1_P4_U1_CFG1 0x400118c1 +#define CYDEV_UCFG_B1_P4_U1_CFG2 0x400118c2 +#define CYDEV_UCFG_B1_P4_U1_CFG3 0x400118c3 +#define CYDEV_UCFG_B1_P4_U1_CFG4 0x400118c4 +#define CYDEV_UCFG_B1_P4_U1_CFG5 0x400118c5 +#define CYDEV_UCFG_B1_P4_U1_CFG6 0x400118c6 +#define CYDEV_UCFG_B1_P4_U1_CFG7 0x400118c7 +#define CYDEV_UCFG_B1_P4_U1_CFG8 0x400118c8 +#define CYDEV_UCFG_B1_P4_U1_CFG9 0x400118c9 +#define CYDEV_UCFG_B1_P4_U1_CFG10 0x400118ca +#define CYDEV_UCFG_B1_P4_U1_CFG11 0x400118cb +#define CYDEV_UCFG_B1_P4_U1_CFG12 0x400118cc +#define CYDEV_UCFG_B1_P4_U1_CFG13 0x400118cd +#define CYDEV_UCFG_B1_P4_U1_CFG14 0x400118ce +#define CYDEV_UCFG_B1_P4_U1_CFG15 0x400118cf +#define CYDEV_UCFG_B1_P4_U1_CFG16 0x400118d0 +#define CYDEV_UCFG_B1_P4_U1_CFG17 0x400118d1 +#define CYDEV_UCFG_B1_P4_U1_CFG18 0x400118d2 +#define CYDEV_UCFG_B1_P4_U1_CFG19 0x400118d3 +#define CYDEV_UCFG_B1_P4_U1_CFG20 0x400118d4 +#define CYDEV_UCFG_B1_P4_U1_CFG21 0x400118d5 +#define CYDEV_UCFG_B1_P4_U1_CFG22 0x400118d6 +#define CYDEV_UCFG_B1_P4_U1_CFG23 0x400118d7 +#define CYDEV_UCFG_B1_P4_U1_CFG24 0x400118d8 +#define CYDEV_UCFG_B1_P4_U1_CFG25 0x400118d9 +#define CYDEV_UCFG_B1_P4_U1_CFG26 0x400118da +#define CYDEV_UCFG_B1_P4_U1_CFG27 0x400118db +#define CYDEV_UCFG_B1_P4_U1_CFG28 0x400118dc +#define CYDEV_UCFG_B1_P4_U1_CFG29 0x400118dd +#define CYDEV_UCFG_B1_P4_U1_CFG30 0x400118de +#define CYDEV_UCFG_B1_P4_U1_CFG31 0x400118df +#define CYDEV_UCFG_B1_P4_U1_DCFG0 0x400118e0 +#define CYDEV_UCFG_B1_P4_U1_DCFG1 0x400118e2 +#define CYDEV_UCFG_B1_P4_U1_DCFG2 0x400118e4 +#define CYDEV_UCFG_B1_P4_U1_DCFG3 0x400118e6 +#define CYDEV_UCFG_B1_P4_U1_DCFG4 0x400118e8 +#define CYDEV_UCFG_B1_P4_U1_DCFG5 0x400118ea +#define CYDEV_UCFG_B1_P4_U1_DCFG6 0x400118ec +#define CYDEV_UCFG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYDEV_UCFG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYDEV_UCFG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYDEV_UCFG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYDEV_UCFG_B1_P5_U0_CFG0 0x40011a40 +#define CYDEV_UCFG_B1_P5_U0_CFG1 0x40011a41 +#define CYDEV_UCFG_B1_P5_U0_CFG2 0x40011a42 +#define CYDEV_UCFG_B1_P5_U0_CFG3 0x40011a43 +#define CYDEV_UCFG_B1_P5_U0_CFG4 0x40011a44 +#define CYDEV_UCFG_B1_P5_U0_CFG5 0x40011a45 +#define CYDEV_UCFG_B1_P5_U0_CFG6 0x40011a46 +#define CYDEV_UCFG_B1_P5_U0_CFG7 0x40011a47 +#define CYDEV_UCFG_B1_P5_U0_CFG8 0x40011a48 +#define CYDEV_UCFG_B1_P5_U0_CFG9 0x40011a49 +#define CYDEV_UCFG_B1_P5_U0_CFG10 0x40011a4a +#define CYDEV_UCFG_B1_P5_U0_CFG11 0x40011a4b +#define CYDEV_UCFG_B1_P5_U0_CFG12 0x40011a4c +#define CYDEV_UCFG_B1_P5_U0_CFG13 0x40011a4d +#define CYDEV_UCFG_B1_P5_U0_CFG14 0x40011a4e +#define CYDEV_UCFG_B1_P5_U0_CFG15 0x40011a4f +#define CYDEV_UCFG_B1_P5_U0_CFG16 0x40011a50 +#define CYDEV_UCFG_B1_P5_U0_CFG17 0x40011a51 +#define CYDEV_UCFG_B1_P5_U0_CFG18 0x40011a52 +#define CYDEV_UCFG_B1_P5_U0_CFG19 0x40011a53 +#define CYDEV_UCFG_B1_P5_U0_CFG20 0x40011a54 +#define CYDEV_UCFG_B1_P5_U0_CFG21 0x40011a55 +#define CYDEV_UCFG_B1_P5_U0_CFG22 0x40011a56 +#define CYDEV_UCFG_B1_P5_U0_CFG23 0x40011a57 +#define CYDEV_UCFG_B1_P5_U0_CFG24 0x40011a58 +#define CYDEV_UCFG_B1_P5_U0_CFG25 0x40011a59 +#define CYDEV_UCFG_B1_P5_U0_CFG26 0x40011a5a +#define CYDEV_UCFG_B1_P5_U0_CFG27 0x40011a5b +#define CYDEV_UCFG_B1_P5_U0_CFG28 0x40011a5c +#define CYDEV_UCFG_B1_P5_U0_CFG29 0x40011a5d +#define CYDEV_UCFG_B1_P5_U0_CFG30 0x40011a5e +#define CYDEV_UCFG_B1_P5_U0_CFG31 0x40011a5f +#define CYDEV_UCFG_B1_P5_U0_DCFG0 0x40011a60 +#define CYDEV_UCFG_B1_P5_U0_DCFG1 0x40011a62 +#define CYDEV_UCFG_B1_P5_U0_DCFG2 0x40011a64 +#define CYDEV_UCFG_B1_P5_U0_DCFG3 0x40011a66 +#define CYDEV_UCFG_B1_P5_U0_DCFG4 0x40011a68 +#define CYDEV_UCFG_B1_P5_U0_DCFG5 0x40011a6a +#define CYDEV_UCFG_B1_P5_U0_DCFG6 0x40011a6c +#define CYDEV_UCFG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYDEV_UCFG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYDEV_UCFG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYDEV_UCFG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYDEV_UCFG_B1_P5_U1_CFG0 0x40011ac0 +#define CYDEV_UCFG_B1_P5_U1_CFG1 0x40011ac1 +#define CYDEV_UCFG_B1_P5_U1_CFG2 0x40011ac2 +#define CYDEV_UCFG_B1_P5_U1_CFG3 0x40011ac3 +#define CYDEV_UCFG_B1_P5_U1_CFG4 0x40011ac4 +#define CYDEV_UCFG_B1_P5_U1_CFG5 0x40011ac5 +#define CYDEV_UCFG_B1_P5_U1_CFG6 0x40011ac6 +#define CYDEV_UCFG_B1_P5_U1_CFG7 0x40011ac7 +#define CYDEV_UCFG_B1_P5_U1_CFG8 0x40011ac8 +#define CYDEV_UCFG_B1_P5_U1_CFG9 0x40011ac9 +#define CYDEV_UCFG_B1_P5_U1_CFG10 0x40011aca +#define CYDEV_UCFG_B1_P5_U1_CFG11 0x40011acb +#define CYDEV_UCFG_B1_P5_U1_CFG12 0x40011acc +#define CYDEV_UCFG_B1_P5_U1_CFG13 0x40011acd +#define CYDEV_UCFG_B1_P5_U1_CFG14 0x40011ace +#define CYDEV_UCFG_B1_P5_U1_CFG15 0x40011acf +#define CYDEV_UCFG_B1_P5_U1_CFG16 0x40011ad0 +#define CYDEV_UCFG_B1_P5_U1_CFG17 0x40011ad1 +#define CYDEV_UCFG_B1_P5_U1_CFG18 0x40011ad2 +#define CYDEV_UCFG_B1_P5_U1_CFG19 0x40011ad3 +#define CYDEV_UCFG_B1_P5_U1_CFG20 0x40011ad4 +#define CYDEV_UCFG_B1_P5_U1_CFG21 0x40011ad5 +#define CYDEV_UCFG_B1_P5_U1_CFG22 0x40011ad6 +#define CYDEV_UCFG_B1_P5_U1_CFG23 0x40011ad7 +#define CYDEV_UCFG_B1_P5_U1_CFG24 0x40011ad8 +#define CYDEV_UCFG_B1_P5_U1_CFG25 0x40011ad9 +#define CYDEV_UCFG_B1_P5_U1_CFG26 0x40011ada +#define CYDEV_UCFG_B1_P5_U1_CFG27 0x40011adb +#define CYDEV_UCFG_B1_P5_U1_CFG28 0x40011adc +#define CYDEV_UCFG_B1_P5_U1_CFG29 0x40011add +#define CYDEV_UCFG_B1_P5_U1_CFG30 0x40011ade +#define CYDEV_UCFG_B1_P5_U1_CFG31 0x40011adf +#define CYDEV_UCFG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYDEV_UCFG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYDEV_UCFG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYDEV_UCFG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYDEV_UCFG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYDEV_UCFG_B1_P5_U1_DCFG5 0x40011aea +#define CYDEV_UCFG_B1_P5_U1_DCFG6 0x40011aec +#define CYDEV_UCFG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL0_MDCLK_EN 0x40015000 +#define CYDEV_UCFG_BCTL0_MBCLK_EN 0x40015001 +#define CYDEV_UCFG_BCTL0_WAIT_CFG 0x40015002 +#define CYDEV_UCFG_BCTL0_BANK_CTL 0x40015003 +#define CYDEV_UCFG_BCTL0_UDB_TEST_3 0x40015007 +#define CYDEV_UCFG_BCTL0_DCLK_EN0 0x40015008 +#define CYDEV_UCFG_BCTL0_BCLK_EN0 0x40015009 +#define CYDEV_UCFG_BCTL0_DCLK_EN1 0x4001500a +#define CYDEV_UCFG_BCTL0_BCLK_EN1 0x4001500b +#define CYDEV_UCFG_BCTL0_DCLK_EN2 0x4001500c +#define CYDEV_UCFG_BCTL0_BCLK_EN2 0x4001500d +#define CYDEV_UCFG_BCTL0_DCLK_EN3 0x4001500e +#define CYDEV_UCFG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYDEV_UCFG_BCTL1_MDCLK_EN 0x40015010 +#define CYDEV_UCFG_BCTL1_MBCLK_EN 0x40015011 +#define CYDEV_UCFG_BCTL1_WAIT_CFG 0x40015012 +#define CYDEV_UCFG_BCTL1_BANK_CTL 0x40015013 +#define CYDEV_UCFG_BCTL1_UDB_TEST_3 0x40015017 +#define CYDEV_UCFG_BCTL1_DCLK_EN0 0x40015018 +#define CYDEV_UCFG_BCTL1_BCLK_EN0 0x40015019 +#define CYDEV_UCFG_BCTL1_DCLK_EN1 0x4001501a +#define CYDEV_UCFG_BCTL1_BCLK_EN1 0x4001501b +#define CYDEV_UCFG_BCTL1_DCLK_EN2 0x4001501c +#define CYDEV_UCFG_BCTL1_BCLK_EN2 0x4001501d +#define CYDEV_UCFG_BCTL1_DCLK_EN3 0x4001501e +#define CYDEV_UCFG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYDEV_IDMUX_IRQ_CTL0 0x40015100 +#define CYDEV_IDMUX_IRQ_CTL1 0x40015101 +#define CYDEV_IDMUX_IRQ_CTL2 0x40015102 +#define CYDEV_IDMUX_IRQ_CTL3 0x40015103 +#define CYDEV_IDMUX_IRQ_CTL4 0x40015104 +#define CYDEV_IDMUX_IRQ_CTL5 0x40015105 +#define CYDEV_IDMUX_IRQ_CTL6 0x40015106 +#define CYDEV_IDMUX_IRQ_CTL7 0x40015107 +#define CYDEV_IDMUX_DRQ_CTL0 0x40015110 +#define CYDEV_IDMUX_DRQ_CTL1 0x40015111 +#define CYDEV_IDMUX_DRQ_CTL2 0x40015112 +#define CYDEV_IDMUX_DRQ_CTL3 0x40015113 +#define CYDEV_IDMUX_DRQ_CTL4 0x40015114 +#define CYDEV_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYDEV_CACHERAM_DATA_MBASE 0x40030000 +#define CYDEV_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYDEV_SFR_GPIO0 0x40050180 +#define CYDEV_SFR_GPIRD0 0x40050189 +#define CYDEV_SFR_GPIO0_SEL 0x4005018a +#define CYDEV_SFR_GPIO1 0x40050190 +#define CYDEV_SFR_GPIRD1 0x40050191 +#define CYDEV_SFR_GPIO2 0x40050198 +#define CYDEV_SFR_GPIRD2 0x40050199 +#define CYDEV_SFR_GPIO2_SEL 0x4005019a +#define CYDEV_SFR_GPIO1_SEL 0x400501a2 +#define CYDEV_SFR_GPIO3 0x400501b0 +#define CYDEV_SFR_GPIRD3 0x400501b1 +#define CYDEV_SFR_GPIO3_SEL 0x400501b2 +#define CYDEV_SFR_GPIO4 0x400501c0 +#define CYDEV_SFR_GPIRD4 0x400501c1 +#define CYDEV_SFR_GPIO4_SEL 0x400501c2 +#define CYDEV_SFR_GPIO5 0x400501c8 +#define CYDEV_SFR_GPIRD5 0x400501c9 +#define CYDEV_SFR_GPIO5_SEL 0x400501ca +#define CYDEV_SFR_GPIO6 0x400501d8 +#define CYDEV_SFR_GPIRD6 0x400501d9 +#define CYDEV_SFR_GPIO6_SEL 0x400501da +#define CYDEV_SFR_GPIO12 0x400501e8 +#define CYDEV_SFR_GPIRD12 0x400501e9 +#define CYDEV_SFR_GPIO12_SEL 0x400501f2 +#define CYDEV_SFR_GPIO15 0x400501f8 +#define CYDEV_SFR_GPIRD15 0x400501f9 +#define CYDEV_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYDEV_P3BA_Y_START 0x40050300 +#define CYDEV_P3BA_YROLL 0x40050301 +#define CYDEV_P3BA_YCFG 0x40050302 +#define CYDEV_P3BA_X_START1 0x40050303 +#define CYDEV_P3BA_X_START2 0x40050304 +#define CYDEV_P3BA_XROLL1 0x40050305 +#define CYDEV_P3BA_XROLL2 0x40050306 +#define CYDEV_P3BA_XINC 0x40050307 +#define CYDEV_P3BA_XCFG 0x40050308 +#define CYDEV_P3BA_OFFSETADDR1 0x40050309 +#define CYDEV_P3BA_OFFSETADDR2 0x4005030a +#define CYDEV_P3BA_OFFSETADDR3 0x4005030b +#define CYDEV_P3BA_ABSADDR1 0x4005030c +#define CYDEV_P3BA_ABSADDR2 0x4005030d +#define CYDEV_P3BA_ABSADDR3 0x4005030e +#define CYDEV_P3BA_ABSADDR4 0x4005030f +#define CYDEV_P3BA_DATCFG1 0x40050310 +#define CYDEV_P3BA_DATCFG2 0x40050311 +#define CYDEV_P3BA_CMP_RSLT1 0x40050314 +#define CYDEV_P3BA_CMP_RSLT2 0x40050315 +#define CYDEV_P3BA_CMP_RSLT3 0x40050316 +#define CYDEV_P3BA_CMP_RSLT4 0x40050317 +#define CYDEV_P3BA_DATA_REG1 0x40050318 +#define CYDEV_P3BA_DATA_REG2 0x40050319 +#define CYDEV_P3BA_DATA_REG3 0x4005031a +#define CYDEV_P3BA_DATA_REG4 0x4005031b +#define CYDEV_P3BA_EXP_DATA1 0x4005031c +#define CYDEV_P3BA_EXP_DATA2 0x4005031d +#define CYDEV_P3BA_EXP_DATA3 0x4005031e +#define CYDEV_P3BA_EXP_DATA4 0x4005031f +#define CYDEV_P3BA_MSTR_HRDATA1 0x40050320 +#define CYDEV_P3BA_MSTR_HRDATA2 0x40050321 +#define CYDEV_P3BA_MSTR_HRDATA3 0x40050322 +#define CYDEV_P3BA_MSTR_HRDATA4 0x40050323 +#define CYDEV_P3BA_BIST_EN 0x40050324 +#define CYDEV_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYDEV_P3BA_SEQCFG1 0x40050326 +#define CYDEV_P3BA_SEQCFG2 0x40050327 +#define CYDEV_P3BA_Y_CURR 0x40050328 +#define CYDEV_P3BA_X_CURR1 0x40050329 +#define CYDEV_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYDEV_PANTHER_STCALIB_CFG 0x40080000 +#define CYDEV_PANTHER_WAITPIPE 0x40080004 +#define CYDEV_PANTHER_TRACE_CFG 0x40080008 +#define CYDEV_PANTHER_DBG_CFG 0x4008000c +#define CYDEV_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYDEV_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYDEV_FLSECC_DATA_MBASE 0x48000000 +#define CYDEV_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYDEV_FLSHID_RSVD_MBASE 0x49000000 +#define CYDEV_FLSHID_RSVD_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYDEV_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYDEV_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYDEV_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYDEV_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYDEV_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYDEV_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYDEV_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYDEV_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYDEV_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYDEV_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYDEV_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYDEV_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYDEV_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYDEV_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYDEV_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYDEV_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYDEV_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYDEV_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYDEV_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYDEV_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYDEV_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYDEV_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYDEV_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYDEV_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYDEV_EXTMEM_DATA_MBASE 0x60000000 +#define CYDEV_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYDEV_ITM_TRACE_EN 0xe0000e00 +#define CYDEV_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYDEV_ITM_TRACE_CTRL 0xe0000e80 +#define CYDEV_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYDEV_ITM_LOCK_STATUS 0xe0000fb4 +#define CYDEV_ITM_PID4 0xe0000fd0 +#define CYDEV_ITM_PID5 0xe0000fd4 +#define CYDEV_ITM_PID6 0xe0000fd8 +#define CYDEV_ITM_PID7 0xe0000fdc +#define CYDEV_ITM_PID0 0xe0000fe0 +#define CYDEV_ITM_PID1 0xe0000fe4 +#define CYDEV_ITM_PID2 0xe0000fe8 +#define CYDEV_ITM_PID3 0xe0000fec +#define CYDEV_ITM_CID0 0xe0000ff0 +#define CYDEV_ITM_CID1 0xe0000ff4 +#define CYDEV_ITM_CID2 0xe0000ff8 +#define CYDEV_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYDEV_DWT_CTRL 0xe0001000 +#define CYDEV_DWT_CYCLE_COUNT 0xe0001004 +#define CYDEV_DWT_CPI_COUNT 0xe0001008 +#define CYDEV_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYDEV_DWT_SLEEP_COUNT 0xe0001010 +#define CYDEV_DWT_LSU_COUNT 0xe0001014 +#define CYDEV_DWT_FOLD_COUNT 0xe0001018 +#define CYDEV_DWT_PC_SAMPLE 0xe000101c +#define CYDEV_DWT_COMP_0 0xe0001020 +#define CYDEV_DWT_MASK_0 0xe0001024 +#define CYDEV_DWT_FUNCTION_0 0xe0001028 +#define CYDEV_DWT_COMP_1 0xe0001030 +#define CYDEV_DWT_MASK_1 0xe0001034 +#define CYDEV_DWT_FUNCTION_1 0xe0001038 +#define CYDEV_DWT_COMP_2 0xe0001040 +#define CYDEV_DWT_MASK_2 0xe0001044 +#define CYDEV_DWT_FUNCTION_2 0xe0001048 +#define CYDEV_DWT_COMP_3 0xe0001050 +#define CYDEV_DWT_MASK_3 0xe0001054 +#define CYDEV_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYDEV_FPB_CTRL 0xe0002000 +#define CYDEV_FPB_REMAP 0xe0002004 +#define CYDEV_FPB_FP_COMP_0 0xe0002008 +#define CYDEV_FPB_FP_COMP_1 0xe000200c +#define CYDEV_FPB_FP_COMP_2 0xe0002010 +#define CYDEV_FPB_FP_COMP_3 0xe0002014 +#define CYDEV_FPB_FP_COMP_4 0xe0002018 +#define CYDEV_FPB_FP_COMP_5 0xe000201c +#define CYDEV_FPB_FP_COMP_6 0xe0002020 +#define CYDEV_FPB_FP_COMP_7 0xe0002024 +#define CYDEV_FPB_PID4 0xe0002fd0 +#define CYDEV_FPB_PID5 0xe0002fd4 +#define CYDEV_FPB_PID6 0xe0002fd8 +#define CYDEV_FPB_PID7 0xe0002fdc +#define CYDEV_FPB_PID0 0xe0002fe0 +#define CYDEV_FPB_PID1 0xe0002fe4 +#define CYDEV_FPB_PID2 0xe0002fe8 +#define CYDEV_FPB_PID3 0xe0002fec +#define CYDEV_FPB_CID0 0xe0002ff0 +#define CYDEV_FPB_CID1 0xe0002ff4 +#define CYDEV_FPB_CID2 0xe0002ff8 +#define CYDEV_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYDEV_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYDEV_NVIC_SYSTICK_CTL 0xe000e010 +#define CYDEV_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYDEV_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYDEV_NVIC_SYSTICK_CAL 0xe000e01c +#define CYDEV_NVIC_SETENA0 0xe000e100 +#define CYDEV_NVIC_CLRENA0 0xe000e180 +#define CYDEV_NVIC_SETPEND0 0xe000e200 +#define CYDEV_NVIC_CLRPEND0 0xe000e280 +#define CYDEV_NVIC_ACTIVE0 0xe000e300 +#define CYDEV_NVIC_PRI_0 0xe000e400 +#define CYDEV_NVIC_PRI_1 0xe000e401 +#define CYDEV_NVIC_PRI_2 0xe000e402 +#define CYDEV_NVIC_PRI_3 0xe000e403 +#define CYDEV_NVIC_PRI_4 0xe000e404 +#define CYDEV_NVIC_PRI_5 0xe000e405 +#define CYDEV_NVIC_PRI_6 0xe000e406 +#define CYDEV_NVIC_PRI_7 0xe000e407 +#define CYDEV_NVIC_PRI_8 0xe000e408 +#define CYDEV_NVIC_PRI_9 0xe000e409 +#define CYDEV_NVIC_PRI_10 0xe000e40a +#define CYDEV_NVIC_PRI_11 0xe000e40b +#define CYDEV_NVIC_PRI_12 0xe000e40c +#define CYDEV_NVIC_PRI_13 0xe000e40d +#define CYDEV_NVIC_PRI_14 0xe000e40e +#define CYDEV_NVIC_PRI_15 0xe000e40f +#define CYDEV_NVIC_PRI_16 0xe000e410 +#define CYDEV_NVIC_PRI_17 0xe000e411 +#define CYDEV_NVIC_PRI_18 0xe000e412 +#define CYDEV_NVIC_PRI_19 0xe000e413 +#define CYDEV_NVIC_PRI_20 0xe000e414 +#define CYDEV_NVIC_PRI_21 0xe000e415 +#define CYDEV_NVIC_PRI_22 0xe000e416 +#define CYDEV_NVIC_PRI_23 0xe000e417 +#define CYDEV_NVIC_PRI_24 0xe000e418 +#define CYDEV_NVIC_PRI_25 0xe000e419 +#define CYDEV_NVIC_PRI_26 0xe000e41a +#define CYDEV_NVIC_PRI_27 0xe000e41b +#define CYDEV_NVIC_PRI_28 0xe000e41c +#define CYDEV_NVIC_PRI_29 0xe000e41d +#define CYDEV_NVIC_PRI_30 0xe000e41e +#define CYDEV_NVIC_PRI_31 0xe000e41f +#define CYDEV_NVIC_CPUID_BASE 0xe000ed00 +#define CYDEV_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYDEV_NVIC_VECT_OFFSET 0xe000ed08 +#define CYDEV_NVIC_APPLN_INTR 0xe000ed0c +#define CYDEV_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYDEV_NVIC_CFG_CONTROL 0xe000ed14 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYDEV_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYDEV_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYDEV_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYDEV_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYDEV_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYDEV_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYDEV_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYDEV_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYDEV_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYDEV_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYDEV_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYDEV_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYDEV_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYDEV_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYDEV_TPIU_PROTOCOL 0xe00400f0 +#define CYDEV_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYDEV_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYDEV_TPIU_TRIGGER 0xe0040ee8 +#define CYDEV_TPIU_ITETMDATA 0xe0040eec +#define CYDEV_TPIU_ITATBCTR2 0xe0040ef0 +#define CYDEV_TPIU_ITATBCTR0 0xe0040ef8 +#define CYDEV_TPIU_ITITMDATA 0xe0040efc +#define CYDEV_TPIU_ITCTRL 0xe0040f00 +#define CYDEV_TPIU_DEVID 0xe0040fc8 +#define CYDEV_TPIU_DEVTYPE 0xe0040fcc +#define CYDEV_TPIU_PID4 0xe0040fd0 +#define CYDEV_TPIU_PID5 0xe0040fd4 +#define CYDEV_TPIU_PID6 0xe0040fd8 +#define CYDEV_TPIU_PID7 0xe0040fdc +#define CYDEV_TPIU_PID0 0xe0040fe0 +#define CYDEV_TPIU_PID1 0xe0040fe4 +#define CYDEV_TPIU_PID2 0xe0040fe8 +#define CYDEV_TPIU_PID3 0xe0040fec +#define CYDEV_TPIU_CID0 0xe0040ff0 +#define CYDEV_TPIU_CID1 0xe0040ff4 +#define CYDEV_TPIU_CID2 0xe0040ff8 +#define CYDEV_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYDEV_ETM_CTL 0xe0041000 +#define CYDEV_ETM_CFG_CODE 0xe0041004 +#define CYDEV_ETM_TRIG_EVENT 0xe0041008 +#define CYDEV_ETM_STATUS 0xe0041010 +#define CYDEV_ETM_SYS_CFG 0xe0041014 +#define CYDEV_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYDEV_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYDEV_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYDEV_ETM_SYNC_FREQ 0xe00411e0 +#define CYDEV_ETM_ETM_ID 0xe00411e4 +#define CYDEV_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYDEV_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYDEV_ETM_CS_TRACE_ID 0xe0041200 +#define CYDEV_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYDEV_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYDEV_ETM_PDSR 0xe0041314 +#define CYDEV_ETM_ITMISCIN 0xe0041ee0 +#define CYDEV_ETM_ITTRIGOUT 0xe0041ee8 +#define CYDEV_ETM_ITATBCTR2 0xe0041ef0 +#define CYDEV_ETM_ITATBCTR0 0xe0041ef8 +#define CYDEV_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYDEV_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYDEV_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYDEV_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYDEV_ETM_LOCK_STATUS 0xe0041fb4 +#define CYDEV_ETM_AUTH_STATUS 0xe0041fb8 +#define CYDEV_ETM_DEV_TYPE 0xe0041fcc +#define CYDEV_ETM_PID4 0xe0041fd0 +#define CYDEV_ETM_PID5 0xe0041fd4 +#define CYDEV_ETM_PID6 0xe0041fd8 +#define CYDEV_ETM_PID7 0xe0041fdc +#define CYDEV_ETM_PID0 0xe0041fe0 +#define CYDEV_ETM_PID1 0xe0041fe4 +#define CYDEV_ETM_PID2 0xe0041fe8 +#define CYDEV_ETM_PID3 0xe0041fec +#define CYDEV_ETM_CID0 0xe0041ff0 +#define CYDEV_ETM_CID1 0xe0041ff4 +#define CYDEV_ETM_CID2 0xe0041ff8 +#define CYDEV_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYDEV_ROM_TABLE_NVIC 0xe00ff000 +#define CYDEV_ROM_TABLE_DWT 0xe00ff004 +#define CYDEV_ROM_TABLE_FPB 0xe00ff008 +#define CYDEV_ROM_TABLE_ITM 0xe00ff00c +#define CYDEV_ROM_TABLE_TPIU 0xe00ff010 +#define CYDEV_ROM_TABLE_ETM 0xe00ff014 +#define CYDEV_ROM_TABLE_END 0xe00ff018 +#define CYDEV_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYDEV_ROM_TABLE_PID4 0xe00fffd0 +#define CYDEV_ROM_TABLE_PID5 0xe00fffd4 +#define CYDEV_ROM_TABLE_PID6 0xe00fffd8 +#define CYDEV_ROM_TABLE_PID7 0xe00fffdc +#define CYDEV_ROM_TABLE_PID0 0xe00fffe0 +#define CYDEV_ROM_TABLE_PID1 0xe00fffe4 +#define CYDEV_ROM_TABLE_PID2 0xe00fffe8 +#define CYDEV_ROM_TABLE_PID3 0xe00fffec +#define CYDEV_ROM_TABLE_CID0 0xe00ffff0 +#define CYDEV_ROM_TABLE_CID1 0xe00ffff4 +#define CYDEV_ROM_TABLE_CID2 0xe00ffff8 +#define CYDEV_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc new file mode 100644 index 0000000..30429cd --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc @@ -0,0 +1,5356 @@ +; +; File Name: cydeviceiar_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#define CYDEV_FLASH_BASE 0x00000000 +#define CYDEV_FLASH_SIZE 0x00020000 +#define CYREG_FLASH_DATA_MBASE 0x00000000 +#define CYREG_FLASH_DATA_MSIZE 0x00020000 +#define CYDEV_SRAM_BASE 0x1fffc000 +#define CYDEV_SRAM_SIZE 0x00008000 +#define CYREG_SRAM_CODE64K_MBASE 0x1fff8000 +#define CYREG_SRAM_CODE64K_MSIZE 0x00004000 +#define CYREG_SRAM_CODE32K_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE32K_MSIZE 0x00002000 +#define CYREG_SRAM_CODE16K_MBASE 0x1fffe000 +#define CYREG_SRAM_CODE16K_MSIZE 0x00001000 +#define CYREG_SRAM_CODE_MBASE 0x1fffc000 +#define CYREG_SRAM_CODE_MSIZE 0x00004000 +#define CYREG_SRAM_DATA_MBASE 0x20000000 +#define CYREG_SRAM_DATA_MSIZE 0x00004000 +#define CYREG_SRAM_DATA16K_MBASE 0x20001000 +#define CYREG_SRAM_DATA16K_MSIZE 0x00001000 +#define CYREG_SRAM_DATA32K_MBASE 0x20002000 +#define CYREG_SRAM_DATA32K_MSIZE 0x00002000 +#define CYREG_SRAM_DATA64K_MBASE 0x20004000 +#define CYREG_SRAM_DATA64K_MSIZE 0x00004000 +#define CYDEV_DMA_BASE 0x20008000 +#define CYDEV_DMA_SIZE 0x00008000 +#define CYREG_DMA_SRAM64K_MBASE 0x20008000 +#define CYREG_DMA_SRAM64K_MSIZE 0x00004000 +#define CYREG_DMA_SRAM32K_MBASE 0x2000c000 +#define CYREG_DMA_SRAM32K_MSIZE 0x00002000 +#define CYREG_DMA_SRAM16K_MBASE 0x2000e000 +#define CYREG_DMA_SRAM16K_MSIZE 0x00001000 +#define CYREG_DMA_SRAM_MBASE 0x2000f000 +#define CYREG_DMA_SRAM_MSIZE 0x00001000 +#define CYDEV_CLKDIST_BASE 0x40004000 +#define CYDEV_CLKDIST_SIZE 0x00000110 +#define CYREG_CLKDIST_CR 0x40004000 +#define CYREG_CLKDIST_LD 0x40004001 +#define CYREG_CLKDIST_WRK0 0x40004002 +#define CYREG_CLKDIST_WRK1 0x40004003 +#define CYREG_CLKDIST_MSTR0 0x40004004 +#define CYREG_CLKDIST_MSTR1 0x40004005 +#define CYREG_CLKDIST_BCFG0 0x40004006 +#define CYREG_CLKDIST_BCFG1 0x40004007 +#define CYREG_CLKDIST_BCFG2 0x40004008 +#define CYREG_CLKDIST_UCFG 0x40004009 +#define CYREG_CLKDIST_DLY0 0x4000400a +#define CYREG_CLKDIST_DLY1 0x4000400b +#define CYREG_CLKDIST_DMASK 0x40004010 +#define CYREG_CLKDIST_AMASK 0x40004014 +#define CYDEV_CLKDIST_DCFG0_BASE 0x40004080 +#define CYDEV_CLKDIST_DCFG0_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG0_CFG0 0x40004080 +#define CYREG_CLKDIST_DCFG0_CFG1 0x40004081 +#define CYREG_CLKDIST_DCFG0_CFG2 0x40004082 +#define CYDEV_CLKDIST_DCFG1_BASE 0x40004084 +#define CYDEV_CLKDIST_DCFG1_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG1_CFG0 0x40004084 +#define CYREG_CLKDIST_DCFG1_CFG1 0x40004085 +#define CYREG_CLKDIST_DCFG1_CFG2 0x40004086 +#define CYDEV_CLKDIST_DCFG2_BASE 0x40004088 +#define CYDEV_CLKDIST_DCFG2_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG2_CFG0 0x40004088 +#define CYREG_CLKDIST_DCFG2_CFG1 0x40004089 +#define CYREG_CLKDIST_DCFG2_CFG2 0x4000408a +#define CYDEV_CLKDIST_DCFG3_BASE 0x4000408c +#define CYDEV_CLKDIST_DCFG3_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG3_CFG0 0x4000408c +#define CYREG_CLKDIST_DCFG3_CFG1 0x4000408d +#define CYREG_CLKDIST_DCFG3_CFG2 0x4000408e +#define CYDEV_CLKDIST_DCFG4_BASE 0x40004090 +#define CYDEV_CLKDIST_DCFG4_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG4_CFG0 0x40004090 +#define CYREG_CLKDIST_DCFG4_CFG1 0x40004091 +#define CYREG_CLKDIST_DCFG4_CFG2 0x40004092 +#define CYDEV_CLKDIST_DCFG5_BASE 0x40004094 +#define CYDEV_CLKDIST_DCFG5_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG5_CFG0 0x40004094 +#define CYREG_CLKDIST_DCFG5_CFG1 0x40004095 +#define CYREG_CLKDIST_DCFG5_CFG2 0x40004096 +#define CYDEV_CLKDIST_DCFG6_BASE 0x40004098 +#define CYDEV_CLKDIST_DCFG6_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG6_CFG0 0x40004098 +#define CYREG_CLKDIST_DCFG6_CFG1 0x40004099 +#define CYREG_CLKDIST_DCFG6_CFG2 0x4000409a +#define CYDEV_CLKDIST_DCFG7_BASE 0x4000409c +#define CYDEV_CLKDIST_DCFG7_SIZE 0x00000003 +#define CYREG_CLKDIST_DCFG7_CFG0 0x4000409c +#define CYREG_CLKDIST_DCFG7_CFG1 0x4000409d +#define CYREG_CLKDIST_DCFG7_CFG2 0x4000409e +#define CYDEV_CLKDIST_ACFG0_BASE 0x40004100 +#define CYDEV_CLKDIST_ACFG0_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG0_CFG0 0x40004100 +#define CYREG_CLKDIST_ACFG0_CFG1 0x40004101 +#define CYREG_CLKDIST_ACFG0_CFG2 0x40004102 +#define CYREG_CLKDIST_ACFG0_CFG3 0x40004103 +#define CYDEV_CLKDIST_ACFG1_BASE 0x40004104 +#define CYDEV_CLKDIST_ACFG1_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG1_CFG0 0x40004104 +#define CYREG_CLKDIST_ACFG1_CFG1 0x40004105 +#define CYREG_CLKDIST_ACFG1_CFG2 0x40004106 +#define CYREG_CLKDIST_ACFG1_CFG3 0x40004107 +#define CYDEV_CLKDIST_ACFG2_BASE 0x40004108 +#define CYDEV_CLKDIST_ACFG2_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG2_CFG0 0x40004108 +#define CYREG_CLKDIST_ACFG2_CFG1 0x40004109 +#define CYREG_CLKDIST_ACFG2_CFG2 0x4000410a +#define CYREG_CLKDIST_ACFG2_CFG3 0x4000410b +#define CYDEV_CLKDIST_ACFG3_BASE 0x4000410c +#define CYDEV_CLKDIST_ACFG3_SIZE 0x00000004 +#define CYREG_CLKDIST_ACFG3_CFG0 0x4000410c +#define CYREG_CLKDIST_ACFG3_CFG1 0x4000410d +#define CYREG_CLKDIST_ACFG3_CFG2 0x4000410e +#define CYREG_CLKDIST_ACFG3_CFG3 0x4000410f +#define CYDEV_FASTCLK_BASE 0x40004200 +#define CYDEV_FASTCLK_SIZE 0x00000026 +#define CYDEV_FASTCLK_IMO_BASE 0x40004200 +#define CYDEV_FASTCLK_IMO_SIZE 0x00000001 +#define CYREG_FASTCLK_IMO_CR 0x40004200 +#define CYDEV_FASTCLK_XMHZ_BASE 0x40004210 +#define CYDEV_FASTCLK_XMHZ_SIZE 0x00000004 +#define CYREG_FASTCLK_XMHZ_CSR 0x40004210 +#define CYREG_FASTCLK_XMHZ_CFG0 0x40004212 +#define CYREG_FASTCLK_XMHZ_CFG1 0x40004213 +#define CYDEV_FASTCLK_PLL_BASE 0x40004220 +#define CYDEV_FASTCLK_PLL_SIZE 0x00000006 +#define CYREG_FASTCLK_PLL_CFG0 0x40004220 +#define CYREG_FASTCLK_PLL_CFG1 0x40004221 +#define CYREG_FASTCLK_PLL_P 0x40004222 +#define CYREG_FASTCLK_PLL_Q 0x40004223 +#define CYREG_FASTCLK_PLL_SR 0x40004225 +#define CYDEV_SLOWCLK_BASE 0x40004300 +#define CYDEV_SLOWCLK_SIZE 0x0000000b +#define CYDEV_SLOWCLK_ILO_BASE 0x40004300 +#define CYDEV_SLOWCLK_ILO_SIZE 0x00000002 +#define CYREG_SLOWCLK_ILO_CR0 0x40004300 +#define CYREG_SLOWCLK_ILO_CR1 0x40004301 +#define CYDEV_SLOWCLK_X32_BASE 0x40004308 +#define CYDEV_SLOWCLK_X32_SIZE 0x00000003 +#define CYREG_SLOWCLK_X32_CR 0x40004308 +#define CYREG_SLOWCLK_X32_CFG 0x40004309 +#define CYREG_SLOWCLK_X32_TST 0x4000430a +#define CYDEV_BOOST_BASE 0x40004320 +#define CYDEV_BOOST_SIZE 0x00000007 +#define CYREG_BOOST_CR0 0x40004320 +#define CYREG_BOOST_CR1 0x40004321 +#define CYREG_BOOST_CR2 0x40004322 +#define CYREG_BOOST_CR3 0x40004323 +#define CYREG_BOOST_SR 0x40004324 +#define CYREG_BOOST_CR4 0x40004325 +#define CYREG_BOOST_SR2 0x40004326 +#define CYDEV_PWRSYS_BASE 0x40004330 +#define CYDEV_PWRSYS_SIZE 0x00000002 +#define CYREG_PWRSYS_CR0 0x40004330 +#define CYREG_PWRSYS_CR1 0x40004331 +#define CYDEV_PM_BASE 0x40004380 +#define CYDEV_PM_SIZE 0x00000057 +#define CYREG_PM_TW_CFG0 0x40004380 +#define CYREG_PM_TW_CFG1 0x40004381 +#define CYREG_PM_TW_CFG2 0x40004382 +#define CYREG_PM_WDT_CFG 0x40004383 +#define CYREG_PM_WDT_CR 0x40004384 +#define CYREG_PM_INT_SR 0x40004390 +#define CYREG_PM_MODE_CFG0 0x40004391 +#define CYREG_PM_MODE_CFG1 0x40004392 +#define CYREG_PM_MODE_CSR 0x40004393 +#define CYREG_PM_USB_CR0 0x40004394 +#define CYREG_PM_WAKEUP_CFG0 0x40004398 +#define CYREG_PM_WAKEUP_CFG1 0x40004399 +#define CYREG_PM_WAKEUP_CFG2 0x4000439a +#define CYDEV_PM_ACT_BASE 0x400043a0 +#define CYDEV_PM_ACT_SIZE 0x0000000e +#define CYREG_PM_ACT_CFG0 0x400043a0 +#define CYREG_PM_ACT_CFG1 0x400043a1 +#define CYREG_PM_ACT_CFG2 0x400043a2 +#define CYREG_PM_ACT_CFG3 0x400043a3 +#define CYREG_PM_ACT_CFG4 0x400043a4 +#define CYREG_PM_ACT_CFG5 0x400043a5 +#define CYREG_PM_ACT_CFG6 0x400043a6 +#define CYREG_PM_ACT_CFG7 0x400043a7 +#define CYREG_PM_ACT_CFG8 0x400043a8 +#define CYREG_PM_ACT_CFG9 0x400043a9 +#define CYREG_PM_ACT_CFG10 0x400043aa +#define CYREG_PM_ACT_CFG11 0x400043ab +#define CYREG_PM_ACT_CFG12 0x400043ac +#define CYREG_PM_ACT_CFG13 0x400043ad +#define CYDEV_PM_STBY_BASE 0x400043b0 +#define CYDEV_PM_STBY_SIZE 0x0000000e +#define CYREG_PM_STBY_CFG0 0x400043b0 +#define CYREG_PM_STBY_CFG1 0x400043b1 +#define CYREG_PM_STBY_CFG2 0x400043b2 +#define CYREG_PM_STBY_CFG3 0x400043b3 +#define CYREG_PM_STBY_CFG4 0x400043b4 +#define CYREG_PM_STBY_CFG5 0x400043b5 +#define CYREG_PM_STBY_CFG6 0x400043b6 +#define CYREG_PM_STBY_CFG7 0x400043b7 +#define CYREG_PM_STBY_CFG8 0x400043b8 +#define CYREG_PM_STBY_CFG9 0x400043b9 +#define CYREG_PM_STBY_CFG10 0x400043ba +#define CYREG_PM_STBY_CFG11 0x400043bb +#define CYREG_PM_STBY_CFG12 0x400043bc +#define CYREG_PM_STBY_CFG13 0x400043bd +#define CYDEV_PM_AVAIL_BASE 0x400043c0 +#define CYDEV_PM_AVAIL_SIZE 0x00000017 +#define CYREG_PM_AVAIL_CR0 0x400043c0 +#define CYREG_PM_AVAIL_CR1 0x400043c1 +#define CYREG_PM_AVAIL_CR2 0x400043c2 +#define CYREG_PM_AVAIL_CR3 0x400043c3 +#define CYREG_PM_AVAIL_CR4 0x400043c4 +#define CYREG_PM_AVAIL_CR5 0x400043c5 +#define CYREG_PM_AVAIL_CR6 0x400043c6 +#define CYREG_PM_AVAIL_SR0 0x400043d0 +#define CYREG_PM_AVAIL_SR1 0x400043d1 +#define CYREG_PM_AVAIL_SR2 0x400043d2 +#define CYREG_PM_AVAIL_SR3 0x400043d3 +#define CYREG_PM_AVAIL_SR4 0x400043d4 +#define CYREG_PM_AVAIL_SR5 0x400043d5 +#define CYREG_PM_AVAIL_SR6 0x400043d6 +#define CYDEV_PICU_BASE 0x40004500 +#define CYDEV_PICU_SIZE 0x000000b0 +#define CYDEV_PICU_INTTYPE_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_SIZE 0x00000080 +#define CYDEV_PICU_INTTYPE_PICU0_BASE 0x40004500 +#define CYDEV_PICU_INTTYPE_PICU0_SIZE 0x00000008 +#define CYREG_PICU0_INTTYPE0 0x40004500 +#define CYREG_PICU0_INTTYPE1 0x40004501 +#define CYREG_PICU0_INTTYPE2 0x40004502 +#define CYREG_PICU0_INTTYPE3 0x40004503 +#define CYREG_PICU0_INTTYPE4 0x40004504 +#define CYREG_PICU0_INTTYPE5 0x40004505 +#define CYREG_PICU0_INTTYPE6 0x40004506 +#define CYREG_PICU0_INTTYPE7 0x40004507 +#define CYDEV_PICU_INTTYPE_PICU1_BASE 0x40004508 +#define CYDEV_PICU_INTTYPE_PICU1_SIZE 0x00000008 +#define CYREG_PICU1_INTTYPE0 0x40004508 +#define CYREG_PICU1_INTTYPE1 0x40004509 +#define CYREG_PICU1_INTTYPE2 0x4000450a +#define CYREG_PICU1_INTTYPE3 0x4000450b +#define CYREG_PICU1_INTTYPE4 0x4000450c +#define CYREG_PICU1_INTTYPE5 0x4000450d +#define CYREG_PICU1_INTTYPE6 0x4000450e +#define CYREG_PICU1_INTTYPE7 0x4000450f +#define CYDEV_PICU_INTTYPE_PICU2_BASE 0x40004510 +#define CYDEV_PICU_INTTYPE_PICU2_SIZE 0x00000008 +#define CYREG_PICU2_INTTYPE0 0x40004510 +#define CYREG_PICU2_INTTYPE1 0x40004511 +#define CYREG_PICU2_INTTYPE2 0x40004512 +#define CYREG_PICU2_INTTYPE3 0x40004513 +#define CYREG_PICU2_INTTYPE4 0x40004514 +#define CYREG_PICU2_INTTYPE5 0x40004515 +#define CYREG_PICU2_INTTYPE6 0x40004516 +#define CYREG_PICU2_INTTYPE7 0x40004517 +#define CYDEV_PICU_INTTYPE_PICU3_BASE 0x40004518 +#define CYDEV_PICU_INTTYPE_PICU3_SIZE 0x00000008 +#define CYREG_PICU3_INTTYPE0 0x40004518 +#define CYREG_PICU3_INTTYPE1 0x40004519 +#define CYREG_PICU3_INTTYPE2 0x4000451a +#define CYREG_PICU3_INTTYPE3 0x4000451b +#define CYREG_PICU3_INTTYPE4 0x4000451c +#define CYREG_PICU3_INTTYPE5 0x4000451d +#define CYREG_PICU3_INTTYPE6 0x4000451e +#define CYREG_PICU3_INTTYPE7 0x4000451f +#define CYDEV_PICU_INTTYPE_PICU4_BASE 0x40004520 +#define CYDEV_PICU_INTTYPE_PICU4_SIZE 0x00000008 +#define CYREG_PICU4_INTTYPE0 0x40004520 +#define CYREG_PICU4_INTTYPE1 0x40004521 +#define CYREG_PICU4_INTTYPE2 0x40004522 +#define CYREG_PICU4_INTTYPE3 0x40004523 +#define CYREG_PICU4_INTTYPE4 0x40004524 +#define CYREG_PICU4_INTTYPE5 0x40004525 +#define CYREG_PICU4_INTTYPE6 0x40004526 +#define CYREG_PICU4_INTTYPE7 0x40004527 +#define CYDEV_PICU_INTTYPE_PICU5_BASE 0x40004528 +#define CYDEV_PICU_INTTYPE_PICU5_SIZE 0x00000008 +#define CYREG_PICU5_INTTYPE0 0x40004528 +#define CYREG_PICU5_INTTYPE1 0x40004529 +#define CYREG_PICU5_INTTYPE2 0x4000452a +#define CYREG_PICU5_INTTYPE3 0x4000452b +#define CYREG_PICU5_INTTYPE4 0x4000452c +#define CYREG_PICU5_INTTYPE5 0x4000452d +#define CYREG_PICU5_INTTYPE6 0x4000452e +#define CYREG_PICU5_INTTYPE7 0x4000452f +#define CYDEV_PICU_INTTYPE_PICU6_BASE 0x40004530 +#define CYDEV_PICU_INTTYPE_PICU6_SIZE 0x00000008 +#define CYREG_PICU6_INTTYPE0 0x40004530 +#define CYREG_PICU6_INTTYPE1 0x40004531 +#define CYREG_PICU6_INTTYPE2 0x40004532 +#define CYREG_PICU6_INTTYPE3 0x40004533 +#define CYREG_PICU6_INTTYPE4 0x40004534 +#define CYREG_PICU6_INTTYPE5 0x40004535 +#define CYREG_PICU6_INTTYPE6 0x40004536 +#define CYREG_PICU6_INTTYPE7 0x40004537 +#define CYDEV_PICU_INTTYPE_PICU12_BASE 0x40004560 +#define CYDEV_PICU_INTTYPE_PICU12_SIZE 0x00000008 +#define CYREG_PICU12_INTTYPE0 0x40004560 +#define CYREG_PICU12_INTTYPE1 0x40004561 +#define CYREG_PICU12_INTTYPE2 0x40004562 +#define CYREG_PICU12_INTTYPE3 0x40004563 +#define CYREG_PICU12_INTTYPE4 0x40004564 +#define CYREG_PICU12_INTTYPE5 0x40004565 +#define CYREG_PICU12_INTTYPE6 0x40004566 +#define CYREG_PICU12_INTTYPE7 0x40004567 +#define CYDEV_PICU_INTTYPE_PICU15_BASE 0x40004578 +#define CYDEV_PICU_INTTYPE_PICU15_SIZE 0x00000008 +#define CYREG_PICU15_INTTYPE0 0x40004578 +#define CYREG_PICU15_INTTYPE1 0x40004579 +#define CYREG_PICU15_INTTYPE2 0x4000457a +#define CYREG_PICU15_INTTYPE3 0x4000457b +#define CYREG_PICU15_INTTYPE4 0x4000457c +#define CYREG_PICU15_INTTYPE5 0x4000457d +#define CYREG_PICU15_INTTYPE6 0x4000457e +#define CYREG_PICU15_INTTYPE7 0x4000457f +#define CYDEV_PICU_STAT_BASE 0x40004580 +#define CYDEV_PICU_STAT_SIZE 0x00000010 +#define CYDEV_PICU_STAT_PICU0_BASE 0x40004580 +#define CYDEV_PICU_STAT_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_INTSTAT 0x40004580 +#define CYDEV_PICU_STAT_PICU1_BASE 0x40004581 +#define CYDEV_PICU_STAT_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_INTSTAT 0x40004581 +#define CYDEV_PICU_STAT_PICU2_BASE 0x40004582 +#define CYDEV_PICU_STAT_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_INTSTAT 0x40004582 +#define CYDEV_PICU_STAT_PICU3_BASE 0x40004583 +#define CYDEV_PICU_STAT_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_INTSTAT 0x40004583 +#define CYDEV_PICU_STAT_PICU4_BASE 0x40004584 +#define CYDEV_PICU_STAT_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_INTSTAT 0x40004584 +#define CYDEV_PICU_STAT_PICU5_BASE 0x40004585 +#define CYDEV_PICU_STAT_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_INTSTAT 0x40004585 +#define CYDEV_PICU_STAT_PICU6_BASE 0x40004586 +#define CYDEV_PICU_STAT_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_INTSTAT 0x40004586 +#define CYDEV_PICU_STAT_PICU12_BASE 0x4000458c +#define CYDEV_PICU_STAT_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_INTSTAT 0x4000458c +#define CYDEV_PICU_STAT_PICU15_BASE 0x4000458f +#define CYDEV_PICU_STAT_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_INTSTAT 0x4000458f +#define CYDEV_PICU_SNAP_BASE 0x40004590 +#define CYDEV_PICU_SNAP_SIZE 0x00000010 +#define CYDEV_PICU_SNAP_PICU0_BASE 0x40004590 +#define CYDEV_PICU_SNAP_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_SNAP 0x40004590 +#define CYDEV_PICU_SNAP_PICU1_BASE 0x40004591 +#define CYDEV_PICU_SNAP_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_SNAP 0x40004591 +#define CYDEV_PICU_SNAP_PICU2_BASE 0x40004592 +#define CYDEV_PICU_SNAP_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_SNAP 0x40004592 +#define CYDEV_PICU_SNAP_PICU3_BASE 0x40004593 +#define CYDEV_PICU_SNAP_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_SNAP 0x40004593 +#define CYDEV_PICU_SNAP_PICU4_BASE 0x40004594 +#define CYDEV_PICU_SNAP_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_SNAP 0x40004594 +#define CYDEV_PICU_SNAP_PICU5_BASE 0x40004595 +#define CYDEV_PICU_SNAP_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_SNAP 0x40004595 +#define CYDEV_PICU_SNAP_PICU6_BASE 0x40004596 +#define CYDEV_PICU_SNAP_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_SNAP 0x40004596 +#define CYDEV_PICU_SNAP_PICU12_BASE 0x4000459c +#define CYDEV_PICU_SNAP_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_SNAP 0x4000459c +#define CYDEV_PICU_SNAP_PICU_15_BASE 0x4000459f +#define CYDEV_PICU_SNAP_PICU_15_SIZE 0x00000001 +#define CYREG_PICU_15_SNAP_15 0x4000459f +#define CYDEV_PICU_DISABLE_COR_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_SIZE 0x00000010 +#define CYDEV_PICU_DISABLE_COR_PICU0_BASE 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU0_SIZE 0x00000001 +#define CYREG_PICU0_DISABLE_COR 0x400045a0 +#define CYDEV_PICU_DISABLE_COR_PICU1_BASE 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU1_SIZE 0x00000001 +#define CYREG_PICU1_DISABLE_COR 0x400045a1 +#define CYDEV_PICU_DISABLE_COR_PICU2_BASE 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU2_SIZE 0x00000001 +#define CYREG_PICU2_DISABLE_COR 0x400045a2 +#define CYDEV_PICU_DISABLE_COR_PICU3_BASE 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU3_SIZE 0x00000001 +#define CYREG_PICU3_DISABLE_COR 0x400045a3 +#define CYDEV_PICU_DISABLE_COR_PICU4_BASE 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU4_SIZE 0x00000001 +#define CYREG_PICU4_DISABLE_COR 0x400045a4 +#define CYDEV_PICU_DISABLE_COR_PICU5_BASE 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU5_SIZE 0x00000001 +#define CYREG_PICU5_DISABLE_COR 0x400045a5 +#define CYDEV_PICU_DISABLE_COR_PICU6_BASE 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU6_SIZE 0x00000001 +#define CYREG_PICU6_DISABLE_COR 0x400045a6 +#define CYDEV_PICU_DISABLE_COR_PICU12_BASE 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU12_SIZE 0x00000001 +#define CYREG_PICU12_DISABLE_COR 0x400045ac +#define CYDEV_PICU_DISABLE_COR_PICU15_BASE 0x400045af +#define CYDEV_PICU_DISABLE_COR_PICU15_SIZE 0x00000001 +#define CYREG_PICU15_DISABLE_COR 0x400045af +#define CYDEV_MFGCFG_BASE 0x40004600 +#define CYDEV_MFGCFG_SIZE 0x000000ed +#define CYDEV_MFGCFG_ANAIF_BASE 0x40004600 +#define CYDEV_MFGCFG_ANAIF_SIZE 0x00000038 +#define CYDEV_MFGCFG_ANAIF_DAC0_BASE 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_TR 0x40004608 +#define CYDEV_MFGCFG_ANAIF_DAC1_BASE 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_TR 0x40004609 +#define CYDEV_MFGCFG_ANAIF_DAC2_BASE 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_TR 0x4000460a +#define CYDEV_MFGCFG_ANAIF_DAC3_BASE 0x4000460b +#define CYDEV_MFGCFG_ANAIF_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_TR 0x4000460b +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE 0x00000001 +#define CYREG_NPUMP_DSM_TR0 0x40004610 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE 0x00000001 +#define CYREG_NPUMP_SC_TR0 0x40004611 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE 0x40004612 +#define CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE 0x00000001 +#define CYREG_NPUMP_OPAMP_TR0 0x40004612 +#define CYDEV_MFGCFG_ANAIF_SAR0_BASE 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR0_SIZE 0x00000001 +#define CYREG_SAR0_TR0 0x40004614 +#define CYDEV_MFGCFG_ANAIF_SAR1_BASE 0x40004616 +#define CYDEV_MFGCFG_ANAIF_SAR1_SIZE 0x00000001 +#define CYREG_SAR1_TR0 0x40004616 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_BASE 0x40004620 +#define CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_TR0 0x40004620 +#define CYREG_OPAMP0_TR1 0x40004621 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_BASE 0x40004622 +#define CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_TR0 0x40004622 +#define CYREG_OPAMP1_TR1 0x40004623 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_BASE 0x40004624 +#define CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_TR0 0x40004624 +#define CYREG_OPAMP2_TR1 0x40004625 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_BASE 0x40004626 +#define CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_TR0 0x40004626 +#define CYREG_OPAMP3_TR1 0x40004627 +#define CYDEV_MFGCFG_ANAIF_CMP0_BASE 0x40004630 +#define CYDEV_MFGCFG_ANAIF_CMP0_SIZE 0x00000002 +#define CYREG_CMP0_TR0 0x40004630 +#define CYREG_CMP0_TR1 0x40004631 +#define CYDEV_MFGCFG_ANAIF_CMP1_BASE 0x40004632 +#define CYDEV_MFGCFG_ANAIF_CMP1_SIZE 0x00000002 +#define CYREG_CMP1_TR0 0x40004632 +#define CYREG_CMP1_TR1 0x40004633 +#define CYDEV_MFGCFG_ANAIF_CMP2_BASE 0x40004634 +#define CYDEV_MFGCFG_ANAIF_CMP2_SIZE 0x00000002 +#define CYREG_CMP2_TR0 0x40004634 +#define CYREG_CMP2_TR1 0x40004635 +#define CYDEV_MFGCFG_ANAIF_CMP3_BASE 0x40004636 +#define CYDEV_MFGCFG_ANAIF_CMP3_SIZE 0x00000002 +#define CYREG_CMP3_TR0 0x40004636 +#define CYREG_CMP3_TR1 0x40004637 +#define CYDEV_MFGCFG_PWRSYS_BASE 0x40004680 +#define CYDEV_MFGCFG_PWRSYS_SIZE 0x0000000b +#define CYREG_PWRSYS_HIB_TR0 0x40004680 +#define CYREG_PWRSYS_HIB_TR1 0x40004681 +#define CYREG_PWRSYS_I2C_TR 0x40004682 +#define CYREG_PWRSYS_SLP_TR 0x40004683 +#define CYREG_PWRSYS_BUZZ_TR 0x40004684 +#define CYREG_PWRSYS_WAKE_TR0 0x40004685 +#define CYREG_PWRSYS_WAKE_TR1 0x40004686 +#define CYREG_PWRSYS_BREF_TR 0x40004687 +#define CYREG_PWRSYS_BG_TR 0x40004688 +#define CYREG_PWRSYS_WAKE_TR2 0x40004689 +#define CYREG_PWRSYS_WAKE_TR3 0x4000468a +#define CYDEV_MFGCFG_ILO_BASE 0x40004690 +#define CYDEV_MFGCFG_ILO_SIZE 0x00000002 +#define CYREG_ILO_TR0 0x40004690 +#define CYREG_ILO_TR1 0x40004691 +#define CYDEV_MFGCFG_X32_BASE 0x40004698 +#define CYDEV_MFGCFG_X32_SIZE 0x00000001 +#define CYREG_X32_TR 0x40004698 +#define CYDEV_MFGCFG_IMO_BASE 0x400046a0 +#define CYDEV_MFGCFG_IMO_SIZE 0x00000005 +#define CYREG_IMO_TR0 0x400046a0 +#define CYREG_IMO_TR1 0x400046a1 +#define CYREG_IMO_GAIN 0x400046a2 +#define CYREG_IMO_C36M 0x400046a3 +#define CYREG_IMO_TR2 0x400046a4 +#define CYDEV_MFGCFG_XMHZ_BASE 0x400046a8 +#define CYDEV_MFGCFG_XMHZ_SIZE 0x00000001 +#define CYREG_XMHZ_TR 0x400046a8 +#define CYREG_MFGCFG_DLY 0x400046c0 +#define CYDEV_MFGCFG_MLOGIC_BASE 0x400046e0 +#define CYDEV_MFGCFG_MLOGIC_SIZE 0x0000000d +#define CYREG_MLOGIC_DMPSTR 0x400046e2 +#define CYDEV_MFGCFG_MLOGIC_SEG_BASE 0x400046e4 +#define CYDEV_MFGCFG_MLOGIC_SEG_SIZE 0x00000002 +#define CYREG_MLOGIC_SEG_CR 0x400046e4 +#define CYREG_MLOGIC_SEG_CFG0 0x400046e5 +#define CYREG_MLOGIC_DEBUG 0x400046e8 +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE 0x400046ea +#define CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE 0x00000001 +#define CYREG_MLOGIC_CPU_SCR_CPU_SCR 0x400046ea +#define CYREG_MLOGIC_REV_ID 0x400046ec +#define CYDEV_RESET_BASE 0x400046f0 +#define CYDEV_RESET_SIZE 0x0000000f +#define CYREG_RESET_IPOR_CR0 0x400046f0 +#define CYREG_RESET_IPOR_CR1 0x400046f1 +#define CYREG_RESET_IPOR_CR2 0x400046f2 +#define CYREG_RESET_IPOR_CR3 0x400046f3 +#define CYREG_RESET_CR0 0x400046f4 +#define CYREG_RESET_CR1 0x400046f5 +#define CYREG_RESET_CR2 0x400046f6 +#define CYREG_RESET_CR3 0x400046f7 +#define CYREG_RESET_CR4 0x400046f8 +#define CYREG_RESET_CR5 0x400046f9 +#define CYREG_RESET_SR0 0x400046fa +#define CYREG_RESET_SR1 0x400046fb +#define CYREG_RESET_SR2 0x400046fc +#define CYREG_RESET_SR3 0x400046fd +#define CYREG_RESET_TR 0x400046fe +#define CYDEV_SPC_BASE 0x40004700 +#define CYDEV_SPC_SIZE 0x00000100 +#define CYREG_SPC_FM_EE_CR 0x40004700 +#define CYREG_SPC_FM_EE_WAKE_CNT 0x40004701 +#define CYREG_SPC_EE_SCR 0x40004702 +#define CYREG_SPC_EE_ERR 0x40004703 +#define CYREG_SPC_CPU_DATA 0x40004720 +#define CYREG_SPC_DMA_DATA 0x40004721 +#define CYREG_SPC_SR 0x40004722 +#define CYREG_SPC_CR 0x40004723 +#define CYDEV_SPC_DMM_MAP_BASE 0x40004780 +#define CYDEV_SPC_DMM_MAP_SIZE 0x00000080 +#define CYREG_SPC_DMM_MAP_SRAM_MBASE 0x40004780 +#define CYREG_SPC_DMM_MAP_SRAM_MSIZE 0x00000080 +#define CYDEV_CACHE_BASE 0x40004800 +#define CYDEV_CACHE_SIZE 0x0000009c +#define CYREG_CACHE_CC_CTL 0x40004800 +#define CYREG_CACHE_ECC_CORR 0x40004880 +#define CYREG_CACHE_ECC_ERR 0x40004888 +#define CYREG_CACHE_FLASH_ERR 0x40004890 +#define CYREG_CACHE_HITMISS 0x40004898 +#define CYDEV_I2C_BASE 0x40004900 +#define CYDEV_I2C_SIZE 0x000000e1 +#define CYREG_I2C_XCFG 0x400049c8 +#define CYREG_I2C_ADR 0x400049ca +#define CYREG_I2C_CFG 0x400049d6 +#define CYREG_I2C_CSR 0x400049d7 +#define CYREG_I2C_D 0x400049d8 +#define CYREG_I2C_MCSR 0x400049d9 +#define CYREG_I2C_CLK_DIV1 0x400049db +#define CYREG_I2C_CLK_DIV2 0x400049dc +#define CYREG_I2C_TMOUT_CSR 0x400049dd +#define CYREG_I2C_TMOUT_SR 0x400049de +#define CYREG_I2C_TMOUT_CFG0 0x400049df +#define CYREG_I2C_TMOUT_CFG1 0x400049e0 +#define CYDEV_DEC_BASE 0x40004e00 +#define CYDEV_DEC_SIZE 0x00000015 +#define CYREG_DEC_CR 0x40004e00 +#define CYREG_DEC_SR 0x40004e01 +#define CYREG_DEC_SHIFT1 0x40004e02 +#define CYREG_DEC_SHIFT2 0x40004e03 +#define CYREG_DEC_DR2 0x40004e04 +#define CYREG_DEC_DR2H 0x40004e05 +#define CYREG_DEC_DR1 0x40004e06 +#define CYREG_DEC_OCOR 0x40004e08 +#define CYREG_DEC_OCORM 0x40004e09 +#define CYREG_DEC_OCORH 0x40004e0a +#define CYREG_DEC_GCOR 0x40004e0c +#define CYREG_DEC_GCORH 0x40004e0d +#define CYREG_DEC_GVAL 0x40004e0e +#define CYREG_DEC_OUTSAMP 0x40004e10 +#define CYREG_DEC_OUTSAMPM 0x40004e11 +#define CYREG_DEC_OUTSAMPH 0x40004e12 +#define CYREG_DEC_OUTSAMPS 0x40004e13 +#define CYREG_DEC_COHER 0x40004e14 +#define CYDEV_TMR0_BASE 0x40004f00 +#define CYDEV_TMR0_SIZE 0x0000000c +#define CYREG_TMR0_CFG0 0x40004f00 +#define CYREG_TMR0_CFG1 0x40004f01 +#define CYREG_TMR0_CFG2 0x40004f02 +#define CYREG_TMR0_SR0 0x40004f03 +#define CYREG_TMR0_PER0 0x40004f04 +#define CYREG_TMR0_PER1 0x40004f05 +#define CYREG_TMR0_CNT_CMP0 0x40004f06 +#define CYREG_TMR0_CNT_CMP1 0x40004f07 +#define CYREG_TMR0_CAP0 0x40004f08 +#define CYREG_TMR0_CAP1 0x40004f09 +#define CYREG_TMR0_RT0 0x40004f0a +#define CYREG_TMR0_RT1 0x40004f0b +#define CYDEV_TMR1_BASE 0x40004f0c +#define CYDEV_TMR1_SIZE 0x0000000c +#define CYREG_TMR1_CFG0 0x40004f0c +#define CYREG_TMR1_CFG1 0x40004f0d +#define CYREG_TMR1_CFG2 0x40004f0e +#define CYREG_TMR1_SR0 0x40004f0f +#define CYREG_TMR1_PER0 0x40004f10 +#define CYREG_TMR1_PER1 0x40004f11 +#define CYREG_TMR1_CNT_CMP0 0x40004f12 +#define CYREG_TMR1_CNT_CMP1 0x40004f13 +#define CYREG_TMR1_CAP0 0x40004f14 +#define CYREG_TMR1_CAP1 0x40004f15 +#define CYREG_TMR1_RT0 0x40004f16 +#define CYREG_TMR1_RT1 0x40004f17 +#define CYDEV_TMR2_BASE 0x40004f18 +#define CYDEV_TMR2_SIZE 0x0000000c +#define CYREG_TMR2_CFG0 0x40004f18 +#define CYREG_TMR2_CFG1 0x40004f19 +#define CYREG_TMR2_CFG2 0x40004f1a +#define CYREG_TMR2_SR0 0x40004f1b +#define CYREG_TMR2_PER0 0x40004f1c +#define CYREG_TMR2_PER1 0x40004f1d +#define CYREG_TMR2_CNT_CMP0 0x40004f1e +#define CYREG_TMR2_CNT_CMP1 0x40004f1f +#define CYREG_TMR2_CAP0 0x40004f20 +#define CYREG_TMR2_CAP1 0x40004f21 +#define CYREG_TMR2_RT0 0x40004f22 +#define CYREG_TMR2_RT1 0x40004f23 +#define CYDEV_TMR3_BASE 0x40004f24 +#define CYDEV_TMR3_SIZE 0x0000000c +#define CYREG_TMR3_CFG0 0x40004f24 +#define CYREG_TMR3_CFG1 0x40004f25 +#define CYREG_TMR3_CFG2 0x40004f26 +#define CYREG_TMR3_SR0 0x40004f27 +#define CYREG_TMR3_PER0 0x40004f28 +#define CYREG_TMR3_PER1 0x40004f29 +#define CYREG_TMR3_CNT_CMP0 0x40004f2a +#define CYREG_TMR3_CNT_CMP1 0x40004f2b +#define CYREG_TMR3_CAP0 0x40004f2c +#define CYREG_TMR3_CAP1 0x40004f2d +#define CYREG_TMR3_RT0 0x40004f2e +#define CYREG_TMR3_RT1 0x40004f2f +#define CYDEV_IO_BASE 0x40005000 +#define CYDEV_IO_SIZE 0x00000200 +#define CYDEV_IO_PC_BASE 0x40005000 +#define CYDEV_IO_PC_SIZE 0x00000080 +#define CYDEV_IO_PC_PRT0_BASE 0x40005000 +#define CYDEV_IO_PC_PRT0_SIZE 0x00000008 +#define CYREG_PRT0_PC0 0x40005000 +#define CYREG_PRT0_PC1 0x40005001 +#define CYREG_PRT0_PC2 0x40005002 +#define CYREG_PRT0_PC3 0x40005003 +#define CYREG_PRT0_PC4 0x40005004 +#define CYREG_PRT0_PC5 0x40005005 +#define CYREG_PRT0_PC6 0x40005006 +#define CYREG_PRT0_PC7 0x40005007 +#define CYDEV_IO_PC_PRT1_BASE 0x40005008 +#define CYDEV_IO_PC_PRT1_SIZE 0x00000008 +#define CYREG_PRT1_PC0 0x40005008 +#define CYREG_PRT1_PC1 0x40005009 +#define CYREG_PRT1_PC2 0x4000500a +#define CYREG_PRT1_PC3 0x4000500b +#define CYREG_PRT1_PC4 0x4000500c +#define CYREG_PRT1_PC5 0x4000500d +#define CYREG_PRT1_PC6 0x4000500e +#define CYREG_PRT1_PC7 0x4000500f +#define CYDEV_IO_PC_PRT2_BASE 0x40005010 +#define CYDEV_IO_PC_PRT2_SIZE 0x00000008 +#define CYREG_PRT2_PC0 0x40005010 +#define CYREG_PRT2_PC1 0x40005011 +#define CYREG_PRT2_PC2 0x40005012 +#define CYREG_PRT2_PC3 0x40005013 +#define CYREG_PRT2_PC4 0x40005014 +#define CYREG_PRT2_PC5 0x40005015 +#define CYREG_PRT2_PC6 0x40005016 +#define CYREG_PRT2_PC7 0x40005017 +#define CYDEV_IO_PC_PRT3_BASE 0x40005018 +#define CYDEV_IO_PC_PRT3_SIZE 0x00000008 +#define CYREG_PRT3_PC0 0x40005018 +#define CYREG_PRT3_PC1 0x40005019 +#define CYREG_PRT3_PC2 0x4000501a +#define CYREG_PRT3_PC3 0x4000501b +#define CYREG_PRT3_PC4 0x4000501c +#define CYREG_PRT3_PC5 0x4000501d +#define CYREG_PRT3_PC6 0x4000501e +#define CYREG_PRT3_PC7 0x4000501f +#define CYDEV_IO_PC_PRT4_BASE 0x40005020 +#define CYDEV_IO_PC_PRT4_SIZE 0x00000008 +#define CYREG_PRT4_PC0 0x40005020 +#define CYREG_PRT4_PC1 0x40005021 +#define CYREG_PRT4_PC2 0x40005022 +#define CYREG_PRT4_PC3 0x40005023 +#define CYREG_PRT4_PC4 0x40005024 +#define CYREG_PRT4_PC5 0x40005025 +#define CYREG_PRT4_PC6 0x40005026 +#define CYREG_PRT4_PC7 0x40005027 +#define CYDEV_IO_PC_PRT5_BASE 0x40005028 +#define CYDEV_IO_PC_PRT5_SIZE 0x00000008 +#define CYREG_PRT5_PC0 0x40005028 +#define CYREG_PRT5_PC1 0x40005029 +#define CYREG_PRT5_PC2 0x4000502a +#define CYREG_PRT5_PC3 0x4000502b +#define CYREG_PRT5_PC4 0x4000502c +#define CYREG_PRT5_PC5 0x4000502d +#define CYREG_PRT5_PC6 0x4000502e +#define CYREG_PRT5_PC7 0x4000502f +#define CYDEV_IO_PC_PRT6_BASE 0x40005030 +#define CYDEV_IO_PC_PRT6_SIZE 0x00000008 +#define CYREG_PRT6_PC0 0x40005030 +#define CYREG_PRT6_PC1 0x40005031 +#define CYREG_PRT6_PC2 0x40005032 +#define CYREG_PRT6_PC3 0x40005033 +#define CYREG_PRT6_PC4 0x40005034 +#define CYREG_PRT6_PC5 0x40005035 +#define CYREG_PRT6_PC6 0x40005036 +#define CYREG_PRT6_PC7 0x40005037 +#define CYDEV_IO_PC_PRT12_BASE 0x40005060 +#define CYDEV_IO_PC_PRT12_SIZE 0x00000008 +#define CYREG_PRT12_PC0 0x40005060 +#define CYREG_PRT12_PC1 0x40005061 +#define CYREG_PRT12_PC2 0x40005062 +#define CYREG_PRT12_PC3 0x40005063 +#define CYREG_PRT12_PC4 0x40005064 +#define CYREG_PRT12_PC5 0x40005065 +#define CYREG_PRT12_PC6 0x40005066 +#define CYREG_PRT12_PC7 0x40005067 +#define CYDEV_IO_PC_PRT15_BASE 0x40005078 +#define CYDEV_IO_PC_PRT15_SIZE 0x00000006 +#define CYREG_IO_PC_PRT15_PC0 0x40005078 +#define CYREG_IO_PC_PRT15_PC1 0x40005079 +#define CYREG_IO_PC_PRT15_PC2 0x4000507a +#define CYREG_IO_PC_PRT15_PC3 0x4000507b +#define CYREG_IO_PC_PRT15_PC4 0x4000507c +#define CYREG_IO_PC_PRT15_PC5 0x4000507d +#define CYDEV_IO_PC_PRT15_7_6_BASE 0x4000507e +#define CYDEV_IO_PC_PRT15_7_6_SIZE 0x00000002 +#define CYREG_IO_PC_PRT15_7_6_PC0 0x4000507e +#define CYREG_IO_PC_PRT15_7_6_PC1 0x4000507f +#define CYDEV_IO_DR_BASE 0x40005080 +#define CYDEV_IO_DR_SIZE 0x00000010 +#define CYDEV_IO_DR_PRT0_BASE 0x40005080 +#define CYDEV_IO_DR_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_DR_ALIAS 0x40005080 +#define CYDEV_IO_DR_PRT1_BASE 0x40005081 +#define CYDEV_IO_DR_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_DR_ALIAS 0x40005081 +#define CYDEV_IO_DR_PRT2_BASE 0x40005082 +#define CYDEV_IO_DR_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_DR_ALIAS 0x40005082 +#define CYDEV_IO_DR_PRT3_BASE 0x40005083 +#define CYDEV_IO_DR_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_DR_ALIAS 0x40005083 +#define CYDEV_IO_DR_PRT4_BASE 0x40005084 +#define CYDEV_IO_DR_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_DR_ALIAS 0x40005084 +#define CYDEV_IO_DR_PRT5_BASE 0x40005085 +#define CYDEV_IO_DR_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_DR_ALIAS 0x40005085 +#define CYDEV_IO_DR_PRT6_BASE 0x40005086 +#define CYDEV_IO_DR_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_DR_ALIAS 0x40005086 +#define CYDEV_IO_DR_PRT12_BASE 0x4000508c +#define CYDEV_IO_DR_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_DR_ALIAS 0x4000508c +#define CYDEV_IO_DR_PRT15_BASE 0x4000508f +#define CYDEV_IO_DR_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_DR_15_ALIAS 0x4000508f +#define CYDEV_IO_PS_BASE 0x40005090 +#define CYDEV_IO_PS_SIZE 0x00000010 +#define CYDEV_IO_PS_PRT0_BASE 0x40005090 +#define CYDEV_IO_PS_PRT0_SIZE 0x00000001 +#define CYREG_PRT0_PS_ALIAS 0x40005090 +#define CYDEV_IO_PS_PRT1_BASE 0x40005091 +#define CYDEV_IO_PS_PRT1_SIZE 0x00000001 +#define CYREG_PRT1_PS_ALIAS 0x40005091 +#define CYDEV_IO_PS_PRT2_BASE 0x40005092 +#define CYDEV_IO_PS_PRT2_SIZE 0x00000001 +#define CYREG_PRT2_PS_ALIAS 0x40005092 +#define CYDEV_IO_PS_PRT3_BASE 0x40005093 +#define CYDEV_IO_PS_PRT3_SIZE 0x00000001 +#define CYREG_PRT3_PS_ALIAS 0x40005093 +#define CYDEV_IO_PS_PRT4_BASE 0x40005094 +#define CYDEV_IO_PS_PRT4_SIZE 0x00000001 +#define CYREG_PRT4_PS_ALIAS 0x40005094 +#define CYDEV_IO_PS_PRT5_BASE 0x40005095 +#define CYDEV_IO_PS_PRT5_SIZE 0x00000001 +#define CYREG_PRT5_PS_ALIAS 0x40005095 +#define CYDEV_IO_PS_PRT6_BASE 0x40005096 +#define CYDEV_IO_PS_PRT6_SIZE 0x00000001 +#define CYREG_PRT6_PS_ALIAS 0x40005096 +#define CYDEV_IO_PS_PRT12_BASE 0x4000509c +#define CYDEV_IO_PS_PRT12_SIZE 0x00000001 +#define CYREG_PRT12_PS_ALIAS 0x4000509c +#define CYDEV_IO_PS_PRT15_BASE 0x4000509f +#define CYDEV_IO_PS_PRT15_SIZE 0x00000001 +#define CYREG_PRT15_PS15_ALIAS 0x4000509f +#define CYDEV_IO_PRT_BASE 0x40005100 +#define CYDEV_IO_PRT_SIZE 0x00000100 +#define CYDEV_IO_PRT_PRT0_BASE 0x40005100 +#define CYDEV_IO_PRT_PRT0_SIZE 0x00000010 +#define CYREG_PRT0_DR 0x40005100 +#define CYREG_PRT0_PS 0x40005101 +#define CYREG_PRT0_DM0 0x40005102 +#define CYREG_PRT0_DM1 0x40005103 +#define CYREG_PRT0_DM2 0x40005104 +#define CYREG_PRT0_SLW 0x40005105 +#define CYREG_PRT0_BYP 0x40005106 +#define CYREG_PRT0_BIE 0x40005107 +#define CYREG_PRT0_INP_DIS 0x40005108 +#define CYREG_PRT0_CTL 0x40005109 +#define CYREG_PRT0_PRT 0x4000510a +#define CYREG_PRT0_BIT_MASK 0x4000510b +#define CYREG_PRT0_AMUX 0x4000510c +#define CYREG_PRT0_AG 0x4000510d +#define CYREG_PRT0_LCD_COM_SEG 0x4000510e +#define CYREG_PRT0_LCD_EN 0x4000510f +#define CYDEV_IO_PRT_PRT1_BASE 0x40005110 +#define CYDEV_IO_PRT_PRT1_SIZE 0x00000010 +#define CYREG_PRT1_DR 0x40005110 +#define CYREG_PRT1_PS 0x40005111 +#define CYREG_PRT1_DM0 0x40005112 +#define CYREG_PRT1_DM1 0x40005113 +#define CYREG_PRT1_DM2 0x40005114 +#define CYREG_PRT1_SLW 0x40005115 +#define CYREG_PRT1_BYP 0x40005116 +#define CYREG_PRT1_BIE 0x40005117 +#define CYREG_PRT1_INP_DIS 0x40005118 +#define CYREG_PRT1_CTL 0x40005119 +#define CYREG_PRT1_PRT 0x4000511a +#define CYREG_PRT1_BIT_MASK 0x4000511b +#define CYREG_PRT1_AMUX 0x4000511c +#define CYREG_PRT1_AG 0x4000511d +#define CYREG_PRT1_LCD_COM_SEG 0x4000511e +#define CYREG_PRT1_LCD_EN 0x4000511f +#define CYDEV_IO_PRT_PRT2_BASE 0x40005120 +#define CYDEV_IO_PRT_PRT2_SIZE 0x00000010 +#define CYREG_PRT2_DR 0x40005120 +#define CYREG_PRT2_PS 0x40005121 +#define CYREG_PRT2_DM0 0x40005122 +#define CYREG_PRT2_DM1 0x40005123 +#define CYREG_PRT2_DM2 0x40005124 +#define CYREG_PRT2_SLW 0x40005125 +#define CYREG_PRT2_BYP 0x40005126 +#define CYREG_PRT2_BIE 0x40005127 +#define CYREG_PRT2_INP_DIS 0x40005128 +#define CYREG_PRT2_CTL 0x40005129 +#define CYREG_PRT2_PRT 0x4000512a +#define CYREG_PRT2_BIT_MASK 0x4000512b +#define CYREG_PRT2_AMUX 0x4000512c +#define CYREG_PRT2_AG 0x4000512d +#define CYREG_PRT2_LCD_COM_SEG 0x4000512e +#define CYREG_PRT2_LCD_EN 0x4000512f +#define CYDEV_IO_PRT_PRT3_BASE 0x40005130 +#define CYDEV_IO_PRT_PRT3_SIZE 0x00000010 +#define CYREG_PRT3_DR 0x40005130 +#define CYREG_PRT3_PS 0x40005131 +#define CYREG_PRT3_DM0 0x40005132 +#define CYREG_PRT3_DM1 0x40005133 +#define CYREG_PRT3_DM2 0x40005134 +#define CYREG_PRT3_SLW 0x40005135 +#define CYREG_PRT3_BYP 0x40005136 +#define CYREG_PRT3_BIE 0x40005137 +#define CYREG_PRT3_INP_DIS 0x40005138 +#define CYREG_PRT3_CTL 0x40005139 +#define CYREG_PRT3_PRT 0x4000513a +#define CYREG_PRT3_BIT_MASK 0x4000513b +#define CYREG_PRT3_AMUX 0x4000513c +#define CYREG_PRT3_AG 0x4000513d +#define CYREG_PRT3_LCD_COM_SEG 0x4000513e +#define CYREG_PRT3_LCD_EN 0x4000513f +#define CYDEV_IO_PRT_PRT4_BASE 0x40005140 +#define CYDEV_IO_PRT_PRT4_SIZE 0x00000010 +#define CYREG_PRT4_DR 0x40005140 +#define CYREG_PRT4_PS 0x40005141 +#define CYREG_PRT4_DM0 0x40005142 +#define CYREG_PRT4_DM1 0x40005143 +#define CYREG_PRT4_DM2 0x40005144 +#define CYREG_PRT4_SLW 0x40005145 +#define CYREG_PRT4_BYP 0x40005146 +#define CYREG_PRT4_BIE 0x40005147 +#define CYREG_PRT4_INP_DIS 0x40005148 +#define CYREG_PRT4_CTL 0x40005149 +#define CYREG_PRT4_PRT 0x4000514a +#define CYREG_PRT4_BIT_MASK 0x4000514b +#define CYREG_PRT4_AMUX 0x4000514c +#define CYREG_PRT4_AG 0x4000514d +#define CYREG_PRT4_LCD_COM_SEG 0x4000514e +#define CYREG_PRT4_LCD_EN 0x4000514f +#define CYDEV_IO_PRT_PRT5_BASE 0x40005150 +#define CYDEV_IO_PRT_PRT5_SIZE 0x00000010 +#define CYREG_PRT5_DR 0x40005150 +#define CYREG_PRT5_PS 0x40005151 +#define CYREG_PRT5_DM0 0x40005152 +#define CYREG_PRT5_DM1 0x40005153 +#define CYREG_PRT5_DM2 0x40005154 +#define CYREG_PRT5_SLW 0x40005155 +#define CYREG_PRT5_BYP 0x40005156 +#define CYREG_PRT5_BIE 0x40005157 +#define CYREG_PRT5_INP_DIS 0x40005158 +#define CYREG_PRT5_CTL 0x40005159 +#define CYREG_PRT5_PRT 0x4000515a +#define CYREG_PRT5_BIT_MASK 0x4000515b +#define CYREG_PRT5_AMUX 0x4000515c +#define CYREG_PRT5_AG 0x4000515d +#define CYREG_PRT5_LCD_COM_SEG 0x4000515e +#define CYREG_PRT5_LCD_EN 0x4000515f +#define CYDEV_IO_PRT_PRT6_BASE 0x40005160 +#define CYDEV_IO_PRT_PRT6_SIZE 0x00000010 +#define CYREG_PRT6_DR 0x40005160 +#define CYREG_PRT6_PS 0x40005161 +#define CYREG_PRT6_DM0 0x40005162 +#define CYREG_PRT6_DM1 0x40005163 +#define CYREG_PRT6_DM2 0x40005164 +#define CYREG_PRT6_SLW 0x40005165 +#define CYREG_PRT6_BYP 0x40005166 +#define CYREG_PRT6_BIE 0x40005167 +#define CYREG_PRT6_INP_DIS 0x40005168 +#define CYREG_PRT6_CTL 0x40005169 +#define CYREG_PRT6_PRT 0x4000516a +#define CYREG_PRT6_BIT_MASK 0x4000516b +#define CYREG_PRT6_AMUX 0x4000516c +#define CYREG_PRT6_AG 0x4000516d +#define CYREG_PRT6_LCD_COM_SEG 0x4000516e +#define CYREG_PRT6_LCD_EN 0x4000516f +#define CYDEV_IO_PRT_PRT12_BASE 0x400051c0 +#define CYDEV_IO_PRT_PRT12_SIZE 0x00000010 +#define CYREG_PRT12_DR 0x400051c0 +#define CYREG_PRT12_PS 0x400051c1 +#define CYREG_PRT12_DM0 0x400051c2 +#define CYREG_PRT12_DM1 0x400051c3 +#define CYREG_PRT12_DM2 0x400051c4 +#define CYREG_PRT12_SLW 0x400051c5 +#define CYREG_PRT12_BYP 0x400051c6 +#define CYREG_PRT12_BIE 0x400051c7 +#define CYREG_PRT12_INP_DIS 0x400051c8 +#define CYREG_PRT12_SIO_HYST_EN 0x400051c9 +#define CYREG_PRT12_PRT 0x400051ca +#define CYREG_PRT12_BIT_MASK 0x400051cb +#define CYREG_PRT12_SIO_REG_HIFREQ 0x400051cc +#define CYREG_PRT12_AG 0x400051cd +#define CYREG_PRT12_SIO_CFG 0x400051ce +#define CYREG_PRT12_SIO_DIFF 0x400051cf +#define CYDEV_IO_PRT_PRT15_BASE 0x400051f0 +#define CYDEV_IO_PRT_PRT15_SIZE 0x00000010 +#define CYREG_PRT15_DR 0x400051f0 +#define CYREG_PRT15_PS 0x400051f1 +#define CYREG_PRT15_DM0 0x400051f2 +#define CYREG_PRT15_DM1 0x400051f3 +#define CYREG_PRT15_DM2 0x400051f4 +#define CYREG_PRT15_SLW 0x400051f5 +#define CYREG_PRT15_BYP 0x400051f6 +#define CYREG_PRT15_BIE 0x400051f7 +#define CYREG_PRT15_INP_DIS 0x400051f8 +#define CYREG_PRT15_CTL 0x400051f9 +#define CYREG_PRT15_PRT 0x400051fa +#define CYREG_PRT15_BIT_MASK 0x400051fb +#define CYREG_PRT15_AMUX 0x400051fc +#define CYREG_PRT15_AG 0x400051fd +#define CYREG_PRT15_LCD_COM_SEG 0x400051fe +#define CYREG_PRT15_LCD_EN 0x400051ff +#define CYDEV_PRTDSI_BASE 0x40005200 +#define CYDEV_PRTDSI_SIZE 0x0000007f +#define CYDEV_PRTDSI_PRT0_BASE 0x40005200 +#define CYDEV_PRTDSI_PRT0_SIZE 0x00000007 +#define CYREG_PRT0_OUT_SEL0 0x40005200 +#define CYREG_PRT0_OUT_SEL1 0x40005201 +#define CYREG_PRT0_OE_SEL0 0x40005202 +#define CYREG_PRT0_OE_SEL1 0x40005203 +#define CYREG_PRT0_DBL_SYNC_IN 0x40005204 +#define CYREG_PRT0_SYNC_OUT 0x40005205 +#define CYREG_PRT0_CAPS_SEL 0x40005206 +#define CYDEV_PRTDSI_PRT1_BASE 0x40005208 +#define CYDEV_PRTDSI_PRT1_SIZE 0x00000007 +#define CYREG_PRT1_OUT_SEL0 0x40005208 +#define CYREG_PRT1_OUT_SEL1 0x40005209 +#define CYREG_PRT1_OE_SEL0 0x4000520a +#define CYREG_PRT1_OE_SEL1 0x4000520b +#define CYREG_PRT1_DBL_SYNC_IN 0x4000520c +#define CYREG_PRT1_SYNC_OUT 0x4000520d +#define CYREG_PRT1_CAPS_SEL 0x4000520e +#define CYDEV_PRTDSI_PRT2_BASE 0x40005210 +#define CYDEV_PRTDSI_PRT2_SIZE 0x00000007 +#define CYREG_PRT2_OUT_SEL0 0x40005210 +#define CYREG_PRT2_OUT_SEL1 0x40005211 +#define CYREG_PRT2_OE_SEL0 0x40005212 +#define CYREG_PRT2_OE_SEL1 0x40005213 +#define CYREG_PRT2_DBL_SYNC_IN 0x40005214 +#define CYREG_PRT2_SYNC_OUT 0x40005215 +#define CYREG_PRT2_CAPS_SEL 0x40005216 +#define CYDEV_PRTDSI_PRT3_BASE 0x40005218 +#define CYDEV_PRTDSI_PRT3_SIZE 0x00000007 +#define CYREG_PRT3_OUT_SEL0 0x40005218 +#define CYREG_PRT3_OUT_SEL1 0x40005219 +#define CYREG_PRT3_OE_SEL0 0x4000521a +#define CYREG_PRT3_OE_SEL1 0x4000521b +#define CYREG_PRT3_DBL_SYNC_IN 0x4000521c +#define CYREG_PRT3_SYNC_OUT 0x4000521d +#define CYREG_PRT3_CAPS_SEL 0x4000521e +#define CYDEV_PRTDSI_PRT4_BASE 0x40005220 +#define CYDEV_PRTDSI_PRT4_SIZE 0x00000007 +#define CYREG_PRT4_OUT_SEL0 0x40005220 +#define CYREG_PRT4_OUT_SEL1 0x40005221 +#define CYREG_PRT4_OE_SEL0 0x40005222 +#define CYREG_PRT4_OE_SEL1 0x40005223 +#define CYREG_PRT4_DBL_SYNC_IN 0x40005224 +#define CYREG_PRT4_SYNC_OUT 0x40005225 +#define CYREG_PRT4_CAPS_SEL 0x40005226 +#define CYDEV_PRTDSI_PRT5_BASE 0x40005228 +#define CYDEV_PRTDSI_PRT5_SIZE 0x00000007 +#define CYREG_PRT5_OUT_SEL0 0x40005228 +#define CYREG_PRT5_OUT_SEL1 0x40005229 +#define CYREG_PRT5_OE_SEL0 0x4000522a +#define CYREG_PRT5_OE_SEL1 0x4000522b +#define CYREG_PRT5_DBL_SYNC_IN 0x4000522c +#define CYREG_PRT5_SYNC_OUT 0x4000522d +#define CYREG_PRT5_CAPS_SEL 0x4000522e +#define CYDEV_PRTDSI_PRT6_BASE 0x40005230 +#define CYDEV_PRTDSI_PRT6_SIZE 0x00000007 +#define CYREG_PRT6_OUT_SEL0 0x40005230 +#define CYREG_PRT6_OUT_SEL1 0x40005231 +#define CYREG_PRT6_OE_SEL0 0x40005232 +#define CYREG_PRT6_OE_SEL1 0x40005233 +#define CYREG_PRT6_DBL_SYNC_IN 0x40005234 +#define CYREG_PRT6_SYNC_OUT 0x40005235 +#define CYREG_PRT6_CAPS_SEL 0x40005236 +#define CYDEV_PRTDSI_PRT12_BASE 0x40005260 +#define CYDEV_PRTDSI_PRT12_SIZE 0x00000006 +#define CYREG_PRT12_OUT_SEL0 0x40005260 +#define CYREG_PRT12_OUT_SEL1 0x40005261 +#define CYREG_PRT12_OE_SEL0 0x40005262 +#define CYREG_PRT12_OE_SEL1 0x40005263 +#define CYREG_PRT12_DBL_SYNC_IN 0x40005264 +#define CYREG_PRT12_SYNC_OUT 0x40005265 +#define CYDEV_PRTDSI_PRT15_BASE 0x40005278 +#define CYDEV_PRTDSI_PRT15_SIZE 0x00000007 +#define CYREG_PRT15_OUT_SEL0 0x40005278 +#define CYREG_PRT15_OUT_SEL1 0x40005279 +#define CYREG_PRT15_OE_SEL0 0x4000527a +#define CYREG_PRT15_OE_SEL1 0x4000527b +#define CYREG_PRT15_DBL_SYNC_IN 0x4000527c +#define CYREG_PRT15_SYNC_OUT 0x4000527d +#define CYREG_PRT15_CAPS_SEL 0x4000527e +#define CYDEV_EMIF_BASE 0x40005400 +#define CYDEV_EMIF_SIZE 0x00000007 +#define CYREG_EMIF_NO_UDB 0x40005400 +#define CYREG_EMIF_RP_WAIT_STATES 0x40005401 +#define CYREG_EMIF_MEM_DWN 0x40005402 +#define CYREG_EMIF_MEMCLK_DIV 0x40005403 +#define CYREG_EMIF_CLOCK_EN 0x40005404 +#define CYREG_EMIF_EM_TYPE 0x40005405 +#define CYREG_EMIF_WP_WAIT_STATES 0x40005406 +#define CYDEV_ANAIF_BASE 0x40005800 +#define CYDEV_ANAIF_SIZE 0x000003a9 +#define CYDEV_ANAIF_CFG_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SIZE 0x0000010f +#define CYDEV_ANAIF_CFG_SC0_BASE 0x40005800 +#define CYDEV_ANAIF_CFG_SC0_SIZE 0x00000003 +#define CYREG_SC0_CR0 0x40005800 +#define CYREG_SC0_CR1 0x40005801 +#define CYREG_SC0_CR2 0x40005802 +#define CYDEV_ANAIF_CFG_SC1_BASE 0x40005804 +#define CYDEV_ANAIF_CFG_SC1_SIZE 0x00000003 +#define CYREG_SC1_CR0 0x40005804 +#define CYREG_SC1_CR1 0x40005805 +#define CYREG_SC1_CR2 0x40005806 +#define CYDEV_ANAIF_CFG_SC2_BASE 0x40005808 +#define CYDEV_ANAIF_CFG_SC2_SIZE 0x00000003 +#define CYREG_SC2_CR0 0x40005808 +#define CYREG_SC2_CR1 0x40005809 +#define CYREG_SC2_CR2 0x4000580a +#define CYDEV_ANAIF_CFG_SC3_BASE 0x4000580c +#define CYDEV_ANAIF_CFG_SC3_SIZE 0x00000003 +#define CYREG_SC3_CR0 0x4000580c +#define CYREG_SC3_CR1 0x4000580d +#define CYREG_SC3_CR2 0x4000580e +#define CYDEV_ANAIF_CFG_DAC0_BASE 0x40005820 +#define CYDEV_ANAIF_CFG_DAC0_SIZE 0x00000003 +#define CYREG_DAC0_CR0 0x40005820 +#define CYREG_DAC0_CR1 0x40005821 +#define CYREG_DAC0_TST 0x40005822 +#define CYDEV_ANAIF_CFG_DAC1_BASE 0x40005824 +#define CYDEV_ANAIF_CFG_DAC1_SIZE 0x00000003 +#define CYREG_DAC1_CR0 0x40005824 +#define CYREG_DAC1_CR1 0x40005825 +#define CYREG_DAC1_TST 0x40005826 +#define CYDEV_ANAIF_CFG_DAC2_BASE 0x40005828 +#define CYDEV_ANAIF_CFG_DAC2_SIZE 0x00000003 +#define CYREG_DAC2_CR0 0x40005828 +#define CYREG_DAC2_CR1 0x40005829 +#define CYREG_DAC2_TST 0x4000582a +#define CYDEV_ANAIF_CFG_DAC3_BASE 0x4000582c +#define CYDEV_ANAIF_CFG_DAC3_SIZE 0x00000003 +#define CYREG_DAC3_CR0 0x4000582c +#define CYREG_DAC3_CR1 0x4000582d +#define CYREG_DAC3_TST 0x4000582e +#define CYDEV_ANAIF_CFG_CMP0_BASE 0x40005840 +#define CYDEV_ANAIF_CFG_CMP0_SIZE 0x00000001 +#define CYREG_CMP0_CR 0x40005840 +#define CYDEV_ANAIF_CFG_CMP1_BASE 0x40005841 +#define CYDEV_ANAIF_CFG_CMP1_SIZE 0x00000001 +#define CYREG_CMP1_CR 0x40005841 +#define CYDEV_ANAIF_CFG_CMP2_BASE 0x40005842 +#define CYDEV_ANAIF_CFG_CMP2_SIZE 0x00000001 +#define CYREG_CMP2_CR 0x40005842 +#define CYDEV_ANAIF_CFG_CMP3_BASE 0x40005843 +#define CYDEV_ANAIF_CFG_CMP3_SIZE 0x00000001 +#define CYREG_CMP3_CR 0x40005843 +#define CYDEV_ANAIF_CFG_LUT0_BASE 0x40005848 +#define CYDEV_ANAIF_CFG_LUT0_SIZE 0x00000002 +#define CYREG_LUT0_CR 0x40005848 +#define CYREG_LUT0_MX 0x40005849 +#define CYDEV_ANAIF_CFG_LUT1_BASE 0x4000584a +#define CYDEV_ANAIF_CFG_LUT1_SIZE 0x00000002 +#define CYREG_LUT1_CR 0x4000584a +#define CYREG_LUT1_MX 0x4000584b +#define CYDEV_ANAIF_CFG_LUT2_BASE 0x4000584c +#define CYDEV_ANAIF_CFG_LUT2_SIZE 0x00000002 +#define CYREG_LUT2_CR 0x4000584c +#define CYREG_LUT2_MX 0x4000584d +#define CYDEV_ANAIF_CFG_LUT3_BASE 0x4000584e +#define CYDEV_ANAIF_CFG_LUT3_SIZE 0x00000002 +#define CYREG_LUT3_CR 0x4000584e +#define CYREG_LUT3_MX 0x4000584f +#define CYDEV_ANAIF_CFG_OPAMP0_BASE 0x40005858 +#define CYDEV_ANAIF_CFG_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_CR 0x40005858 +#define CYREG_OPAMP0_RSVD 0x40005859 +#define CYDEV_ANAIF_CFG_OPAMP1_BASE 0x4000585a +#define CYDEV_ANAIF_CFG_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_CR 0x4000585a +#define CYREG_OPAMP1_RSVD 0x4000585b +#define CYDEV_ANAIF_CFG_OPAMP2_BASE 0x4000585c +#define CYDEV_ANAIF_CFG_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_CR 0x4000585c +#define CYREG_OPAMP2_RSVD 0x4000585d +#define CYDEV_ANAIF_CFG_OPAMP3_BASE 0x4000585e +#define CYDEV_ANAIF_CFG_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_CR 0x4000585e +#define CYREG_OPAMP3_RSVD 0x4000585f +#define CYDEV_ANAIF_CFG_LCDDAC_BASE 0x40005868 +#define CYDEV_ANAIF_CFG_LCDDAC_SIZE 0x00000002 +#define CYREG_LCDDAC_CR0 0x40005868 +#define CYREG_LCDDAC_CR1 0x40005869 +#define CYDEV_ANAIF_CFG_LCDDRV_BASE 0x4000586a +#define CYDEV_ANAIF_CFG_LCDDRV_SIZE 0x00000001 +#define CYREG_LCDDRV_CR 0x4000586a +#define CYDEV_ANAIF_CFG_LCDTMR_BASE 0x4000586b +#define CYDEV_ANAIF_CFG_LCDTMR_SIZE 0x00000001 +#define CYREG_LCDTMR_CFG 0x4000586b +#define CYDEV_ANAIF_CFG_BG_BASE 0x4000586c +#define CYDEV_ANAIF_CFG_BG_SIZE 0x00000004 +#define CYREG_BG_CR0 0x4000586c +#define CYREG_BG_RSVD 0x4000586d +#define CYREG_BG_DFT0 0x4000586e +#define CYREG_BG_DFT1 0x4000586f +#define CYDEV_ANAIF_CFG_CAPSL_BASE 0x40005870 +#define CYDEV_ANAIF_CFG_CAPSL_SIZE 0x00000002 +#define CYREG_CAPSL_CFG0 0x40005870 +#define CYREG_CAPSL_CFG1 0x40005871 +#define CYDEV_ANAIF_CFG_CAPSR_BASE 0x40005872 +#define CYDEV_ANAIF_CFG_CAPSR_SIZE 0x00000002 +#define CYREG_CAPSR_CFG0 0x40005872 +#define CYREG_CAPSR_CFG1 0x40005873 +#define CYDEV_ANAIF_CFG_PUMP_BASE 0x40005876 +#define CYDEV_ANAIF_CFG_PUMP_SIZE 0x00000002 +#define CYREG_PUMP_CR0 0x40005876 +#define CYREG_PUMP_CR1 0x40005877 +#define CYDEV_ANAIF_CFG_LPF0_BASE 0x40005878 +#define CYDEV_ANAIF_CFG_LPF0_SIZE 0x00000002 +#define CYREG_LPF0_CR0 0x40005878 +#define CYREG_LPF0_RSVD 0x40005879 +#define CYDEV_ANAIF_CFG_LPF1_BASE 0x4000587a +#define CYDEV_ANAIF_CFG_LPF1_SIZE 0x00000002 +#define CYREG_LPF1_CR0 0x4000587a +#define CYREG_LPF1_RSVD 0x4000587b +#define CYDEV_ANAIF_CFG_MISC_BASE 0x4000587c +#define CYDEV_ANAIF_CFG_MISC_SIZE 0x00000001 +#define CYREG_ANAIF_CFG_MISC_CR0 0x4000587c +#define CYDEV_ANAIF_CFG_DSM0_BASE 0x40005880 +#define CYDEV_ANAIF_CFG_DSM0_SIZE 0x00000020 +#define CYREG_DSM0_CR0 0x40005880 +#define CYREG_DSM0_CR1 0x40005881 +#define CYREG_DSM0_CR2 0x40005882 +#define CYREG_DSM0_CR3 0x40005883 +#define CYREG_DSM0_CR4 0x40005884 +#define CYREG_DSM0_CR5 0x40005885 +#define CYREG_DSM0_CR6 0x40005886 +#define CYREG_DSM0_CR7 0x40005887 +#define CYREG_DSM0_CR8 0x40005888 +#define CYREG_DSM0_CR9 0x40005889 +#define CYREG_DSM0_CR10 0x4000588a +#define CYREG_DSM0_CR11 0x4000588b +#define CYREG_DSM0_CR12 0x4000588c +#define CYREG_DSM0_CR13 0x4000588d +#define CYREG_DSM0_CR14 0x4000588e +#define CYREG_DSM0_CR15 0x4000588f +#define CYREG_DSM0_CR16 0x40005890 +#define CYREG_DSM0_CR17 0x40005891 +#define CYREG_DSM0_REF0 0x40005892 +#define CYREG_DSM0_REF1 0x40005893 +#define CYREG_DSM0_REF2 0x40005894 +#define CYREG_DSM0_REF3 0x40005895 +#define CYREG_DSM0_DEM0 0x40005896 +#define CYREG_DSM0_DEM1 0x40005897 +#define CYREG_DSM0_TST0 0x40005898 +#define CYREG_DSM0_TST1 0x40005899 +#define CYREG_DSM0_BUF0 0x4000589a +#define CYREG_DSM0_BUF1 0x4000589b +#define CYREG_DSM0_BUF2 0x4000589c +#define CYREG_DSM0_BUF3 0x4000589d +#define CYREG_DSM0_MISC 0x4000589e +#define CYREG_DSM0_RSVD1 0x4000589f +#define CYDEV_ANAIF_CFG_SAR0_BASE 0x40005900 +#define CYDEV_ANAIF_CFG_SAR0_SIZE 0x00000007 +#define CYREG_SAR0_CSR0 0x40005900 +#define CYREG_SAR0_CSR1 0x40005901 +#define CYREG_SAR0_CSR2 0x40005902 +#define CYREG_SAR0_CSR3 0x40005903 +#define CYREG_SAR0_CSR4 0x40005904 +#define CYREG_SAR0_CSR5 0x40005905 +#define CYREG_SAR0_CSR6 0x40005906 +#define CYDEV_ANAIF_CFG_SAR1_BASE 0x40005908 +#define CYDEV_ANAIF_CFG_SAR1_SIZE 0x00000007 +#define CYREG_SAR1_CSR0 0x40005908 +#define CYREG_SAR1_CSR1 0x40005909 +#define CYREG_SAR1_CSR2 0x4000590a +#define CYREG_SAR1_CSR3 0x4000590b +#define CYREG_SAR1_CSR4 0x4000590c +#define CYREG_SAR1_CSR5 0x4000590d +#define CYREG_SAR1_CSR6 0x4000590e +#define CYDEV_ANAIF_RT_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SIZE 0x00000162 +#define CYDEV_ANAIF_RT_SC0_BASE 0x40005a00 +#define CYDEV_ANAIF_RT_SC0_SIZE 0x0000000d +#define CYREG_SC0_SW0 0x40005a00 +#define CYREG_SC0_SW2 0x40005a02 +#define CYREG_SC0_SW3 0x40005a03 +#define CYREG_SC0_SW4 0x40005a04 +#define CYREG_SC0_SW6 0x40005a06 +#define CYREG_SC0_SW7 0x40005a07 +#define CYREG_SC0_SW8 0x40005a08 +#define CYREG_SC0_SW10 0x40005a0a +#define CYREG_SC0_CLK 0x40005a0b +#define CYREG_SC0_BST 0x40005a0c +#define CYDEV_ANAIF_RT_SC1_BASE 0x40005a10 +#define CYDEV_ANAIF_RT_SC1_SIZE 0x0000000d +#define CYREG_SC1_SW0 0x40005a10 +#define CYREG_SC1_SW2 0x40005a12 +#define CYREG_SC1_SW3 0x40005a13 +#define CYREG_SC1_SW4 0x40005a14 +#define CYREG_SC1_SW6 0x40005a16 +#define CYREG_SC1_SW7 0x40005a17 +#define CYREG_SC1_SW8 0x40005a18 +#define CYREG_SC1_SW10 0x40005a1a +#define CYREG_SC1_CLK 0x40005a1b +#define CYREG_SC1_BST 0x40005a1c +#define CYDEV_ANAIF_RT_SC2_BASE 0x40005a20 +#define CYDEV_ANAIF_RT_SC2_SIZE 0x0000000d +#define CYREG_SC2_SW0 0x40005a20 +#define CYREG_SC2_SW2 0x40005a22 +#define CYREG_SC2_SW3 0x40005a23 +#define CYREG_SC2_SW4 0x40005a24 +#define CYREG_SC2_SW6 0x40005a26 +#define CYREG_SC2_SW7 0x40005a27 +#define CYREG_SC2_SW8 0x40005a28 +#define CYREG_SC2_SW10 0x40005a2a +#define CYREG_SC2_CLK 0x40005a2b +#define CYREG_SC2_BST 0x40005a2c +#define CYDEV_ANAIF_RT_SC3_BASE 0x40005a30 +#define CYDEV_ANAIF_RT_SC3_SIZE 0x0000000d +#define CYREG_SC3_SW0 0x40005a30 +#define CYREG_SC3_SW2 0x40005a32 +#define CYREG_SC3_SW3 0x40005a33 +#define CYREG_SC3_SW4 0x40005a34 +#define CYREG_SC3_SW6 0x40005a36 +#define CYREG_SC3_SW7 0x40005a37 +#define CYREG_SC3_SW8 0x40005a38 +#define CYREG_SC3_SW10 0x40005a3a +#define CYREG_SC3_CLK 0x40005a3b +#define CYREG_SC3_BST 0x40005a3c +#define CYDEV_ANAIF_RT_DAC0_BASE 0x40005a80 +#define CYDEV_ANAIF_RT_DAC0_SIZE 0x00000008 +#define CYREG_DAC0_SW0 0x40005a80 +#define CYREG_DAC0_SW2 0x40005a82 +#define CYREG_DAC0_SW3 0x40005a83 +#define CYREG_DAC0_SW4 0x40005a84 +#define CYREG_DAC0_STROBE 0x40005a87 +#define CYDEV_ANAIF_RT_DAC1_BASE 0x40005a88 +#define CYDEV_ANAIF_RT_DAC1_SIZE 0x00000008 +#define CYREG_DAC1_SW0 0x40005a88 +#define CYREG_DAC1_SW2 0x40005a8a +#define CYREG_DAC1_SW3 0x40005a8b +#define CYREG_DAC1_SW4 0x40005a8c +#define CYREG_DAC1_STROBE 0x40005a8f +#define CYDEV_ANAIF_RT_DAC2_BASE 0x40005a90 +#define CYDEV_ANAIF_RT_DAC2_SIZE 0x00000008 +#define CYREG_DAC2_SW0 0x40005a90 +#define CYREG_DAC2_SW2 0x40005a92 +#define CYREG_DAC2_SW3 0x40005a93 +#define CYREG_DAC2_SW4 0x40005a94 +#define CYREG_DAC2_STROBE 0x40005a97 +#define CYDEV_ANAIF_RT_DAC3_BASE 0x40005a98 +#define CYDEV_ANAIF_RT_DAC3_SIZE 0x00000008 +#define CYREG_DAC3_SW0 0x40005a98 +#define CYREG_DAC3_SW2 0x40005a9a +#define CYREG_DAC3_SW3 0x40005a9b +#define CYREG_DAC3_SW4 0x40005a9c +#define CYREG_DAC3_STROBE 0x40005a9f +#define CYDEV_ANAIF_RT_CMP0_BASE 0x40005ac0 +#define CYDEV_ANAIF_RT_CMP0_SIZE 0x00000008 +#define CYREG_CMP0_SW0 0x40005ac0 +#define CYREG_CMP0_SW2 0x40005ac2 +#define CYREG_CMP0_SW3 0x40005ac3 +#define CYREG_CMP0_SW4 0x40005ac4 +#define CYREG_CMP0_SW6 0x40005ac6 +#define CYREG_CMP0_CLK 0x40005ac7 +#define CYDEV_ANAIF_RT_CMP1_BASE 0x40005ac8 +#define CYDEV_ANAIF_RT_CMP1_SIZE 0x00000008 +#define CYREG_CMP1_SW0 0x40005ac8 +#define CYREG_CMP1_SW2 0x40005aca +#define CYREG_CMP1_SW3 0x40005acb +#define CYREG_CMP1_SW4 0x40005acc +#define CYREG_CMP1_SW6 0x40005ace +#define CYREG_CMP1_CLK 0x40005acf +#define CYDEV_ANAIF_RT_CMP2_BASE 0x40005ad0 +#define CYDEV_ANAIF_RT_CMP2_SIZE 0x00000008 +#define CYREG_CMP2_SW0 0x40005ad0 +#define CYREG_CMP2_SW2 0x40005ad2 +#define CYREG_CMP2_SW3 0x40005ad3 +#define CYREG_CMP2_SW4 0x40005ad4 +#define CYREG_CMP2_SW6 0x40005ad6 +#define CYREG_CMP2_CLK 0x40005ad7 +#define CYDEV_ANAIF_RT_CMP3_BASE 0x40005ad8 +#define CYDEV_ANAIF_RT_CMP3_SIZE 0x00000008 +#define CYREG_CMP3_SW0 0x40005ad8 +#define CYREG_CMP3_SW2 0x40005ada +#define CYREG_CMP3_SW3 0x40005adb +#define CYREG_CMP3_SW4 0x40005adc +#define CYREG_CMP3_SW6 0x40005ade +#define CYREG_CMP3_CLK 0x40005adf +#define CYDEV_ANAIF_RT_DSM0_BASE 0x40005b00 +#define CYDEV_ANAIF_RT_DSM0_SIZE 0x00000008 +#define CYREG_DSM0_SW0 0x40005b00 +#define CYREG_DSM0_SW2 0x40005b02 +#define CYREG_DSM0_SW3 0x40005b03 +#define CYREG_DSM0_SW4 0x40005b04 +#define CYREG_DSM0_SW6 0x40005b06 +#define CYREG_DSM0_CLK 0x40005b07 +#define CYDEV_ANAIF_RT_SAR0_BASE 0x40005b20 +#define CYDEV_ANAIF_RT_SAR0_SIZE 0x00000008 +#define CYREG_SAR0_SW0 0x40005b20 +#define CYREG_SAR0_SW2 0x40005b22 +#define CYREG_SAR0_SW3 0x40005b23 +#define CYREG_SAR0_SW4 0x40005b24 +#define CYREG_SAR0_SW6 0x40005b26 +#define CYREG_SAR0_CLK 0x40005b27 +#define CYDEV_ANAIF_RT_SAR1_BASE 0x40005b28 +#define CYDEV_ANAIF_RT_SAR1_SIZE 0x00000008 +#define CYREG_SAR1_SW0 0x40005b28 +#define CYREG_SAR1_SW2 0x40005b2a +#define CYREG_SAR1_SW3 0x40005b2b +#define CYREG_SAR1_SW4 0x40005b2c +#define CYREG_SAR1_SW6 0x40005b2e +#define CYREG_SAR1_CLK 0x40005b2f +#define CYDEV_ANAIF_RT_OPAMP0_BASE 0x40005b40 +#define CYDEV_ANAIF_RT_OPAMP0_SIZE 0x00000002 +#define CYREG_OPAMP0_MX 0x40005b40 +#define CYREG_OPAMP0_SW 0x40005b41 +#define CYDEV_ANAIF_RT_OPAMP1_BASE 0x40005b42 +#define CYDEV_ANAIF_RT_OPAMP1_SIZE 0x00000002 +#define CYREG_OPAMP1_MX 0x40005b42 +#define CYREG_OPAMP1_SW 0x40005b43 +#define CYDEV_ANAIF_RT_OPAMP2_BASE 0x40005b44 +#define CYDEV_ANAIF_RT_OPAMP2_SIZE 0x00000002 +#define CYREG_OPAMP2_MX 0x40005b44 +#define CYREG_OPAMP2_SW 0x40005b45 +#define CYDEV_ANAIF_RT_OPAMP3_BASE 0x40005b46 +#define CYDEV_ANAIF_RT_OPAMP3_SIZE 0x00000002 +#define CYREG_OPAMP3_MX 0x40005b46 +#define CYREG_OPAMP3_SW 0x40005b47 +#define CYDEV_ANAIF_RT_LCDDAC_BASE 0x40005b50 +#define CYDEV_ANAIF_RT_LCDDAC_SIZE 0x00000005 +#define CYREG_LCDDAC_SW0 0x40005b50 +#define CYREG_LCDDAC_SW1 0x40005b51 +#define CYREG_LCDDAC_SW2 0x40005b52 +#define CYREG_LCDDAC_SW3 0x40005b53 +#define CYREG_LCDDAC_SW4 0x40005b54 +#define CYDEV_ANAIF_RT_SC_BASE 0x40005b56 +#define CYDEV_ANAIF_RT_SC_SIZE 0x00000001 +#define CYREG_SC_MISC 0x40005b56 +#define CYDEV_ANAIF_RT_BUS_BASE 0x40005b58 +#define CYDEV_ANAIF_RT_BUS_SIZE 0x00000004 +#define CYREG_BUS_SW0 0x40005b58 +#define CYREG_BUS_SW2 0x40005b5a +#define CYREG_BUS_SW3 0x40005b5b +#define CYDEV_ANAIF_RT_DFT_BASE 0x40005b5c +#define CYDEV_ANAIF_RT_DFT_SIZE 0x00000006 +#define CYREG_DFT_CR0 0x40005b5c +#define CYREG_DFT_CR1 0x40005b5d +#define CYREG_DFT_CR2 0x40005b5e +#define CYREG_DFT_CR3 0x40005b5f +#define CYREG_DFT_CR4 0x40005b60 +#define CYREG_DFT_CR5 0x40005b61 +#define CYDEV_ANAIF_WRK_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_SIZE 0x00000029 +#define CYDEV_ANAIF_WRK_DAC0_BASE 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC0_SIZE 0x00000001 +#define CYREG_DAC0_D 0x40005b80 +#define CYDEV_ANAIF_WRK_DAC1_BASE 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC1_SIZE 0x00000001 +#define CYREG_DAC1_D 0x40005b81 +#define CYDEV_ANAIF_WRK_DAC2_BASE 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC2_SIZE 0x00000001 +#define CYREG_DAC2_D 0x40005b82 +#define CYDEV_ANAIF_WRK_DAC3_BASE 0x40005b83 +#define CYDEV_ANAIF_WRK_DAC3_SIZE 0x00000001 +#define CYREG_DAC3_D 0x40005b83 +#define CYDEV_ANAIF_WRK_DSM0_BASE 0x40005b88 +#define CYDEV_ANAIF_WRK_DSM0_SIZE 0x00000002 +#define CYREG_DSM0_OUT0 0x40005b88 +#define CYREG_DSM0_OUT1 0x40005b89 +#define CYDEV_ANAIF_WRK_LUT_BASE 0x40005b90 +#define CYDEV_ANAIF_WRK_LUT_SIZE 0x00000005 +#define CYREG_LUT_SR 0x40005b90 +#define CYREG_LUT_WRK1 0x40005b91 +#define CYREG_LUT_MSK 0x40005b92 +#define CYREG_LUT_CLK 0x40005b93 +#define CYREG_LUT_CPTR 0x40005b94 +#define CYDEV_ANAIF_WRK_CMP_BASE 0x40005b96 +#define CYDEV_ANAIF_WRK_CMP_SIZE 0x00000002 +#define CYREG_CMP_WRK 0x40005b96 +#define CYREG_CMP_TST 0x40005b97 +#define CYDEV_ANAIF_WRK_SC_BASE 0x40005b98 +#define CYDEV_ANAIF_WRK_SC_SIZE 0x00000005 +#define CYREG_SC_SR 0x40005b98 +#define CYREG_SC_WRK1 0x40005b99 +#define CYREG_SC_MSK 0x40005b9a +#define CYREG_SC_CMPINV 0x40005b9b +#define CYREG_SC_CPTR 0x40005b9c +#define CYDEV_ANAIF_WRK_SAR0_BASE 0x40005ba0 +#define CYDEV_ANAIF_WRK_SAR0_SIZE 0x00000002 +#define CYREG_SAR0_WRK0 0x40005ba0 +#define CYREG_SAR0_WRK1 0x40005ba1 +#define CYDEV_ANAIF_WRK_SAR1_BASE 0x40005ba2 +#define CYDEV_ANAIF_WRK_SAR1_SIZE 0x00000002 +#define CYREG_SAR1_WRK0 0x40005ba2 +#define CYREG_SAR1_WRK1 0x40005ba3 +#define CYDEV_ANAIF_WRK_SARS_BASE 0x40005ba8 +#define CYDEV_ANAIF_WRK_SARS_SIZE 0x00000001 +#define CYREG_ANAIF_WRK_SARS_SOF 0x40005ba8 +#define CYDEV_USB_BASE 0x40006000 +#define CYDEV_USB_SIZE 0x00000300 +#define CYREG_USB_EP0_DR0 0x40006000 +#define CYREG_USB_EP0_DR1 0x40006001 +#define CYREG_USB_EP0_DR2 0x40006002 +#define CYREG_USB_EP0_DR3 0x40006003 +#define CYREG_USB_EP0_DR4 0x40006004 +#define CYREG_USB_EP0_DR5 0x40006005 +#define CYREG_USB_EP0_DR6 0x40006006 +#define CYREG_USB_EP0_DR7 0x40006007 +#define CYREG_USB_CR0 0x40006008 +#define CYREG_USB_CR1 0x40006009 +#define CYREG_USB_SIE_EP_INT_EN 0x4000600a +#define CYREG_USB_SIE_EP_INT_SR 0x4000600b +#define CYDEV_USB_SIE_EP1_BASE 0x4000600c +#define CYDEV_USB_SIE_EP1_SIZE 0x00000003 +#define CYREG_USB_SIE_EP1_CNT0 0x4000600c +#define CYREG_USB_SIE_EP1_CNT1 0x4000600d +#define CYREG_USB_SIE_EP1_CR0 0x4000600e +#define CYREG_USB_USBIO_CR0 0x40006010 +#define CYREG_USB_USBIO_CR1 0x40006012 +#define CYREG_USB_DYN_RECONFIG 0x40006014 +#define CYREG_USB_SOF0 0x40006018 +#define CYREG_USB_SOF1 0x40006019 +#define CYDEV_USB_SIE_EP2_BASE 0x4000601c +#define CYDEV_USB_SIE_EP2_SIZE 0x00000003 +#define CYREG_USB_SIE_EP2_CNT0 0x4000601c +#define CYREG_USB_SIE_EP2_CNT1 0x4000601d +#define CYREG_USB_SIE_EP2_CR0 0x4000601e +#define CYREG_USB_EP0_CR 0x40006028 +#define CYREG_USB_EP0_CNT 0x40006029 +#define CYDEV_USB_SIE_EP3_BASE 0x4000602c +#define CYDEV_USB_SIE_EP3_SIZE 0x00000003 +#define CYREG_USB_SIE_EP3_CNT0 0x4000602c +#define CYREG_USB_SIE_EP3_CNT1 0x4000602d +#define CYREG_USB_SIE_EP3_CR0 0x4000602e +#define CYDEV_USB_SIE_EP4_BASE 0x4000603c +#define CYDEV_USB_SIE_EP4_SIZE 0x00000003 +#define CYREG_USB_SIE_EP4_CNT0 0x4000603c +#define CYREG_USB_SIE_EP4_CNT1 0x4000603d +#define CYREG_USB_SIE_EP4_CR0 0x4000603e +#define CYDEV_USB_SIE_EP5_BASE 0x4000604c +#define CYDEV_USB_SIE_EP5_SIZE 0x00000003 +#define CYREG_USB_SIE_EP5_CNT0 0x4000604c +#define CYREG_USB_SIE_EP5_CNT1 0x4000604d +#define CYREG_USB_SIE_EP5_CR0 0x4000604e +#define CYDEV_USB_SIE_EP6_BASE 0x4000605c +#define CYDEV_USB_SIE_EP6_SIZE 0x00000003 +#define CYREG_USB_SIE_EP6_CNT0 0x4000605c +#define CYREG_USB_SIE_EP6_CNT1 0x4000605d +#define CYREG_USB_SIE_EP6_CR0 0x4000605e +#define CYDEV_USB_SIE_EP7_BASE 0x4000606c +#define CYDEV_USB_SIE_EP7_SIZE 0x00000003 +#define CYREG_USB_SIE_EP7_CNT0 0x4000606c +#define CYREG_USB_SIE_EP7_CNT1 0x4000606d +#define CYREG_USB_SIE_EP7_CR0 0x4000606e +#define CYDEV_USB_SIE_EP8_BASE 0x4000607c +#define CYDEV_USB_SIE_EP8_SIZE 0x00000003 +#define CYREG_USB_SIE_EP8_CNT0 0x4000607c +#define CYREG_USB_SIE_EP8_CNT1 0x4000607d +#define CYREG_USB_SIE_EP8_CR0 0x4000607e +#define CYDEV_USB_ARB_EP1_BASE 0x40006080 +#define CYDEV_USB_ARB_EP1_SIZE 0x00000003 +#define CYREG_USB_ARB_EP1_CFG 0x40006080 +#define CYREG_USB_ARB_EP1_INT_EN 0x40006081 +#define CYREG_USB_ARB_EP1_SR 0x40006082 +#define CYDEV_USB_ARB_RW1_BASE 0x40006084 +#define CYDEV_USB_ARB_RW1_SIZE 0x00000005 +#define CYREG_USB_ARB_RW1_WA 0x40006084 +#define CYREG_USB_ARB_RW1_WA_MSB 0x40006085 +#define CYREG_USB_ARB_RW1_RA 0x40006086 +#define CYREG_USB_ARB_RW1_RA_MSB 0x40006087 +#define CYREG_USB_ARB_RW1_DR 0x40006088 +#define CYREG_USB_BUF_SIZE 0x4000608c +#define CYREG_USB_EP_ACTIVE 0x4000608e +#define CYREG_USB_EP_TYPE 0x4000608f +#define CYDEV_USB_ARB_EP2_BASE 0x40006090 +#define CYDEV_USB_ARB_EP2_SIZE 0x00000003 +#define CYREG_USB_ARB_EP2_CFG 0x40006090 +#define CYREG_USB_ARB_EP2_INT_EN 0x40006091 +#define CYREG_USB_ARB_EP2_SR 0x40006092 +#define CYDEV_USB_ARB_RW2_BASE 0x40006094 +#define CYDEV_USB_ARB_RW2_SIZE 0x00000005 +#define CYREG_USB_ARB_RW2_WA 0x40006094 +#define CYREG_USB_ARB_RW2_WA_MSB 0x40006095 +#define CYREG_USB_ARB_RW2_RA 0x40006096 +#define CYREG_USB_ARB_RW2_RA_MSB 0x40006097 +#define CYREG_USB_ARB_RW2_DR 0x40006098 +#define CYREG_USB_ARB_CFG 0x4000609c +#define CYREG_USB_USB_CLK_EN 0x4000609d +#define CYREG_USB_ARB_INT_EN 0x4000609e +#define CYREG_USB_ARB_INT_SR 0x4000609f +#define CYDEV_USB_ARB_EP3_BASE 0x400060a0 +#define CYDEV_USB_ARB_EP3_SIZE 0x00000003 +#define CYREG_USB_ARB_EP3_CFG 0x400060a0 +#define CYREG_USB_ARB_EP3_INT_EN 0x400060a1 +#define CYREG_USB_ARB_EP3_SR 0x400060a2 +#define CYDEV_USB_ARB_RW3_BASE 0x400060a4 +#define CYDEV_USB_ARB_RW3_SIZE 0x00000005 +#define CYREG_USB_ARB_RW3_WA 0x400060a4 +#define CYREG_USB_ARB_RW3_WA_MSB 0x400060a5 +#define CYREG_USB_ARB_RW3_RA 0x400060a6 +#define CYREG_USB_ARB_RW3_RA_MSB 0x400060a7 +#define CYREG_USB_ARB_RW3_DR 0x400060a8 +#define CYREG_USB_CWA 0x400060ac +#define CYREG_USB_CWA_MSB 0x400060ad +#define CYDEV_USB_ARB_EP4_BASE 0x400060b0 +#define CYDEV_USB_ARB_EP4_SIZE 0x00000003 +#define CYREG_USB_ARB_EP4_CFG 0x400060b0 +#define CYREG_USB_ARB_EP4_INT_EN 0x400060b1 +#define CYREG_USB_ARB_EP4_SR 0x400060b2 +#define CYDEV_USB_ARB_RW4_BASE 0x400060b4 +#define CYDEV_USB_ARB_RW4_SIZE 0x00000005 +#define CYREG_USB_ARB_RW4_WA 0x400060b4 +#define CYREG_USB_ARB_RW4_WA_MSB 0x400060b5 +#define CYREG_USB_ARB_RW4_RA 0x400060b6 +#define CYREG_USB_ARB_RW4_RA_MSB 0x400060b7 +#define CYREG_USB_ARB_RW4_DR 0x400060b8 +#define CYREG_USB_DMA_THRES 0x400060bc +#define CYREG_USB_DMA_THRES_MSB 0x400060bd +#define CYDEV_USB_ARB_EP5_BASE 0x400060c0 +#define CYDEV_USB_ARB_EP5_SIZE 0x00000003 +#define CYREG_USB_ARB_EP5_CFG 0x400060c0 +#define CYREG_USB_ARB_EP5_INT_EN 0x400060c1 +#define CYREG_USB_ARB_EP5_SR 0x400060c2 +#define CYDEV_USB_ARB_RW5_BASE 0x400060c4 +#define CYDEV_USB_ARB_RW5_SIZE 0x00000005 +#define CYREG_USB_ARB_RW5_WA 0x400060c4 +#define CYREG_USB_ARB_RW5_WA_MSB 0x400060c5 +#define CYREG_USB_ARB_RW5_RA 0x400060c6 +#define CYREG_USB_ARB_RW5_RA_MSB 0x400060c7 +#define CYREG_USB_ARB_RW5_DR 0x400060c8 +#define CYREG_USB_BUS_RST_CNT 0x400060cc +#define CYDEV_USB_ARB_EP6_BASE 0x400060d0 +#define CYDEV_USB_ARB_EP6_SIZE 0x00000003 +#define CYREG_USB_ARB_EP6_CFG 0x400060d0 +#define CYREG_USB_ARB_EP6_INT_EN 0x400060d1 +#define CYREG_USB_ARB_EP6_SR 0x400060d2 +#define CYDEV_USB_ARB_RW6_BASE 0x400060d4 +#define CYDEV_USB_ARB_RW6_SIZE 0x00000005 +#define CYREG_USB_ARB_RW6_WA 0x400060d4 +#define CYREG_USB_ARB_RW6_WA_MSB 0x400060d5 +#define CYREG_USB_ARB_RW6_RA 0x400060d6 +#define CYREG_USB_ARB_RW6_RA_MSB 0x400060d7 +#define CYREG_USB_ARB_RW6_DR 0x400060d8 +#define CYDEV_USB_ARB_EP7_BASE 0x400060e0 +#define CYDEV_USB_ARB_EP7_SIZE 0x00000003 +#define CYREG_USB_ARB_EP7_CFG 0x400060e0 +#define CYREG_USB_ARB_EP7_INT_EN 0x400060e1 +#define CYREG_USB_ARB_EP7_SR 0x400060e2 +#define CYDEV_USB_ARB_RW7_BASE 0x400060e4 +#define CYDEV_USB_ARB_RW7_SIZE 0x00000005 +#define CYREG_USB_ARB_RW7_WA 0x400060e4 +#define CYREG_USB_ARB_RW7_WA_MSB 0x400060e5 +#define CYREG_USB_ARB_RW7_RA 0x400060e6 +#define CYREG_USB_ARB_RW7_RA_MSB 0x400060e7 +#define CYREG_USB_ARB_RW7_DR 0x400060e8 +#define CYDEV_USB_ARB_EP8_BASE 0x400060f0 +#define CYDEV_USB_ARB_EP8_SIZE 0x00000003 +#define CYREG_USB_ARB_EP8_CFG 0x400060f0 +#define CYREG_USB_ARB_EP8_INT_EN 0x400060f1 +#define CYREG_USB_ARB_EP8_SR 0x400060f2 +#define CYDEV_USB_ARB_RW8_BASE 0x400060f4 +#define CYDEV_USB_ARB_RW8_SIZE 0x00000005 +#define CYREG_USB_ARB_RW8_WA 0x400060f4 +#define CYREG_USB_ARB_RW8_WA_MSB 0x400060f5 +#define CYREG_USB_ARB_RW8_RA 0x400060f6 +#define CYREG_USB_ARB_RW8_RA_MSB 0x400060f7 +#define CYREG_USB_ARB_RW8_DR 0x400060f8 +#define CYDEV_USB_MEM_BASE 0x40006100 +#define CYDEV_USB_MEM_SIZE 0x00000200 +#define CYREG_USB_MEM_DATA_MBASE 0x40006100 +#define CYREG_USB_MEM_DATA_MSIZE 0x00000200 +#define CYDEV_UWRK_BASE 0x40006400 +#define CYDEV_UWRK_SIZE 0x00000b60 +#define CYDEV_UWRK_UWRK8_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_SIZE 0x000003b0 +#define CYDEV_UWRK_UWRK8_B0_BASE 0x40006400 +#define CYDEV_UWRK_UWRK8_B0_SIZE 0x000000b0 +#define CYREG_B0_UDB00_A0 0x40006400 +#define CYREG_B0_UDB01_A0 0x40006401 +#define CYREG_B0_UDB02_A0 0x40006402 +#define CYREG_B0_UDB03_A0 0x40006403 +#define CYREG_B0_UDB04_A0 0x40006404 +#define CYREG_B0_UDB05_A0 0x40006405 +#define CYREG_B0_UDB06_A0 0x40006406 +#define CYREG_B0_UDB07_A0 0x40006407 +#define CYREG_B0_UDB08_A0 0x40006408 +#define CYREG_B0_UDB09_A0 0x40006409 +#define CYREG_B0_UDB10_A0 0x4000640a +#define CYREG_B0_UDB11_A0 0x4000640b +#define CYREG_B0_UDB12_A0 0x4000640c +#define CYREG_B0_UDB13_A0 0x4000640d +#define CYREG_B0_UDB14_A0 0x4000640e +#define CYREG_B0_UDB15_A0 0x4000640f +#define CYREG_B0_UDB00_A1 0x40006410 +#define CYREG_B0_UDB01_A1 0x40006411 +#define CYREG_B0_UDB02_A1 0x40006412 +#define CYREG_B0_UDB03_A1 0x40006413 +#define CYREG_B0_UDB04_A1 0x40006414 +#define CYREG_B0_UDB05_A1 0x40006415 +#define CYREG_B0_UDB06_A1 0x40006416 +#define CYREG_B0_UDB07_A1 0x40006417 +#define CYREG_B0_UDB08_A1 0x40006418 +#define CYREG_B0_UDB09_A1 0x40006419 +#define CYREG_B0_UDB10_A1 0x4000641a +#define CYREG_B0_UDB11_A1 0x4000641b +#define CYREG_B0_UDB12_A1 0x4000641c +#define CYREG_B0_UDB13_A1 0x4000641d +#define CYREG_B0_UDB14_A1 0x4000641e +#define CYREG_B0_UDB15_A1 0x4000641f +#define CYREG_B0_UDB00_D0 0x40006420 +#define CYREG_B0_UDB01_D0 0x40006421 +#define CYREG_B0_UDB02_D0 0x40006422 +#define CYREG_B0_UDB03_D0 0x40006423 +#define CYREG_B0_UDB04_D0 0x40006424 +#define CYREG_B0_UDB05_D0 0x40006425 +#define CYREG_B0_UDB06_D0 0x40006426 +#define CYREG_B0_UDB07_D0 0x40006427 +#define CYREG_B0_UDB08_D0 0x40006428 +#define CYREG_B0_UDB09_D0 0x40006429 +#define CYREG_B0_UDB10_D0 0x4000642a +#define CYREG_B0_UDB11_D0 0x4000642b +#define CYREG_B0_UDB12_D0 0x4000642c +#define CYREG_B0_UDB13_D0 0x4000642d +#define CYREG_B0_UDB14_D0 0x4000642e +#define CYREG_B0_UDB15_D0 0x4000642f +#define CYREG_B0_UDB00_D1 0x40006430 +#define CYREG_B0_UDB01_D1 0x40006431 +#define CYREG_B0_UDB02_D1 0x40006432 +#define CYREG_B0_UDB03_D1 0x40006433 +#define CYREG_B0_UDB04_D1 0x40006434 +#define CYREG_B0_UDB05_D1 0x40006435 +#define CYREG_B0_UDB06_D1 0x40006436 +#define CYREG_B0_UDB07_D1 0x40006437 +#define CYREG_B0_UDB08_D1 0x40006438 +#define CYREG_B0_UDB09_D1 0x40006439 +#define CYREG_B0_UDB10_D1 0x4000643a +#define CYREG_B0_UDB11_D1 0x4000643b +#define CYREG_B0_UDB12_D1 0x4000643c +#define CYREG_B0_UDB13_D1 0x4000643d +#define CYREG_B0_UDB14_D1 0x4000643e +#define CYREG_B0_UDB15_D1 0x4000643f +#define CYREG_B0_UDB00_F0 0x40006440 +#define CYREG_B0_UDB01_F0 0x40006441 +#define CYREG_B0_UDB02_F0 0x40006442 +#define CYREG_B0_UDB03_F0 0x40006443 +#define CYREG_B0_UDB04_F0 0x40006444 +#define CYREG_B0_UDB05_F0 0x40006445 +#define CYREG_B0_UDB06_F0 0x40006446 +#define CYREG_B0_UDB07_F0 0x40006447 +#define CYREG_B0_UDB08_F0 0x40006448 +#define CYREG_B0_UDB09_F0 0x40006449 +#define CYREG_B0_UDB10_F0 0x4000644a +#define CYREG_B0_UDB11_F0 0x4000644b +#define CYREG_B0_UDB12_F0 0x4000644c +#define CYREG_B0_UDB13_F0 0x4000644d +#define CYREG_B0_UDB14_F0 0x4000644e +#define CYREG_B0_UDB15_F0 0x4000644f +#define CYREG_B0_UDB00_F1 0x40006450 +#define CYREG_B0_UDB01_F1 0x40006451 +#define CYREG_B0_UDB02_F1 0x40006452 +#define CYREG_B0_UDB03_F1 0x40006453 +#define CYREG_B0_UDB04_F1 0x40006454 +#define CYREG_B0_UDB05_F1 0x40006455 +#define CYREG_B0_UDB06_F1 0x40006456 +#define CYREG_B0_UDB07_F1 0x40006457 +#define CYREG_B0_UDB08_F1 0x40006458 +#define CYREG_B0_UDB09_F1 0x40006459 +#define CYREG_B0_UDB10_F1 0x4000645a +#define CYREG_B0_UDB11_F1 0x4000645b +#define CYREG_B0_UDB12_F1 0x4000645c +#define CYREG_B0_UDB13_F1 0x4000645d +#define CYREG_B0_UDB14_F1 0x4000645e +#define CYREG_B0_UDB15_F1 0x4000645f +#define CYREG_B0_UDB00_ST 0x40006460 +#define CYREG_B0_UDB01_ST 0x40006461 +#define CYREG_B0_UDB02_ST 0x40006462 +#define CYREG_B0_UDB03_ST 0x40006463 +#define CYREG_B0_UDB04_ST 0x40006464 +#define CYREG_B0_UDB05_ST 0x40006465 +#define CYREG_B0_UDB06_ST 0x40006466 +#define CYREG_B0_UDB07_ST 0x40006467 +#define CYREG_B0_UDB08_ST 0x40006468 +#define CYREG_B0_UDB09_ST 0x40006469 +#define CYREG_B0_UDB10_ST 0x4000646a +#define CYREG_B0_UDB11_ST 0x4000646b +#define CYREG_B0_UDB12_ST 0x4000646c +#define CYREG_B0_UDB13_ST 0x4000646d +#define CYREG_B0_UDB14_ST 0x4000646e +#define CYREG_B0_UDB15_ST 0x4000646f +#define CYREG_B0_UDB00_CTL 0x40006470 +#define CYREG_B0_UDB01_CTL 0x40006471 +#define CYREG_B0_UDB02_CTL 0x40006472 +#define CYREG_B0_UDB03_CTL 0x40006473 +#define CYREG_B0_UDB04_CTL 0x40006474 +#define CYREG_B0_UDB05_CTL 0x40006475 +#define CYREG_B0_UDB06_CTL 0x40006476 +#define CYREG_B0_UDB07_CTL 0x40006477 +#define CYREG_B0_UDB08_CTL 0x40006478 +#define CYREG_B0_UDB09_CTL 0x40006479 +#define CYREG_B0_UDB10_CTL 0x4000647a +#define CYREG_B0_UDB11_CTL 0x4000647b +#define CYREG_B0_UDB12_CTL 0x4000647c +#define CYREG_B0_UDB13_CTL 0x4000647d +#define CYREG_B0_UDB14_CTL 0x4000647e +#define CYREG_B0_UDB15_CTL 0x4000647f +#define CYREG_B0_UDB00_MSK 0x40006480 +#define CYREG_B0_UDB01_MSK 0x40006481 +#define CYREG_B0_UDB02_MSK 0x40006482 +#define CYREG_B0_UDB03_MSK 0x40006483 +#define CYREG_B0_UDB04_MSK 0x40006484 +#define CYREG_B0_UDB05_MSK 0x40006485 +#define CYREG_B0_UDB06_MSK 0x40006486 +#define CYREG_B0_UDB07_MSK 0x40006487 +#define CYREG_B0_UDB08_MSK 0x40006488 +#define CYREG_B0_UDB09_MSK 0x40006489 +#define CYREG_B0_UDB10_MSK 0x4000648a +#define CYREG_B0_UDB11_MSK 0x4000648b +#define CYREG_B0_UDB12_MSK 0x4000648c +#define CYREG_B0_UDB13_MSK 0x4000648d +#define CYREG_B0_UDB14_MSK 0x4000648e +#define CYREG_B0_UDB15_MSK 0x4000648f +#define CYREG_B0_UDB00_ACTL 0x40006490 +#define CYREG_B0_UDB01_ACTL 0x40006491 +#define CYREG_B0_UDB02_ACTL 0x40006492 +#define CYREG_B0_UDB03_ACTL 0x40006493 +#define CYREG_B0_UDB04_ACTL 0x40006494 +#define CYREG_B0_UDB05_ACTL 0x40006495 +#define CYREG_B0_UDB06_ACTL 0x40006496 +#define CYREG_B0_UDB07_ACTL 0x40006497 +#define CYREG_B0_UDB08_ACTL 0x40006498 +#define CYREG_B0_UDB09_ACTL 0x40006499 +#define CYREG_B0_UDB10_ACTL 0x4000649a +#define CYREG_B0_UDB11_ACTL 0x4000649b +#define CYREG_B0_UDB12_ACTL 0x4000649c +#define CYREG_B0_UDB13_ACTL 0x4000649d +#define CYREG_B0_UDB14_ACTL 0x4000649e +#define CYREG_B0_UDB15_ACTL 0x4000649f +#define CYREG_B0_UDB00_MC 0x400064a0 +#define CYREG_B0_UDB01_MC 0x400064a1 +#define CYREG_B0_UDB02_MC 0x400064a2 +#define CYREG_B0_UDB03_MC 0x400064a3 +#define CYREG_B0_UDB04_MC 0x400064a4 +#define CYREG_B0_UDB05_MC 0x400064a5 +#define CYREG_B0_UDB06_MC 0x400064a6 +#define CYREG_B0_UDB07_MC 0x400064a7 +#define CYREG_B0_UDB08_MC 0x400064a8 +#define CYREG_B0_UDB09_MC 0x400064a9 +#define CYREG_B0_UDB10_MC 0x400064aa +#define CYREG_B0_UDB11_MC 0x400064ab +#define CYREG_B0_UDB12_MC 0x400064ac +#define CYREG_B0_UDB13_MC 0x400064ad +#define CYREG_B0_UDB14_MC 0x400064ae +#define CYREG_B0_UDB15_MC 0x400064af +#define CYDEV_UWRK_UWRK8_B1_BASE 0x40006500 +#define CYDEV_UWRK_UWRK8_B1_SIZE 0x000000b0 +#define CYREG_B1_UDB04_A0 0x40006504 +#define CYREG_B1_UDB05_A0 0x40006505 +#define CYREG_B1_UDB06_A0 0x40006506 +#define CYREG_B1_UDB07_A0 0x40006507 +#define CYREG_B1_UDB08_A0 0x40006508 +#define CYREG_B1_UDB09_A0 0x40006509 +#define CYREG_B1_UDB10_A0 0x4000650a +#define CYREG_B1_UDB11_A0 0x4000650b +#define CYREG_B1_UDB04_A1 0x40006514 +#define CYREG_B1_UDB05_A1 0x40006515 +#define CYREG_B1_UDB06_A1 0x40006516 +#define CYREG_B1_UDB07_A1 0x40006517 +#define CYREG_B1_UDB08_A1 0x40006518 +#define CYREG_B1_UDB09_A1 0x40006519 +#define CYREG_B1_UDB10_A1 0x4000651a +#define CYREG_B1_UDB11_A1 0x4000651b +#define CYREG_B1_UDB04_D0 0x40006524 +#define CYREG_B1_UDB05_D0 0x40006525 +#define CYREG_B1_UDB06_D0 0x40006526 +#define CYREG_B1_UDB07_D0 0x40006527 +#define CYREG_B1_UDB08_D0 0x40006528 +#define CYREG_B1_UDB09_D0 0x40006529 +#define CYREG_B1_UDB10_D0 0x4000652a +#define CYREG_B1_UDB11_D0 0x4000652b +#define CYREG_B1_UDB04_D1 0x40006534 +#define CYREG_B1_UDB05_D1 0x40006535 +#define CYREG_B1_UDB06_D1 0x40006536 +#define CYREG_B1_UDB07_D1 0x40006537 +#define CYREG_B1_UDB08_D1 0x40006538 +#define CYREG_B1_UDB09_D1 0x40006539 +#define CYREG_B1_UDB10_D1 0x4000653a +#define CYREG_B1_UDB11_D1 0x4000653b +#define CYREG_B1_UDB04_F0 0x40006544 +#define CYREG_B1_UDB05_F0 0x40006545 +#define CYREG_B1_UDB06_F0 0x40006546 +#define CYREG_B1_UDB07_F0 0x40006547 +#define CYREG_B1_UDB08_F0 0x40006548 +#define CYREG_B1_UDB09_F0 0x40006549 +#define CYREG_B1_UDB10_F0 0x4000654a +#define CYREG_B1_UDB11_F0 0x4000654b +#define CYREG_B1_UDB04_F1 0x40006554 +#define CYREG_B1_UDB05_F1 0x40006555 +#define CYREG_B1_UDB06_F1 0x40006556 +#define CYREG_B1_UDB07_F1 0x40006557 +#define CYREG_B1_UDB08_F1 0x40006558 +#define CYREG_B1_UDB09_F1 0x40006559 +#define CYREG_B1_UDB10_F1 0x4000655a +#define CYREG_B1_UDB11_F1 0x4000655b +#define CYREG_B1_UDB04_ST 0x40006564 +#define CYREG_B1_UDB05_ST 0x40006565 +#define CYREG_B1_UDB06_ST 0x40006566 +#define CYREG_B1_UDB07_ST 0x40006567 +#define CYREG_B1_UDB08_ST 0x40006568 +#define CYREG_B1_UDB09_ST 0x40006569 +#define CYREG_B1_UDB10_ST 0x4000656a +#define CYREG_B1_UDB11_ST 0x4000656b +#define CYREG_B1_UDB04_CTL 0x40006574 +#define CYREG_B1_UDB05_CTL 0x40006575 +#define CYREG_B1_UDB06_CTL 0x40006576 +#define CYREG_B1_UDB07_CTL 0x40006577 +#define CYREG_B1_UDB08_CTL 0x40006578 +#define CYREG_B1_UDB09_CTL 0x40006579 +#define CYREG_B1_UDB10_CTL 0x4000657a +#define CYREG_B1_UDB11_CTL 0x4000657b +#define CYREG_B1_UDB04_MSK 0x40006584 +#define CYREG_B1_UDB05_MSK 0x40006585 +#define CYREG_B1_UDB06_MSK 0x40006586 +#define CYREG_B1_UDB07_MSK 0x40006587 +#define CYREG_B1_UDB08_MSK 0x40006588 +#define CYREG_B1_UDB09_MSK 0x40006589 +#define CYREG_B1_UDB10_MSK 0x4000658a +#define CYREG_B1_UDB11_MSK 0x4000658b +#define CYREG_B1_UDB04_ACTL 0x40006594 +#define CYREG_B1_UDB05_ACTL 0x40006595 +#define CYREG_B1_UDB06_ACTL 0x40006596 +#define CYREG_B1_UDB07_ACTL 0x40006597 +#define CYREG_B1_UDB08_ACTL 0x40006598 +#define CYREG_B1_UDB09_ACTL 0x40006599 +#define CYREG_B1_UDB10_ACTL 0x4000659a +#define CYREG_B1_UDB11_ACTL 0x4000659b +#define CYREG_B1_UDB04_MC 0x400065a4 +#define CYREG_B1_UDB05_MC 0x400065a5 +#define CYREG_B1_UDB06_MC 0x400065a6 +#define CYREG_B1_UDB07_MC 0x400065a7 +#define CYREG_B1_UDB08_MC 0x400065a8 +#define CYREG_B1_UDB09_MC 0x400065a9 +#define CYREG_B1_UDB10_MC 0x400065aa +#define CYREG_B1_UDB11_MC 0x400065ab +#define CYDEV_UWRK_UWRK16_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_SIZE 0x00000760 +#define CYDEV_UWRK_UWRK16_CAT_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_CAT_B0_SIZE 0x00000160 +#define CYREG_B0_UDB00_A0_A1 0x40006800 +#define CYREG_B0_UDB01_A0_A1 0x40006802 +#define CYREG_B0_UDB02_A0_A1 0x40006804 +#define CYREG_B0_UDB03_A0_A1 0x40006806 +#define CYREG_B0_UDB04_A0_A1 0x40006808 +#define CYREG_B0_UDB05_A0_A1 0x4000680a +#define CYREG_B0_UDB06_A0_A1 0x4000680c +#define CYREG_B0_UDB07_A0_A1 0x4000680e +#define CYREG_B0_UDB08_A0_A1 0x40006810 +#define CYREG_B0_UDB09_A0_A1 0x40006812 +#define CYREG_B0_UDB10_A0_A1 0x40006814 +#define CYREG_B0_UDB11_A0_A1 0x40006816 +#define CYREG_B0_UDB12_A0_A1 0x40006818 +#define CYREG_B0_UDB13_A0_A1 0x4000681a +#define CYREG_B0_UDB14_A0_A1 0x4000681c +#define CYREG_B0_UDB15_A0_A1 0x4000681e +#define CYREG_B0_UDB00_D0_D1 0x40006840 +#define CYREG_B0_UDB01_D0_D1 0x40006842 +#define CYREG_B0_UDB02_D0_D1 0x40006844 +#define CYREG_B0_UDB03_D0_D1 0x40006846 +#define CYREG_B0_UDB04_D0_D1 0x40006848 +#define CYREG_B0_UDB05_D0_D1 0x4000684a +#define CYREG_B0_UDB06_D0_D1 0x4000684c +#define CYREG_B0_UDB07_D0_D1 0x4000684e +#define CYREG_B0_UDB08_D0_D1 0x40006850 +#define CYREG_B0_UDB09_D0_D1 0x40006852 +#define CYREG_B0_UDB10_D0_D1 0x40006854 +#define CYREG_B0_UDB11_D0_D1 0x40006856 +#define CYREG_B0_UDB12_D0_D1 0x40006858 +#define CYREG_B0_UDB13_D0_D1 0x4000685a +#define CYREG_B0_UDB14_D0_D1 0x4000685c +#define CYREG_B0_UDB15_D0_D1 0x4000685e +#define CYREG_B0_UDB00_F0_F1 0x40006880 +#define CYREG_B0_UDB01_F0_F1 0x40006882 +#define CYREG_B0_UDB02_F0_F1 0x40006884 +#define CYREG_B0_UDB03_F0_F1 0x40006886 +#define CYREG_B0_UDB04_F0_F1 0x40006888 +#define CYREG_B0_UDB05_F0_F1 0x4000688a +#define CYREG_B0_UDB06_F0_F1 0x4000688c +#define CYREG_B0_UDB07_F0_F1 0x4000688e +#define CYREG_B0_UDB08_F0_F1 0x40006890 +#define CYREG_B0_UDB09_F0_F1 0x40006892 +#define CYREG_B0_UDB10_F0_F1 0x40006894 +#define CYREG_B0_UDB11_F0_F1 0x40006896 +#define CYREG_B0_UDB12_F0_F1 0x40006898 +#define CYREG_B0_UDB13_F0_F1 0x4000689a +#define CYREG_B0_UDB14_F0_F1 0x4000689c +#define CYREG_B0_UDB15_F0_F1 0x4000689e +#define CYREG_B0_UDB00_ST_CTL 0x400068c0 +#define CYREG_B0_UDB01_ST_CTL 0x400068c2 +#define CYREG_B0_UDB02_ST_CTL 0x400068c4 +#define CYREG_B0_UDB03_ST_CTL 0x400068c6 +#define CYREG_B0_UDB04_ST_CTL 0x400068c8 +#define CYREG_B0_UDB05_ST_CTL 0x400068ca +#define CYREG_B0_UDB06_ST_CTL 0x400068cc +#define CYREG_B0_UDB07_ST_CTL 0x400068ce +#define CYREG_B0_UDB08_ST_CTL 0x400068d0 +#define CYREG_B0_UDB09_ST_CTL 0x400068d2 +#define CYREG_B0_UDB10_ST_CTL 0x400068d4 +#define CYREG_B0_UDB11_ST_CTL 0x400068d6 +#define CYREG_B0_UDB12_ST_CTL 0x400068d8 +#define CYREG_B0_UDB13_ST_CTL 0x400068da +#define CYREG_B0_UDB14_ST_CTL 0x400068dc +#define CYREG_B0_UDB15_ST_CTL 0x400068de +#define CYREG_B0_UDB00_MSK_ACTL 0x40006900 +#define CYREG_B0_UDB01_MSK_ACTL 0x40006902 +#define CYREG_B0_UDB02_MSK_ACTL 0x40006904 +#define CYREG_B0_UDB03_MSK_ACTL 0x40006906 +#define CYREG_B0_UDB04_MSK_ACTL 0x40006908 +#define CYREG_B0_UDB05_MSK_ACTL 0x4000690a +#define CYREG_B0_UDB06_MSK_ACTL 0x4000690c +#define CYREG_B0_UDB07_MSK_ACTL 0x4000690e +#define CYREG_B0_UDB08_MSK_ACTL 0x40006910 +#define CYREG_B0_UDB09_MSK_ACTL 0x40006912 +#define CYREG_B0_UDB10_MSK_ACTL 0x40006914 +#define CYREG_B0_UDB11_MSK_ACTL 0x40006916 +#define CYREG_B0_UDB12_MSK_ACTL 0x40006918 +#define CYREG_B0_UDB13_MSK_ACTL 0x4000691a +#define CYREG_B0_UDB14_MSK_ACTL 0x4000691c +#define CYREG_B0_UDB15_MSK_ACTL 0x4000691e +#define CYREG_B0_UDB00_MC_00 0x40006940 +#define CYREG_B0_UDB01_MC_00 0x40006942 +#define CYREG_B0_UDB02_MC_00 0x40006944 +#define CYREG_B0_UDB03_MC_00 0x40006946 +#define CYREG_B0_UDB04_MC_00 0x40006948 +#define CYREG_B0_UDB05_MC_00 0x4000694a +#define CYREG_B0_UDB06_MC_00 0x4000694c +#define CYREG_B0_UDB07_MC_00 0x4000694e +#define CYREG_B0_UDB08_MC_00 0x40006950 +#define CYREG_B0_UDB09_MC_00 0x40006952 +#define CYREG_B0_UDB10_MC_00 0x40006954 +#define CYREG_B0_UDB11_MC_00 0x40006956 +#define CYREG_B0_UDB12_MC_00 0x40006958 +#define CYREG_B0_UDB13_MC_00 0x4000695a +#define CYREG_B0_UDB14_MC_00 0x4000695c +#define CYREG_B0_UDB15_MC_00 0x4000695e +#define CYDEV_UWRK_UWRK16_CAT_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_CAT_B1_SIZE 0x00000160 +#define CYREG_B1_UDB04_A0_A1 0x40006a08 +#define CYREG_B1_UDB05_A0_A1 0x40006a0a +#define CYREG_B1_UDB06_A0_A1 0x40006a0c +#define CYREG_B1_UDB07_A0_A1 0x40006a0e +#define CYREG_B1_UDB08_A0_A1 0x40006a10 +#define CYREG_B1_UDB09_A0_A1 0x40006a12 +#define CYREG_B1_UDB10_A0_A1 0x40006a14 +#define CYREG_B1_UDB11_A0_A1 0x40006a16 +#define CYREG_B1_UDB04_D0_D1 0x40006a48 +#define CYREG_B1_UDB05_D0_D1 0x40006a4a +#define CYREG_B1_UDB06_D0_D1 0x40006a4c +#define CYREG_B1_UDB07_D0_D1 0x40006a4e +#define CYREG_B1_UDB08_D0_D1 0x40006a50 +#define CYREG_B1_UDB09_D0_D1 0x40006a52 +#define CYREG_B1_UDB10_D0_D1 0x40006a54 +#define CYREG_B1_UDB11_D0_D1 0x40006a56 +#define CYREG_B1_UDB04_F0_F1 0x40006a88 +#define CYREG_B1_UDB05_F0_F1 0x40006a8a +#define CYREG_B1_UDB06_F0_F1 0x40006a8c +#define CYREG_B1_UDB07_F0_F1 0x40006a8e +#define CYREG_B1_UDB08_F0_F1 0x40006a90 +#define CYREG_B1_UDB09_F0_F1 0x40006a92 +#define CYREG_B1_UDB10_F0_F1 0x40006a94 +#define CYREG_B1_UDB11_F0_F1 0x40006a96 +#define CYREG_B1_UDB04_ST_CTL 0x40006ac8 +#define CYREG_B1_UDB05_ST_CTL 0x40006aca +#define CYREG_B1_UDB06_ST_CTL 0x40006acc +#define CYREG_B1_UDB07_ST_CTL 0x40006ace +#define CYREG_B1_UDB08_ST_CTL 0x40006ad0 +#define CYREG_B1_UDB09_ST_CTL 0x40006ad2 +#define CYREG_B1_UDB10_ST_CTL 0x40006ad4 +#define CYREG_B1_UDB11_ST_CTL 0x40006ad6 +#define CYREG_B1_UDB04_MSK_ACTL 0x40006b08 +#define CYREG_B1_UDB05_MSK_ACTL 0x40006b0a +#define CYREG_B1_UDB06_MSK_ACTL 0x40006b0c +#define CYREG_B1_UDB07_MSK_ACTL 0x40006b0e +#define CYREG_B1_UDB08_MSK_ACTL 0x40006b10 +#define CYREG_B1_UDB09_MSK_ACTL 0x40006b12 +#define CYREG_B1_UDB10_MSK_ACTL 0x40006b14 +#define CYREG_B1_UDB11_MSK_ACTL 0x40006b16 +#define CYREG_B1_UDB04_MC_00 0x40006b48 +#define CYREG_B1_UDB05_MC_00 0x40006b4a +#define CYREG_B1_UDB06_MC_00 0x40006b4c +#define CYREG_B1_UDB07_MC_00 0x40006b4e +#define CYREG_B1_UDB08_MC_00 0x40006b50 +#define CYREG_B1_UDB09_MC_00 0x40006b52 +#define CYREG_B1_UDB10_MC_00 0x40006b54 +#define CYREG_B1_UDB11_MC_00 0x40006b56 +#define CYDEV_UWRK_UWRK16_DEF_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_SIZE 0x0000075e +#define CYDEV_UWRK_UWRK16_DEF_B0_BASE 0x40006800 +#define CYDEV_UWRK_UWRK16_DEF_B0_SIZE 0x0000015e +#define CYREG_B0_UDB00_01_A0 0x40006800 +#define CYREG_B0_UDB01_02_A0 0x40006802 +#define CYREG_B0_UDB02_03_A0 0x40006804 +#define CYREG_B0_UDB03_04_A0 0x40006806 +#define CYREG_B0_UDB04_05_A0 0x40006808 +#define CYREG_B0_UDB05_06_A0 0x4000680a +#define CYREG_B0_UDB06_07_A0 0x4000680c +#define CYREG_B0_UDB07_08_A0 0x4000680e +#define CYREG_B0_UDB08_09_A0 0x40006810 +#define CYREG_B0_UDB09_10_A0 0x40006812 +#define CYREG_B0_UDB10_11_A0 0x40006814 +#define CYREG_B0_UDB11_12_A0 0x40006816 +#define CYREG_B0_UDB12_13_A0 0x40006818 +#define CYREG_B0_UDB13_14_A0 0x4000681a +#define CYREG_B0_UDB14_15_A0 0x4000681c +#define CYREG_B0_UDB00_01_A1 0x40006820 +#define CYREG_B0_UDB01_02_A1 0x40006822 +#define CYREG_B0_UDB02_03_A1 0x40006824 +#define CYREG_B0_UDB03_04_A1 0x40006826 +#define CYREG_B0_UDB04_05_A1 0x40006828 +#define CYREG_B0_UDB05_06_A1 0x4000682a +#define CYREG_B0_UDB06_07_A1 0x4000682c +#define CYREG_B0_UDB07_08_A1 0x4000682e +#define CYREG_B0_UDB08_09_A1 0x40006830 +#define CYREG_B0_UDB09_10_A1 0x40006832 +#define CYREG_B0_UDB10_11_A1 0x40006834 +#define CYREG_B0_UDB11_12_A1 0x40006836 +#define CYREG_B0_UDB12_13_A1 0x40006838 +#define CYREG_B0_UDB13_14_A1 0x4000683a +#define CYREG_B0_UDB14_15_A1 0x4000683c +#define CYREG_B0_UDB00_01_D0 0x40006840 +#define CYREG_B0_UDB01_02_D0 0x40006842 +#define CYREG_B0_UDB02_03_D0 0x40006844 +#define CYREG_B0_UDB03_04_D0 0x40006846 +#define CYREG_B0_UDB04_05_D0 0x40006848 +#define CYREG_B0_UDB05_06_D0 0x4000684a +#define CYREG_B0_UDB06_07_D0 0x4000684c +#define CYREG_B0_UDB07_08_D0 0x4000684e +#define CYREG_B0_UDB08_09_D0 0x40006850 +#define CYREG_B0_UDB09_10_D0 0x40006852 +#define CYREG_B0_UDB10_11_D0 0x40006854 +#define CYREG_B0_UDB11_12_D0 0x40006856 +#define CYREG_B0_UDB12_13_D0 0x40006858 +#define CYREG_B0_UDB13_14_D0 0x4000685a +#define CYREG_B0_UDB14_15_D0 0x4000685c +#define CYREG_B0_UDB00_01_D1 0x40006860 +#define CYREG_B0_UDB01_02_D1 0x40006862 +#define CYREG_B0_UDB02_03_D1 0x40006864 +#define CYREG_B0_UDB03_04_D1 0x40006866 +#define CYREG_B0_UDB04_05_D1 0x40006868 +#define CYREG_B0_UDB05_06_D1 0x4000686a +#define CYREG_B0_UDB06_07_D1 0x4000686c +#define CYREG_B0_UDB07_08_D1 0x4000686e +#define CYREG_B0_UDB08_09_D1 0x40006870 +#define CYREG_B0_UDB09_10_D1 0x40006872 +#define CYREG_B0_UDB10_11_D1 0x40006874 +#define CYREG_B0_UDB11_12_D1 0x40006876 +#define CYREG_B0_UDB12_13_D1 0x40006878 +#define CYREG_B0_UDB13_14_D1 0x4000687a +#define CYREG_B0_UDB14_15_D1 0x4000687c +#define CYREG_B0_UDB00_01_F0 0x40006880 +#define CYREG_B0_UDB01_02_F0 0x40006882 +#define CYREG_B0_UDB02_03_F0 0x40006884 +#define CYREG_B0_UDB03_04_F0 0x40006886 +#define CYREG_B0_UDB04_05_F0 0x40006888 +#define CYREG_B0_UDB05_06_F0 0x4000688a +#define CYREG_B0_UDB06_07_F0 0x4000688c +#define CYREG_B0_UDB07_08_F0 0x4000688e +#define CYREG_B0_UDB08_09_F0 0x40006890 +#define CYREG_B0_UDB09_10_F0 0x40006892 +#define CYREG_B0_UDB10_11_F0 0x40006894 +#define CYREG_B0_UDB11_12_F0 0x40006896 +#define CYREG_B0_UDB12_13_F0 0x40006898 +#define CYREG_B0_UDB13_14_F0 0x4000689a +#define CYREG_B0_UDB14_15_F0 0x4000689c +#define CYREG_B0_UDB00_01_F1 0x400068a0 +#define CYREG_B0_UDB01_02_F1 0x400068a2 +#define CYREG_B0_UDB02_03_F1 0x400068a4 +#define CYREG_B0_UDB03_04_F1 0x400068a6 +#define CYREG_B0_UDB04_05_F1 0x400068a8 +#define CYREG_B0_UDB05_06_F1 0x400068aa +#define CYREG_B0_UDB06_07_F1 0x400068ac +#define CYREG_B0_UDB07_08_F1 0x400068ae +#define CYREG_B0_UDB08_09_F1 0x400068b0 +#define CYREG_B0_UDB09_10_F1 0x400068b2 +#define CYREG_B0_UDB10_11_F1 0x400068b4 +#define CYREG_B0_UDB11_12_F1 0x400068b6 +#define CYREG_B0_UDB12_13_F1 0x400068b8 +#define CYREG_B0_UDB13_14_F1 0x400068ba +#define CYREG_B0_UDB14_15_F1 0x400068bc +#define CYREG_B0_UDB00_01_ST 0x400068c0 +#define CYREG_B0_UDB01_02_ST 0x400068c2 +#define CYREG_B0_UDB02_03_ST 0x400068c4 +#define CYREG_B0_UDB03_04_ST 0x400068c6 +#define CYREG_B0_UDB04_05_ST 0x400068c8 +#define CYREG_B0_UDB05_06_ST 0x400068ca +#define CYREG_B0_UDB06_07_ST 0x400068cc +#define CYREG_B0_UDB07_08_ST 0x400068ce +#define CYREG_B0_UDB08_09_ST 0x400068d0 +#define CYREG_B0_UDB09_10_ST 0x400068d2 +#define CYREG_B0_UDB10_11_ST 0x400068d4 +#define CYREG_B0_UDB11_12_ST 0x400068d6 +#define CYREG_B0_UDB12_13_ST 0x400068d8 +#define CYREG_B0_UDB13_14_ST 0x400068da +#define CYREG_B0_UDB14_15_ST 0x400068dc +#define CYREG_B0_UDB00_01_CTL 0x400068e0 +#define CYREG_B0_UDB01_02_CTL 0x400068e2 +#define CYREG_B0_UDB02_03_CTL 0x400068e4 +#define CYREG_B0_UDB03_04_CTL 0x400068e6 +#define CYREG_B0_UDB04_05_CTL 0x400068e8 +#define CYREG_B0_UDB05_06_CTL 0x400068ea +#define CYREG_B0_UDB06_07_CTL 0x400068ec +#define CYREG_B0_UDB07_08_CTL 0x400068ee +#define CYREG_B0_UDB08_09_CTL 0x400068f0 +#define CYREG_B0_UDB09_10_CTL 0x400068f2 +#define CYREG_B0_UDB10_11_CTL 0x400068f4 +#define CYREG_B0_UDB11_12_CTL 0x400068f6 +#define CYREG_B0_UDB12_13_CTL 0x400068f8 +#define CYREG_B0_UDB13_14_CTL 0x400068fa +#define CYREG_B0_UDB14_15_CTL 0x400068fc +#define CYREG_B0_UDB00_01_MSK 0x40006900 +#define CYREG_B0_UDB01_02_MSK 0x40006902 +#define CYREG_B0_UDB02_03_MSK 0x40006904 +#define CYREG_B0_UDB03_04_MSK 0x40006906 +#define CYREG_B0_UDB04_05_MSK 0x40006908 +#define CYREG_B0_UDB05_06_MSK 0x4000690a +#define CYREG_B0_UDB06_07_MSK 0x4000690c +#define CYREG_B0_UDB07_08_MSK 0x4000690e +#define CYREG_B0_UDB08_09_MSK 0x40006910 +#define CYREG_B0_UDB09_10_MSK 0x40006912 +#define CYREG_B0_UDB10_11_MSK 0x40006914 +#define CYREG_B0_UDB11_12_MSK 0x40006916 +#define CYREG_B0_UDB12_13_MSK 0x40006918 +#define CYREG_B0_UDB13_14_MSK 0x4000691a +#define CYREG_B0_UDB14_15_MSK 0x4000691c +#define CYREG_B0_UDB00_01_ACTL 0x40006920 +#define CYREG_B0_UDB01_02_ACTL 0x40006922 +#define CYREG_B0_UDB02_03_ACTL 0x40006924 +#define CYREG_B0_UDB03_04_ACTL 0x40006926 +#define CYREG_B0_UDB04_05_ACTL 0x40006928 +#define CYREG_B0_UDB05_06_ACTL 0x4000692a +#define CYREG_B0_UDB06_07_ACTL 0x4000692c +#define CYREG_B0_UDB07_08_ACTL 0x4000692e +#define CYREG_B0_UDB08_09_ACTL 0x40006930 +#define CYREG_B0_UDB09_10_ACTL 0x40006932 +#define CYREG_B0_UDB10_11_ACTL 0x40006934 +#define CYREG_B0_UDB11_12_ACTL 0x40006936 +#define CYREG_B0_UDB12_13_ACTL 0x40006938 +#define CYREG_B0_UDB13_14_ACTL 0x4000693a +#define CYREG_B0_UDB14_15_ACTL 0x4000693c +#define CYREG_B0_UDB00_01_MC 0x40006940 +#define CYREG_B0_UDB01_02_MC 0x40006942 +#define CYREG_B0_UDB02_03_MC 0x40006944 +#define CYREG_B0_UDB03_04_MC 0x40006946 +#define CYREG_B0_UDB04_05_MC 0x40006948 +#define CYREG_B0_UDB05_06_MC 0x4000694a +#define CYREG_B0_UDB06_07_MC 0x4000694c +#define CYREG_B0_UDB07_08_MC 0x4000694e +#define CYREG_B0_UDB08_09_MC 0x40006950 +#define CYREG_B0_UDB09_10_MC 0x40006952 +#define CYREG_B0_UDB10_11_MC 0x40006954 +#define CYREG_B0_UDB11_12_MC 0x40006956 +#define CYREG_B0_UDB12_13_MC 0x40006958 +#define CYREG_B0_UDB13_14_MC 0x4000695a +#define CYREG_B0_UDB14_15_MC 0x4000695c +#define CYDEV_UWRK_UWRK16_DEF_B1_BASE 0x40006a00 +#define CYDEV_UWRK_UWRK16_DEF_B1_SIZE 0x0000015e +#define CYREG_B1_UDB04_05_A0 0x40006a08 +#define CYREG_B1_UDB05_06_A0 0x40006a0a +#define CYREG_B1_UDB06_07_A0 0x40006a0c +#define CYREG_B1_UDB07_08_A0 0x40006a0e +#define CYREG_B1_UDB08_09_A0 0x40006a10 +#define CYREG_B1_UDB09_10_A0 0x40006a12 +#define CYREG_B1_UDB10_11_A0 0x40006a14 +#define CYREG_B1_UDB11_12_A0 0x40006a16 +#define CYREG_B1_UDB04_05_A1 0x40006a28 +#define CYREG_B1_UDB05_06_A1 0x40006a2a +#define CYREG_B1_UDB06_07_A1 0x40006a2c +#define CYREG_B1_UDB07_08_A1 0x40006a2e +#define CYREG_B1_UDB08_09_A1 0x40006a30 +#define CYREG_B1_UDB09_10_A1 0x40006a32 +#define CYREG_B1_UDB10_11_A1 0x40006a34 +#define CYREG_B1_UDB11_12_A1 0x40006a36 +#define CYREG_B1_UDB04_05_D0 0x40006a48 +#define CYREG_B1_UDB05_06_D0 0x40006a4a +#define CYREG_B1_UDB06_07_D0 0x40006a4c +#define CYREG_B1_UDB07_08_D0 0x40006a4e +#define CYREG_B1_UDB08_09_D0 0x40006a50 +#define CYREG_B1_UDB09_10_D0 0x40006a52 +#define CYREG_B1_UDB10_11_D0 0x40006a54 +#define CYREG_B1_UDB11_12_D0 0x40006a56 +#define CYREG_B1_UDB04_05_D1 0x40006a68 +#define CYREG_B1_UDB05_06_D1 0x40006a6a +#define CYREG_B1_UDB06_07_D1 0x40006a6c +#define CYREG_B1_UDB07_08_D1 0x40006a6e +#define CYREG_B1_UDB08_09_D1 0x40006a70 +#define CYREG_B1_UDB09_10_D1 0x40006a72 +#define CYREG_B1_UDB10_11_D1 0x40006a74 +#define CYREG_B1_UDB11_12_D1 0x40006a76 +#define CYREG_B1_UDB04_05_F0 0x40006a88 +#define CYREG_B1_UDB05_06_F0 0x40006a8a +#define CYREG_B1_UDB06_07_F0 0x40006a8c +#define CYREG_B1_UDB07_08_F0 0x40006a8e +#define CYREG_B1_UDB08_09_F0 0x40006a90 +#define CYREG_B1_UDB09_10_F0 0x40006a92 +#define CYREG_B1_UDB10_11_F0 0x40006a94 +#define CYREG_B1_UDB11_12_F0 0x40006a96 +#define CYREG_B1_UDB04_05_F1 0x40006aa8 +#define CYREG_B1_UDB05_06_F1 0x40006aaa +#define CYREG_B1_UDB06_07_F1 0x40006aac +#define CYREG_B1_UDB07_08_F1 0x40006aae +#define CYREG_B1_UDB08_09_F1 0x40006ab0 +#define CYREG_B1_UDB09_10_F1 0x40006ab2 +#define CYREG_B1_UDB10_11_F1 0x40006ab4 +#define CYREG_B1_UDB11_12_F1 0x40006ab6 +#define CYREG_B1_UDB04_05_ST 0x40006ac8 +#define CYREG_B1_UDB05_06_ST 0x40006aca +#define CYREG_B1_UDB06_07_ST 0x40006acc +#define CYREG_B1_UDB07_08_ST 0x40006ace +#define CYREG_B1_UDB08_09_ST 0x40006ad0 +#define CYREG_B1_UDB09_10_ST 0x40006ad2 +#define CYREG_B1_UDB10_11_ST 0x40006ad4 +#define CYREG_B1_UDB11_12_ST 0x40006ad6 +#define CYREG_B1_UDB04_05_CTL 0x40006ae8 +#define CYREG_B1_UDB05_06_CTL 0x40006aea +#define CYREG_B1_UDB06_07_CTL 0x40006aec +#define CYREG_B1_UDB07_08_CTL 0x40006aee +#define CYREG_B1_UDB08_09_CTL 0x40006af0 +#define CYREG_B1_UDB09_10_CTL 0x40006af2 +#define CYREG_B1_UDB10_11_CTL 0x40006af4 +#define CYREG_B1_UDB11_12_CTL 0x40006af6 +#define CYREG_B1_UDB04_05_MSK 0x40006b08 +#define CYREG_B1_UDB05_06_MSK 0x40006b0a +#define CYREG_B1_UDB06_07_MSK 0x40006b0c +#define CYREG_B1_UDB07_08_MSK 0x40006b0e +#define CYREG_B1_UDB08_09_MSK 0x40006b10 +#define CYREG_B1_UDB09_10_MSK 0x40006b12 +#define CYREG_B1_UDB10_11_MSK 0x40006b14 +#define CYREG_B1_UDB11_12_MSK 0x40006b16 +#define CYREG_B1_UDB04_05_ACTL 0x40006b28 +#define CYREG_B1_UDB05_06_ACTL 0x40006b2a +#define CYREG_B1_UDB06_07_ACTL 0x40006b2c +#define CYREG_B1_UDB07_08_ACTL 0x40006b2e +#define CYREG_B1_UDB08_09_ACTL 0x40006b30 +#define CYREG_B1_UDB09_10_ACTL 0x40006b32 +#define CYREG_B1_UDB10_11_ACTL 0x40006b34 +#define CYREG_B1_UDB11_12_ACTL 0x40006b36 +#define CYREG_B1_UDB04_05_MC 0x40006b48 +#define CYREG_B1_UDB05_06_MC 0x40006b4a +#define CYREG_B1_UDB06_07_MC 0x40006b4c +#define CYREG_B1_UDB07_08_MC 0x40006b4e +#define CYREG_B1_UDB08_09_MC 0x40006b50 +#define CYREG_B1_UDB09_10_MC 0x40006b52 +#define CYREG_B1_UDB10_11_MC 0x40006b54 +#define CYREG_B1_UDB11_12_MC 0x40006b56 +#define CYDEV_PHUB_BASE 0x40007000 +#define CYDEV_PHUB_SIZE 0x00000c00 +#define CYREG_PHUB_CFG 0x40007000 +#define CYREG_PHUB_ERR 0x40007004 +#define CYREG_PHUB_ERR_ADR 0x40007008 +#define CYDEV_PHUB_CH0_BASE 0x40007010 +#define CYDEV_PHUB_CH0_SIZE 0x0000000c +#define CYREG_PHUB_CH0_BASIC_CFG 0x40007010 +#define CYREG_PHUB_CH0_ACTION 0x40007014 +#define CYREG_PHUB_CH0_BASIC_STATUS 0x40007018 +#define CYDEV_PHUB_CH1_BASE 0x40007020 +#define CYDEV_PHUB_CH1_SIZE 0x0000000c +#define CYREG_PHUB_CH1_BASIC_CFG 0x40007020 +#define CYREG_PHUB_CH1_ACTION 0x40007024 +#define CYREG_PHUB_CH1_BASIC_STATUS 0x40007028 +#define CYDEV_PHUB_CH2_BASE 0x40007030 +#define CYDEV_PHUB_CH2_SIZE 0x0000000c +#define CYREG_PHUB_CH2_BASIC_CFG 0x40007030 +#define CYREG_PHUB_CH2_ACTION 0x40007034 +#define CYREG_PHUB_CH2_BASIC_STATUS 0x40007038 +#define CYDEV_PHUB_CH3_BASE 0x40007040 +#define CYDEV_PHUB_CH3_SIZE 0x0000000c +#define CYREG_PHUB_CH3_BASIC_CFG 0x40007040 +#define CYREG_PHUB_CH3_ACTION 0x40007044 +#define CYREG_PHUB_CH3_BASIC_STATUS 0x40007048 +#define CYDEV_PHUB_CH4_BASE 0x40007050 +#define CYDEV_PHUB_CH4_SIZE 0x0000000c +#define CYREG_PHUB_CH4_BASIC_CFG 0x40007050 +#define CYREG_PHUB_CH4_ACTION 0x40007054 +#define CYREG_PHUB_CH4_BASIC_STATUS 0x40007058 +#define CYDEV_PHUB_CH5_BASE 0x40007060 +#define CYDEV_PHUB_CH5_SIZE 0x0000000c +#define CYREG_PHUB_CH5_BASIC_CFG 0x40007060 +#define CYREG_PHUB_CH5_ACTION 0x40007064 +#define CYREG_PHUB_CH5_BASIC_STATUS 0x40007068 +#define CYDEV_PHUB_CH6_BASE 0x40007070 +#define CYDEV_PHUB_CH6_SIZE 0x0000000c +#define CYREG_PHUB_CH6_BASIC_CFG 0x40007070 +#define CYREG_PHUB_CH6_ACTION 0x40007074 +#define CYREG_PHUB_CH6_BASIC_STATUS 0x40007078 +#define CYDEV_PHUB_CH7_BASE 0x40007080 +#define CYDEV_PHUB_CH7_SIZE 0x0000000c +#define CYREG_PHUB_CH7_BASIC_CFG 0x40007080 +#define CYREG_PHUB_CH7_ACTION 0x40007084 +#define CYREG_PHUB_CH7_BASIC_STATUS 0x40007088 +#define CYDEV_PHUB_CH8_BASE 0x40007090 +#define CYDEV_PHUB_CH8_SIZE 0x0000000c +#define CYREG_PHUB_CH8_BASIC_CFG 0x40007090 +#define CYREG_PHUB_CH8_ACTION 0x40007094 +#define CYREG_PHUB_CH8_BASIC_STATUS 0x40007098 +#define CYDEV_PHUB_CH9_BASE 0x400070a0 +#define CYDEV_PHUB_CH9_SIZE 0x0000000c +#define CYREG_PHUB_CH9_BASIC_CFG 0x400070a0 +#define CYREG_PHUB_CH9_ACTION 0x400070a4 +#define CYREG_PHUB_CH9_BASIC_STATUS 0x400070a8 +#define CYDEV_PHUB_CH10_BASE 0x400070b0 +#define CYDEV_PHUB_CH10_SIZE 0x0000000c +#define CYREG_PHUB_CH10_BASIC_CFG 0x400070b0 +#define CYREG_PHUB_CH10_ACTION 0x400070b4 +#define CYREG_PHUB_CH10_BASIC_STATUS 0x400070b8 +#define CYDEV_PHUB_CH11_BASE 0x400070c0 +#define CYDEV_PHUB_CH11_SIZE 0x0000000c +#define CYREG_PHUB_CH11_BASIC_CFG 0x400070c0 +#define CYREG_PHUB_CH11_ACTION 0x400070c4 +#define CYREG_PHUB_CH11_BASIC_STATUS 0x400070c8 +#define CYDEV_PHUB_CH12_BASE 0x400070d0 +#define CYDEV_PHUB_CH12_SIZE 0x0000000c +#define CYREG_PHUB_CH12_BASIC_CFG 0x400070d0 +#define CYREG_PHUB_CH12_ACTION 0x400070d4 +#define CYREG_PHUB_CH12_BASIC_STATUS 0x400070d8 +#define CYDEV_PHUB_CH13_BASE 0x400070e0 +#define CYDEV_PHUB_CH13_SIZE 0x0000000c +#define CYREG_PHUB_CH13_BASIC_CFG 0x400070e0 +#define CYREG_PHUB_CH13_ACTION 0x400070e4 +#define CYREG_PHUB_CH13_BASIC_STATUS 0x400070e8 +#define CYDEV_PHUB_CH14_BASE 0x400070f0 +#define CYDEV_PHUB_CH14_SIZE 0x0000000c +#define CYREG_PHUB_CH14_BASIC_CFG 0x400070f0 +#define CYREG_PHUB_CH14_ACTION 0x400070f4 +#define CYREG_PHUB_CH14_BASIC_STATUS 0x400070f8 +#define CYDEV_PHUB_CH15_BASE 0x40007100 +#define CYDEV_PHUB_CH15_SIZE 0x0000000c +#define CYREG_PHUB_CH15_BASIC_CFG 0x40007100 +#define CYREG_PHUB_CH15_ACTION 0x40007104 +#define CYREG_PHUB_CH15_BASIC_STATUS 0x40007108 +#define CYDEV_PHUB_CH16_BASE 0x40007110 +#define CYDEV_PHUB_CH16_SIZE 0x0000000c +#define CYREG_PHUB_CH16_BASIC_CFG 0x40007110 +#define CYREG_PHUB_CH16_ACTION 0x40007114 +#define CYREG_PHUB_CH16_BASIC_STATUS 0x40007118 +#define CYDEV_PHUB_CH17_BASE 0x40007120 +#define CYDEV_PHUB_CH17_SIZE 0x0000000c +#define CYREG_PHUB_CH17_BASIC_CFG 0x40007120 +#define CYREG_PHUB_CH17_ACTION 0x40007124 +#define CYREG_PHUB_CH17_BASIC_STATUS 0x40007128 +#define CYDEV_PHUB_CH18_BASE 0x40007130 +#define CYDEV_PHUB_CH18_SIZE 0x0000000c +#define CYREG_PHUB_CH18_BASIC_CFG 0x40007130 +#define CYREG_PHUB_CH18_ACTION 0x40007134 +#define CYREG_PHUB_CH18_BASIC_STATUS 0x40007138 +#define CYDEV_PHUB_CH19_BASE 0x40007140 +#define CYDEV_PHUB_CH19_SIZE 0x0000000c +#define CYREG_PHUB_CH19_BASIC_CFG 0x40007140 +#define CYREG_PHUB_CH19_ACTION 0x40007144 +#define CYREG_PHUB_CH19_BASIC_STATUS 0x40007148 +#define CYDEV_PHUB_CH20_BASE 0x40007150 +#define CYDEV_PHUB_CH20_SIZE 0x0000000c +#define CYREG_PHUB_CH20_BASIC_CFG 0x40007150 +#define CYREG_PHUB_CH20_ACTION 0x40007154 +#define CYREG_PHUB_CH20_BASIC_STATUS 0x40007158 +#define CYDEV_PHUB_CH21_BASE 0x40007160 +#define CYDEV_PHUB_CH21_SIZE 0x0000000c +#define CYREG_PHUB_CH21_BASIC_CFG 0x40007160 +#define CYREG_PHUB_CH21_ACTION 0x40007164 +#define CYREG_PHUB_CH21_BASIC_STATUS 0x40007168 +#define CYDEV_PHUB_CH22_BASE 0x40007170 +#define CYDEV_PHUB_CH22_SIZE 0x0000000c +#define CYREG_PHUB_CH22_BASIC_CFG 0x40007170 +#define CYREG_PHUB_CH22_ACTION 0x40007174 +#define CYREG_PHUB_CH22_BASIC_STATUS 0x40007178 +#define CYDEV_PHUB_CH23_BASE 0x40007180 +#define CYDEV_PHUB_CH23_SIZE 0x0000000c +#define CYREG_PHUB_CH23_BASIC_CFG 0x40007180 +#define CYREG_PHUB_CH23_ACTION 0x40007184 +#define CYREG_PHUB_CH23_BASIC_STATUS 0x40007188 +#define CYDEV_PHUB_CFGMEM0_BASE 0x40007600 +#define CYDEV_PHUB_CFGMEM0_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM0_CFG0 0x40007600 +#define CYREG_PHUB_CFGMEM0_CFG1 0x40007604 +#define CYDEV_PHUB_CFGMEM1_BASE 0x40007608 +#define CYDEV_PHUB_CFGMEM1_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM1_CFG0 0x40007608 +#define CYREG_PHUB_CFGMEM1_CFG1 0x4000760c +#define CYDEV_PHUB_CFGMEM2_BASE 0x40007610 +#define CYDEV_PHUB_CFGMEM2_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM2_CFG0 0x40007610 +#define CYREG_PHUB_CFGMEM2_CFG1 0x40007614 +#define CYDEV_PHUB_CFGMEM3_BASE 0x40007618 +#define CYDEV_PHUB_CFGMEM3_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM3_CFG0 0x40007618 +#define CYREG_PHUB_CFGMEM3_CFG1 0x4000761c +#define CYDEV_PHUB_CFGMEM4_BASE 0x40007620 +#define CYDEV_PHUB_CFGMEM4_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM4_CFG0 0x40007620 +#define CYREG_PHUB_CFGMEM4_CFG1 0x40007624 +#define CYDEV_PHUB_CFGMEM5_BASE 0x40007628 +#define CYDEV_PHUB_CFGMEM5_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM5_CFG0 0x40007628 +#define CYREG_PHUB_CFGMEM5_CFG1 0x4000762c +#define CYDEV_PHUB_CFGMEM6_BASE 0x40007630 +#define CYDEV_PHUB_CFGMEM6_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM6_CFG0 0x40007630 +#define CYREG_PHUB_CFGMEM6_CFG1 0x40007634 +#define CYDEV_PHUB_CFGMEM7_BASE 0x40007638 +#define CYDEV_PHUB_CFGMEM7_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM7_CFG0 0x40007638 +#define CYREG_PHUB_CFGMEM7_CFG1 0x4000763c +#define CYDEV_PHUB_CFGMEM8_BASE 0x40007640 +#define CYDEV_PHUB_CFGMEM8_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM8_CFG0 0x40007640 +#define CYREG_PHUB_CFGMEM8_CFG1 0x40007644 +#define CYDEV_PHUB_CFGMEM9_BASE 0x40007648 +#define CYDEV_PHUB_CFGMEM9_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM9_CFG0 0x40007648 +#define CYREG_PHUB_CFGMEM9_CFG1 0x4000764c +#define CYDEV_PHUB_CFGMEM10_BASE 0x40007650 +#define CYDEV_PHUB_CFGMEM10_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM10_CFG0 0x40007650 +#define CYREG_PHUB_CFGMEM10_CFG1 0x40007654 +#define CYDEV_PHUB_CFGMEM11_BASE 0x40007658 +#define CYDEV_PHUB_CFGMEM11_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM11_CFG0 0x40007658 +#define CYREG_PHUB_CFGMEM11_CFG1 0x4000765c +#define CYDEV_PHUB_CFGMEM12_BASE 0x40007660 +#define CYDEV_PHUB_CFGMEM12_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM12_CFG0 0x40007660 +#define CYREG_PHUB_CFGMEM12_CFG1 0x40007664 +#define CYDEV_PHUB_CFGMEM13_BASE 0x40007668 +#define CYDEV_PHUB_CFGMEM13_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM13_CFG0 0x40007668 +#define CYREG_PHUB_CFGMEM13_CFG1 0x4000766c +#define CYDEV_PHUB_CFGMEM14_BASE 0x40007670 +#define CYDEV_PHUB_CFGMEM14_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM14_CFG0 0x40007670 +#define CYREG_PHUB_CFGMEM14_CFG1 0x40007674 +#define CYDEV_PHUB_CFGMEM15_BASE 0x40007678 +#define CYDEV_PHUB_CFGMEM15_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM15_CFG0 0x40007678 +#define CYREG_PHUB_CFGMEM15_CFG1 0x4000767c +#define CYDEV_PHUB_CFGMEM16_BASE 0x40007680 +#define CYDEV_PHUB_CFGMEM16_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM16_CFG0 0x40007680 +#define CYREG_PHUB_CFGMEM16_CFG1 0x40007684 +#define CYDEV_PHUB_CFGMEM17_BASE 0x40007688 +#define CYDEV_PHUB_CFGMEM17_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM17_CFG0 0x40007688 +#define CYREG_PHUB_CFGMEM17_CFG1 0x4000768c +#define CYDEV_PHUB_CFGMEM18_BASE 0x40007690 +#define CYDEV_PHUB_CFGMEM18_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM18_CFG0 0x40007690 +#define CYREG_PHUB_CFGMEM18_CFG1 0x40007694 +#define CYDEV_PHUB_CFGMEM19_BASE 0x40007698 +#define CYDEV_PHUB_CFGMEM19_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM19_CFG0 0x40007698 +#define CYREG_PHUB_CFGMEM19_CFG1 0x4000769c +#define CYDEV_PHUB_CFGMEM20_BASE 0x400076a0 +#define CYDEV_PHUB_CFGMEM20_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM20_CFG0 0x400076a0 +#define CYREG_PHUB_CFGMEM20_CFG1 0x400076a4 +#define CYDEV_PHUB_CFGMEM21_BASE 0x400076a8 +#define CYDEV_PHUB_CFGMEM21_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM21_CFG0 0x400076a8 +#define CYREG_PHUB_CFGMEM21_CFG1 0x400076ac +#define CYDEV_PHUB_CFGMEM22_BASE 0x400076b0 +#define CYDEV_PHUB_CFGMEM22_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM22_CFG0 0x400076b0 +#define CYREG_PHUB_CFGMEM22_CFG1 0x400076b4 +#define CYDEV_PHUB_CFGMEM23_BASE 0x400076b8 +#define CYDEV_PHUB_CFGMEM23_SIZE 0x00000008 +#define CYREG_PHUB_CFGMEM23_CFG0 0x400076b8 +#define CYREG_PHUB_CFGMEM23_CFG1 0x400076bc +#define CYDEV_PHUB_TDMEM0_BASE 0x40007800 +#define CYDEV_PHUB_TDMEM0_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM0_ORIG_TD0 0x40007800 +#define CYREG_PHUB_TDMEM0_ORIG_TD1 0x40007804 +#define CYDEV_PHUB_TDMEM1_BASE 0x40007808 +#define CYDEV_PHUB_TDMEM1_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM1_ORIG_TD0 0x40007808 +#define CYREG_PHUB_TDMEM1_ORIG_TD1 0x4000780c +#define CYDEV_PHUB_TDMEM2_BASE 0x40007810 +#define CYDEV_PHUB_TDMEM2_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM2_ORIG_TD0 0x40007810 +#define CYREG_PHUB_TDMEM2_ORIG_TD1 0x40007814 +#define CYDEV_PHUB_TDMEM3_BASE 0x40007818 +#define CYDEV_PHUB_TDMEM3_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM3_ORIG_TD0 0x40007818 +#define CYREG_PHUB_TDMEM3_ORIG_TD1 0x4000781c +#define CYDEV_PHUB_TDMEM4_BASE 0x40007820 +#define CYDEV_PHUB_TDMEM4_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM4_ORIG_TD0 0x40007820 +#define CYREG_PHUB_TDMEM4_ORIG_TD1 0x40007824 +#define CYDEV_PHUB_TDMEM5_BASE 0x40007828 +#define CYDEV_PHUB_TDMEM5_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM5_ORIG_TD0 0x40007828 +#define CYREG_PHUB_TDMEM5_ORIG_TD1 0x4000782c +#define CYDEV_PHUB_TDMEM6_BASE 0x40007830 +#define CYDEV_PHUB_TDMEM6_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM6_ORIG_TD0 0x40007830 +#define CYREG_PHUB_TDMEM6_ORIG_TD1 0x40007834 +#define CYDEV_PHUB_TDMEM7_BASE 0x40007838 +#define CYDEV_PHUB_TDMEM7_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM7_ORIG_TD0 0x40007838 +#define CYREG_PHUB_TDMEM7_ORIG_TD1 0x4000783c +#define CYDEV_PHUB_TDMEM8_BASE 0x40007840 +#define CYDEV_PHUB_TDMEM8_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM8_ORIG_TD0 0x40007840 +#define CYREG_PHUB_TDMEM8_ORIG_TD1 0x40007844 +#define CYDEV_PHUB_TDMEM9_BASE 0x40007848 +#define CYDEV_PHUB_TDMEM9_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM9_ORIG_TD0 0x40007848 +#define CYREG_PHUB_TDMEM9_ORIG_TD1 0x4000784c +#define CYDEV_PHUB_TDMEM10_BASE 0x40007850 +#define CYDEV_PHUB_TDMEM10_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM10_ORIG_TD0 0x40007850 +#define CYREG_PHUB_TDMEM10_ORIG_TD1 0x40007854 +#define CYDEV_PHUB_TDMEM11_BASE 0x40007858 +#define CYDEV_PHUB_TDMEM11_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM11_ORIG_TD0 0x40007858 +#define CYREG_PHUB_TDMEM11_ORIG_TD1 0x4000785c +#define CYDEV_PHUB_TDMEM12_BASE 0x40007860 +#define CYDEV_PHUB_TDMEM12_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM12_ORIG_TD0 0x40007860 +#define CYREG_PHUB_TDMEM12_ORIG_TD1 0x40007864 +#define CYDEV_PHUB_TDMEM13_BASE 0x40007868 +#define CYDEV_PHUB_TDMEM13_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM13_ORIG_TD0 0x40007868 +#define CYREG_PHUB_TDMEM13_ORIG_TD1 0x4000786c +#define CYDEV_PHUB_TDMEM14_BASE 0x40007870 +#define CYDEV_PHUB_TDMEM14_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM14_ORIG_TD0 0x40007870 +#define CYREG_PHUB_TDMEM14_ORIG_TD1 0x40007874 +#define CYDEV_PHUB_TDMEM15_BASE 0x40007878 +#define CYDEV_PHUB_TDMEM15_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM15_ORIG_TD0 0x40007878 +#define CYREG_PHUB_TDMEM15_ORIG_TD1 0x4000787c +#define CYDEV_PHUB_TDMEM16_BASE 0x40007880 +#define CYDEV_PHUB_TDMEM16_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM16_ORIG_TD0 0x40007880 +#define CYREG_PHUB_TDMEM16_ORIG_TD1 0x40007884 +#define CYDEV_PHUB_TDMEM17_BASE 0x40007888 +#define CYDEV_PHUB_TDMEM17_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM17_ORIG_TD0 0x40007888 +#define CYREG_PHUB_TDMEM17_ORIG_TD1 0x4000788c +#define CYDEV_PHUB_TDMEM18_BASE 0x40007890 +#define CYDEV_PHUB_TDMEM18_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM18_ORIG_TD0 0x40007890 +#define CYREG_PHUB_TDMEM18_ORIG_TD1 0x40007894 +#define CYDEV_PHUB_TDMEM19_BASE 0x40007898 +#define CYDEV_PHUB_TDMEM19_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM19_ORIG_TD0 0x40007898 +#define CYREG_PHUB_TDMEM19_ORIG_TD1 0x4000789c +#define CYDEV_PHUB_TDMEM20_BASE 0x400078a0 +#define CYDEV_PHUB_TDMEM20_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM20_ORIG_TD0 0x400078a0 +#define CYREG_PHUB_TDMEM20_ORIG_TD1 0x400078a4 +#define CYDEV_PHUB_TDMEM21_BASE 0x400078a8 +#define CYDEV_PHUB_TDMEM21_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM21_ORIG_TD0 0x400078a8 +#define CYREG_PHUB_TDMEM21_ORIG_TD1 0x400078ac +#define CYDEV_PHUB_TDMEM22_BASE 0x400078b0 +#define CYDEV_PHUB_TDMEM22_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM22_ORIG_TD0 0x400078b0 +#define CYREG_PHUB_TDMEM22_ORIG_TD1 0x400078b4 +#define CYDEV_PHUB_TDMEM23_BASE 0x400078b8 +#define CYDEV_PHUB_TDMEM23_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM23_ORIG_TD0 0x400078b8 +#define CYREG_PHUB_TDMEM23_ORIG_TD1 0x400078bc +#define CYDEV_PHUB_TDMEM24_BASE 0x400078c0 +#define CYDEV_PHUB_TDMEM24_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM24_ORIG_TD0 0x400078c0 +#define CYREG_PHUB_TDMEM24_ORIG_TD1 0x400078c4 +#define CYDEV_PHUB_TDMEM25_BASE 0x400078c8 +#define CYDEV_PHUB_TDMEM25_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM25_ORIG_TD0 0x400078c8 +#define CYREG_PHUB_TDMEM25_ORIG_TD1 0x400078cc +#define CYDEV_PHUB_TDMEM26_BASE 0x400078d0 +#define CYDEV_PHUB_TDMEM26_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM26_ORIG_TD0 0x400078d0 +#define CYREG_PHUB_TDMEM26_ORIG_TD1 0x400078d4 +#define CYDEV_PHUB_TDMEM27_BASE 0x400078d8 +#define CYDEV_PHUB_TDMEM27_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM27_ORIG_TD0 0x400078d8 +#define CYREG_PHUB_TDMEM27_ORIG_TD1 0x400078dc +#define CYDEV_PHUB_TDMEM28_BASE 0x400078e0 +#define CYDEV_PHUB_TDMEM28_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM28_ORIG_TD0 0x400078e0 +#define CYREG_PHUB_TDMEM28_ORIG_TD1 0x400078e4 +#define CYDEV_PHUB_TDMEM29_BASE 0x400078e8 +#define CYDEV_PHUB_TDMEM29_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM29_ORIG_TD0 0x400078e8 +#define CYREG_PHUB_TDMEM29_ORIG_TD1 0x400078ec +#define CYDEV_PHUB_TDMEM30_BASE 0x400078f0 +#define CYDEV_PHUB_TDMEM30_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM30_ORIG_TD0 0x400078f0 +#define CYREG_PHUB_TDMEM30_ORIG_TD1 0x400078f4 +#define CYDEV_PHUB_TDMEM31_BASE 0x400078f8 +#define CYDEV_PHUB_TDMEM31_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM31_ORIG_TD0 0x400078f8 +#define CYREG_PHUB_TDMEM31_ORIG_TD1 0x400078fc +#define CYDEV_PHUB_TDMEM32_BASE 0x40007900 +#define CYDEV_PHUB_TDMEM32_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM32_ORIG_TD0 0x40007900 +#define CYREG_PHUB_TDMEM32_ORIG_TD1 0x40007904 +#define CYDEV_PHUB_TDMEM33_BASE 0x40007908 +#define CYDEV_PHUB_TDMEM33_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM33_ORIG_TD0 0x40007908 +#define CYREG_PHUB_TDMEM33_ORIG_TD1 0x4000790c +#define CYDEV_PHUB_TDMEM34_BASE 0x40007910 +#define CYDEV_PHUB_TDMEM34_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM34_ORIG_TD0 0x40007910 +#define CYREG_PHUB_TDMEM34_ORIG_TD1 0x40007914 +#define CYDEV_PHUB_TDMEM35_BASE 0x40007918 +#define CYDEV_PHUB_TDMEM35_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM35_ORIG_TD0 0x40007918 +#define CYREG_PHUB_TDMEM35_ORIG_TD1 0x4000791c +#define CYDEV_PHUB_TDMEM36_BASE 0x40007920 +#define CYDEV_PHUB_TDMEM36_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM36_ORIG_TD0 0x40007920 +#define CYREG_PHUB_TDMEM36_ORIG_TD1 0x40007924 +#define CYDEV_PHUB_TDMEM37_BASE 0x40007928 +#define CYDEV_PHUB_TDMEM37_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM37_ORIG_TD0 0x40007928 +#define CYREG_PHUB_TDMEM37_ORIG_TD1 0x4000792c +#define CYDEV_PHUB_TDMEM38_BASE 0x40007930 +#define CYDEV_PHUB_TDMEM38_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM38_ORIG_TD0 0x40007930 +#define CYREG_PHUB_TDMEM38_ORIG_TD1 0x40007934 +#define CYDEV_PHUB_TDMEM39_BASE 0x40007938 +#define CYDEV_PHUB_TDMEM39_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM39_ORIG_TD0 0x40007938 +#define CYREG_PHUB_TDMEM39_ORIG_TD1 0x4000793c +#define CYDEV_PHUB_TDMEM40_BASE 0x40007940 +#define CYDEV_PHUB_TDMEM40_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM40_ORIG_TD0 0x40007940 +#define CYREG_PHUB_TDMEM40_ORIG_TD1 0x40007944 +#define CYDEV_PHUB_TDMEM41_BASE 0x40007948 +#define CYDEV_PHUB_TDMEM41_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM41_ORIG_TD0 0x40007948 +#define CYREG_PHUB_TDMEM41_ORIG_TD1 0x4000794c +#define CYDEV_PHUB_TDMEM42_BASE 0x40007950 +#define CYDEV_PHUB_TDMEM42_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM42_ORIG_TD0 0x40007950 +#define CYREG_PHUB_TDMEM42_ORIG_TD1 0x40007954 +#define CYDEV_PHUB_TDMEM43_BASE 0x40007958 +#define CYDEV_PHUB_TDMEM43_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM43_ORIG_TD0 0x40007958 +#define CYREG_PHUB_TDMEM43_ORIG_TD1 0x4000795c +#define CYDEV_PHUB_TDMEM44_BASE 0x40007960 +#define CYDEV_PHUB_TDMEM44_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM44_ORIG_TD0 0x40007960 +#define CYREG_PHUB_TDMEM44_ORIG_TD1 0x40007964 +#define CYDEV_PHUB_TDMEM45_BASE 0x40007968 +#define CYDEV_PHUB_TDMEM45_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM45_ORIG_TD0 0x40007968 +#define CYREG_PHUB_TDMEM45_ORIG_TD1 0x4000796c +#define CYDEV_PHUB_TDMEM46_BASE 0x40007970 +#define CYDEV_PHUB_TDMEM46_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM46_ORIG_TD0 0x40007970 +#define CYREG_PHUB_TDMEM46_ORIG_TD1 0x40007974 +#define CYDEV_PHUB_TDMEM47_BASE 0x40007978 +#define CYDEV_PHUB_TDMEM47_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM47_ORIG_TD0 0x40007978 +#define CYREG_PHUB_TDMEM47_ORIG_TD1 0x4000797c +#define CYDEV_PHUB_TDMEM48_BASE 0x40007980 +#define CYDEV_PHUB_TDMEM48_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM48_ORIG_TD0 0x40007980 +#define CYREG_PHUB_TDMEM48_ORIG_TD1 0x40007984 +#define CYDEV_PHUB_TDMEM49_BASE 0x40007988 +#define CYDEV_PHUB_TDMEM49_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM49_ORIG_TD0 0x40007988 +#define CYREG_PHUB_TDMEM49_ORIG_TD1 0x4000798c +#define CYDEV_PHUB_TDMEM50_BASE 0x40007990 +#define CYDEV_PHUB_TDMEM50_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM50_ORIG_TD0 0x40007990 +#define CYREG_PHUB_TDMEM50_ORIG_TD1 0x40007994 +#define CYDEV_PHUB_TDMEM51_BASE 0x40007998 +#define CYDEV_PHUB_TDMEM51_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM51_ORIG_TD0 0x40007998 +#define CYREG_PHUB_TDMEM51_ORIG_TD1 0x4000799c +#define CYDEV_PHUB_TDMEM52_BASE 0x400079a0 +#define CYDEV_PHUB_TDMEM52_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM52_ORIG_TD0 0x400079a0 +#define CYREG_PHUB_TDMEM52_ORIG_TD1 0x400079a4 +#define CYDEV_PHUB_TDMEM53_BASE 0x400079a8 +#define CYDEV_PHUB_TDMEM53_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM53_ORIG_TD0 0x400079a8 +#define CYREG_PHUB_TDMEM53_ORIG_TD1 0x400079ac +#define CYDEV_PHUB_TDMEM54_BASE 0x400079b0 +#define CYDEV_PHUB_TDMEM54_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM54_ORIG_TD0 0x400079b0 +#define CYREG_PHUB_TDMEM54_ORIG_TD1 0x400079b4 +#define CYDEV_PHUB_TDMEM55_BASE 0x400079b8 +#define CYDEV_PHUB_TDMEM55_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM55_ORIG_TD0 0x400079b8 +#define CYREG_PHUB_TDMEM55_ORIG_TD1 0x400079bc +#define CYDEV_PHUB_TDMEM56_BASE 0x400079c0 +#define CYDEV_PHUB_TDMEM56_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM56_ORIG_TD0 0x400079c0 +#define CYREG_PHUB_TDMEM56_ORIG_TD1 0x400079c4 +#define CYDEV_PHUB_TDMEM57_BASE 0x400079c8 +#define CYDEV_PHUB_TDMEM57_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM57_ORIG_TD0 0x400079c8 +#define CYREG_PHUB_TDMEM57_ORIG_TD1 0x400079cc +#define CYDEV_PHUB_TDMEM58_BASE 0x400079d0 +#define CYDEV_PHUB_TDMEM58_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM58_ORIG_TD0 0x400079d0 +#define CYREG_PHUB_TDMEM58_ORIG_TD1 0x400079d4 +#define CYDEV_PHUB_TDMEM59_BASE 0x400079d8 +#define CYDEV_PHUB_TDMEM59_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM59_ORIG_TD0 0x400079d8 +#define CYREG_PHUB_TDMEM59_ORIG_TD1 0x400079dc +#define CYDEV_PHUB_TDMEM60_BASE 0x400079e0 +#define CYDEV_PHUB_TDMEM60_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM60_ORIG_TD0 0x400079e0 +#define CYREG_PHUB_TDMEM60_ORIG_TD1 0x400079e4 +#define CYDEV_PHUB_TDMEM61_BASE 0x400079e8 +#define CYDEV_PHUB_TDMEM61_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM61_ORIG_TD0 0x400079e8 +#define CYREG_PHUB_TDMEM61_ORIG_TD1 0x400079ec +#define CYDEV_PHUB_TDMEM62_BASE 0x400079f0 +#define CYDEV_PHUB_TDMEM62_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM62_ORIG_TD0 0x400079f0 +#define CYREG_PHUB_TDMEM62_ORIG_TD1 0x400079f4 +#define CYDEV_PHUB_TDMEM63_BASE 0x400079f8 +#define CYDEV_PHUB_TDMEM63_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM63_ORIG_TD0 0x400079f8 +#define CYREG_PHUB_TDMEM63_ORIG_TD1 0x400079fc +#define CYDEV_PHUB_TDMEM64_BASE 0x40007a00 +#define CYDEV_PHUB_TDMEM64_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM64_ORIG_TD0 0x40007a00 +#define CYREG_PHUB_TDMEM64_ORIG_TD1 0x40007a04 +#define CYDEV_PHUB_TDMEM65_BASE 0x40007a08 +#define CYDEV_PHUB_TDMEM65_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM65_ORIG_TD0 0x40007a08 +#define CYREG_PHUB_TDMEM65_ORIG_TD1 0x40007a0c +#define CYDEV_PHUB_TDMEM66_BASE 0x40007a10 +#define CYDEV_PHUB_TDMEM66_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM66_ORIG_TD0 0x40007a10 +#define CYREG_PHUB_TDMEM66_ORIG_TD1 0x40007a14 +#define CYDEV_PHUB_TDMEM67_BASE 0x40007a18 +#define CYDEV_PHUB_TDMEM67_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM67_ORIG_TD0 0x40007a18 +#define CYREG_PHUB_TDMEM67_ORIG_TD1 0x40007a1c +#define CYDEV_PHUB_TDMEM68_BASE 0x40007a20 +#define CYDEV_PHUB_TDMEM68_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM68_ORIG_TD0 0x40007a20 +#define CYREG_PHUB_TDMEM68_ORIG_TD1 0x40007a24 +#define CYDEV_PHUB_TDMEM69_BASE 0x40007a28 +#define CYDEV_PHUB_TDMEM69_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM69_ORIG_TD0 0x40007a28 +#define CYREG_PHUB_TDMEM69_ORIG_TD1 0x40007a2c +#define CYDEV_PHUB_TDMEM70_BASE 0x40007a30 +#define CYDEV_PHUB_TDMEM70_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM70_ORIG_TD0 0x40007a30 +#define CYREG_PHUB_TDMEM70_ORIG_TD1 0x40007a34 +#define CYDEV_PHUB_TDMEM71_BASE 0x40007a38 +#define CYDEV_PHUB_TDMEM71_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM71_ORIG_TD0 0x40007a38 +#define CYREG_PHUB_TDMEM71_ORIG_TD1 0x40007a3c +#define CYDEV_PHUB_TDMEM72_BASE 0x40007a40 +#define CYDEV_PHUB_TDMEM72_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM72_ORIG_TD0 0x40007a40 +#define CYREG_PHUB_TDMEM72_ORIG_TD1 0x40007a44 +#define CYDEV_PHUB_TDMEM73_BASE 0x40007a48 +#define CYDEV_PHUB_TDMEM73_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM73_ORIG_TD0 0x40007a48 +#define CYREG_PHUB_TDMEM73_ORIG_TD1 0x40007a4c +#define CYDEV_PHUB_TDMEM74_BASE 0x40007a50 +#define CYDEV_PHUB_TDMEM74_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM74_ORIG_TD0 0x40007a50 +#define CYREG_PHUB_TDMEM74_ORIG_TD1 0x40007a54 +#define CYDEV_PHUB_TDMEM75_BASE 0x40007a58 +#define CYDEV_PHUB_TDMEM75_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM75_ORIG_TD0 0x40007a58 +#define CYREG_PHUB_TDMEM75_ORIG_TD1 0x40007a5c +#define CYDEV_PHUB_TDMEM76_BASE 0x40007a60 +#define CYDEV_PHUB_TDMEM76_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM76_ORIG_TD0 0x40007a60 +#define CYREG_PHUB_TDMEM76_ORIG_TD1 0x40007a64 +#define CYDEV_PHUB_TDMEM77_BASE 0x40007a68 +#define CYDEV_PHUB_TDMEM77_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM77_ORIG_TD0 0x40007a68 +#define CYREG_PHUB_TDMEM77_ORIG_TD1 0x40007a6c +#define CYDEV_PHUB_TDMEM78_BASE 0x40007a70 +#define CYDEV_PHUB_TDMEM78_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM78_ORIG_TD0 0x40007a70 +#define CYREG_PHUB_TDMEM78_ORIG_TD1 0x40007a74 +#define CYDEV_PHUB_TDMEM79_BASE 0x40007a78 +#define CYDEV_PHUB_TDMEM79_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM79_ORIG_TD0 0x40007a78 +#define CYREG_PHUB_TDMEM79_ORIG_TD1 0x40007a7c +#define CYDEV_PHUB_TDMEM80_BASE 0x40007a80 +#define CYDEV_PHUB_TDMEM80_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM80_ORIG_TD0 0x40007a80 +#define CYREG_PHUB_TDMEM80_ORIG_TD1 0x40007a84 +#define CYDEV_PHUB_TDMEM81_BASE 0x40007a88 +#define CYDEV_PHUB_TDMEM81_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM81_ORIG_TD0 0x40007a88 +#define CYREG_PHUB_TDMEM81_ORIG_TD1 0x40007a8c +#define CYDEV_PHUB_TDMEM82_BASE 0x40007a90 +#define CYDEV_PHUB_TDMEM82_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM82_ORIG_TD0 0x40007a90 +#define CYREG_PHUB_TDMEM82_ORIG_TD1 0x40007a94 +#define CYDEV_PHUB_TDMEM83_BASE 0x40007a98 +#define CYDEV_PHUB_TDMEM83_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM83_ORIG_TD0 0x40007a98 +#define CYREG_PHUB_TDMEM83_ORIG_TD1 0x40007a9c +#define CYDEV_PHUB_TDMEM84_BASE 0x40007aa0 +#define CYDEV_PHUB_TDMEM84_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM84_ORIG_TD0 0x40007aa0 +#define CYREG_PHUB_TDMEM84_ORIG_TD1 0x40007aa4 +#define CYDEV_PHUB_TDMEM85_BASE 0x40007aa8 +#define CYDEV_PHUB_TDMEM85_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM85_ORIG_TD0 0x40007aa8 +#define CYREG_PHUB_TDMEM85_ORIG_TD1 0x40007aac +#define CYDEV_PHUB_TDMEM86_BASE 0x40007ab0 +#define CYDEV_PHUB_TDMEM86_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM86_ORIG_TD0 0x40007ab0 +#define CYREG_PHUB_TDMEM86_ORIG_TD1 0x40007ab4 +#define CYDEV_PHUB_TDMEM87_BASE 0x40007ab8 +#define CYDEV_PHUB_TDMEM87_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM87_ORIG_TD0 0x40007ab8 +#define CYREG_PHUB_TDMEM87_ORIG_TD1 0x40007abc +#define CYDEV_PHUB_TDMEM88_BASE 0x40007ac0 +#define CYDEV_PHUB_TDMEM88_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM88_ORIG_TD0 0x40007ac0 +#define CYREG_PHUB_TDMEM88_ORIG_TD1 0x40007ac4 +#define CYDEV_PHUB_TDMEM89_BASE 0x40007ac8 +#define CYDEV_PHUB_TDMEM89_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM89_ORIG_TD0 0x40007ac8 +#define CYREG_PHUB_TDMEM89_ORIG_TD1 0x40007acc +#define CYDEV_PHUB_TDMEM90_BASE 0x40007ad0 +#define CYDEV_PHUB_TDMEM90_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM90_ORIG_TD0 0x40007ad0 +#define CYREG_PHUB_TDMEM90_ORIG_TD1 0x40007ad4 +#define CYDEV_PHUB_TDMEM91_BASE 0x40007ad8 +#define CYDEV_PHUB_TDMEM91_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM91_ORIG_TD0 0x40007ad8 +#define CYREG_PHUB_TDMEM91_ORIG_TD1 0x40007adc +#define CYDEV_PHUB_TDMEM92_BASE 0x40007ae0 +#define CYDEV_PHUB_TDMEM92_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM92_ORIG_TD0 0x40007ae0 +#define CYREG_PHUB_TDMEM92_ORIG_TD1 0x40007ae4 +#define CYDEV_PHUB_TDMEM93_BASE 0x40007ae8 +#define CYDEV_PHUB_TDMEM93_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM93_ORIG_TD0 0x40007ae8 +#define CYREG_PHUB_TDMEM93_ORIG_TD1 0x40007aec +#define CYDEV_PHUB_TDMEM94_BASE 0x40007af0 +#define CYDEV_PHUB_TDMEM94_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM94_ORIG_TD0 0x40007af0 +#define CYREG_PHUB_TDMEM94_ORIG_TD1 0x40007af4 +#define CYDEV_PHUB_TDMEM95_BASE 0x40007af8 +#define CYDEV_PHUB_TDMEM95_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM95_ORIG_TD0 0x40007af8 +#define CYREG_PHUB_TDMEM95_ORIG_TD1 0x40007afc +#define CYDEV_PHUB_TDMEM96_BASE 0x40007b00 +#define CYDEV_PHUB_TDMEM96_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM96_ORIG_TD0 0x40007b00 +#define CYREG_PHUB_TDMEM96_ORIG_TD1 0x40007b04 +#define CYDEV_PHUB_TDMEM97_BASE 0x40007b08 +#define CYDEV_PHUB_TDMEM97_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM97_ORIG_TD0 0x40007b08 +#define CYREG_PHUB_TDMEM97_ORIG_TD1 0x40007b0c +#define CYDEV_PHUB_TDMEM98_BASE 0x40007b10 +#define CYDEV_PHUB_TDMEM98_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM98_ORIG_TD0 0x40007b10 +#define CYREG_PHUB_TDMEM98_ORIG_TD1 0x40007b14 +#define CYDEV_PHUB_TDMEM99_BASE 0x40007b18 +#define CYDEV_PHUB_TDMEM99_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM99_ORIG_TD0 0x40007b18 +#define CYREG_PHUB_TDMEM99_ORIG_TD1 0x40007b1c +#define CYDEV_PHUB_TDMEM100_BASE 0x40007b20 +#define CYDEV_PHUB_TDMEM100_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM100_ORIG_TD0 0x40007b20 +#define CYREG_PHUB_TDMEM100_ORIG_TD1 0x40007b24 +#define CYDEV_PHUB_TDMEM101_BASE 0x40007b28 +#define CYDEV_PHUB_TDMEM101_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM101_ORIG_TD0 0x40007b28 +#define CYREG_PHUB_TDMEM101_ORIG_TD1 0x40007b2c +#define CYDEV_PHUB_TDMEM102_BASE 0x40007b30 +#define CYDEV_PHUB_TDMEM102_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM102_ORIG_TD0 0x40007b30 +#define CYREG_PHUB_TDMEM102_ORIG_TD1 0x40007b34 +#define CYDEV_PHUB_TDMEM103_BASE 0x40007b38 +#define CYDEV_PHUB_TDMEM103_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM103_ORIG_TD0 0x40007b38 +#define CYREG_PHUB_TDMEM103_ORIG_TD1 0x40007b3c +#define CYDEV_PHUB_TDMEM104_BASE 0x40007b40 +#define CYDEV_PHUB_TDMEM104_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM104_ORIG_TD0 0x40007b40 +#define CYREG_PHUB_TDMEM104_ORIG_TD1 0x40007b44 +#define CYDEV_PHUB_TDMEM105_BASE 0x40007b48 +#define CYDEV_PHUB_TDMEM105_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM105_ORIG_TD0 0x40007b48 +#define CYREG_PHUB_TDMEM105_ORIG_TD1 0x40007b4c +#define CYDEV_PHUB_TDMEM106_BASE 0x40007b50 +#define CYDEV_PHUB_TDMEM106_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM106_ORIG_TD0 0x40007b50 +#define CYREG_PHUB_TDMEM106_ORIG_TD1 0x40007b54 +#define CYDEV_PHUB_TDMEM107_BASE 0x40007b58 +#define CYDEV_PHUB_TDMEM107_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM107_ORIG_TD0 0x40007b58 +#define CYREG_PHUB_TDMEM107_ORIG_TD1 0x40007b5c +#define CYDEV_PHUB_TDMEM108_BASE 0x40007b60 +#define CYDEV_PHUB_TDMEM108_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM108_ORIG_TD0 0x40007b60 +#define CYREG_PHUB_TDMEM108_ORIG_TD1 0x40007b64 +#define CYDEV_PHUB_TDMEM109_BASE 0x40007b68 +#define CYDEV_PHUB_TDMEM109_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM109_ORIG_TD0 0x40007b68 +#define CYREG_PHUB_TDMEM109_ORIG_TD1 0x40007b6c +#define CYDEV_PHUB_TDMEM110_BASE 0x40007b70 +#define CYDEV_PHUB_TDMEM110_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM110_ORIG_TD0 0x40007b70 +#define CYREG_PHUB_TDMEM110_ORIG_TD1 0x40007b74 +#define CYDEV_PHUB_TDMEM111_BASE 0x40007b78 +#define CYDEV_PHUB_TDMEM111_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM111_ORIG_TD0 0x40007b78 +#define CYREG_PHUB_TDMEM111_ORIG_TD1 0x40007b7c +#define CYDEV_PHUB_TDMEM112_BASE 0x40007b80 +#define CYDEV_PHUB_TDMEM112_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM112_ORIG_TD0 0x40007b80 +#define CYREG_PHUB_TDMEM112_ORIG_TD1 0x40007b84 +#define CYDEV_PHUB_TDMEM113_BASE 0x40007b88 +#define CYDEV_PHUB_TDMEM113_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM113_ORIG_TD0 0x40007b88 +#define CYREG_PHUB_TDMEM113_ORIG_TD1 0x40007b8c +#define CYDEV_PHUB_TDMEM114_BASE 0x40007b90 +#define CYDEV_PHUB_TDMEM114_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM114_ORIG_TD0 0x40007b90 +#define CYREG_PHUB_TDMEM114_ORIG_TD1 0x40007b94 +#define CYDEV_PHUB_TDMEM115_BASE 0x40007b98 +#define CYDEV_PHUB_TDMEM115_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM115_ORIG_TD0 0x40007b98 +#define CYREG_PHUB_TDMEM115_ORIG_TD1 0x40007b9c +#define CYDEV_PHUB_TDMEM116_BASE 0x40007ba0 +#define CYDEV_PHUB_TDMEM116_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM116_ORIG_TD0 0x40007ba0 +#define CYREG_PHUB_TDMEM116_ORIG_TD1 0x40007ba4 +#define CYDEV_PHUB_TDMEM117_BASE 0x40007ba8 +#define CYDEV_PHUB_TDMEM117_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM117_ORIG_TD0 0x40007ba8 +#define CYREG_PHUB_TDMEM117_ORIG_TD1 0x40007bac +#define CYDEV_PHUB_TDMEM118_BASE 0x40007bb0 +#define CYDEV_PHUB_TDMEM118_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM118_ORIG_TD0 0x40007bb0 +#define CYREG_PHUB_TDMEM118_ORIG_TD1 0x40007bb4 +#define CYDEV_PHUB_TDMEM119_BASE 0x40007bb8 +#define CYDEV_PHUB_TDMEM119_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM119_ORIG_TD0 0x40007bb8 +#define CYREG_PHUB_TDMEM119_ORIG_TD1 0x40007bbc +#define CYDEV_PHUB_TDMEM120_BASE 0x40007bc0 +#define CYDEV_PHUB_TDMEM120_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM120_ORIG_TD0 0x40007bc0 +#define CYREG_PHUB_TDMEM120_ORIG_TD1 0x40007bc4 +#define CYDEV_PHUB_TDMEM121_BASE 0x40007bc8 +#define CYDEV_PHUB_TDMEM121_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM121_ORIG_TD0 0x40007bc8 +#define CYREG_PHUB_TDMEM121_ORIG_TD1 0x40007bcc +#define CYDEV_PHUB_TDMEM122_BASE 0x40007bd0 +#define CYDEV_PHUB_TDMEM122_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM122_ORIG_TD0 0x40007bd0 +#define CYREG_PHUB_TDMEM122_ORIG_TD1 0x40007bd4 +#define CYDEV_PHUB_TDMEM123_BASE 0x40007bd8 +#define CYDEV_PHUB_TDMEM123_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM123_ORIG_TD0 0x40007bd8 +#define CYREG_PHUB_TDMEM123_ORIG_TD1 0x40007bdc +#define CYDEV_PHUB_TDMEM124_BASE 0x40007be0 +#define CYDEV_PHUB_TDMEM124_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM124_ORIG_TD0 0x40007be0 +#define CYREG_PHUB_TDMEM124_ORIG_TD1 0x40007be4 +#define CYDEV_PHUB_TDMEM125_BASE 0x40007be8 +#define CYDEV_PHUB_TDMEM125_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM125_ORIG_TD0 0x40007be8 +#define CYREG_PHUB_TDMEM125_ORIG_TD1 0x40007bec +#define CYDEV_PHUB_TDMEM126_BASE 0x40007bf0 +#define CYDEV_PHUB_TDMEM126_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM126_ORIG_TD0 0x40007bf0 +#define CYREG_PHUB_TDMEM126_ORIG_TD1 0x40007bf4 +#define CYDEV_PHUB_TDMEM127_BASE 0x40007bf8 +#define CYDEV_PHUB_TDMEM127_SIZE 0x00000008 +#define CYREG_PHUB_TDMEM127_ORIG_TD0 0x40007bf8 +#define CYREG_PHUB_TDMEM127_ORIG_TD1 0x40007bfc +#define CYDEV_EE_BASE 0x40008000 +#define CYDEV_EE_SIZE 0x00000800 +#define CYREG_EE_DATA_MBASE 0x40008000 +#define CYREG_EE_DATA_MSIZE 0x00000800 +#define CYDEV_CAN0_BASE 0x4000a000 +#define CYDEV_CAN0_SIZE 0x000002a0 +#define CYDEV_CAN0_CSR_BASE 0x4000a000 +#define CYDEV_CAN0_CSR_SIZE 0x00000018 +#define CYREG_CAN0_CSR_INT_SR 0x4000a000 +#define CYREG_CAN0_CSR_INT_EN 0x4000a004 +#define CYREG_CAN0_CSR_BUF_SR 0x4000a008 +#define CYREG_CAN0_CSR_ERR_SR 0x4000a00c +#define CYREG_CAN0_CSR_CMD 0x4000a010 +#define CYREG_CAN0_CSR_CFG 0x4000a014 +#define CYDEV_CAN0_TX0_BASE 0x4000a020 +#define CYDEV_CAN0_TX0_SIZE 0x00000010 +#define CYREG_CAN0_TX0_CMD 0x4000a020 +#define CYREG_CAN0_TX0_ID 0x4000a024 +#define CYREG_CAN0_TX0_DH 0x4000a028 +#define CYREG_CAN0_TX0_DL 0x4000a02c +#define CYDEV_CAN0_TX1_BASE 0x4000a030 +#define CYDEV_CAN0_TX1_SIZE 0x00000010 +#define CYREG_CAN0_TX1_CMD 0x4000a030 +#define CYREG_CAN0_TX1_ID 0x4000a034 +#define CYREG_CAN0_TX1_DH 0x4000a038 +#define CYREG_CAN0_TX1_DL 0x4000a03c +#define CYDEV_CAN0_TX2_BASE 0x4000a040 +#define CYDEV_CAN0_TX2_SIZE 0x00000010 +#define CYREG_CAN0_TX2_CMD 0x4000a040 +#define CYREG_CAN0_TX2_ID 0x4000a044 +#define CYREG_CAN0_TX2_DH 0x4000a048 +#define CYREG_CAN0_TX2_DL 0x4000a04c +#define CYDEV_CAN0_TX3_BASE 0x4000a050 +#define CYDEV_CAN0_TX3_SIZE 0x00000010 +#define CYREG_CAN0_TX3_CMD 0x4000a050 +#define CYREG_CAN0_TX3_ID 0x4000a054 +#define CYREG_CAN0_TX3_DH 0x4000a058 +#define CYREG_CAN0_TX3_DL 0x4000a05c +#define CYDEV_CAN0_TX4_BASE 0x4000a060 +#define CYDEV_CAN0_TX4_SIZE 0x00000010 +#define CYREG_CAN0_TX4_CMD 0x4000a060 +#define CYREG_CAN0_TX4_ID 0x4000a064 +#define CYREG_CAN0_TX4_DH 0x4000a068 +#define CYREG_CAN0_TX4_DL 0x4000a06c +#define CYDEV_CAN0_TX5_BASE 0x4000a070 +#define CYDEV_CAN0_TX5_SIZE 0x00000010 +#define CYREG_CAN0_TX5_CMD 0x4000a070 +#define CYREG_CAN0_TX5_ID 0x4000a074 +#define CYREG_CAN0_TX5_DH 0x4000a078 +#define CYREG_CAN0_TX5_DL 0x4000a07c +#define CYDEV_CAN0_TX6_BASE 0x4000a080 +#define CYDEV_CAN0_TX6_SIZE 0x00000010 +#define CYREG_CAN0_TX6_CMD 0x4000a080 +#define CYREG_CAN0_TX6_ID 0x4000a084 +#define CYREG_CAN0_TX6_DH 0x4000a088 +#define CYREG_CAN0_TX6_DL 0x4000a08c +#define CYDEV_CAN0_TX7_BASE 0x4000a090 +#define CYDEV_CAN0_TX7_SIZE 0x00000010 +#define CYREG_CAN0_TX7_CMD 0x4000a090 +#define CYREG_CAN0_TX7_ID 0x4000a094 +#define CYREG_CAN0_TX7_DH 0x4000a098 +#define CYREG_CAN0_TX7_DL 0x4000a09c +#define CYDEV_CAN0_RX0_BASE 0x4000a0a0 +#define CYDEV_CAN0_RX0_SIZE 0x00000020 +#define CYREG_CAN0_RX0_CMD 0x4000a0a0 +#define CYREG_CAN0_RX0_ID 0x4000a0a4 +#define CYREG_CAN0_RX0_DH 0x4000a0a8 +#define CYREG_CAN0_RX0_DL 0x4000a0ac +#define CYREG_CAN0_RX0_AMR 0x4000a0b0 +#define CYREG_CAN0_RX0_ACR 0x4000a0b4 +#define CYREG_CAN0_RX0_AMRD 0x4000a0b8 +#define CYREG_CAN0_RX0_ACRD 0x4000a0bc +#define CYDEV_CAN0_RX1_BASE 0x4000a0c0 +#define CYDEV_CAN0_RX1_SIZE 0x00000020 +#define CYREG_CAN0_RX1_CMD 0x4000a0c0 +#define CYREG_CAN0_RX1_ID 0x4000a0c4 +#define CYREG_CAN0_RX1_DH 0x4000a0c8 +#define CYREG_CAN0_RX1_DL 0x4000a0cc +#define CYREG_CAN0_RX1_AMR 0x4000a0d0 +#define CYREG_CAN0_RX1_ACR 0x4000a0d4 +#define CYREG_CAN0_RX1_AMRD 0x4000a0d8 +#define CYREG_CAN0_RX1_ACRD 0x4000a0dc +#define CYDEV_CAN0_RX2_BASE 0x4000a0e0 +#define CYDEV_CAN0_RX2_SIZE 0x00000020 +#define CYREG_CAN0_RX2_CMD 0x4000a0e0 +#define CYREG_CAN0_RX2_ID 0x4000a0e4 +#define CYREG_CAN0_RX2_DH 0x4000a0e8 +#define CYREG_CAN0_RX2_DL 0x4000a0ec +#define CYREG_CAN0_RX2_AMR 0x4000a0f0 +#define CYREG_CAN0_RX2_ACR 0x4000a0f4 +#define CYREG_CAN0_RX2_AMRD 0x4000a0f8 +#define CYREG_CAN0_RX2_ACRD 0x4000a0fc +#define CYDEV_CAN0_RX3_BASE 0x4000a100 +#define CYDEV_CAN0_RX3_SIZE 0x00000020 +#define CYREG_CAN0_RX3_CMD 0x4000a100 +#define CYREG_CAN0_RX3_ID 0x4000a104 +#define CYREG_CAN0_RX3_DH 0x4000a108 +#define CYREG_CAN0_RX3_DL 0x4000a10c +#define CYREG_CAN0_RX3_AMR 0x4000a110 +#define CYREG_CAN0_RX3_ACR 0x4000a114 +#define CYREG_CAN0_RX3_AMRD 0x4000a118 +#define CYREG_CAN0_RX3_ACRD 0x4000a11c +#define CYDEV_CAN0_RX4_BASE 0x4000a120 +#define CYDEV_CAN0_RX4_SIZE 0x00000020 +#define CYREG_CAN0_RX4_CMD 0x4000a120 +#define CYREG_CAN0_RX4_ID 0x4000a124 +#define CYREG_CAN0_RX4_DH 0x4000a128 +#define CYREG_CAN0_RX4_DL 0x4000a12c +#define CYREG_CAN0_RX4_AMR 0x4000a130 +#define CYREG_CAN0_RX4_ACR 0x4000a134 +#define CYREG_CAN0_RX4_AMRD 0x4000a138 +#define CYREG_CAN0_RX4_ACRD 0x4000a13c +#define CYDEV_CAN0_RX5_BASE 0x4000a140 +#define CYDEV_CAN0_RX5_SIZE 0x00000020 +#define CYREG_CAN0_RX5_CMD 0x4000a140 +#define CYREG_CAN0_RX5_ID 0x4000a144 +#define CYREG_CAN0_RX5_DH 0x4000a148 +#define CYREG_CAN0_RX5_DL 0x4000a14c +#define CYREG_CAN0_RX5_AMR 0x4000a150 +#define CYREG_CAN0_RX5_ACR 0x4000a154 +#define CYREG_CAN0_RX5_AMRD 0x4000a158 +#define CYREG_CAN0_RX5_ACRD 0x4000a15c +#define CYDEV_CAN0_RX6_BASE 0x4000a160 +#define CYDEV_CAN0_RX6_SIZE 0x00000020 +#define CYREG_CAN0_RX6_CMD 0x4000a160 +#define CYREG_CAN0_RX6_ID 0x4000a164 +#define CYREG_CAN0_RX6_DH 0x4000a168 +#define CYREG_CAN0_RX6_DL 0x4000a16c +#define CYREG_CAN0_RX6_AMR 0x4000a170 +#define CYREG_CAN0_RX6_ACR 0x4000a174 +#define CYREG_CAN0_RX6_AMRD 0x4000a178 +#define CYREG_CAN0_RX6_ACRD 0x4000a17c +#define CYDEV_CAN0_RX7_BASE 0x4000a180 +#define CYDEV_CAN0_RX7_SIZE 0x00000020 +#define CYREG_CAN0_RX7_CMD 0x4000a180 +#define CYREG_CAN0_RX7_ID 0x4000a184 +#define CYREG_CAN0_RX7_DH 0x4000a188 +#define CYREG_CAN0_RX7_DL 0x4000a18c +#define CYREG_CAN0_RX7_AMR 0x4000a190 +#define CYREG_CAN0_RX7_ACR 0x4000a194 +#define CYREG_CAN0_RX7_AMRD 0x4000a198 +#define CYREG_CAN0_RX7_ACRD 0x4000a19c +#define CYDEV_CAN0_RX8_BASE 0x4000a1a0 +#define CYDEV_CAN0_RX8_SIZE 0x00000020 +#define CYREG_CAN0_RX8_CMD 0x4000a1a0 +#define CYREG_CAN0_RX8_ID 0x4000a1a4 +#define CYREG_CAN0_RX8_DH 0x4000a1a8 +#define CYREG_CAN0_RX8_DL 0x4000a1ac +#define CYREG_CAN0_RX8_AMR 0x4000a1b0 +#define CYREG_CAN0_RX8_ACR 0x4000a1b4 +#define CYREG_CAN0_RX8_AMRD 0x4000a1b8 +#define CYREG_CAN0_RX8_ACRD 0x4000a1bc +#define CYDEV_CAN0_RX9_BASE 0x4000a1c0 +#define CYDEV_CAN0_RX9_SIZE 0x00000020 +#define CYREG_CAN0_RX9_CMD 0x4000a1c0 +#define CYREG_CAN0_RX9_ID 0x4000a1c4 +#define CYREG_CAN0_RX9_DH 0x4000a1c8 +#define CYREG_CAN0_RX9_DL 0x4000a1cc +#define CYREG_CAN0_RX9_AMR 0x4000a1d0 +#define CYREG_CAN0_RX9_ACR 0x4000a1d4 +#define CYREG_CAN0_RX9_AMRD 0x4000a1d8 +#define CYREG_CAN0_RX9_ACRD 0x4000a1dc +#define CYDEV_CAN0_RX10_BASE 0x4000a1e0 +#define CYDEV_CAN0_RX10_SIZE 0x00000020 +#define CYREG_CAN0_RX10_CMD 0x4000a1e0 +#define CYREG_CAN0_RX10_ID 0x4000a1e4 +#define CYREG_CAN0_RX10_DH 0x4000a1e8 +#define CYREG_CAN0_RX10_DL 0x4000a1ec +#define CYREG_CAN0_RX10_AMR 0x4000a1f0 +#define CYREG_CAN0_RX10_ACR 0x4000a1f4 +#define CYREG_CAN0_RX10_AMRD 0x4000a1f8 +#define CYREG_CAN0_RX10_ACRD 0x4000a1fc +#define CYDEV_CAN0_RX11_BASE 0x4000a200 +#define CYDEV_CAN0_RX11_SIZE 0x00000020 +#define CYREG_CAN0_RX11_CMD 0x4000a200 +#define CYREG_CAN0_RX11_ID 0x4000a204 +#define CYREG_CAN0_RX11_DH 0x4000a208 +#define CYREG_CAN0_RX11_DL 0x4000a20c +#define CYREG_CAN0_RX11_AMR 0x4000a210 +#define CYREG_CAN0_RX11_ACR 0x4000a214 +#define CYREG_CAN0_RX11_AMRD 0x4000a218 +#define CYREG_CAN0_RX11_ACRD 0x4000a21c +#define CYDEV_CAN0_RX12_BASE 0x4000a220 +#define CYDEV_CAN0_RX12_SIZE 0x00000020 +#define CYREG_CAN0_RX12_CMD 0x4000a220 +#define CYREG_CAN0_RX12_ID 0x4000a224 +#define CYREG_CAN0_RX12_DH 0x4000a228 +#define CYREG_CAN0_RX12_DL 0x4000a22c +#define CYREG_CAN0_RX12_AMR 0x4000a230 +#define CYREG_CAN0_RX12_ACR 0x4000a234 +#define CYREG_CAN0_RX12_AMRD 0x4000a238 +#define CYREG_CAN0_RX12_ACRD 0x4000a23c +#define CYDEV_CAN0_RX13_BASE 0x4000a240 +#define CYDEV_CAN0_RX13_SIZE 0x00000020 +#define CYREG_CAN0_RX13_CMD 0x4000a240 +#define CYREG_CAN0_RX13_ID 0x4000a244 +#define CYREG_CAN0_RX13_DH 0x4000a248 +#define CYREG_CAN0_RX13_DL 0x4000a24c +#define CYREG_CAN0_RX13_AMR 0x4000a250 +#define CYREG_CAN0_RX13_ACR 0x4000a254 +#define CYREG_CAN0_RX13_AMRD 0x4000a258 +#define CYREG_CAN0_RX13_ACRD 0x4000a25c +#define CYDEV_CAN0_RX14_BASE 0x4000a260 +#define CYDEV_CAN0_RX14_SIZE 0x00000020 +#define CYREG_CAN0_RX14_CMD 0x4000a260 +#define CYREG_CAN0_RX14_ID 0x4000a264 +#define CYREG_CAN0_RX14_DH 0x4000a268 +#define CYREG_CAN0_RX14_DL 0x4000a26c +#define CYREG_CAN0_RX14_AMR 0x4000a270 +#define CYREG_CAN0_RX14_ACR 0x4000a274 +#define CYREG_CAN0_RX14_AMRD 0x4000a278 +#define CYREG_CAN0_RX14_ACRD 0x4000a27c +#define CYDEV_CAN0_RX15_BASE 0x4000a280 +#define CYDEV_CAN0_RX15_SIZE 0x00000020 +#define CYREG_CAN0_RX15_CMD 0x4000a280 +#define CYREG_CAN0_RX15_ID 0x4000a284 +#define CYREG_CAN0_RX15_DH 0x4000a288 +#define CYREG_CAN0_RX15_DL 0x4000a28c +#define CYREG_CAN0_RX15_AMR 0x4000a290 +#define CYREG_CAN0_RX15_ACR 0x4000a294 +#define CYREG_CAN0_RX15_AMRD 0x4000a298 +#define CYREG_CAN0_RX15_ACRD 0x4000a29c +#define CYDEV_DFB0_BASE 0x4000c000 +#define CYDEV_DFB0_SIZE 0x000007b5 +#define CYDEV_DFB0_DPA_SRAM_BASE 0x4000c000 +#define CYDEV_DFB0_DPA_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPA_SRAM_DATA_MBASE 0x4000c000 +#define CYREG_DFB0_DPA_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_DPB_SRAM_BASE 0x4000c200 +#define CYDEV_DFB0_DPB_SRAM_SIZE 0x00000200 +#define CYREG_DFB0_DPB_SRAM_DATA_MBASE 0x4000c200 +#define CYREG_DFB0_DPB_SRAM_DATA_MSIZE 0x00000200 +#define CYDEV_DFB0_CSA_SRAM_BASE 0x4000c400 +#define CYDEV_DFB0_CSA_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSA_SRAM_DATA_MBASE 0x4000c400 +#define CYREG_DFB0_CSA_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_CSB_SRAM_BASE 0x4000c500 +#define CYDEV_DFB0_CSB_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_CSB_SRAM_DATA_MBASE 0x4000c500 +#define CYREG_DFB0_CSB_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_FSM_SRAM_BASE 0x4000c600 +#define CYDEV_DFB0_FSM_SRAM_SIZE 0x00000100 +#define CYREG_DFB0_FSM_SRAM_DATA_MBASE 0x4000c600 +#define CYREG_DFB0_FSM_SRAM_DATA_MSIZE 0x00000100 +#define CYDEV_DFB0_ACU_SRAM_BASE 0x4000c700 +#define CYDEV_DFB0_ACU_SRAM_SIZE 0x00000040 +#define CYREG_DFB0_ACU_SRAM_DATA_MBASE 0x4000c700 +#define CYREG_DFB0_ACU_SRAM_DATA_MSIZE 0x00000040 +#define CYREG_DFB0_CR 0x4000c780 +#define CYREG_DFB0_SR 0x4000c784 +#define CYREG_DFB0_RAM_EN 0x4000c788 +#define CYREG_DFB0_RAM_DIR 0x4000c78c +#define CYREG_DFB0_SEMA 0x4000c790 +#define CYREG_DFB0_DSI_CTRL 0x4000c794 +#define CYREG_DFB0_INT_CTRL 0x4000c798 +#define CYREG_DFB0_DMA_CTRL 0x4000c79c +#define CYREG_DFB0_STAGEA 0x4000c7a0 +#define CYREG_DFB0_STAGEAM 0x4000c7a1 +#define CYREG_DFB0_STAGEAH 0x4000c7a2 +#define CYREG_DFB0_STAGEB 0x4000c7a4 +#define CYREG_DFB0_STAGEBM 0x4000c7a5 +#define CYREG_DFB0_STAGEBH 0x4000c7a6 +#define CYREG_DFB0_HOLDA 0x4000c7a8 +#define CYREG_DFB0_HOLDAM 0x4000c7a9 +#define CYREG_DFB0_HOLDAH 0x4000c7aa +#define CYREG_DFB0_HOLDAS 0x4000c7ab +#define CYREG_DFB0_HOLDB 0x4000c7ac +#define CYREG_DFB0_HOLDBM 0x4000c7ad +#define CYREG_DFB0_HOLDBH 0x4000c7ae +#define CYREG_DFB0_HOLDBS 0x4000c7af +#define CYREG_DFB0_COHER 0x4000c7b0 +#define CYREG_DFB0_DALIGN 0x4000c7b4 +#define CYDEV_UCFG_BASE 0x40010000 +#define CYDEV_UCFG_SIZE 0x00005040 +#define CYDEV_UCFG_B0_BASE 0x40010000 +#define CYDEV_UCFG_B0_SIZE 0x00000fef +#define CYDEV_UCFG_B0_P0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P0_U0_BASE 0x40010000 +#define CYDEV_UCFG_B0_P0_U0_SIZE 0x00000070 +#define CYREG_B0_P0_U0_PLD_IT0 0x40010000 +#define CYREG_B0_P0_U0_PLD_IT1 0x40010004 +#define CYREG_B0_P0_U0_PLD_IT2 0x40010008 +#define CYREG_B0_P0_U0_PLD_IT3 0x4001000c +#define CYREG_B0_P0_U0_PLD_IT4 0x40010010 +#define CYREG_B0_P0_U0_PLD_IT5 0x40010014 +#define CYREG_B0_P0_U0_PLD_IT6 0x40010018 +#define CYREG_B0_P0_U0_PLD_IT7 0x4001001c +#define CYREG_B0_P0_U0_PLD_IT8 0x40010020 +#define CYREG_B0_P0_U0_PLD_IT9 0x40010024 +#define CYREG_B0_P0_U0_PLD_IT10 0x40010028 +#define CYREG_B0_P0_U0_PLD_IT11 0x4001002c +#define CYREG_B0_P0_U0_PLD_ORT0 0x40010030 +#define CYREG_B0_P0_U0_PLD_ORT1 0x40010032 +#define CYREG_B0_P0_U0_PLD_ORT2 0x40010034 +#define CYREG_B0_P0_U0_PLD_ORT3 0x40010036 +#define CYREG_B0_P0_U0_MC_CFG_CEN_CONST 0x40010038 +#define CYREG_B0_P0_U0_MC_CFG_XORFB 0x4001003a +#define CYREG_B0_P0_U0_MC_CFG_SET_RESET 0x4001003c +#define CYREG_B0_P0_U0_MC_CFG_BYPASS 0x4001003e +#define CYREG_B0_P0_U0_CFG0 0x40010040 +#define CYREG_B0_P0_U0_CFG1 0x40010041 +#define CYREG_B0_P0_U0_CFG2 0x40010042 +#define CYREG_B0_P0_U0_CFG3 0x40010043 +#define CYREG_B0_P0_U0_CFG4 0x40010044 +#define CYREG_B0_P0_U0_CFG5 0x40010045 +#define CYREG_B0_P0_U0_CFG6 0x40010046 +#define CYREG_B0_P0_U0_CFG7 0x40010047 +#define CYREG_B0_P0_U0_CFG8 0x40010048 +#define CYREG_B0_P0_U0_CFG9 0x40010049 +#define CYREG_B0_P0_U0_CFG10 0x4001004a +#define CYREG_B0_P0_U0_CFG11 0x4001004b +#define CYREG_B0_P0_U0_CFG12 0x4001004c +#define CYREG_B0_P0_U0_CFG13 0x4001004d +#define CYREG_B0_P0_U0_CFG14 0x4001004e +#define CYREG_B0_P0_U0_CFG15 0x4001004f +#define CYREG_B0_P0_U0_CFG16 0x40010050 +#define CYREG_B0_P0_U0_CFG17 0x40010051 +#define CYREG_B0_P0_U0_CFG18 0x40010052 +#define CYREG_B0_P0_U0_CFG19 0x40010053 +#define CYREG_B0_P0_U0_CFG20 0x40010054 +#define CYREG_B0_P0_U0_CFG21 0x40010055 +#define CYREG_B0_P0_U0_CFG22 0x40010056 +#define CYREG_B0_P0_U0_CFG23 0x40010057 +#define CYREG_B0_P0_U0_CFG24 0x40010058 +#define CYREG_B0_P0_U0_CFG25 0x40010059 +#define CYREG_B0_P0_U0_CFG26 0x4001005a +#define CYREG_B0_P0_U0_CFG27 0x4001005b +#define CYREG_B0_P0_U0_CFG28 0x4001005c +#define CYREG_B0_P0_U0_CFG29 0x4001005d +#define CYREG_B0_P0_U0_CFG30 0x4001005e +#define CYREG_B0_P0_U0_CFG31 0x4001005f +#define CYREG_B0_P0_U0_DCFG0 0x40010060 +#define CYREG_B0_P0_U0_DCFG1 0x40010062 +#define CYREG_B0_P0_U0_DCFG2 0x40010064 +#define CYREG_B0_P0_U0_DCFG3 0x40010066 +#define CYREG_B0_P0_U0_DCFG4 0x40010068 +#define CYREG_B0_P0_U0_DCFG5 0x4001006a +#define CYREG_B0_P0_U0_DCFG6 0x4001006c +#define CYREG_B0_P0_U0_DCFG7 0x4001006e +#define CYDEV_UCFG_B0_P0_U1_BASE 0x40010080 +#define CYDEV_UCFG_B0_P0_U1_SIZE 0x00000070 +#define CYREG_B0_P0_U1_PLD_IT0 0x40010080 +#define CYREG_B0_P0_U1_PLD_IT1 0x40010084 +#define CYREG_B0_P0_U1_PLD_IT2 0x40010088 +#define CYREG_B0_P0_U1_PLD_IT3 0x4001008c +#define CYREG_B0_P0_U1_PLD_IT4 0x40010090 +#define CYREG_B0_P0_U1_PLD_IT5 0x40010094 +#define CYREG_B0_P0_U1_PLD_IT6 0x40010098 +#define CYREG_B0_P0_U1_PLD_IT7 0x4001009c +#define CYREG_B0_P0_U1_PLD_IT8 0x400100a0 +#define CYREG_B0_P0_U1_PLD_IT9 0x400100a4 +#define CYREG_B0_P0_U1_PLD_IT10 0x400100a8 +#define CYREG_B0_P0_U1_PLD_IT11 0x400100ac +#define CYREG_B0_P0_U1_PLD_ORT0 0x400100b0 +#define CYREG_B0_P0_U1_PLD_ORT1 0x400100b2 +#define CYREG_B0_P0_U1_PLD_ORT2 0x400100b4 +#define CYREG_B0_P0_U1_PLD_ORT3 0x400100b6 +#define CYREG_B0_P0_U1_MC_CFG_CEN_CONST 0x400100b8 +#define CYREG_B0_P0_U1_MC_CFG_XORFB 0x400100ba +#define CYREG_B0_P0_U1_MC_CFG_SET_RESET 0x400100bc +#define CYREG_B0_P0_U1_MC_CFG_BYPASS 0x400100be +#define CYREG_B0_P0_U1_CFG0 0x400100c0 +#define CYREG_B0_P0_U1_CFG1 0x400100c1 +#define CYREG_B0_P0_U1_CFG2 0x400100c2 +#define CYREG_B0_P0_U1_CFG3 0x400100c3 +#define CYREG_B0_P0_U1_CFG4 0x400100c4 +#define CYREG_B0_P0_U1_CFG5 0x400100c5 +#define CYREG_B0_P0_U1_CFG6 0x400100c6 +#define CYREG_B0_P0_U1_CFG7 0x400100c7 +#define CYREG_B0_P0_U1_CFG8 0x400100c8 +#define CYREG_B0_P0_U1_CFG9 0x400100c9 +#define CYREG_B0_P0_U1_CFG10 0x400100ca +#define CYREG_B0_P0_U1_CFG11 0x400100cb +#define CYREG_B0_P0_U1_CFG12 0x400100cc +#define CYREG_B0_P0_U1_CFG13 0x400100cd +#define CYREG_B0_P0_U1_CFG14 0x400100ce +#define CYREG_B0_P0_U1_CFG15 0x400100cf +#define CYREG_B0_P0_U1_CFG16 0x400100d0 +#define CYREG_B0_P0_U1_CFG17 0x400100d1 +#define CYREG_B0_P0_U1_CFG18 0x400100d2 +#define CYREG_B0_P0_U1_CFG19 0x400100d3 +#define CYREG_B0_P0_U1_CFG20 0x400100d4 +#define CYREG_B0_P0_U1_CFG21 0x400100d5 +#define CYREG_B0_P0_U1_CFG22 0x400100d6 +#define CYREG_B0_P0_U1_CFG23 0x400100d7 +#define CYREG_B0_P0_U1_CFG24 0x400100d8 +#define CYREG_B0_P0_U1_CFG25 0x400100d9 +#define CYREG_B0_P0_U1_CFG26 0x400100da +#define CYREG_B0_P0_U1_CFG27 0x400100db +#define CYREG_B0_P0_U1_CFG28 0x400100dc +#define CYREG_B0_P0_U1_CFG29 0x400100dd +#define CYREG_B0_P0_U1_CFG30 0x400100de +#define CYREG_B0_P0_U1_CFG31 0x400100df +#define CYREG_B0_P0_U1_DCFG0 0x400100e0 +#define CYREG_B0_P0_U1_DCFG1 0x400100e2 +#define CYREG_B0_P0_U1_DCFG2 0x400100e4 +#define CYREG_B0_P0_U1_DCFG3 0x400100e6 +#define CYREG_B0_P0_U1_DCFG4 0x400100e8 +#define CYREG_B0_P0_U1_DCFG5 0x400100ea +#define CYREG_B0_P0_U1_DCFG6 0x400100ec +#define CYREG_B0_P0_U1_DCFG7 0x400100ee +#define CYDEV_UCFG_B0_P0_ROUTE_BASE 0x40010100 +#define CYDEV_UCFG_B0_P0_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P1_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P1_U0_BASE 0x40010200 +#define CYDEV_UCFG_B0_P1_U0_SIZE 0x00000070 +#define CYREG_B0_P1_U0_PLD_IT0 0x40010200 +#define CYREG_B0_P1_U0_PLD_IT1 0x40010204 +#define CYREG_B0_P1_U0_PLD_IT2 0x40010208 +#define CYREG_B0_P1_U0_PLD_IT3 0x4001020c +#define CYREG_B0_P1_U0_PLD_IT4 0x40010210 +#define CYREG_B0_P1_U0_PLD_IT5 0x40010214 +#define CYREG_B0_P1_U0_PLD_IT6 0x40010218 +#define CYREG_B0_P1_U0_PLD_IT7 0x4001021c +#define CYREG_B0_P1_U0_PLD_IT8 0x40010220 +#define CYREG_B0_P1_U0_PLD_IT9 0x40010224 +#define CYREG_B0_P1_U0_PLD_IT10 0x40010228 +#define CYREG_B0_P1_U0_PLD_IT11 0x4001022c +#define CYREG_B0_P1_U0_PLD_ORT0 0x40010230 +#define CYREG_B0_P1_U0_PLD_ORT1 0x40010232 +#define CYREG_B0_P1_U0_PLD_ORT2 0x40010234 +#define CYREG_B0_P1_U0_PLD_ORT3 0x40010236 +#define CYREG_B0_P1_U0_MC_CFG_CEN_CONST 0x40010238 +#define CYREG_B0_P1_U0_MC_CFG_XORFB 0x4001023a +#define CYREG_B0_P1_U0_MC_CFG_SET_RESET 0x4001023c +#define CYREG_B0_P1_U0_MC_CFG_BYPASS 0x4001023e +#define CYREG_B0_P1_U0_CFG0 0x40010240 +#define CYREG_B0_P1_U0_CFG1 0x40010241 +#define CYREG_B0_P1_U0_CFG2 0x40010242 +#define CYREG_B0_P1_U0_CFG3 0x40010243 +#define CYREG_B0_P1_U0_CFG4 0x40010244 +#define CYREG_B0_P1_U0_CFG5 0x40010245 +#define CYREG_B0_P1_U0_CFG6 0x40010246 +#define CYREG_B0_P1_U0_CFG7 0x40010247 +#define CYREG_B0_P1_U0_CFG8 0x40010248 +#define CYREG_B0_P1_U0_CFG9 0x40010249 +#define CYREG_B0_P1_U0_CFG10 0x4001024a +#define CYREG_B0_P1_U0_CFG11 0x4001024b +#define CYREG_B0_P1_U0_CFG12 0x4001024c +#define CYREG_B0_P1_U0_CFG13 0x4001024d +#define CYREG_B0_P1_U0_CFG14 0x4001024e +#define CYREG_B0_P1_U0_CFG15 0x4001024f +#define CYREG_B0_P1_U0_CFG16 0x40010250 +#define CYREG_B0_P1_U0_CFG17 0x40010251 +#define CYREG_B0_P1_U0_CFG18 0x40010252 +#define CYREG_B0_P1_U0_CFG19 0x40010253 +#define CYREG_B0_P1_U0_CFG20 0x40010254 +#define CYREG_B0_P1_U0_CFG21 0x40010255 +#define CYREG_B0_P1_U0_CFG22 0x40010256 +#define CYREG_B0_P1_U0_CFG23 0x40010257 +#define CYREG_B0_P1_U0_CFG24 0x40010258 +#define CYREG_B0_P1_U0_CFG25 0x40010259 +#define CYREG_B0_P1_U0_CFG26 0x4001025a +#define CYREG_B0_P1_U0_CFG27 0x4001025b +#define CYREG_B0_P1_U0_CFG28 0x4001025c +#define CYREG_B0_P1_U0_CFG29 0x4001025d +#define CYREG_B0_P1_U0_CFG30 0x4001025e +#define CYREG_B0_P1_U0_CFG31 0x4001025f +#define CYREG_B0_P1_U0_DCFG0 0x40010260 +#define CYREG_B0_P1_U0_DCFG1 0x40010262 +#define CYREG_B0_P1_U0_DCFG2 0x40010264 +#define CYREG_B0_P1_U0_DCFG3 0x40010266 +#define CYREG_B0_P1_U0_DCFG4 0x40010268 +#define CYREG_B0_P1_U0_DCFG5 0x4001026a +#define CYREG_B0_P1_U0_DCFG6 0x4001026c +#define CYREG_B0_P1_U0_DCFG7 0x4001026e +#define CYDEV_UCFG_B0_P1_U1_BASE 0x40010280 +#define CYDEV_UCFG_B0_P1_U1_SIZE 0x00000070 +#define CYREG_B0_P1_U1_PLD_IT0 0x40010280 +#define CYREG_B0_P1_U1_PLD_IT1 0x40010284 +#define CYREG_B0_P1_U1_PLD_IT2 0x40010288 +#define CYREG_B0_P1_U1_PLD_IT3 0x4001028c +#define CYREG_B0_P1_U1_PLD_IT4 0x40010290 +#define CYREG_B0_P1_U1_PLD_IT5 0x40010294 +#define CYREG_B0_P1_U1_PLD_IT6 0x40010298 +#define CYREG_B0_P1_U1_PLD_IT7 0x4001029c +#define CYREG_B0_P1_U1_PLD_IT8 0x400102a0 +#define CYREG_B0_P1_U1_PLD_IT9 0x400102a4 +#define CYREG_B0_P1_U1_PLD_IT10 0x400102a8 +#define CYREG_B0_P1_U1_PLD_IT11 0x400102ac +#define CYREG_B0_P1_U1_PLD_ORT0 0x400102b0 +#define CYREG_B0_P1_U1_PLD_ORT1 0x400102b2 +#define CYREG_B0_P1_U1_PLD_ORT2 0x400102b4 +#define CYREG_B0_P1_U1_PLD_ORT3 0x400102b6 +#define CYREG_B0_P1_U1_MC_CFG_CEN_CONST 0x400102b8 +#define CYREG_B0_P1_U1_MC_CFG_XORFB 0x400102ba +#define CYREG_B0_P1_U1_MC_CFG_SET_RESET 0x400102bc +#define CYREG_B0_P1_U1_MC_CFG_BYPASS 0x400102be +#define CYREG_B0_P1_U1_CFG0 0x400102c0 +#define CYREG_B0_P1_U1_CFG1 0x400102c1 +#define CYREG_B0_P1_U1_CFG2 0x400102c2 +#define CYREG_B0_P1_U1_CFG3 0x400102c3 +#define CYREG_B0_P1_U1_CFG4 0x400102c4 +#define CYREG_B0_P1_U1_CFG5 0x400102c5 +#define CYREG_B0_P1_U1_CFG6 0x400102c6 +#define CYREG_B0_P1_U1_CFG7 0x400102c7 +#define CYREG_B0_P1_U1_CFG8 0x400102c8 +#define CYREG_B0_P1_U1_CFG9 0x400102c9 +#define CYREG_B0_P1_U1_CFG10 0x400102ca +#define CYREG_B0_P1_U1_CFG11 0x400102cb +#define CYREG_B0_P1_U1_CFG12 0x400102cc +#define CYREG_B0_P1_U1_CFG13 0x400102cd +#define CYREG_B0_P1_U1_CFG14 0x400102ce +#define CYREG_B0_P1_U1_CFG15 0x400102cf +#define CYREG_B0_P1_U1_CFG16 0x400102d0 +#define CYREG_B0_P1_U1_CFG17 0x400102d1 +#define CYREG_B0_P1_U1_CFG18 0x400102d2 +#define CYREG_B0_P1_U1_CFG19 0x400102d3 +#define CYREG_B0_P1_U1_CFG20 0x400102d4 +#define CYREG_B0_P1_U1_CFG21 0x400102d5 +#define CYREG_B0_P1_U1_CFG22 0x400102d6 +#define CYREG_B0_P1_U1_CFG23 0x400102d7 +#define CYREG_B0_P1_U1_CFG24 0x400102d8 +#define CYREG_B0_P1_U1_CFG25 0x400102d9 +#define CYREG_B0_P1_U1_CFG26 0x400102da +#define CYREG_B0_P1_U1_CFG27 0x400102db +#define CYREG_B0_P1_U1_CFG28 0x400102dc +#define CYREG_B0_P1_U1_CFG29 0x400102dd +#define CYREG_B0_P1_U1_CFG30 0x400102de +#define CYREG_B0_P1_U1_CFG31 0x400102df +#define CYREG_B0_P1_U1_DCFG0 0x400102e0 +#define CYREG_B0_P1_U1_DCFG1 0x400102e2 +#define CYREG_B0_P1_U1_DCFG2 0x400102e4 +#define CYREG_B0_P1_U1_DCFG3 0x400102e6 +#define CYREG_B0_P1_U1_DCFG4 0x400102e8 +#define CYREG_B0_P1_U1_DCFG5 0x400102ea +#define CYREG_B0_P1_U1_DCFG6 0x400102ec +#define CYREG_B0_P1_U1_DCFG7 0x400102ee +#define CYDEV_UCFG_B0_P1_ROUTE_BASE 0x40010300 +#define CYDEV_UCFG_B0_P1_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P2_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P2_U0_BASE 0x40010400 +#define CYDEV_UCFG_B0_P2_U0_SIZE 0x00000070 +#define CYREG_B0_P2_U0_PLD_IT0 0x40010400 +#define CYREG_B0_P2_U0_PLD_IT1 0x40010404 +#define CYREG_B0_P2_U0_PLD_IT2 0x40010408 +#define CYREG_B0_P2_U0_PLD_IT3 0x4001040c +#define CYREG_B0_P2_U0_PLD_IT4 0x40010410 +#define CYREG_B0_P2_U0_PLD_IT5 0x40010414 +#define CYREG_B0_P2_U0_PLD_IT6 0x40010418 +#define CYREG_B0_P2_U0_PLD_IT7 0x4001041c +#define CYREG_B0_P2_U0_PLD_IT8 0x40010420 +#define CYREG_B0_P2_U0_PLD_IT9 0x40010424 +#define CYREG_B0_P2_U0_PLD_IT10 0x40010428 +#define CYREG_B0_P2_U0_PLD_IT11 0x4001042c +#define CYREG_B0_P2_U0_PLD_ORT0 0x40010430 +#define CYREG_B0_P2_U0_PLD_ORT1 0x40010432 +#define CYREG_B0_P2_U0_PLD_ORT2 0x40010434 +#define CYREG_B0_P2_U0_PLD_ORT3 0x40010436 +#define CYREG_B0_P2_U0_MC_CFG_CEN_CONST 0x40010438 +#define CYREG_B0_P2_U0_MC_CFG_XORFB 0x4001043a +#define CYREG_B0_P2_U0_MC_CFG_SET_RESET 0x4001043c +#define CYREG_B0_P2_U0_MC_CFG_BYPASS 0x4001043e +#define CYREG_B0_P2_U0_CFG0 0x40010440 +#define CYREG_B0_P2_U0_CFG1 0x40010441 +#define CYREG_B0_P2_U0_CFG2 0x40010442 +#define CYREG_B0_P2_U0_CFG3 0x40010443 +#define CYREG_B0_P2_U0_CFG4 0x40010444 +#define CYREG_B0_P2_U0_CFG5 0x40010445 +#define CYREG_B0_P2_U0_CFG6 0x40010446 +#define CYREG_B0_P2_U0_CFG7 0x40010447 +#define CYREG_B0_P2_U0_CFG8 0x40010448 +#define CYREG_B0_P2_U0_CFG9 0x40010449 +#define CYREG_B0_P2_U0_CFG10 0x4001044a +#define CYREG_B0_P2_U0_CFG11 0x4001044b +#define CYREG_B0_P2_U0_CFG12 0x4001044c +#define CYREG_B0_P2_U0_CFG13 0x4001044d +#define CYREG_B0_P2_U0_CFG14 0x4001044e +#define CYREG_B0_P2_U0_CFG15 0x4001044f +#define CYREG_B0_P2_U0_CFG16 0x40010450 +#define CYREG_B0_P2_U0_CFG17 0x40010451 +#define CYREG_B0_P2_U0_CFG18 0x40010452 +#define CYREG_B0_P2_U0_CFG19 0x40010453 +#define CYREG_B0_P2_U0_CFG20 0x40010454 +#define CYREG_B0_P2_U0_CFG21 0x40010455 +#define CYREG_B0_P2_U0_CFG22 0x40010456 +#define CYREG_B0_P2_U0_CFG23 0x40010457 +#define CYREG_B0_P2_U0_CFG24 0x40010458 +#define CYREG_B0_P2_U0_CFG25 0x40010459 +#define CYREG_B0_P2_U0_CFG26 0x4001045a +#define CYREG_B0_P2_U0_CFG27 0x4001045b +#define CYREG_B0_P2_U0_CFG28 0x4001045c +#define CYREG_B0_P2_U0_CFG29 0x4001045d +#define CYREG_B0_P2_U0_CFG30 0x4001045e +#define CYREG_B0_P2_U0_CFG31 0x4001045f +#define CYREG_B0_P2_U0_DCFG0 0x40010460 +#define CYREG_B0_P2_U0_DCFG1 0x40010462 +#define CYREG_B0_P2_U0_DCFG2 0x40010464 +#define CYREG_B0_P2_U0_DCFG3 0x40010466 +#define CYREG_B0_P2_U0_DCFG4 0x40010468 +#define CYREG_B0_P2_U0_DCFG5 0x4001046a +#define CYREG_B0_P2_U0_DCFG6 0x4001046c +#define CYREG_B0_P2_U0_DCFG7 0x4001046e +#define CYDEV_UCFG_B0_P2_U1_BASE 0x40010480 +#define CYDEV_UCFG_B0_P2_U1_SIZE 0x00000070 +#define CYREG_B0_P2_U1_PLD_IT0 0x40010480 +#define CYREG_B0_P2_U1_PLD_IT1 0x40010484 +#define CYREG_B0_P2_U1_PLD_IT2 0x40010488 +#define CYREG_B0_P2_U1_PLD_IT3 0x4001048c +#define CYREG_B0_P2_U1_PLD_IT4 0x40010490 +#define CYREG_B0_P2_U1_PLD_IT5 0x40010494 +#define CYREG_B0_P2_U1_PLD_IT6 0x40010498 +#define CYREG_B0_P2_U1_PLD_IT7 0x4001049c +#define CYREG_B0_P2_U1_PLD_IT8 0x400104a0 +#define CYREG_B0_P2_U1_PLD_IT9 0x400104a4 +#define CYREG_B0_P2_U1_PLD_IT10 0x400104a8 +#define CYREG_B0_P2_U1_PLD_IT11 0x400104ac +#define CYREG_B0_P2_U1_PLD_ORT0 0x400104b0 +#define CYREG_B0_P2_U1_PLD_ORT1 0x400104b2 +#define CYREG_B0_P2_U1_PLD_ORT2 0x400104b4 +#define CYREG_B0_P2_U1_PLD_ORT3 0x400104b6 +#define CYREG_B0_P2_U1_MC_CFG_CEN_CONST 0x400104b8 +#define CYREG_B0_P2_U1_MC_CFG_XORFB 0x400104ba +#define CYREG_B0_P2_U1_MC_CFG_SET_RESET 0x400104bc +#define CYREG_B0_P2_U1_MC_CFG_BYPASS 0x400104be +#define CYREG_B0_P2_U1_CFG0 0x400104c0 +#define CYREG_B0_P2_U1_CFG1 0x400104c1 +#define CYREG_B0_P2_U1_CFG2 0x400104c2 +#define CYREG_B0_P2_U1_CFG3 0x400104c3 +#define CYREG_B0_P2_U1_CFG4 0x400104c4 +#define CYREG_B0_P2_U1_CFG5 0x400104c5 +#define CYREG_B0_P2_U1_CFG6 0x400104c6 +#define CYREG_B0_P2_U1_CFG7 0x400104c7 +#define CYREG_B0_P2_U1_CFG8 0x400104c8 +#define CYREG_B0_P2_U1_CFG9 0x400104c9 +#define CYREG_B0_P2_U1_CFG10 0x400104ca +#define CYREG_B0_P2_U1_CFG11 0x400104cb +#define CYREG_B0_P2_U1_CFG12 0x400104cc +#define CYREG_B0_P2_U1_CFG13 0x400104cd +#define CYREG_B0_P2_U1_CFG14 0x400104ce +#define CYREG_B0_P2_U1_CFG15 0x400104cf +#define CYREG_B0_P2_U1_CFG16 0x400104d0 +#define CYREG_B0_P2_U1_CFG17 0x400104d1 +#define CYREG_B0_P2_U1_CFG18 0x400104d2 +#define CYREG_B0_P2_U1_CFG19 0x400104d3 +#define CYREG_B0_P2_U1_CFG20 0x400104d4 +#define CYREG_B0_P2_U1_CFG21 0x400104d5 +#define CYREG_B0_P2_U1_CFG22 0x400104d6 +#define CYREG_B0_P2_U1_CFG23 0x400104d7 +#define CYREG_B0_P2_U1_CFG24 0x400104d8 +#define CYREG_B0_P2_U1_CFG25 0x400104d9 +#define CYREG_B0_P2_U1_CFG26 0x400104da +#define CYREG_B0_P2_U1_CFG27 0x400104db +#define CYREG_B0_P2_U1_CFG28 0x400104dc +#define CYREG_B0_P2_U1_CFG29 0x400104dd +#define CYREG_B0_P2_U1_CFG30 0x400104de +#define CYREG_B0_P2_U1_CFG31 0x400104df +#define CYREG_B0_P2_U1_DCFG0 0x400104e0 +#define CYREG_B0_P2_U1_DCFG1 0x400104e2 +#define CYREG_B0_P2_U1_DCFG2 0x400104e4 +#define CYREG_B0_P2_U1_DCFG3 0x400104e6 +#define CYREG_B0_P2_U1_DCFG4 0x400104e8 +#define CYREG_B0_P2_U1_DCFG5 0x400104ea +#define CYREG_B0_P2_U1_DCFG6 0x400104ec +#define CYREG_B0_P2_U1_DCFG7 0x400104ee +#define CYDEV_UCFG_B0_P2_ROUTE_BASE 0x40010500 +#define CYDEV_UCFG_B0_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P3_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P3_U0_BASE 0x40010600 +#define CYDEV_UCFG_B0_P3_U0_SIZE 0x00000070 +#define CYREG_B0_P3_U0_PLD_IT0 0x40010600 +#define CYREG_B0_P3_U0_PLD_IT1 0x40010604 +#define CYREG_B0_P3_U0_PLD_IT2 0x40010608 +#define CYREG_B0_P3_U0_PLD_IT3 0x4001060c +#define CYREG_B0_P3_U0_PLD_IT4 0x40010610 +#define CYREG_B0_P3_U0_PLD_IT5 0x40010614 +#define CYREG_B0_P3_U0_PLD_IT6 0x40010618 +#define CYREG_B0_P3_U0_PLD_IT7 0x4001061c +#define CYREG_B0_P3_U0_PLD_IT8 0x40010620 +#define CYREG_B0_P3_U0_PLD_IT9 0x40010624 +#define CYREG_B0_P3_U0_PLD_IT10 0x40010628 +#define CYREG_B0_P3_U0_PLD_IT11 0x4001062c +#define CYREG_B0_P3_U0_PLD_ORT0 0x40010630 +#define CYREG_B0_P3_U0_PLD_ORT1 0x40010632 +#define CYREG_B0_P3_U0_PLD_ORT2 0x40010634 +#define CYREG_B0_P3_U0_PLD_ORT3 0x40010636 +#define CYREG_B0_P3_U0_MC_CFG_CEN_CONST 0x40010638 +#define CYREG_B0_P3_U0_MC_CFG_XORFB 0x4001063a +#define CYREG_B0_P3_U0_MC_CFG_SET_RESET 0x4001063c +#define CYREG_B0_P3_U0_MC_CFG_BYPASS 0x4001063e +#define CYREG_B0_P3_U0_CFG0 0x40010640 +#define CYREG_B0_P3_U0_CFG1 0x40010641 +#define CYREG_B0_P3_U0_CFG2 0x40010642 +#define CYREG_B0_P3_U0_CFG3 0x40010643 +#define CYREG_B0_P3_U0_CFG4 0x40010644 +#define CYREG_B0_P3_U0_CFG5 0x40010645 +#define CYREG_B0_P3_U0_CFG6 0x40010646 +#define CYREG_B0_P3_U0_CFG7 0x40010647 +#define CYREG_B0_P3_U0_CFG8 0x40010648 +#define CYREG_B0_P3_U0_CFG9 0x40010649 +#define CYREG_B0_P3_U0_CFG10 0x4001064a +#define CYREG_B0_P3_U0_CFG11 0x4001064b +#define CYREG_B0_P3_U0_CFG12 0x4001064c +#define CYREG_B0_P3_U0_CFG13 0x4001064d +#define CYREG_B0_P3_U0_CFG14 0x4001064e +#define CYREG_B0_P3_U0_CFG15 0x4001064f +#define CYREG_B0_P3_U0_CFG16 0x40010650 +#define CYREG_B0_P3_U0_CFG17 0x40010651 +#define CYREG_B0_P3_U0_CFG18 0x40010652 +#define CYREG_B0_P3_U0_CFG19 0x40010653 +#define CYREG_B0_P3_U0_CFG20 0x40010654 +#define CYREG_B0_P3_U0_CFG21 0x40010655 +#define CYREG_B0_P3_U0_CFG22 0x40010656 +#define CYREG_B0_P3_U0_CFG23 0x40010657 +#define CYREG_B0_P3_U0_CFG24 0x40010658 +#define CYREG_B0_P3_U0_CFG25 0x40010659 +#define CYREG_B0_P3_U0_CFG26 0x4001065a +#define CYREG_B0_P3_U0_CFG27 0x4001065b +#define CYREG_B0_P3_U0_CFG28 0x4001065c +#define CYREG_B0_P3_U0_CFG29 0x4001065d +#define CYREG_B0_P3_U0_CFG30 0x4001065e +#define CYREG_B0_P3_U0_CFG31 0x4001065f +#define CYREG_B0_P3_U0_DCFG0 0x40010660 +#define CYREG_B0_P3_U0_DCFG1 0x40010662 +#define CYREG_B0_P3_U0_DCFG2 0x40010664 +#define CYREG_B0_P3_U0_DCFG3 0x40010666 +#define CYREG_B0_P3_U0_DCFG4 0x40010668 +#define CYREG_B0_P3_U0_DCFG5 0x4001066a +#define CYREG_B0_P3_U0_DCFG6 0x4001066c +#define CYREG_B0_P3_U0_DCFG7 0x4001066e +#define CYDEV_UCFG_B0_P3_U1_BASE 0x40010680 +#define CYDEV_UCFG_B0_P3_U1_SIZE 0x00000070 +#define CYREG_B0_P3_U1_PLD_IT0 0x40010680 +#define CYREG_B0_P3_U1_PLD_IT1 0x40010684 +#define CYREG_B0_P3_U1_PLD_IT2 0x40010688 +#define CYREG_B0_P3_U1_PLD_IT3 0x4001068c +#define CYREG_B0_P3_U1_PLD_IT4 0x40010690 +#define CYREG_B0_P3_U1_PLD_IT5 0x40010694 +#define CYREG_B0_P3_U1_PLD_IT6 0x40010698 +#define CYREG_B0_P3_U1_PLD_IT7 0x4001069c +#define CYREG_B0_P3_U1_PLD_IT8 0x400106a0 +#define CYREG_B0_P3_U1_PLD_IT9 0x400106a4 +#define CYREG_B0_P3_U1_PLD_IT10 0x400106a8 +#define CYREG_B0_P3_U1_PLD_IT11 0x400106ac +#define CYREG_B0_P3_U1_PLD_ORT0 0x400106b0 +#define CYREG_B0_P3_U1_PLD_ORT1 0x400106b2 +#define CYREG_B0_P3_U1_PLD_ORT2 0x400106b4 +#define CYREG_B0_P3_U1_PLD_ORT3 0x400106b6 +#define CYREG_B0_P3_U1_MC_CFG_CEN_CONST 0x400106b8 +#define CYREG_B0_P3_U1_MC_CFG_XORFB 0x400106ba +#define CYREG_B0_P3_U1_MC_CFG_SET_RESET 0x400106bc +#define CYREG_B0_P3_U1_MC_CFG_BYPASS 0x400106be +#define CYREG_B0_P3_U1_CFG0 0x400106c0 +#define CYREG_B0_P3_U1_CFG1 0x400106c1 +#define CYREG_B0_P3_U1_CFG2 0x400106c2 +#define CYREG_B0_P3_U1_CFG3 0x400106c3 +#define CYREG_B0_P3_U1_CFG4 0x400106c4 +#define CYREG_B0_P3_U1_CFG5 0x400106c5 +#define CYREG_B0_P3_U1_CFG6 0x400106c6 +#define CYREG_B0_P3_U1_CFG7 0x400106c7 +#define CYREG_B0_P3_U1_CFG8 0x400106c8 +#define CYREG_B0_P3_U1_CFG9 0x400106c9 +#define CYREG_B0_P3_U1_CFG10 0x400106ca +#define CYREG_B0_P3_U1_CFG11 0x400106cb +#define CYREG_B0_P3_U1_CFG12 0x400106cc +#define CYREG_B0_P3_U1_CFG13 0x400106cd +#define CYREG_B0_P3_U1_CFG14 0x400106ce +#define CYREG_B0_P3_U1_CFG15 0x400106cf +#define CYREG_B0_P3_U1_CFG16 0x400106d0 +#define CYREG_B0_P3_U1_CFG17 0x400106d1 +#define CYREG_B0_P3_U1_CFG18 0x400106d2 +#define CYREG_B0_P3_U1_CFG19 0x400106d3 +#define CYREG_B0_P3_U1_CFG20 0x400106d4 +#define CYREG_B0_P3_U1_CFG21 0x400106d5 +#define CYREG_B0_P3_U1_CFG22 0x400106d6 +#define CYREG_B0_P3_U1_CFG23 0x400106d7 +#define CYREG_B0_P3_U1_CFG24 0x400106d8 +#define CYREG_B0_P3_U1_CFG25 0x400106d9 +#define CYREG_B0_P3_U1_CFG26 0x400106da +#define CYREG_B0_P3_U1_CFG27 0x400106db +#define CYREG_B0_P3_U1_CFG28 0x400106dc +#define CYREG_B0_P3_U1_CFG29 0x400106dd +#define CYREG_B0_P3_U1_CFG30 0x400106de +#define CYREG_B0_P3_U1_CFG31 0x400106df +#define CYREG_B0_P3_U1_DCFG0 0x400106e0 +#define CYREG_B0_P3_U1_DCFG1 0x400106e2 +#define CYREG_B0_P3_U1_DCFG2 0x400106e4 +#define CYREG_B0_P3_U1_DCFG3 0x400106e6 +#define CYREG_B0_P3_U1_DCFG4 0x400106e8 +#define CYREG_B0_P3_U1_DCFG5 0x400106ea +#define CYREG_B0_P3_U1_DCFG6 0x400106ec +#define CYREG_B0_P3_U1_DCFG7 0x400106ee +#define CYDEV_UCFG_B0_P3_ROUTE_BASE 0x40010700 +#define CYDEV_UCFG_B0_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P4_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P4_U0_BASE 0x40010800 +#define CYDEV_UCFG_B0_P4_U0_SIZE 0x00000070 +#define CYREG_B0_P4_U0_PLD_IT0 0x40010800 +#define CYREG_B0_P4_U0_PLD_IT1 0x40010804 +#define CYREG_B0_P4_U0_PLD_IT2 0x40010808 +#define CYREG_B0_P4_U0_PLD_IT3 0x4001080c +#define CYREG_B0_P4_U0_PLD_IT4 0x40010810 +#define CYREG_B0_P4_U0_PLD_IT5 0x40010814 +#define CYREG_B0_P4_U0_PLD_IT6 0x40010818 +#define CYREG_B0_P4_U0_PLD_IT7 0x4001081c +#define CYREG_B0_P4_U0_PLD_IT8 0x40010820 +#define CYREG_B0_P4_U0_PLD_IT9 0x40010824 +#define CYREG_B0_P4_U0_PLD_IT10 0x40010828 +#define CYREG_B0_P4_U0_PLD_IT11 0x4001082c +#define CYREG_B0_P4_U0_PLD_ORT0 0x40010830 +#define CYREG_B0_P4_U0_PLD_ORT1 0x40010832 +#define CYREG_B0_P4_U0_PLD_ORT2 0x40010834 +#define CYREG_B0_P4_U0_PLD_ORT3 0x40010836 +#define CYREG_B0_P4_U0_MC_CFG_CEN_CONST 0x40010838 +#define CYREG_B0_P4_U0_MC_CFG_XORFB 0x4001083a +#define CYREG_B0_P4_U0_MC_CFG_SET_RESET 0x4001083c +#define CYREG_B0_P4_U0_MC_CFG_BYPASS 0x4001083e +#define CYREG_B0_P4_U0_CFG0 0x40010840 +#define CYREG_B0_P4_U0_CFG1 0x40010841 +#define CYREG_B0_P4_U0_CFG2 0x40010842 +#define CYREG_B0_P4_U0_CFG3 0x40010843 +#define CYREG_B0_P4_U0_CFG4 0x40010844 +#define CYREG_B0_P4_U0_CFG5 0x40010845 +#define CYREG_B0_P4_U0_CFG6 0x40010846 +#define CYREG_B0_P4_U0_CFG7 0x40010847 +#define CYREG_B0_P4_U0_CFG8 0x40010848 +#define CYREG_B0_P4_U0_CFG9 0x40010849 +#define CYREG_B0_P4_U0_CFG10 0x4001084a +#define CYREG_B0_P4_U0_CFG11 0x4001084b +#define CYREG_B0_P4_U0_CFG12 0x4001084c +#define CYREG_B0_P4_U0_CFG13 0x4001084d +#define CYREG_B0_P4_U0_CFG14 0x4001084e +#define CYREG_B0_P4_U0_CFG15 0x4001084f +#define CYREG_B0_P4_U0_CFG16 0x40010850 +#define CYREG_B0_P4_U0_CFG17 0x40010851 +#define CYREG_B0_P4_U0_CFG18 0x40010852 +#define CYREG_B0_P4_U0_CFG19 0x40010853 +#define CYREG_B0_P4_U0_CFG20 0x40010854 +#define CYREG_B0_P4_U0_CFG21 0x40010855 +#define CYREG_B0_P4_U0_CFG22 0x40010856 +#define CYREG_B0_P4_U0_CFG23 0x40010857 +#define CYREG_B0_P4_U0_CFG24 0x40010858 +#define CYREG_B0_P4_U0_CFG25 0x40010859 +#define CYREG_B0_P4_U0_CFG26 0x4001085a +#define CYREG_B0_P4_U0_CFG27 0x4001085b +#define CYREG_B0_P4_U0_CFG28 0x4001085c +#define CYREG_B0_P4_U0_CFG29 0x4001085d +#define CYREG_B0_P4_U0_CFG30 0x4001085e +#define CYREG_B0_P4_U0_CFG31 0x4001085f +#define CYREG_B0_P4_U0_DCFG0 0x40010860 +#define CYREG_B0_P4_U0_DCFG1 0x40010862 +#define CYREG_B0_P4_U0_DCFG2 0x40010864 +#define CYREG_B0_P4_U0_DCFG3 0x40010866 +#define CYREG_B0_P4_U0_DCFG4 0x40010868 +#define CYREG_B0_P4_U0_DCFG5 0x4001086a +#define CYREG_B0_P4_U0_DCFG6 0x4001086c +#define CYREG_B0_P4_U0_DCFG7 0x4001086e +#define CYDEV_UCFG_B0_P4_U1_BASE 0x40010880 +#define CYDEV_UCFG_B0_P4_U1_SIZE 0x00000070 +#define CYREG_B0_P4_U1_PLD_IT0 0x40010880 +#define CYREG_B0_P4_U1_PLD_IT1 0x40010884 +#define CYREG_B0_P4_U1_PLD_IT2 0x40010888 +#define CYREG_B0_P4_U1_PLD_IT3 0x4001088c +#define CYREG_B0_P4_U1_PLD_IT4 0x40010890 +#define CYREG_B0_P4_U1_PLD_IT5 0x40010894 +#define CYREG_B0_P4_U1_PLD_IT6 0x40010898 +#define CYREG_B0_P4_U1_PLD_IT7 0x4001089c +#define CYREG_B0_P4_U1_PLD_IT8 0x400108a0 +#define CYREG_B0_P4_U1_PLD_IT9 0x400108a4 +#define CYREG_B0_P4_U1_PLD_IT10 0x400108a8 +#define CYREG_B0_P4_U1_PLD_IT11 0x400108ac +#define CYREG_B0_P4_U1_PLD_ORT0 0x400108b0 +#define CYREG_B0_P4_U1_PLD_ORT1 0x400108b2 +#define CYREG_B0_P4_U1_PLD_ORT2 0x400108b4 +#define CYREG_B0_P4_U1_PLD_ORT3 0x400108b6 +#define CYREG_B0_P4_U1_MC_CFG_CEN_CONST 0x400108b8 +#define CYREG_B0_P4_U1_MC_CFG_XORFB 0x400108ba +#define CYREG_B0_P4_U1_MC_CFG_SET_RESET 0x400108bc +#define CYREG_B0_P4_U1_MC_CFG_BYPASS 0x400108be +#define CYREG_B0_P4_U1_CFG0 0x400108c0 +#define CYREG_B0_P4_U1_CFG1 0x400108c1 +#define CYREG_B0_P4_U1_CFG2 0x400108c2 +#define CYREG_B0_P4_U1_CFG3 0x400108c3 +#define CYREG_B0_P4_U1_CFG4 0x400108c4 +#define CYREG_B0_P4_U1_CFG5 0x400108c5 +#define CYREG_B0_P4_U1_CFG6 0x400108c6 +#define CYREG_B0_P4_U1_CFG7 0x400108c7 +#define CYREG_B0_P4_U1_CFG8 0x400108c8 +#define CYREG_B0_P4_U1_CFG9 0x400108c9 +#define CYREG_B0_P4_U1_CFG10 0x400108ca +#define CYREG_B0_P4_U1_CFG11 0x400108cb +#define CYREG_B0_P4_U1_CFG12 0x400108cc +#define CYREG_B0_P4_U1_CFG13 0x400108cd +#define CYREG_B0_P4_U1_CFG14 0x400108ce +#define CYREG_B0_P4_U1_CFG15 0x400108cf +#define CYREG_B0_P4_U1_CFG16 0x400108d0 +#define CYREG_B0_P4_U1_CFG17 0x400108d1 +#define CYREG_B0_P4_U1_CFG18 0x400108d2 +#define CYREG_B0_P4_U1_CFG19 0x400108d3 +#define CYREG_B0_P4_U1_CFG20 0x400108d4 +#define CYREG_B0_P4_U1_CFG21 0x400108d5 +#define CYREG_B0_P4_U1_CFG22 0x400108d6 +#define CYREG_B0_P4_U1_CFG23 0x400108d7 +#define CYREG_B0_P4_U1_CFG24 0x400108d8 +#define CYREG_B0_P4_U1_CFG25 0x400108d9 +#define CYREG_B0_P4_U1_CFG26 0x400108da +#define CYREG_B0_P4_U1_CFG27 0x400108db +#define CYREG_B0_P4_U1_CFG28 0x400108dc +#define CYREG_B0_P4_U1_CFG29 0x400108dd +#define CYREG_B0_P4_U1_CFG30 0x400108de +#define CYREG_B0_P4_U1_CFG31 0x400108df +#define CYREG_B0_P4_U1_DCFG0 0x400108e0 +#define CYREG_B0_P4_U1_DCFG1 0x400108e2 +#define CYREG_B0_P4_U1_DCFG2 0x400108e4 +#define CYREG_B0_P4_U1_DCFG3 0x400108e6 +#define CYREG_B0_P4_U1_DCFG4 0x400108e8 +#define CYREG_B0_P4_U1_DCFG5 0x400108ea +#define CYREG_B0_P4_U1_DCFG6 0x400108ec +#define CYREG_B0_P4_U1_DCFG7 0x400108ee +#define CYDEV_UCFG_B0_P4_ROUTE_BASE 0x40010900 +#define CYDEV_UCFG_B0_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P5_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P5_U0_BASE 0x40010a00 +#define CYDEV_UCFG_B0_P5_U0_SIZE 0x00000070 +#define CYREG_B0_P5_U0_PLD_IT0 0x40010a00 +#define CYREG_B0_P5_U0_PLD_IT1 0x40010a04 +#define CYREG_B0_P5_U0_PLD_IT2 0x40010a08 +#define CYREG_B0_P5_U0_PLD_IT3 0x40010a0c +#define CYREG_B0_P5_U0_PLD_IT4 0x40010a10 +#define CYREG_B0_P5_U0_PLD_IT5 0x40010a14 +#define CYREG_B0_P5_U0_PLD_IT6 0x40010a18 +#define CYREG_B0_P5_U0_PLD_IT7 0x40010a1c +#define CYREG_B0_P5_U0_PLD_IT8 0x40010a20 +#define CYREG_B0_P5_U0_PLD_IT9 0x40010a24 +#define CYREG_B0_P5_U0_PLD_IT10 0x40010a28 +#define CYREG_B0_P5_U0_PLD_IT11 0x40010a2c +#define CYREG_B0_P5_U0_PLD_ORT0 0x40010a30 +#define CYREG_B0_P5_U0_PLD_ORT1 0x40010a32 +#define CYREG_B0_P5_U0_PLD_ORT2 0x40010a34 +#define CYREG_B0_P5_U0_PLD_ORT3 0x40010a36 +#define CYREG_B0_P5_U0_MC_CFG_CEN_CONST 0x40010a38 +#define CYREG_B0_P5_U0_MC_CFG_XORFB 0x40010a3a +#define CYREG_B0_P5_U0_MC_CFG_SET_RESET 0x40010a3c +#define CYREG_B0_P5_U0_MC_CFG_BYPASS 0x40010a3e +#define CYREG_B0_P5_U0_CFG0 0x40010a40 +#define CYREG_B0_P5_U0_CFG1 0x40010a41 +#define CYREG_B0_P5_U0_CFG2 0x40010a42 +#define CYREG_B0_P5_U0_CFG3 0x40010a43 +#define CYREG_B0_P5_U0_CFG4 0x40010a44 +#define CYREG_B0_P5_U0_CFG5 0x40010a45 +#define CYREG_B0_P5_U0_CFG6 0x40010a46 +#define CYREG_B0_P5_U0_CFG7 0x40010a47 +#define CYREG_B0_P5_U0_CFG8 0x40010a48 +#define CYREG_B0_P5_U0_CFG9 0x40010a49 +#define CYREG_B0_P5_U0_CFG10 0x40010a4a +#define CYREG_B0_P5_U0_CFG11 0x40010a4b +#define CYREG_B0_P5_U0_CFG12 0x40010a4c +#define CYREG_B0_P5_U0_CFG13 0x40010a4d +#define CYREG_B0_P5_U0_CFG14 0x40010a4e +#define CYREG_B0_P5_U0_CFG15 0x40010a4f +#define CYREG_B0_P5_U0_CFG16 0x40010a50 +#define CYREG_B0_P5_U0_CFG17 0x40010a51 +#define CYREG_B0_P5_U0_CFG18 0x40010a52 +#define CYREG_B0_P5_U0_CFG19 0x40010a53 +#define CYREG_B0_P5_U0_CFG20 0x40010a54 +#define CYREG_B0_P5_U0_CFG21 0x40010a55 +#define CYREG_B0_P5_U0_CFG22 0x40010a56 +#define CYREG_B0_P5_U0_CFG23 0x40010a57 +#define CYREG_B0_P5_U0_CFG24 0x40010a58 +#define CYREG_B0_P5_U0_CFG25 0x40010a59 +#define CYREG_B0_P5_U0_CFG26 0x40010a5a +#define CYREG_B0_P5_U0_CFG27 0x40010a5b +#define CYREG_B0_P5_U0_CFG28 0x40010a5c +#define CYREG_B0_P5_U0_CFG29 0x40010a5d +#define CYREG_B0_P5_U0_CFG30 0x40010a5e +#define CYREG_B0_P5_U0_CFG31 0x40010a5f +#define CYREG_B0_P5_U0_DCFG0 0x40010a60 +#define CYREG_B0_P5_U0_DCFG1 0x40010a62 +#define CYREG_B0_P5_U0_DCFG2 0x40010a64 +#define CYREG_B0_P5_U0_DCFG3 0x40010a66 +#define CYREG_B0_P5_U0_DCFG4 0x40010a68 +#define CYREG_B0_P5_U0_DCFG5 0x40010a6a +#define CYREG_B0_P5_U0_DCFG6 0x40010a6c +#define CYREG_B0_P5_U0_DCFG7 0x40010a6e +#define CYDEV_UCFG_B0_P5_U1_BASE 0x40010a80 +#define CYDEV_UCFG_B0_P5_U1_SIZE 0x00000070 +#define CYREG_B0_P5_U1_PLD_IT0 0x40010a80 +#define CYREG_B0_P5_U1_PLD_IT1 0x40010a84 +#define CYREG_B0_P5_U1_PLD_IT2 0x40010a88 +#define CYREG_B0_P5_U1_PLD_IT3 0x40010a8c +#define CYREG_B0_P5_U1_PLD_IT4 0x40010a90 +#define CYREG_B0_P5_U1_PLD_IT5 0x40010a94 +#define CYREG_B0_P5_U1_PLD_IT6 0x40010a98 +#define CYREG_B0_P5_U1_PLD_IT7 0x40010a9c +#define CYREG_B0_P5_U1_PLD_IT8 0x40010aa0 +#define CYREG_B0_P5_U1_PLD_IT9 0x40010aa4 +#define CYREG_B0_P5_U1_PLD_IT10 0x40010aa8 +#define CYREG_B0_P5_U1_PLD_IT11 0x40010aac +#define CYREG_B0_P5_U1_PLD_ORT0 0x40010ab0 +#define CYREG_B0_P5_U1_PLD_ORT1 0x40010ab2 +#define CYREG_B0_P5_U1_PLD_ORT2 0x40010ab4 +#define CYREG_B0_P5_U1_PLD_ORT3 0x40010ab6 +#define CYREG_B0_P5_U1_MC_CFG_CEN_CONST 0x40010ab8 +#define CYREG_B0_P5_U1_MC_CFG_XORFB 0x40010aba +#define CYREG_B0_P5_U1_MC_CFG_SET_RESET 0x40010abc +#define CYREG_B0_P5_U1_MC_CFG_BYPASS 0x40010abe +#define CYREG_B0_P5_U1_CFG0 0x40010ac0 +#define CYREG_B0_P5_U1_CFG1 0x40010ac1 +#define CYREG_B0_P5_U1_CFG2 0x40010ac2 +#define CYREG_B0_P5_U1_CFG3 0x40010ac3 +#define CYREG_B0_P5_U1_CFG4 0x40010ac4 +#define CYREG_B0_P5_U1_CFG5 0x40010ac5 +#define CYREG_B0_P5_U1_CFG6 0x40010ac6 +#define CYREG_B0_P5_U1_CFG7 0x40010ac7 +#define CYREG_B0_P5_U1_CFG8 0x40010ac8 +#define CYREG_B0_P5_U1_CFG9 0x40010ac9 +#define CYREG_B0_P5_U1_CFG10 0x40010aca +#define CYREG_B0_P5_U1_CFG11 0x40010acb +#define CYREG_B0_P5_U1_CFG12 0x40010acc +#define CYREG_B0_P5_U1_CFG13 0x40010acd +#define CYREG_B0_P5_U1_CFG14 0x40010ace +#define CYREG_B0_P5_U1_CFG15 0x40010acf +#define CYREG_B0_P5_U1_CFG16 0x40010ad0 +#define CYREG_B0_P5_U1_CFG17 0x40010ad1 +#define CYREG_B0_P5_U1_CFG18 0x40010ad2 +#define CYREG_B0_P5_U1_CFG19 0x40010ad3 +#define CYREG_B0_P5_U1_CFG20 0x40010ad4 +#define CYREG_B0_P5_U1_CFG21 0x40010ad5 +#define CYREG_B0_P5_U1_CFG22 0x40010ad6 +#define CYREG_B0_P5_U1_CFG23 0x40010ad7 +#define CYREG_B0_P5_U1_CFG24 0x40010ad8 +#define CYREG_B0_P5_U1_CFG25 0x40010ad9 +#define CYREG_B0_P5_U1_CFG26 0x40010ada +#define CYREG_B0_P5_U1_CFG27 0x40010adb +#define CYREG_B0_P5_U1_CFG28 0x40010adc +#define CYREG_B0_P5_U1_CFG29 0x40010add +#define CYREG_B0_P5_U1_CFG30 0x40010ade +#define CYREG_B0_P5_U1_CFG31 0x40010adf +#define CYREG_B0_P5_U1_DCFG0 0x40010ae0 +#define CYREG_B0_P5_U1_DCFG1 0x40010ae2 +#define CYREG_B0_P5_U1_DCFG2 0x40010ae4 +#define CYREG_B0_P5_U1_DCFG3 0x40010ae6 +#define CYREG_B0_P5_U1_DCFG4 0x40010ae8 +#define CYREG_B0_P5_U1_DCFG5 0x40010aea +#define CYREG_B0_P5_U1_DCFG6 0x40010aec +#define CYREG_B0_P5_U1_DCFG7 0x40010aee +#define CYDEV_UCFG_B0_P5_ROUTE_BASE 0x40010b00 +#define CYDEV_UCFG_B0_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P6_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P6_U0_BASE 0x40010c00 +#define CYDEV_UCFG_B0_P6_U0_SIZE 0x00000070 +#define CYREG_B0_P6_U0_PLD_IT0 0x40010c00 +#define CYREG_B0_P6_U0_PLD_IT1 0x40010c04 +#define CYREG_B0_P6_U0_PLD_IT2 0x40010c08 +#define CYREG_B0_P6_U0_PLD_IT3 0x40010c0c +#define CYREG_B0_P6_U0_PLD_IT4 0x40010c10 +#define CYREG_B0_P6_U0_PLD_IT5 0x40010c14 +#define CYREG_B0_P6_U0_PLD_IT6 0x40010c18 +#define CYREG_B0_P6_U0_PLD_IT7 0x40010c1c +#define CYREG_B0_P6_U0_PLD_IT8 0x40010c20 +#define CYREG_B0_P6_U0_PLD_IT9 0x40010c24 +#define CYREG_B0_P6_U0_PLD_IT10 0x40010c28 +#define CYREG_B0_P6_U0_PLD_IT11 0x40010c2c +#define CYREG_B0_P6_U0_PLD_ORT0 0x40010c30 +#define CYREG_B0_P6_U0_PLD_ORT1 0x40010c32 +#define CYREG_B0_P6_U0_PLD_ORT2 0x40010c34 +#define CYREG_B0_P6_U0_PLD_ORT3 0x40010c36 +#define CYREG_B0_P6_U0_MC_CFG_CEN_CONST 0x40010c38 +#define CYREG_B0_P6_U0_MC_CFG_XORFB 0x40010c3a +#define CYREG_B0_P6_U0_MC_CFG_SET_RESET 0x40010c3c +#define CYREG_B0_P6_U0_MC_CFG_BYPASS 0x40010c3e +#define CYREG_B0_P6_U0_CFG0 0x40010c40 +#define CYREG_B0_P6_U0_CFG1 0x40010c41 +#define CYREG_B0_P6_U0_CFG2 0x40010c42 +#define CYREG_B0_P6_U0_CFG3 0x40010c43 +#define CYREG_B0_P6_U0_CFG4 0x40010c44 +#define CYREG_B0_P6_U0_CFG5 0x40010c45 +#define CYREG_B0_P6_U0_CFG6 0x40010c46 +#define CYREG_B0_P6_U0_CFG7 0x40010c47 +#define CYREG_B0_P6_U0_CFG8 0x40010c48 +#define CYREG_B0_P6_U0_CFG9 0x40010c49 +#define CYREG_B0_P6_U0_CFG10 0x40010c4a +#define CYREG_B0_P6_U0_CFG11 0x40010c4b +#define CYREG_B0_P6_U0_CFG12 0x40010c4c +#define CYREG_B0_P6_U0_CFG13 0x40010c4d +#define CYREG_B0_P6_U0_CFG14 0x40010c4e +#define CYREG_B0_P6_U0_CFG15 0x40010c4f +#define CYREG_B0_P6_U0_CFG16 0x40010c50 +#define CYREG_B0_P6_U0_CFG17 0x40010c51 +#define CYREG_B0_P6_U0_CFG18 0x40010c52 +#define CYREG_B0_P6_U0_CFG19 0x40010c53 +#define CYREG_B0_P6_U0_CFG20 0x40010c54 +#define CYREG_B0_P6_U0_CFG21 0x40010c55 +#define CYREG_B0_P6_U0_CFG22 0x40010c56 +#define CYREG_B0_P6_U0_CFG23 0x40010c57 +#define CYREG_B0_P6_U0_CFG24 0x40010c58 +#define CYREG_B0_P6_U0_CFG25 0x40010c59 +#define CYREG_B0_P6_U0_CFG26 0x40010c5a +#define CYREG_B0_P6_U0_CFG27 0x40010c5b +#define CYREG_B0_P6_U0_CFG28 0x40010c5c +#define CYREG_B0_P6_U0_CFG29 0x40010c5d +#define CYREG_B0_P6_U0_CFG30 0x40010c5e +#define CYREG_B0_P6_U0_CFG31 0x40010c5f +#define CYREG_B0_P6_U0_DCFG0 0x40010c60 +#define CYREG_B0_P6_U0_DCFG1 0x40010c62 +#define CYREG_B0_P6_U0_DCFG2 0x40010c64 +#define CYREG_B0_P6_U0_DCFG3 0x40010c66 +#define CYREG_B0_P6_U0_DCFG4 0x40010c68 +#define CYREG_B0_P6_U0_DCFG5 0x40010c6a +#define CYREG_B0_P6_U0_DCFG6 0x40010c6c +#define CYREG_B0_P6_U0_DCFG7 0x40010c6e +#define CYDEV_UCFG_B0_P6_U1_BASE 0x40010c80 +#define CYDEV_UCFG_B0_P6_U1_SIZE 0x00000070 +#define CYREG_B0_P6_U1_PLD_IT0 0x40010c80 +#define CYREG_B0_P6_U1_PLD_IT1 0x40010c84 +#define CYREG_B0_P6_U1_PLD_IT2 0x40010c88 +#define CYREG_B0_P6_U1_PLD_IT3 0x40010c8c +#define CYREG_B0_P6_U1_PLD_IT4 0x40010c90 +#define CYREG_B0_P6_U1_PLD_IT5 0x40010c94 +#define CYREG_B0_P6_U1_PLD_IT6 0x40010c98 +#define CYREG_B0_P6_U1_PLD_IT7 0x40010c9c +#define CYREG_B0_P6_U1_PLD_IT8 0x40010ca0 +#define CYREG_B0_P6_U1_PLD_IT9 0x40010ca4 +#define CYREG_B0_P6_U1_PLD_IT10 0x40010ca8 +#define CYREG_B0_P6_U1_PLD_IT11 0x40010cac +#define CYREG_B0_P6_U1_PLD_ORT0 0x40010cb0 +#define CYREG_B0_P6_U1_PLD_ORT1 0x40010cb2 +#define CYREG_B0_P6_U1_PLD_ORT2 0x40010cb4 +#define CYREG_B0_P6_U1_PLD_ORT3 0x40010cb6 +#define CYREG_B0_P6_U1_MC_CFG_CEN_CONST 0x40010cb8 +#define CYREG_B0_P6_U1_MC_CFG_XORFB 0x40010cba +#define CYREG_B0_P6_U1_MC_CFG_SET_RESET 0x40010cbc +#define CYREG_B0_P6_U1_MC_CFG_BYPASS 0x40010cbe +#define CYREG_B0_P6_U1_CFG0 0x40010cc0 +#define CYREG_B0_P6_U1_CFG1 0x40010cc1 +#define CYREG_B0_P6_U1_CFG2 0x40010cc2 +#define CYREG_B0_P6_U1_CFG3 0x40010cc3 +#define CYREG_B0_P6_U1_CFG4 0x40010cc4 +#define CYREG_B0_P6_U1_CFG5 0x40010cc5 +#define CYREG_B0_P6_U1_CFG6 0x40010cc6 +#define CYREG_B0_P6_U1_CFG7 0x40010cc7 +#define CYREG_B0_P6_U1_CFG8 0x40010cc8 +#define CYREG_B0_P6_U1_CFG9 0x40010cc9 +#define CYREG_B0_P6_U1_CFG10 0x40010cca +#define CYREG_B0_P6_U1_CFG11 0x40010ccb +#define CYREG_B0_P6_U1_CFG12 0x40010ccc +#define CYREG_B0_P6_U1_CFG13 0x40010ccd +#define CYREG_B0_P6_U1_CFG14 0x40010cce +#define CYREG_B0_P6_U1_CFG15 0x40010ccf +#define CYREG_B0_P6_U1_CFG16 0x40010cd0 +#define CYREG_B0_P6_U1_CFG17 0x40010cd1 +#define CYREG_B0_P6_U1_CFG18 0x40010cd2 +#define CYREG_B0_P6_U1_CFG19 0x40010cd3 +#define CYREG_B0_P6_U1_CFG20 0x40010cd4 +#define CYREG_B0_P6_U1_CFG21 0x40010cd5 +#define CYREG_B0_P6_U1_CFG22 0x40010cd6 +#define CYREG_B0_P6_U1_CFG23 0x40010cd7 +#define CYREG_B0_P6_U1_CFG24 0x40010cd8 +#define CYREG_B0_P6_U1_CFG25 0x40010cd9 +#define CYREG_B0_P6_U1_CFG26 0x40010cda +#define CYREG_B0_P6_U1_CFG27 0x40010cdb +#define CYREG_B0_P6_U1_CFG28 0x40010cdc +#define CYREG_B0_P6_U1_CFG29 0x40010cdd +#define CYREG_B0_P6_U1_CFG30 0x40010cde +#define CYREG_B0_P6_U1_CFG31 0x40010cdf +#define CYREG_B0_P6_U1_DCFG0 0x40010ce0 +#define CYREG_B0_P6_U1_DCFG1 0x40010ce2 +#define CYREG_B0_P6_U1_DCFG2 0x40010ce4 +#define CYREG_B0_P6_U1_DCFG3 0x40010ce6 +#define CYREG_B0_P6_U1_DCFG4 0x40010ce8 +#define CYREG_B0_P6_U1_DCFG5 0x40010cea +#define CYREG_B0_P6_U1_DCFG6 0x40010cec +#define CYREG_B0_P6_U1_DCFG7 0x40010cee +#define CYDEV_UCFG_B0_P6_ROUTE_BASE 0x40010d00 +#define CYDEV_UCFG_B0_P6_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B0_P7_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_SIZE 0x000001ef +#define CYDEV_UCFG_B0_P7_U0_BASE 0x40010e00 +#define CYDEV_UCFG_B0_P7_U0_SIZE 0x00000070 +#define CYREG_B0_P7_U0_PLD_IT0 0x40010e00 +#define CYREG_B0_P7_U0_PLD_IT1 0x40010e04 +#define CYREG_B0_P7_U0_PLD_IT2 0x40010e08 +#define CYREG_B0_P7_U0_PLD_IT3 0x40010e0c +#define CYREG_B0_P7_U0_PLD_IT4 0x40010e10 +#define CYREG_B0_P7_U0_PLD_IT5 0x40010e14 +#define CYREG_B0_P7_U0_PLD_IT6 0x40010e18 +#define CYREG_B0_P7_U0_PLD_IT7 0x40010e1c +#define CYREG_B0_P7_U0_PLD_IT8 0x40010e20 +#define CYREG_B0_P7_U0_PLD_IT9 0x40010e24 +#define CYREG_B0_P7_U0_PLD_IT10 0x40010e28 +#define CYREG_B0_P7_U0_PLD_IT11 0x40010e2c +#define CYREG_B0_P7_U0_PLD_ORT0 0x40010e30 +#define CYREG_B0_P7_U0_PLD_ORT1 0x40010e32 +#define CYREG_B0_P7_U0_PLD_ORT2 0x40010e34 +#define CYREG_B0_P7_U0_PLD_ORT3 0x40010e36 +#define CYREG_B0_P7_U0_MC_CFG_CEN_CONST 0x40010e38 +#define CYREG_B0_P7_U0_MC_CFG_XORFB 0x40010e3a +#define CYREG_B0_P7_U0_MC_CFG_SET_RESET 0x40010e3c +#define CYREG_B0_P7_U0_MC_CFG_BYPASS 0x40010e3e +#define CYREG_B0_P7_U0_CFG0 0x40010e40 +#define CYREG_B0_P7_U0_CFG1 0x40010e41 +#define CYREG_B0_P7_U0_CFG2 0x40010e42 +#define CYREG_B0_P7_U0_CFG3 0x40010e43 +#define CYREG_B0_P7_U0_CFG4 0x40010e44 +#define CYREG_B0_P7_U0_CFG5 0x40010e45 +#define CYREG_B0_P7_U0_CFG6 0x40010e46 +#define CYREG_B0_P7_U0_CFG7 0x40010e47 +#define CYREG_B0_P7_U0_CFG8 0x40010e48 +#define CYREG_B0_P7_U0_CFG9 0x40010e49 +#define CYREG_B0_P7_U0_CFG10 0x40010e4a +#define CYREG_B0_P7_U0_CFG11 0x40010e4b +#define CYREG_B0_P7_U0_CFG12 0x40010e4c +#define CYREG_B0_P7_U0_CFG13 0x40010e4d +#define CYREG_B0_P7_U0_CFG14 0x40010e4e +#define CYREG_B0_P7_U0_CFG15 0x40010e4f +#define CYREG_B0_P7_U0_CFG16 0x40010e50 +#define CYREG_B0_P7_U0_CFG17 0x40010e51 +#define CYREG_B0_P7_U0_CFG18 0x40010e52 +#define CYREG_B0_P7_U0_CFG19 0x40010e53 +#define CYREG_B0_P7_U0_CFG20 0x40010e54 +#define CYREG_B0_P7_U0_CFG21 0x40010e55 +#define CYREG_B0_P7_U0_CFG22 0x40010e56 +#define CYREG_B0_P7_U0_CFG23 0x40010e57 +#define CYREG_B0_P7_U0_CFG24 0x40010e58 +#define CYREG_B0_P7_U0_CFG25 0x40010e59 +#define CYREG_B0_P7_U0_CFG26 0x40010e5a +#define CYREG_B0_P7_U0_CFG27 0x40010e5b +#define CYREG_B0_P7_U0_CFG28 0x40010e5c +#define CYREG_B0_P7_U0_CFG29 0x40010e5d +#define CYREG_B0_P7_U0_CFG30 0x40010e5e +#define CYREG_B0_P7_U0_CFG31 0x40010e5f +#define CYREG_B0_P7_U0_DCFG0 0x40010e60 +#define CYREG_B0_P7_U0_DCFG1 0x40010e62 +#define CYREG_B0_P7_U0_DCFG2 0x40010e64 +#define CYREG_B0_P7_U0_DCFG3 0x40010e66 +#define CYREG_B0_P7_U0_DCFG4 0x40010e68 +#define CYREG_B0_P7_U0_DCFG5 0x40010e6a +#define CYREG_B0_P7_U0_DCFG6 0x40010e6c +#define CYREG_B0_P7_U0_DCFG7 0x40010e6e +#define CYDEV_UCFG_B0_P7_U1_BASE 0x40010e80 +#define CYDEV_UCFG_B0_P7_U1_SIZE 0x00000070 +#define CYREG_B0_P7_U1_PLD_IT0 0x40010e80 +#define CYREG_B0_P7_U1_PLD_IT1 0x40010e84 +#define CYREG_B0_P7_U1_PLD_IT2 0x40010e88 +#define CYREG_B0_P7_U1_PLD_IT3 0x40010e8c +#define CYREG_B0_P7_U1_PLD_IT4 0x40010e90 +#define CYREG_B0_P7_U1_PLD_IT5 0x40010e94 +#define CYREG_B0_P7_U1_PLD_IT6 0x40010e98 +#define CYREG_B0_P7_U1_PLD_IT7 0x40010e9c +#define CYREG_B0_P7_U1_PLD_IT8 0x40010ea0 +#define CYREG_B0_P7_U1_PLD_IT9 0x40010ea4 +#define CYREG_B0_P7_U1_PLD_IT10 0x40010ea8 +#define CYREG_B0_P7_U1_PLD_IT11 0x40010eac +#define CYREG_B0_P7_U1_PLD_ORT0 0x40010eb0 +#define CYREG_B0_P7_U1_PLD_ORT1 0x40010eb2 +#define CYREG_B0_P7_U1_PLD_ORT2 0x40010eb4 +#define CYREG_B0_P7_U1_PLD_ORT3 0x40010eb6 +#define CYREG_B0_P7_U1_MC_CFG_CEN_CONST 0x40010eb8 +#define CYREG_B0_P7_U1_MC_CFG_XORFB 0x40010eba +#define CYREG_B0_P7_U1_MC_CFG_SET_RESET 0x40010ebc +#define CYREG_B0_P7_U1_MC_CFG_BYPASS 0x40010ebe +#define CYREG_B0_P7_U1_CFG0 0x40010ec0 +#define CYREG_B0_P7_U1_CFG1 0x40010ec1 +#define CYREG_B0_P7_U1_CFG2 0x40010ec2 +#define CYREG_B0_P7_U1_CFG3 0x40010ec3 +#define CYREG_B0_P7_U1_CFG4 0x40010ec4 +#define CYREG_B0_P7_U1_CFG5 0x40010ec5 +#define CYREG_B0_P7_U1_CFG6 0x40010ec6 +#define CYREG_B0_P7_U1_CFG7 0x40010ec7 +#define CYREG_B0_P7_U1_CFG8 0x40010ec8 +#define CYREG_B0_P7_U1_CFG9 0x40010ec9 +#define CYREG_B0_P7_U1_CFG10 0x40010eca +#define CYREG_B0_P7_U1_CFG11 0x40010ecb +#define CYREG_B0_P7_U1_CFG12 0x40010ecc +#define CYREG_B0_P7_U1_CFG13 0x40010ecd +#define CYREG_B0_P7_U1_CFG14 0x40010ece +#define CYREG_B0_P7_U1_CFG15 0x40010ecf +#define CYREG_B0_P7_U1_CFG16 0x40010ed0 +#define CYREG_B0_P7_U1_CFG17 0x40010ed1 +#define CYREG_B0_P7_U1_CFG18 0x40010ed2 +#define CYREG_B0_P7_U1_CFG19 0x40010ed3 +#define CYREG_B0_P7_U1_CFG20 0x40010ed4 +#define CYREG_B0_P7_U1_CFG21 0x40010ed5 +#define CYREG_B0_P7_U1_CFG22 0x40010ed6 +#define CYREG_B0_P7_U1_CFG23 0x40010ed7 +#define CYREG_B0_P7_U1_CFG24 0x40010ed8 +#define CYREG_B0_P7_U1_CFG25 0x40010ed9 +#define CYREG_B0_P7_U1_CFG26 0x40010eda +#define CYREG_B0_P7_U1_CFG27 0x40010edb +#define CYREG_B0_P7_U1_CFG28 0x40010edc +#define CYREG_B0_P7_U1_CFG29 0x40010edd +#define CYREG_B0_P7_U1_CFG30 0x40010ede +#define CYREG_B0_P7_U1_CFG31 0x40010edf +#define CYREG_B0_P7_U1_DCFG0 0x40010ee0 +#define CYREG_B0_P7_U1_DCFG1 0x40010ee2 +#define CYREG_B0_P7_U1_DCFG2 0x40010ee4 +#define CYREG_B0_P7_U1_DCFG3 0x40010ee6 +#define CYREG_B0_P7_U1_DCFG4 0x40010ee8 +#define CYREG_B0_P7_U1_DCFG5 0x40010eea +#define CYREG_B0_P7_U1_DCFG6 0x40010eec +#define CYREG_B0_P7_U1_DCFG7 0x40010eee +#define CYDEV_UCFG_B0_P7_ROUTE_BASE 0x40010f00 +#define CYDEV_UCFG_B0_P7_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_BASE 0x40011000 +#define CYDEV_UCFG_B1_SIZE 0x00000fef +#define CYDEV_UCFG_B1_P2_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P2_U0_BASE 0x40011400 +#define CYDEV_UCFG_B1_P2_U0_SIZE 0x00000070 +#define CYREG_B1_P2_U0_PLD_IT0 0x40011400 +#define CYREG_B1_P2_U0_PLD_IT1 0x40011404 +#define CYREG_B1_P2_U0_PLD_IT2 0x40011408 +#define CYREG_B1_P2_U0_PLD_IT3 0x4001140c +#define CYREG_B1_P2_U0_PLD_IT4 0x40011410 +#define CYREG_B1_P2_U0_PLD_IT5 0x40011414 +#define CYREG_B1_P2_U0_PLD_IT6 0x40011418 +#define CYREG_B1_P2_U0_PLD_IT7 0x4001141c +#define CYREG_B1_P2_U0_PLD_IT8 0x40011420 +#define CYREG_B1_P2_U0_PLD_IT9 0x40011424 +#define CYREG_B1_P2_U0_PLD_IT10 0x40011428 +#define CYREG_B1_P2_U0_PLD_IT11 0x4001142c +#define CYREG_B1_P2_U0_PLD_ORT0 0x40011430 +#define CYREG_B1_P2_U0_PLD_ORT1 0x40011432 +#define CYREG_B1_P2_U0_PLD_ORT2 0x40011434 +#define CYREG_B1_P2_U0_PLD_ORT3 0x40011436 +#define CYREG_B1_P2_U0_MC_CFG_CEN_CONST 0x40011438 +#define CYREG_B1_P2_U0_MC_CFG_XORFB 0x4001143a +#define CYREG_B1_P2_U0_MC_CFG_SET_RESET 0x4001143c +#define CYREG_B1_P2_U0_MC_CFG_BYPASS 0x4001143e +#define CYREG_B1_P2_U0_CFG0 0x40011440 +#define CYREG_B1_P2_U0_CFG1 0x40011441 +#define CYREG_B1_P2_U0_CFG2 0x40011442 +#define CYREG_B1_P2_U0_CFG3 0x40011443 +#define CYREG_B1_P2_U0_CFG4 0x40011444 +#define CYREG_B1_P2_U0_CFG5 0x40011445 +#define CYREG_B1_P2_U0_CFG6 0x40011446 +#define CYREG_B1_P2_U0_CFG7 0x40011447 +#define CYREG_B1_P2_U0_CFG8 0x40011448 +#define CYREG_B1_P2_U0_CFG9 0x40011449 +#define CYREG_B1_P2_U0_CFG10 0x4001144a +#define CYREG_B1_P2_U0_CFG11 0x4001144b +#define CYREG_B1_P2_U0_CFG12 0x4001144c +#define CYREG_B1_P2_U0_CFG13 0x4001144d +#define CYREG_B1_P2_U0_CFG14 0x4001144e +#define CYREG_B1_P2_U0_CFG15 0x4001144f +#define CYREG_B1_P2_U0_CFG16 0x40011450 +#define CYREG_B1_P2_U0_CFG17 0x40011451 +#define CYREG_B1_P2_U0_CFG18 0x40011452 +#define CYREG_B1_P2_U0_CFG19 0x40011453 +#define CYREG_B1_P2_U0_CFG20 0x40011454 +#define CYREG_B1_P2_U0_CFG21 0x40011455 +#define CYREG_B1_P2_U0_CFG22 0x40011456 +#define CYREG_B1_P2_U0_CFG23 0x40011457 +#define CYREG_B1_P2_U0_CFG24 0x40011458 +#define CYREG_B1_P2_U0_CFG25 0x40011459 +#define CYREG_B1_P2_U0_CFG26 0x4001145a +#define CYREG_B1_P2_U0_CFG27 0x4001145b +#define CYREG_B1_P2_U0_CFG28 0x4001145c +#define CYREG_B1_P2_U0_CFG29 0x4001145d +#define CYREG_B1_P2_U0_CFG30 0x4001145e +#define CYREG_B1_P2_U0_CFG31 0x4001145f +#define CYREG_B1_P2_U0_DCFG0 0x40011460 +#define CYREG_B1_P2_U0_DCFG1 0x40011462 +#define CYREG_B1_P2_U0_DCFG2 0x40011464 +#define CYREG_B1_P2_U0_DCFG3 0x40011466 +#define CYREG_B1_P2_U0_DCFG4 0x40011468 +#define CYREG_B1_P2_U0_DCFG5 0x4001146a +#define CYREG_B1_P2_U0_DCFG6 0x4001146c +#define CYREG_B1_P2_U0_DCFG7 0x4001146e +#define CYDEV_UCFG_B1_P2_U1_BASE 0x40011480 +#define CYDEV_UCFG_B1_P2_U1_SIZE 0x00000070 +#define CYREG_B1_P2_U1_PLD_IT0 0x40011480 +#define CYREG_B1_P2_U1_PLD_IT1 0x40011484 +#define CYREG_B1_P2_U1_PLD_IT2 0x40011488 +#define CYREG_B1_P2_U1_PLD_IT3 0x4001148c +#define CYREG_B1_P2_U1_PLD_IT4 0x40011490 +#define CYREG_B1_P2_U1_PLD_IT5 0x40011494 +#define CYREG_B1_P2_U1_PLD_IT6 0x40011498 +#define CYREG_B1_P2_U1_PLD_IT7 0x4001149c +#define CYREG_B1_P2_U1_PLD_IT8 0x400114a0 +#define CYREG_B1_P2_U1_PLD_IT9 0x400114a4 +#define CYREG_B1_P2_U1_PLD_IT10 0x400114a8 +#define CYREG_B1_P2_U1_PLD_IT11 0x400114ac +#define CYREG_B1_P2_U1_PLD_ORT0 0x400114b0 +#define CYREG_B1_P2_U1_PLD_ORT1 0x400114b2 +#define CYREG_B1_P2_U1_PLD_ORT2 0x400114b4 +#define CYREG_B1_P2_U1_PLD_ORT3 0x400114b6 +#define CYREG_B1_P2_U1_MC_CFG_CEN_CONST 0x400114b8 +#define CYREG_B1_P2_U1_MC_CFG_XORFB 0x400114ba +#define CYREG_B1_P2_U1_MC_CFG_SET_RESET 0x400114bc +#define CYREG_B1_P2_U1_MC_CFG_BYPASS 0x400114be +#define CYREG_B1_P2_U1_CFG0 0x400114c0 +#define CYREG_B1_P2_U1_CFG1 0x400114c1 +#define CYREG_B1_P2_U1_CFG2 0x400114c2 +#define CYREG_B1_P2_U1_CFG3 0x400114c3 +#define CYREG_B1_P2_U1_CFG4 0x400114c4 +#define CYREG_B1_P2_U1_CFG5 0x400114c5 +#define CYREG_B1_P2_U1_CFG6 0x400114c6 +#define CYREG_B1_P2_U1_CFG7 0x400114c7 +#define CYREG_B1_P2_U1_CFG8 0x400114c8 +#define CYREG_B1_P2_U1_CFG9 0x400114c9 +#define CYREG_B1_P2_U1_CFG10 0x400114ca +#define CYREG_B1_P2_U1_CFG11 0x400114cb +#define CYREG_B1_P2_U1_CFG12 0x400114cc +#define CYREG_B1_P2_U1_CFG13 0x400114cd +#define CYREG_B1_P2_U1_CFG14 0x400114ce +#define CYREG_B1_P2_U1_CFG15 0x400114cf +#define CYREG_B1_P2_U1_CFG16 0x400114d0 +#define CYREG_B1_P2_U1_CFG17 0x400114d1 +#define CYREG_B1_P2_U1_CFG18 0x400114d2 +#define CYREG_B1_P2_U1_CFG19 0x400114d3 +#define CYREG_B1_P2_U1_CFG20 0x400114d4 +#define CYREG_B1_P2_U1_CFG21 0x400114d5 +#define CYREG_B1_P2_U1_CFG22 0x400114d6 +#define CYREG_B1_P2_U1_CFG23 0x400114d7 +#define CYREG_B1_P2_U1_CFG24 0x400114d8 +#define CYREG_B1_P2_U1_CFG25 0x400114d9 +#define CYREG_B1_P2_U1_CFG26 0x400114da +#define CYREG_B1_P2_U1_CFG27 0x400114db +#define CYREG_B1_P2_U1_CFG28 0x400114dc +#define CYREG_B1_P2_U1_CFG29 0x400114dd +#define CYREG_B1_P2_U1_CFG30 0x400114de +#define CYREG_B1_P2_U1_CFG31 0x400114df +#define CYREG_B1_P2_U1_DCFG0 0x400114e0 +#define CYREG_B1_P2_U1_DCFG1 0x400114e2 +#define CYREG_B1_P2_U1_DCFG2 0x400114e4 +#define CYREG_B1_P2_U1_DCFG3 0x400114e6 +#define CYREG_B1_P2_U1_DCFG4 0x400114e8 +#define CYREG_B1_P2_U1_DCFG5 0x400114ea +#define CYREG_B1_P2_U1_DCFG6 0x400114ec +#define CYREG_B1_P2_U1_DCFG7 0x400114ee +#define CYDEV_UCFG_B1_P2_ROUTE_BASE 0x40011500 +#define CYDEV_UCFG_B1_P2_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P3_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P3_U0_BASE 0x40011600 +#define CYDEV_UCFG_B1_P3_U0_SIZE 0x00000070 +#define CYREG_B1_P3_U0_PLD_IT0 0x40011600 +#define CYREG_B1_P3_U0_PLD_IT1 0x40011604 +#define CYREG_B1_P3_U0_PLD_IT2 0x40011608 +#define CYREG_B1_P3_U0_PLD_IT3 0x4001160c +#define CYREG_B1_P3_U0_PLD_IT4 0x40011610 +#define CYREG_B1_P3_U0_PLD_IT5 0x40011614 +#define CYREG_B1_P3_U0_PLD_IT6 0x40011618 +#define CYREG_B1_P3_U0_PLD_IT7 0x4001161c +#define CYREG_B1_P3_U0_PLD_IT8 0x40011620 +#define CYREG_B1_P3_U0_PLD_IT9 0x40011624 +#define CYREG_B1_P3_U0_PLD_IT10 0x40011628 +#define CYREG_B1_P3_U0_PLD_IT11 0x4001162c +#define CYREG_B1_P3_U0_PLD_ORT0 0x40011630 +#define CYREG_B1_P3_U0_PLD_ORT1 0x40011632 +#define CYREG_B1_P3_U0_PLD_ORT2 0x40011634 +#define CYREG_B1_P3_U0_PLD_ORT3 0x40011636 +#define CYREG_B1_P3_U0_MC_CFG_CEN_CONST 0x40011638 +#define CYREG_B1_P3_U0_MC_CFG_XORFB 0x4001163a +#define CYREG_B1_P3_U0_MC_CFG_SET_RESET 0x4001163c +#define CYREG_B1_P3_U0_MC_CFG_BYPASS 0x4001163e +#define CYREG_B1_P3_U0_CFG0 0x40011640 +#define CYREG_B1_P3_U0_CFG1 0x40011641 +#define CYREG_B1_P3_U0_CFG2 0x40011642 +#define CYREG_B1_P3_U0_CFG3 0x40011643 +#define CYREG_B1_P3_U0_CFG4 0x40011644 +#define CYREG_B1_P3_U0_CFG5 0x40011645 +#define CYREG_B1_P3_U0_CFG6 0x40011646 +#define CYREG_B1_P3_U0_CFG7 0x40011647 +#define CYREG_B1_P3_U0_CFG8 0x40011648 +#define CYREG_B1_P3_U0_CFG9 0x40011649 +#define CYREG_B1_P3_U0_CFG10 0x4001164a +#define CYREG_B1_P3_U0_CFG11 0x4001164b +#define CYREG_B1_P3_U0_CFG12 0x4001164c +#define CYREG_B1_P3_U0_CFG13 0x4001164d +#define CYREG_B1_P3_U0_CFG14 0x4001164e +#define CYREG_B1_P3_U0_CFG15 0x4001164f +#define CYREG_B1_P3_U0_CFG16 0x40011650 +#define CYREG_B1_P3_U0_CFG17 0x40011651 +#define CYREG_B1_P3_U0_CFG18 0x40011652 +#define CYREG_B1_P3_U0_CFG19 0x40011653 +#define CYREG_B1_P3_U0_CFG20 0x40011654 +#define CYREG_B1_P3_U0_CFG21 0x40011655 +#define CYREG_B1_P3_U0_CFG22 0x40011656 +#define CYREG_B1_P3_U0_CFG23 0x40011657 +#define CYREG_B1_P3_U0_CFG24 0x40011658 +#define CYREG_B1_P3_U0_CFG25 0x40011659 +#define CYREG_B1_P3_U0_CFG26 0x4001165a +#define CYREG_B1_P3_U0_CFG27 0x4001165b +#define CYREG_B1_P3_U0_CFG28 0x4001165c +#define CYREG_B1_P3_U0_CFG29 0x4001165d +#define CYREG_B1_P3_U0_CFG30 0x4001165e +#define CYREG_B1_P3_U0_CFG31 0x4001165f +#define CYREG_B1_P3_U0_DCFG0 0x40011660 +#define CYREG_B1_P3_U0_DCFG1 0x40011662 +#define CYREG_B1_P3_U0_DCFG2 0x40011664 +#define CYREG_B1_P3_U0_DCFG3 0x40011666 +#define CYREG_B1_P3_U0_DCFG4 0x40011668 +#define CYREG_B1_P3_U0_DCFG5 0x4001166a +#define CYREG_B1_P3_U0_DCFG6 0x4001166c +#define CYREG_B1_P3_U0_DCFG7 0x4001166e +#define CYDEV_UCFG_B1_P3_U1_BASE 0x40011680 +#define CYDEV_UCFG_B1_P3_U1_SIZE 0x00000070 +#define CYREG_B1_P3_U1_PLD_IT0 0x40011680 +#define CYREG_B1_P3_U1_PLD_IT1 0x40011684 +#define CYREG_B1_P3_U1_PLD_IT2 0x40011688 +#define CYREG_B1_P3_U1_PLD_IT3 0x4001168c +#define CYREG_B1_P3_U1_PLD_IT4 0x40011690 +#define CYREG_B1_P3_U1_PLD_IT5 0x40011694 +#define CYREG_B1_P3_U1_PLD_IT6 0x40011698 +#define CYREG_B1_P3_U1_PLD_IT7 0x4001169c +#define CYREG_B1_P3_U1_PLD_IT8 0x400116a0 +#define CYREG_B1_P3_U1_PLD_IT9 0x400116a4 +#define CYREG_B1_P3_U1_PLD_IT10 0x400116a8 +#define CYREG_B1_P3_U1_PLD_IT11 0x400116ac +#define CYREG_B1_P3_U1_PLD_ORT0 0x400116b0 +#define CYREG_B1_P3_U1_PLD_ORT1 0x400116b2 +#define CYREG_B1_P3_U1_PLD_ORT2 0x400116b4 +#define CYREG_B1_P3_U1_PLD_ORT3 0x400116b6 +#define CYREG_B1_P3_U1_MC_CFG_CEN_CONST 0x400116b8 +#define CYREG_B1_P3_U1_MC_CFG_XORFB 0x400116ba +#define CYREG_B1_P3_U1_MC_CFG_SET_RESET 0x400116bc +#define CYREG_B1_P3_U1_MC_CFG_BYPASS 0x400116be +#define CYREG_B1_P3_U1_CFG0 0x400116c0 +#define CYREG_B1_P3_U1_CFG1 0x400116c1 +#define CYREG_B1_P3_U1_CFG2 0x400116c2 +#define CYREG_B1_P3_U1_CFG3 0x400116c3 +#define CYREG_B1_P3_U1_CFG4 0x400116c4 +#define CYREG_B1_P3_U1_CFG5 0x400116c5 +#define CYREG_B1_P3_U1_CFG6 0x400116c6 +#define CYREG_B1_P3_U1_CFG7 0x400116c7 +#define CYREG_B1_P3_U1_CFG8 0x400116c8 +#define CYREG_B1_P3_U1_CFG9 0x400116c9 +#define CYREG_B1_P3_U1_CFG10 0x400116ca +#define CYREG_B1_P3_U1_CFG11 0x400116cb +#define CYREG_B1_P3_U1_CFG12 0x400116cc +#define CYREG_B1_P3_U1_CFG13 0x400116cd +#define CYREG_B1_P3_U1_CFG14 0x400116ce +#define CYREG_B1_P3_U1_CFG15 0x400116cf +#define CYREG_B1_P3_U1_CFG16 0x400116d0 +#define CYREG_B1_P3_U1_CFG17 0x400116d1 +#define CYREG_B1_P3_U1_CFG18 0x400116d2 +#define CYREG_B1_P3_U1_CFG19 0x400116d3 +#define CYREG_B1_P3_U1_CFG20 0x400116d4 +#define CYREG_B1_P3_U1_CFG21 0x400116d5 +#define CYREG_B1_P3_U1_CFG22 0x400116d6 +#define CYREG_B1_P3_U1_CFG23 0x400116d7 +#define CYREG_B1_P3_U1_CFG24 0x400116d8 +#define CYREG_B1_P3_U1_CFG25 0x400116d9 +#define CYREG_B1_P3_U1_CFG26 0x400116da +#define CYREG_B1_P3_U1_CFG27 0x400116db +#define CYREG_B1_P3_U1_CFG28 0x400116dc +#define CYREG_B1_P3_U1_CFG29 0x400116dd +#define CYREG_B1_P3_U1_CFG30 0x400116de +#define CYREG_B1_P3_U1_CFG31 0x400116df +#define CYREG_B1_P3_U1_DCFG0 0x400116e0 +#define CYREG_B1_P3_U1_DCFG1 0x400116e2 +#define CYREG_B1_P3_U1_DCFG2 0x400116e4 +#define CYREG_B1_P3_U1_DCFG3 0x400116e6 +#define CYREG_B1_P3_U1_DCFG4 0x400116e8 +#define CYREG_B1_P3_U1_DCFG5 0x400116ea +#define CYREG_B1_P3_U1_DCFG6 0x400116ec +#define CYREG_B1_P3_U1_DCFG7 0x400116ee +#define CYDEV_UCFG_B1_P3_ROUTE_BASE 0x40011700 +#define CYDEV_UCFG_B1_P3_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P4_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P4_U0_BASE 0x40011800 +#define CYDEV_UCFG_B1_P4_U0_SIZE 0x00000070 +#define CYREG_B1_P4_U0_PLD_IT0 0x40011800 +#define CYREG_B1_P4_U0_PLD_IT1 0x40011804 +#define CYREG_B1_P4_U0_PLD_IT2 0x40011808 +#define CYREG_B1_P4_U0_PLD_IT3 0x4001180c +#define CYREG_B1_P4_U0_PLD_IT4 0x40011810 +#define CYREG_B1_P4_U0_PLD_IT5 0x40011814 +#define CYREG_B1_P4_U0_PLD_IT6 0x40011818 +#define CYREG_B1_P4_U0_PLD_IT7 0x4001181c +#define CYREG_B1_P4_U0_PLD_IT8 0x40011820 +#define CYREG_B1_P4_U0_PLD_IT9 0x40011824 +#define CYREG_B1_P4_U0_PLD_IT10 0x40011828 +#define CYREG_B1_P4_U0_PLD_IT11 0x4001182c +#define CYREG_B1_P4_U0_PLD_ORT0 0x40011830 +#define CYREG_B1_P4_U0_PLD_ORT1 0x40011832 +#define CYREG_B1_P4_U0_PLD_ORT2 0x40011834 +#define CYREG_B1_P4_U0_PLD_ORT3 0x40011836 +#define CYREG_B1_P4_U0_MC_CFG_CEN_CONST 0x40011838 +#define CYREG_B1_P4_U0_MC_CFG_XORFB 0x4001183a +#define CYREG_B1_P4_U0_MC_CFG_SET_RESET 0x4001183c +#define CYREG_B1_P4_U0_MC_CFG_BYPASS 0x4001183e +#define CYREG_B1_P4_U0_CFG0 0x40011840 +#define CYREG_B1_P4_U0_CFG1 0x40011841 +#define CYREG_B1_P4_U0_CFG2 0x40011842 +#define CYREG_B1_P4_U0_CFG3 0x40011843 +#define CYREG_B1_P4_U0_CFG4 0x40011844 +#define CYREG_B1_P4_U0_CFG5 0x40011845 +#define CYREG_B1_P4_U0_CFG6 0x40011846 +#define CYREG_B1_P4_U0_CFG7 0x40011847 +#define CYREG_B1_P4_U0_CFG8 0x40011848 +#define CYREG_B1_P4_U0_CFG9 0x40011849 +#define CYREG_B1_P4_U0_CFG10 0x4001184a +#define CYREG_B1_P4_U0_CFG11 0x4001184b +#define CYREG_B1_P4_U0_CFG12 0x4001184c +#define CYREG_B1_P4_U0_CFG13 0x4001184d +#define CYREG_B1_P4_U0_CFG14 0x4001184e +#define CYREG_B1_P4_U0_CFG15 0x4001184f +#define CYREG_B1_P4_U0_CFG16 0x40011850 +#define CYREG_B1_P4_U0_CFG17 0x40011851 +#define CYREG_B1_P4_U0_CFG18 0x40011852 +#define CYREG_B1_P4_U0_CFG19 0x40011853 +#define CYREG_B1_P4_U0_CFG20 0x40011854 +#define CYREG_B1_P4_U0_CFG21 0x40011855 +#define CYREG_B1_P4_U0_CFG22 0x40011856 +#define CYREG_B1_P4_U0_CFG23 0x40011857 +#define CYREG_B1_P4_U0_CFG24 0x40011858 +#define CYREG_B1_P4_U0_CFG25 0x40011859 +#define CYREG_B1_P4_U0_CFG26 0x4001185a +#define CYREG_B1_P4_U0_CFG27 0x4001185b +#define CYREG_B1_P4_U0_CFG28 0x4001185c +#define CYREG_B1_P4_U0_CFG29 0x4001185d +#define CYREG_B1_P4_U0_CFG30 0x4001185e +#define CYREG_B1_P4_U0_CFG31 0x4001185f +#define CYREG_B1_P4_U0_DCFG0 0x40011860 +#define CYREG_B1_P4_U0_DCFG1 0x40011862 +#define CYREG_B1_P4_U0_DCFG2 0x40011864 +#define CYREG_B1_P4_U0_DCFG3 0x40011866 +#define CYREG_B1_P4_U0_DCFG4 0x40011868 +#define CYREG_B1_P4_U0_DCFG5 0x4001186a +#define CYREG_B1_P4_U0_DCFG6 0x4001186c +#define CYREG_B1_P4_U0_DCFG7 0x4001186e +#define CYDEV_UCFG_B1_P4_U1_BASE 0x40011880 +#define CYDEV_UCFG_B1_P4_U1_SIZE 0x00000070 +#define CYREG_B1_P4_U1_PLD_IT0 0x40011880 +#define CYREG_B1_P4_U1_PLD_IT1 0x40011884 +#define CYREG_B1_P4_U1_PLD_IT2 0x40011888 +#define CYREG_B1_P4_U1_PLD_IT3 0x4001188c +#define CYREG_B1_P4_U1_PLD_IT4 0x40011890 +#define CYREG_B1_P4_U1_PLD_IT5 0x40011894 +#define CYREG_B1_P4_U1_PLD_IT6 0x40011898 +#define CYREG_B1_P4_U1_PLD_IT7 0x4001189c +#define CYREG_B1_P4_U1_PLD_IT8 0x400118a0 +#define CYREG_B1_P4_U1_PLD_IT9 0x400118a4 +#define CYREG_B1_P4_U1_PLD_IT10 0x400118a8 +#define CYREG_B1_P4_U1_PLD_IT11 0x400118ac +#define CYREG_B1_P4_U1_PLD_ORT0 0x400118b0 +#define CYREG_B1_P4_U1_PLD_ORT1 0x400118b2 +#define CYREG_B1_P4_U1_PLD_ORT2 0x400118b4 +#define CYREG_B1_P4_U1_PLD_ORT3 0x400118b6 +#define CYREG_B1_P4_U1_MC_CFG_CEN_CONST 0x400118b8 +#define CYREG_B1_P4_U1_MC_CFG_XORFB 0x400118ba +#define CYREG_B1_P4_U1_MC_CFG_SET_RESET 0x400118bc +#define CYREG_B1_P4_U1_MC_CFG_BYPASS 0x400118be +#define CYREG_B1_P4_U1_CFG0 0x400118c0 +#define CYREG_B1_P4_U1_CFG1 0x400118c1 +#define CYREG_B1_P4_U1_CFG2 0x400118c2 +#define CYREG_B1_P4_U1_CFG3 0x400118c3 +#define CYREG_B1_P4_U1_CFG4 0x400118c4 +#define CYREG_B1_P4_U1_CFG5 0x400118c5 +#define CYREG_B1_P4_U1_CFG6 0x400118c6 +#define CYREG_B1_P4_U1_CFG7 0x400118c7 +#define CYREG_B1_P4_U1_CFG8 0x400118c8 +#define CYREG_B1_P4_U1_CFG9 0x400118c9 +#define CYREG_B1_P4_U1_CFG10 0x400118ca +#define CYREG_B1_P4_U1_CFG11 0x400118cb +#define CYREG_B1_P4_U1_CFG12 0x400118cc +#define CYREG_B1_P4_U1_CFG13 0x400118cd +#define CYREG_B1_P4_U1_CFG14 0x400118ce +#define CYREG_B1_P4_U1_CFG15 0x400118cf +#define CYREG_B1_P4_U1_CFG16 0x400118d0 +#define CYREG_B1_P4_U1_CFG17 0x400118d1 +#define CYREG_B1_P4_U1_CFG18 0x400118d2 +#define CYREG_B1_P4_U1_CFG19 0x400118d3 +#define CYREG_B1_P4_U1_CFG20 0x400118d4 +#define CYREG_B1_P4_U1_CFG21 0x400118d5 +#define CYREG_B1_P4_U1_CFG22 0x400118d6 +#define CYREG_B1_P4_U1_CFG23 0x400118d7 +#define CYREG_B1_P4_U1_CFG24 0x400118d8 +#define CYREG_B1_P4_U1_CFG25 0x400118d9 +#define CYREG_B1_P4_U1_CFG26 0x400118da +#define CYREG_B1_P4_U1_CFG27 0x400118db +#define CYREG_B1_P4_U1_CFG28 0x400118dc +#define CYREG_B1_P4_U1_CFG29 0x400118dd +#define CYREG_B1_P4_U1_CFG30 0x400118de +#define CYREG_B1_P4_U1_CFG31 0x400118df +#define CYREG_B1_P4_U1_DCFG0 0x400118e0 +#define CYREG_B1_P4_U1_DCFG1 0x400118e2 +#define CYREG_B1_P4_U1_DCFG2 0x400118e4 +#define CYREG_B1_P4_U1_DCFG3 0x400118e6 +#define CYREG_B1_P4_U1_DCFG4 0x400118e8 +#define CYREG_B1_P4_U1_DCFG5 0x400118ea +#define CYREG_B1_P4_U1_DCFG6 0x400118ec +#define CYREG_B1_P4_U1_DCFG7 0x400118ee +#define CYDEV_UCFG_B1_P4_ROUTE_BASE 0x40011900 +#define CYDEV_UCFG_B1_P4_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_B1_P5_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_SIZE 0x000001ef +#define CYDEV_UCFG_B1_P5_U0_BASE 0x40011a00 +#define CYDEV_UCFG_B1_P5_U0_SIZE 0x00000070 +#define CYREG_B1_P5_U0_PLD_IT0 0x40011a00 +#define CYREG_B1_P5_U0_PLD_IT1 0x40011a04 +#define CYREG_B1_P5_U0_PLD_IT2 0x40011a08 +#define CYREG_B1_P5_U0_PLD_IT3 0x40011a0c +#define CYREG_B1_P5_U0_PLD_IT4 0x40011a10 +#define CYREG_B1_P5_U0_PLD_IT5 0x40011a14 +#define CYREG_B1_P5_U0_PLD_IT6 0x40011a18 +#define CYREG_B1_P5_U0_PLD_IT7 0x40011a1c +#define CYREG_B1_P5_U0_PLD_IT8 0x40011a20 +#define CYREG_B1_P5_U0_PLD_IT9 0x40011a24 +#define CYREG_B1_P5_U0_PLD_IT10 0x40011a28 +#define CYREG_B1_P5_U0_PLD_IT11 0x40011a2c +#define CYREG_B1_P5_U0_PLD_ORT0 0x40011a30 +#define CYREG_B1_P5_U0_PLD_ORT1 0x40011a32 +#define CYREG_B1_P5_U0_PLD_ORT2 0x40011a34 +#define CYREG_B1_P5_U0_PLD_ORT3 0x40011a36 +#define CYREG_B1_P5_U0_MC_CFG_CEN_CONST 0x40011a38 +#define CYREG_B1_P5_U0_MC_CFG_XORFB 0x40011a3a +#define CYREG_B1_P5_U0_MC_CFG_SET_RESET 0x40011a3c +#define CYREG_B1_P5_U0_MC_CFG_BYPASS 0x40011a3e +#define CYREG_B1_P5_U0_CFG0 0x40011a40 +#define CYREG_B1_P5_U0_CFG1 0x40011a41 +#define CYREG_B1_P5_U0_CFG2 0x40011a42 +#define CYREG_B1_P5_U0_CFG3 0x40011a43 +#define CYREG_B1_P5_U0_CFG4 0x40011a44 +#define CYREG_B1_P5_U0_CFG5 0x40011a45 +#define CYREG_B1_P5_U0_CFG6 0x40011a46 +#define CYREG_B1_P5_U0_CFG7 0x40011a47 +#define CYREG_B1_P5_U0_CFG8 0x40011a48 +#define CYREG_B1_P5_U0_CFG9 0x40011a49 +#define CYREG_B1_P5_U0_CFG10 0x40011a4a +#define CYREG_B1_P5_U0_CFG11 0x40011a4b +#define CYREG_B1_P5_U0_CFG12 0x40011a4c +#define CYREG_B1_P5_U0_CFG13 0x40011a4d +#define CYREG_B1_P5_U0_CFG14 0x40011a4e +#define CYREG_B1_P5_U0_CFG15 0x40011a4f +#define CYREG_B1_P5_U0_CFG16 0x40011a50 +#define CYREG_B1_P5_U0_CFG17 0x40011a51 +#define CYREG_B1_P5_U0_CFG18 0x40011a52 +#define CYREG_B1_P5_U0_CFG19 0x40011a53 +#define CYREG_B1_P5_U0_CFG20 0x40011a54 +#define CYREG_B1_P5_U0_CFG21 0x40011a55 +#define CYREG_B1_P5_U0_CFG22 0x40011a56 +#define CYREG_B1_P5_U0_CFG23 0x40011a57 +#define CYREG_B1_P5_U0_CFG24 0x40011a58 +#define CYREG_B1_P5_U0_CFG25 0x40011a59 +#define CYREG_B1_P5_U0_CFG26 0x40011a5a +#define CYREG_B1_P5_U0_CFG27 0x40011a5b +#define CYREG_B1_P5_U0_CFG28 0x40011a5c +#define CYREG_B1_P5_U0_CFG29 0x40011a5d +#define CYREG_B1_P5_U0_CFG30 0x40011a5e +#define CYREG_B1_P5_U0_CFG31 0x40011a5f +#define CYREG_B1_P5_U0_DCFG0 0x40011a60 +#define CYREG_B1_P5_U0_DCFG1 0x40011a62 +#define CYREG_B1_P5_U0_DCFG2 0x40011a64 +#define CYREG_B1_P5_U0_DCFG3 0x40011a66 +#define CYREG_B1_P5_U0_DCFG4 0x40011a68 +#define CYREG_B1_P5_U0_DCFG5 0x40011a6a +#define CYREG_B1_P5_U0_DCFG6 0x40011a6c +#define CYREG_B1_P5_U0_DCFG7 0x40011a6e +#define CYDEV_UCFG_B1_P5_U1_BASE 0x40011a80 +#define CYDEV_UCFG_B1_P5_U1_SIZE 0x00000070 +#define CYREG_B1_P5_U1_PLD_IT0 0x40011a80 +#define CYREG_B1_P5_U1_PLD_IT1 0x40011a84 +#define CYREG_B1_P5_U1_PLD_IT2 0x40011a88 +#define CYREG_B1_P5_U1_PLD_IT3 0x40011a8c +#define CYREG_B1_P5_U1_PLD_IT4 0x40011a90 +#define CYREG_B1_P5_U1_PLD_IT5 0x40011a94 +#define CYREG_B1_P5_U1_PLD_IT6 0x40011a98 +#define CYREG_B1_P5_U1_PLD_IT7 0x40011a9c +#define CYREG_B1_P5_U1_PLD_IT8 0x40011aa0 +#define CYREG_B1_P5_U1_PLD_IT9 0x40011aa4 +#define CYREG_B1_P5_U1_PLD_IT10 0x40011aa8 +#define CYREG_B1_P5_U1_PLD_IT11 0x40011aac +#define CYREG_B1_P5_U1_PLD_ORT0 0x40011ab0 +#define CYREG_B1_P5_U1_PLD_ORT1 0x40011ab2 +#define CYREG_B1_P5_U1_PLD_ORT2 0x40011ab4 +#define CYREG_B1_P5_U1_PLD_ORT3 0x40011ab6 +#define CYREG_B1_P5_U1_MC_CFG_CEN_CONST 0x40011ab8 +#define CYREG_B1_P5_U1_MC_CFG_XORFB 0x40011aba +#define CYREG_B1_P5_U1_MC_CFG_SET_RESET 0x40011abc +#define CYREG_B1_P5_U1_MC_CFG_BYPASS 0x40011abe +#define CYREG_B1_P5_U1_CFG0 0x40011ac0 +#define CYREG_B1_P5_U1_CFG1 0x40011ac1 +#define CYREG_B1_P5_U1_CFG2 0x40011ac2 +#define CYREG_B1_P5_U1_CFG3 0x40011ac3 +#define CYREG_B1_P5_U1_CFG4 0x40011ac4 +#define CYREG_B1_P5_U1_CFG5 0x40011ac5 +#define CYREG_B1_P5_U1_CFG6 0x40011ac6 +#define CYREG_B1_P5_U1_CFG7 0x40011ac7 +#define CYREG_B1_P5_U1_CFG8 0x40011ac8 +#define CYREG_B1_P5_U1_CFG9 0x40011ac9 +#define CYREG_B1_P5_U1_CFG10 0x40011aca +#define CYREG_B1_P5_U1_CFG11 0x40011acb +#define CYREG_B1_P5_U1_CFG12 0x40011acc +#define CYREG_B1_P5_U1_CFG13 0x40011acd +#define CYREG_B1_P5_U1_CFG14 0x40011ace +#define CYREG_B1_P5_U1_CFG15 0x40011acf +#define CYREG_B1_P5_U1_CFG16 0x40011ad0 +#define CYREG_B1_P5_U1_CFG17 0x40011ad1 +#define CYREG_B1_P5_U1_CFG18 0x40011ad2 +#define CYREG_B1_P5_U1_CFG19 0x40011ad3 +#define CYREG_B1_P5_U1_CFG20 0x40011ad4 +#define CYREG_B1_P5_U1_CFG21 0x40011ad5 +#define CYREG_B1_P5_U1_CFG22 0x40011ad6 +#define CYREG_B1_P5_U1_CFG23 0x40011ad7 +#define CYREG_B1_P5_U1_CFG24 0x40011ad8 +#define CYREG_B1_P5_U1_CFG25 0x40011ad9 +#define CYREG_B1_P5_U1_CFG26 0x40011ada +#define CYREG_B1_P5_U1_CFG27 0x40011adb +#define CYREG_B1_P5_U1_CFG28 0x40011adc +#define CYREG_B1_P5_U1_CFG29 0x40011add +#define CYREG_B1_P5_U1_CFG30 0x40011ade +#define CYREG_B1_P5_U1_CFG31 0x40011adf +#define CYREG_B1_P5_U1_DCFG0 0x40011ae0 +#define CYREG_B1_P5_U1_DCFG1 0x40011ae2 +#define CYREG_B1_P5_U1_DCFG2 0x40011ae4 +#define CYREG_B1_P5_U1_DCFG3 0x40011ae6 +#define CYREG_B1_P5_U1_DCFG4 0x40011ae8 +#define CYREG_B1_P5_U1_DCFG5 0x40011aea +#define CYREG_B1_P5_U1_DCFG6 0x40011aec +#define CYREG_B1_P5_U1_DCFG7 0x40011aee +#define CYDEV_UCFG_B1_P5_ROUTE_BASE 0x40011b00 +#define CYDEV_UCFG_B1_P5_ROUTE_SIZE 0x000000ef +#define CYDEV_UCFG_DSI0_BASE 0x40014000 +#define CYDEV_UCFG_DSI0_SIZE 0x000000ef +#define CYDEV_UCFG_DSI1_BASE 0x40014100 +#define CYDEV_UCFG_DSI1_SIZE 0x000000ef +#define CYDEV_UCFG_DSI2_BASE 0x40014200 +#define CYDEV_UCFG_DSI2_SIZE 0x000000ef +#define CYDEV_UCFG_DSI3_BASE 0x40014300 +#define CYDEV_UCFG_DSI3_SIZE 0x000000ef +#define CYDEV_UCFG_DSI4_BASE 0x40014400 +#define CYDEV_UCFG_DSI4_SIZE 0x000000ef +#define CYDEV_UCFG_DSI5_BASE 0x40014500 +#define CYDEV_UCFG_DSI5_SIZE 0x000000ef +#define CYDEV_UCFG_DSI6_BASE 0x40014600 +#define CYDEV_UCFG_DSI6_SIZE 0x000000ef +#define CYDEV_UCFG_DSI7_BASE 0x40014700 +#define CYDEV_UCFG_DSI7_SIZE 0x000000ef +#define CYDEV_UCFG_DSI8_BASE 0x40014800 +#define CYDEV_UCFG_DSI8_SIZE 0x000000ef +#define CYDEV_UCFG_DSI9_BASE 0x40014900 +#define CYDEV_UCFG_DSI9_SIZE 0x000000ef +#define CYDEV_UCFG_DSI12_BASE 0x40014c00 +#define CYDEV_UCFG_DSI12_SIZE 0x000000ef +#define CYDEV_UCFG_DSI13_BASE 0x40014d00 +#define CYDEV_UCFG_DSI13_SIZE 0x000000ef +#define CYDEV_UCFG_BCTL0_BASE 0x40015000 +#define CYDEV_UCFG_BCTL0_SIZE 0x00000010 +#define CYREG_BCTL0_MDCLK_EN 0x40015000 +#define CYREG_BCTL0_MBCLK_EN 0x40015001 +#define CYREG_BCTL0_WAIT_CFG 0x40015002 +#define CYREG_BCTL0_BANK_CTL 0x40015003 +#define CYREG_BCTL0_UDB_TEST_3 0x40015007 +#define CYREG_BCTL0_DCLK_EN0 0x40015008 +#define CYREG_BCTL0_BCLK_EN0 0x40015009 +#define CYREG_BCTL0_DCLK_EN1 0x4001500a +#define CYREG_BCTL0_BCLK_EN1 0x4001500b +#define CYREG_BCTL0_DCLK_EN2 0x4001500c +#define CYREG_BCTL0_BCLK_EN2 0x4001500d +#define CYREG_BCTL0_DCLK_EN3 0x4001500e +#define CYREG_BCTL0_BCLK_EN3 0x4001500f +#define CYDEV_UCFG_BCTL1_BASE 0x40015010 +#define CYDEV_UCFG_BCTL1_SIZE 0x00000010 +#define CYREG_BCTL1_MDCLK_EN 0x40015010 +#define CYREG_BCTL1_MBCLK_EN 0x40015011 +#define CYREG_BCTL1_WAIT_CFG 0x40015012 +#define CYREG_BCTL1_BANK_CTL 0x40015013 +#define CYREG_BCTL1_UDB_TEST_3 0x40015017 +#define CYREG_BCTL1_DCLK_EN0 0x40015018 +#define CYREG_BCTL1_BCLK_EN0 0x40015019 +#define CYREG_BCTL1_DCLK_EN1 0x4001501a +#define CYREG_BCTL1_BCLK_EN1 0x4001501b +#define CYREG_BCTL1_DCLK_EN2 0x4001501c +#define CYREG_BCTL1_BCLK_EN2 0x4001501d +#define CYREG_BCTL1_DCLK_EN3 0x4001501e +#define CYREG_BCTL1_BCLK_EN3 0x4001501f +#define CYDEV_IDMUX_BASE 0x40015100 +#define CYDEV_IDMUX_SIZE 0x00000016 +#define CYREG_IDMUX_IRQ_CTL0 0x40015100 +#define CYREG_IDMUX_IRQ_CTL1 0x40015101 +#define CYREG_IDMUX_IRQ_CTL2 0x40015102 +#define CYREG_IDMUX_IRQ_CTL3 0x40015103 +#define CYREG_IDMUX_IRQ_CTL4 0x40015104 +#define CYREG_IDMUX_IRQ_CTL5 0x40015105 +#define CYREG_IDMUX_IRQ_CTL6 0x40015106 +#define CYREG_IDMUX_IRQ_CTL7 0x40015107 +#define CYREG_IDMUX_DRQ_CTL0 0x40015110 +#define CYREG_IDMUX_DRQ_CTL1 0x40015111 +#define CYREG_IDMUX_DRQ_CTL2 0x40015112 +#define CYREG_IDMUX_DRQ_CTL3 0x40015113 +#define CYREG_IDMUX_DRQ_CTL4 0x40015114 +#define CYREG_IDMUX_DRQ_CTL5 0x40015115 +#define CYDEV_CACHERAM_BASE 0x40030000 +#define CYDEV_CACHERAM_SIZE 0x00000400 +#define CYREG_CACHERAM_DATA_MBASE 0x40030000 +#define CYREG_CACHERAM_DATA_MSIZE 0x00000400 +#define CYDEV_SFR_BASE 0x40050100 +#define CYDEV_SFR_SIZE 0x000000fb +#define CYREG_SFR_GPIO0 0x40050180 +#define CYREG_SFR_GPIRD0 0x40050189 +#define CYREG_SFR_GPIO0_SEL 0x4005018a +#define CYREG_SFR_GPIO1 0x40050190 +#define CYREG_SFR_GPIRD1 0x40050191 +#define CYREG_SFR_GPIO2 0x40050198 +#define CYREG_SFR_GPIRD2 0x40050199 +#define CYREG_SFR_GPIO2_SEL 0x4005019a +#define CYREG_SFR_GPIO1_SEL 0x400501a2 +#define CYREG_SFR_GPIO3 0x400501b0 +#define CYREG_SFR_GPIRD3 0x400501b1 +#define CYREG_SFR_GPIO3_SEL 0x400501b2 +#define CYREG_SFR_GPIO4 0x400501c0 +#define CYREG_SFR_GPIRD4 0x400501c1 +#define CYREG_SFR_GPIO4_SEL 0x400501c2 +#define CYREG_SFR_GPIO5 0x400501c8 +#define CYREG_SFR_GPIRD5 0x400501c9 +#define CYREG_SFR_GPIO5_SEL 0x400501ca +#define CYREG_SFR_GPIO6 0x400501d8 +#define CYREG_SFR_GPIRD6 0x400501d9 +#define CYREG_SFR_GPIO6_SEL 0x400501da +#define CYREG_SFR_GPIO12 0x400501e8 +#define CYREG_SFR_GPIRD12 0x400501e9 +#define CYREG_SFR_GPIO12_SEL 0x400501f2 +#define CYREG_SFR_GPIO15 0x400501f8 +#define CYREG_SFR_GPIRD15 0x400501f9 +#define CYREG_SFR_GPIO15_SEL 0x400501fa +#define CYDEV_P3BA_BASE 0x40050300 +#define CYDEV_P3BA_SIZE 0x0000002b +#define CYREG_P3BA_Y_START 0x40050300 +#define CYREG_P3BA_YROLL 0x40050301 +#define CYREG_P3BA_YCFG 0x40050302 +#define CYREG_P3BA_X_START1 0x40050303 +#define CYREG_P3BA_X_START2 0x40050304 +#define CYREG_P3BA_XROLL1 0x40050305 +#define CYREG_P3BA_XROLL2 0x40050306 +#define CYREG_P3BA_XINC 0x40050307 +#define CYREG_P3BA_XCFG 0x40050308 +#define CYREG_P3BA_OFFSETADDR1 0x40050309 +#define CYREG_P3BA_OFFSETADDR2 0x4005030a +#define CYREG_P3BA_OFFSETADDR3 0x4005030b +#define CYREG_P3BA_ABSADDR1 0x4005030c +#define CYREG_P3BA_ABSADDR2 0x4005030d +#define CYREG_P3BA_ABSADDR3 0x4005030e +#define CYREG_P3BA_ABSADDR4 0x4005030f +#define CYREG_P3BA_DATCFG1 0x40050310 +#define CYREG_P3BA_DATCFG2 0x40050311 +#define CYREG_P3BA_CMP_RSLT1 0x40050314 +#define CYREG_P3BA_CMP_RSLT2 0x40050315 +#define CYREG_P3BA_CMP_RSLT3 0x40050316 +#define CYREG_P3BA_CMP_RSLT4 0x40050317 +#define CYREG_P3BA_DATA_REG1 0x40050318 +#define CYREG_P3BA_DATA_REG2 0x40050319 +#define CYREG_P3BA_DATA_REG3 0x4005031a +#define CYREG_P3BA_DATA_REG4 0x4005031b +#define CYREG_P3BA_EXP_DATA1 0x4005031c +#define CYREG_P3BA_EXP_DATA2 0x4005031d +#define CYREG_P3BA_EXP_DATA3 0x4005031e +#define CYREG_P3BA_EXP_DATA4 0x4005031f +#define CYREG_P3BA_MSTR_HRDATA1 0x40050320 +#define CYREG_P3BA_MSTR_HRDATA2 0x40050321 +#define CYREG_P3BA_MSTR_HRDATA3 0x40050322 +#define CYREG_P3BA_MSTR_HRDATA4 0x40050323 +#define CYREG_P3BA_BIST_EN 0x40050324 +#define CYREG_P3BA_PHUB_MASTER_SSR 0x40050325 +#define CYREG_P3BA_SEQCFG1 0x40050326 +#define CYREG_P3BA_SEQCFG2 0x40050327 +#define CYREG_P3BA_Y_CURR 0x40050328 +#define CYREG_P3BA_X_CURR1 0x40050329 +#define CYREG_P3BA_X_CURR2 0x4005032a +#define CYDEV_PANTHER_BASE 0x40080000 +#define CYDEV_PANTHER_SIZE 0x00000020 +#define CYREG_PANTHER_STCALIB_CFG 0x40080000 +#define CYREG_PANTHER_WAITPIPE 0x40080004 +#define CYREG_PANTHER_TRACE_CFG 0x40080008 +#define CYREG_PANTHER_DBG_CFG 0x4008000c +#define CYREG_PANTHER_CM3_LCKRST_STAT 0x40080018 +#define CYREG_PANTHER_DEVICE_ID 0x4008001c +#define CYDEV_FLSECC_BASE 0x48000000 +#define CYDEV_FLSECC_SIZE 0x00008000 +#define CYREG_FLSECC_DATA_MBASE 0x48000000 +#define CYREG_FLSECC_DATA_MSIZE 0x00008000 +#define CYDEV_FLSHID_BASE 0x49000000 +#define CYDEV_FLSHID_SIZE 0x00000200 +#define CYREG_FLSHID_RSVD_MBASE 0x49000000 +#define CYREG_FLSHID_RSVD_MSIZE 0x00000080 +#define CYREG_FLSHID_CUST_MDATA_MBASE 0x49000080 +#define CYREG_FLSHID_CUST_MDATA_MSIZE 0x00000080 +#define CYDEV_FLSHID_CUST_TABLES_BASE 0x49000100 +#define CYDEV_FLSHID_CUST_TABLES_SIZE 0x00000040 +#define CYREG_FLSHID_CUST_TABLES_Y_LOC 0x49000100 +#define CYREG_FLSHID_CUST_TABLES_X_LOC 0x49000101 +#define CYREG_FLSHID_CUST_TABLES_WAFER_NUM 0x49000102 +#define CYREG_FLSHID_CUST_TABLES_LOT_LSB 0x49000103 +#define CYREG_FLSHID_CUST_TABLES_LOT_MSB 0x49000104 +#define CYREG_FLSHID_CUST_TABLES_WRK_WK 0x49000105 +#define CYREG_FLSHID_CUST_TABLES_FAB_YR 0x49000106 +#define CYREG_FLSHID_CUST_TABLES_MINOR 0x49000107 +#define CYREG_FLSHID_CUST_TABLES_IMO_3MHZ 0x49000108 +#define CYREG_FLSHID_CUST_TABLES_IMO_6MHZ 0x49000109 +#define CYREG_FLSHID_CUST_TABLES_IMO_12MHZ 0x4900010a +#define CYREG_FLSHID_CUST_TABLES_IMO_24MHZ 0x4900010b +#define CYREG_FLSHID_CUST_TABLES_IMO_67MHZ 0x4900010c +#define CYREG_FLSHID_CUST_TABLES_IMO_80MHZ 0x4900010d +#define CYREG_FLSHID_CUST_TABLES_IMO_92MHZ 0x4900010e +#define CYREG_FLSHID_CUST_TABLES_IMO_USB 0x4900010f +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS 0x49000110 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS 0x49000111 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS 0x49000112 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS 0x49000113 +#define CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS 0x49000114 +#define CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS 0x49000115 +#define CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS 0x49000116 +#define CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS 0x49000117 +#define CYREG_FLSHID_CUST_TABLES_DEC_M1 0x49000118 +#define CYREG_FLSHID_CUST_TABLES_DEC_M2 0x49000119 +#define CYREG_FLSHID_CUST_TABLES_DEC_M3 0x4900011a +#define CYREG_FLSHID_CUST_TABLES_DEC_M4 0x4900011b +#define CYREG_FLSHID_CUST_TABLES_DEC_M5 0x4900011c +#define CYREG_FLSHID_CUST_TABLES_DEC_M6 0x4900011d +#define CYREG_FLSHID_CUST_TABLES_DEC_M7 0x4900011e +#define CYREG_FLSHID_CUST_TABLES_DEC_M8 0x4900011f +#define CYREG_FLSHID_CUST_TABLES_DAC0_M1 0x49000120 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M2 0x49000121 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M3 0x49000122 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M4 0x49000123 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M5 0x49000124 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M6 0x49000125 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M7 0x49000126 +#define CYREG_FLSHID_CUST_TABLES_DAC0_M8 0x49000127 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M1 0x49000128 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M2 0x49000129 +#define CYREG_FLSHID_CUST_TABLES_DAC2_M3 0x4900012a +#define CYREG_FLSHID_CUST_TABLES_DAC2_M4 0x4900012b +#define CYREG_FLSHID_CUST_TABLES_DAC2_M5 0x4900012c +#define CYREG_FLSHID_CUST_TABLES_DAC2_M6 0x4900012d +#define CYREG_FLSHID_CUST_TABLES_DAC2_M7 0x4900012e +#define CYREG_FLSHID_CUST_TABLES_DAC2_M8 0x4900012f +#define CYREG_FLSHID_CUST_TABLES_DAC1_M1 0x49000130 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M2 0x49000131 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M3 0x49000132 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M4 0x49000133 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M5 0x49000134 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M6 0x49000135 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M7 0x49000136 +#define CYREG_FLSHID_CUST_TABLES_DAC1_M8 0x49000137 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M1 0x49000138 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M2 0x49000139 +#define CYREG_FLSHID_CUST_TABLES_DAC3_M3 0x4900013a +#define CYREG_FLSHID_CUST_TABLES_DAC3_M4 0x4900013b +#define CYREG_FLSHID_CUST_TABLES_DAC3_M5 0x4900013c +#define CYREG_FLSHID_CUST_TABLES_DAC3_M6 0x4900013d +#define CYREG_FLSHID_CUST_TABLES_DAC3_M7 0x4900013e +#define CYREG_FLSHID_CUST_TABLES_DAC3_M8 0x4900013f +#define CYDEV_FLSHID_MFG_CFG_BASE 0x49000180 +#define CYDEV_FLSHID_MFG_CFG_SIZE 0x00000080 +#define CYREG_FLSHID_MFG_CFG_IMO_TR1 0x49000188 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR0 0x490001ac +#define CYREG_FLSHID_MFG_CFG_CMP1_TR0 0x490001ae +#define CYREG_FLSHID_MFG_CFG_CMP2_TR0 0x490001b0 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR0 0x490001b2 +#define CYREG_FLSHID_MFG_CFG_CMP0_TR1 0x490001b4 +#define CYREG_FLSHID_MFG_CFG_CMP1_TR1 0x490001b6 +#define CYREG_FLSHID_MFG_CFG_CMP2_TR1 0x490001b8 +#define CYREG_FLSHID_MFG_CFG_CMP3_TR1 0x490001ba +#define CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM 0x490001ce +#define CYDEV_EXTMEM_BASE 0x60000000 +#define CYDEV_EXTMEM_SIZE 0x00800000 +#define CYREG_EXTMEM_DATA_MBASE 0x60000000 +#define CYREG_EXTMEM_DATA_MSIZE 0x00800000 +#define CYDEV_ITM_BASE 0xe0000000 +#define CYDEV_ITM_SIZE 0x00001000 +#define CYREG_ITM_TRACE_EN 0xe0000e00 +#define CYREG_ITM_TRACE_PRIVILEGE 0xe0000e40 +#define CYREG_ITM_TRACE_CTRL 0xe0000e80 +#define CYREG_ITM_LOCK_ACCESS 0xe0000fb0 +#define CYREG_ITM_LOCK_STATUS 0xe0000fb4 +#define CYREG_ITM_PID4 0xe0000fd0 +#define CYREG_ITM_PID5 0xe0000fd4 +#define CYREG_ITM_PID6 0xe0000fd8 +#define CYREG_ITM_PID7 0xe0000fdc +#define CYREG_ITM_PID0 0xe0000fe0 +#define CYREG_ITM_PID1 0xe0000fe4 +#define CYREG_ITM_PID2 0xe0000fe8 +#define CYREG_ITM_PID3 0xe0000fec +#define CYREG_ITM_CID0 0xe0000ff0 +#define CYREG_ITM_CID1 0xe0000ff4 +#define CYREG_ITM_CID2 0xe0000ff8 +#define CYREG_ITM_CID3 0xe0000ffc +#define CYDEV_DWT_BASE 0xe0001000 +#define CYDEV_DWT_SIZE 0x0000005c +#define CYREG_DWT_CTRL 0xe0001000 +#define CYREG_DWT_CYCLE_COUNT 0xe0001004 +#define CYREG_DWT_CPI_COUNT 0xe0001008 +#define CYREG_DWT_EXC_OVHD_COUNT 0xe000100c +#define CYREG_DWT_SLEEP_COUNT 0xe0001010 +#define CYREG_DWT_LSU_COUNT 0xe0001014 +#define CYREG_DWT_FOLD_COUNT 0xe0001018 +#define CYREG_DWT_PC_SAMPLE 0xe000101c +#define CYREG_DWT_COMP_0 0xe0001020 +#define CYREG_DWT_MASK_0 0xe0001024 +#define CYREG_DWT_FUNCTION_0 0xe0001028 +#define CYREG_DWT_COMP_1 0xe0001030 +#define CYREG_DWT_MASK_1 0xe0001034 +#define CYREG_DWT_FUNCTION_1 0xe0001038 +#define CYREG_DWT_COMP_2 0xe0001040 +#define CYREG_DWT_MASK_2 0xe0001044 +#define CYREG_DWT_FUNCTION_2 0xe0001048 +#define CYREG_DWT_COMP_3 0xe0001050 +#define CYREG_DWT_MASK_3 0xe0001054 +#define CYREG_DWT_FUNCTION_3 0xe0001058 +#define CYDEV_FPB_BASE 0xe0002000 +#define CYDEV_FPB_SIZE 0x00001000 +#define CYREG_FPB_CTRL 0xe0002000 +#define CYREG_FPB_REMAP 0xe0002004 +#define CYREG_FPB_FP_COMP_0 0xe0002008 +#define CYREG_FPB_FP_COMP_1 0xe000200c +#define CYREG_FPB_FP_COMP_2 0xe0002010 +#define CYREG_FPB_FP_COMP_3 0xe0002014 +#define CYREG_FPB_FP_COMP_4 0xe0002018 +#define CYREG_FPB_FP_COMP_5 0xe000201c +#define CYREG_FPB_FP_COMP_6 0xe0002020 +#define CYREG_FPB_FP_COMP_7 0xe0002024 +#define CYREG_FPB_PID4 0xe0002fd0 +#define CYREG_FPB_PID5 0xe0002fd4 +#define CYREG_FPB_PID6 0xe0002fd8 +#define CYREG_FPB_PID7 0xe0002fdc +#define CYREG_FPB_PID0 0xe0002fe0 +#define CYREG_FPB_PID1 0xe0002fe4 +#define CYREG_FPB_PID2 0xe0002fe8 +#define CYREG_FPB_PID3 0xe0002fec +#define CYREG_FPB_CID0 0xe0002ff0 +#define CYREG_FPB_CID1 0xe0002ff4 +#define CYREG_FPB_CID2 0xe0002ff8 +#define CYREG_FPB_CID3 0xe0002ffc +#define CYDEV_NVIC_BASE 0xe000e000 +#define CYDEV_NVIC_SIZE 0x00000d3c +#define CYREG_NVIC_INT_CTL_TYPE 0xe000e004 +#define CYREG_NVIC_SYSTICK_CTL 0xe000e010 +#define CYREG_NVIC_SYSTICK_RELOAD 0xe000e014 +#define CYREG_NVIC_SYSTICK_CURRENT 0xe000e018 +#define CYREG_NVIC_SYSTICK_CAL 0xe000e01c +#define CYREG_NVIC_SETENA0 0xe000e100 +#define CYREG_NVIC_CLRENA0 0xe000e180 +#define CYREG_NVIC_SETPEND0 0xe000e200 +#define CYREG_NVIC_CLRPEND0 0xe000e280 +#define CYREG_NVIC_ACTIVE0 0xe000e300 +#define CYREG_NVIC_PRI_0 0xe000e400 +#define CYREG_NVIC_PRI_1 0xe000e401 +#define CYREG_NVIC_PRI_2 0xe000e402 +#define CYREG_NVIC_PRI_3 0xe000e403 +#define CYREG_NVIC_PRI_4 0xe000e404 +#define CYREG_NVIC_PRI_5 0xe000e405 +#define CYREG_NVIC_PRI_6 0xe000e406 +#define CYREG_NVIC_PRI_7 0xe000e407 +#define CYREG_NVIC_PRI_8 0xe000e408 +#define CYREG_NVIC_PRI_9 0xe000e409 +#define CYREG_NVIC_PRI_10 0xe000e40a +#define CYREG_NVIC_PRI_11 0xe000e40b +#define CYREG_NVIC_PRI_12 0xe000e40c +#define CYREG_NVIC_PRI_13 0xe000e40d +#define CYREG_NVIC_PRI_14 0xe000e40e +#define CYREG_NVIC_PRI_15 0xe000e40f +#define CYREG_NVIC_PRI_16 0xe000e410 +#define CYREG_NVIC_PRI_17 0xe000e411 +#define CYREG_NVIC_PRI_18 0xe000e412 +#define CYREG_NVIC_PRI_19 0xe000e413 +#define CYREG_NVIC_PRI_20 0xe000e414 +#define CYREG_NVIC_PRI_21 0xe000e415 +#define CYREG_NVIC_PRI_22 0xe000e416 +#define CYREG_NVIC_PRI_23 0xe000e417 +#define CYREG_NVIC_PRI_24 0xe000e418 +#define CYREG_NVIC_PRI_25 0xe000e419 +#define CYREG_NVIC_PRI_26 0xe000e41a +#define CYREG_NVIC_PRI_27 0xe000e41b +#define CYREG_NVIC_PRI_28 0xe000e41c +#define CYREG_NVIC_PRI_29 0xe000e41d +#define CYREG_NVIC_PRI_30 0xe000e41e +#define CYREG_NVIC_PRI_31 0xe000e41f +#define CYREG_NVIC_CPUID_BASE 0xe000ed00 +#define CYREG_NVIC_INTR_CTRL_STATE 0xe000ed04 +#define CYREG_NVIC_VECT_OFFSET 0xe000ed08 +#define CYREG_NVIC_APPLN_INTR 0xe000ed0c +#define CYREG_NVIC_SYSTEM_CONTROL 0xe000ed10 +#define CYREG_NVIC_CFG_CONTROL 0xe000ed14 +#define CYREG_NVIC_SYS_PRIO_HANDLER_4_7 0xe000ed18 +#define CYREG_NVIC_SYS_PRIO_HANDLER_8_11 0xe000ed1c +#define CYREG_NVIC_SYS_PRIO_HANDLER_12_15 0xe000ed20 +#define CYREG_NVIC_SYS_HANDLER_CSR 0xe000ed24 +#define CYREG_NVIC_MEMMAN_FAULT_STATUS 0xe000ed28 +#define CYREG_NVIC_BUS_FAULT_STATUS 0xe000ed29 +#define CYREG_NVIC_USAGE_FAULT_STATUS 0xe000ed2a +#define CYREG_NVIC_HARD_FAULT_STATUS 0xe000ed2c +#define CYREG_NVIC_DEBUG_FAULT_STATUS 0xe000ed30 +#define CYREG_NVIC_MEMMAN_FAULT_ADD 0xe000ed34 +#define CYREG_NVIC_BUS_FAULT_ADD 0xe000ed38 +#define CYDEV_CORE_DBG_BASE 0xe000edf0 +#define CYDEV_CORE_DBG_SIZE 0x00000010 +#define CYREG_CORE_DBG_DBG_HLT_CS 0xe000edf0 +#define CYREG_CORE_DBG_DBG_REG_SEL 0xe000edf4 +#define CYREG_CORE_DBG_DBG_REG_DATA 0xe000edf8 +#define CYREG_CORE_DBG_EXC_MON_CTL 0xe000edfc +#define CYDEV_TPIU_BASE 0xe0040000 +#define CYDEV_TPIU_SIZE 0x00001000 +#define CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ 0xe0040000 +#define CYREG_TPIU_CURRENT_SYNC_PRT_SZ 0xe0040004 +#define CYREG_TPIU_ASYNC_CLK_PRESCALER 0xe0040010 +#define CYREG_TPIU_PROTOCOL 0xe00400f0 +#define CYREG_TPIU_FORM_FLUSH_STAT 0xe0040300 +#define CYREG_TPIU_FORM_FLUSH_CTRL 0xe0040304 +#define CYREG_TPIU_TRIGGER 0xe0040ee8 +#define CYREG_TPIU_ITETMDATA 0xe0040eec +#define CYREG_TPIU_ITATBCTR2 0xe0040ef0 +#define CYREG_TPIU_ITATBCTR0 0xe0040ef8 +#define CYREG_TPIU_ITITMDATA 0xe0040efc +#define CYREG_TPIU_ITCTRL 0xe0040f00 +#define CYREG_TPIU_DEVID 0xe0040fc8 +#define CYREG_TPIU_DEVTYPE 0xe0040fcc +#define CYREG_TPIU_PID4 0xe0040fd0 +#define CYREG_TPIU_PID5 0xe0040fd4 +#define CYREG_TPIU_PID6 0xe0040fd8 +#define CYREG_TPIU_PID7 0xe0040fdc +#define CYREG_TPIU_PID0 0xe0040fe0 +#define CYREG_TPIU_PID1 0xe0040fe4 +#define CYREG_TPIU_PID2 0xe0040fe8 +#define CYREG_TPIU_PID3 0xe0040fec +#define CYREG_TPIU_CID0 0xe0040ff0 +#define CYREG_TPIU_CID1 0xe0040ff4 +#define CYREG_TPIU_CID2 0xe0040ff8 +#define CYREG_TPIU_CID3 0xe0040ffc +#define CYDEV_ETM_BASE 0xe0041000 +#define CYDEV_ETM_SIZE 0x00001000 +#define CYREG_ETM_CTL 0xe0041000 +#define CYREG_ETM_CFG_CODE 0xe0041004 +#define CYREG_ETM_TRIG_EVENT 0xe0041008 +#define CYREG_ETM_STATUS 0xe0041010 +#define CYREG_ETM_SYS_CFG 0xe0041014 +#define CYREG_ETM_TRACE_ENB_EVENT 0xe0041020 +#define CYREG_ETM_TRACE_EN_CTRL1 0xe0041024 +#define CYREG_ETM_FIFOFULL_LEVEL 0xe004102c +#define CYREG_ETM_SYNC_FREQ 0xe00411e0 +#define CYREG_ETM_ETM_ID 0xe00411e4 +#define CYREG_ETM_CFG_CODE_EXT 0xe00411e8 +#define CYREG_ETM_TR_SS_EMBICE_CTRL 0xe00411f0 +#define CYREG_ETM_CS_TRACE_ID 0xe0041200 +#define CYREG_ETM_OS_LOCK_ACCESS 0xe0041300 +#define CYREG_ETM_OS_LOCK_STATUS 0xe0041304 +#define CYREG_ETM_PDSR 0xe0041314 +#define CYREG_ETM_ITMISCIN 0xe0041ee0 +#define CYREG_ETM_ITTRIGOUT 0xe0041ee8 +#define CYREG_ETM_ITATBCTR2 0xe0041ef0 +#define CYREG_ETM_ITATBCTR0 0xe0041ef8 +#define CYREG_ETM_INT_MODE_CTRL 0xe0041f00 +#define CYREG_ETM_CLM_TAG_SET 0xe0041fa0 +#define CYREG_ETM_CLM_TAG_CLR 0xe0041fa4 +#define CYREG_ETM_LOCK_ACCESS 0xe0041fb0 +#define CYREG_ETM_LOCK_STATUS 0xe0041fb4 +#define CYREG_ETM_AUTH_STATUS 0xe0041fb8 +#define CYREG_ETM_DEV_TYPE 0xe0041fcc +#define CYREG_ETM_PID4 0xe0041fd0 +#define CYREG_ETM_PID5 0xe0041fd4 +#define CYREG_ETM_PID6 0xe0041fd8 +#define CYREG_ETM_PID7 0xe0041fdc +#define CYREG_ETM_PID0 0xe0041fe0 +#define CYREG_ETM_PID1 0xe0041fe4 +#define CYREG_ETM_PID2 0xe0041fe8 +#define CYREG_ETM_PID3 0xe0041fec +#define CYREG_ETM_CID0 0xe0041ff0 +#define CYREG_ETM_CID1 0xe0041ff4 +#define CYREG_ETM_CID2 0xe0041ff8 +#define CYREG_ETM_CID3 0xe0041ffc +#define CYDEV_ROM_TABLE_BASE 0xe00ff000 +#define CYDEV_ROM_TABLE_SIZE 0x00001000 +#define CYREG_ROM_TABLE_NVIC 0xe00ff000 +#define CYREG_ROM_TABLE_DWT 0xe00ff004 +#define CYREG_ROM_TABLE_FPB 0xe00ff008 +#define CYREG_ROM_TABLE_ITM 0xe00ff00c +#define CYREG_ROM_TABLE_TPIU 0xe00ff010 +#define CYREG_ROM_TABLE_ETM 0xe00ff014 +#define CYREG_ROM_TABLE_END 0xe00ff018 +#define CYREG_ROM_TABLE_MEMTYPE 0xe00fffcc +#define CYREG_ROM_TABLE_PID4 0xe00fffd0 +#define CYREG_ROM_TABLE_PID5 0xe00fffd4 +#define CYREG_ROM_TABLE_PID6 0xe00fffd8 +#define CYREG_ROM_TABLE_PID7 0xe00fffdc +#define CYREG_ROM_TABLE_PID0 0xe00fffe0 +#define CYREG_ROM_TABLE_PID1 0xe00fffe4 +#define CYREG_ROM_TABLE_PID2 0xe00fffe8 +#define CYREG_ROM_TABLE_PID3 0xe00fffec +#define CYREG_ROM_TABLE_CID0 0xe00ffff0 +#define CYREG_ROM_TABLE_CID1 0xe00ffff4 +#define CYREG_ROM_TABLE_CID2 0xe00ffff8 +#define CYREG_ROM_TABLE_CID3 0xe00ffffc +#define CYDEV_FLS_SIZE CYDEV_FLASH_SIZE +#define CYDEV_ECC_BASE CYDEV_FLSECC_BASE +#define CYDEV_FLS_SECTOR_SIZE 0x00010000 +#define CYDEV_FLS_ROW_SIZE 0x00000100 +#define CYDEV_ECC_SECTOR_SIZE 0x00002000 +#define CYDEV_ECC_ROW_SIZE 0x00000020 +#define CYDEV_EEPROM_SECTOR_SIZE 0x00000400 +#define CYDEV_EEPROM_ROW_SIZE 0x00000010 +#define CYDEV_PERIPH_BASE CYDEV_CLKDIST_BASE +#define CYCLK_LD_DISABLE 0x00000004 +#define CYCLK_LD_SYNC_EN 0x00000002 +#define CYCLK_LD_LOAD 0x00000001 +#define CYCLK_PIPE 0x00000080 +#define CYCLK_SSS 0x00000040 +#define CYCLK_EARLY 0x00000020 +#define CYCLK_DUTY 0x00000010 +#define CYCLK_SYNC 0x00000008 +#define CYCLK_SRC_SEL_CLK_SYNC_D 0 +#define CYCLK_SRC_SEL_SYNC_DIG 0 +#define CYCLK_SRC_SEL_IMO 1 +#define CYCLK_SRC_SEL_XTAL_MHZ 2 +#define CYCLK_SRC_SEL_XTALM 2 +#define CYCLK_SRC_SEL_ILO 3 +#define CYCLK_SRC_SEL_PLL 4 +#define CYCLK_SRC_SEL_XTAL_KHZ 5 +#define CYCLK_SRC_SEL_XTALK 5 +#define CYCLK_SRC_SEL_DSI_G 6 +#define CYCLK_SRC_SEL_DSI_D 7 +#define CYCLK_SRC_SEL_CLK_SYNC_A 0 +#define CYCLK_SRC_SEL_DSI_A 7 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc new file mode 100644 index 0000000..cff336b --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv.inc @@ -0,0 +1,16039 @@ +; +; File Name: cydevicerv.inc +; OBSOLETE: Do not use this file. Use the _trm version instead. +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MBASE +CYDEV_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_DATA_MSIZE +CYDEV_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MBASE +CYDEV_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE64K_MSIZE +CYDEV_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MBASE +CYDEV_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE32K_MSIZE +CYDEV_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MBASE +CYDEV_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE16K_MSIZE +CYDEV_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MBASE +CYDEV_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_CODE_MSIZE +CYDEV_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MBASE +CYDEV_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA_MSIZE +CYDEV_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MBASE +CYDEV_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA16K_MSIZE +CYDEV_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MBASE +CYDEV_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA32K_MSIZE +CYDEV_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MBASE +CYDEV_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_DATA64K_MSIZE +CYDEV_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MBASE +CYDEV_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM64K_MSIZE +CYDEV_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MBASE +CYDEV_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM32K_MSIZE +CYDEV_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MBASE +CYDEV_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM16K_MSIZE +CYDEV_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MBASE +CYDEV_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SRAM_MSIZE +CYDEV_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_CR +CYDEV_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_LD +CYDEV_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK0 +CYDEV_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_WRK1 +CYDEV_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR0 +CYDEV_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_MSTR1 +CYDEV_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG0 +CYDEV_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG1 +CYDEV_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BCFG2 +CYDEV_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_UCFG +CYDEV_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY0 +CYDEV_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DLY1 +CYDEV_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DMASK +CYDEV_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_AMASK +CYDEV_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG0 +CYDEV_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG1 +CYDEV_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_CFG2 +CYDEV_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG0 +CYDEV_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG1 +CYDEV_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_CFG2 +CYDEV_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG0 +CYDEV_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG1 +CYDEV_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_CFG2 +CYDEV_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG0 +CYDEV_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG1 +CYDEV_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_CFG2 +CYDEV_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG0 +CYDEV_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG1 +CYDEV_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_CFG2 +CYDEV_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG0 +CYDEV_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG1 +CYDEV_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_CFG2 +CYDEV_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG0 +CYDEV_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG1 +CYDEV_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_CFG2 +CYDEV_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG0 +CYDEV_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG1 +CYDEV_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_CFG2 +CYDEV_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG0 +CYDEV_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG1 +CYDEV_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG2 +CYDEV_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_CFG3 +CYDEV_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG0 +CYDEV_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG1 +CYDEV_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG2 +CYDEV_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_CFG3 +CYDEV_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG0 +CYDEV_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG1 +CYDEV_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG2 +CYDEV_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_CFG3 +CYDEV_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG0 +CYDEV_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG1 +CYDEV_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG2 +CYDEV_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_CFG3 +CYDEV_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_CR +CYDEV_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CSR +CYDEV_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG0 +CYDEV_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_CFG1 +CYDEV_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG0 +CYDEV_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_CFG1 +CYDEV_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_P +CYDEV_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_Q +CYDEV_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SR +CYDEV_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR0 +CYDEV_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_CR1 +CYDEV_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CR +CYDEV_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_CFG +CYDEV_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_TST +CYDEV_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR0 +CYDEV_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR1 +CYDEV_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR2 +CYDEV_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR3 +CYDEV_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR +CYDEV_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_CR4 +CYDEV_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SR2 +CYDEV_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR0 +CYDEV_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_CR1 +CYDEV_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG0 +CYDEV_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG1 +CYDEV_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYDEV_PM_TW_CFG2 +CYDEV_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CFG +CYDEV_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WDT_CR +CYDEV_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYDEV_PM_INT_SR +CYDEV_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG0 +CYDEV_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CFG1 +CYDEV_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYDEV_PM_MODE_CSR +CYDEV_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYDEV_PM_USB_CR0 +CYDEV_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG0 +CYDEV_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG1 +CYDEV_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYDEV_PM_WAKEUP_CFG2 +CYDEV_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG0 +CYDEV_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG1 +CYDEV_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG2 +CYDEV_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG3 +CYDEV_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG4 +CYDEV_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG5 +CYDEV_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG6 +CYDEV_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG7 +CYDEV_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG8 +CYDEV_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG9 +CYDEV_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG10 +CYDEV_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG11 +CYDEV_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG12 +CYDEV_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_CFG13 +CYDEV_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG0 +CYDEV_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG1 +CYDEV_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG2 +CYDEV_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG3 +CYDEV_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG4 +CYDEV_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG5 +CYDEV_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG6 +CYDEV_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG7 +CYDEV_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG8 +CYDEV_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG9 +CYDEV_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG10 +CYDEV_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG11 +CYDEV_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG12 +CYDEV_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_CFG13 +CYDEV_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR0 +CYDEV_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR1 +CYDEV_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR2 +CYDEV_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR3 +CYDEV_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR4 +CYDEV_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR5 +CYDEV_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_CR6 +CYDEV_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR0 +CYDEV_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR1 +CYDEV_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR2 +CYDEV_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR3 +CYDEV_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR4 +CYDEV_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR5 +CYDEV_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SR6 +CYDEV_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 +CYDEV_PICU_INTTYPE_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_INTSTAT +CYDEV_PICU_STAT_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_INTSTAT +CYDEV_PICU_STAT_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_INTSTAT +CYDEV_PICU_STAT_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_INTSTAT +CYDEV_PICU_STAT_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_INTSTAT +CYDEV_PICU_STAT_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_INTSTAT +CYDEV_PICU_STAT_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_INTSTAT +CYDEV_PICU_STAT_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_INTSTAT +CYDEV_PICU_STAT_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_INTSTAT +CYDEV_PICU_STAT_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SNAP +CYDEV_PICU_SNAP_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SNAP +CYDEV_PICU_SNAP_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SNAP +CYDEV_PICU_SNAP_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SNAP +CYDEV_PICU_SNAP_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SNAP +CYDEV_PICU_SNAP_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SNAP +CYDEV_PICU_SNAP_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SNAP +CYDEV_PICU_SNAP_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SNAP +CYDEV_PICU_SNAP_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SNAP_15 +CYDEV_PICU_SNAP_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR +CYDEV_PICU_DISABLE_COR_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_TR +CYDEV_MFGCFG_ANAIF_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_TR +CYDEV_MFGCFG_ANAIF_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_TR +CYDEV_MFGCFG_ANAIF_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_TR +CYDEV_MFGCFG_ANAIF_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_TR0 +CYDEV_MFGCFG_ANAIF_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_TR0 +CYDEV_MFGCFG_ANAIF_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 +CYDEV_MFGCFG_ANAIF_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR0 +CYDEV_MFGCFG_ANAIF_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_TR1 +CYDEV_MFGCFG_ANAIF_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR0 +CYDEV_MFGCFG_ANAIF_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_TR1 +CYDEV_MFGCFG_ANAIF_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR0 +CYDEV_MFGCFG_ANAIF_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_TR1 +CYDEV_MFGCFG_ANAIF_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR0 +CYDEV_MFGCFG_ANAIF_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_TR1 +CYDEV_MFGCFG_ANAIF_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR0 +CYDEV_MFGCFG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_HIB_TR1 +CYDEV_MFGCFG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_I2C_TR +CYDEV_MFGCFG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SLP_TR +CYDEV_MFGCFG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BUZZ_TR +CYDEV_MFGCFG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR0 +CYDEV_MFGCFG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR1 +CYDEV_MFGCFG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BREF_TR +CYDEV_MFGCFG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BG_TR +CYDEV_MFGCFG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR2 +CYDEV_MFGCFG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_WAKE_TR3 +CYDEV_MFGCFG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR0 +CYDEV_MFGCFG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_TR1 +CYDEV_MFGCFG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_TR +CYDEV_MFGCFG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR0 +CYDEV_MFGCFG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR1 +CYDEV_MFGCFG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_GAIN +CYDEV_MFGCFG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_C36M +CYDEV_MFGCFG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_TR2 +CYDEV_MFGCFG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_TR +CYDEV_MFGCFG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_DLY +CYDEV_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DMPSTR +CYDEV_MFGCFG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CR +CYDEV_MFGCFG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_CFG0 +CYDEV_MFGCFG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_DEBUG +CYDEV_MFGCFG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR +CYDEV_MFGCFG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_REV_ID +CYDEV_MFGCFG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR0 +CYDEV_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR1 +CYDEV_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR2 +CYDEV_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_IPOR_CR3 +CYDEV_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR0 +CYDEV_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR1 +CYDEV_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR2 +CYDEV_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR3 +CYDEV_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR4 +CYDEV_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_CR5 +CYDEV_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR0 +CYDEV_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR1 +CYDEV_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR2 +CYDEV_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SR3 +CYDEV_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYDEV_RESET_TR +CYDEV_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_CR +CYDEV_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_FM_EE_WAKE_CNT +CYDEV_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_SCR +CYDEV_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_EE_ERR +CYDEV_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CPU_DATA +CYDEV_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMA_DATA +CYDEV_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SR +CYDEV_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_CR +CYDEV_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MBASE +CYDEV_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SRAM_MSIZE +CYDEV_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_CC_CTL +CYDEV_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_CORR +CYDEV_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_ECC_ERR +CYDEV_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_FLASH_ERR +CYDEV_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_HITMISS +CYDEV_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_XCFG +CYDEV_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_ADR +CYDEV_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CFG +CYDEV_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CSR +CYDEV_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_D +CYDEV_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_MCSR +CYDEV_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV1 +CYDEV_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYDEV_I2C_CLK_DIV2 +CYDEV_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CSR +CYDEV_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_SR +CYDEV_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG0 +CYDEV_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYDEV_I2C_TMOUT_CFG1 +CYDEV_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_CR +CYDEV_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SR +CYDEV_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT1 +CYDEV_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SHIFT2 +CYDEV_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2 +CYDEV_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR2H +CYDEV_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_DR1 +CYDEV_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCOR +CYDEV_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORM +CYDEV_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OCORH +CYDEV_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCOR +CYDEV_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GCORH +CYDEV_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYDEV_DEC_GVAL +CYDEV_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMP +CYDEV_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPM +CYDEV_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPH +CYDEV_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_OUTSAMPS +CYDEV_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_COHER +CYDEV_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG0 +CYDEV_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG1 +CYDEV_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CFG2 +CYDEV_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SR0 +CYDEV_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER0 +CYDEV_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_PER1 +CYDEV_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP0 +CYDEV_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CNT_CMP1 +CYDEV_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP0 +CYDEV_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_CAP1 +CYDEV_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT0 +CYDEV_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_RT1 +CYDEV_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG0 +CYDEV_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG1 +CYDEV_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CFG2 +CYDEV_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SR0 +CYDEV_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER0 +CYDEV_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_PER1 +CYDEV_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP0 +CYDEV_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CNT_CMP1 +CYDEV_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP0 +CYDEV_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_CAP1 +CYDEV_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT0 +CYDEV_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_RT1 +CYDEV_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG0 +CYDEV_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG1 +CYDEV_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CFG2 +CYDEV_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SR0 +CYDEV_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER0 +CYDEV_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_PER1 +CYDEV_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP0 +CYDEV_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CNT_CMP1 +CYDEV_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP0 +CYDEV_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_CAP1 +CYDEV_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT0 +CYDEV_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_RT1 +CYDEV_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG0 +CYDEV_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG1 +CYDEV_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CFG2 +CYDEV_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SR0 +CYDEV_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER0 +CYDEV_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_PER1 +CYDEV_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP0 +CYDEV_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CNT_CMP1 +CYDEV_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP0 +CYDEV_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_CAP1 +CYDEV_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT0 +CYDEV_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_RT1 +CYDEV_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC0 +CYDEV_IO_PC_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC1 +CYDEV_IO_PC_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC2 +CYDEV_IO_PC_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC3 +CYDEV_IO_PC_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC4 +CYDEV_IO_PC_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC5 +CYDEV_IO_PC_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC6 +CYDEV_IO_PC_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_PC7 +CYDEV_IO_PC_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC0 +CYDEV_IO_PC_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC1 +CYDEV_IO_PC_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC2 +CYDEV_IO_PC_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC3 +CYDEV_IO_PC_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC4 +CYDEV_IO_PC_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC5 +CYDEV_IO_PC_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC6 +CYDEV_IO_PC_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_PC7 +CYDEV_IO_PC_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC0 +CYDEV_IO_PC_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC1 +CYDEV_IO_PC_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC2 +CYDEV_IO_PC_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC3 +CYDEV_IO_PC_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC4 +CYDEV_IO_PC_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC5 +CYDEV_IO_PC_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC6 +CYDEV_IO_PC_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_PC7 +CYDEV_IO_PC_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC0 +CYDEV_IO_PC_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC1 +CYDEV_IO_PC_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC2 +CYDEV_IO_PC_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC3 +CYDEV_IO_PC_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC4 +CYDEV_IO_PC_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC5 +CYDEV_IO_PC_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC6 +CYDEV_IO_PC_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_PC7 +CYDEV_IO_PC_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC0 +CYDEV_IO_PC_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC1 +CYDEV_IO_PC_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC2 +CYDEV_IO_PC_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC3 +CYDEV_IO_PC_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC4 +CYDEV_IO_PC_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC5 +CYDEV_IO_PC_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC6 +CYDEV_IO_PC_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_PC7 +CYDEV_IO_PC_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC0 +CYDEV_IO_PC_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC1 +CYDEV_IO_PC_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC2 +CYDEV_IO_PC_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC3 +CYDEV_IO_PC_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC4 +CYDEV_IO_PC_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC5 +CYDEV_IO_PC_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC6 +CYDEV_IO_PC_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_PC7 +CYDEV_IO_PC_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC0 +CYDEV_IO_PC_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC1 +CYDEV_IO_PC_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC2 +CYDEV_IO_PC_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC3 +CYDEV_IO_PC_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC4 +CYDEV_IO_PC_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC5 +CYDEV_IO_PC_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC6 +CYDEV_IO_PC_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_PC7 +CYDEV_IO_PC_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC0 +CYDEV_IO_PC_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC1 +CYDEV_IO_PC_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC2 +CYDEV_IO_PC_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC3 +CYDEV_IO_PC_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC4 +CYDEV_IO_PC_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC5 +CYDEV_IO_PC_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC6 +CYDEV_IO_PC_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_PC7 +CYDEV_IO_PC_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC0 +CYDEV_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC1 +CYDEV_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC2 +CYDEV_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC3 +CYDEV_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC4 +CYDEV_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_PC5 +CYDEV_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC0 +CYDEV_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_PC1 +CYDEV_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_DR_ALIAS +CYDEV_IO_DR_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_DR_ALIAS +CYDEV_IO_DR_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_DR_ALIAS +CYDEV_IO_DR_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_DR_ALIAS +CYDEV_IO_DR_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_DR_ALIAS +CYDEV_IO_DR_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_DR_ALIAS +CYDEV_IO_DR_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_DR_ALIAS +CYDEV_IO_DR_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_DR_ALIAS +CYDEV_IO_DR_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_DR_15_ALIAS +CYDEV_IO_DR_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_PS_ALIAS +CYDEV_IO_PS_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_PS_ALIAS +CYDEV_IO_PS_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_PS_ALIAS +CYDEV_IO_PS_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_PS_ALIAS +CYDEV_IO_PS_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_PS_ALIAS +CYDEV_IO_PS_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_PS_ALIAS +CYDEV_IO_PS_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_PS_ALIAS +CYDEV_IO_PS_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_PS_ALIAS +CYDEV_IO_PS_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_PS15_ALIAS +CYDEV_IO_PS_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DR +CYDEV_IO_PRT_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PS +CYDEV_IO_PRT_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM0 +CYDEV_IO_PRT_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM1 +CYDEV_IO_PRT_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_DM2 +CYDEV_IO_PRT_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SLW +CYDEV_IO_PRT_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BYP +CYDEV_IO_PRT_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIE +CYDEV_IO_PRT_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_INP_DIS +CYDEV_IO_PRT_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_CTL +CYDEV_IO_PRT_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_PRT +CYDEV_IO_PRT_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BIT_MASK +CYDEV_IO_PRT_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AMUX +CYDEV_IO_PRT_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_AG +CYDEV_IO_PRT_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_COM_SEG +CYDEV_IO_PRT_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_LCD_EN +CYDEV_IO_PRT_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DR +CYDEV_IO_PRT_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PS +CYDEV_IO_PRT_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM0 +CYDEV_IO_PRT_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM1 +CYDEV_IO_PRT_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_DM2 +CYDEV_IO_PRT_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SLW +CYDEV_IO_PRT_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BYP +CYDEV_IO_PRT_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIE +CYDEV_IO_PRT_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_INP_DIS +CYDEV_IO_PRT_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_CTL +CYDEV_IO_PRT_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_PRT +CYDEV_IO_PRT_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BIT_MASK +CYDEV_IO_PRT_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AMUX +CYDEV_IO_PRT_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_AG +CYDEV_IO_PRT_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_COM_SEG +CYDEV_IO_PRT_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_LCD_EN +CYDEV_IO_PRT_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DR +CYDEV_IO_PRT_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PS +CYDEV_IO_PRT_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM0 +CYDEV_IO_PRT_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM1 +CYDEV_IO_PRT_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_DM2 +CYDEV_IO_PRT_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SLW +CYDEV_IO_PRT_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BYP +CYDEV_IO_PRT_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIE +CYDEV_IO_PRT_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_INP_DIS +CYDEV_IO_PRT_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_CTL +CYDEV_IO_PRT_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_PRT +CYDEV_IO_PRT_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BIT_MASK +CYDEV_IO_PRT_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AMUX +CYDEV_IO_PRT_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_AG +CYDEV_IO_PRT_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_COM_SEG +CYDEV_IO_PRT_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_LCD_EN +CYDEV_IO_PRT_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DR +CYDEV_IO_PRT_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PS +CYDEV_IO_PRT_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM0 +CYDEV_IO_PRT_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM1 +CYDEV_IO_PRT_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_DM2 +CYDEV_IO_PRT_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SLW +CYDEV_IO_PRT_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BYP +CYDEV_IO_PRT_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIE +CYDEV_IO_PRT_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_INP_DIS +CYDEV_IO_PRT_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_CTL +CYDEV_IO_PRT_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_PRT +CYDEV_IO_PRT_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BIT_MASK +CYDEV_IO_PRT_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AMUX +CYDEV_IO_PRT_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_AG +CYDEV_IO_PRT_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_COM_SEG +CYDEV_IO_PRT_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_LCD_EN +CYDEV_IO_PRT_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DR +CYDEV_IO_PRT_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PS +CYDEV_IO_PRT_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM0 +CYDEV_IO_PRT_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM1 +CYDEV_IO_PRT_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_DM2 +CYDEV_IO_PRT_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SLW +CYDEV_IO_PRT_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BYP +CYDEV_IO_PRT_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIE +CYDEV_IO_PRT_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_INP_DIS +CYDEV_IO_PRT_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_CTL +CYDEV_IO_PRT_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_PRT +CYDEV_IO_PRT_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BIT_MASK +CYDEV_IO_PRT_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AMUX +CYDEV_IO_PRT_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_AG +CYDEV_IO_PRT_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_COM_SEG +CYDEV_IO_PRT_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_LCD_EN +CYDEV_IO_PRT_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DR +CYDEV_IO_PRT_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PS +CYDEV_IO_PRT_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM0 +CYDEV_IO_PRT_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM1 +CYDEV_IO_PRT_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_DM2 +CYDEV_IO_PRT_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SLW +CYDEV_IO_PRT_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BYP +CYDEV_IO_PRT_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIE +CYDEV_IO_PRT_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_INP_DIS +CYDEV_IO_PRT_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_CTL +CYDEV_IO_PRT_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_PRT +CYDEV_IO_PRT_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BIT_MASK +CYDEV_IO_PRT_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AMUX +CYDEV_IO_PRT_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_AG +CYDEV_IO_PRT_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_COM_SEG +CYDEV_IO_PRT_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_LCD_EN +CYDEV_IO_PRT_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DR +CYDEV_IO_PRT_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PS +CYDEV_IO_PRT_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM0 +CYDEV_IO_PRT_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM1 +CYDEV_IO_PRT_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_DM2 +CYDEV_IO_PRT_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SLW +CYDEV_IO_PRT_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BYP +CYDEV_IO_PRT_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIE +CYDEV_IO_PRT_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_INP_DIS +CYDEV_IO_PRT_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_CTL +CYDEV_IO_PRT_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_PRT +CYDEV_IO_PRT_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BIT_MASK +CYDEV_IO_PRT_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AMUX +CYDEV_IO_PRT_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_AG +CYDEV_IO_PRT_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_COM_SEG +CYDEV_IO_PRT_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_LCD_EN +CYDEV_IO_PRT_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DR +CYDEV_IO_PRT_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PS +CYDEV_IO_PRT_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM0 +CYDEV_IO_PRT_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM1 +CYDEV_IO_PRT_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_DM2 +CYDEV_IO_PRT_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SLW +CYDEV_IO_PRT_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BYP +CYDEV_IO_PRT_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIE +CYDEV_IO_PRT_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_INP_DIS +CYDEV_IO_PRT_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_HYST_EN +CYDEV_IO_PRT_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_PRT +CYDEV_IO_PRT_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BIT_MASK +CYDEV_IO_PRT_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ +CYDEV_IO_PRT_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_AG +CYDEV_IO_PRT_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_CFG +CYDEV_IO_PRT_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIO_DIFF +CYDEV_IO_PRT_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DR +CYDEV_IO_PRT_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PS +CYDEV_IO_PRT_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM0 +CYDEV_IO_PRT_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM1 +CYDEV_IO_PRT_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_DM2 +CYDEV_IO_PRT_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SLW +CYDEV_IO_PRT_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BYP +CYDEV_IO_PRT_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIE +CYDEV_IO_PRT_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_INP_DIS +CYDEV_IO_PRT_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_CTL +CYDEV_IO_PRT_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_PRT +CYDEV_IO_PRT_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BIT_MASK +CYDEV_IO_PRT_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AMUX +CYDEV_IO_PRT_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_AG +CYDEV_IO_PRT_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_COM_SEG +CYDEV_IO_PRT_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_LCD_EN +CYDEV_IO_PRT_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL0 +CYDEV_PRTDSI_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OUT_SEL1 +CYDEV_PRTDSI_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL0 +CYDEV_PRTDSI_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_OE_SEL1 +CYDEV_PRTDSI_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_DBL_SYNC_IN +CYDEV_PRTDSI_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SYNC_OUT +CYDEV_PRTDSI_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_CAPS_SEL +CYDEV_PRTDSI_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL0 +CYDEV_PRTDSI_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OUT_SEL1 +CYDEV_PRTDSI_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL0 +CYDEV_PRTDSI_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_OE_SEL1 +CYDEV_PRTDSI_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_DBL_SYNC_IN +CYDEV_PRTDSI_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SYNC_OUT +CYDEV_PRTDSI_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_CAPS_SEL +CYDEV_PRTDSI_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL0 +CYDEV_PRTDSI_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OUT_SEL1 +CYDEV_PRTDSI_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL0 +CYDEV_PRTDSI_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_OE_SEL1 +CYDEV_PRTDSI_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_DBL_SYNC_IN +CYDEV_PRTDSI_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SYNC_OUT +CYDEV_PRTDSI_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_CAPS_SEL +CYDEV_PRTDSI_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL0 +CYDEV_PRTDSI_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OUT_SEL1 +CYDEV_PRTDSI_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL0 +CYDEV_PRTDSI_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_OE_SEL1 +CYDEV_PRTDSI_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_DBL_SYNC_IN +CYDEV_PRTDSI_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SYNC_OUT +CYDEV_PRTDSI_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_CAPS_SEL +CYDEV_PRTDSI_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL0 +CYDEV_PRTDSI_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OUT_SEL1 +CYDEV_PRTDSI_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL0 +CYDEV_PRTDSI_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_OE_SEL1 +CYDEV_PRTDSI_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_DBL_SYNC_IN +CYDEV_PRTDSI_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SYNC_OUT +CYDEV_PRTDSI_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_CAPS_SEL +CYDEV_PRTDSI_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL0 +CYDEV_PRTDSI_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OUT_SEL1 +CYDEV_PRTDSI_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL0 +CYDEV_PRTDSI_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_OE_SEL1 +CYDEV_PRTDSI_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_DBL_SYNC_IN +CYDEV_PRTDSI_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SYNC_OUT +CYDEV_PRTDSI_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_CAPS_SEL +CYDEV_PRTDSI_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL0 +CYDEV_PRTDSI_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OUT_SEL1 +CYDEV_PRTDSI_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL0 +CYDEV_PRTDSI_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_OE_SEL1 +CYDEV_PRTDSI_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_DBL_SYNC_IN +CYDEV_PRTDSI_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SYNC_OUT +CYDEV_PRTDSI_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_CAPS_SEL +CYDEV_PRTDSI_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL0 +CYDEV_PRTDSI_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OUT_SEL1 +CYDEV_PRTDSI_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL0 +CYDEV_PRTDSI_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_OE_SEL1 +CYDEV_PRTDSI_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_DBL_SYNC_IN +CYDEV_PRTDSI_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SYNC_OUT +CYDEV_PRTDSI_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL0 +CYDEV_PRTDSI_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OUT_SEL1 +CYDEV_PRTDSI_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL0 +CYDEV_PRTDSI_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_OE_SEL1 +CYDEV_PRTDSI_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_DBL_SYNC_IN +CYDEV_PRTDSI_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SYNC_OUT +CYDEV_PRTDSI_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_CAPS_SEL +CYDEV_PRTDSI_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_NO_UDB +CYDEV_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_RP_WAIT_STATES +CYDEV_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEM_DWN +CYDEV_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_MEMCLK_DIV +CYDEV_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_CLOCK_EN +CYDEV_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_EM_TYPE +CYDEV_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_WP_WAIT_STATES +CYDEV_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR0 +CYDEV_ANAIF_CFG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR1 +CYDEV_ANAIF_CFG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_CR2 +CYDEV_ANAIF_CFG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR0 +CYDEV_ANAIF_CFG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR1 +CYDEV_ANAIF_CFG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_CR2 +CYDEV_ANAIF_CFG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR0 +CYDEV_ANAIF_CFG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR1 +CYDEV_ANAIF_CFG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_CR2 +CYDEV_ANAIF_CFG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR0 +CYDEV_ANAIF_CFG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR1 +CYDEV_ANAIF_CFG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_CR2 +CYDEV_ANAIF_CFG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR0 +CYDEV_ANAIF_CFG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_CR1 +CYDEV_ANAIF_CFG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_TST +CYDEV_ANAIF_CFG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR0 +CYDEV_ANAIF_CFG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_CR1 +CYDEV_ANAIF_CFG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_TST +CYDEV_ANAIF_CFG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR0 +CYDEV_ANAIF_CFG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_CR1 +CYDEV_ANAIF_CFG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_TST +CYDEV_ANAIF_CFG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR0 +CYDEV_ANAIF_CFG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_CR1 +CYDEV_ANAIF_CFG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_TST +CYDEV_ANAIF_CFG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_CR +CYDEV_ANAIF_CFG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_CR +CYDEV_ANAIF_CFG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_CR +CYDEV_ANAIF_CFG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_CR +CYDEV_ANAIF_CFG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_CR +CYDEV_ANAIF_CFG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_MX +CYDEV_ANAIF_CFG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_CR +CYDEV_ANAIF_CFG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_MX +CYDEV_ANAIF_CFG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_CR +CYDEV_ANAIF_CFG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_MX +CYDEV_ANAIF_CFG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_CR +CYDEV_ANAIF_CFG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_MX +CYDEV_ANAIF_CFG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_CR +CYDEV_ANAIF_CFG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_RSVD +CYDEV_ANAIF_CFG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_CR +CYDEV_ANAIF_CFG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_RSVD +CYDEV_ANAIF_CFG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_CR +CYDEV_ANAIF_CFG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_RSVD +CYDEV_ANAIF_CFG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_CR +CYDEV_ANAIF_CFG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_RSVD +CYDEV_ANAIF_CFG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR0 +CYDEV_ANAIF_CFG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_CR1 +CYDEV_ANAIF_CFG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_CR +CYDEV_ANAIF_CFG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_CFG +CYDEV_ANAIF_CFG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_CR0 +CYDEV_ANAIF_CFG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_RSVD +CYDEV_ANAIF_CFG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT0 +CYDEV_ANAIF_CFG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_DFT1 +CYDEV_ANAIF_CFG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG0 +CYDEV_ANAIF_CFG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_CFG1 +CYDEV_ANAIF_CFG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG0 +CYDEV_ANAIF_CFG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_CFG1 +CYDEV_ANAIF_CFG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR0 +CYDEV_ANAIF_CFG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_CR1 +CYDEV_ANAIF_CFG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_CR0 +CYDEV_ANAIF_CFG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_RSVD +CYDEV_ANAIF_CFG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_CR0 +CYDEV_ANAIF_CFG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_RSVD +CYDEV_ANAIF_CFG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_CR0 +CYDEV_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR0 +CYDEV_ANAIF_CFG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR1 +CYDEV_ANAIF_CFG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR2 +CYDEV_ANAIF_CFG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR3 +CYDEV_ANAIF_CFG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR4 +CYDEV_ANAIF_CFG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR5 +CYDEV_ANAIF_CFG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR6 +CYDEV_ANAIF_CFG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR7 +CYDEV_ANAIF_CFG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR8 +CYDEV_ANAIF_CFG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR9 +CYDEV_ANAIF_CFG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR10 +CYDEV_ANAIF_CFG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR11 +CYDEV_ANAIF_CFG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR12 +CYDEV_ANAIF_CFG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR13 +CYDEV_ANAIF_CFG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR14 +CYDEV_ANAIF_CFG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR15 +CYDEV_ANAIF_CFG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR16 +CYDEV_ANAIF_CFG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_CR17 +CYDEV_ANAIF_CFG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF0 +CYDEV_ANAIF_CFG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF1 +CYDEV_ANAIF_CFG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF2 +CYDEV_ANAIF_CFG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_REF3 +CYDEV_ANAIF_CFG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM0 +CYDEV_ANAIF_CFG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_DEM1 +CYDEV_ANAIF_CFG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST0 +CYDEV_ANAIF_CFG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_TST1 +CYDEV_ANAIF_CFG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF0 +CYDEV_ANAIF_CFG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF1 +CYDEV_ANAIF_CFG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF2 +CYDEV_ANAIF_CFG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BUF3 +CYDEV_ANAIF_CFG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_MISC +CYDEV_ANAIF_CFG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_RSVD1 +CYDEV_ANAIF_CFG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR0 +CYDEV_ANAIF_CFG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR1 +CYDEV_ANAIF_CFG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR2 +CYDEV_ANAIF_CFG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR3 +CYDEV_ANAIF_CFG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR4 +CYDEV_ANAIF_CFG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR5 +CYDEV_ANAIF_CFG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_CSR6 +CYDEV_ANAIF_CFG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR0 +CYDEV_ANAIF_CFG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR1 +CYDEV_ANAIF_CFG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR2 +CYDEV_ANAIF_CFG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR3 +CYDEV_ANAIF_CFG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR4 +CYDEV_ANAIF_CFG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR5 +CYDEV_ANAIF_CFG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_CSR6 +CYDEV_ANAIF_CFG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW0 +CYDEV_ANAIF_RT_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW2 +CYDEV_ANAIF_RT_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW3 +CYDEV_ANAIF_RT_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW4 +CYDEV_ANAIF_RT_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW6 +CYDEV_ANAIF_RT_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW7 +CYDEV_ANAIF_RT_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW8 +CYDEV_ANAIF_RT_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SW10 +CYDEV_ANAIF_RT_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_CLK +CYDEV_ANAIF_RT_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BST +CYDEV_ANAIF_RT_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW0 +CYDEV_ANAIF_RT_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW2 +CYDEV_ANAIF_RT_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW3 +CYDEV_ANAIF_RT_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW4 +CYDEV_ANAIF_RT_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW6 +CYDEV_ANAIF_RT_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW7 +CYDEV_ANAIF_RT_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW8 +CYDEV_ANAIF_RT_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SW10 +CYDEV_ANAIF_RT_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_CLK +CYDEV_ANAIF_RT_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BST +CYDEV_ANAIF_RT_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW0 +CYDEV_ANAIF_RT_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW2 +CYDEV_ANAIF_RT_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW3 +CYDEV_ANAIF_RT_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW4 +CYDEV_ANAIF_RT_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW6 +CYDEV_ANAIF_RT_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW7 +CYDEV_ANAIF_RT_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW8 +CYDEV_ANAIF_RT_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SW10 +CYDEV_ANAIF_RT_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_CLK +CYDEV_ANAIF_RT_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BST +CYDEV_ANAIF_RT_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW0 +CYDEV_ANAIF_RT_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW2 +CYDEV_ANAIF_RT_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW3 +CYDEV_ANAIF_RT_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW4 +CYDEV_ANAIF_RT_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW6 +CYDEV_ANAIF_RT_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW7 +CYDEV_ANAIF_RT_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW8 +CYDEV_ANAIF_RT_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SW10 +CYDEV_ANAIF_RT_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_CLK +CYDEV_ANAIF_RT_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BST +CYDEV_ANAIF_RT_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW0 +CYDEV_ANAIF_RT_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW2 +CYDEV_ANAIF_RT_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW3 +CYDEV_ANAIF_RT_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SW4 +CYDEV_ANAIF_RT_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_STROBE +CYDEV_ANAIF_RT_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW0 +CYDEV_ANAIF_RT_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW2 +CYDEV_ANAIF_RT_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW3 +CYDEV_ANAIF_RT_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SW4 +CYDEV_ANAIF_RT_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_STROBE +CYDEV_ANAIF_RT_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW0 +CYDEV_ANAIF_RT_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW2 +CYDEV_ANAIF_RT_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW3 +CYDEV_ANAIF_RT_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SW4 +CYDEV_ANAIF_RT_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_STROBE +CYDEV_ANAIF_RT_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW0 +CYDEV_ANAIF_RT_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW2 +CYDEV_ANAIF_RT_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW3 +CYDEV_ANAIF_RT_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SW4 +CYDEV_ANAIF_RT_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_STROBE +CYDEV_ANAIF_RT_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW0 +CYDEV_ANAIF_RT_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW2 +CYDEV_ANAIF_RT_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW3 +CYDEV_ANAIF_RT_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW4 +CYDEV_ANAIF_RT_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SW6 +CYDEV_ANAIF_RT_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_CLK +CYDEV_ANAIF_RT_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW0 +CYDEV_ANAIF_RT_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW2 +CYDEV_ANAIF_RT_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW3 +CYDEV_ANAIF_RT_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW4 +CYDEV_ANAIF_RT_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SW6 +CYDEV_ANAIF_RT_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_CLK +CYDEV_ANAIF_RT_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW0 +CYDEV_ANAIF_RT_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW2 +CYDEV_ANAIF_RT_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW3 +CYDEV_ANAIF_RT_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW4 +CYDEV_ANAIF_RT_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SW6 +CYDEV_ANAIF_RT_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_CLK +CYDEV_ANAIF_RT_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW0 +CYDEV_ANAIF_RT_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW2 +CYDEV_ANAIF_RT_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW3 +CYDEV_ANAIF_RT_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW4 +CYDEV_ANAIF_RT_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SW6 +CYDEV_ANAIF_RT_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_CLK +CYDEV_ANAIF_RT_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW0 +CYDEV_ANAIF_RT_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW2 +CYDEV_ANAIF_RT_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW3 +CYDEV_ANAIF_RT_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW4 +CYDEV_ANAIF_RT_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SW6 +CYDEV_ANAIF_RT_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_CLK +CYDEV_ANAIF_RT_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW0 +CYDEV_ANAIF_RT_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW2 +CYDEV_ANAIF_RT_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW3 +CYDEV_ANAIF_RT_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW4 +CYDEV_ANAIF_RT_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SW6 +CYDEV_ANAIF_RT_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_CLK +CYDEV_ANAIF_RT_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW0 +CYDEV_ANAIF_RT_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW2 +CYDEV_ANAIF_RT_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW3 +CYDEV_ANAIF_RT_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW4 +CYDEV_ANAIF_RT_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SW6 +CYDEV_ANAIF_RT_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_CLK +CYDEV_ANAIF_RT_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_MX +CYDEV_ANAIF_RT_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SW +CYDEV_ANAIF_RT_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_MX +CYDEV_ANAIF_RT_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SW +CYDEV_ANAIF_RT_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_MX +CYDEV_ANAIF_RT_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SW +CYDEV_ANAIF_RT_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_MX +CYDEV_ANAIF_RT_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SW +CYDEV_ANAIF_RT_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW0 +CYDEV_ANAIF_RT_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW1 +CYDEV_ANAIF_RT_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW2 +CYDEV_ANAIF_RT_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW3 +CYDEV_ANAIF_RT_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SW4 +CYDEV_ANAIF_RT_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_MISC +CYDEV_ANAIF_RT_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW0 +CYDEV_ANAIF_RT_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW2 +CYDEV_ANAIF_RT_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SW3 +CYDEV_ANAIF_RT_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR0 +CYDEV_ANAIF_RT_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR1 +CYDEV_ANAIF_RT_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR2 +CYDEV_ANAIF_RT_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR3 +CYDEV_ANAIF_RT_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR4 +CYDEV_ANAIF_RT_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_CR5 +CYDEV_ANAIF_RT_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_D +CYDEV_ANAIF_WRK_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_D +CYDEV_ANAIF_WRK_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_D +CYDEV_ANAIF_WRK_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_D +CYDEV_ANAIF_WRK_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT0 +CYDEV_ANAIF_WRK_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_OUT1 +CYDEV_ANAIF_WRK_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SR +CYDEV_ANAIF_WRK_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_WRK1 +CYDEV_ANAIF_WRK_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_MSK +CYDEV_ANAIF_WRK_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CLK +CYDEV_ANAIF_WRK_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_CPTR +CYDEV_ANAIF_WRK_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_WRK +CYDEV_ANAIF_WRK_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_TST +CYDEV_ANAIF_WRK_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SR +CYDEV_ANAIF_WRK_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_WRK1 +CYDEV_ANAIF_WRK_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_MSK +CYDEV_ANAIF_WRK_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CMPINV +CYDEV_ANAIF_WRK_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_CPTR +CYDEV_ANAIF_WRK_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK0 +CYDEV_ANAIF_WRK_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_WRK1 +CYDEV_ANAIF_WRK_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK0 +CYDEV_ANAIF_WRK_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_WRK1 +CYDEV_ANAIF_WRK_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SOF +CYDEV_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR0 +CYDEV_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR1 +CYDEV_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR2 +CYDEV_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR3 +CYDEV_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR4 +CYDEV_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR5 +CYDEV_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR6 +CYDEV_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_DR7 +CYDEV_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR0 +CYDEV_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CR1 +CYDEV_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_EN +CYDEV_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP_INT_SR +CYDEV_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT0 +CYDEV_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CNT1 +CYDEV_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_CR0 +CYDEV_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR0 +CYDEV_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYDEV_USB_USBIO_CR1 +CYDEV_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DYN_RECONFIG +CYDEV_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF0 +CYDEV_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SOF1 +CYDEV_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT0 +CYDEV_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CNT1 +CYDEV_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_CR0 +CYDEV_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CR +CYDEV_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP0_CNT +CYDEV_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT0 +CYDEV_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CNT1 +CYDEV_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_CR0 +CYDEV_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT0 +CYDEV_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CNT1 +CYDEV_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_CR0 +CYDEV_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT0 +CYDEV_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CNT1 +CYDEV_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_CR0 +CYDEV_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT0 +CYDEV_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CNT1 +CYDEV_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_CR0 +CYDEV_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT0 +CYDEV_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CNT1 +CYDEV_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_CR0 +CYDEV_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT0 +CYDEV_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CNT1 +CYDEV_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_CR0 +CYDEV_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_CFG +CYDEV_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_INT_EN +CYDEV_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SR +CYDEV_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA +CYDEV_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_WA_MSB +CYDEV_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA +CYDEV_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_RA_MSB +CYDEV_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_DR +CYDEV_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUF_SIZE +CYDEV_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_ACTIVE +CYDEV_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYDEV_USB_EP_TYPE +CYDEV_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_CFG +CYDEV_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_INT_EN +CYDEV_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SR +CYDEV_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA +CYDEV_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_WA_MSB +CYDEV_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA +CYDEV_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_RA_MSB +CYDEV_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_DR +CYDEV_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_CFG +CYDEV_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYDEV_USB_USB_CLK_EN +CYDEV_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_EN +CYDEV_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_INT_SR +CYDEV_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_CFG +CYDEV_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_INT_EN +CYDEV_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SR +CYDEV_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA +CYDEV_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_WA_MSB +CYDEV_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA +CYDEV_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_RA_MSB +CYDEV_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_DR +CYDEV_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA +CYDEV_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYDEV_USB_CWA_MSB +CYDEV_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_CFG +CYDEV_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_INT_EN +CYDEV_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SR +CYDEV_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA +CYDEV_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_WA_MSB +CYDEV_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA +CYDEV_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_RA_MSB +CYDEV_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_DR +CYDEV_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES +CYDEV_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYDEV_USB_DMA_THRES_MSB +CYDEV_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_CFG +CYDEV_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_INT_EN +CYDEV_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SR +CYDEV_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA +CYDEV_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_WA_MSB +CYDEV_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA +CYDEV_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_RA_MSB +CYDEV_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_DR +CYDEV_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BUS_RST_CNT +CYDEV_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_CFG +CYDEV_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_INT_EN +CYDEV_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SR +CYDEV_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA +CYDEV_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_WA_MSB +CYDEV_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA +CYDEV_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_RA_MSB +CYDEV_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_DR +CYDEV_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_CFG +CYDEV_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_INT_EN +CYDEV_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SR +CYDEV_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA +CYDEV_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_WA_MSB +CYDEV_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA +CYDEV_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_RA_MSB +CYDEV_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_DR +CYDEV_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_CFG +CYDEV_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_INT_EN +CYDEV_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SR +CYDEV_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA +CYDEV_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_WA_MSB +CYDEV_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA +CYDEV_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_RA_MSB +CYDEV_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_DR +CYDEV_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MBASE +CYDEV_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_DATA_MSIZE +CYDEV_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A0 +CYDEV_UWRK_UWRK8_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A0 +CYDEV_UWRK_UWRK8_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A0 +CYDEV_UWRK_UWRK8_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A0 +CYDEV_UWRK_UWRK8_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A0 +CYDEV_UWRK_UWRK8_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A0 +CYDEV_UWRK_UWRK8_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A0 +CYDEV_UWRK_UWRK8_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A0 +CYDEV_UWRK_UWRK8_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A0 +CYDEV_UWRK_UWRK8_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A0 +CYDEV_UWRK_UWRK8_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A0 +CYDEV_UWRK_UWRK8_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A0 +CYDEV_UWRK_UWRK8_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A0 +CYDEV_UWRK_UWRK8_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A0 +CYDEV_UWRK_UWRK8_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A0 +CYDEV_UWRK_UWRK8_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A0 +CYDEV_UWRK_UWRK8_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_A1 +CYDEV_UWRK_UWRK8_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_A1 +CYDEV_UWRK_UWRK8_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_A1 +CYDEV_UWRK_UWRK8_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_A1 +CYDEV_UWRK_UWRK8_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_A1 +CYDEV_UWRK_UWRK8_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_A1 +CYDEV_UWRK_UWRK8_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_A1 +CYDEV_UWRK_UWRK8_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_A1 +CYDEV_UWRK_UWRK8_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_A1 +CYDEV_UWRK_UWRK8_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_A1 +CYDEV_UWRK_UWRK8_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_A1 +CYDEV_UWRK_UWRK8_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_A1 +CYDEV_UWRK_UWRK8_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_A1 +CYDEV_UWRK_UWRK8_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_A1 +CYDEV_UWRK_UWRK8_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_A1 +CYDEV_UWRK_UWRK8_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_A1 +CYDEV_UWRK_UWRK8_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D0 +CYDEV_UWRK_UWRK8_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D0 +CYDEV_UWRK_UWRK8_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D0 +CYDEV_UWRK_UWRK8_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D0 +CYDEV_UWRK_UWRK8_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D0 +CYDEV_UWRK_UWRK8_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D0 +CYDEV_UWRK_UWRK8_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D0 +CYDEV_UWRK_UWRK8_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D0 +CYDEV_UWRK_UWRK8_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D0 +CYDEV_UWRK_UWRK8_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D0 +CYDEV_UWRK_UWRK8_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D0 +CYDEV_UWRK_UWRK8_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D0 +CYDEV_UWRK_UWRK8_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D0 +CYDEV_UWRK_UWRK8_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D0 +CYDEV_UWRK_UWRK8_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D0 +CYDEV_UWRK_UWRK8_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D0 +CYDEV_UWRK_UWRK8_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_D1 +CYDEV_UWRK_UWRK8_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_D1 +CYDEV_UWRK_UWRK8_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_D1 +CYDEV_UWRK_UWRK8_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_D1 +CYDEV_UWRK_UWRK8_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_D1 +CYDEV_UWRK_UWRK8_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_D1 +CYDEV_UWRK_UWRK8_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_D1 +CYDEV_UWRK_UWRK8_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_D1 +CYDEV_UWRK_UWRK8_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_D1 +CYDEV_UWRK_UWRK8_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_D1 +CYDEV_UWRK_UWRK8_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_D1 +CYDEV_UWRK_UWRK8_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_D1 +CYDEV_UWRK_UWRK8_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_D1 +CYDEV_UWRK_UWRK8_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_D1 +CYDEV_UWRK_UWRK8_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_D1 +CYDEV_UWRK_UWRK8_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_D1 +CYDEV_UWRK_UWRK8_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F0 +CYDEV_UWRK_UWRK8_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F0 +CYDEV_UWRK_UWRK8_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F0 +CYDEV_UWRK_UWRK8_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F0 +CYDEV_UWRK_UWRK8_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F0 +CYDEV_UWRK_UWRK8_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F0 +CYDEV_UWRK_UWRK8_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F0 +CYDEV_UWRK_UWRK8_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F0 +CYDEV_UWRK_UWRK8_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F0 +CYDEV_UWRK_UWRK8_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F0 +CYDEV_UWRK_UWRK8_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F0 +CYDEV_UWRK_UWRK8_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F0 +CYDEV_UWRK_UWRK8_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F0 +CYDEV_UWRK_UWRK8_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F0 +CYDEV_UWRK_UWRK8_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F0 +CYDEV_UWRK_UWRK8_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F0 +CYDEV_UWRK_UWRK8_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_F1 +CYDEV_UWRK_UWRK8_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_F1 +CYDEV_UWRK_UWRK8_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_F1 +CYDEV_UWRK_UWRK8_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_F1 +CYDEV_UWRK_UWRK8_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_F1 +CYDEV_UWRK_UWRK8_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_F1 +CYDEV_UWRK_UWRK8_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_F1 +CYDEV_UWRK_UWRK8_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_F1 +CYDEV_UWRK_UWRK8_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_F1 +CYDEV_UWRK_UWRK8_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_F1 +CYDEV_UWRK_UWRK8_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_F1 +CYDEV_UWRK_UWRK8_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_F1 +CYDEV_UWRK_UWRK8_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_F1 +CYDEV_UWRK_UWRK8_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_F1 +CYDEV_UWRK_UWRK8_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_F1 +CYDEV_UWRK_UWRK8_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_F1 +CYDEV_UWRK_UWRK8_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ST +CYDEV_UWRK_UWRK8_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ST +CYDEV_UWRK_UWRK8_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ST +CYDEV_UWRK_UWRK8_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ST +CYDEV_UWRK_UWRK8_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ST +CYDEV_UWRK_UWRK8_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ST +CYDEV_UWRK_UWRK8_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ST +CYDEV_UWRK_UWRK8_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ST +CYDEV_UWRK_UWRK8_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ST +CYDEV_UWRK_UWRK8_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ST +CYDEV_UWRK_UWRK8_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ST +CYDEV_UWRK_UWRK8_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ST +CYDEV_UWRK_UWRK8_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ST +CYDEV_UWRK_UWRK8_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ST +CYDEV_UWRK_UWRK8_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ST +CYDEV_UWRK_UWRK8_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ST +CYDEV_UWRK_UWRK8_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_CTL +CYDEV_UWRK_UWRK8_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_CTL +CYDEV_UWRK_UWRK8_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_CTL +CYDEV_UWRK_UWRK8_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_CTL +CYDEV_UWRK_UWRK8_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_CTL +CYDEV_UWRK_UWRK8_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_CTL +CYDEV_UWRK_UWRK8_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_CTL +CYDEV_UWRK_UWRK8_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_CTL +CYDEV_UWRK_UWRK8_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_CTL +CYDEV_UWRK_UWRK8_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_CTL +CYDEV_UWRK_UWRK8_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_CTL +CYDEV_UWRK_UWRK8_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_CTL +CYDEV_UWRK_UWRK8_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_CTL +CYDEV_UWRK_UWRK8_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_CTL +CYDEV_UWRK_UWRK8_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_CTL +CYDEV_UWRK_UWRK8_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_CTL +CYDEV_UWRK_UWRK8_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MSK +CYDEV_UWRK_UWRK8_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MSK +CYDEV_UWRK_UWRK8_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MSK +CYDEV_UWRK_UWRK8_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MSK +CYDEV_UWRK_UWRK8_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MSK +CYDEV_UWRK_UWRK8_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MSK +CYDEV_UWRK_UWRK8_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MSK +CYDEV_UWRK_UWRK8_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MSK +CYDEV_UWRK_UWRK8_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MSK +CYDEV_UWRK_UWRK8_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MSK +CYDEV_UWRK_UWRK8_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MSK +CYDEV_UWRK_UWRK8_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MSK +CYDEV_UWRK_UWRK8_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MSK +CYDEV_UWRK_UWRK8_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MSK +CYDEV_UWRK_UWRK8_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MSK +CYDEV_UWRK_UWRK8_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MSK +CYDEV_UWRK_UWRK8_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_ACTL +CYDEV_UWRK_UWRK8_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_ACTL +CYDEV_UWRK_UWRK8_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_ACTL +CYDEV_UWRK_UWRK8_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_ACTL +CYDEV_UWRK_UWRK8_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_ACTL +CYDEV_UWRK_UWRK8_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_ACTL +CYDEV_UWRK_UWRK8_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_ACTL +CYDEV_UWRK_UWRK8_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_ACTL +CYDEV_UWRK_UWRK8_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_ACTL +CYDEV_UWRK_UWRK8_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_ACTL +CYDEV_UWRK_UWRK8_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_ACTL +CYDEV_UWRK_UWRK8_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_ACTL +CYDEV_UWRK_UWRK8_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_ACTL +CYDEV_UWRK_UWRK8_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_ACTL +CYDEV_UWRK_UWRK8_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_ACTL +CYDEV_UWRK_UWRK8_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_ACTL +CYDEV_UWRK_UWRK8_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB00_MC +CYDEV_UWRK_UWRK8_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB01_MC +CYDEV_UWRK_UWRK8_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB02_MC +CYDEV_UWRK_UWRK8_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB03_MC +CYDEV_UWRK_UWRK8_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB04_MC +CYDEV_UWRK_UWRK8_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB05_MC +CYDEV_UWRK_UWRK8_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB06_MC +CYDEV_UWRK_UWRK8_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB07_MC +CYDEV_UWRK_UWRK8_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB08_MC +CYDEV_UWRK_UWRK8_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB09_MC +CYDEV_UWRK_UWRK8_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB10_MC +CYDEV_UWRK_UWRK8_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB11_MC +CYDEV_UWRK_UWRK8_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB12_MC +CYDEV_UWRK_UWRK8_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB13_MC +CYDEV_UWRK_UWRK8_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB14_MC +CYDEV_UWRK_UWRK8_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_UDB15_MC +CYDEV_UWRK_UWRK8_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A0 +CYDEV_UWRK_UWRK8_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A0 +CYDEV_UWRK_UWRK8_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A0 +CYDEV_UWRK_UWRK8_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A0 +CYDEV_UWRK_UWRK8_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A0 +CYDEV_UWRK_UWRK8_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A0 +CYDEV_UWRK_UWRK8_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A0 +CYDEV_UWRK_UWRK8_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A0 +CYDEV_UWRK_UWRK8_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_A1 +CYDEV_UWRK_UWRK8_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_A1 +CYDEV_UWRK_UWRK8_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_A1 +CYDEV_UWRK_UWRK8_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_A1 +CYDEV_UWRK_UWRK8_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_A1 +CYDEV_UWRK_UWRK8_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_A1 +CYDEV_UWRK_UWRK8_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_A1 +CYDEV_UWRK_UWRK8_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_A1 +CYDEV_UWRK_UWRK8_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D0 +CYDEV_UWRK_UWRK8_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D0 +CYDEV_UWRK_UWRK8_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D0 +CYDEV_UWRK_UWRK8_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D0 +CYDEV_UWRK_UWRK8_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D0 +CYDEV_UWRK_UWRK8_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D0 +CYDEV_UWRK_UWRK8_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D0 +CYDEV_UWRK_UWRK8_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D0 +CYDEV_UWRK_UWRK8_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_D1 +CYDEV_UWRK_UWRK8_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_D1 +CYDEV_UWRK_UWRK8_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_D1 +CYDEV_UWRK_UWRK8_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_D1 +CYDEV_UWRK_UWRK8_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_D1 +CYDEV_UWRK_UWRK8_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_D1 +CYDEV_UWRK_UWRK8_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_D1 +CYDEV_UWRK_UWRK8_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_D1 +CYDEV_UWRK_UWRK8_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F0 +CYDEV_UWRK_UWRK8_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F0 +CYDEV_UWRK_UWRK8_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F0 +CYDEV_UWRK_UWRK8_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F0 +CYDEV_UWRK_UWRK8_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F0 +CYDEV_UWRK_UWRK8_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F0 +CYDEV_UWRK_UWRK8_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F0 +CYDEV_UWRK_UWRK8_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F0 +CYDEV_UWRK_UWRK8_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_F1 +CYDEV_UWRK_UWRK8_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_F1 +CYDEV_UWRK_UWRK8_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_F1 +CYDEV_UWRK_UWRK8_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_F1 +CYDEV_UWRK_UWRK8_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_F1 +CYDEV_UWRK_UWRK8_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_F1 +CYDEV_UWRK_UWRK8_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_F1 +CYDEV_UWRK_UWRK8_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_F1 +CYDEV_UWRK_UWRK8_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ST +CYDEV_UWRK_UWRK8_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ST +CYDEV_UWRK_UWRK8_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ST +CYDEV_UWRK_UWRK8_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ST +CYDEV_UWRK_UWRK8_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ST +CYDEV_UWRK_UWRK8_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ST +CYDEV_UWRK_UWRK8_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ST +CYDEV_UWRK_UWRK8_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ST +CYDEV_UWRK_UWRK8_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_CTL +CYDEV_UWRK_UWRK8_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_CTL +CYDEV_UWRK_UWRK8_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_CTL +CYDEV_UWRK_UWRK8_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_CTL +CYDEV_UWRK_UWRK8_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_CTL +CYDEV_UWRK_UWRK8_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_CTL +CYDEV_UWRK_UWRK8_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_CTL +CYDEV_UWRK_UWRK8_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_CTL +CYDEV_UWRK_UWRK8_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MSK +CYDEV_UWRK_UWRK8_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MSK +CYDEV_UWRK_UWRK8_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MSK +CYDEV_UWRK_UWRK8_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MSK +CYDEV_UWRK_UWRK8_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MSK +CYDEV_UWRK_UWRK8_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MSK +CYDEV_UWRK_UWRK8_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MSK +CYDEV_UWRK_UWRK8_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MSK +CYDEV_UWRK_UWRK8_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_ACTL +CYDEV_UWRK_UWRK8_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_ACTL +CYDEV_UWRK_UWRK8_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_ACTL +CYDEV_UWRK_UWRK8_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_ACTL +CYDEV_UWRK_UWRK8_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_ACTL +CYDEV_UWRK_UWRK8_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_ACTL +CYDEV_UWRK_UWRK8_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_ACTL +CYDEV_UWRK_UWRK8_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_ACTL +CYDEV_UWRK_UWRK8_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB04_MC +CYDEV_UWRK_UWRK8_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB05_MC +CYDEV_UWRK_UWRK8_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB06_MC +CYDEV_UWRK_UWRK8_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB07_MC +CYDEV_UWRK_UWRK8_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB08_MC +CYDEV_UWRK_UWRK8_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB09_MC +CYDEV_UWRK_UWRK8_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB10_MC +CYDEV_UWRK_UWRK8_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_UDB11_MC +CYDEV_UWRK_UWRK8_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 +CYDEV_UWRK_UWRK16_CAT_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 +CYDEV_UWRK_UWRK16_CAT_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC +CYDEV_UWRK_UWRK16_DEF_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC +CYDEV_UWRK_UWRK16_DEF_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFG +CYDEV_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR +CYDEV_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_ERR_ADR +CYDEV_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_CFG +CYDEV_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_ACTION +CYDEV_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASIC_STATUS +CYDEV_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_CFG +CYDEV_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_ACTION +CYDEV_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASIC_STATUS +CYDEV_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_CFG +CYDEV_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_ACTION +CYDEV_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASIC_STATUS +CYDEV_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_CFG +CYDEV_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_ACTION +CYDEV_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASIC_STATUS +CYDEV_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_CFG +CYDEV_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_ACTION +CYDEV_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASIC_STATUS +CYDEV_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_CFG +CYDEV_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_ACTION +CYDEV_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASIC_STATUS +CYDEV_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_CFG +CYDEV_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_ACTION +CYDEV_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASIC_STATUS +CYDEV_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_CFG +CYDEV_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_ACTION +CYDEV_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASIC_STATUS +CYDEV_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_CFG +CYDEV_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_ACTION +CYDEV_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASIC_STATUS +CYDEV_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_CFG +CYDEV_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_ACTION +CYDEV_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASIC_STATUS +CYDEV_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_CFG +CYDEV_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_ACTION +CYDEV_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASIC_STATUS +CYDEV_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_CFG +CYDEV_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_ACTION +CYDEV_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASIC_STATUS +CYDEV_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_CFG +CYDEV_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_ACTION +CYDEV_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASIC_STATUS +CYDEV_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_CFG +CYDEV_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_ACTION +CYDEV_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASIC_STATUS +CYDEV_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_CFG +CYDEV_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_ACTION +CYDEV_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASIC_STATUS +CYDEV_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_CFG +CYDEV_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_ACTION +CYDEV_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASIC_STATUS +CYDEV_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_CFG +CYDEV_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_ACTION +CYDEV_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASIC_STATUS +CYDEV_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_CFG +CYDEV_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_ACTION +CYDEV_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASIC_STATUS +CYDEV_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_CFG +CYDEV_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_ACTION +CYDEV_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASIC_STATUS +CYDEV_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_CFG +CYDEV_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_ACTION +CYDEV_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASIC_STATUS +CYDEV_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_CFG +CYDEV_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_ACTION +CYDEV_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASIC_STATUS +CYDEV_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_CFG +CYDEV_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_ACTION +CYDEV_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASIC_STATUS +CYDEV_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_CFG +CYDEV_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_ACTION +CYDEV_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASIC_STATUS +CYDEV_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_CFG +CYDEV_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_ACTION +CYDEV_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASIC_STATUS +CYDEV_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG0 +CYDEV_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_CFG1 +CYDEV_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG0 +CYDEV_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_CFG1 +CYDEV_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG0 +CYDEV_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_CFG1 +CYDEV_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG0 +CYDEV_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_CFG1 +CYDEV_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG0 +CYDEV_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_CFG1 +CYDEV_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG0 +CYDEV_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_CFG1 +CYDEV_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG0 +CYDEV_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_CFG1 +CYDEV_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG0 +CYDEV_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_CFG1 +CYDEV_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG0 +CYDEV_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_CFG1 +CYDEV_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG0 +CYDEV_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_CFG1 +CYDEV_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG0 +CYDEV_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_CFG1 +CYDEV_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG0 +CYDEV_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_CFG1 +CYDEV_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG0 +CYDEV_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_CFG1 +CYDEV_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG0 +CYDEV_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_CFG1 +CYDEV_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG0 +CYDEV_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_CFG1 +CYDEV_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG0 +CYDEV_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_CFG1 +CYDEV_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG0 +CYDEV_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_CFG1 +CYDEV_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG0 +CYDEV_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_CFG1 +CYDEV_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG0 +CYDEV_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_CFG1 +CYDEV_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG0 +CYDEV_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_CFG1 +CYDEV_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG0 +CYDEV_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_CFG1 +CYDEV_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG0 +CYDEV_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_CFG1 +CYDEV_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG0 +CYDEV_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_CFG1 +CYDEV_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG0 +CYDEV_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_CFG1 +CYDEV_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD0 +CYDEV_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_ORIG_TD1 +CYDEV_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD0 +CYDEV_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_ORIG_TD1 +CYDEV_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD0 +CYDEV_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_ORIG_TD1 +CYDEV_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD0 +CYDEV_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_ORIG_TD1 +CYDEV_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD0 +CYDEV_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_ORIG_TD1 +CYDEV_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD0 +CYDEV_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_ORIG_TD1 +CYDEV_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD0 +CYDEV_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_ORIG_TD1 +CYDEV_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD0 +CYDEV_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_ORIG_TD1 +CYDEV_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD0 +CYDEV_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_ORIG_TD1 +CYDEV_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD0 +CYDEV_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_ORIG_TD1 +CYDEV_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD0 +CYDEV_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_ORIG_TD1 +CYDEV_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD0 +CYDEV_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_ORIG_TD1 +CYDEV_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD0 +CYDEV_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_ORIG_TD1 +CYDEV_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD0 +CYDEV_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_ORIG_TD1 +CYDEV_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD0 +CYDEV_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_ORIG_TD1 +CYDEV_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD0 +CYDEV_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_ORIG_TD1 +CYDEV_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD0 +CYDEV_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_ORIG_TD1 +CYDEV_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD0 +CYDEV_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_ORIG_TD1 +CYDEV_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD0 +CYDEV_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_ORIG_TD1 +CYDEV_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD0 +CYDEV_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_ORIG_TD1 +CYDEV_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD0 +CYDEV_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_ORIG_TD1 +CYDEV_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD0 +CYDEV_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_ORIG_TD1 +CYDEV_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD0 +CYDEV_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_ORIG_TD1 +CYDEV_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD0 +CYDEV_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_ORIG_TD1 +CYDEV_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD0 +CYDEV_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_ORIG_TD1 +CYDEV_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD0 +CYDEV_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_ORIG_TD1 +CYDEV_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD0 +CYDEV_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_ORIG_TD1 +CYDEV_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD0 +CYDEV_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_ORIG_TD1 +CYDEV_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD0 +CYDEV_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_ORIG_TD1 +CYDEV_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD0 +CYDEV_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_ORIG_TD1 +CYDEV_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD0 +CYDEV_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_ORIG_TD1 +CYDEV_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD0 +CYDEV_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_ORIG_TD1 +CYDEV_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD0 +CYDEV_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_ORIG_TD1 +CYDEV_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD0 +CYDEV_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_ORIG_TD1 +CYDEV_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD0 +CYDEV_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_ORIG_TD1 +CYDEV_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD0 +CYDEV_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_ORIG_TD1 +CYDEV_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD0 +CYDEV_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_ORIG_TD1 +CYDEV_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD0 +CYDEV_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_ORIG_TD1 +CYDEV_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD0 +CYDEV_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_ORIG_TD1 +CYDEV_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD0 +CYDEV_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_ORIG_TD1 +CYDEV_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD0 +CYDEV_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_ORIG_TD1 +CYDEV_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD0 +CYDEV_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_ORIG_TD1 +CYDEV_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD0 +CYDEV_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_ORIG_TD1 +CYDEV_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD0 +CYDEV_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_ORIG_TD1 +CYDEV_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD0 +CYDEV_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_ORIG_TD1 +CYDEV_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD0 +CYDEV_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_ORIG_TD1 +CYDEV_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD0 +CYDEV_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_ORIG_TD1 +CYDEV_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD0 +CYDEV_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_ORIG_TD1 +CYDEV_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD0 +CYDEV_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_ORIG_TD1 +CYDEV_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD0 +CYDEV_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_ORIG_TD1 +CYDEV_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD0 +CYDEV_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_ORIG_TD1 +CYDEV_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD0 +CYDEV_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_ORIG_TD1 +CYDEV_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD0 +CYDEV_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_ORIG_TD1 +CYDEV_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD0 +CYDEV_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_ORIG_TD1 +CYDEV_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD0 +CYDEV_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_ORIG_TD1 +CYDEV_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD0 +CYDEV_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_ORIG_TD1 +CYDEV_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD0 +CYDEV_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_ORIG_TD1 +CYDEV_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD0 +CYDEV_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_ORIG_TD1 +CYDEV_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD0 +CYDEV_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_ORIG_TD1 +CYDEV_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD0 +CYDEV_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_ORIG_TD1 +CYDEV_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD0 +CYDEV_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_ORIG_TD1 +CYDEV_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD0 +CYDEV_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_ORIG_TD1 +CYDEV_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD0 +CYDEV_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_ORIG_TD1 +CYDEV_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD0 +CYDEV_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_ORIG_TD1 +CYDEV_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD0 +CYDEV_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_ORIG_TD1 +CYDEV_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD0 +CYDEV_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_ORIG_TD1 +CYDEV_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD0 +CYDEV_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_ORIG_TD1 +CYDEV_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD0 +CYDEV_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_ORIG_TD1 +CYDEV_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD0 +CYDEV_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_ORIG_TD1 +CYDEV_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD0 +CYDEV_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_ORIG_TD1 +CYDEV_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD0 +CYDEV_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_ORIG_TD1 +CYDEV_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD0 +CYDEV_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_ORIG_TD1 +CYDEV_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD0 +CYDEV_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_ORIG_TD1 +CYDEV_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD0 +CYDEV_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_ORIG_TD1 +CYDEV_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD0 +CYDEV_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_ORIG_TD1 +CYDEV_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD0 +CYDEV_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_ORIG_TD1 +CYDEV_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD0 +CYDEV_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_ORIG_TD1 +CYDEV_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD0 +CYDEV_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_ORIG_TD1 +CYDEV_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD0 +CYDEV_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_ORIG_TD1 +CYDEV_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD0 +CYDEV_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_ORIG_TD1 +CYDEV_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD0 +CYDEV_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_ORIG_TD1 +CYDEV_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD0 +CYDEV_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_ORIG_TD1 +CYDEV_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD0 +CYDEV_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_ORIG_TD1 +CYDEV_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD0 +CYDEV_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_ORIG_TD1 +CYDEV_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD0 +CYDEV_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_ORIG_TD1 +CYDEV_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD0 +CYDEV_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_ORIG_TD1 +CYDEV_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD0 +CYDEV_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_ORIG_TD1 +CYDEV_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD0 +CYDEV_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_ORIG_TD1 +CYDEV_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD0 +CYDEV_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_ORIG_TD1 +CYDEV_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD0 +CYDEV_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_ORIG_TD1 +CYDEV_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD0 +CYDEV_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_ORIG_TD1 +CYDEV_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD0 +CYDEV_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_ORIG_TD1 +CYDEV_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD0 +CYDEV_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_ORIG_TD1 +CYDEV_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD0 +CYDEV_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_ORIG_TD1 +CYDEV_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD0 +CYDEV_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_ORIG_TD1 +CYDEV_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD0 +CYDEV_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_ORIG_TD1 +CYDEV_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD0 +CYDEV_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_ORIG_TD1 +CYDEV_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD0 +CYDEV_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_ORIG_TD1 +CYDEV_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD0 +CYDEV_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_ORIG_TD1 +CYDEV_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD0 +CYDEV_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_ORIG_TD1 +CYDEV_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD0 +CYDEV_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_ORIG_TD1 +CYDEV_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD0 +CYDEV_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_ORIG_TD1 +CYDEV_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD0 +CYDEV_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_ORIG_TD1 +CYDEV_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD0 +CYDEV_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_ORIG_TD1 +CYDEV_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD0 +CYDEV_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_ORIG_TD1 +CYDEV_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD0 +CYDEV_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_ORIG_TD1 +CYDEV_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD0 +CYDEV_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_ORIG_TD1 +CYDEV_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD0 +CYDEV_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_ORIG_TD1 +CYDEV_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD0 +CYDEV_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_ORIG_TD1 +CYDEV_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD0 +CYDEV_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_ORIG_TD1 +CYDEV_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD0 +CYDEV_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_ORIG_TD1 +CYDEV_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD0 +CYDEV_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_ORIG_TD1 +CYDEV_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD0 +CYDEV_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_ORIG_TD1 +CYDEV_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD0 +CYDEV_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_ORIG_TD1 +CYDEV_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD0 +CYDEV_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_ORIG_TD1 +CYDEV_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD0 +CYDEV_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_ORIG_TD1 +CYDEV_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD0 +CYDEV_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_ORIG_TD1 +CYDEV_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD0 +CYDEV_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_ORIG_TD1 +CYDEV_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD0 +CYDEV_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_ORIG_TD1 +CYDEV_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD0 +CYDEV_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_ORIG_TD1 +CYDEV_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD0 +CYDEV_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_ORIG_TD1 +CYDEV_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD0 +CYDEV_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_ORIG_TD1 +CYDEV_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD0 +CYDEV_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_ORIG_TD1 +CYDEV_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD0 +CYDEV_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_ORIG_TD1 +CYDEV_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD0 +CYDEV_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_ORIG_TD1 +CYDEV_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD0 +CYDEV_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_ORIG_TD1 +CYDEV_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD0 +CYDEV_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_ORIG_TD1 +CYDEV_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD0 +CYDEV_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_ORIG_TD1 +CYDEV_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MBASE +CYDEV_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_DATA_MSIZE +CYDEV_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_SR +CYDEV_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_INT_EN +CYDEV_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BUF_SR +CYDEV_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_ERR_SR +CYDEV_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CMD +CYDEV_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_CFG +CYDEV_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_CMD +CYDEV_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_ID +CYDEV_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DH +CYDEV_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_DL +CYDEV_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_CMD +CYDEV_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_ID +CYDEV_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DH +CYDEV_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_DL +CYDEV_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_CMD +CYDEV_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_ID +CYDEV_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DH +CYDEV_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_DL +CYDEV_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_CMD +CYDEV_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_ID +CYDEV_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DH +CYDEV_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_DL +CYDEV_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_CMD +CYDEV_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_ID +CYDEV_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DH +CYDEV_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_DL +CYDEV_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_CMD +CYDEV_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_ID +CYDEV_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DH +CYDEV_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_DL +CYDEV_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_CMD +CYDEV_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_ID +CYDEV_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DH +CYDEV_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_DL +CYDEV_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_CMD +CYDEV_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_ID +CYDEV_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DH +CYDEV_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_DL +CYDEV_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_CMD +CYDEV_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ID +CYDEV_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DH +CYDEV_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_DL +CYDEV_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMR +CYDEV_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACR +CYDEV_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_AMRD +CYDEV_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_ACRD +CYDEV_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_CMD +CYDEV_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ID +CYDEV_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DH +CYDEV_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_DL +CYDEV_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMR +CYDEV_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACR +CYDEV_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_AMRD +CYDEV_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_ACRD +CYDEV_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_CMD +CYDEV_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ID +CYDEV_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DH +CYDEV_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_DL +CYDEV_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMR +CYDEV_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACR +CYDEV_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_AMRD +CYDEV_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_ACRD +CYDEV_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_CMD +CYDEV_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ID +CYDEV_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DH +CYDEV_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_DL +CYDEV_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMR +CYDEV_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACR +CYDEV_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_AMRD +CYDEV_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_ACRD +CYDEV_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_CMD +CYDEV_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ID +CYDEV_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DH +CYDEV_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_DL +CYDEV_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMR +CYDEV_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACR +CYDEV_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_AMRD +CYDEV_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_ACRD +CYDEV_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_CMD +CYDEV_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ID +CYDEV_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DH +CYDEV_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_DL +CYDEV_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMR +CYDEV_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACR +CYDEV_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_AMRD +CYDEV_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_ACRD +CYDEV_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_CMD +CYDEV_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ID +CYDEV_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DH +CYDEV_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_DL +CYDEV_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMR +CYDEV_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACR +CYDEV_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_AMRD +CYDEV_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_ACRD +CYDEV_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_CMD +CYDEV_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ID +CYDEV_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DH +CYDEV_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_DL +CYDEV_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMR +CYDEV_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACR +CYDEV_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_AMRD +CYDEV_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_ACRD +CYDEV_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_CMD +CYDEV_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ID +CYDEV_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DH +CYDEV_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_DL +CYDEV_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMR +CYDEV_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACR +CYDEV_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_AMRD +CYDEV_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_ACRD +CYDEV_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_CMD +CYDEV_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ID +CYDEV_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DH +CYDEV_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_DL +CYDEV_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMR +CYDEV_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACR +CYDEV_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_AMRD +CYDEV_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_ACRD +CYDEV_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_CMD +CYDEV_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ID +CYDEV_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DH +CYDEV_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_DL +CYDEV_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMR +CYDEV_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACR +CYDEV_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_AMRD +CYDEV_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_ACRD +CYDEV_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_CMD +CYDEV_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ID +CYDEV_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DH +CYDEV_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_DL +CYDEV_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMR +CYDEV_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACR +CYDEV_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_AMRD +CYDEV_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_ACRD +CYDEV_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_CMD +CYDEV_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ID +CYDEV_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DH +CYDEV_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_DL +CYDEV_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMR +CYDEV_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACR +CYDEV_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_AMRD +CYDEV_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_ACRD +CYDEV_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_CMD +CYDEV_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ID +CYDEV_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DH +CYDEV_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_DL +CYDEV_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMR +CYDEV_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACR +CYDEV_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_AMRD +CYDEV_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_ACRD +CYDEV_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_CMD +CYDEV_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ID +CYDEV_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DH +CYDEV_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_DL +CYDEV_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMR +CYDEV_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACR +CYDEV_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_AMRD +CYDEV_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_ACRD +CYDEV_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_CMD +CYDEV_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ID +CYDEV_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DH +CYDEV_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_DL +CYDEV_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMR +CYDEV_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACR +CYDEV_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_AMRD +CYDEV_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_ACRD +CYDEV_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MBASE +CYDEV_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_DATA_MSIZE +CYDEV_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MBASE +CYDEV_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_DATA_MSIZE +CYDEV_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MBASE +CYDEV_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_DATA_MSIZE +CYDEV_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MBASE +CYDEV_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_DATA_MSIZE +CYDEV_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MBASE +CYDEV_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_DATA_MSIZE +CYDEV_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MBASE +CYDEV_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_DATA_MSIZE +CYDEV_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CR +CYDEV_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SR +CYDEV_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_EN +CYDEV_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_RAM_DIR +CYDEV_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SEMA +CYDEV_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DSI_CTRL +CYDEV_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_INT_CTRL +CYDEV_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DMA_CTRL +CYDEV_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEA +CYDEV_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAM +CYDEV_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEAH +CYDEV_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEB +CYDEV_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBM +CYDEV_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_STAGEBH +CYDEV_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDA +CYDEV_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAM +CYDEV_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAH +CYDEV_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDAS +CYDEV_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDB +CYDEV_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBM +CYDEV_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBH +CYDEV_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_HOLDBS +CYDEV_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_COHER +CYDEV_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DALIGN +CYDEV_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT0 +CYDEV_UCFG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT1 +CYDEV_UCFG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT2 +CYDEV_UCFG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT3 +CYDEV_UCFG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT4 +CYDEV_UCFG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT5 +CYDEV_UCFG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT6 +CYDEV_UCFG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT7 +CYDEV_UCFG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT8 +CYDEV_UCFG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT9 +CYDEV_UCFG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT10 +CYDEV_UCFG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_IT11 +CYDEV_UCFG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT0 +CYDEV_UCFG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT1 +CYDEV_UCFG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT2 +CYDEV_UCFG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_PLD_ORT3 +CYDEV_UCFG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG0 +CYDEV_UCFG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG1 +CYDEV_UCFG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG2 +CYDEV_UCFG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG3 +CYDEV_UCFG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG4 +CYDEV_UCFG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG5 +CYDEV_UCFG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG6 +CYDEV_UCFG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG7 +CYDEV_UCFG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG8 +CYDEV_UCFG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG9 +CYDEV_UCFG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG10 +CYDEV_UCFG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG11 +CYDEV_UCFG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG12 +CYDEV_UCFG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG13 +CYDEV_UCFG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG14 +CYDEV_UCFG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG15 +CYDEV_UCFG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG16 +CYDEV_UCFG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG17 +CYDEV_UCFG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG18 +CYDEV_UCFG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG19 +CYDEV_UCFG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG20 +CYDEV_UCFG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG21 +CYDEV_UCFG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG22 +CYDEV_UCFG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG23 +CYDEV_UCFG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG24 +CYDEV_UCFG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG25 +CYDEV_UCFG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG26 +CYDEV_UCFG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG27 +CYDEV_UCFG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG28 +CYDEV_UCFG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG29 +CYDEV_UCFG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG30 +CYDEV_UCFG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_CFG31 +CYDEV_UCFG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG0 +CYDEV_UCFG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG1 +CYDEV_UCFG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG2 +CYDEV_UCFG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG3 +CYDEV_UCFG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG4 +CYDEV_UCFG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG5 +CYDEV_UCFG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG6 +CYDEV_UCFG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_DCFG7 +CYDEV_UCFG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT0 +CYDEV_UCFG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT1 +CYDEV_UCFG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT2 +CYDEV_UCFG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT3 +CYDEV_UCFG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT4 +CYDEV_UCFG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT5 +CYDEV_UCFG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT6 +CYDEV_UCFG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT7 +CYDEV_UCFG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT8 +CYDEV_UCFG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT9 +CYDEV_UCFG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT10 +CYDEV_UCFG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_IT11 +CYDEV_UCFG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT0 +CYDEV_UCFG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT1 +CYDEV_UCFG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT2 +CYDEV_UCFG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_PLD_ORT3 +CYDEV_UCFG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG0 +CYDEV_UCFG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG1 +CYDEV_UCFG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG2 +CYDEV_UCFG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG3 +CYDEV_UCFG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG4 +CYDEV_UCFG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG5 +CYDEV_UCFG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG6 +CYDEV_UCFG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG7 +CYDEV_UCFG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG8 +CYDEV_UCFG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG9 +CYDEV_UCFG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG10 +CYDEV_UCFG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG11 +CYDEV_UCFG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG12 +CYDEV_UCFG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG13 +CYDEV_UCFG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG14 +CYDEV_UCFG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG15 +CYDEV_UCFG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG16 +CYDEV_UCFG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG17 +CYDEV_UCFG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG18 +CYDEV_UCFG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG19 +CYDEV_UCFG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG20 +CYDEV_UCFG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG21 +CYDEV_UCFG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG22 +CYDEV_UCFG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG23 +CYDEV_UCFG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG24 +CYDEV_UCFG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG25 +CYDEV_UCFG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG26 +CYDEV_UCFG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG27 +CYDEV_UCFG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG28 +CYDEV_UCFG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG29 +CYDEV_UCFG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG30 +CYDEV_UCFG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_CFG31 +CYDEV_UCFG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG0 +CYDEV_UCFG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG1 +CYDEV_UCFG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG2 +CYDEV_UCFG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG3 +CYDEV_UCFG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG4 +CYDEV_UCFG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG5 +CYDEV_UCFG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG6 +CYDEV_UCFG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_DCFG7 +CYDEV_UCFG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT0 +CYDEV_UCFG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT1 +CYDEV_UCFG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT2 +CYDEV_UCFG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT3 +CYDEV_UCFG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT4 +CYDEV_UCFG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT5 +CYDEV_UCFG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT6 +CYDEV_UCFG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT7 +CYDEV_UCFG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT8 +CYDEV_UCFG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT9 +CYDEV_UCFG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT10 +CYDEV_UCFG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_IT11 +CYDEV_UCFG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT0 +CYDEV_UCFG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT1 +CYDEV_UCFG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT2 +CYDEV_UCFG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_PLD_ORT3 +CYDEV_UCFG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG0 +CYDEV_UCFG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG1 +CYDEV_UCFG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG2 +CYDEV_UCFG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG3 +CYDEV_UCFG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG4 +CYDEV_UCFG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG5 +CYDEV_UCFG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG6 +CYDEV_UCFG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG7 +CYDEV_UCFG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG8 +CYDEV_UCFG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG9 +CYDEV_UCFG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG10 +CYDEV_UCFG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG11 +CYDEV_UCFG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG12 +CYDEV_UCFG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG13 +CYDEV_UCFG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG14 +CYDEV_UCFG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG15 +CYDEV_UCFG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG16 +CYDEV_UCFG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG17 +CYDEV_UCFG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG18 +CYDEV_UCFG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG19 +CYDEV_UCFG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG20 +CYDEV_UCFG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG21 +CYDEV_UCFG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG22 +CYDEV_UCFG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG23 +CYDEV_UCFG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG24 +CYDEV_UCFG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG25 +CYDEV_UCFG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG26 +CYDEV_UCFG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG27 +CYDEV_UCFG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG28 +CYDEV_UCFG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG29 +CYDEV_UCFG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG30 +CYDEV_UCFG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_CFG31 +CYDEV_UCFG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG0 +CYDEV_UCFG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG1 +CYDEV_UCFG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG2 +CYDEV_UCFG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG3 +CYDEV_UCFG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG4 +CYDEV_UCFG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG5 +CYDEV_UCFG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG6 +CYDEV_UCFG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_DCFG7 +CYDEV_UCFG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT0 +CYDEV_UCFG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT1 +CYDEV_UCFG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT2 +CYDEV_UCFG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT3 +CYDEV_UCFG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT4 +CYDEV_UCFG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT5 +CYDEV_UCFG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT6 +CYDEV_UCFG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT7 +CYDEV_UCFG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT8 +CYDEV_UCFG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT9 +CYDEV_UCFG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT10 +CYDEV_UCFG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_IT11 +CYDEV_UCFG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT0 +CYDEV_UCFG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT1 +CYDEV_UCFG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT2 +CYDEV_UCFG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_PLD_ORT3 +CYDEV_UCFG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG0 +CYDEV_UCFG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG1 +CYDEV_UCFG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG2 +CYDEV_UCFG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG3 +CYDEV_UCFG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG4 +CYDEV_UCFG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG5 +CYDEV_UCFG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG6 +CYDEV_UCFG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG7 +CYDEV_UCFG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG8 +CYDEV_UCFG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG9 +CYDEV_UCFG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG10 +CYDEV_UCFG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG11 +CYDEV_UCFG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG12 +CYDEV_UCFG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG13 +CYDEV_UCFG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG14 +CYDEV_UCFG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG15 +CYDEV_UCFG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG16 +CYDEV_UCFG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG17 +CYDEV_UCFG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG18 +CYDEV_UCFG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG19 +CYDEV_UCFG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG20 +CYDEV_UCFG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG21 +CYDEV_UCFG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG22 +CYDEV_UCFG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG23 +CYDEV_UCFG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG24 +CYDEV_UCFG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG25 +CYDEV_UCFG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG26 +CYDEV_UCFG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG27 +CYDEV_UCFG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG28 +CYDEV_UCFG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG29 +CYDEV_UCFG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG30 +CYDEV_UCFG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_CFG31 +CYDEV_UCFG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG0 +CYDEV_UCFG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG1 +CYDEV_UCFG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG2 +CYDEV_UCFG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG3 +CYDEV_UCFG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG4 +CYDEV_UCFG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG5 +CYDEV_UCFG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG6 +CYDEV_UCFG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_DCFG7 +CYDEV_UCFG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT0 +CYDEV_UCFG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT1 +CYDEV_UCFG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT2 +CYDEV_UCFG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT3 +CYDEV_UCFG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT4 +CYDEV_UCFG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT5 +CYDEV_UCFG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT6 +CYDEV_UCFG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT7 +CYDEV_UCFG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT8 +CYDEV_UCFG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT9 +CYDEV_UCFG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT10 +CYDEV_UCFG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_IT11 +CYDEV_UCFG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT0 +CYDEV_UCFG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT1 +CYDEV_UCFG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT2 +CYDEV_UCFG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_PLD_ORT3 +CYDEV_UCFG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG0 +CYDEV_UCFG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG1 +CYDEV_UCFG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG2 +CYDEV_UCFG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG3 +CYDEV_UCFG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG4 +CYDEV_UCFG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG5 +CYDEV_UCFG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG6 +CYDEV_UCFG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG7 +CYDEV_UCFG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG8 +CYDEV_UCFG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG9 +CYDEV_UCFG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG10 +CYDEV_UCFG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG11 +CYDEV_UCFG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG12 +CYDEV_UCFG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG13 +CYDEV_UCFG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG14 +CYDEV_UCFG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG15 +CYDEV_UCFG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG16 +CYDEV_UCFG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG17 +CYDEV_UCFG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG18 +CYDEV_UCFG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG19 +CYDEV_UCFG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG20 +CYDEV_UCFG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG21 +CYDEV_UCFG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG22 +CYDEV_UCFG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG23 +CYDEV_UCFG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG24 +CYDEV_UCFG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG25 +CYDEV_UCFG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG26 +CYDEV_UCFG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG27 +CYDEV_UCFG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG28 +CYDEV_UCFG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG29 +CYDEV_UCFG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG30 +CYDEV_UCFG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_CFG31 +CYDEV_UCFG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG0 +CYDEV_UCFG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG1 +CYDEV_UCFG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG2 +CYDEV_UCFG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG3 +CYDEV_UCFG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG4 +CYDEV_UCFG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG5 +CYDEV_UCFG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG6 +CYDEV_UCFG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_DCFG7 +CYDEV_UCFG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT0 +CYDEV_UCFG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT1 +CYDEV_UCFG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT2 +CYDEV_UCFG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT3 +CYDEV_UCFG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT4 +CYDEV_UCFG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT5 +CYDEV_UCFG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT6 +CYDEV_UCFG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT7 +CYDEV_UCFG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT8 +CYDEV_UCFG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT9 +CYDEV_UCFG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT10 +CYDEV_UCFG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_IT11 +CYDEV_UCFG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT0 +CYDEV_UCFG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT1 +CYDEV_UCFG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT2 +CYDEV_UCFG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_PLD_ORT3 +CYDEV_UCFG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG0 +CYDEV_UCFG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG1 +CYDEV_UCFG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG2 +CYDEV_UCFG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG3 +CYDEV_UCFG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG4 +CYDEV_UCFG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG5 +CYDEV_UCFG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG6 +CYDEV_UCFG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG7 +CYDEV_UCFG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG8 +CYDEV_UCFG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG9 +CYDEV_UCFG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG10 +CYDEV_UCFG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG11 +CYDEV_UCFG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG12 +CYDEV_UCFG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG13 +CYDEV_UCFG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG14 +CYDEV_UCFG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG15 +CYDEV_UCFG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG16 +CYDEV_UCFG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG17 +CYDEV_UCFG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG18 +CYDEV_UCFG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG19 +CYDEV_UCFG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG20 +CYDEV_UCFG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG21 +CYDEV_UCFG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG22 +CYDEV_UCFG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG23 +CYDEV_UCFG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG24 +CYDEV_UCFG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG25 +CYDEV_UCFG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG26 +CYDEV_UCFG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG27 +CYDEV_UCFG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG28 +CYDEV_UCFG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG29 +CYDEV_UCFG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG30 +CYDEV_UCFG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_CFG31 +CYDEV_UCFG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG0 +CYDEV_UCFG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG1 +CYDEV_UCFG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG2 +CYDEV_UCFG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG3 +CYDEV_UCFG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG4 +CYDEV_UCFG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG5 +CYDEV_UCFG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG6 +CYDEV_UCFG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_DCFG7 +CYDEV_UCFG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT0 +CYDEV_UCFG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT1 +CYDEV_UCFG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT2 +CYDEV_UCFG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT3 +CYDEV_UCFG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT4 +CYDEV_UCFG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT5 +CYDEV_UCFG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT6 +CYDEV_UCFG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT7 +CYDEV_UCFG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT8 +CYDEV_UCFG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT9 +CYDEV_UCFG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT10 +CYDEV_UCFG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_IT11 +CYDEV_UCFG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT0 +CYDEV_UCFG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT1 +CYDEV_UCFG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT2 +CYDEV_UCFG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_PLD_ORT3 +CYDEV_UCFG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG0 +CYDEV_UCFG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG1 +CYDEV_UCFG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG2 +CYDEV_UCFG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG3 +CYDEV_UCFG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG4 +CYDEV_UCFG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG5 +CYDEV_UCFG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG6 +CYDEV_UCFG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG7 +CYDEV_UCFG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG8 +CYDEV_UCFG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG9 +CYDEV_UCFG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG10 +CYDEV_UCFG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG11 +CYDEV_UCFG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG12 +CYDEV_UCFG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG13 +CYDEV_UCFG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG14 +CYDEV_UCFG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG15 +CYDEV_UCFG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG16 +CYDEV_UCFG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG17 +CYDEV_UCFG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG18 +CYDEV_UCFG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG19 +CYDEV_UCFG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG20 +CYDEV_UCFG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG21 +CYDEV_UCFG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG22 +CYDEV_UCFG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG23 +CYDEV_UCFG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG24 +CYDEV_UCFG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG25 +CYDEV_UCFG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG26 +CYDEV_UCFG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG27 +CYDEV_UCFG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG28 +CYDEV_UCFG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG29 +CYDEV_UCFG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG30 +CYDEV_UCFG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_CFG31 +CYDEV_UCFG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG0 +CYDEV_UCFG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG1 +CYDEV_UCFG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG2 +CYDEV_UCFG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG3 +CYDEV_UCFG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG4 +CYDEV_UCFG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG5 +CYDEV_UCFG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG6 +CYDEV_UCFG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_DCFG7 +CYDEV_UCFG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT0 +CYDEV_UCFG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT1 +CYDEV_UCFG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT2 +CYDEV_UCFG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT3 +CYDEV_UCFG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT4 +CYDEV_UCFG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT5 +CYDEV_UCFG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT6 +CYDEV_UCFG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT7 +CYDEV_UCFG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT8 +CYDEV_UCFG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT9 +CYDEV_UCFG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT10 +CYDEV_UCFG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_IT11 +CYDEV_UCFG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT0 +CYDEV_UCFG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT1 +CYDEV_UCFG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT2 +CYDEV_UCFG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_PLD_ORT3 +CYDEV_UCFG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG0 +CYDEV_UCFG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG1 +CYDEV_UCFG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG2 +CYDEV_UCFG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG3 +CYDEV_UCFG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG4 +CYDEV_UCFG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG5 +CYDEV_UCFG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG6 +CYDEV_UCFG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG7 +CYDEV_UCFG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG8 +CYDEV_UCFG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG9 +CYDEV_UCFG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG10 +CYDEV_UCFG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG11 +CYDEV_UCFG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG12 +CYDEV_UCFG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG13 +CYDEV_UCFG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG14 +CYDEV_UCFG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG15 +CYDEV_UCFG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG16 +CYDEV_UCFG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG17 +CYDEV_UCFG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG18 +CYDEV_UCFG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG19 +CYDEV_UCFG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG20 +CYDEV_UCFG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG21 +CYDEV_UCFG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG22 +CYDEV_UCFG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG23 +CYDEV_UCFG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG24 +CYDEV_UCFG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG25 +CYDEV_UCFG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG26 +CYDEV_UCFG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG27 +CYDEV_UCFG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG28 +CYDEV_UCFG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG29 +CYDEV_UCFG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG30 +CYDEV_UCFG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_CFG31 +CYDEV_UCFG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG0 +CYDEV_UCFG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG1 +CYDEV_UCFG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG2 +CYDEV_UCFG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG3 +CYDEV_UCFG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG4 +CYDEV_UCFG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG5 +CYDEV_UCFG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG6 +CYDEV_UCFG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_DCFG7 +CYDEV_UCFG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT0 +CYDEV_UCFG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT1 +CYDEV_UCFG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT2 +CYDEV_UCFG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT3 +CYDEV_UCFG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT4 +CYDEV_UCFG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT5 +CYDEV_UCFG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT6 +CYDEV_UCFG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT7 +CYDEV_UCFG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT8 +CYDEV_UCFG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT9 +CYDEV_UCFG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT10 +CYDEV_UCFG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_IT11 +CYDEV_UCFG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT0 +CYDEV_UCFG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT1 +CYDEV_UCFG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT2 +CYDEV_UCFG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_PLD_ORT3 +CYDEV_UCFG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG0 +CYDEV_UCFG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG1 +CYDEV_UCFG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG2 +CYDEV_UCFG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG3 +CYDEV_UCFG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG4 +CYDEV_UCFG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG5 +CYDEV_UCFG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG6 +CYDEV_UCFG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG7 +CYDEV_UCFG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG8 +CYDEV_UCFG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG9 +CYDEV_UCFG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG10 +CYDEV_UCFG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG11 +CYDEV_UCFG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG12 +CYDEV_UCFG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG13 +CYDEV_UCFG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG14 +CYDEV_UCFG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG15 +CYDEV_UCFG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG16 +CYDEV_UCFG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG17 +CYDEV_UCFG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG18 +CYDEV_UCFG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG19 +CYDEV_UCFG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG20 +CYDEV_UCFG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG21 +CYDEV_UCFG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG22 +CYDEV_UCFG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG23 +CYDEV_UCFG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG24 +CYDEV_UCFG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG25 +CYDEV_UCFG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG26 +CYDEV_UCFG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG27 +CYDEV_UCFG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG28 +CYDEV_UCFG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG29 +CYDEV_UCFG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG30 +CYDEV_UCFG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_CFG31 +CYDEV_UCFG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG0 +CYDEV_UCFG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG1 +CYDEV_UCFG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG2 +CYDEV_UCFG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG3 +CYDEV_UCFG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG4 +CYDEV_UCFG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG5 +CYDEV_UCFG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG6 +CYDEV_UCFG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_DCFG7 +CYDEV_UCFG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT0 +CYDEV_UCFG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT1 +CYDEV_UCFG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT2 +CYDEV_UCFG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT3 +CYDEV_UCFG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT4 +CYDEV_UCFG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT5 +CYDEV_UCFG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT6 +CYDEV_UCFG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT7 +CYDEV_UCFG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT8 +CYDEV_UCFG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT9 +CYDEV_UCFG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT10 +CYDEV_UCFG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_IT11 +CYDEV_UCFG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT0 +CYDEV_UCFG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT1 +CYDEV_UCFG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT2 +CYDEV_UCFG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_PLD_ORT3 +CYDEV_UCFG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG0 +CYDEV_UCFG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG1 +CYDEV_UCFG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG2 +CYDEV_UCFG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG3 +CYDEV_UCFG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG4 +CYDEV_UCFG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG5 +CYDEV_UCFG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG6 +CYDEV_UCFG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG7 +CYDEV_UCFG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG8 +CYDEV_UCFG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG9 +CYDEV_UCFG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG10 +CYDEV_UCFG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG11 +CYDEV_UCFG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG12 +CYDEV_UCFG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG13 +CYDEV_UCFG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG14 +CYDEV_UCFG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG15 +CYDEV_UCFG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG16 +CYDEV_UCFG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG17 +CYDEV_UCFG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG18 +CYDEV_UCFG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG19 +CYDEV_UCFG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG20 +CYDEV_UCFG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG21 +CYDEV_UCFG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG22 +CYDEV_UCFG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG23 +CYDEV_UCFG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG24 +CYDEV_UCFG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG25 +CYDEV_UCFG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG26 +CYDEV_UCFG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG27 +CYDEV_UCFG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG28 +CYDEV_UCFG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG29 +CYDEV_UCFG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG30 +CYDEV_UCFG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_CFG31 +CYDEV_UCFG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG0 +CYDEV_UCFG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG1 +CYDEV_UCFG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG2 +CYDEV_UCFG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG3 +CYDEV_UCFG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG4 +CYDEV_UCFG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG5 +CYDEV_UCFG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG6 +CYDEV_UCFG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_DCFG7 +CYDEV_UCFG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT0 +CYDEV_UCFG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT1 +CYDEV_UCFG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT2 +CYDEV_UCFG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT3 +CYDEV_UCFG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT4 +CYDEV_UCFG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT5 +CYDEV_UCFG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT6 +CYDEV_UCFG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT7 +CYDEV_UCFG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT8 +CYDEV_UCFG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT9 +CYDEV_UCFG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT10 +CYDEV_UCFG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_IT11 +CYDEV_UCFG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT0 +CYDEV_UCFG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT1 +CYDEV_UCFG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT2 +CYDEV_UCFG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_PLD_ORT3 +CYDEV_UCFG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG0 +CYDEV_UCFG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG1 +CYDEV_UCFG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG2 +CYDEV_UCFG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG3 +CYDEV_UCFG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG4 +CYDEV_UCFG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG5 +CYDEV_UCFG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG6 +CYDEV_UCFG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG7 +CYDEV_UCFG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG8 +CYDEV_UCFG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG9 +CYDEV_UCFG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG10 +CYDEV_UCFG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG11 +CYDEV_UCFG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG12 +CYDEV_UCFG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG13 +CYDEV_UCFG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG14 +CYDEV_UCFG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG15 +CYDEV_UCFG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG16 +CYDEV_UCFG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG17 +CYDEV_UCFG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG18 +CYDEV_UCFG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG19 +CYDEV_UCFG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG20 +CYDEV_UCFG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG21 +CYDEV_UCFG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG22 +CYDEV_UCFG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG23 +CYDEV_UCFG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG24 +CYDEV_UCFG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG25 +CYDEV_UCFG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG26 +CYDEV_UCFG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG27 +CYDEV_UCFG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG28 +CYDEV_UCFG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG29 +CYDEV_UCFG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG30 +CYDEV_UCFG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_CFG31 +CYDEV_UCFG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG0 +CYDEV_UCFG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG1 +CYDEV_UCFG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG2 +CYDEV_UCFG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG3 +CYDEV_UCFG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG4 +CYDEV_UCFG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG5 +CYDEV_UCFG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG6 +CYDEV_UCFG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_DCFG7 +CYDEV_UCFG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT0 +CYDEV_UCFG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT1 +CYDEV_UCFG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT2 +CYDEV_UCFG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT3 +CYDEV_UCFG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT4 +CYDEV_UCFG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT5 +CYDEV_UCFG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT6 +CYDEV_UCFG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT7 +CYDEV_UCFG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT8 +CYDEV_UCFG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT9 +CYDEV_UCFG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT10 +CYDEV_UCFG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_IT11 +CYDEV_UCFG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT0 +CYDEV_UCFG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT1 +CYDEV_UCFG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT2 +CYDEV_UCFG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_PLD_ORT3 +CYDEV_UCFG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG0 +CYDEV_UCFG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG1 +CYDEV_UCFG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG2 +CYDEV_UCFG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG3 +CYDEV_UCFG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG4 +CYDEV_UCFG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG5 +CYDEV_UCFG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG6 +CYDEV_UCFG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG7 +CYDEV_UCFG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG8 +CYDEV_UCFG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG9 +CYDEV_UCFG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG10 +CYDEV_UCFG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG11 +CYDEV_UCFG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG12 +CYDEV_UCFG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG13 +CYDEV_UCFG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG14 +CYDEV_UCFG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG15 +CYDEV_UCFG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG16 +CYDEV_UCFG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG17 +CYDEV_UCFG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG18 +CYDEV_UCFG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG19 +CYDEV_UCFG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG20 +CYDEV_UCFG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG21 +CYDEV_UCFG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG22 +CYDEV_UCFG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG23 +CYDEV_UCFG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG24 +CYDEV_UCFG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG25 +CYDEV_UCFG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG26 +CYDEV_UCFG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG27 +CYDEV_UCFG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG28 +CYDEV_UCFG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG29 +CYDEV_UCFG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG30 +CYDEV_UCFG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_CFG31 +CYDEV_UCFG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG0 +CYDEV_UCFG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG1 +CYDEV_UCFG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG2 +CYDEV_UCFG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG3 +CYDEV_UCFG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG4 +CYDEV_UCFG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG5 +CYDEV_UCFG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG6 +CYDEV_UCFG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_DCFG7 +CYDEV_UCFG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT0 +CYDEV_UCFG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT1 +CYDEV_UCFG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT2 +CYDEV_UCFG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT3 +CYDEV_UCFG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT4 +CYDEV_UCFG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT5 +CYDEV_UCFG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT6 +CYDEV_UCFG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT7 +CYDEV_UCFG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT8 +CYDEV_UCFG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT9 +CYDEV_UCFG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT10 +CYDEV_UCFG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_IT11 +CYDEV_UCFG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT0 +CYDEV_UCFG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT1 +CYDEV_UCFG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT2 +CYDEV_UCFG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_PLD_ORT3 +CYDEV_UCFG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG0 +CYDEV_UCFG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG1 +CYDEV_UCFG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG2 +CYDEV_UCFG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG3 +CYDEV_UCFG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG4 +CYDEV_UCFG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG5 +CYDEV_UCFG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG6 +CYDEV_UCFG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG7 +CYDEV_UCFG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG8 +CYDEV_UCFG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG9 +CYDEV_UCFG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG10 +CYDEV_UCFG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG11 +CYDEV_UCFG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG12 +CYDEV_UCFG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG13 +CYDEV_UCFG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG14 +CYDEV_UCFG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG15 +CYDEV_UCFG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG16 +CYDEV_UCFG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG17 +CYDEV_UCFG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG18 +CYDEV_UCFG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG19 +CYDEV_UCFG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG20 +CYDEV_UCFG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG21 +CYDEV_UCFG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG22 +CYDEV_UCFG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG23 +CYDEV_UCFG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG24 +CYDEV_UCFG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG25 +CYDEV_UCFG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG26 +CYDEV_UCFG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG27 +CYDEV_UCFG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG28 +CYDEV_UCFG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG29 +CYDEV_UCFG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG30 +CYDEV_UCFG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_CFG31 +CYDEV_UCFG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG0 +CYDEV_UCFG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG1 +CYDEV_UCFG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG2 +CYDEV_UCFG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG3 +CYDEV_UCFG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG4 +CYDEV_UCFG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG5 +CYDEV_UCFG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG6 +CYDEV_UCFG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_DCFG7 +CYDEV_UCFG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT0 +CYDEV_UCFG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT1 +CYDEV_UCFG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT2 +CYDEV_UCFG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT3 +CYDEV_UCFG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT4 +CYDEV_UCFG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT5 +CYDEV_UCFG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT6 +CYDEV_UCFG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT7 +CYDEV_UCFG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT8 +CYDEV_UCFG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT9 +CYDEV_UCFG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT10 +CYDEV_UCFG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_IT11 +CYDEV_UCFG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT0 +CYDEV_UCFG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT1 +CYDEV_UCFG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT2 +CYDEV_UCFG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_PLD_ORT3 +CYDEV_UCFG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG0 +CYDEV_UCFG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG1 +CYDEV_UCFG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG2 +CYDEV_UCFG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG3 +CYDEV_UCFG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG4 +CYDEV_UCFG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG5 +CYDEV_UCFG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG6 +CYDEV_UCFG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG7 +CYDEV_UCFG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG8 +CYDEV_UCFG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG9 +CYDEV_UCFG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG10 +CYDEV_UCFG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG11 +CYDEV_UCFG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG12 +CYDEV_UCFG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG13 +CYDEV_UCFG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG14 +CYDEV_UCFG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG15 +CYDEV_UCFG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG16 +CYDEV_UCFG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG17 +CYDEV_UCFG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG18 +CYDEV_UCFG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG19 +CYDEV_UCFG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG20 +CYDEV_UCFG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG21 +CYDEV_UCFG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG22 +CYDEV_UCFG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG23 +CYDEV_UCFG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG24 +CYDEV_UCFG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG25 +CYDEV_UCFG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG26 +CYDEV_UCFG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG27 +CYDEV_UCFG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG28 +CYDEV_UCFG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG29 +CYDEV_UCFG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG30 +CYDEV_UCFG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_CFG31 +CYDEV_UCFG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG0 +CYDEV_UCFG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG1 +CYDEV_UCFG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG2 +CYDEV_UCFG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG3 +CYDEV_UCFG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG4 +CYDEV_UCFG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG5 +CYDEV_UCFG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG6 +CYDEV_UCFG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_DCFG7 +CYDEV_UCFG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT0 +CYDEV_UCFG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT1 +CYDEV_UCFG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT2 +CYDEV_UCFG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT3 +CYDEV_UCFG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT4 +CYDEV_UCFG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT5 +CYDEV_UCFG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT6 +CYDEV_UCFG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT7 +CYDEV_UCFG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT8 +CYDEV_UCFG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT9 +CYDEV_UCFG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT10 +CYDEV_UCFG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_IT11 +CYDEV_UCFG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT0 +CYDEV_UCFG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT1 +CYDEV_UCFG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT2 +CYDEV_UCFG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_PLD_ORT3 +CYDEV_UCFG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG0 +CYDEV_UCFG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG1 +CYDEV_UCFG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG2 +CYDEV_UCFG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG3 +CYDEV_UCFG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG4 +CYDEV_UCFG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG5 +CYDEV_UCFG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG6 +CYDEV_UCFG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG7 +CYDEV_UCFG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG8 +CYDEV_UCFG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG9 +CYDEV_UCFG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG10 +CYDEV_UCFG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG11 +CYDEV_UCFG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG12 +CYDEV_UCFG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG13 +CYDEV_UCFG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG14 +CYDEV_UCFG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG15 +CYDEV_UCFG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG16 +CYDEV_UCFG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG17 +CYDEV_UCFG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG18 +CYDEV_UCFG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG19 +CYDEV_UCFG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG20 +CYDEV_UCFG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG21 +CYDEV_UCFG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG22 +CYDEV_UCFG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG23 +CYDEV_UCFG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG24 +CYDEV_UCFG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG25 +CYDEV_UCFG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG26 +CYDEV_UCFG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG27 +CYDEV_UCFG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG28 +CYDEV_UCFG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG29 +CYDEV_UCFG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG30 +CYDEV_UCFG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_CFG31 +CYDEV_UCFG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG0 +CYDEV_UCFG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG1 +CYDEV_UCFG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG2 +CYDEV_UCFG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG3 +CYDEV_UCFG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG4 +CYDEV_UCFG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG5 +CYDEV_UCFG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG6 +CYDEV_UCFG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_DCFG7 +CYDEV_UCFG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT0 +CYDEV_UCFG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT1 +CYDEV_UCFG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT2 +CYDEV_UCFG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT3 +CYDEV_UCFG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT4 +CYDEV_UCFG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT5 +CYDEV_UCFG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT6 +CYDEV_UCFG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT7 +CYDEV_UCFG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT8 +CYDEV_UCFG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT9 +CYDEV_UCFG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT10 +CYDEV_UCFG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_IT11 +CYDEV_UCFG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT0 +CYDEV_UCFG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT1 +CYDEV_UCFG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT2 +CYDEV_UCFG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_PLD_ORT3 +CYDEV_UCFG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB +CYDEV_UCFG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS +CYDEV_UCFG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG0 +CYDEV_UCFG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG1 +CYDEV_UCFG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG2 +CYDEV_UCFG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG3 +CYDEV_UCFG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG4 +CYDEV_UCFG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG5 +CYDEV_UCFG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG6 +CYDEV_UCFG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG7 +CYDEV_UCFG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG8 +CYDEV_UCFG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG9 +CYDEV_UCFG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG10 +CYDEV_UCFG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG11 +CYDEV_UCFG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG12 +CYDEV_UCFG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG13 +CYDEV_UCFG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG14 +CYDEV_UCFG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG15 +CYDEV_UCFG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG16 +CYDEV_UCFG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG17 +CYDEV_UCFG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG18 +CYDEV_UCFG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG19 +CYDEV_UCFG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG20 +CYDEV_UCFG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG21 +CYDEV_UCFG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG22 +CYDEV_UCFG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG23 +CYDEV_UCFG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG24 +CYDEV_UCFG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG25 +CYDEV_UCFG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG26 +CYDEV_UCFG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG27 +CYDEV_UCFG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG28 +CYDEV_UCFG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG29 +CYDEV_UCFG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG30 +CYDEV_UCFG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_CFG31 +CYDEV_UCFG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG0 +CYDEV_UCFG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG1 +CYDEV_UCFG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG2 +CYDEV_UCFG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG3 +CYDEV_UCFG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG4 +CYDEV_UCFG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG5 +CYDEV_UCFG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG6 +CYDEV_UCFG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_DCFG7 +CYDEV_UCFG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT0 +CYDEV_UCFG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT1 +CYDEV_UCFG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT2 +CYDEV_UCFG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT3 +CYDEV_UCFG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT4 +CYDEV_UCFG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT5 +CYDEV_UCFG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT6 +CYDEV_UCFG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT7 +CYDEV_UCFG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT8 +CYDEV_UCFG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT9 +CYDEV_UCFG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT10 +CYDEV_UCFG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_IT11 +CYDEV_UCFG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT0 +CYDEV_UCFG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT1 +CYDEV_UCFG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT2 +CYDEV_UCFG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_PLD_ORT3 +CYDEV_UCFG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG0 +CYDEV_UCFG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG1 +CYDEV_UCFG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG2 +CYDEV_UCFG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG3 +CYDEV_UCFG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG4 +CYDEV_UCFG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG5 +CYDEV_UCFG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG6 +CYDEV_UCFG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG7 +CYDEV_UCFG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG8 +CYDEV_UCFG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG9 +CYDEV_UCFG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG10 +CYDEV_UCFG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG11 +CYDEV_UCFG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG12 +CYDEV_UCFG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG13 +CYDEV_UCFG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG14 +CYDEV_UCFG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG15 +CYDEV_UCFG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG16 +CYDEV_UCFG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG17 +CYDEV_UCFG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG18 +CYDEV_UCFG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG19 +CYDEV_UCFG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG20 +CYDEV_UCFG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG21 +CYDEV_UCFG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG22 +CYDEV_UCFG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG23 +CYDEV_UCFG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG24 +CYDEV_UCFG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG25 +CYDEV_UCFG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG26 +CYDEV_UCFG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG27 +CYDEV_UCFG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG28 +CYDEV_UCFG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG29 +CYDEV_UCFG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG30 +CYDEV_UCFG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_CFG31 +CYDEV_UCFG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG0 +CYDEV_UCFG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG1 +CYDEV_UCFG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG2 +CYDEV_UCFG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG3 +CYDEV_UCFG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG4 +CYDEV_UCFG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG5 +CYDEV_UCFG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG6 +CYDEV_UCFG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_DCFG7 +CYDEV_UCFG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT0 +CYDEV_UCFG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT1 +CYDEV_UCFG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT2 +CYDEV_UCFG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT3 +CYDEV_UCFG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT4 +CYDEV_UCFG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT5 +CYDEV_UCFG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT6 +CYDEV_UCFG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT7 +CYDEV_UCFG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT8 +CYDEV_UCFG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT9 +CYDEV_UCFG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT10 +CYDEV_UCFG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_IT11 +CYDEV_UCFG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT0 +CYDEV_UCFG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT1 +CYDEV_UCFG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT2 +CYDEV_UCFG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_PLD_ORT3 +CYDEV_UCFG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG0 +CYDEV_UCFG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG1 +CYDEV_UCFG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG2 +CYDEV_UCFG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG3 +CYDEV_UCFG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG4 +CYDEV_UCFG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG5 +CYDEV_UCFG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG6 +CYDEV_UCFG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG7 +CYDEV_UCFG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG8 +CYDEV_UCFG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG9 +CYDEV_UCFG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG10 +CYDEV_UCFG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG11 +CYDEV_UCFG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG12 +CYDEV_UCFG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG13 +CYDEV_UCFG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG14 +CYDEV_UCFG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG15 +CYDEV_UCFG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG16 +CYDEV_UCFG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG17 +CYDEV_UCFG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG18 +CYDEV_UCFG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG19 +CYDEV_UCFG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG20 +CYDEV_UCFG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG21 +CYDEV_UCFG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG22 +CYDEV_UCFG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG23 +CYDEV_UCFG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG24 +CYDEV_UCFG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG25 +CYDEV_UCFG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG26 +CYDEV_UCFG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG27 +CYDEV_UCFG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG28 +CYDEV_UCFG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG29 +CYDEV_UCFG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG30 +CYDEV_UCFG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_CFG31 +CYDEV_UCFG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG0 +CYDEV_UCFG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG1 +CYDEV_UCFG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG2 +CYDEV_UCFG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG3 +CYDEV_UCFG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG4 +CYDEV_UCFG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG5 +CYDEV_UCFG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG6 +CYDEV_UCFG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_DCFG7 +CYDEV_UCFG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT0 +CYDEV_UCFG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT1 +CYDEV_UCFG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT2 +CYDEV_UCFG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT3 +CYDEV_UCFG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT4 +CYDEV_UCFG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT5 +CYDEV_UCFG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT6 +CYDEV_UCFG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT7 +CYDEV_UCFG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT8 +CYDEV_UCFG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT9 +CYDEV_UCFG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT10 +CYDEV_UCFG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_IT11 +CYDEV_UCFG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT0 +CYDEV_UCFG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT1 +CYDEV_UCFG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT2 +CYDEV_UCFG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_PLD_ORT3 +CYDEV_UCFG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG0 +CYDEV_UCFG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG1 +CYDEV_UCFG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG2 +CYDEV_UCFG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG3 +CYDEV_UCFG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG4 +CYDEV_UCFG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG5 +CYDEV_UCFG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG6 +CYDEV_UCFG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG7 +CYDEV_UCFG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG8 +CYDEV_UCFG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG9 +CYDEV_UCFG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG10 +CYDEV_UCFG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG11 +CYDEV_UCFG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG12 +CYDEV_UCFG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG13 +CYDEV_UCFG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG14 +CYDEV_UCFG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG15 +CYDEV_UCFG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG16 +CYDEV_UCFG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG17 +CYDEV_UCFG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG18 +CYDEV_UCFG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG19 +CYDEV_UCFG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG20 +CYDEV_UCFG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG21 +CYDEV_UCFG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG22 +CYDEV_UCFG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG23 +CYDEV_UCFG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG24 +CYDEV_UCFG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG25 +CYDEV_UCFG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG26 +CYDEV_UCFG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG27 +CYDEV_UCFG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG28 +CYDEV_UCFG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG29 +CYDEV_UCFG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG30 +CYDEV_UCFG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_CFG31 +CYDEV_UCFG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG0 +CYDEV_UCFG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG1 +CYDEV_UCFG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG2 +CYDEV_UCFG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG3 +CYDEV_UCFG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG4 +CYDEV_UCFG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG5 +CYDEV_UCFG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG6 +CYDEV_UCFG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_DCFG7 +CYDEV_UCFG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT0 +CYDEV_UCFG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT1 +CYDEV_UCFG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT2 +CYDEV_UCFG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT3 +CYDEV_UCFG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT4 +CYDEV_UCFG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT5 +CYDEV_UCFG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT6 +CYDEV_UCFG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT7 +CYDEV_UCFG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT8 +CYDEV_UCFG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT9 +CYDEV_UCFG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT10 +CYDEV_UCFG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_IT11 +CYDEV_UCFG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT0 +CYDEV_UCFG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT1 +CYDEV_UCFG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT2 +CYDEV_UCFG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_PLD_ORT3 +CYDEV_UCFG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG0 +CYDEV_UCFG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG1 +CYDEV_UCFG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG2 +CYDEV_UCFG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG3 +CYDEV_UCFG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG4 +CYDEV_UCFG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG5 +CYDEV_UCFG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG6 +CYDEV_UCFG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG7 +CYDEV_UCFG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG8 +CYDEV_UCFG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG9 +CYDEV_UCFG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG10 +CYDEV_UCFG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG11 +CYDEV_UCFG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG12 +CYDEV_UCFG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG13 +CYDEV_UCFG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG14 +CYDEV_UCFG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG15 +CYDEV_UCFG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG16 +CYDEV_UCFG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG17 +CYDEV_UCFG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG18 +CYDEV_UCFG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG19 +CYDEV_UCFG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG20 +CYDEV_UCFG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG21 +CYDEV_UCFG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG22 +CYDEV_UCFG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG23 +CYDEV_UCFG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG24 +CYDEV_UCFG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG25 +CYDEV_UCFG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG26 +CYDEV_UCFG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG27 +CYDEV_UCFG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG28 +CYDEV_UCFG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG29 +CYDEV_UCFG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG30 +CYDEV_UCFG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_CFG31 +CYDEV_UCFG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG0 +CYDEV_UCFG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG1 +CYDEV_UCFG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG2 +CYDEV_UCFG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG3 +CYDEV_UCFG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG4 +CYDEV_UCFG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG5 +CYDEV_UCFG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG6 +CYDEV_UCFG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_DCFG7 +CYDEV_UCFG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT0 +CYDEV_UCFG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT1 +CYDEV_UCFG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT2 +CYDEV_UCFG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT3 +CYDEV_UCFG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT4 +CYDEV_UCFG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT5 +CYDEV_UCFG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT6 +CYDEV_UCFG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT7 +CYDEV_UCFG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT8 +CYDEV_UCFG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT9 +CYDEV_UCFG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT10 +CYDEV_UCFG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_IT11 +CYDEV_UCFG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT0 +CYDEV_UCFG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT1 +CYDEV_UCFG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT2 +CYDEV_UCFG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_PLD_ORT3 +CYDEV_UCFG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG0 +CYDEV_UCFG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG1 +CYDEV_UCFG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG2 +CYDEV_UCFG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG3 +CYDEV_UCFG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG4 +CYDEV_UCFG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG5 +CYDEV_UCFG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG6 +CYDEV_UCFG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG7 +CYDEV_UCFG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG8 +CYDEV_UCFG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG9 +CYDEV_UCFG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG10 +CYDEV_UCFG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG11 +CYDEV_UCFG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG12 +CYDEV_UCFG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG13 +CYDEV_UCFG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG14 +CYDEV_UCFG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG15 +CYDEV_UCFG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG16 +CYDEV_UCFG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG17 +CYDEV_UCFG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG18 +CYDEV_UCFG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG19 +CYDEV_UCFG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG20 +CYDEV_UCFG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG21 +CYDEV_UCFG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG22 +CYDEV_UCFG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG23 +CYDEV_UCFG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG24 +CYDEV_UCFG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG25 +CYDEV_UCFG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG26 +CYDEV_UCFG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG27 +CYDEV_UCFG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG28 +CYDEV_UCFG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG29 +CYDEV_UCFG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG30 +CYDEV_UCFG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_CFG31 +CYDEV_UCFG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG0 +CYDEV_UCFG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG1 +CYDEV_UCFG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG2 +CYDEV_UCFG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG3 +CYDEV_UCFG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG4 +CYDEV_UCFG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG5 +CYDEV_UCFG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG6 +CYDEV_UCFG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_DCFG7 +CYDEV_UCFG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT0 +CYDEV_UCFG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT1 +CYDEV_UCFG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT2 +CYDEV_UCFG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT3 +CYDEV_UCFG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT4 +CYDEV_UCFG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT5 +CYDEV_UCFG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT6 +CYDEV_UCFG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT7 +CYDEV_UCFG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT8 +CYDEV_UCFG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT9 +CYDEV_UCFG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT10 +CYDEV_UCFG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_IT11 +CYDEV_UCFG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT0 +CYDEV_UCFG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT1 +CYDEV_UCFG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT2 +CYDEV_UCFG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_PLD_ORT3 +CYDEV_UCFG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG0 +CYDEV_UCFG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG1 +CYDEV_UCFG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG2 +CYDEV_UCFG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG3 +CYDEV_UCFG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG4 +CYDEV_UCFG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG5 +CYDEV_UCFG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG6 +CYDEV_UCFG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG7 +CYDEV_UCFG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG8 +CYDEV_UCFG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG9 +CYDEV_UCFG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG10 +CYDEV_UCFG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG11 +CYDEV_UCFG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG12 +CYDEV_UCFG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG13 +CYDEV_UCFG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG14 +CYDEV_UCFG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG15 +CYDEV_UCFG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG16 +CYDEV_UCFG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG17 +CYDEV_UCFG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG18 +CYDEV_UCFG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG19 +CYDEV_UCFG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG20 +CYDEV_UCFG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG21 +CYDEV_UCFG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG22 +CYDEV_UCFG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG23 +CYDEV_UCFG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG24 +CYDEV_UCFG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG25 +CYDEV_UCFG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG26 +CYDEV_UCFG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG27 +CYDEV_UCFG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG28 +CYDEV_UCFG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG29 +CYDEV_UCFG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG30 +CYDEV_UCFG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_CFG31 +CYDEV_UCFG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG0 +CYDEV_UCFG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG1 +CYDEV_UCFG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG2 +CYDEV_UCFG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG3 +CYDEV_UCFG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG4 +CYDEV_UCFG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG5 +CYDEV_UCFG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG6 +CYDEV_UCFG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_DCFG7 +CYDEV_UCFG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT0 +CYDEV_UCFG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT1 +CYDEV_UCFG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT2 +CYDEV_UCFG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT3 +CYDEV_UCFG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT4 +CYDEV_UCFG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT5 +CYDEV_UCFG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT6 +CYDEV_UCFG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT7 +CYDEV_UCFG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT8 +CYDEV_UCFG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT9 +CYDEV_UCFG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT10 +CYDEV_UCFG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_IT11 +CYDEV_UCFG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT0 +CYDEV_UCFG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT1 +CYDEV_UCFG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT2 +CYDEV_UCFG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_PLD_ORT3 +CYDEV_UCFG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG0 +CYDEV_UCFG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG1 +CYDEV_UCFG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG2 +CYDEV_UCFG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG3 +CYDEV_UCFG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG4 +CYDEV_UCFG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG5 +CYDEV_UCFG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG6 +CYDEV_UCFG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG7 +CYDEV_UCFG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG8 +CYDEV_UCFG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG9 +CYDEV_UCFG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG10 +CYDEV_UCFG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG11 +CYDEV_UCFG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG12 +CYDEV_UCFG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG13 +CYDEV_UCFG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG14 +CYDEV_UCFG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG15 +CYDEV_UCFG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG16 +CYDEV_UCFG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG17 +CYDEV_UCFG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG18 +CYDEV_UCFG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG19 +CYDEV_UCFG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG20 +CYDEV_UCFG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG21 +CYDEV_UCFG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG22 +CYDEV_UCFG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG23 +CYDEV_UCFG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG24 +CYDEV_UCFG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG25 +CYDEV_UCFG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG26 +CYDEV_UCFG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG27 +CYDEV_UCFG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG28 +CYDEV_UCFG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG29 +CYDEV_UCFG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG30 +CYDEV_UCFG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_CFG31 +CYDEV_UCFG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG0 +CYDEV_UCFG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG1 +CYDEV_UCFG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG2 +CYDEV_UCFG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG3 +CYDEV_UCFG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG4 +CYDEV_UCFG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG5 +CYDEV_UCFG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG6 +CYDEV_UCFG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_DCFG7 +CYDEV_UCFG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT0 +CYDEV_UCFG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT1 +CYDEV_UCFG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT2 +CYDEV_UCFG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT3 +CYDEV_UCFG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT4 +CYDEV_UCFG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT5 +CYDEV_UCFG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT6 +CYDEV_UCFG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT7 +CYDEV_UCFG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT8 +CYDEV_UCFG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT9 +CYDEV_UCFG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT10 +CYDEV_UCFG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_IT11 +CYDEV_UCFG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT0 +CYDEV_UCFG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT1 +CYDEV_UCFG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT2 +CYDEV_UCFG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_PLD_ORT3 +CYDEV_UCFG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST +CYDEV_UCFG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB +CYDEV_UCFG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET +CYDEV_UCFG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS +CYDEV_UCFG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG0 +CYDEV_UCFG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG1 +CYDEV_UCFG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG2 +CYDEV_UCFG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG3 +CYDEV_UCFG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG4 +CYDEV_UCFG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG5 +CYDEV_UCFG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG6 +CYDEV_UCFG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG7 +CYDEV_UCFG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG8 +CYDEV_UCFG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG9 +CYDEV_UCFG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG10 +CYDEV_UCFG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG11 +CYDEV_UCFG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG12 +CYDEV_UCFG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG13 +CYDEV_UCFG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG14 +CYDEV_UCFG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG15 +CYDEV_UCFG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG16 +CYDEV_UCFG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG17 +CYDEV_UCFG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG18 +CYDEV_UCFG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG19 +CYDEV_UCFG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG20 +CYDEV_UCFG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG21 +CYDEV_UCFG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG22 +CYDEV_UCFG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG23 +CYDEV_UCFG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG24 +CYDEV_UCFG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG25 +CYDEV_UCFG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG26 +CYDEV_UCFG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG27 +CYDEV_UCFG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG28 +CYDEV_UCFG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG29 +CYDEV_UCFG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG30 +CYDEV_UCFG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_CFG31 +CYDEV_UCFG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG0 +CYDEV_UCFG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG1 +CYDEV_UCFG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG2 +CYDEV_UCFG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG3 +CYDEV_UCFG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG4 +CYDEV_UCFG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG5 +CYDEV_UCFG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG6 +CYDEV_UCFG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_DCFG7 +CYDEV_UCFG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MDCLK_EN +CYDEV_UCFG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_MBCLK_EN +CYDEV_UCFG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_WAIT_CFG +CYDEV_UCFG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BANK_CTL +CYDEV_UCFG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_UDB_TEST_3 +CYDEV_UCFG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN0 +CYDEV_UCFG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN0 +CYDEV_UCFG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN1 +CYDEV_UCFG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN1 +CYDEV_UCFG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN2 +CYDEV_UCFG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN2 +CYDEV_UCFG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_DCLK_EN3 +CYDEV_UCFG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BCLK_EN3 +CYDEV_UCFG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MDCLK_EN +CYDEV_UCFG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_MBCLK_EN +CYDEV_UCFG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_WAIT_CFG +CYDEV_UCFG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BANK_CTL +CYDEV_UCFG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_UDB_TEST_3 +CYDEV_UCFG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN0 +CYDEV_UCFG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN0 +CYDEV_UCFG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN1 +CYDEV_UCFG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN1 +CYDEV_UCFG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN2 +CYDEV_UCFG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN2 +CYDEV_UCFG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_DCLK_EN3 +CYDEV_UCFG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BCLK_EN3 +CYDEV_UCFG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL0 +CYDEV_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL1 +CYDEV_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL2 +CYDEV_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL3 +CYDEV_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL4 +CYDEV_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL5 +CYDEV_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL6 +CYDEV_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_IRQ_CTL7 +CYDEV_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL0 +CYDEV_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL1 +CYDEV_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL2 +CYDEV_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL3 +CYDEV_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL4 +CYDEV_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_DRQ_CTL5 +CYDEV_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MBASE +CYDEV_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_DATA_MSIZE +CYDEV_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0 +CYDEV_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD0 +CYDEV_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO0_SEL +CYDEV_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1 +CYDEV_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD1 +CYDEV_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2 +CYDEV_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD2 +CYDEV_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO2_SEL +CYDEV_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO1_SEL +CYDEV_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3 +CYDEV_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD3 +CYDEV_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO3_SEL +CYDEV_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4 +CYDEV_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD4 +CYDEV_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO4_SEL +CYDEV_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5 +CYDEV_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD5 +CYDEV_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO5_SEL +CYDEV_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6 +CYDEV_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD6 +CYDEV_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO6_SEL +CYDEV_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12 +CYDEV_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD12 +CYDEV_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO12_SEL +CYDEV_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15 +CYDEV_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIRD15 +CYDEV_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_GPIO15_SEL +CYDEV_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_START +CYDEV_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YROLL +CYDEV_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_YCFG +CYDEV_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START1 +CYDEV_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_START2 +CYDEV_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL1 +CYDEV_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XROLL2 +CYDEV_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XINC +CYDEV_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_XCFG +CYDEV_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR1 +CYDEV_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR2 +CYDEV_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_OFFSETADDR3 +CYDEV_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR1 +CYDEV_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR2 +CYDEV_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR3 +CYDEV_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_ABSADDR4 +CYDEV_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG1 +CYDEV_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATCFG2 +CYDEV_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT1 +CYDEV_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT2 +CYDEV_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT3 +CYDEV_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_CMP_RSLT4 +CYDEV_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG1 +CYDEV_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG2 +CYDEV_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG3 +CYDEV_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_DATA_REG4 +CYDEV_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA1 +CYDEV_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA2 +CYDEV_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA3 +CYDEV_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_EXP_DATA4 +CYDEV_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA1 +CYDEV_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA2 +CYDEV_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA3 +CYDEV_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_MSTR_HRDATA4 +CYDEV_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BIST_EN +CYDEV_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_PHUB_MASTER_SSR +CYDEV_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG1 +CYDEV_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SEQCFG2 +CYDEV_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_Y_CURR +CYDEV_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR1 +CYDEV_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_X_CURR2 +CYDEV_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_STCALIB_CFG +CYDEV_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_WAITPIPE +CYDEV_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_TRACE_CFG +CYDEV_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DBG_CFG +CYDEV_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_CM3_LCKRST_STAT +CYDEV_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_DEVICE_ID +CYDEV_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MBASE +CYDEV_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_DATA_MSIZE +CYDEV_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MBASE +CYDEV_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_RSVD_MSIZE +CYDEV_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MBASE +CYDEV_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_MDATA_MSIZE +CYDEV_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_Y_LOC +CYDEV_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_X_LOC +CYDEV_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WAFER_NUM +CYDEV_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_LSB +CYDEV_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_LOT_MSB +CYDEV_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_WRK_WK +CYDEV_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_FAB_YR +CYDEV_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_MINOR +CYDEV_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ +CYDEV_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_IMO_USB +CYDEV_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYDEV_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M1 +CYDEV_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M2 +CYDEV_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M3 +CYDEV_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M4 +CYDEV_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M5 +CYDEV_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M6 +CYDEV_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M7 +CYDEV_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DEC_M8 +CYDEV_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M1 +CYDEV_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M2 +CYDEV_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M3 +CYDEV_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M4 +CYDEV_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M5 +CYDEV_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M6 +CYDEV_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M7 +CYDEV_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC0_M8 +CYDEV_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M1 +CYDEV_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M2 +CYDEV_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M3 +CYDEV_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M4 +CYDEV_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M5 +CYDEV_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M6 +CYDEV_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M7 +CYDEV_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC2_M8 +CYDEV_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M1 +CYDEV_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M2 +CYDEV_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M3 +CYDEV_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M4 +CYDEV_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M5 +CYDEV_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M6 +CYDEV_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M7 +CYDEV_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC1_M8 +CYDEV_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M1 +CYDEV_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M2 +CYDEV_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M3 +CYDEV_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M4 +CYDEV_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M5 +CYDEV_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M6 +CYDEV_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M7 +CYDEV_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_DAC3_M8 +CYDEV_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_IMO_TR1 +CYDEV_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR0 +CYDEV_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR0 +CYDEV_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR0 +CYDEV_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR0 +CYDEV_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP0_TR1 +CYDEV_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP1_TR1 +CYDEV_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP2_TR1 +CYDEV_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_CMP3_TR1 +CYDEV_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYDEV_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MBASE +CYDEV_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_DATA_MSIZE +CYDEV_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_EN +CYDEV_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_PRIVILEGE +CYDEV_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_TRACE_CTRL +CYDEV_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_ACCESS +CYDEV_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_LOCK_STATUS +CYDEV_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID4 +CYDEV_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID5 +CYDEV_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID6 +CYDEV_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID7 +CYDEV_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID0 +CYDEV_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID1 +CYDEV_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID2 +CYDEV_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_PID3 +CYDEV_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID0 +CYDEV_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID1 +CYDEV_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID2 +CYDEV_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_CID3 +CYDEV_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CTRL +CYDEV_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CYCLE_COUNT +CYDEV_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_CPI_COUNT +CYDEV_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_EXC_OVHD_COUNT +CYDEV_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SLEEP_COUNT +CYDEV_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_LSU_COUNT +CYDEV_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FOLD_COUNT +CYDEV_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_PC_SAMPLE +CYDEV_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_0 +CYDEV_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_0 +CYDEV_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_0 +CYDEV_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_1 +CYDEV_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_1 +CYDEV_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_1 +CYDEV_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_2 +CYDEV_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_2 +CYDEV_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_2 +CYDEV_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_COMP_3 +CYDEV_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_MASK_3 +CYDEV_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_FUNCTION_3 +CYDEV_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CTRL +CYDEV_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_REMAP +CYDEV_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_0 +CYDEV_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_1 +CYDEV_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_2 +CYDEV_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_3 +CYDEV_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_4 +CYDEV_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_5 +CYDEV_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_6 +CYDEV_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_FP_COMP_7 +CYDEV_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID4 +CYDEV_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID5 +CYDEV_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID6 +CYDEV_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID7 +CYDEV_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID0 +CYDEV_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID1 +CYDEV_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID2 +CYDEV_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_PID3 +CYDEV_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID0 +CYDEV_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID1 +CYDEV_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID2 +CYDEV_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_CID3 +CYDEV_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INT_CTL_TYPE +CYDEV_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CTL +CYDEV_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_RELOAD +CYDEV_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CURRENT +CYDEV_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTICK_CAL +CYDEV_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETENA0 +CYDEV_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRENA0 +CYDEV_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SETPEND0 +CYDEV_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CLRPEND0 +CYDEV_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_ACTIVE0 +CYDEV_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_0 +CYDEV_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_1 +CYDEV_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_2 +CYDEV_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_3 +CYDEV_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_4 +CYDEV_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_5 +CYDEV_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_6 +CYDEV_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_7 +CYDEV_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_8 +CYDEV_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_9 +CYDEV_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_10 +CYDEV_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_11 +CYDEV_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_12 +CYDEV_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_13 +CYDEV_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_14 +CYDEV_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_15 +CYDEV_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_16 +CYDEV_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_17 +CYDEV_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_18 +CYDEV_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_19 +CYDEV_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_20 +CYDEV_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_21 +CYDEV_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_22 +CYDEV_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_23 +CYDEV_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_24 +CYDEV_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_25 +CYDEV_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_26 +CYDEV_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_27 +CYDEV_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_28 +CYDEV_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_29 +CYDEV_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_30 +CYDEV_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_PRI_31 +CYDEV_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CPUID_BASE +CYDEV_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_INTR_CTRL_STATE +CYDEV_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_VECT_OFFSET +CYDEV_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_APPLN_INTR +CYDEV_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYSTEM_CONTROL +CYDEV_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_CFG_CONTROL +CYDEV_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 +CYDEV_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 +CYDEV_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 +CYDEV_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SYS_HANDLER_CSR +CYDEV_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_STATUS +CYDEV_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_STATUS +CYDEV_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_USAGE_FAULT_STATUS +CYDEV_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_HARD_FAULT_STATUS +CYDEV_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_DEBUG_FAULT_STATUS +CYDEV_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_MEMMAN_FAULT_ADD +CYDEV_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BUS_FAULT_ADD +CYDEV_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_HLT_CS +CYDEV_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_SEL +CYDEV_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_DBG_REG_DATA +CYDEV_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_EXC_MON_CTL +CYDEV_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ +CYDEV_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CURRENT_SYNC_PRT_SZ +CYDEV_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ASYNC_CLK_PRESCALER +CYDEV_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PROTOCOL +CYDEV_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_STAT +CYDEV_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_FORM_FLUSH_CTRL +CYDEV_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_TRIGGER +CYDEV_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITETMDATA +CYDEV_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR2 +CYDEV_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITATBCTR0 +CYDEV_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITITMDATA +CYDEV_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_ITCTRL +CYDEV_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVID +CYDEV_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_DEVTYPE +CYDEV_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID4 +CYDEV_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID5 +CYDEV_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID6 +CYDEV_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID7 +CYDEV_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID0 +CYDEV_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID1 +CYDEV_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID2 +CYDEV_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_PID3 +CYDEV_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID0 +CYDEV_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID1 +CYDEV_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID2 +CYDEV_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_CID3 +CYDEV_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CTL +CYDEV_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE +CYDEV_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRIG_EVENT +CYDEV_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_STATUS +CYDEV_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYS_CFG +CYDEV_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_ENB_EVENT +CYDEV_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TRACE_EN_CTRL1 +CYDEV_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_FIFOFULL_LEVEL +CYDEV_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SYNC_FREQ +CYDEV_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ETM_ID +CYDEV_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CFG_CODE_EXT +CYDEV_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_TR_SS_EMBICE_CTRL +CYDEV_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CS_TRACE_ID +CYDEV_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_ACCESS +CYDEV_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_OS_LOCK_STATUS +CYDEV_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PDSR +CYDEV_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITMISCIN +CYDEV_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITTRIGOUT +CYDEV_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR2 +CYDEV_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_ITATBCTR0 +CYDEV_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_INT_MODE_CTRL +CYDEV_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_SET +CYDEV_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CLM_TAG_CLR +CYDEV_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_ACCESS +CYDEV_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_LOCK_STATUS +CYDEV_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_AUTH_STATUS +CYDEV_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_DEV_TYPE +CYDEV_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID4 +CYDEV_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID5 +CYDEV_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID6 +CYDEV_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID7 +CYDEV_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID0 +CYDEV_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID1 +CYDEV_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID2 +CYDEV_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_PID3 +CYDEV_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID0 +CYDEV_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID1 +CYDEV_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID2 +CYDEV_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_CID3 +CYDEV_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_NVIC +CYDEV_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_DWT +CYDEV_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_FPB +CYDEV_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ITM +CYDEV_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_TPIU +CYDEV_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_ETM +CYDEV_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_END +CYDEV_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_MEMTYPE +CYDEV_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID4 +CYDEV_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID5 +CYDEV_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID6 +CYDEV_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID7 +CYDEV_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID0 +CYDEV_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID1 +CYDEV_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID2 +CYDEV_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_PID3 +CYDEV_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID0 +CYDEV_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID1 +CYDEV_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID2 +CYDEV_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_CID3 +CYDEV_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc new file mode 100644 index 0000000..fc79212 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc @@ -0,0 +1,16039 @@ +; +; File Name: cydevicerv_trm.inc +; +; PSoC Creator 4.2 +; +; Description: +; This file provides all of the address values for the entire PSoC device. +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:CYDEV_FLASH_BASE +CYDEV_FLASH_BASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLASH_SIZE +CYDEV_FLASH_SIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MBASE +CYREG_FLASH_DATA_MBASE EQU 0x00000000 + ENDIF + IF :LNOT::DEF:CYREG_FLASH_DATA_MSIZE +CYREG_FLASH_DATA_MSIZE EQU 0x00020000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_BASE +CYDEV_SRAM_BASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYDEV_SRAM_SIZE +CYDEV_SRAM_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MBASE +CYREG_SRAM_CODE64K_MBASE EQU 0x1fff8000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE64K_MSIZE +CYREG_SRAM_CODE64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MBASE +CYREG_SRAM_CODE32K_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE32K_MSIZE +CYREG_SRAM_CODE32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MBASE +CYREG_SRAM_CODE16K_MBASE EQU 0x1fffe000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE16K_MSIZE +CYREG_SRAM_CODE16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MBASE +CYREG_SRAM_CODE_MBASE EQU 0x1fffc000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_CODE_MSIZE +CYREG_SRAM_CODE_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MBASE +CYREG_SRAM_DATA_MBASE EQU 0x20000000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA_MSIZE +CYREG_SRAM_DATA_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MBASE +CYREG_SRAM_DATA16K_MBASE EQU 0x20001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA16K_MSIZE +CYREG_SRAM_DATA16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MBASE +CYREG_SRAM_DATA32K_MBASE EQU 0x20002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA32K_MSIZE +CYREG_SRAM_DATA32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MBASE +CYREG_SRAM_DATA64K_MBASE EQU 0x20004000 + ENDIF + IF :LNOT::DEF:CYREG_SRAM_DATA64K_MSIZE +CYREG_SRAM_DATA64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_BASE +CYDEV_DMA_BASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYDEV_DMA_SIZE +CYDEV_DMA_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MBASE +CYREG_DMA_SRAM64K_MBASE EQU 0x20008000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM64K_MSIZE +CYREG_DMA_SRAM64K_MSIZE EQU 0x00004000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MBASE +CYREG_DMA_SRAM32K_MBASE EQU 0x2000c000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM32K_MSIZE +CYREG_DMA_SRAM32K_MSIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MBASE +CYREG_DMA_SRAM16K_MBASE EQU 0x2000e000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM16K_MSIZE +CYREG_DMA_SRAM16K_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MBASE +CYREG_DMA_SRAM_MBASE EQU 0x2000f000 + ENDIF + IF :LNOT::DEF:CYREG_DMA_SRAM_MSIZE +CYREG_DMA_SRAM_MSIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_BASE +CYDEV_CLKDIST_BASE EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_SIZE +CYDEV_CLKDIST_SIZE EQU 0x00000110 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_CR +CYREG_CLKDIST_CR EQU 0x40004000 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_LD +CYREG_CLKDIST_LD EQU 0x40004001 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK0 +CYREG_CLKDIST_WRK0 EQU 0x40004002 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_WRK1 +CYREG_CLKDIST_WRK1 EQU 0x40004003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR0 +CYREG_CLKDIST_MSTR0 EQU 0x40004004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_MSTR1 +CYREG_CLKDIST_MSTR1 EQU 0x40004005 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG0 +CYREG_CLKDIST_BCFG0 EQU 0x40004006 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG1 +CYREG_CLKDIST_BCFG1 EQU 0x40004007 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_BCFG2 +CYREG_CLKDIST_BCFG2 EQU 0x40004008 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_UCFG +CYREG_CLKDIST_UCFG EQU 0x40004009 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY0 +CYREG_CLKDIST_DLY0 EQU 0x4000400a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DLY1 +CYREG_CLKDIST_DLY1 EQU 0x4000400b + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DMASK +CYREG_CLKDIST_DMASK EQU 0x40004010 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_AMASK +CYREG_CLKDIST_AMASK EQU 0x40004014 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_BASE +CYDEV_CLKDIST_DCFG0_BASE EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG0_SIZE +CYDEV_CLKDIST_DCFG0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG0 +CYREG_CLKDIST_DCFG0_CFG0 EQU 0x40004080 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG1 +CYREG_CLKDIST_DCFG0_CFG1 EQU 0x40004081 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG0_CFG2 +CYREG_CLKDIST_DCFG0_CFG2 EQU 0x40004082 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_BASE +CYDEV_CLKDIST_DCFG1_BASE EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG1_SIZE +CYDEV_CLKDIST_DCFG1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG0 +CYREG_CLKDIST_DCFG1_CFG0 EQU 0x40004084 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG1 +CYREG_CLKDIST_DCFG1_CFG1 EQU 0x40004085 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG1_CFG2 +CYREG_CLKDIST_DCFG1_CFG2 EQU 0x40004086 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_BASE +CYDEV_CLKDIST_DCFG2_BASE EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG2_SIZE +CYDEV_CLKDIST_DCFG2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG0 +CYREG_CLKDIST_DCFG2_CFG0 EQU 0x40004088 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG1 +CYREG_CLKDIST_DCFG2_CFG1 EQU 0x40004089 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG2_CFG2 +CYREG_CLKDIST_DCFG2_CFG2 EQU 0x4000408a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_BASE +CYDEV_CLKDIST_DCFG3_BASE EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG3_SIZE +CYDEV_CLKDIST_DCFG3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG0 +CYREG_CLKDIST_DCFG3_CFG0 EQU 0x4000408c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG1 +CYREG_CLKDIST_DCFG3_CFG1 EQU 0x4000408d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG3_CFG2 +CYREG_CLKDIST_DCFG3_CFG2 EQU 0x4000408e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_BASE +CYDEV_CLKDIST_DCFG4_BASE EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG4_SIZE +CYDEV_CLKDIST_DCFG4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG0 +CYREG_CLKDIST_DCFG4_CFG0 EQU 0x40004090 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG1 +CYREG_CLKDIST_DCFG4_CFG1 EQU 0x40004091 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG4_CFG2 +CYREG_CLKDIST_DCFG4_CFG2 EQU 0x40004092 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_BASE +CYDEV_CLKDIST_DCFG5_BASE EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG5_SIZE +CYDEV_CLKDIST_DCFG5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG0 +CYREG_CLKDIST_DCFG5_CFG0 EQU 0x40004094 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG1 +CYREG_CLKDIST_DCFG5_CFG1 EQU 0x40004095 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG5_CFG2 +CYREG_CLKDIST_DCFG5_CFG2 EQU 0x40004096 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_BASE +CYDEV_CLKDIST_DCFG6_BASE EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG6_SIZE +CYDEV_CLKDIST_DCFG6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG0 +CYREG_CLKDIST_DCFG6_CFG0 EQU 0x40004098 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG1 +CYREG_CLKDIST_DCFG6_CFG1 EQU 0x40004099 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG6_CFG2 +CYREG_CLKDIST_DCFG6_CFG2 EQU 0x4000409a + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_BASE +CYDEV_CLKDIST_DCFG7_BASE EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_DCFG7_SIZE +CYDEV_CLKDIST_DCFG7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG0 +CYREG_CLKDIST_DCFG7_CFG0 EQU 0x4000409c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG1 +CYREG_CLKDIST_DCFG7_CFG1 EQU 0x4000409d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_DCFG7_CFG2 +CYREG_CLKDIST_DCFG7_CFG2 EQU 0x4000409e + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_BASE +CYDEV_CLKDIST_ACFG0_BASE EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG0_SIZE +CYDEV_CLKDIST_ACFG0_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG0 +CYREG_CLKDIST_ACFG0_CFG0 EQU 0x40004100 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG1 +CYREG_CLKDIST_ACFG0_CFG1 EQU 0x40004101 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG2 +CYREG_CLKDIST_ACFG0_CFG2 EQU 0x40004102 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG0_CFG3 +CYREG_CLKDIST_ACFG0_CFG3 EQU 0x40004103 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_BASE +CYDEV_CLKDIST_ACFG1_BASE EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG1_SIZE +CYDEV_CLKDIST_ACFG1_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG0 +CYREG_CLKDIST_ACFG1_CFG0 EQU 0x40004104 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG1 +CYREG_CLKDIST_ACFG1_CFG1 EQU 0x40004105 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG2 +CYREG_CLKDIST_ACFG1_CFG2 EQU 0x40004106 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG1_CFG3 +CYREG_CLKDIST_ACFG1_CFG3 EQU 0x40004107 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_BASE +CYDEV_CLKDIST_ACFG2_BASE EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG2_SIZE +CYDEV_CLKDIST_ACFG2_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG0 +CYREG_CLKDIST_ACFG2_CFG0 EQU 0x40004108 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG1 +CYREG_CLKDIST_ACFG2_CFG1 EQU 0x40004109 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG2 +CYREG_CLKDIST_ACFG2_CFG2 EQU 0x4000410a + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG2_CFG3 +CYREG_CLKDIST_ACFG2_CFG3 EQU 0x4000410b + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_BASE +CYDEV_CLKDIST_ACFG3_BASE EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYDEV_CLKDIST_ACFG3_SIZE +CYDEV_CLKDIST_ACFG3_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG0 +CYREG_CLKDIST_ACFG3_CFG0 EQU 0x4000410c + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG1 +CYREG_CLKDIST_ACFG3_CFG1 EQU 0x4000410d + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG2 +CYREG_CLKDIST_ACFG3_CFG2 EQU 0x4000410e + ENDIF + IF :LNOT::DEF:CYREG_CLKDIST_ACFG3_CFG3 +CYREG_CLKDIST_ACFG3_CFG3 EQU 0x4000410f + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_BASE +CYDEV_FASTCLK_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_SIZE +CYDEV_FASTCLK_SIZE EQU 0x00000026 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_BASE +CYDEV_FASTCLK_IMO_BASE EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_IMO_SIZE +CYDEV_FASTCLK_IMO_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_IMO_CR +CYREG_FASTCLK_IMO_CR EQU 0x40004200 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_BASE +CYDEV_FASTCLK_XMHZ_BASE EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_XMHZ_SIZE +CYDEV_FASTCLK_XMHZ_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CSR +CYREG_FASTCLK_XMHZ_CSR EQU 0x40004210 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG0 +CYREG_FASTCLK_XMHZ_CFG0 EQU 0x40004212 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_XMHZ_CFG1 +CYREG_FASTCLK_XMHZ_CFG1 EQU 0x40004213 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_BASE +CYDEV_FASTCLK_PLL_BASE EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYDEV_FASTCLK_PLL_SIZE +CYDEV_FASTCLK_PLL_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG0 +CYREG_FASTCLK_PLL_CFG0 EQU 0x40004220 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_CFG1 +CYREG_FASTCLK_PLL_CFG1 EQU 0x40004221 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_P +CYREG_FASTCLK_PLL_P EQU 0x40004222 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_Q +CYREG_FASTCLK_PLL_Q EQU 0x40004223 + ENDIF + IF :LNOT::DEF:CYREG_FASTCLK_PLL_SR +CYREG_FASTCLK_PLL_SR EQU 0x40004225 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_BASE +CYDEV_SLOWCLK_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_SIZE +CYDEV_SLOWCLK_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_BASE +CYDEV_SLOWCLK_ILO_BASE EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_ILO_SIZE +CYDEV_SLOWCLK_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR0 +CYREG_SLOWCLK_ILO_CR0 EQU 0x40004300 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_ILO_CR1 +CYREG_SLOWCLK_ILO_CR1 EQU 0x40004301 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_BASE +CYDEV_SLOWCLK_X32_BASE EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYDEV_SLOWCLK_X32_SIZE +CYDEV_SLOWCLK_X32_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CR +CYREG_SLOWCLK_X32_CR EQU 0x40004308 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_CFG +CYREG_SLOWCLK_X32_CFG EQU 0x40004309 + ENDIF + IF :LNOT::DEF:CYREG_SLOWCLK_X32_TST +CYREG_SLOWCLK_X32_TST EQU 0x4000430a + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_BASE +CYDEV_BOOST_BASE EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYDEV_BOOST_SIZE +CYDEV_BOOST_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR0 +CYREG_BOOST_CR0 EQU 0x40004320 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR1 +CYREG_BOOST_CR1 EQU 0x40004321 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR2 +CYREG_BOOST_CR2 EQU 0x40004322 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR3 +CYREG_BOOST_CR3 EQU 0x40004323 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR +CYREG_BOOST_SR EQU 0x40004324 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_CR4 +CYREG_BOOST_CR4 EQU 0x40004325 + ENDIF + IF :LNOT::DEF:CYREG_BOOST_SR2 +CYREG_BOOST_SR2 EQU 0x40004326 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_BASE +CYDEV_PWRSYS_BASE EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYDEV_PWRSYS_SIZE +CYDEV_PWRSYS_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR0 +CYREG_PWRSYS_CR0 EQU 0x40004330 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_CR1 +CYREG_PWRSYS_CR1 EQU 0x40004331 + ENDIF + IF :LNOT::DEF:CYDEV_PM_BASE +CYDEV_PM_BASE EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYDEV_PM_SIZE +CYDEV_PM_SIZE EQU 0x00000057 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG0 +CYREG_PM_TW_CFG0 EQU 0x40004380 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG1 +CYREG_PM_TW_CFG1 EQU 0x40004381 + ENDIF + IF :LNOT::DEF:CYREG_PM_TW_CFG2 +CYREG_PM_TW_CFG2 EQU 0x40004382 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CFG +CYREG_PM_WDT_CFG EQU 0x40004383 + ENDIF + IF :LNOT::DEF:CYREG_PM_WDT_CR +CYREG_PM_WDT_CR EQU 0x40004384 + ENDIF + IF :LNOT::DEF:CYREG_PM_INT_SR +CYREG_PM_INT_SR EQU 0x40004390 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG0 +CYREG_PM_MODE_CFG0 EQU 0x40004391 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CFG1 +CYREG_PM_MODE_CFG1 EQU 0x40004392 + ENDIF + IF :LNOT::DEF:CYREG_PM_MODE_CSR +CYREG_PM_MODE_CSR EQU 0x40004393 + ENDIF + IF :LNOT::DEF:CYREG_PM_USB_CR0 +CYREG_PM_USB_CR0 EQU 0x40004394 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG0 +CYREG_PM_WAKEUP_CFG0 EQU 0x40004398 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG1 +CYREG_PM_WAKEUP_CFG1 EQU 0x40004399 + ENDIF + IF :LNOT::DEF:CYREG_PM_WAKEUP_CFG2 +CYREG_PM_WAKEUP_CFG2 EQU 0x4000439a + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_BASE +CYDEV_PM_ACT_BASE EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_ACT_SIZE +CYDEV_PM_ACT_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG0 +CYREG_PM_ACT_CFG0 EQU 0x400043a0 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG1 +CYREG_PM_ACT_CFG1 EQU 0x400043a1 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG2 +CYREG_PM_ACT_CFG2 EQU 0x400043a2 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG3 +CYREG_PM_ACT_CFG3 EQU 0x400043a3 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG4 +CYREG_PM_ACT_CFG4 EQU 0x400043a4 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG5 +CYREG_PM_ACT_CFG5 EQU 0x400043a5 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG6 +CYREG_PM_ACT_CFG6 EQU 0x400043a6 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG7 +CYREG_PM_ACT_CFG7 EQU 0x400043a7 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG8 +CYREG_PM_ACT_CFG8 EQU 0x400043a8 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG9 +CYREG_PM_ACT_CFG9 EQU 0x400043a9 + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG10 +CYREG_PM_ACT_CFG10 EQU 0x400043aa + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG11 +CYREG_PM_ACT_CFG11 EQU 0x400043ab + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG12 +CYREG_PM_ACT_CFG12 EQU 0x400043ac + ENDIF + IF :LNOT::DEF:CYREG_PM_ACT_CFG13 +CYREG_PM_ACT_CFG13 EQU 0x400043ad + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_BASE +CYDEV_PM_STBY_BASE EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_STBY_SIZE +CYDEV_PM_STBY_SIZE EQU 0x0000000e + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG0 +CYREG_PM_STBY_CFG0 EQU 0x400043b0 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG1 +CYREG_PM_STBY_CFG1 EQU 0x400043b1 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG2 +CYREG_PM_STBY_CFG2 EQU 0x400043b2 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG3 +CYREG_PM_STBY_CFG3 EQU 0x400043b3 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG4 +CYREG_PM_STBY_CFG4 EQU 0x400043b4 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG5 +CYREG_PM_STBY_CFG5 EQU 0x400043b5 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG6 +CYREG_PM_STBY_CFG6 EQU 0x400043b6 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG7 +CYREG_PM_STBY_CFG7 EQU 0x400043b7 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG8 +CYREG_PM_STBY_CFG8 EQU 0x400043b8 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG9 +CYREG_PM_STBY_CFG9 EQU 0x400043b9 + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG10 +CYREG_PM_STBY_CFG10 EQU 0x400043ba + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG11 +CYREG_PM_STBY_CFG11 EQU 0x400043bb + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG12 +CYREG_PM_STBY_CFG12 EQU 0x400043bc + ENDIF + IF :LNOT::DEF:CYREG_PM_STBY_CFG13 +CYREG_PM_STBY_CFG13 EQU 0x400043bd + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_BASE +CYDEV_PM_AVAIL_BASE EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYDEV_PM_AVAIL_SIZE +CYDEV_PM_AVAIL_SIZE EQU 0x00000017 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR0 +CYREG_PM_AVAIL_CR0 EQU 0x400043c0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR1 +CYREG_PM_AVAIL_CR1 EQU 0x400043c1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR2 +CYREG_PM_AVAIL_CR2 EQU 0x400043c2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR3 +CYREG_PM_AVAIL_CR3 EQU 0x400043c3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR4 +CYREG_PM_AVAIL_CR4 EQU 0x400043c4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR5 +CYREG_PM_AVAIL_CR5 EQU 0x400043c5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_CR6 +CYREG_PM_AVAIL_CR6 EQU 0x400043c6 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR0 +CYREG_PM_AVAIL_SR0 EQU 0x400043d0 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR1 +CYREG_PM_AVAIL_SR1 EQU 0x400043d1 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR2 +CYREG_PM_AVAIL_SR2 EQU 0x400043d2 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR3 +CYREG_PM_AVAIL_SR3 EQU 0x400043d3 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR4 +CYREG_PM_AVAIL_SR4 EQU 0x400043d4 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR5 +CYREG_PM_AVAIL_SR5 EQU 0x400043d5 + ENDIF + IF :LNOT::DEF:CYREG_PM_AVAIL_SR6 +CYREG_PM_AVAIL_SR6 EQU 0x400043d6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_BASE +CYDEV_PICU_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SIZE +CYDEV_PICU_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_BASE +CYDEV_PICU_INTTYPE_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_SIZE +CYDEV_PICU_INTTYPE_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_BASE +CYDEV_PICU_INTTYPE_PICU0_BASE EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU0_SIZE +CYDEV_PICU_INTTYPE_PICU0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE0 +CYREG_PICU0_INTTYPE0 EQU 0x40004500 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE1 +CYREG_PICU0_INTTYPE1 EQU 0x40004501 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE2 +CYREG_PICU0_INTTYPE2 EQU 0x40004502 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE3 +CYREG_PICU0_INTTYPE3 EQU 0x40004503 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE4 +CYREG_PICU0_INTTYPE4 EQU 0x40004504 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE5 +CYREG_PICU0_INTTYPE5 EQU 0x40004505 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE6 +CYREG_PICU0_INTTYPE6 EQU 0x40004506 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTTYPE7 +CYREG_PICU0_INTTYPE7 EQU 0x40004507 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_BASE +CYDEV_PICU_INTTYPE_PICU1_BASE EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU1_SIZE +CYDEV_PICU_INTTYPE_PICU1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE0 +CYREG_PICU1_INTTYPE0 EQU 0x40004508 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE1 +CYREG_PICU1_INTTYPE1 EQU 0x40004509 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE2 +CYREG_PICU1_INTTYPE2 EQU 0x4000450a + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE3 +CYREG_PICU1_INTTYPE3 EQU 0x4000450b + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE4 +CYREG_PICU1_INTTYPE4 EQU 0x4000450c + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE5 +CYREG_PICU1_INTTYPE5 EQU 0x4000450d + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE6 +CYREG_PICU1_INTTYPE6 EQU 0x4000450e + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTTYPE7 +CYREG_PICU1_INTTYPE7 EQU 0x4000450f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_BASE +CYDEV_PICU_INTTYPE_PICU2_BASE EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU2_SIZE +CYDEV_PICU_INTTYPE_PICU2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE0 +CYREG_PICU2_INTTYPE0 EQU 0x40004510 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE1 +CYREG_PICU2_INTTYPE1 EQU 0x40004511 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE2 +CYREG_PICU2_INTTYPE2 EQU 0x40004512 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE3 +CYREG_PICU2_INTTYPE3 EQU 0x40004513 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE4 +CYREG_PICU2_INTTYPE4 EQU 0x40004514 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE5 +CYREG_PICU2_INTTYPE5 EQU 0x40004515 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE6 +CYREG_PICU2_INTTYPE6 EQU 0x40004516 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTTYPE7 +CYREG_PICU2_INTTYPE7 EQU 0x40004517 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_BASE +CYDEV_PICU_INTTYPE_PICU3_BASE EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU3_SIZE +CYDEV_PICU_INTTYPE_PICU3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE0 +CYREG_PICU3_INTTYPE0 EQU 0x40004518 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE1 +CYREG_PICU3_INTTYPE1 EQU 0x40004519 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE2 +CYREG_PICU3_INTTYPE2 EQU 0x4000451a + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE3 +CYREG_PICU3_INTTYPE3 EQU 0x4000451b + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE4 +CYREG_PICU3_INTTYPE4 EQU 0x4000451c + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE5 +CYREG_PICU3_INTTYPE5 EQU 0x4000451d + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE6 +CYREG_PICU3_INTTYPE6 EQU 0x4000451e + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTTYPE7 +CYREG_PICU3_INTTYPE7 EQU 0x4000451f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_BASE +CYDEV_PICU_INTTYPE_PICU4_BASE EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU4_SIZE +CYDEV_PICU_INTTYPE_PICU4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE0 +CYREG_PICU4_INTTYPE0 EQU 0x40004520 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE1 +CYREG_PICU4_INTTYPE1 EQU 0x40004521 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE2 +CYREG_PICU4_INTTYPE2 EQU 0x40004522 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE3 +CYREG_PICU4_INTTYPE3 EQU 0x40004523 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE4 +CYREG_PICU4_INTTYPE4 EQU 0x40004524 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE5 +CYREG_PICU4_INTTYPE5 EQU 0x40004525 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE6 +CYREG_PICU4_INTTYPE6 EQU 0x40004526 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTTYPE7 +CYREG_PICU4_INTTYPE7 EQU 0x40004527 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_BASE +CYDEV_PICU_INTTYPE_PICU5_BASE EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU5_SIZE +CYDEV_PICU_INTTYPE_PICU5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE0 +CYREG_PICU5_INTTYPE0 EQU 0x40004528 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE1 +CYREG_PICU5_INTTYPE1 EQU 0x40004529 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE2 +CYREG_PICU5_INTTYPE2 EQU 0x4000452a + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE3 +CYREG_PICU5_INTTYPE3 EQU 0x4000452b + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE4 +CYREG_PICU5_INTTYPE4 EQU 0x4000452c + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE5 +CYREG_PICU5_INTTYPE5 EQU 0x4000452d + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE6 +CYREG_PICU5_INTTYPE6 EQU 0x4000452e + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTTYPE7 +CYREG_PICU5_INTTYPE7 EQU 0x4000452f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_BASE +CYDEV_PICU_INTTYPE_PICU6_BASE EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU6_SIZE +CYDEV_PICU_INTTYPE_PICU6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE0 +CYREG_PICU6_INTTYPE0 EQU 0x40004530 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE1 +CYREG_PICU6_INTTYPE1 EQU 0x40004531 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE2 +CYREG_PICU6_INTTYPE2 EQU 0x40004532 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE3 +CYREG_PICU6_INTTYPE3 EQU 0x40004533 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE4 +CYREG_PICU6_INTTYPE4 EQU 0x40004534 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE5 +CYREG_PICU6_INTTYPE5 EQU 0x40004535 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE6 +CYREG_PICU6_INTTYPE6 EQU 0x40004536 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTTYPE7 +CYREG_PICU6_INTTYPE7 EQU 0x40004537 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_BASE +CYDEV_PICU_INTTYPE_PICU12_BASE EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU12_SIZE +CYDEV_PICU_INTTYPE_PICU12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE0 +CYREG_PICU12_INTTYPE0 EQU 0x40004560 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE1 +CYREG_PICU12_INTTYPE1 EQU 0x40004561 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE2 +CYREG_PICU12_INTTYPE2 EQU 0x40004562 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE3 +CYREG_PICU12_INTTYPE3 EQU 0x40004563 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE4 +CYREG_PICU12_INTTYPE4 EQU 0x40004564 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE5 +CYREG_PICU12_INTTYPE5 EQU 0x40004565 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE6 +CYREG_PICU12_INTTYPE6 EQU 0x40004566 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTTYPE7 +CYREG_PICU12_INTTYPE7 EQU 0x40004567 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_BASE +CYDEV_PICU_INTTYPE_PICU15_BASE EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_INTTYPE_PICU15_SIZE +CYDEV_PICU_INTTYPE_PICU15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE0 +CYREG_PICU15_INTTYPE0 EQU 0x40004578 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE1 +CYREG_PICU15_INTTYPE1 EQU 0x40004579 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE2 +CYREG_PICU15_INTTYPE2 EQU 0x4000457a + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE3 +CYREG_PICU15_INTTYPE3 EQU 0x4000457b + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE4 +CYREG_PICU15_INTTYPE4 EQU 0x4000457c + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE5 +CYREG_PICU15_INTTYPE5 EQU 0x4000457d + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE6 +CYREG_PICU15_INTTYPE6 EQU 0x4000457e + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTTYPE7 +CYREG_PICU15_INTTYPE7 EQU 0x4000457f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_BASE +CYDEV_PICU_STAT_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_SIZE +CYDEV_PICU_STAT_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_BASE +CYDEV_PICU_STAT_PICU0_BASE EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU0_SIZE +CYDEV_PICU_STAT_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_INTSTAT +CYREG_PICU0_INTSTAT EQU 0x40004580 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_BASE +CYDEV_PICU_STAT_PICU1_BASE EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU1_SIZE +CYDEV_PICU_STAT_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_INTSTAT +CYREG_PICU1_INTSTAT EQU 0x40004581 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_BASE +CYDEV_PICU_STAT_PICU2_BASE EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU2_SIZE +CYDEV_PICU_STAT_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_INTSTAT +CYREG_PICU2_INTSTAT EQU 0x40004582 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_BASE +CYDEV_PICU_STAT_PICU3_BASE EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU3_SIZE +CYDEV_PICU_STAT_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_INTSTAT +CYREG_PICU3_INTSTAT EQU 0x40004583 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_BASE +CYDEV_PICU_STAT_PICU4_BASE EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU4_SIZE +CYDEV_PICU_STAT_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_INTSTAT +CYREG_PICU4_INTSTAT EQU 0x40004584 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_BASE +CYDEV_PICU_STAT_PICU5_BASE EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU5_SIZE +CYDEV_PICU_STAT_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_INTSTAT +CYREG_PICU5_INTSTAT EQU 0x40004585 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_BASE +CYDEV_PICU_STAT_PICU6_BASE EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU6_SIZE +CYDEV_PICU_STAT_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_INTSTAT +CYREG_PICU6_INTSTAT EQU 0x40004586 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_BASE +CYDEV_PICU_STAT_PICU12_BASE EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU12_SIZE +CYDEV_PICU_STAT_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_INTSTAT +CYREG_PICU12_INTSTAT EQU 0x4000458c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_BASE +CYDEV_PICU_STAT_PICU15_BASE EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_STAT_PICU15_SIZE +CYDEV_PICU_STAT_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_INTSTAT +CYREG_PICU15_INTSTAT EQU 0x4000458f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_BASE +CYDEV_PICU_SNAP_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_SIZE +CYDEV_PICU_SNAP_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_BASE +CYDEV_PICU_SNAP_PICU0_BASE EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU0_SIZE +CYDEV_PICU_SNAP_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_SNAP +CYREG_PICU0_SNAP EQU 0x40004590 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_BASE +CYDEV_PICU_SNAP_PICU1_BASE EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU1_SIZE +CYDEV_PICU_SNAP_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_SNAP +CYREG_PICU1_SNAP EQU 0x40004591 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_BASE +CYDEV_PICU_SNAP_PICU2_BASE EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU2_SIZE +CYDEV_PICU_SNAP_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_SNAP +CYREG_PICU2_SNAP EQU 0x40004592 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_BASE +CYDEV_PICU_SNAP_PICU3_BASE EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU3_SIZE +CYDEV_PICU_SNAP_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_SNAP +CYREG_PICU3_SNAP EQU 0x40004593 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_BASE +CYDEV_PICU_SNAP_PICU4_BASE EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU4_SIZE +CYDEV_PICU_SNAP_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_SNAP +CYREG_PICU4_SNAP EQU 0x40004594 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_BASE +CYDEV_PICU_SNAP_PICU5_BASE EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU5_SIZE +CYDEV_PICU_SNAP_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_SNAP +CYREG_PICU5_SNAP EQU 0x40004595 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_BASE +CYDEV_PICU_SNAP_PICU6_BASE EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU6_SIZE +CYDEV_PICU_SNAP_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_SNAP +CYREG_PICU6_SNAP EQU 0x40004596 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_BASE +CYDEV_PICU_SNAP_PICU12_BASE EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU12_SIZE +CYDEV_PICU_SNAP_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_SNAP +CYREG_PICU12_SNAP EQU 0x4000459c + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_BASE +CYDEV_PICU_SNAP_PICU_15_BASE EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_SNAP_PICU_15_SIZE +CYDEV_PICU_SNAP_PICU_15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU_15_SNAP_15 +CYREG_PICU_15_SNAP_15 EQU 0x4000459f + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_BASE +CYDEV_PICU_DISABLE_COR_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_SIZE +CYDEV_PICU_DISABLE_COR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_BASE +CYDEV_PICU_DISABLE_COR_PICU0_BASE EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU0_SIZE +CYDEV_PICU_DISABLE_COR_PICU0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU0_DISABLE_COR +CYREG_PICU0_DISABLE_COR EQU 0x400045a0 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_BASE +CYDEV_PICU_DISABLE_COR_PICU1_BASE EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU1_SIZE +CYDEV_PICU_DISABLE_COR_PICU1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU1_DISABLE_COR +CYREG_PICU1_DISABLE_COR EQU 0x400045a1 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_BASE +CYDEV_PICU_DISABLE_COR_PICU2_BASE EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU2_SIZE +CYDEV_PICU_DISABLE_COR_PICU2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU2_DISABLE_COR +CYREG_PICU2_DISABLE_COR EQU 0x400045a2 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_BASE +CYDEV_PICU_DISABLE_COR_PICU3_BASE EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU3_SIZE +CYDEV_PICU_DISABLE_COR_PICU3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU3_DISABLE_COR +CYREG_PICU3_DISABLE_COR EQU 0x400045a3 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_BASE +CYDEV_PICU_DISABLE_COR_PICU4_BASE EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU4_SIZE +CYDEV_PICU_DISABLE_COR_PICU4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU4_DISABLE_COR +CYREG_PICU4_DISABLE_COR EQU 0x400045a4 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_BASE +CYDEV_PICU_DISABLE_COR_PICU5_BASE EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU5_SIZE +CYDEV_PICU_DISABLE_COR_PICU5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU5_DISABLE_COR +CYREG_PICU5_DISABLE_COR EQU 0x400045a5 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_BASE +CYDEV_PICU_DISABLE_COR_PICU6_BASE EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU6_SIZE +CYDEV_PICU_DISABLE_COR_PICU6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU6_DISABLE_COR +CYREG_PICU6_DISABLE_COR EQU 0x400045a6 + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_BASE +CYDEV_PICU_DISABLE_COR_PICU12_BASE EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU12_SIZE +CYDEV_PICU_DISABLE_COR_PICU12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU12_DISABLE_COR +CYREG_PICU12_DISABLE_COR EQU 0x400045ac + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_BASE +CYDEV_PICU_DISABLE_COR_PICU15_BASE EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_PICU_DISABLE_COR_PICU15_SIZE +CYDEV_PICU_DISABLE_COR_PICU15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PICU15_DISABLE_COR +CYREG_PICU15_DISABLE_COR EQU 0x400045af + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_BASE +CYDEV_MFGCFG_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_SIZE +CYDEV_MFGCFG_SIZE EQU 0x000000ed + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_BASE +CYDEV_MFGCFG_ANAIF_BASE EQU 0x40004600 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SIZE +CYDEV_MFGCFG_ANAIF_SIZE EQU 0x00000038 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_BASE +CYDEV_MFGCFG_ANAIF_DAC0_BASE EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC0_SIZE +CYDEV_MFGCFG_ANAIF_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TR +CYREG_DAC0_TR EQU 0x40004608 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_BASE +CYDEV_MFGCFG_ANAIF_DAC1_BASE EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC1_SIZE +CYDEV_MFGCFG_ANAIF_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TR +CYREG_DAC1_TR EQU 0x40004609 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_BASE +CYDEV_MFGCFG_ANAIF_DAC2_BASE EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC2_SIZE +CYDEV_MFGCFG_ANAIF_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TR +CYREG_DAC2_TR EQU 0x4000460a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_BASE +CYDEV_MFGCFG_ANAIF_DAC3_BASE EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_DAC3_SIZE +CYDEV_MFGCFG_ANAIF_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TR +CYREG_DAC3_TR EQU 0x4000460b + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_BASE EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_DSM_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_DSM_TR0 +CYREG_NPUMP_DSM_TR0 EQU 0x40004610 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_BASE EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_SC_TR0 +CYREG_NPUMP_SC_TR0 EQU 0x40004611 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_BASE EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE +CYDEV_MFGCFG_ANAIF_NPUMP_OPAMP_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_NPUMP_OPAMP_TR0 +CYREG_NPUMP_OPAMP_TR0 EQU 0x40004612 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_BASE +CYDEV_MFGCFG_ANAIF_SAR0_BASE EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR0_SIZE +CYDEV_MFGCFG_ANAIF_SAR0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_TR0 +CYREG_SAR0_TR0 EQU 0x40004614 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_BASE +CYDEV_MFGCFG_ANAIF_SAR1_BASE EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_SAR1_SIZE +CYDEV_MFGCFG_ANAIF_SAR1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_TR0 +CYREG_SAR1_TR0 EQU 0x40004616 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_BASE +CYDEV_MFGCFG_ANAIF_OPAMP0_BASE EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR0 +CYREG_OPAMP0_TR0 EQU 0x40004620 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_TR1 +CYREG_OPAMP0_TR1 EQU 0x40004621 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_BASE +CYDEV_MFGCFG_ANAIF_OPAMP1_BASE EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR0 +CYREG_OPAMP1_TR0 EQU 0x40004622 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_TR1 +CYREG_OPAMP1_TR1 EQU 0x40004623 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_BASE +CYDEV_MFGCFG_ANAIF_OPAMP2_BASE EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR0 +CYREG_OPAMP2_TR0 EQU 0x40004624 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_TR1 +CYREG_OPAMP2_TR1 EQU 0x40004625 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_BASE +CYDEV_MFGCFG_ANAIF_OPAMP3_BASE EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE +CYDEV_MFGCFG_ANAIF_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR0 +CYREG_OPAMP3_TR0 EQU 0x40004626 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_TR1 +CYREG_OPAMP3_TR1 EQU 0x40004627 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_BASE +CYDEV_MFGCFG_ANAIF_CMP0_BASE EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP0_SIZE +CYDEV_MFGCFG_ANAIF_CMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR0 +CYREG_CMP0_TR0 EQU 0x40004630 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_TR1 +CYREG_CMP0_TR1 EQU 0x40004631 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_BASE +CYDEV_MFGCFG_ANAIF_CMP1_BASE EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP1_SIZE +CYDEV_MFGCFG_ANAIF_CMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR0 +CYREG_CMP1_TR0 EQU 0x40004632 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_TR1 +CYREG_CMP1_TR1 EQU 0x40004633 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_BASE +CYDEV_MFGCFG_ANAIF_CMP2_BASE EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP2_SIZE +CYDEV_MFGCFG_ANAIF_CMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR0 +CYREG_CMP2_TR0 EQU 0x40004634 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_TR1 +CYREG_CMP2_TR1 EQU 0x40004635 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_BASE +CYDEV_MFGCFG_ANAIF_CMP3_BASE EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ANAIF_CMP3_SIZE +CYDEV_MFGCFG_ANAIF_CMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR0 +CYREG_CMP3_TR0 EQU 0x40004636 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_TR1 +CYREG_CMP3_TR1 EQU 0x40004637 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_BASE +CYDEV_MFGCFG_PWRSYS_BASE EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_PWRSYS_SIZE +CYDEV_MFGCFG_PWRSYS_SIZE EQU 0x0000000b + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR0 +CYREG_PWRSYS_HIB_TR0 EQU 0x40004680 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_HIB_TR1 +CYREG_PWRSYS_HIB_TR1 EQU 0x40004681 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_I2C_TR +CYREG_PWRSYS_I2C_TR EQU 0x40004682 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_SLP_TR +CYREG_PWRSYS_SLP_TR EQU 0x40004683 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BUZZ_TR +CYREG_PWRSYS_BUZZ_TR EQU 0x40004684 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR0 +CYREG_PWRSYS_WAKE_TR0 EQU 0x40004685 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR1 +CYREG_PWRSYS_WAKE_TR1 EQU 0x40004686 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BREF_TR +CYREG_PWRSYS_BREF_TR EQU 0x40004687 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_BG_TR +CYREG_PWRSYS_BG_TR EQU 0x40004688 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR2 +CYREG_PWRSYS_WAKE_TR2 EQU 0x40004689 + ENDIF + IF :LNOT::DEF:CYREG_PWRSYS_WAKE_TR3 +CYREG_PWRSYS_WAKE_TR3 EQU 0x4000468a + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_BASE +CYDEV_MFGCFG_ILO_BASE EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_ILO_SIZE +CYDEV_MFGCFG_ILO_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR0 +CYREG_ILO_TR0 EQU 0x40004690 + ENDIF + IF :LNOT::DEF:CYREG_ILO_TR1 +CYREG_ILO_TR1 EQU 0x40004691 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_BASE +CYDEV_MFGCFG_X32_BASE EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_X32_SIZE +CYDEV_MFGCFG_X32_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_X32_TR +CYREG_X32_TR EQU 0x40004698 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_BASE +CYDEV_MFGCFG_IMO_BASE EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_IMO_SIZE +CYDEV_MFGCFG_IMO_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR0 +CYREG_IMO_TR0 EQU 0x400046a0 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR1 +CYREG_IMO_TR1 EQU 0x400046a1 + ENDIF + IF :LNOT::DEF:CYREG_IMO_GAIN +CYREG_IMO_GAIN EQU 0x400046a2 + ENDIF + IF :LNOT::DEF:CYREG_IMO_C36M +CYREG_IMO_C36M EQU 0x400046a3 + ENDIF + IF :LNOT::DEF:CYREG_IMO_TR2 +CYREG_IMO_TR2 EQU 0x400046a4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_BASE +CYDEV_MFGCFG_XMHZ_BASE EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_XMHZ_SIZE +CYDEV_MFGCFG_XMHZ_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_XMHZ_TR +CYREG_XMHZ_TR EQU 0x400046a8 + ENDIF + IF :LNOT::DEF:CYREG_MFGCFG_DLY +CYREG_MFGCFG_DLY EQU 0x400046c0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_BASE +CYDEV_MFGCFG_MLOGIC_BASE EQU 0x400046e0 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SIZE +CYDEV_MFGCFG_MLOGIC_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DMPSTR +CYREG_MLOGIC_DMPSTR EQU 0x400046e2 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_BASE +CYDEV_MFGCFG_MLOGIC_SEG_BASE EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_SEG_SIZE +CYDEV_MFGCFG_MLOGIC_SEG_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CR +CYREG_MLOGIC_SEG_CR EQU 0x400046e4 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_SEG_CFG0 +CYREG_MLOGIC_SEG_CFG0 EQU 0x400046e5 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_DEBUG +CYREG_MLOGIC_DEBUG EQU 0x400046e8 + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_BASE EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE +CYDEV_MFGCFG_MLOGIC_CPU_SCR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_CPU_SCR_CPU_SCR +CYREG_MLOGIC_CPU_SCR_CPU_SCR EQU 0x400046ea + ENDIF + IF :LNOT::DEF:CYREG_MLOGIC_REV_ID +CYREG_MLOGIC_REV_ID EQU 0x400046ec + ENDIF + IF :LNOT::DEF:CYDEV_RESET_BASE +CYDEV_RESET_BASE EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYDEV_RESET_SIZE +CYDEV_RESET_SIZE EQU 0x0000000f + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR0 +CYREG_RESET_IPOR_CR0 EQU 0x400046f0 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR1 +CYREG_RESET_IPOR_CR1 EQU 0x400046f1 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR2 +CYREG_RESET_IPOR_CR2 EQU 0x400046f2 + ENDIF + IF :LNOT::DEF:CYREG_RESET_IPOR_CR3 +CYREG_RESET_IPOR_CR3 EQU 0x400046f3 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR0 +CYREG_RESET_CR0 EQU 0x400046f4 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR1 +CYREG_RESET_CR1 EQU 0x400046f5 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR2 +CYREG_RESET_CR2 EQU 0x400046f6 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR3 +CYREG_RESET_CR3 EQU 0x400046f7 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR4 +CYREG_RESET_CR4 EQU 0x400046f8 + ENDIF + IF :LNOT::DEF:CYREG_RESET_CR5 +CYREG_RESET_CR5 EQU 0x400046f9 + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR0 +CYREG_RESET_SR0 EQU 0x400046fa + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR1 +CYREG_RESET_SR1 EQU 0x400046fb + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR2 +CYREG_RESET_SR2 EQU 0x400046fc + ENDIF + IF :LNOT::DEF:CYREG_RESET_SR3 +CYREG_RESET_SR3 EQU 0x400046fd + ENDIF + IF :LNOT::DEF:CYREG_RESET_TR +CYREG_RESET_TR EQU 0x400046fe + ENDIF + IF :LNOT::DEF:CYDEV_SPC_BASE +CYDEV_SPC_BASE EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_SIZE +CYDEV_SPC_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_CR +CYREG_SPC_FM_EE_CR EQU 0x40004700 + ENDIF + IF :LNOT::DEF:CYREG_SPC_FM_EE_WAKE_CNT +CYREG_SPC_FM_EE_WAKE_CNT EQU 0x40004701 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_SCR +CYREG_SPC_EE_SCR EQU 0x40004702 + ENDIF + IF :LNOT::DEF:CYREG_SPC_EE_ERR +CYREG_SPC_EE_ERR EQU 0x40004703 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CPU_DATA +CYREG_SPC_CPU_DATA EQU 0x40004720 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMA_DATA +CYREG_SPC_DMA_DATA EQU 0x40004721 + ENDIF + IF :LNOT::DEF:CYREG_SPC_SR +CYREG_SPC_SR EQU 0x40004722 + ENDIF + IF :LNOT::DEF:CYREG_SPC_CR +CYREG_SPC_CR EQU 0x40004723 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_BASE +CYDEV_SPC_DMM_MAP_BASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYDEV_SPC_DMM_MAP_SIZE +CYDEV_SPC_DMM_MAP_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MBASE +CYREG_SPC_DMM_MAP_SRAM_MBASE EQU 0x40004780 + ENDIF + IF :LNOT::DEF:CYREG_SPC_DMM_MAP_SRAM_MSIZE +CYREG_SPC_DMM_MAP_SRAM_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_BASE +CYDEV_CACHE_BASE EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYDEV_CACHE_SIZE +CYDEV_CACHE_SIZE EQU 0x0000009c + ENDIF + IF :LNOT::DEF:CYREG_CACHE_CC_CTL +CYREG_CACHE_CC_CTL EQU 0x40004800 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_CORR +CYREG_CACHE_ECC_CORR EQU 0x40004880 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_ECC_ERR +CYREG_CACHE_ECC_ERR EQU 0x40004888 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_FLASH_ERR +CYREG_CACHE_FLASH_ERR EQU 0x40004890 + ENDIF + IF :LNOT::DEF:CYREG_CACHE_HITMISS +CYREG_CACHE_HITMISS EQU 0x40004898 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_BASE +CYDEV_I2C_BASE EQU 0x40004900 + ENDIF + IF :LNOT::DEF:CYDEV_I2C_SIZE +CYDEV_I2C_SIZE EQU 0x000000e1 + ENDIF + IF :LNOT::DEF:CYREG_I2C_XCFG +CYREG_I2C_XCFG EQU 0x400049c8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_ADR +CYREG_I2C_ADR EQU 0x400049ca + ENDIF + IF :LNOT::DEF:CYREG_I2C_CFG +CYREG_I2C_CFG EQU 0x400049d6 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CSR +CYREG_I2C_CSR EQU 0x400049d7 + ENDIF + IF :LNOT::DEF:CYREG_I2C_D +CYREG_I2C_D EQU 0x400049d8 + ENDIF + IF :LNOT::DEF:CYREG_I2C_MCSR +CYREG_I2C_MCSR EQU 0x400049d9 + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV1 +CYREG_I2C_CLK_DIV1 EQU 0x400049db + ENDIF + IF :LNOT::DEF:CYREG_I2C_CLK_DIV2 +CYREG_I2C_CLK_DIV2 EQU 0x400049dc + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CSR +CYREG_I2C_TMOUT_CSR EQU 0x400049dd + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_SR +CYREG_I2C_TMOUT_SR EQU 0x400049de + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG0 +CYREG_I2C_TMOUT_CFG0 EQU 0x400049df + ENDIF + IF :LNOT::DEF:CYREG_I2C_TMOUT_CFG1 +CYREG_I2C_TMOUT_CFG1 EQU 0x400049e0 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_BASE +CYDEV_DEC_BASE EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYDEV_DEC_SIZE +CYDEV_DEC_SIZE EQU 0x00000015 + ENDIF + IF :LNOT::DEF:CYREG_DEC_CR +CYREG_DEC_CR EQU 0x40004e00 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SR +CYREG_DEC_SR EQU 0x40004e01 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT1 +CYREG_DEC_SHIFT1 EQU 0x40004e02 + ENDIF + IF :LNOT::DEF:CYREG_DEC_SHIFT2 +CYREG_DEC_SHIFT2 EQU 0x40004e03 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2 +CYREG_DEC_DR2 EQU 0x40004e04 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR2H +CYREG_DEC_DR2H EQU 0x40004e05 + ENDIF + IF :LNOT::DEF:CYREG_DEC_DR1 +CYREG_DEC_DR1 EQU 0x40004e06 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCOR +CYREG_DEC_OCOR EQU 0x40004e08 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORM +CYREG_DEC_OCORM EQU 0x40004e09 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OCORH +CYREG_DEC_OCORH EQU 0x40004e0a + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCOR +CYREG_DEC_GCOR EQU 0x40004e0c + ENDIF + IF :LNOT::DEF:CYREG_DEC_GCORH +CYREG_DEC_GCORH EQU 0x40004e0d + ENDIF + IF :LNOT::DEF:CYREG_DEC_GVAL +CYREG_DEC_GVAL EQU 0x40004e0e + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMP +CYREG_DEC_OUTSAMP EQU 0x40004e10 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPM +CYREG_DEC_OUTSAMPM EQU 0x40004e11 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPH +CYREG_DEC_OUTSAMPH EQU 0x40004e12 + ENDIF + IF :LNOT::DEF:CYREG_DEC_OUTSAMPS +CYREG_DEC_OUTSAMPS EQU 0x40004e13 + ENDIF + IF :LNOT::DEF:CYREG_DEC_COHER +CYREG_DEC_COHER EQU 0x40004e14 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_BASE +CYDEV_TMR0_BASE EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYDEV_TMR0_SIZE +CYDEV_TMR0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG0 +CYREG_TMR0_CFG0 EQU 0x40004f00 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG1 +CYREG_TMR0_CFG1 EQU 0x40004f01 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CFG2 +CYREG_TMR0_CFG2 EQU 0x40004f02 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_SR0 +CYREG_TMR0_SR0 EQU 0x40004f03 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER0 +CYREG_TMR0_PER0 EQU 0x40004f04 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_PER1 +CYREG_TMR0_PER1 EQU 0x40004f05 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP0 +CYREG_TMR0_CNT_CMP0 EQU 0x40004f06 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CNT_CMP1 +CYREG_TMR0_CNT_CMP1 EQU 0x40004f07 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP0 +CYREG_TMR0_CAP0 EQU 0x40004f08 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_CAP1 +CYREG_TMR0_CAP1 EQU 0x40004f09 + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT0 +CYREG_TMR0_RT0 EQU 0x40004f0a + ENDIF + IF :LNOT::DEF:CYREG_TMR0_RT1 +CYREG_TMR0_RT1 EQU 0x40004f0b + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_BASE +CYDEV_TMR1_BASE EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYDEV_TMR1_SIZE +CYDEV_TMR1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG0 +CYREG_TMR1_CFG0 EQU 0x40004f0c + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG1 +CYREG_TMR1_CFG1 EQU 0x40004f0d + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CFG2 +CYREG_TMR1_CFG2 EQU 0x40004f0e + ENDIF + IF :LNOT::DEF:CYREG_TMR1_SR0 +CYREG_TMR1_SR0 EQU 0x40004f0f + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER0 +CYREG_TMR1_PER0 EQU 0x40004f10 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_PER1 +CYREG_TMR1_PER1 EQU 0x40004f11 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP0 +CYREG_TMR1_CNT_CMP0 EQU 0x40004f12 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CNT_CMP1 +CYREG_TMR1_CNT_CMP1 EQU 0x40004f13 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP0 +CYREG_TMR1_CAP0 EQU 0x40004f14 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_CAP1 +CYREG_TMR1_CAP1 EQU 0x40004f15 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT0 +CYREG_TMR1_RT0 EQU 0x40004f16 + ENDIF + IF :LNOT::DEF:CYREG_TMR1_RT1 +CYREG_TMR1_RT1 EQU 0x40004f17 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_BASE +CYDEV_TMR2_BASE EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYDEV_TMR2_SIZE +CYDEV_TMR2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG0 +CYREG_TMR2_CFG0 EQU 0x40004f18 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG1 +CYREG_TMR2_CFG1 EQU 0x40004f19 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CFG2 +CYREG_TMR2_CFG2 EQU 0x40004f1a + ENDIF + IF :LNOT::DEF:CYREG_TMR2_SR0 +CYREG_TMR2_SR0 EQU 0x40004f1b + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER0 +CYREG_TMR2_PER0 EQU 0x40004f1c + ENDIF + IF :LNOT::DEF:CYREG_TMR2_PER1 +CYREG_TMR2_PER1 EQU 0x40004f1d + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP0 +CYREG_TMR2_CNT_CMP0 EQU 0x40004f1e + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CNT_CMP1 +CYREG_TMR2_CNT_CMP1 EQU 0x40004f1f + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP0 +CYREG_TMR2_CAP0 EQU 0x40004f20 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_CAP1 +CYREG_TMR2_CAP1 EQU 0x40004f21 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT0 +CYREG_TMR2_RT0 EQU 0x40004f22 + ENDIF + IF :LNOT::DEF:CYREG_TMR2_RT1 +CYREG_TMR2_RT1 EQU 0x40004f23 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_BASE +CYDEV_TMR3_BASE EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYDEV_TMR3_SIZE +CYDEV_TMR3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG0 +CYREG_TMR3_CFG0 EQU 0x40004f24 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG1 +CYREG_TMR3_CFG1 EQU 0x40004f25 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CFG2 +CYREG_TMR3_CFG2 EQU 0x40004f26 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_SR0 +CYREG_TMR3_SR0 EQU 0x40004f27 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER0 +CYREG_TMR3_PER0 EQU 0x40004f28 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_PER1 +CYREG_TMR3_PER1 EQU 0x40004f29 + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP0 +CYREG_TMR3_CNT_CMP0 EQU 0x40004f2a + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CNT_CMP1 +CYREG_TMR3_CNT_CMP1 EQU 0x40004f2b + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP0 +CYREG_TMR3_CAP0 EQU 0x40004f2c + ENDIF + IF :LNOT::DEF:CYREG_TMR3_CAP1 +CYREG_TMR3_CAP1 EQU 0x40004f2d + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT0 +CYREG_TMR3_RT0 EQU 0x40004f2e + ENDIF + IF :LNOT::DEF:CYREG_TMR3_RT1 +CYREG_TMR3_RT1 EQU 0x40004f2f + ENDIF + IF :LNOT::DEF:CYDEV_IO_BASE +CYDEV_IO_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_SIZE +CYDEV_IO_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_BASE +CYDEV_IO_PC_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_SIZE +CYDEV_IO_PC_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_BASE +CYDEV_IO_PC_PRT0_BASE EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT0_SIZE +CYDEV_IO_PC_PRT0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC0 +CYREG_PRT0_PC0 EQU 0x40005000 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC1 +CYREG_PRT0_PC1 EQU 0x40005001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC2 +CYREG_PRT0_PC2 EQU 0x40005002 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC3 +CYREG_PRT0_PC3 EQU 0x40005003 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC4 +CYREG_PRT0_PC4 EQU 0x40005004 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC5 +CYREG_PRT0_PC5 EQU 0x40005005 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC6 +CYREG_PRT0_PC6 EQU 0x40005006 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PC7 +CYREG_PRT0_PC7 EQU 0x40005007 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_BASE +CYDEV_IO_PC_PRT1_BASE EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT1_SIZE +CYDEV_IO_PC_PRT1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC0 +CYREG_PRT1_PC0 EQU 0x40005008 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC1 +CYREG_PRT1_PC1 EQU 0x40005009 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC2 +CYREG_PRT1_PC2 EQU 0x4000500a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC3 +CYREG_PRT1_PC3 EQU 0x4000500b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC4 +CYREG_PRT1_PC4 EQU 0x4000500c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC5 +CYREG_PRT1_PC5 EQU 0x4000500d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC6 +CYREG_PRT1_PC6 EQU 0x4000500e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PC7 +CYREG_PRT1_PC7 EQU 0x4000500f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_BASE +CYDEV_IO_PC_PRT2_BASE EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT2_SIZE +CYDEV_IO_PC_PRT2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC0 +CYREG_PRT2_PC0 EQU 0x40005010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC1 +CYREG_PRT2_PC1 EQU 0x40005011 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC2 +CYREG_PRT2_PC2 EQU 0x40005012 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC3 +CYREG_PRT2_PC3 EQU 0x40005013 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC4 +CYREG_PRT2_PC4 EQU 0x40005014 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC5 +CYREG_PRT2_PC5 EQU 0x40005015 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC6 +CYREG_PRT2_PC6 EQU 0x40005016 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PC7 +CYREG_PRT2_PC7 EQU 0x40005017 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_BASE +CYDEV_IO_PC_PRT3_BASE EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT3_SIZE +CYDEV_IO_PC_PRT3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC0 +CYREG_PRT3_PC0 EQU 0x40005018 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC1 +CYREG_PRT3_PC1 EQU 0x40005019 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC2 +CYREG_PRT3_PC2 EQU 0x4000501a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC3 +CYREG_PRT3_PC3 EQU 0x4000501b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC4 +CYREG_PRT3_PC4 EQU 0x4000501c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC5 +CYREG_PRT3_PC5 EQU 0x4000501d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC6 +CYREG_PRT3_PC6 EQU 0x4000501e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PC7 +CYREG_PRT3_PC7 EQU 0x4000501f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_BASE +CYDEV_IO_PC_PRT4_BASE EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT4_SIZE +CYDEV_IO_PC_PRT4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC0 +CYREG_PRT4_PC0 EQU 0x40005020 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC1 +CYREG_PRT4_PC1 EQU 0x40005021 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC2 +CYREG_PRT4_PC2 EQU 0x40005022 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC3 +CYREG_PRT4_PC3 EQU 0x40005023 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC4 +CYREG_PRT4_PC4 EQU 0x40005024 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC5 +CYREG_PRT4_PC5 EQU 0x40005025 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC6 +CYREG_PRT4_PC6 EQU 0x40005026 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PC7 +CYREG_PRT4_PC7 EQU 0x40005027 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_BASE +CYDEV_IO_PC_PRT5_BASE EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT5_SIZE +CYDEV_IO_PC_PRT5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC0 +CYREG_PRT5_PC0 EQU 0x40005028 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC1 +CYREG_PRT5_PC1 EQU 0x40005029 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC2 +CYREG_PRT5_PC2 EQU 0x4000502a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC3 +CYREG_PRT5_PC3 EQU 0x4000502b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC4 +CYREG_PRT5_PC4 EQU 0x4000502c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC5 +CYREG_PRT5_PC5 EQU 0x4000502d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC6 +CYREG_PRT5_PC6 EQU 0x4000502e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PC7 +CYREG_PRT5_PC7 EQU 0x4000502f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_BASE +CYDEV_IO_PC_PRT6_BASE EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT6_SIZE +CYDEV_IO_PC_PRT6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC0 +CYREG_PRT6_PC0 EQU 0x40005030 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC1 +CYREG_PRT6_PC1 EQU 0x40005031 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC2 +CYREG_PRT6_PC2 EQU 0x40005032 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC3 +CYREG_PRT6_PC3 EQU 0x40005033 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC4 +CYREG_PRT6_PC4 EQU 0x40005034 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC5 +CYREG_PRT6_PC5 EQU 0x40005035 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC6 +CYREG_PRT6_PC6 EQU 0x40005036 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PC7 +CYREG_PRT6_PC7 EQU 0x40005037 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_BASE +CYDEV_IO_PC_PRT12_BASE EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT12_SIZE +CYDEV_IO_PC_PRT12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC0 +CYREG_PRT12_PC0 EQU 0x40005060 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC1 +CYREG_PRT12_PC1 EQU 0x40005061 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC2 +CYREG_PRT12_PC2 EQU 0x40005062 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC3 +CYREG_PRT12_PC3 EQU 0x40005063 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC4 +CYREG_PRT12_PC4 EQU 0x40005064 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC5 +CYREG_PRT12_PC5 EQU 0x40005065 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC6 +CYREG_PRT12_PC6 EQU 0x40005066 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PC7 +CYREG_PRT12_PC7 EQU 0x40005067 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_BASE +CYDEV_IO_PC_PRT15_BASE EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_SIZE +CYDEV_IO_PC_PRT15_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC0 +CYREG_IO_PC_PRT15_PC0 EQU 0x40005078 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC1 +CYREG_IO_PC_PRT15_PC1 EQU 0x40005079 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC2 +CYREG_IO_PC_PRT15_PC2 EQU 0x4000507a + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC3 +CYREG_IO_PC_PRT15_PC3 EQU 0x4000507b + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC4 +CYREG_IO_PC_PRT15_PC4 EQU 0x4000507c + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_PC5 +CYREG_IO_PC_PRT15_PC5 EQU 0x4000507d + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_BASE +CYDEV_IO_PC_PRT15_7_6_BASE EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYDEV_IO_PC_PRT15_7_6_SIZE +CYDEV_IO_PC_PRT15_7_6_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC0 +CYREG_IO_PC_PRT15_7_6_PC0 EQU 0x4000507e + ENDIF + IF :LNOT::DEF:CYREG_IO_PC_PRT15_7_6_PC1 +CYREG_IO_PC_PRT15_7_6_PC1 EQU 0x4000507f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_BASE +CYDEV_IO_DR_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_SIZE +CYDEV_IO_DR_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_BASE +CYDEV_IO_DR_PRT0_BASE EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT0_SIZE +CYDEV_IO_DR_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR_ALIAS +CYREG_PRT0_DR_ALIAS EQU 0x40005080 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_BASE +CYDEV_IO_DR_PRT1_BASE EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT1_SIZE +CYDEV_IO_DR_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR_ALIAS +CYREG_PRT1_DR_ALIAS EQU 0x40005081 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_BASE +CYDEV_IO_DR_PRT2_BASE EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT2_SIZE +CYDEV_IO_DR_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR_ALIAS +CYREG_PRT2_DR_ALIAS EQU 0x40005082 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_BASE +CYDEV_IO_DR_PRT3_BASE EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT3_SIZE +CYDEV_IO_DR_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR_ALIAS +CYREG_PRT3_DR_ALIAS EQU 0x40005083 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_BASE +CYDEV_IO_DR_PRT4_BASE EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT4_SIZE +CYDEV_IO_DR_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR_ALIAS +CYREG_PRT4_DR_ALIAS EQU 0x40005084 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_BASE +CYDEV_IO_DR_PRT5_BASE EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT5_SIZE +CYDEV_IO_DR_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR_ALIAS +CYREG_PRT5_DR_ALIAS EQU 0x40005085 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_BASE +CYDEV_IO_DR_PRT6_BASE EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT6_SIZE +CYDEV_IO_DR_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR_ALIAS +CYREG_PRT6_DR_ALIAS EQU 0x40005086 + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_BASE +CYDEV_IO_DR_PRT12_BASE EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT12_SIZE +CYDEV_IO_DR_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR_ALIAS +CYREG_PRT12_DR_ALIAS EQU 0x4000508c + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_BASE +CYDEV_IO_DR_PRT15_BASE EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_DR_PRT15_SIZE +CYDEV_IO_DR_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR_15_ALIAS +CYREG_PRT15_DR_15_ALIAS EQU 0x4000508f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_BASE +CYDEV_IO_PS_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_SIZE +CYDEV_IO_PS_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_BASE +CYDEV_IO_PS_PRT0_BASE EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT0_SIZE +CYDEV_IO_PS_PRT0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS_ALIAS +CYREG_PRT0_PS_ALIAS EQU 0x40005090 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_BASE +CYDEV_IO_PS_PRT1_BASE EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT1_SIZE +CYDEV_IO_PS_PRT1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS_ALIAS +CYREG_PRT1_PS_ALIAS EQU 0x40005091 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_BASE +CYDEV_IO_PS_PRT2_BASE EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT2_SIZE +CYDEV_IO_PS_PRT2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS_ALIAS +CYREG_PRT2_PS_ALIAS EQU 0x40005092 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_BASE +CYDEV_IO_PS_PRT3_BASE EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT3_SIZE +CYDEV_IO_PS_PRT3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS_ALIAS +CYREG_PRT3_PS_ALIAS EQU 0x40005093 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_BASE +CYDEV_IO_PS_PRT4_BASE EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT4_SIZE +CYDEV_IO_PS_PRT4_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS_ALIAS +CYREG_PRT4_PS_ALIAS EQU 0x40005094 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_BASE +CYDEV_IO_PS_PRT5_BASE EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT5_SIZE +CYDEV_IO_PS_PRT5_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS_ALIAS +CYREG_PRT5_PS_ALIAS EQU 0x40005095 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_BASE +CYDEV_IO_PS_PRT6_BASE EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT6_SIZE +CYDEV_IO_PS_PRT6_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS_ALIAS +CYREG_PRT6_PS_ALIAS EQU 0x40005096 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_BASE +CYDEV_IO_PS_PRT12_BASE EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT12_SIZE +CYDEV_IO_PS_PRT12_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS_ALIAS +CYREG_PRT12_PS_ALIAS EQU 0x4000509c + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_BASE +CYDEV_IO_PS_PRT15_BASE EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PS_PRT15_SIZE +CYDEV_IO_PS_PRT15_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS15_ALIAS +CYREG_PRT15_PS15_ALIAS EQU 0x4000509f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_BASE +CYDEV_IO_PRT_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_SIZE +CYDEV_IO_PRT_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_BASE +CYDEV_IO_PRT_PRT0_BASE EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT0_SIZE +CYDEV_IO_PRT_PRT0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DR +CYREG_PRT0_DR EQU 0x40005100 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PS +CYREG_PRT0_PS EQU 0x40005101 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM0 +CYREG_PRT0_DM0 EQU 0x40005102 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM1 +CYREG_PRT0_DM1 EQU 0x40005103 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DM2 +CYREG_PRT0_DM2 EQU 0x40005104 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SLW +CYREG_PRT0_SLW EQU 0x40005105 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BYP +CYREG_PRT0_BYP EQU 0x40005106 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIE +CYREG_PRT0_BIE EQU 0x40005107 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_INP_DIS +CYREG_PRT0_INP_DIS EQU 0x40005108 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CTL +CYREG_PRT0_CTL EQU 0x40005109 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_PRT +CYREG_PRT0_PRT EQU 0x4000510a + ENDIF + IF :LNOT::DEF:CYREG_PRT0_BIT_MASK +CYREG_PRT0_BIT_MASK EQU 0x4000510b + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AMUX +CYREG_PRT0_AMUX EQU 0x4000510c + ENDIF + IF :LNOT::DEF:CYREG_PRT0_AG +CYREG_PRT0_AG EQU 0x4000510d + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_COM_SEG +CYREG_PRT0_LCD_COM_SEG EQU 0x4000510e + ENDIF + IF :LNOT::DEF:CYREG_PRT0_LCD_EN +CYREG_PRT0_LCD_EN EQU 0x4000510f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_BASE +CYDEV_IO_PRT_PRT1_BASE EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT1_SIZE +CYDEV_IO_PRT_PRT1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DR +CYREG_PRT1_DR EQU 0x40005110 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PS +CYREG_PRT1_PS EQU 0x40005111 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM0 +CYREG_PRT1_DM0 EQU 0x40005112 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM1 +CYREG_PRT1_DM1 EQU 0x40005113 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DM2 +CYREG_PRT1_DM2 EQU 0x40005114 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SLW +CYREG_PRT1_SLW EQU 0x40005115 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BYP +CYREG_PRT1_BYP EQU 0x40005116 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIE +CYREG_PRT1_BIE EQU 0x40005117 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_INP_DIS +CYREG_PRT1_INP_DIS EQU 0x40005118 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CTL +CYREG_PRT1_CTL EQU 0x40005119 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_PRT +CYREG_PRT1_PRT EQU 0x4000511a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_BIT_MASK +CYREG_PRT1_BIT_MASK EQU 0x4000511b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AMUX +CYREG_PRT1_AMUX EQU 0x4000511c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_AG +CYREG_PRT1_AG EQU 0x4000511d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_COM_SEG +CYREG_PRT1_LCD_COM_SEG EQU 0x4000511e + ENDIF + IF :LNOT::DEF:CYREG_PRT1_LCD_EN +CYREG_PRT1_LCD_EN EQU 0x4000511f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_BASE +CYDEV_IO_PRT_PRT2_BASE EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT2_SIZE +CYDEV_IO_PRT_PRT2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DR +CYREG_PRT2_DR EQU 0x40005120 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PS +CYREG_PRT2_PS EQU 0x40005121 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM0 +CYREG_PRT2_DM0 EQU 0x40005122 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM1 +CYREG_PRT2_DM1 EQU 0x40005123 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DM2 +CYREG_PRT2_DM2 EQU 0x40005124 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SLW +CYREG_PRT2_SLW EQU 0x40005125 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BYP +CYREG_PRT2_BYP EQU 0x40005126 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIE +CYREG_PRT2_BIE EQU 0x40005127 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_INP_DIS +CYREG_PRT2_INP_DIS EQU 0x40005128 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CTL +CYREG_PRT2_CTL EQU 0x40005129 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_PRT +CYREG_PRT2_PRT EQU 0x4000512a + ENDIF + IF :LNOT::DEF:CYREG_PRT2_BIT_MASK +CYREG_PRT2_BIT_MASK EQU 0x4000512b + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AMUX +CYREG_PRT2_AMUX EQU 0x4000512c + ENDIF + IF :LNOT::DEF:CYREG_PRT2_AG +CYREG_PRT2_AG EQU 0x4000512d + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_COM_SEG +CYREG_PRT2_LCD_COM_SEG EQU 0x4000512e + ENDIF + IF :LNOT::DEF:CYREG_PRT2_LCD_EN +CYREG_PRT2_LCD_EN EQU 0x4000512f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_BASE +CYDEV_IO_PRT_PRT3_BASE EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT3_SIZE +CYDEV_IO_PRT_PRT3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DR +CYREG_PRT3_DR EQU 0x40005130 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PS +CYREG_PRT3_PS EQU 0x40005131 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM0 +CYREG_PRT3_DM0 EQU 0x40005132 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM1 +CYREG_PRT3_DM1 EQU 0x40005133 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DM2 +CYREG_PRT3_DM2 EQU 0x40005134 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SLW +CYREG_PRT3_SLW EQU 0x40005135 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BYP +CYREG_PRT3_BYP EQU 0x40005136 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIE +CYREG_PRT3_BIE EQU 0x40005137 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_INP_DIS +CYREG_PRT3_INP_DIS EQU 0x40005138 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CTL +CYREG_PRT3_CTL EQU 0x40005139 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_PRT +CYREG_PRT3_PRT EQU 0x4000513a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_BIT_MASK +CYREG_PRT3_BIT_MASK EQU 0x4000513b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AMUX +CYREG_PRT3_AMUX EQU 0x4000513c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_AG +CYREG_PRT3_AG EQU 0x4000513d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_COM_SEG +CYREG_PRT3_LCD_COM_SEG EQU 0x4000513e + ENDIF + IF :LNOT::DEF:CYREG_PRT3_LCD_EN +CYREG_PRT3_LCD_EN EQU 0x4000513f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_BASE +CYDEV_IO_PRT_PRT4_BASE EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT4_SIZE +CYDEV_IO_PRT_PRT4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DR +CYREG_PRT4_DR EQU 0x40005140 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PS +CYREG_PRT4_PS EQU 0x40005141 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM0 +CYREG_PRT4_DM0 EQU 0x40005142 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM1 +CYREG_PRT4_DM1 EQU 0x40005143 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DM2 +CYREG_PRT4_DM2 EQU 0x40005144 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SLW +CYREG_PRT4_SLW EQU 0x40005145 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BYP +CYREG_PRT4_BYP EQU 0x40005146 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIE +CYREG_PRT4_BIE EQU 0x40005147 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_INP_DIS +CYREG_PRT4_INP_DIS EQU 0x40005148 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CTL +CYREG_PRT4_CTL EQU 0x40005149 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_PRT +CYREG_PRT4_PRT EQU 0x4000514a + ENDIF + IF :LNOT::DEF:CYREG_PRT4_BIT_MASK +CYREG_PRT4_BIT_MASK EQU 0x4000514b + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AMUX +CYREG_PRT4_AMUX EQU 0x4000514c + ENDIF + IF :LNOT::DEF:CYREG_PRT4_AG +CYREG_PRT4_AG EQU 0x4000514d + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_COM_SEG +CYREG_PRT4_LCD_COM_SEG EQU 0x4000514e + ENDIF + IF :LNOT::DEF:CYREG_PRT4_LCD_EN +CYREG_PRT4_LCD_EN EQU 0x4000514f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_BASE +CYDEV_IO_PRT_PRT5_BASE EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT5_SIZE +CYDEV_IO_PRT_PRT5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DR +CYREG_PRT5_DR EQU 0x40005150 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PS +CYREG_PRT5_PS EQU 0x40005151 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM0 +CYREG_PRT5_DM0 EQU 0x40005152 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM1 +CYREG_PRT5_DM1 EQU 0x40005153 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DM2 +CYREG_PRT5_DM2 EQU 0x40005154 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SLW +CYREG_PRT5_SLW EQU 0x40005155 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BYP +CYREG_PRT5_BYP EQU 0x40005156 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIE +CYREG_PRT5_BIE EQU 0x40005157 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_INP_DIS +CYREG_PRT5_INP_DIS EQU 0x40005158 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CTL +CYREG_PRT5_CTL EQU 0x40005159 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_PRT +CYREG_PRT5_PRT EQU 0x4000515a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_BIT_MASK +CYREG_PRT5_BIT_MASK EQU 0x4000515b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AMUX +CYREG_PRT5_AMUX EQU 0x4000515c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_AG +CYREG_PRT5_AG EQU 0x4000515d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_COM_SEG +CYREG_PRT5_LCD_COM_SEG EQU 0x4000515e + ENDIF + IF :LNOT::DEF:CYREG_PRT5_LCD_EN +CYREG_PRT5_LCD_EN EQU 0x4000515f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_BASE +CYDEV_IO_PRT_PRT6_BASE EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT6_SIZE +CYDEV_IO_PRT_PRT6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DR +CYREG_PRT6_DR EQU 0x40005160 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PS +CYREG_PRT6_PS EQU 0x40005161 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM0 +CYREG_PRT6_DM0 EQU 0x40005162 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM1 +CYREG_PRT6_DM1 EQU 0x40005163 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DM2 +CYREG_PRT6_DM2 EQU 0x40005164 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SLW +CYREG_PRT6_SLW EQU 0x40005165 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BYP +CYREG_PRT6_BYP EQU 0x40005166 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIE +CYREG_PRT6_BIE EQU 0x40005167 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_INP_DIS +CYREG_PRT6_INP_DIS EQU 0x40005168 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CTL +CYREG_PRT6_CTL EQU 0x40005169 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_PRT +CYREG_PRT6_PRT EQU 0x4000516a + ENDIF + IF :LNOT::DEF:CYREG_PRT6_BIT_MASK +CYREG_PRT6_BIT_MASK EQU 0x4000516b + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AMUX +CYREG_PRT6_AMUX EQU 0x4000516c + ENDIF + IF :LNOT::DEF:CYREG_PRT6_AG +CYREG_PRT6_AG EQU 0x4000516d + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_COM_SEG +CYREG_PRT6_LCD_COM_SEG EQU 0x4000516e + ENDIF + IF :LNOT::DEF:CYREG_PRT6_LCD_EN +CYREG_PRT6_LCD_EN EQU 0x4000516f + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_BASE +CYDEV_IO_PRT_PRT12_BASE EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT12_SIZE +CYDEV_IO_PRT_PRT12_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DR +CYREG_PRT12_DR EQU 0x400051c0 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PS +CYREG_PRT12_PS EQU 0x400051c1 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM0 +CYREG_PRT12_DM0 EQU 0x400051c2 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM1 +CYREG_PRT12_DM1 EQU 0x400051c3 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DM2 +CYREG_PRT12_DM2 EQU 0x400051c4 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SLW +CYREG_PRT12_SLW EQU 0x400051c5 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BYP +CYREG_PRT12_BYP EQU 0x400051c6 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIE +CYREG_PRT12_BIE EQU 0x400051c7 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_INP_DIS +CYREG_PRT12_INP_DIS EQU 0x400051c8 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_HYST_EN +CYREG_PRT12_SIO_HYST_EN EQU 0x400051c9 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_PRT +CYREG_PRT12_PRT EQU 0x400051ca + ENDIF + IF :LNOT::DEF:CYREG_PRT12_BIT_MASK +CYREG_PRT12_BIT_MASK EQU 0x400051cb + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_REG_HIFREQ +CYREG_PRT12_SIO_REG_HIFREQ EQU 0x400051cc + ENDIF + IF :LNOT::DEF:CYREG_PRT12_AG +CYREG_PRT12_AG EQU 0x400051cd + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_CFG +CYREG_PRT12_SIO_CFG EQU 0x400051ce + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SIO_DIFF +CYREG_PRT12_SIO_DIFF EQU 0x400051cf + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_BASE +CYDEV_IO_PRT_PRT15_BASE EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYDEV_IO_PRT_PRT15_SIZE +CYDEV_IO_PRT_PRT15_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DR +CYREG_PRT15_DR EQU 0x400051f0 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PS +CYREG_PRT15_PS EQU 0x400051f1 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM0 +CYREG_PRT15_DM0 EQU 0x400051f2 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM1 +CYREG_PRT15_DM1 EQU 0x400051f3 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DM2 +CYREG_PRT15_DM2 EQU 0x400051f4 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SLW +CYREG_PRT15_SLW EQU 0x400051f5 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BYP +CYREG_PRT15_BYP EQU 0x400051f6 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIE +CYREG_PRT15_BIE EQU 0x400051f7 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_INP_DIS +CYREG_PRT15_INP_DIS EQU 0x400051f8 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CTL +CYREG_PRT15_CTL EQU 0x400051f9 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_PRT +CYREG_PRT15_PRT EQU 0x400051fa + ENDIF + IF :LNOT::DEF:CYREG_PRT15_BIT_MASK +CYREG_PRT15_BIT_MASK EQU 0x400051fb + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AMUX +CYREG_PRT15_AMUX EQU 0x400051fc + ENDIF + IF :LNOT::DEF:CYREG_PRT15_AG +CYREG_PRT15_AG EQU 0x400051fd + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_COM_SEG +CYREG_PRT15_LCD_COM_SEG EQU 0x400051fe + ENDIF + IF :LNOT::DEF:CYREG_PRT15_LCD_EN +CYREG_PRT15_LCD_EN EQU 0x400051ff + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_BASE +CYDEV_PRTDSI_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_SIZE +CYDEV_PRTDSI_SIZE EQU 0x0000007f + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_BASE +CYDEV_PRTDSI_PRT0_BASE EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT0_SIZE +CYDEV_PRTDSI_PRT0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL0 +CYREG_PRT0_OUT_SEL0 EQU 0x40005200 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OUT_SEL1 +CYREG_PRT0_OUT_SEL1 EQU 0x40005201 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL0 +CYREG_PRT0_OE_SEL0 EQU 0x40005202 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_OE_SEL1 +CYREG_PRT0_OE_SEL1 EQU 0x40005203 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_DBL_SYNC_IN +CYREG_PRT0_DBL_SYNC_IN EQU 0x40005204 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_SYNC_OUT +CYREG_PRT0_SYNC_OUT EQU 0x40005205 + ENDIF + IF :LNOT::DEF:CYREG_PRT0_CAPS_SEL +CYREG_PRT0_CAPS_SEL EQU 0x40005206 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_BASE +CYDEV_PRTDSI_PRT1_BASE EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT1_SIZE +CYDEV_PRTDSI_PRT1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL0 +CYREG_PRT1_OUT_SEL0 EQU 0x40005208 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OUT_SEL1 +CYREG_PRT1_OUT_SEL1 EQU 0x40005209 + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL0 +CYREG_PRT1_OE_SEL0 EQU 0x4000520a + ENDIF + IF :LNOT::DEF:CYREG_PRT1_OE_SEL1 +CYREG_PRT1_OE_SEL1 EQU 0x4000520b + ENDIF + IF :LNOT::DEF:CYREG_PRT1_DBL_SYNC_IN +CYREG_PRT1_DBL_SYNC_IN EQU 0x4000520c + ENDIF + IF :LNOT::DEF:CYREG_PRT1_SYNC_OUT +CYREG_PRT1_SYNC_OUT EQU 0x4000520d + ENDIF + IF :LNOT::DEF:CYREG_PRT1_CAPS_SEL +CYREG_PRT1_CAPS_SEL EQU 0x4000520e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_BASE +CYDEV_PRTDSI_PRT2_BASE EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT2_SIZE +CYDEV_PRTDSI_PRT2_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL0 +CYREG_PRT2_OUT_SEL0 EQU 0x40005210 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OUT_SEL1 +CYREG_PRT2_OUT_SEL1 EQU 0x40005211 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL0 +CYREG_PRT2_OE_SEL0 EQU 0x40005212 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_OE_SEL1 +CYREG_PRT2_OE_SEL1 EQU 0x40005213 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_DBL_SYNC_IN +CYREG_PRT2_DBL_SYNC_IN EQU 0x40005214 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_SYNC_OUT +CYREG_PRT2_SYNC_OUT EQU 0x40005215 + ENDIF + IF :LNOT::DEF:CYREG_PRT2_CAPS_SEL +CYREG_PRT2_CAPS_SEL EQU 0x40005216 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_BASE +CYDEV_PRTDSI_PRT3_BASE EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT3_SIZE +CYDEV_PRTDSI_PRT3_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL0 +CYREG_PRT3_OUT_SEL0 EQU 0x40005218 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OUT_SEL1 +CYREG_PRT3_OUT_SEL1 EQU 0x40005219 + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL0 +CYREG_PRT3_OE_SEL0 EQU 0x4000521a + ENDIF + IF :LNOT::DEF:CYREG_PRT3_OE_SEL1 +CYREG_PRT3_OE_SEL1 EQU 0x4000521b + ENDIF + IF :LNOT::DEF:CYREG_PRT3_DBL_SYNC_IN +CYREG_PRT3_DBL_SYNC_IN EQU 0x4000521c + ENDIF + IF :LNOT::DEF:CYREG_PRT3_SYNC_OUT +CYREG_PRT3_SYNC_OUT EQU 0x4000521d + ENDIF + IF :LNOT::DEF:CYREG_PRT3_CAPS_SEL +CYREG_PRT3_CAPS_SEL EQU 0x4000521e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_BASE +CYDEV_PRTDSI_PRT4_BASE EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT4_SIZE +CYDEV_PRTDSI_PRT4_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL0 +CYREG_PRT4_OUT_SEL0 EQU 0x40005220 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OUT_SEL1 +CYREG_PRT4_OUT_SEL1 EQU 0x40005221 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL0 +CYREG_PRT4_OE_SEL0 EQU 0x40005222 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_OE_SEL1 +CYREG_PRT4_OE_SEL1 EQU 0x40005223 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_DBL_SYNC_IN +CYREG_PRT4_DBL_SYNC_IN EQU 0x40005224 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_SYNC_OUT +CYREG_PRT4_SYNC_OUT EQU 0x40005225 + ENDIF + IF :LNOT::DEF:CYREG_PRT4_CAPS_SEL +CYREG_PRT4_CAPS_SEL EQU 0x40005226 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_BASE +CYDEV_PRTDSI_PRT5_BASE EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT5_SIZE +CYDEV_PRTDSI_PRT5_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL0 +CYREG_PRT5_OUT_SEL0 EQU 0x40005228 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OUT_SEL1 +CYREG_PRT5_OUT_SEL1 EQU 0x40005229 + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL0 +CYREG_PRT5_OE_SEL0 EQU 0x4000522a + ENDIF + IF :LNOT::DEF:CYREG_PRT5_OE_SEL1 +CYREG_PRT5_OE_SEL1 EQU 0x4000522b + ENDIF + IF :LNOT::DEF:CYREG_PRT5_DBL_SYNC_IN +CYREG_PRT5_DBL_SYNC_IN EQU 0x4000522c + ENDIF + IF :LNOT::DEF:CYREG_PRT5_SYNC_OUT +CYREG_PRT5_SYNC_OUT EQU 0x4000522d + ENDIF + IF :LNOT::DEF:CYREG_PRT5_CAPS_SEL +CYREG_PRT5_CAPS_SEL EQU 0x4000522e + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_BASE +CYDEV_PRTDSI_PRT6_BASE EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT6_SIZE +CYDEV_PRTDSI_PRT6_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL0 +CYREG_PRT6_OUT_SEL0 EQU 0x40005230 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OUT_SEL1 +CYREG_PRT6_OUT_SEL1 EQU 0x40005231 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL0 +CYREG_PRT6_OE_SEL0 EQU 0x40005232 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_OE_SEL1 +CYREG_PRT6_OE_SEL1 EQU 0x40005233 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_DBL_SYNC_IN +CYREG_PRT6_DBL_SYNC_IN EQU 0x40005234 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_SYNC_OUT +CYREG_PRT6_SYNC_OUT EQU 0x40005235 + ENDIF + IF :LNOT::DEF:CYREG_PRT6_CAPS_SEL +CYREG_PRT6_CAPS_SEL EQU 0x40005236 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_BASE +CYDEV_PRTDSI_PRT12_BASE EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT12_SIZE +CYDEV_PRTDSI_PRT12_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL0 +CYREG_PRT12_OUT_SEL0 EQU 0x40005260 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OUT_SEL1 +CYREG_PRT12_OUT_SEL1 EQU 0x40005261 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL0 +CYREG_PRT12_OE_SEL0 EQU 0x40005262 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_OE_SEL1 +CYREG_PRT12_OE_SEL1 EQU 0x40005263 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_DBL_SYNC_IN +CYREG_PRT12_DBL_SYNC_IN EQU 0x40005264 + ENDIF + IF :LNOT::DEF:CYREG_PRT12_SYNC_OUT +CYREG_PRT12_SYNC_OUT EQU 0x40005265 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_BASE +CYDEV_PRTDSI_PRT15_BASE EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYDEV_PRTDSI_PRT15_SIZE +CYDEV_PRTDSI_PRT15_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL0 +CYREG_PRT15_OUT_SEL0 EQU 0x40005278 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OUT_SEL1 +CYREG_PRT15_OUT_SEL1 EQU 0x40005279 + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL0 +CYREG_PRT15_OE_SEL0 EQU 0x4000527a + ENDIF + IF :LNOT::DEF:CYREG_PRT15_OE_SEL1 +CYREG_PRT15_OE_SEL1 EQU 0x4000527b + ENDIF + IF :LNOT::DEF:CYREG_PRT15_DBL_SYNC_IN +CYREG_PRT15_DBL_SYNC_IN EQU 0x4000527c + ENDIF + IF :LNOT::DEF:CYREG_PRT15_SYNC_OUT +CYREG_PRT15_SYNC_OUT EQU 0x4000527d + ENDIF + IF :LNOT::DEF:CYREG_PRT15_CAPS_SEL +CYREG_PRT15_CAPS_SEL EQU 0x4000527e + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_BASE +CYDEV_EMIF_BASE EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYDEV_EMIF_SIZE +CYDEV_EMIF_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_NO_UDB +CYREG_EMIF_NO_UDB EQU 0x40005400 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_RP_WAIT_STATES +CYREG_EMIF_RP_WAIT_STATES EQU 0x40005401 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEM_DWN +CYREG_EMIF_MEM_DWN EQU 0x40005402 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_MEMCLK_DIV +CYREG_EMIF_MEMCLK_DIV EQU 0x40005403 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_CLOCK_EN +CYREG_EMIF_CLOCK_EN EQU 0x40005404 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_EM_TYPE +CYREG_EMIF_EM_TYPE EQU 0x40005405 + ENDIF + IF :LNOT::DEF:CYREG_EMIF_WP_WAIT_STATES +CYREG_EMIF_WP_WAIT_STATES EQU 0x40005406 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_BASE +CYDEV_ANAIF_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_SIZE +CYDEV_ANAIF_SIZE EQU 0x000003a9 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BASE +CYDEV_ANAIF_CFG_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SIZE +CYDEV_ANAIF_CFG_SIZE EQU 0x0000010f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_BASE +CYDEV_ANAIF_CFG_SC0_BASE EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC0_SIZE +CYDEV_ANAIF_CFG_SC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR0 +CYREG_SC0_CR0 EQU 0x40005800 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR1 +CYREG_SC0_CR1 EQU 0x40005801 + ENDIF + IF :LNOT::DEF:CYREG_SC0_CR2 +CYREG_SC0_CR2 EQU 0x40005802 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_BASE +CYDEV_ANAIF_CFG_SC1_BASE EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC1_SIZE +CYDEV_ANAIF_CFG_SC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR0 +CYREG_SC1_CR0 EQU 0x40005804 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR1 +CYREG_SC1_CR1 EQU 0x40005805 + ENDIF + IF :LNOT::DEF:CYREG_SC1_CR2 +CYREG_SC1_CR2 EQU 0x40005806 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_BASE +CYDEV_ANAIF_CFG_SC2_BASE EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC2_SIZE +CYDEV_ANAIF_CFG_SC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR0 +CYREG_SC2_CR0 EQU 0x40005808 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR1 +CYREG_SC2_CR1 EQU 0x40005809 + ENDIF + IF :LNOT::DEF:CYREG_SC2_CR2 +CYREG_SC2_CR2 EQU 0x4000580a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_BASE +CYDEV_ANAIF_CFG_SC3_BASE EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SC3_SIZE +CYDEV_ANAIF_CFG_SC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR0 +CYREG_SC3_CR0 EQU 0x4000580c + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR1 +CYREG_SC3_CR1 EQU 0x4000580d + ENDIF + IF :LNOT::DEF:CYREG_SC3_CR2 +CYREG_SC3_CR2 EQU 0x4000580e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_BASE +CYDEV_ANAIF_CFG_DAC0_BASE EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC0_SIZE +CYDEV_ANAIF_CFG_DAC0_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR0 +CYREG_DAC0_CR0 EQU 0x40005820 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_CR1 +CYREG_DAC0_CR1 EQU 0x40005821 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_TST +CYREG_DAC0_TST EQU 0x40005822 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_BASE +CYDEV_ANAIF_CFG_DAC1_BASE EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC1_SIZE +CYDEV_ANAIF_CFG_DAC1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR0 +CYREG_DAC1_CR0 EQU 0x40005824 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_CR1 +CYREG_DAC1_CR1 EQU 0x40005825 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_TST +CYREG_DAC1_TST EQU 0x40005826 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_BASE +CYDEV_ANAIF_CFG_DAC2_BASE EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC2_SIZE +CYDEV_ANAIF_CFG_DAC2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR0 +CYREG_DAC2_CR0 EQU 0x40005828 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_CR1 +CYREG_DAC2_CR1 EQU 0x40005829 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_TST +CYREG_DAC2_TST EQU 0x4000582a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_BASE +CYDEV_ANAIF_CFG_DAC3_BASE EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DAC3_SIZE +CYDEV_ANAIF_CFG_DAC3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR0 +CYREG_DAC3_CR0 EQU 0x4000582c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_CR1 +CYREG_DAC3_CR1 EQU 0x4000582d + ENDIF + IF :LNOT::DEF:CYREG_DAC3_TST +CYREG_DAC3_TST EQU 0x4000582e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_BASE +CYDEV_ANAIF_CFG_CMP0_BASE EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP0_SIZE +CYDEV_ANAIF_CFG_CMP0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CR +CYREG_CMP0_CR EQU 0x40005840 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_BASE +CYDEV_ANAIF_CFG_CMP1_BASE EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP1_SIZE +CYDEV_ANAIF_CFG_CMP1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CR +CYREG_CMP1_CR EQU 0x40005841 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_BASE +CYDEV_ANAIF_CFG_CMP2_BASE EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP2_SIZE +CYDEV_ANAIF_CFG_CMP2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CR +CYREG_CMP2_CR EQU 0x40005842 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_BASE +CYDEV_ANAIF_CFG_CMP3_BASE EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CMP3_SIZE +CYDEV_ANAIF_CFG_CMP3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CR +CYREG_CMP3_CR EQU 0x40005843 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_BASE +CYDEV_ANAIF_CFG_LUT0_BASE EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT0_SIZE +CYDEV_ANAIF_CFG_LUT0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_CR +CYREG_LUT0_CR EQU 0x40005848 + ENDIF + IF :LNOT::DEF:CYREG_LUT0_MX +CYREG_LUT0_MX EQU 0x40005849 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_BASE +CYDEV_ANAIF_CFG_LUT1_BASE EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT1_SIZE +CYDEV_ANAIF_CFG_LUT1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT1_CR +CYREG_LUT1_CR EQU 0x4000584a + ENDIF + IF :LNOT::DEF:CYREG_LUT1_MX +CYREG_LUT1_MX EQU 0x4000584b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_BASE +CYDEV_ANAIF_CFG_LUT2_BASE EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT2_SIZE +CYDEV_ANAIF_CFG_LUT2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT2_CR +CYREG_LUT2_CR EQU 0x4000584c + ENDIF + IF :LNOT::DEF:CYREG_LUT2_MX +CYREG_LUT2_MX EQU 0x4000584d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_BASE +CYDEV_ANAIF_CFG_LUT3_BASE EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LUT3_SIZE +CYDEV_ANAIF_CFG_LUT3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LUT3_CR +CYREG_LUT3_CR EQU 0x4000584e + ENDIF + IF :LNOT::DEF:CYREG_LUT3_MX +CYREG_LUT3_MX EQU 0x4000584f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_BASE +CYDEV_ANAIF_CFG_OPAMP0_BASE EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP0_SIZE +CYDEV_ANAIF_CFG_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_CR +CYREG_OPAMP0_CR EQU 0x40005858 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_RSVD +CYREG_OPAMP0_RSVD EQU 0x40005859 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_BASE +CYDEV_ANAIF_CFG_OPAMP1_BASE EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP1_SIZE +CYDEV_ANAIF_CFG_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_CR +CYREG_OPAMP1_CR EQU 0x4000585a + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_RSVD +CYREG_OPAMP1_RSVD EQU 0x4000585b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_BASE +CYDEV_ANAIF_CFG_OPAMP2_BASE EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP2_SIZE +CYDEV_ANAIF_CFG_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_CR +CYREG_OPAMP2_CR EQU 0x4000585c + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_RSVD +CYREG_OPAMP2_RSVD EQU 0x4000585d + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_BASE +CYDEV_ANAIF_CFG_OPAMP3_BASE EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_OPAMP3_SIZE +CYDEV_ANAIF_CFG_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_CR +CYREG_OPAMP3_CR EQU 0x4000585e + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_RSVD +CYREG_OPAMP3_RSVD EQU 0x4000585f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_BASE +CYDEV_ANAIF_CFG_LCDDAC_BASE EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDAC_SIZE +CYDEV_ANAIF_CFG_LCDDAC_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR0 +CYREG_LCDDAC_CR0 EQU 0x40005868 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_CR1 +CYREG_LCDDAC_CR1 EQU 0x40005869 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_BASE +CYDEV_ANAIF_CFG_LCDDRV_BASE EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDDRV_SIZE +CYDEV_ANAIF_CFG_LCDDRV_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDDRV_CR +CYREG_LCDDRV_CR EQU 0x4000586a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_BASE +CYDEV_ANAIF_CFG_LCDTMR_BASE EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LCDTMR_SIZE +CYDEV_ANAIF_CFG_LCDTMR_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_LCDTMR_CFG +CYREG_LCDTMR_CFG EQU 0x4000586b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_BASE +CYDEV_ANAIF_CFG_BG_BASE EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_BG_SIZE +CYDEV_ANAIF_CFG_BG_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BG_CR0 +CYREG_BG_CR0 EQU 0x4000586c + ENDIF + IF :LNOT::DEF:CYREG_BG_RSVD +CYREG_BG_RSVD EQU 0x4000586d + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT0 +CYREG_BG_DFT0 EQU 0x4000586e + ENDIF + IF :LNOT::DEF:CYREG_BG_DFT1 +CYREG_BG_DFT1 EQU 0x4000586f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_BASE +CYDEV_ANAIF_CFG_CAPSL_BASE EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSL_SIZE +CYDEV_ANAIF_CFG_CAPSL_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG0 +CYREG_CAPSL_CFG0 EQU 0x40005870 + ENDIF + IF :LNOT::DEF:CYREG_CAPSL_CFG1 +CYREG_CAPSL_CFG1 EQU 0x40005871 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_BASE +CYDEV_ANAIF_CFG_CAPSR_BASE EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_CAPSR_SIZE +CYDEV_ANAIF_CFG_CAPSR_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG0 +CYREG_CAPSR_CFG0 EQU 0x40005872 + ENDIF + IF :LNOT::DEF:CYREG_CAPSR_CFG1 +CYREG_CAPSR_CFG1 EQU 0x40005873 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_BASE +CYDEV_ANAIF_CFG_PUMP_BASE EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_PUMP_SIZE +CYDEV_ANAIF_CFG_PUMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR0 +CYREG_PUMP_CR0 EQU 0x40005876 + ENDIF + IF :LNOT::DEF:CYREG_PUMP_CR1 +CYREG_PUMP_CR1 EQU 0x40005877 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_BASE +CYDEV_ANAIF_CFG_LPF0_BASE EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF0_SIZE +CYDEV_ANAIF_CFG_LPF0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_CR0 +CYREG_LPF0_CR0 EQU 0x40005878 + ENDIF + IF :LNOT::DEF:CYREG_LPF0_RSVD +CYREG_LPF0_RSVD EQU 0x40005879 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_BASE +CYDEV_ANAIF_CFG_LPF1_BASE EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_LPF1_SIZE +CYDEV_ANAIF_CFG_LPF1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_LPF1_CR0 +CYREG_LPF1_CR0 EQU 0x4000587a + ENDIF + IF :LNOT::DEF:CYREG_LPF1_RSVD +CYREG_LPF1_RSVD EQU 0x4000587b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_BASE +CYDEV_ANAIF_CFG_MISC_BASE EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_MISC_SIZE +CYDEV_ANAIF_CFG_MISC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_CFG_MISC_CR0 +CYREG_ANAIF_CFG_MISC_CR0 EQU 0x4000587c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_BASE +CYDEV_ANAIF_CFG_DSM0_BASE EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_DSM0_SIZE +CYDEV_ANAIF_CFG_DSM0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR0 +CYREG_DSM0_CR0 EQU 0x40005880 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR1 +CYREG_DSM0_CR1 EQU 0x40005881 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR2 +CYREG_DSM0_CR2 EQU 0x40005882 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR3 +CYREG_DSM0_CR3 EQU 0x40005883 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR4 +CYREG_DSM0_CR4 EQU 0x40005884 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR5 +CYREG_DSM0_CR5 EQU 0x40005885 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR6 +CYREG_DSM0_CR6 EQU 0x40005886 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR7 +CYREG_DSM0_CR7 EQU 0x40005887 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR8 +CYREG_DSM0_CR8 EQU 0x40005888 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR9 +CYREG_DSM0_CR9 EQU 0x40005889 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR10 +CYREG_DSM0_CR10 EQU 0x4000588a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR11 +CYREG_DSM0_CR11 EQU 0x4000588b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR12 +CYREG_DSM0_CR12 EQU 0x4000588c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR13 +CYREG_DSM0_CR13 EQU 0x4000588d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR14 +CYREG_DSM0_CR14 EQU 0x4000588e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR15 +CYREG_DSM0_CR15 EQU 0x4000588f + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR16 +CYREG_DSM0_CR16 EQU 0x40005890 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CR17 +CYREG_DSM0_CR17 EQU 0x40005891 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF0 +CYREG_DSM0_REF0 EQU 0x40005892 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF1 +CYREG_DSM0_REF1 EQU 0x40005893 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF2 +CYREG_DSM0_REF2 EQU 0x40005894 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_REF3 +CYREG_DSM0_REF3 EQU 0x40005895 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM0 +CYREG_DSM0_DEM0 EQU 0x40005896 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_DEM1 +CYREG_DSM0_DEM1 EQU 0x40005897 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST0 +CYREG_DSM0_TST0 EQU 0x40005898 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_TST1 +CYREG_DSM0_TST1 EQU 0x40005899 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF0 +CYREG_DSM0_BUF0 EQU 0x4000589a + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF1 +CYREG_DSM0_BUF1 EQU 0x4000589b + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF2 +CYREG_DSM0_BUF2 EQU 0x4000589c + ENDIF + IF :LNOT::DEF:CYREG_DSM0_BUF3 +CYREG_DSM0_BUF3 EQU 0x4000589d + ENDIF + IF :LNOT::DEF:CYREG_DSM0_MISC +CYREG_DSM0_MISC EQU 0x4000589e + ENDIF + IF :LNOT::DEF:CYREG_DSM0_RSVD1 +CYREG_DSM0_RSVD1 EQU 0x4000589f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_BASE +CYDEV_ANAIF_CFG_SAR0_BASE EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR0_SIZE +CYDEV_ANAIF_CFG_SAR0_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR0 +CYREG_SAR0_CSR0 EQU 0x40005900 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR1 +CYREG_SAR0_CSR1 EQU 0x40005901 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR2 +CYREG_SAR0_CSR2 EQU 0x40005902 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR3 +CYREG_SAR0_CSR3 EQU 0x40005903 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR4 +CYREG_SAR0_CSR4 EQU 0x40005904 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR5 +CYREG_SAR0_CSR5 EQU 0x40005905 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CSR6 +CYREG_SAR0_CSR6 EQU 0x40005906 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_BASE +CYDEV_ANAIF_CFG_SAR1_BASE EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_CFG_SAR1_SIZE +CYDEV_ANAIF_CFG_SAR1_SIZE EQU 0x00000007 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR0 +CYREG_SAR1_CSR0 EQU 0x40005908 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR1 +CYREG_SAR1_CSR1 EQU 0x40005909 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR2 +CYREG_SAR1_CSR2 EQU 0x4000590a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR3 +CYREG_SAR1_CSR3 EQU 0x4000590b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR4 +CYREG_SAR1_CSR4 EQU 0x4000590c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR5 +CYREG_SAR1_CSR5 EQU 0x4000590d + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CSR6 +CYREG_SAR1_CSR6 EQU 0x4000590e + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BASE +CYDEV_ANAIF_RT_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SIZE +CYDEV_ANAIF_RT_SIZE EQU 0x00000162 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_BASE +CYDEV_ANAIF_RT_SC0_BASE EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC0_SIZE +CYDEV_ANAIF_RT_SC0_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW0 +CYREG_SC0_SW0 EQU 0x40005a00 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW2 +CYREG_SC0_SW2 EQU 0x40005a02 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW3 +CYREG_SC0_SW3 EQU 0x40005a03 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW4 +CYREG_SC0_SW4 EQU 0x40005a04 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW6 +CYREG_SC0_SW6 EQU 0x40005a06 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW7 +CYREG_SC0_SW7 EQU 0x40005a07 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW8 +CYREG_SC0_SW8 EQU 0x40005a08 + ENDIF + IF :LNOT::DEF:CYREG_SC0_SW10 +CYREG_SC0_SW10 EQU 0x40005a0a + ENDIF + IF :LNOT::DEF:CYREG_SC0_CLK +CYREG_SC0_CLK EQU 0x40005a0b + ENDIF + IF :LNOT::DEF:CYREG_SC0_BST +CYREG_SC0_BST EQU 0x40005a0c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_BASE +CYDEV_ANAIF_RT_SC1_BASE EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC1_SIZE +CYDEV_ANAIF_RT_SC1_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW0 +CYREG_SC1_SW0 EQU 0x40005a10 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW2 +CYREG_SC1_SW2 EQU 0x40005a12 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW3 +CYREG_SC1_SW3 EQU 0x40005a13 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW4 +CYREG_SC1_SW4 EQU 0x40005a14 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW6 +CYREG_SC1_SW6 EQU 0x40005a16 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW7 +CYREG_SC1_SW7 EQU 0x40005a17 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW8 +CYREG_SC1_SW8 EQU 0x40005a18 + ENDIF + IF :LNOT::DEF:CYREG_SC1_SW10 +CYREG_SC1_SW10 EQU 0x40005a1a + ENDIF + IF :LNOT::DEF:CYREG_SC1_CLK +CYREG_SC1_CLK EQU 0x40005a1b + ENDIF + IF :LNOT::DEF:CYREG_SC1_BST +CYREG_SC1_BST EQU 0x40005a1c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_BASE +CYDEV_ANAIF_RT_SC2_BASE EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC2_SIZE +CYDEV_ANAIF_RT_SC2_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW0 +CYREG_SC2_SW0 EQU 0x40005a20 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW2 +CYREG_SC2_SW2 EQU 0x40005a22 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW3 +CYREG_SC2_SW3 EQU 0x40005a23 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW4 +CYREG_SC2_SW4 EQU 0x40005a24 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW6 +CYREG_SC2_SW6 EQU 0x40005a26 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW7 +CYREG_SC2_SW7 EQU 0x40005a27 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW8 +CYREG_SC2_SW8 EQU 0x40005a28 + ENDIF + IF :LNOT::DEF:CYREG_SC2_SW10 +CYREG_SC2_SW10 EQU 0x40005a2a + ENDIF + IF :LNOT::DEF:CYREG_SC2_CLK +CYREG_SC2_CLK EQU 0x40005a2b + ENDIF + IF :LNOT::DEF:CYREG_SC2_BST +CYREG_SC2_BST EQU 0x40005a2c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_BASE +CYDEV_ANAIF_RT_SC3_BASE EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC3_SIZE +CYDEV_ANAIF_RT_SC3_SIZE EQU 0x0000000d + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW0 +CYREG_SC3_SW0 EQU 0x40005a30 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW2 +CYREG_SC3_SW2 EQU 0x40005a32 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW3 +CYREG_SC3_SW3 EQU 0x40005a33 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW4 +CYREG_SC3_SW4 EQU 0x40005a34 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW6 +CYREG_SC3_SW6 EQU 0x40005a36 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW7 +CYREG_SC3_SW7 EQU 0x40005a37 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW8 +CYREG_SC3_SW8 EQU 0x40005a38 + ENDIF + IF :LNOT::DEF:CYREG_SC3_SW10 +CYREG_SC3_SW10 EQU 0x40005a3a + ENDIF + IF :LNOT::DEF:CYREG_SC3_CLK +CYREG_SC3_CLK EQU 0x40005a3b + ENDIF + IF :LNOT::DEF:CYREG_SC3_BST +CYREG_SC3_BST EQU 0x40005a3c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_BASE +CYDEV_ANAIF_RT_DAC0_BASE EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC0_SIZE +CYDEV_ANAIF_RT_DAC0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW0 +CYREG_DAC0_SW0 EQU 0x40005a80 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW2 +CYREG_DAC0_SW2 EQU 0x40005a82 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW3 +CYREG_DAC0_SW3 EQU 0x40005a83 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_SW4 +CYREG_DAC0_SW4 EQU 0x40005a84 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_STROBE +CYREG_DAC0_STROBE EQU 0x40005a87 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_BASE +CYDEV_ANAIF_RT_DAC1_BASE EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC1_SIZE +CYDEV_ANAIF_RT_DAC1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW0 +CYREG_DAC1_SW0 EQU 0x40005a88 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW2 +CYREG_DAC1_SW2 EQU 0x40005a8a + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW3 +CYREG_DAC1_SW3 EQU 0x40005a8b + ENDIF + IF :LNOT::DEF:CYREG_DAC1_SW4 +CYREG_DAC1_SW4 EQU 0x40005a8c + ENDIF + IF :LNOT::DEF:CYREG_DAC1_STROBE +CYREG_DAC1_STROBE EQU 0x40005a8f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_BASE +CYDEV_ANAIF_RT_DAC2_BASE EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC2_SIZE +CYDEV_ANAIF_RT_DAC2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW0 +CYREG_DAC2_SW0 EQU 0x40005a90 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW2 +CYREG_DAC2_SW2 EQU 0x40005a92 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW3 +CYREG_DAC2_SW3 EQU 0x40005a93 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_SW4 +CYREG_DAC2_SW4 EQU 0x40005a94 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_STROBE +CYREG_DAC2_STROBE EQU 0x40005a97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_BASE +CYDEV_ANAIF_RT_DAC3_BASE EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DAC3_SIZE +CYDEV_ANAIF_RT_DAC3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW0 +CYREG_DAC3_SW0 EQU 0x40005a98 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW2 +CYREG_DAC3_SW2 EQU 0x40005a9a + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW3 +CYREG_DAC3_SW3 EQU 0x40005a9b + ENDIF + IF :LNOT::DEF:CYREG_DAC3_SW4 +CYREG_DAC3_SW4 EQU 0x40005a9c + ENDIF + IF :LNOT::DEF:CYREG_DAC3_STROBE +CYREG_DAC3_STROBE EQU 0x40005a9f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_BASE +CYDEV_ANAIF_RT_CMP0_BASE EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP0_SIZE +CYDEV_ANAIF_RT_CMP0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW0 +CYREG_CMP0_SW0 EQU 0x40005ac0 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW2 +CYREG_CMP0_SW2 EQU 0x40005ac2 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW3 +CYREG_CMP0_SW3 EQU 0x40005ac3 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW4 +CYREG_CMP0_SW4 EQU 0x40005ac4 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_SW6 +CYREG_CMP0_SW6 EQU 0x40005ac6 + ENDIF + IF :LNOT::DEF:CYREG_CMP0_CLK +CYREG_CMP0_CLK EQU 0x40005ac7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_BASE +CYDEV_ANAIF_RT_CMP1_BASE EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP1_SIZE +CYDEV_ANAIF_RT_CMP1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW0 +CYREG_CMP1_SW0 EQU 0x40005ac8 + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW2 +CYREG_CMP1_SW2 EQU 0x40005aca + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW3 +CYREG_CMP1_SW3 EQU 0x40005acb + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW4 +CYREG_CMP1_SW4 EQU 0x40005acc + ENDIF + IF :LNOT::DEF:CYREG_CMP1_SW6 +CYREG_CMP1_SW6 EQU 0x40005ace + ENDIF + IF :LNOT::DEF:CYREG_CMP1_CLK +CYREG_CMP1_CLK EQU 0x40005acf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_BASE +CYDEV_ANAIF_RT_CMP2_BASE EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP2_SIZE +CYDEV_ANAIF_RT_CMP2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW0 +CYREG_CMP2_SW0 EQU 0x40005ad0 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW2 +CYREG_CMP2_SW2 EQU 0x40005ad2 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW3 +CYREG_CMP2_SW3 EQU 0x40005ad3 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW4 +CYREG_CMP2_SW4 EQU 0x40005ad4 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_SW6 +CYREG_CMP2_SW6 EQU 0x40005ad6 + ENDIF + IF :LNOT::DEF:CYREG_CMP2_CLK +CYREG_CMP2_CLK EQU 0x40005ad7 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_BASE +CYDEV_ANAIF_RT_CMP3_BASE EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_CMP3_SIZE +CYDEV_ANAIF_RT_CMP3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW0 +CYREG_CMP3_SW0 EQU 0x40005ad8 + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW2 +CYREG_CMP3_SW2 EQU 0x40005ada + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW3 +CYREG_CMP3_SW3 EQU 0x40005adb + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW4 +CYREG_CMP3_SW4 EQU 0x40005adc + ENDIF + IF :LNOT::DEF:CYREG_CMP3_SW6 +CYREG_CMP3_SW6 EQU 0x40005ade + ENDIF + IF :LNOT::DEF:CYREG_CMP3_CLK +CYREG_CMP3_CLK EQU 0x40005adf + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_BASE +CYDEV_ANAIF_RT_DSM0_BASE EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DSM0_SIZE +CYDEV_ANAIF_RT_DSM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW0 +CYREG_DSM0_SW0 EQU 0x40005b00 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW2 +CYREG_DSM0_SW2 EQU 0x40005b02 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW3 +CYREG_DSM0_SW3 EQU 0x40005b03 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW4 +CYREG_DSM0_SW4 EQU 0x40005b04 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_SW6 +CYREG_DSM0_SW6 EQU 0x40005b06 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_CLK +CYREG_DSM0_CLK EQU 0x40005b07 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_BASE +CYDEV_ANAIF_RT_SAR0_BASE EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR0_SIZE +CYDEV_ANAIF_RT_SAR0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW0 +CYREG_SAR0_SW0 EQU 0x40005b20 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW2 +CYREG_SAR0_SW2 EQU 0x40005b22 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW3 +CYREG_SAR0_SW3 EQU 0x40005b23 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW4 +CYREG_SAR0_SW4 EQU 0x40005b24 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_SW6 +CYREG_SAR0_SW6 EQU 0x40005b26 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_CLK +CYREG_SAR0_CLK EQU 0x40005b27 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_BASE +CYDEV_ANAIF_RT_SAR1_BASE EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SAR1_SIZE +CYDEV_ANAIF_RT_SAR1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW0 +CYREG_SAR1_SW0 EQU 0x40005b28 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW2 +CYREG_SAR1_SW2 EQU 0x40005b2a + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW3 +CYREG_SAR1_SW3 EQU 0x40005b2b + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW4 +CYREG_SAR1_SW4 EQU 0x40005b2c + ENDIF + IF :LNOT::DEF:CYREG_SAR1_SW6 +CYREG_SAR1_SW6 EQU 0x40005b2e + ENDIF + IF :LNOT::DEF:CYREG_SAR1_CLK +CYREG_SAR1_CLK EQU 0x40005b2f + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_BASE +CYDEV_ANAIF_RT_OPAMP0_BASE EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP0_SIZE +CYDEV_ANAIF_RT_OPAMP0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_MX +CYREG_OPAMP0_MX EQU 0x40005b40 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP0_SW +CYREG_OPAMP0_SW EQU 0x40005b41 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_BASE +CYDEV_ANAIF_RT_OPAMP1_BASE EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP1_SIZE +CYDEV_ANAIF_RT_OPAMP1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_MX +CYREG_OPAMP1_MX EQU 0x40005b42 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP1_SW +CYREG_OPAMP1_SW EQU 0x40005b43 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_BASE +CYDEV_ANAIF_RT_OPAMP2_BASE EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP2_SIZE +CYDEV_ANAIF_RT_OPAMP2_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_MX +CYREG_OPAMP2_MX EQU 0x40005b44 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP2_SW +CYREG_OPAMP2_SW EQU 0x40005b45 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_BASE +CYDEV_ANAIF_RT_OPAMP3_BASE EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_OPAMP3_SIZE +CYDEV_ANAIF_RT_OPAMP3_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_MX +CYREG_OPAMP3_MX EQU 0x40005b46 + ENDIF + IF :LNOT::DEF:CYREG_OPAMP3_SW +CYREG_OPAMP3_SW EQU 0x40005b47 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_BASE +CYDEV_ANAIF_RT_LCDDAC_BASE EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_LCDDAC_SIZE +CYDEV_ANAIF_RT_LCDDAC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW0 +CYREG_LCDDAC_SW0 EQU 0x40005b50 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW1 +CYREG_LCDDAC_SW1 EQU 0x40005b51 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW2 +CYREG_LCDDAC_SW2 EQU 0x40005b52 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW3 +CYREG_LCDDAC_SW3 EQU 0x40005b53 + ENDIF + IF :LNOT::DEF:CYREG_LCDDAC_SW4 +CYREG_LCDDAC_SW4 EQU 0x40005b54 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_BASE +CYDEV_ANAIF_RT_SC_BASE EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_SC_SIZE +CYDEV_ANAIF_RT_SC_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_SC_MISC +CYREG_SC_MISC EQU 0x40005b56 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_BASE +CYDEV_ANAIF_RT_BUS_BASE EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_BUS_SIZE +CYDEV_ANAIF_RT_BUS_SIZE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW0 +CYREG_BUS_SW0 EQU 0x40005b58 + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW2 +CYREG_BUS_SW2 EQU 0x40005b5a + ENDIF + IF :LNOT::DEF:CYREG_BUS_SW3 +CYREG_BUS_SW3 EQU 0x40005b5b + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_BASE +CYDEV_ANAIF_RT_DFT_BASE EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_RT_DFT_SIZE +CYDEV_ANAIF_RT_DFT_SIZE EQU 0x00000006 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR0 +CYREG_DFT_CR0 EQU 0x40005b5c + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR1 +CYREG_DFT_CR1 EQU 0x40005b5d + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR2 +CYREG_DFT_CR2 EQU 0x40005b5e + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR3 +CYREG_DFT_CR3 EQU 0x40005b5f + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR4 +CYREG_DFT_CR4 EQU 0x40005b60 + ENDIF + IF :LNOT::DEF:CYREG_DFT_CR5 +CYREG_DFT_CR5 EQU 0x40005b61 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_BASE +CYDEV_ANAIF_WRK_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SIZE +CYDEV_ANAIF_WRK_SIZE EQU 0x00000029 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_BASE +CYDEV_ANAIF_WRK_DAC0_BASE EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC0_SIZE +CYDEV_ANAIF_WRK_DAC0_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC0_D +CYREG_DAC0_D EQU 0x40005b80 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_BASE +CYDEV_ANAIF_WRK_DAC1_BASE EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC1_SIZE +CYDEV_ANAIF_WRK_DAC1_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC1_D +CYREG_DAC1_D EQU 0x40005b81 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_BASE +CYDEV_ANAIF_WRK_DAC2_BASE EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC2_SIZE +CYDEV_ANAIF_WRK_DAC2_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC2_D +CYREG_DAC2_D EQU 0x40005b82 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_BASE +CYDEV_ANAIF_WRK_DAC3_BASE EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DAC3_SIZE +CYDEV_ANAIF_WRK_DAC3_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_DAC3_D +CYREG_DAC3_D EQU 0x40005b83 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_BASE +CYDEV_ANAIF_WRK_DSM0_BASE EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_DSM0_SIZE +CYDEV_ANAIF_WRK_DSM0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT0 +CYREG_DSM0_OUT0 EQU 0x40005b88 + ENDIF + IF :LNOT::DEF:CYREG_DSM0_OUT1 +CYREG_DSM0_OUT1 EQU 0x40005b89 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_BASE +CYDEV_ANAIF_WRK_LUT_BASE EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_LUT_SIZE +CYDEV_ANAIF_WRK_LUT_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_LUT_SR +CYREG_LUT_SR EQU 0x40005b90 + ENDIF + IF :LNOT::DEF:CYREG_LUT_WRK1 +CYREG_LUT_WRK1 EQU 0x40005b91 + ENDIF + IF :LNOT::DEF:CYREG_LUT_MSK +CYREG_LUT_MSK EQU 0x40005b92 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CLK +CYREG_LUT_CLK EQU 0x40005b93 + ENDIF + IF :LNOT::DEF:CYREG_LUT_CPTR +CYREG_LUT_CPTR EQU 0x40005b94 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_BASE +CYDEV_ANAIF_WRK_CMP_BASE EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_CMP_SIZE +CYDEV_ANAIF_WRK_CMP_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_CMP_WRK +CYREG_CMP_WRK EQU 0x40005b96 + ENDIF + IF :LNOT::DEF:CYREG_CMP_TST +CYREG_CMP_TST EQU 0x40005b97 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_BASE +CYDEV_ANAIF_WRK_SC_BASE EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SC_SIZE +CYDEV_ANAIF_WRK_SC_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_SC_SR +CYREG_SC_SR EQU 0x40005b98 + ENDIF + IF :LNOT::DEF:CYREG_SC_WRK1 +CYREG_SC_WRK1 EQU 0x40005b99 + ENDIF + IF :LNOT::DEF:CYREG_SC_MSK +CYREG_SC_MSK EQU 0x40005b9a + ENDIF + IF :LNOT::DEF:CYREG_SC_CMPINV +CYREG_SC_CMPINV EQU 0x40005b9b + ENDIF + IF :LNOT::DEF:CYREG_SC_CPTR +CYREG_SC_CPTR EQU 0x40005b9c + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_BASE +CYDEV_ANAIF_WRK_SAR0_BASE EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR0_SIZE +CYDEV_ANAIF_WRK_SAR0_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK0 +CYREG_SAR0_WRK0 EQU 0x40005ba0 + ENDIF + IF :LNOT::DEF:CYREG_SAR0_WRK1 +CYREG_SAR0_WRK1 EQU 0x40005ba1 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_BASE +CYDEV_ANAIF_WRK_SAR1_BASE EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SAR1_SIZE +CYDEV_ANAIF_WRK_SAR1_SIZE EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK0 +CYREG_SAR1_WRK0 EQU 0x40005ba2 + ENDIF + IF :LNOT::DEF:CYREG_SAR1_WRK1 +CYREG_SAR1_WRK1 EQU 0x40005ba3 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_BASE +CYDEV_ANAIF_WRK_SARS_BASE EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_ANAIF_WRK_SARS_SIZE +CYDEV_ANAIF_WRK_SARS_SIZE EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYREG_ANAIF_WRK_SARS_SOF +CYREG_ANAIF_WRK_SARS_SOF EQU 0x40005ba8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_BASE +CYDEV_USB_BASE EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIZE +CYDEV_USB_SIZE EQU 0x00000300 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR0 +CYREG_USB_EP0_DR0 EQU 0x40006000 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR1 +CYREG_USB_EP0_DR1 EQU 0x40006001 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR2 +CYREG_USB_EP0_DR2 EQU 0x40006002 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR3 +CYREG_USB_EP0_DR3 EQU 0x40006003 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR4 +CYREG_USB_EP0_DR4 EQU 0x40006004 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR5 +CYREG_USB_EP0_DR5 EQU 0x40006005 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR6 +CYREG_USB_EP0_DR6 EQU 0x40006006 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_DR7 +CYREG_USB_EP0_DR7 EQU 0x40006007 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR0 +CYREG_USB_CR0 EQU 0x40006008 + ENDIF + IF :LNOT::DEF:CYREG_USB_CR1 +CYREG_USB_CR1 EQU 0x40006009 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_EN +CYREG_USB_SIE_EP_INT_EN EQU 0x4000600a + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP_INT_SR +CYREG_USB_SIE_EP_INT_SR EQU 0x4000600b + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_BASE +CYDEV_USB_SIE_EP1_BASE EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP1_SIZE +CYDEV_USB_SIE_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT0 +CYREG_USB_SIE_EP1_CNT0 EQU 0x4000600c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CNT1 +CYREG_USB_SIE_EP1_CNT1 EQU 0x4000600d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP1_CR0 +CYREG_USB_SIE_EP1_CR0 EQU 0x4000600e + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR0 +CYREG_USB_USBIO_CR0 EQU 0x40006010 + ENDIF + IF :LNOT::DEF:CYREG_USB_USBIO_CR1 +CYREG_USB_USBIO_CR1 EQU 0x40006012 + ENDIF + IF :LNOT::DEF:CYREG_USB_DYN_RECONFIG +CYREG_USB_DYN_RECONFIG EQU 0x40006014 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF0 +CYREG_USB_SOF0 EQU 0x40006018 + ENDIF + IF :LNOT::DEF:CYREG_USB_SOF1 +CYREG_USB_SOF1 EQU 0x40006019 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_BASE +CYDEV_USB_SIE_EP2_BASE EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP2_SIZE +CYDEV_USB_SIE_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT0 +CYREG_USB_SIE_EP2_CNT0 EQU 0x4000601c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CNT1 +CYREG_USB_SIE_EP2_CNT1 EQU 0x4000601d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP2_CR0 +CYREG_USB_SIE_EP2_CR0 EQU 0x4000601e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CR +CYREG_USB_EP0_CR EQU 0x40006028 + ENDIF + IF :LNOT::DEF:CYREG_USB_EP0_CNT +CYREG_USB_EP0_CNT EQU 0x40006029 + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_BASE +CYDEV_USB_SIE_EP3_BASE EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP3_SIZE +CYDEV_USB_SIE_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT0 +CYREG_USB_SIE_EP3_CNT0 EQU 0x4000602c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CNT1 +CYREG_USB_SIE_EP3_CNT1 EQU 0x4000602d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP3_CR0 +CYREG_USB_SIE_EP3_CR0 EQU 0x4000602e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_BASE +CYDEV_USB_SIE_EP4_BASE EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP4_SIZE +CYDEV_USB_SIE_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT0 +CYREG_USB_SIE_EP4_CNT0 EQU 0x4000603c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CNT1 +CYREG_USB_SIE_EP4_CNT1 EQU 0x4000603d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP4_CR0 +CYREG_USB_SIE_EP4_CR0 EQU 0x4000603e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_BASE +CYDEV_USB_SIE_EP5_BASE EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP5_SIZE +CYDEV_USB_SIE_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT0 +CYREG_USB_SIE_EP5_CNT0 EQU 0x4000604c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CNT1 +CYREG_USB_SIE_EP5_CNT1 EQU 0x4000604d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP5_CR0 +CYREG_USB_SIE_EP5_CR0 EQU 0x4000604e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_BASE +CYDEV_USB_SIE_EP6_BASE EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP6_SIZE +CYDEV_USB_SIE_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT0 +CYREG_USB_SIE_EP6_CNT0 EQU 0x4000605c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CNT1 +CYREG_USB_SIE_EP6_CNT1 EQU 0x4000605d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP6_CR0 +CYREG_USB_SIE_EP6_CR0 EQU 0x4000605e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_BASE +CYDEV_USB_SIE_EP7_BASE EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP7_SIZE +CYDEV_USB_SIE_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT0 +CYREG_USB_SIE_EP7_CNT0 EQU 0x4000606c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CNT1 +CYREG_USB_SIE_EP7_CNT1 EQU 0x4000606d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP7_CR0 +CYREG_USB_SIE_EP7_CR0 EQU 0x4000606e + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_BASE +CYDEV_USB_SIE_EP8_BASE EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYDEV_USB_SIE_EP8_SIZE +CYDEV_USB_SIE_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT0 +CYREG_USB_SIE_EP8_CNT0 EQU 0x4000607c + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CNT1 +CYREG_USB_SIE_EP8_CNT1 EQU 0x4000607d + ENDIF + IF :LNOT::DEF:CYREG_USB_SIE_EP8_CR0 +CYREG_USB_SIE_EP8_CR0 EQU 0x4000607e + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_BASE +CYDEV_USB_ARB_EP1_BASE EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP1_SIZE +CYDEV_USB_ARB_EP1_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_CFG +CYREG_USB_ARB_EP1_CFG EQU 0x40006080 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_INT_EN +CYREG_USB_ARB_EP1_INT_EN EQU 0x40006081 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP1_SR +CYREG_USB_ARB_EP1_SR EQU 0x40006082 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_BASE +CYDEV_USB_ARB_RW1_BASE EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW1_SIZE +CYDEV_USB_ARB_RW1_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA +CYREG_USB_ARB_RW1_WA EQU 0x40006084 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_WA_MSB +CYREG_USB_ARB_RW1_WA_MSB EQU 0x40006085 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA +CYREG_USB_ARB_RW1_RA EQU 0x40006086 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_RA_MSB +CYREG_USB_ARB_RW1_RA_MSB EQU 0x40006087 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW1_DR +CYREG_USB_ARB_RW1_DR EQU 0x40006088 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUF_SIZE +CYREG_USB_BUF_SIZE EQU 0x4000608c + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_ACTIVE +CYREG_USB_EP_ACTIVE EQU 0x4000608e + ENDIF + IF :LNOT::DEF:CYREG_USB_EP_TYPE +CYREG_USB_EP_TYPE EQU 0x4000608f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_BASE +CYDEV_USB_ARB_EP2_BASE EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP2_SIZE +CYDEV_USB_ARB_EP2_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_CFG +CYREG_USB_ARB_EP2_CFG EQU 0x40006090 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_INT_EN +CYREG_USB_ARB_EP2_INT_EN EQU 0x40006091 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP2_SR +CYREG_USB_ARB_EP2_SR EQU 0x40006092 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_BASE +CYDEV_USB_ARB_RW2_BASE EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW2_SIZE +CYDEV_USB_ARB_RW2_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA +CYREG_USB_ARB_RW2_WA EQU 0x40006094 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_WA_MSB +CYREG_USB_ARB_RW2_WA_MSB EQU 0x40006095 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA +CYREG_USB_ARB_RW2_RA EQU 0x40006096 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_RA_MSB +CYREG_USB_ARB_RW2_RA_MSB EQU 0x40006097 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW2_DR +CYREG_USB_ARB_RW2_DR EQU 0x40006098 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_CFG +CYREG_USB_ARB_CFG EQU 0x4000609c + ENDIF + IF :LNOT::DEF:CYREG_USB_USB_CLK_EN +CYREG_USB_USB_CLK_EN EQU 0x4000609d + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_EN +CYREG_USB_ARB_INT_EN EQU 0x4000609e + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_INT_SR +CYREG_USB_ARB_INT_SR EQU 0x4000609f + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_BASE +CYDEV_USB_ARB_EP3_BASE EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP3_SIZE +CYDEV_USB_ARB_EP3_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_CFG +CYREG_USB_ARB_EP3_CFG EQU 0x400060a0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_INT_EN +CYREG_USB_ARB_EP3_INT_EN EQU 0x400060a1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP3_SR +CYREG_USB_ARB_EP3_SR EQU 0x400060a2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_BASE +CYDEV_USB_ARB_RW3_BASE EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW3_SIZE +CYDEV_USB_ARB_RW3_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA +CYREG_USB_ARB_RW3_WA EQU 0x400060a4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_WA_MSB +CYREG_USB_ARB_RW3_WA_MSB EQU 0x400060a5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA +CYREG_USB_ARB_RW3_RA EQU 0x400060a6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_RA_MSB +CYREG_USB_ARB_RW3_RA_MSB EQU 0x400060a7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW3_DR +CYREG_USB_ARB_RW3_DR EQU 0x400060a8 + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA +CYREG_USB_CWA EQU 0x400060ac + ENDIF + IF :LNOT::DEF:CYREG_USB_CWA_MSB +CYREG_USB_CWA_MSB EQU 0x400060ad + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_BASE +CYDEV_USB_ARB_EP4_BASE EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP4_SIZE +CYDEV_USB_ARB_EP4_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_CFG +CYREG_USB_ARB_EP4_CFG EQU 0x400060b0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_INT_EN +CYREG_USB_ARB_EP4_INT_EN EQU 0x400060b1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP4_SR +CYREG_USB_ARB_EP4_SR EQU 0x400060b2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_BASE +CYDEV_USB_ARB_RW4_BASE EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW4_SIZE +CYDEV_USB_ARB_RW4_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA +CYREG_USB_ARB_RW4_WA EQU 0x400060b4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_WA_MSB +CYREG_USB_ARB_RW4_WA_MSB EQU 0x400060b5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA +CYREG_USB_ARB_RW4_RA EQU 0x400060b6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_RA_MSB +CYREG_USB_ARB_RW4_RA_MSB EQU 0x400060b7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW4_DR +CYREG_USB_ARB_RW4_DR EQU 0x400060b8 + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES +CYREG_USB_DMA_THRES EQU 0x400060bc + ENDIF + IF :LNOT::DEF:CYREG_USB_DMA_THRES_MSB +CYREG_USB_DMA_THRES_MSB EQU 0x400060bd + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_BASE +CYDEV_USB_ARB_EP5_BASE EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP5_SIZE +CYDEV_USB_ARB_EP5_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_CFG +CYREG_USB_ARB_EP5_CFG EQU 0x400060c0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_INT_EN +CYREG_USB_ARB_EP5_INT_EN EQU 0x400060c1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP5_SR +CYREG_USB_ARB_EP5_SR EQU 0x400060c2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_BASE +CYDEV_USB_ARB_RW5_BASE EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW5_SIZE +CYDEV_USB_ARB_RW5_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA +CYREG_USB_ARB_RW5_WA EQU 0x400060c4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_WA_MSB +CYREG_USB_ARB_RW5_WA_MSB EQU 0x400060c5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA +CYREG_USB_ARB_RW5_RA EQU 0x400060c6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_RA_MSB +CYREG_USB_ARB_RW5_RA_MSB EQU 0x400060c7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW5_DR +CYREG_USB_ARB_RW5_DR EQU 0x400060c8 + ENDIF + IF :LNOT::DEF:CYREG_USB_BUS_RST_CNT +CYREG_USB_BUS_RST_CNT EQU 0x400060cc + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_BASE +CYDEV_USB_ARB_EP6_BASE EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP6_SIZE +CYDEV_USB_ARB_EP6_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_CFG +CYREG_USB_ARB_EP6_CFG EQU 0x400060d0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_INT_EN +CYREG_USB_ARB_EP6_INT_EN EQU 0x400060d1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP6_SR +CYREG_USB_ARB_EP6_SR EQU 0x400060d2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_BASE +CYDEV_USB_ARB_RW6_BASE EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW6_SIZE +CYDEV_USB_ARB_RW6_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA +CYREG_USB_ARB_RW6_WA EQU 0x400060d4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_WA_MSB +CYREG_USB_ARB_RW6_WA_MSB EQU 0x400060d5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA +CYREG_USB_ARB_RW6_RA EQU 0x400060d6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_RA_MSB +CYREG_USB_ARB_RW6_RA_MSB EQU 0x400060d7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW6_DR +CYREG_USB_ARB_RW6_DR EQU 0x400060d8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_BASE +CYDEV_USB_ARB_EP7_BASE EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP7_SIZE +CYDEV_USB_ARB_EP7_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_CFG +CYREG_USB_ARB_EP7_CFG EQU 0x400060e0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_INT_EN +CYREG_USB_ARB_EP7_INT_EN EQU 0x400060e1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP7_SR +CYREG_USB_ARB_EP7_SR EQU 0x400060e2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_BASE +CYDEV_USB_ARB_RW7_BASE EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW7_SIZE +CYDEV_USB_ARB_RW7_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA +CYREG_USB_ARB_RW7_WA EQU 0x400060e4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_WA_MSB +CYREG_USB_ARB_RW7_WA_MSB EQU 0x400060e5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA +CYREG_USB_ARB_RW7_RA EQU 0x400060e6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_RA_MSB +CYREG_USB_ARB_RW7_RA_MSB EQU 0x400060e7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW7_DR +CYREG_USB_ARB_RW7_DR EQU 0x400060e8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_BASE +CYDEV_USB_ARB_EP8_BASE EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_EP8_SIZE +CYDEV_USB_ARB_EP8_SIZE EQU 0x00000003 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_CFG +CYREG_USB_ARB_EP8_CFG EQU 0x400060f0 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_INT_EN +CYREG_USB_ARB_EP8_INT_EN EQU 0x400060f1 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_EP8_SR +CYREG_USB_ARB_EP8_SR EQU 0x400060f2 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_BASE +CYDEV_USB_ARB_RW8_BASE EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYDEV_USB_ARB_RW8_SIZE +CYDEV_USB_ARB_RW8_SIZE EQU 0x00000005 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA +CYREG_USB_ARB_RW8_WA EQU 0x400060f4 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_WA_MSB +CYREG_USB_ARB_RW8_WA_MSB EQU 0x400060f5 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA +CYREG_USB_ARB_RW8_RA EQU 0x400060f6 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_RA_MSB +CYREG_USB_ARB_RW8_RA_MSB EQU 0x400060f7 + ENDIF + IF :LNOT::DEF:CYREG_USB_ARB_RW8_DR +CYREG_USB_ARB_RW8_DR EQU 0x400060f8 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_BASE +CYDEV_USB_MEM_BASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYDEV_USB_MEM_SIZE +CYDEV_USB_MEM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MBASE +CYREG_USB_MEM_DATA_MBASE EQU 0x40006100 + ENDIF + IF :LNOT::DEF:CYREG_USB_MEM_DATA_MSIZE +CYREG_USB_MEM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_BASE +CYDEV_UWRK_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_SIZE +CYDEV_UWRK_SIZE EQU 0x00000b60 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_BASE +CYDEV_UWRK_UWRK8_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_SIZE +CYDEV_UWRK_UWRK8_SIZE EQU 0x000003b0 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_BASE +CYDEV_UWRK_UWRK8_B0_BASE EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B0_SIZE +CYDEV_UWRK_UWRK8_B0_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0 +CYREG_B0_UDB00_A0 EQU 0x40006400 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0 +CYREG_B0_UDB01_A0 EQU 0x40006401 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0 +CYREG_B0_UDB02_A0 EQU 0x40006402 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0 +CYREG_B0_UDB03_A0 EQU 0x40006403 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0 +CYREG_B0_UDB04_A0 EQU 0x40006404 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0 +CYREG_B0_UDB05_A0 EQU 0x40006405 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0 +CYREG_B0_UDB06_A0 EQU 0x40006406 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0 +CYREG_B0_UDB07_A0 EQU 0x40006407 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0 +CYREG_B0_UDB08_A0 EQU 0x40006408 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0 +CYREG_B0_UDB09_A0 EQU 0x40006409 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0 +CYREG_B0_UDB10_A0 EQU 0x4000640a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0 +CYREG_B0_UDB11_A0 EQU 0x4000640b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0 +CYREG_B0_UDB12_A0 EQU 0x4000640c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0 +CYREG_B0_UDB13_A0 EQU 0x4000640d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0 +CYREG_B0_UDB14_A0 EQU 0x4000640e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0 +CYREG_B0_UDB15_A0 EQU 0x4000640f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A1 +CYREG_B0_UDB00_A1 EQU 0x40006410 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A1 +CYREG_B0_UDB01_A1 EQU 0x40006411 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A1 +CYREG_B0_UDB02_A1 EQU 0x40006412 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A1 +CYREG_B0_UDB03_A1 EQU 0x40006413 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A1 +CYREG_B0_UDB04_A1 EQU 0x40006414 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A1 +CYREG_B0_UDB05_A1 EQU 0x40006415 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A1 +CYREG_B0_UDB06_A1 EQU 0x40006416 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A1 +CYREG_B0_UDB07_A1 EQU 0x40006417 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A1 +CYREG_B0_UDB08_A1 EQU 0x40006418 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A1 +CYREG_B0_UDB09_A1 EQU 0x40006419 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A1 +CYREG_B0_UDB10_A1 EQU 0x4000641a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A1 +CYREG_B0_UDB11_A1 EQU 0x4000641b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A1 +CYREG_B0_UDB12_A1 EQU 0x4000641c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A1 +CYREG_B0_UDB13_A1 EQU 0x4000641d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A1 +CYREG_B0_UDB14_A1 EQU 0x4000641e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A1 +CYREG_B0_UDB15_A1 EQU 0x4000641f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0 +CYREG_B0_UDB00_D0 EQU 0x40006420 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0 +CYREG_B0_UDB01_D0 EQU 0x40006421 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0 +CYREG_B0_UDB02_D0 EQU 0x40006422 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0 +CYREG_B0_UDB03_D0 EQU 0x40006423 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0 +CYREG_B0_UDB04_D0 EQU 0x40006424 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0 +CYREG_B0_UDB05_D0 EQU 0x40006425 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0 +CYREG_B0_UDB06_D0 EQU 0x40006426 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0 +CYREG_B0_UDB07_D0 EQU 0x40006427 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0 +CYREG_B0_UDB08_D0 EQU 0x40006428 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0 +CYREG_B0_UDB09_D0 EQU 0x40006429 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0 +CYREG_B0_UDB10_D0 EQU 0x4000642a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0 +CYREG_B0_UDB11_D0 EQU 0x4000642b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0 +CYREG_B0_UDB12_D0 EQU 0x4000642c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0 +CYREG_B0_UDB13_D0 EQU 0x4000642d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0 +CYREG_B0_UDB14_D0 EQU 0x4000642e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0 +CYREG_B0_UDB15_D0 EQU 0x4000642f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D1 +CYREG_B0_UDB00_D1 EQU 0x40006430 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D1 +CYREG_B0_UDB01_D1 EQU 0x40006431 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D1 +CYREG_B0_UDB02_D1 EQU 0x40006432 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D1 +CYREG_B0_UDB03_D1 EQU 0x40006433 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D1 +CYREG_B0_UDB04_D1 EQU 0x40006434 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D1 +CYREG_B0_UDB05_D1 EQU 0x40006435 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D1 +CYREG_B0_UDB06_D1 EQU 0x40006436 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D1 +CYREG_B0_UDB07_D1 EQU 0x40006437 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D1 +CYREG_B0_UDB08_D1 EQU 0x40006438 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D1 +CYREG_B0_UDB09_D1 EQU 0x40006439 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D1 +CYREG_B0_UDB10_D1 EQU 0x4000643a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D1 +CYREG_B0_UDB11_D1 EQU 0x4000643b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D1 +CYREG_B0_UDB12_D1 EQU 0x4000643c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D1 +CYREG_B0_UDB13_D1 EQU 0x4000643d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D1 +CYREG_B0_UDB14_D1 EQU 0x4000643e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D1 +CYREG_B0_UDB15_D1 EQU 0x4000643f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0 +CYREG_B0_UDB00_F0 EQU 0x40006440 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0 +CYREG_B0_UDB01_F0 EQU 0x40006441 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0 +CYREG_B0_UDB02_F0 EQU 0x40006442 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0 +CYREG_B0_UDB03_F0 EQU 0x40006443 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0 +CYREG_B0_UDB04_F0 EQU 0x40006444 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0 +CYREG_B0_UDB05_F0 EQU 0x40006445 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0 +CYREG_B0_UDB06_F0 EQU 0x40006446 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0 +CYREG_B0_UDB07_F0 EQU 0x40006447 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0 +CYREG_B0_UDB08_F0 EQU 0x40006448 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0 +CYREG_B0_UDB09_F0 EQU 0x40006449 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0 +CYREG_B0_UDB10_F0 EQU 0x4000644a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0 +CYREG_B0_UDB11_F0 EQU 0x4000644b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0 +CYREG_B0_UDB12_F0 EQU 0x4000644c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0 +CYREG_B0_UDB13_F0 EQU 0x4000644d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0 +CYREG_B0_UDB14_F0 EQU 0x4000644e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0 +CYREG_B0_UDB15_F0 EQU 0x4000644f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F1 +CYREG_B0_UDB00_F1 EQU 0x40006450 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F1 +CYREG_B0_UDB01_F1 EQU 0x40006451 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F1 +CYREG_B0_UDB02_F1 EQU 0x40006452 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F1 +CYREG_B0_UDB03_F1 EQU 0x40006453 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F1 +CYREG_B0_UDB04_F1 EQU 0x40006454 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F1 +CYREG_B0_UDB05_F1 EQU 0x40006455 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F1 +CYREG_B0_UDB06_F1 EQU 0x40006456 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F1 +CYREG_B0_UDB07_F1 EQU 0x40006457 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F1 +CYREG_B0_UDB08_F1 EQU 0x40006458 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F1 +CYREG_B0_UDB09_F1 EQU 0x40006459 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F1 +CYREG_B0_UDB10_F1 EQU 0x4000645a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F1 +CYREG_B0_UDB11_F1 EQU 0x4000645b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F1 +CYREG_B0_UDB12_F1 EQU 0x4000645c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F1 +CYREG_B0_UDB13_F1 EQU 0x4000645d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F1 +CYREG_B0_UDB14_F1 EQU 0x4000645e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F1 +CYREG_B0_UDB15_F1 EQU 0x4000645f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST +CYREG_B0_UDB00_ST EQU 0x40006460 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST +CYREG_B0_UDB01_ST EQU 0x40006461 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST +CYREG_B0_UDB02_ST EQU 0x40006462 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST +CYREG_B0_UDB03_ST EQU 0x40006463 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST +CYREG_B0_UDB04_ST EQU 0x40006464 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST +CYREG_B0_UDB05_ST EQU 0x40006465 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST +CYREG_B0_UDB06_ST EQU 0x40006466 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST +CYREG_B0_UDB07_ST EQU 0x40006467 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST +CYREG_B0_UDB08_ST EQU 0x40006468 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST +CYREG_B0_UDB09_ST EQU 0x40006469 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST +CYREG_B0_UDB10_ST EQU 0x4000646a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST +CYREG_B0_UDB11_ST EQU 0x4000646b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST +CYREG_B0_UDB12_ST EQU 0x4000646c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST +CYREG_B0_UDB13_ST EQU 0x4000646d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST +CYREG_B0_UDB14_ST EQU 0x4000646e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST +CYREG_B0_UDB15_ST EQU 0x4000646f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_CTL +CYREG_B0_UDB00_CTL EQU 0x40006470 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_CTL +CYREG_B0_UDB01_CTL EQU 0x40006471 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_CTL +CYREG_B0_UDB02_CTL EQU 0x40006472 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_CTL +CYREG_B0_UDB03_CTL EQU 0x40006473 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_CTL +CYREG_B0_UDB04_CTL EQU 0x40006474 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_CTL +CYREG_B0_UDB05_CTL EQU 0x40006475 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_CTL +CYREG_B0_UDB06_CTL EQU 0x40006476 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_CTL +CYREG_B0_UDB07_CTL EQU 0x40006477 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_CTL +CYREG_B0_UDB08_CTL EQU 0x40006478 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_CTL +CYREG_B0_UDB09_CTL EQU 0x40006479 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_CTL +CYREG_B0_UDB10_CTL EQU 0x4000647a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_CTL +CYREG_B0_UDB11_CTL EQU 0x4000647b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_CTL +CYREG_B0_UDB12_CTL EQU 0x4000647c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_CTL +CYREG_B0_UDB13_CTL EQU 0x4000647d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_CTL +CYREG_B0_UDB14_CTL EQU 0x4000647e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_CTL +CYREG_B0_UDB15_CTL EQU 0x4000647f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK +CYREG_B0_UDB00_MSK EQU 0x40006480 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK +CYREG_B0_UDB01_MSK EQU 0x40006481 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK +CYREG_B0_UDB02_MSK EQU 0x40006482 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK +CYREG_B0_UDB03_MSK EQU 0x40006483 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK +CYREG_B0_UDB04_MSK EQU 0x40006484 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK +CYREG_B0_UDB05_MSK EQU 0x40006485 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK +CYREG_B0_UDB06_MSK EQU 0x40006486 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK +CYREG_B0_UDB07_MSK EQU 0x40006487 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK +CYREG_B0_UDB08_MSK EQU 0x40006488 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK +CYREG_B0_UDB09_MSK EQU 0x40006489 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK +CYREG_B0_UDB10_MSK EQU 0x4000648a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK +CYREG_B0_UDB11_MSK EQU 0x4000648b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK +CYREG_B0_UDB12_MSK EQU 0x4000648c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK +CYREG_B0_UDB13_MSK EQU 0x4000648d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK +CYREG_B0_UDB14_MSK EQU 0x4000648e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK +CYREG_B0_UDB15_MSK EQU 0x4000648f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ACTL +CYREG_B0_UDB00_ACTL EQU 0x40006490 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ACTL +CYREG_B0_UDB01_ACTL EQU 0x40006491 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ACTL +CYREG_B0_UDB02_ACTL EQU 0x40006492 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ACTL +CYREG_B0_UDB03_ACTL EQU 0x40006493 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ACTL +CYREG_B0_UDB04_ACTL EQU 0x40006494 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ACTL +CYREG_B0_UDB05_ACTL EQU 0x40006495 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ACTL +CYREG_B0_UDB06_ACTL EQU 0x40006496 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ACTL +CYREG_B0_UDB07_ACTL EQU 0x40006497 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ACTL +CYREG_B0_UDB08_ACTL EQU 0x40006498 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ACTL +CYREG_B0_UDB09_ACTL EQU 0x40006499 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ACTL +CYREG_B0_UDB10_ACTL EQU 0x4000649a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ACTL +CYREG_B0_UDB11_ACTL EQU 0x4000649b + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ACTL +CYREG_B0_UDB12_ACTL EQU 0x4000649c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ACTL +CYREG_B0_UDB13_ACTL EQU 0x4000649d + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ACTL +CYREG_B0_UDB14_ACTL EQU 0x4000649e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ACTL +CYREG_B0_UDB15_ACTL EQU 0x4000649f + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC +CYREG_B0_UDB00_MC EQU 0x400064a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC +CYREG_B0_UDB01_MC EQU 0x400064a1 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC +CYREG_B0_UDB02_MC EQU 0x400064a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC +CYREG_B0_UDB03_MC EQU 0x400064a3 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC +CYREG_B0_UDB04_MC EQU 0x400064a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC +CYREG_B0_UDB05_MC EQU 0x400064a5 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC +CYREG_B0_UDB06_MC EQU 0x400064a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC +CYREG_B0_UDB07_MC EQU 0x400064a7 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC +CYREG_B0_UDB08_MC EQU 0x400064a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC +CYREG_B0_UDB09_MC EQU 0x400064a9 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC +CYREG_B0_UDB10_MC EQU 0x400064aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC +CYREG_B0_UDB11_MC EQU 0x400064ab + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC +CYREG_B0_UDB12_MC EQU 0x400064ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC +CYREG_B0_UDB13_MC EQU 0x400064ad + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC +CYREG_B0_UDB14_MC EQU 0x400064ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC +CYREG_B0_UDB15_MC EQU 0x400064af + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_BASE +CYDEV_UWRK_UWRK8_B1_BASE EQU 0x40006500 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK8_B1_SIZE +CYDEV_UWRK_UWRK8_B1_SIZE EQU 0x000000b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0 +CYREG_B1_UDB04_A0 EQU 0x40006504 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0 +CYREG_B1_UDB05_A0 EQU 0x40006505 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0 +CYREG_B1_UDB06_A0 EQU 0x40006506 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0 +CYREG_B1_UDB07_A0 EQU 0x40006507 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0 +CYREG_B1_UDB08_A0 EQU 0x40006508 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0 +CYREG_B1_UDB09_A0 EQU 0x40006509 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0 +CYREG_B1_UDB10_A0 EQU 0x4000650a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0 +CYREG_B1_UDB11_A0 EQU 0x4000650b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A1 +CYREG_B1_UDB04_A1 EQU 0x40006514 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A1 +CYREG_B1_UDB05_A1 EQU 0x40006515 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A1 +CYREG_B1_UDB06_A1 EQU 0x40006516 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A1 +CYREG_B1_UDB07_A1 EQU 0x40006517 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A1 +CYREG_B1_UDB08_A1 EQU 0x40006518 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A1 +CYREG_B1_UDB09_A1 EQU 0x40006519 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A1 +CYREG_B1_UDB10_A1 EQU 0x4000651a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A1 +CYREG_B1_UDB11_A1 EQU 0x4000651b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0 +CYREG_B1_UDB04_D0 EQU 0x40006524 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0 +CYREG_B1_UDB05_D0 EQU 0x40006525 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0 +CYREG_B1_UDB06_D0 EQU 0x40006526 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0 +CYREG_B1_UDB07_D0 EQU 0x40006527 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0 +CYREG_B1_UDB08_D0 EQU 0x40006528 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0 +CYREG_B1_UDB09_D0 EQU 0x40006529 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0 +CYREG_B1_UDB10_D0 EQU 0x4000652a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0 +CYREG_B1_UDB11_D0 EQU 0x4000652b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D1 +CYREG_B1_UDB04_D1 EQU 0x40006534 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D1 +CYREG_B1_UDB05_D1 EQU 0x40006535 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D1 +CYREG_B1_UDB06_D1 EQU 0x40006536 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D1 +CYREG_B1_UDB07_D1 EQU 0x40006537 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D1 +CYREG_B1_UDB08_D1 EQU 0x40006538 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D1 +CYREG_B1_UDB09_D1 EQU 0x40006539 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D1 +CYREG_B1_UDB10_D1 EQU 0x4000653a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D1 +CYREG_B1_UDB11_D1 EQU 0x4000653b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0 +CYREG_B1_UDB04_F0 EQU 0x40006544 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0 +CYREG_B1_UDB05_F0 EQU 0x40006545 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0 +CYREG_B1_UDB06_F0 EQU 0x40006546 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0 +CYREG_B1_UDB07_F0 EQU 0x40006547 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0 +CYREG_B1_UDB08_F0 EQU 0x40006548 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0 +CYREG_B1_UDB09_F0 EQU 0x40006549 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0 +CYREG_B1_UDB10_F0 EQU 0x4000654a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0 +CYREG_B1_UDB11_F0 EQU 0x4000654b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F1 +CYREG_B1_UDB04_F1 EQU 0x40006554 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F1 +CYREG_B1_UDB05_F1 EQU 0x40006555 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F1 +CYREG_B1_UDB06_F1 EQU 0x40006556 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F1 +CYREG_B1_UDB07_F1 EQU 0x40006557 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F1 +CYREG_B1_UDB08_F1 EQU 0x40006558 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F1 +CYREG_B1_UDB09_F1 EQU 0x40006559 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F1 +CYREG_B1_UDB10_F1 EQU 0x4000655a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F1 +CYREG_B1_UDB11_F1 EQU 0x4000655b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST +CYREG_B1_UDB04_ST EQU 0x40006564 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST +CYREG_B1_UDB05_ST EQU 0x40006565 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST +CYREG_B1_UDB06_ST EQU 0x40006566 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST +CYREG_B1_UDB07_ST EQU 0x40006567 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST +CYREG_B1_UDB08_ST EQU 0x40006568 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST +CYREG_B1_UDB09_ST EQU 0x40006569 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST +CYREG_B1_UDB10_ST EQU 0x4000656a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST +CYREG_B1_UDB11_ST EQU 0x4000656b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_CTL +CYREG_B1_UDB04_CTL EQU 0x40006574 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_CTL +CYREG_B1_UDB05_CTL EQU 0x40006575 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_CTL +CYREG_B1_UDB06_CTL EQU 0x40006576 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_CTL +CYREG_B1_UDB07_CTL EQU 0x40006577 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_CTL +CYREG_B1_UDB08_CTL EQU 0x40006578 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_CTL +CYREG_B1_UDB09_CTL EQU 0x40006579 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_CTL +CYREG_B1_UDB10_CTL EQU 0x4000657a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_CTL +CYREG_B1_UDB11_CTL EQU 0x4000657b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK +CYREG_B1_UDB04_MSK EQU 0x40006584 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK +CYREG_B1_UDB05_MSK EQU 0x40006585 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK +CYREG_B1_UDB06_MSK EQU 0x40006586 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK +CYREG_B1_UDB07_MSK EQU 0x40006587 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK +CYREG_B1_UDB08_MSK EQU 0x40006588 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK +CYREG_B1_UDB09_MSK EQU 0x40006589 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK +CYREG_B1_UDB10_MSK EQU 0x4000658a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK +CYREG_B1_UDB11_MSK EQU 0x4000658b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ACTL +CYREG_B1_UDB04_ACTL EQU 0x40006594 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ACTL +CYREG_B1_UDB05_ACTL EQU 0x40006595 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ACTL +CYREG_B1_UDB06_ACTL EQU 0x40006596 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ACTL +CYREG_B1_UDB07_ACTL EQU 0x40006597 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ACTL +CYREG_B1_UDB08_ACTL EQU 0x40006598 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ACTL +CYREG_B1_UDB09_ACTL EQU 0x40006599 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ACTL +CYREG_B1_UDB10_ACTL EQU 0x4000659a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ACTL +CYREG_B1_UDB11_ACTL EQU 0x4000659b + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC +CYREG_B1_UDB04_MC EQU 0x400065a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC +CYREG_B1_UDB05_MC EQU 0x400065a5 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC +CYREG_B1_UDB06_MC EQU 0x400065a6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC +CYREG_B1_UDB07_MC EQU 0x400065a7 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC +CYREG_B1_UDB08_MC EQU 0x400065a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC +CYREG_B1_UDB09_MC EQU 0x400065a9 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC +CYREG_B1_UDB10_MC EQU 0x400065aa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC +CYREG_B1_UDB11_MC EQU 0x400065ab + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_BASE +CYDEV_UWRK_UWRK16_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_SIZE +CYDEV_UWRK_UWRK16_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_BASE +CYDEV_UWRK_UWRK16_CAT_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_SIZE +CYDEV_UWRK_UWRK16_CAT_SIZE EQU 0x00000760 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_BASE +CYDEV_UWRK_UWRK16_CAT_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B0_SIZE +CYDEV_UWRK_UWRK16_CAT_B0_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_A0_A1 +CYREG_B0_UDB00_A0_A1 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_A0_A1 +CYREG_B0_UDB01_A0_A1 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_A0_A1 +CYREG_B0_UDB02_A0_A1 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_A0_A1 +CYREG_B0_UDB03_A0_A1 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_A0_A1 +CYREG_B0_UDB04_A0_A1 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_A0_A1 +CYREG_B0_UDB05_A0_A1 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_A0_A1 +CYREG_B0_UDB06_A0_A1 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_A0_A1 +CYREG_B0_UDB07_A0_A1 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_A0_A1 +CYREG_B0_UDB08_A0_A1 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_A0_A1 +CYREG_B0_UDB09_A0_A1 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_A0_A1 +CYREG_B0_UDB10_A0_A1 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_A0_A1 +CYREG_B0_UDB11_A0_A1 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_A0_A1 +CYREG_B0_UDB12_A0_A1 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_A0_A1 +CYREG_B0_UDB13_A0_A1 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_A0_A1 +CYREG_B0_UDB14_A0_A1 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_A0_A1 +CYREG_B0_UDB15_A0_A1 EQU 0x4000681e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_D0_D1 +CYREG_B0_UDB00_D0_D1 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_D0_D1 +CYREG_B0_UDB01_D0_D1 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_D0_D1 +CYREG_B0_UDB02_D0_D1 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_D0_D1 +CYREG_B0_UDB03_D0_D1 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_D0_D1 +CYREG_B0_UDB04_D0_D1 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_D0_D1 +CYREG_B0_UDB05_D0_D1 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_D0_D1 +CYREG_B0_UDB06_D0_D1 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_D0_D1 +CYREG_B0_UDB07_D0_D1 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_D0_D1 +CYREG_B0_UDB08_D0_D1 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_D0_D1 +CYREG_B0_UDB09_D0_D1 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_D0_D1 +CYREG_B0_UDB10_D0_D1 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_D0_D1 +CYREG_B0_UDB11_D0_D1 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_D0_D1 +CYREG_B0_UDB12_D0_D1 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_D0_D1 +CYREG_B0_UDB13_D0_D1 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_D0_D1 +CYREG_B0_UDB14_D0_D1 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_D0_D1 +CYREG_B0_UDB15_D0_D1 EQU 0x4000685e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_F0_F1 +CYREG_B0_UDB00_F0_F1 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_F0_F1 +CYREG_B0_UDB01_F0_F1 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_F0_F1 +CYREG_B0_UDB02_F0_F1 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_F0_F1 +CYREG_B0_UDB03_F0_F1 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_F0_F1 +CYREG_B0_UDB04_F0_F1 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_F0_F1 +CYREG_B0_UDB05_F0_F1 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_F0_F1 +CYREG_B0_UDB06_F0_F1 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_F0_F1 +CYREG_B0_UDB07_F0_F1 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_F0_F1 +CYREG_B0_UDB08_F0_F1 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_F0_F1 +CYREG_B0_UDB09_F0_F1 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_F0_F1 +CYREG_B0_UDB10_F0_F1 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_F0_F1 +CYREG_B0_UDB11_F0_F1 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_F0_F1 +CYREG_B0_UDB12_F0_F1 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_F0_F1 +CYREG_B0_UDB13_F0_F1 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_F0_F1 +CYREG_B0_UDB14_F0_F1 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_F0_F1 +CYREG_B0_UDB15_F0_F1 EQU 0x4000689e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_ST_CTL +CYREG_B0_UDB00_ST_CTL EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_ST_CTL +CYREG_B0_UDB01_ST_CTL EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_ST_CTL +CYREG_B0_UDB02_ST_CTL EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_ST_CTL +CYREG_B0_UDB03_ST_CTL EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_ST_CTL +CYREG_B0_UDB04_ST_CTL EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_ST_CTL +CYREG_B0_UDB05_ST_CTL EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_ST_CTL +CYREG_B0_UDB06_ST_CTL EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_ST_CTL +CYREG_B0_UDB07_ST_CTL EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_ST_CTL +CYREG_B0_UDB08_ST_CTL EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_ST_CTL +CYREG_B0_UDB09_ST_CTL EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_ST_CTL +CYREG_B0_UDB10_ST_CTL EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_ST_CTL +CYREG_B0_UDB11_ST_CTL EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_ST_CTL +CYREG_B0_UDB12_ST_CTL EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_ST_CTL +CYREG_B0_UDB13_ST_CTL EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_ST_CTL +CYREG_B0_UDB14_ST_CTL EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_ST_CTL +CYREG_B0_UDB15_ST_CTL EQU 0x400068de + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MSK_ACTL +CYREG_B0_UDB00_MSK_ACTL EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MSK_ACTL +CYREG_B0_UDB01_MSK_ACTL EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MSK_ACTL +CYREG_B0_UDB02_MSK_ACTL EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MSK_ACTL +CYREG_B0_UDB03_MSK_ACTL EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MSK_ACTL +CYREG_B0_UDB04_MSK_ACTL EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MSK_ACTL +CYREG_B0_UDB05_MSK_ACTL EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MSK_ACTL +CYREG_B0_UDB06_MSK_ACTL EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MSK_ACTL +CYREG_B0_UDB07_MSK_ACTL EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MSK_ACTL +CYREG_B0_UDB08_MSK_ACTL EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MSK_ACTL +CYREG_B0_UDB09_MSK_ACTL EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MSK_ACTL +CYREG_B0_UDB10_MSK_ACTL EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MSK_ACTL +CYREG_B0_UDB11_MSK_ACTL EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MSK_ACTL +CYREG_B0_UDB12_MSK_ACTL EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MSK_ACTL +CYREG_B0_UDB13_MSK_ACTL EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MSK_ACTL +CYREG_B0_UDB14_MSK_ACTL EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MSK_ACTL +CYREG_B0_UDB15_MSK_ACTL EQU 0x4000691e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_MC_00 +CYREG_B0_UDB00_MC_00 EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_MC_00 +CYREG_B0_UDB01_MC_00 EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_MC_00 +CYREG_B0_UDB02_MC_00 EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_MC_00 +CYREG_B0_UDB03_MC_00 EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_MC_00 +CYREG_B0_UDB04_MC_00 EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_MC_00 +CYREG_B0_UDB05_MC_00 EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_MC_00 +CYREG_B0_UDB06_MC_00 EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_MC_00 +CYREG_B0_UDB07_MC_00 EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_MC_00 +CYREG_B0_UDB08_MC_00 EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_MC_00 +CYREG_B0_UDB09_MC_00 EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_MC_00 +CYREG_B0_UDB10_MC_00 EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_MC_00 +CYREG_B0_UDB11_MC_00 EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_MC_00 +CYREG_B0_UDB12_MC_00 EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_MC_00 +CYREG_B0_UDB13_MC_00 EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_MC_00 +CYREG_B0_UDB14_MC_00 EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB15_MC_00 +CYREG_B0_UDB15_MC_00 EQU 0x4000695e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_BASE +CYDEV_UWRK_UWRK16_CAT_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_CAT_B1_SIZE +CYDEV_UWRK_UWRK16_CAT_B1_SIZE EQU 0x00000160 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_A0_A1 +CYREG_B1_UDB04_A0_A1 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_A0_A1 +CYREG_B1_UDB05_A0_A1 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_A0_A1 +CYREG_B1_UDB06_A0_A1 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_A0_A1 +CYREG_B1_UDB07_A0_A1 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_A0_A1 +CYREG_B1_UDB08_A0_A1 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_A0_A1 +CYREG_B1_UDB09_A0_A1 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_A0_A1 +CYREG_B1_UDB10_A0_A1 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_A0_A1 +CYREG_B1_UDB11_A0_A1 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_D0_D1 +CYREG_B1_UDB04_D0_D1 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_D0_D1 +CYREG_B1_UDB05_D0_D1 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_D0_D1 +CYREG_B1_UDB06_D0_D1 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_D0_D1 +CYREG_B1_UDB07_D0_D1 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_D0_D1 +CYREG_B1_UDB08_D0_D1 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_D0_D1 +CYREG_B1_UDB09_D0_D1 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_D0_D1 +CYREG_B1_UDB10_D0_D1 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_D0_D1 +CYREG_B1_UDB11_D0_D1 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_F0_F1 +CYREG_B1_UDB04_F0_F1 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_F0_F1 +CYREG_B1_UDB05_F0_F1 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_F0_F1 +CYREG_B1_UDB06_F0_F1 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_F0_F1 +CYREG_B1_UDB07_F0_F1 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_F0_F1 +CYREG_B1_UDB08_F0_F1 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_F0_F1 +CYREG_B1_UDB09_F0_F1 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_F0_F1 +CYREG_B1_UDB10_F0_F1 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_F0_F1 +CYREG_B1_UDB11_F0_F1 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_ST_CTL +CYREG_B1_UDB04_ST_CTL EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_ST_CTL +CYREG_B1_UDB05_ST_CTL EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_ST_CTL +CYREG_B1_UDB06_ST_CTL EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_ST_CTL +CYREG_B1_UDB07_ST_CTL EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_ST_CTL +CYREG_B1_UDB08_ST_CTL EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_ST_CTL +CYREG_B1_UDB09_ST_CTL EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_ST_CTL +CYREG_B1_UDB10_ST_CTL EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_ST_CTL +CYREG_B1_UDB11_ST_CTL EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MSK_ACTL +CYREG_B1_UDB04_MSK_ACTL EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MSK_ACTL +CYREG_B1_UDB05_MSK_ACTL EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MSK_ACTL +CYREG_B1_UDB06_MSK_ACTL EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MSK_ACTL +CYREG_B1_UDB07_MSK_ACTL EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MSK_ACTL +CYREG_B1_UDB08_MSK_ACTL EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MSK_ACTL +CYREG_B1_UDB09_MSK_ACTL EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MSK_ACTL +CYREG_B1_UDB10_MSK_ACTL EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MSK_ACTL +CYREG_B1_UDB11_MSK_ACTL EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_MC_00 +CYREG_B1_UDB04_MC_00 EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_MC_00 +CYREG_B1_UDB05_MC_00 EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_MC_00 +CYREG_B1_UDB06_MC_00 EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_MC_00 +CYREG_B1_UDB07_MC_00 EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_MC_00 +CYREG_B1_UDB08_MC_00 EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_MC_00 +CYREG_B1_UDB09_MC_00 EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_MC_00 +CYREG_B1_UDB10_MC_00 EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_MC_00 +CYREG_B1_UDB11_MC_00 EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_BASE +CYDEV_UWRK_UWRK16_DEF_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_SIZE +CYDEV_UWRK_UWRK16_DEF_SIZE EQU 0x0000075e + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_BASE +CYDEV_UWRK_UWRK16_DEF_B0_BASE EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B0_SIZE +CYDEV_UWRK_UWRK16_DEF_B0_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A0 +CYREG_B0_UDB00_01_A0 EQU 0x40006800 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A0 +CYREG_B0_UDB01_02_A0 EQU 0x40006802 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A0 +CYREG_B0_UDB02_03_A0 EQU 0x40006804 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A0 +CYREG_B0_UDB03_04_A0 EQU 0x40006806 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A0 +CYREG_B0_UDB04_05_A0 EQU 0x40006808 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A0 +CYREG_B0_UDB05_06_A0 EQU 0x4000680a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A0 +CYREG_B0_UDB06_07_A0 EQU 0x4000680c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A0 +CYREG_B0_UDB07_08_A0 EQU 0x4000680e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A0 +CYREG_B0_UDB08_09_A0 EQU 0x40006810 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A0 +CYREG_B0_UDB09_10_A0 EQU 0x40006812 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A0 +CYREG_B0_UDB10_11_A0 EQU 0x40006814 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A0 +CYREG_B0_UDB11_12_A0 EQU 0x40006816 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A0 +CYREG_B0_UDB12_13_A0 EQU 0x40006818 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A0 +CYREG_B0_UDB13_14_A0 EQU 0x4000681a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A0 +CYREG_B0_UDB14_15_A0 EQU 0x4000681c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_A1 +CYREG_B0_UDB00_01_A1 EQU 0x40006820 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_A1 +CYREG_B0_UDB01_02_A1 EQU 0x40006822 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_A1 +CYREG_B0_UDB02_03_A1 EQU 0x40006824 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_A1 +CYREG_B0_UDB03_04_A1 EQU 0x40006826 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_A1 +CYREG_B0_UDB04_05_A1 EQU 0x40006828 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_A1 +CYREG_B0_UDB05_06_A1 EQU 0x4000682a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_A1 +CYREG_B0_UDB06_07_A1 EQU 0x4000682c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_A1 +CYREG_B0_UDB07_08_A1 EQU 0x4000682e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_A1 +CYREG_B0_UDB08_09_A1 EQU 0x40006830 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_A1 +CYREG_B0_UDB09_10_A1 EQU 0x40006832 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_A1 +CYREG_B0_UDB10_11_A1 EQU 0x40006834 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_A1 +CYREG_B0_UDB11_12_A1 EQU 0x40006836 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_A1 +CYREG_B0_UDB12_13_A1 EQU 0x40006838 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_A1 +CYREG_B0_UDB13_14_A1 EQU 0x4000683a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_A1 +CYREG_B0_UDB14_15_A1 EQU 0x4000683c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D0 +CYREG_B0_UDB00_01_D0 EQU 0x40006840 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D0 +CYREG_B0_UDB01_02_D0 EQU 0x40006842 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D0 +CYREG_B0_UDB02_03_D0 EQU 0x40006844 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D0 +CYREG_B0_UDB03_04_D0 EQU 0x40006846 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D0 +CYREG_B0_UDB04_05_D0 EQU 0x40006848 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D0 +CYREG_B0_UDB05_06_D0 EQU 0x4000684a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D0 +CYREG_B0_UDB06_07_D0 EQU 0x4000684c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D0 +CYREG_B0_UDB07_08_D0 EQU 0x4000684e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D0 +CYREG_B0_UDB08_09_D0 EQU 0x40006850 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D0 +CYREG_B0_UDB09_10_D0 EQU 0x40006852 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D0 +CYREG_B0_UDB10_11_D0 EQU 0x40006854 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D0 +CYREG_B0_UDB11_12_D0 EQU 0x40006856 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D0 +CYREG_B0_UDB12_13_D0 EQU 0x40006858 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D0 +CYREG_B0_UDB13_14_D0 EQU 0x4000685a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D0 +CYREG_B0_UDB14_15_D0 EQU 0x4000685c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_D1 +CYREG_B0_UDB00_01_D1 EQU 0x40006860 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_D1 +CYREG_B0_UDB01_02_D1 EQU 0x40006862 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_D1 +CYREG_B0_UDB02_03_D1 EQU 0x40006864 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_D1 +CYREG_B0_UDB03_04_D1 EQU 0x40006866 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_D1 +CYREG_B0_UDB04_05_D1 EQU 0x40006868 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_D1 +CYREG_B0_UDB05_06_D1 EQU 0x4000686a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_D1 +CYREG_B0_UDB06_07_D1 EQU 0x4000686c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_D1 +CYREG_B0_UDB07_08_D1 EQU 0x4000686e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_D1 +CYREG_B0_UDB08_09_D1 EQU 0x40006870 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_D1 +CYREG_B0_UDB09_10_D1 EQU 0x40006872 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_D1 +CYREG_B0_UDB10_11_D1 EQU 0x40006874 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_D1 +CYREG_B0_UDB11_12_D1 EQU 0x40006876 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_D1 +CYREG_B0_UDB12_13_D1 EQU 0x40006878 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_D1 +CYREG_B0_UDB13_14_D1 EQU 0x4000687a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_D1 +CYREG_B0_UDB14_15_D1 EQU 0x4000687c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F0 +CYREG_B0_UDB00_01_F0 EQU 0x40006880 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F0 +CYREG_B0_UDB01_02_F0 EQU 0x40006882 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F0 +CYREG_B0_UDB02_03_F0 EQU 0x40006884 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F0 +CYREG_B0_UDB03_04_F0 EQU 0x40006886 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F0 +CYREG_B0_UDB04_05_F0 EQU 0x40006888 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F0 +CYREG_B0_UDB05_06_F0 EQU 0x4000688a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F0 +CYREG_B0_UDB06_07_F0 EQU 0x4000688c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F0 +CYREG_B0_UDB07_08_F0 EQU 0x4000688e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F0 +CYREG_B0_UDB08_09_F0 EQU 0x40006890 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F0 +CYREG_B0_UDB09_10_F0 EQU 0x40006892 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F0 +CYREG_B0_UDB10_11_F0 EQU 0x40006894 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F0 +CYREG_B0_UDB11_12_F0 EQU 0x40006896 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F0 +CYREG_B0_UDB12_13_F0 EQU 0x40006898 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F0 +CYREG_B0_UDB13_14_F0 EQU 0x4000689a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F0 +CYREG_B0_UDB14_15_F0 EQU 0x4000689c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_F1 +CYREG_B0_UDB00_01_F1 EQU 0x400068a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_F1 +CYREG_B0_UDB01_02_F1 EQU 0x400068a2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_F1 +CYREG_B0_UDB02_03_F1 EQU 0x400068a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_F1 +CYREG_B0_UDB03_04_F1 EQU 0x400068a6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_F1 +CYREG_B0_UDB04_05_F1 EQU 0x400068a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_F1 +CYREG_B0_UDB05_06_F1 EQU 0x400068aa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_F1 +CYREG_B0_UDB06_07_F1 EQU 0x400068ac + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_F1 +CYREG_B0_UDB07_08_F1 EQU 0x400068ae + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_F1 +CYREG_B0_UDB08_09_F1 EQU 0x400068b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_F1 +CYREG_B0_UDB09_10_F1 EQU 0x400068b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_F1 +CYREG_B0_UDB10_11_F1 EQU 0x400068b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_F1 +CYREG_B0_UDB11_12_F1 EQU 0x400068b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_F1 +CYREG_B0_UDB12_13_F1 EQU 0x400068b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_F1 +CYREG_B0_UDB13_14_F1 EQU 0x400068ba + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_F1 +CYREG_B0_UDB14_15_F1 EQU 0x400068bc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ST +CYREG_B0_UDB00_01_ST EQU 0x400068c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ST +CYREG_B0_UDB01_02_ST EQU 0x400068c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ST +CYREG_B0_UDB02_03_ST EQU 0x400068c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ST +CYREG_B0_UDB03_04_ST EQU 0x400068c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ST +CYREG_B0_UDB04_05_ST EQU 0x400068c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ST +CYREG_B0_UDB05_06_ST EQU 0x400068ca + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ST +CYREG_B0_UDB06_07_ST EQU 0x400068cc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ST +CYREG_B0_UDB07_08_ST EQU 0x400068ce + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ST +CYREG_B0_UDB08_09_ST EQU 0x400068d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ST +CYREG_B0_UDB09_10_ST EQU 0x400068d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ST +CYREG_B0_UDB10_11_ST EQU 0x400068d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ST +CYREG_B0_UDB11_12_ST EQU 0x400068d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ST +CYREG_B0_UDB12_13_ST EQU 0x400068d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ST +CYREG_B0_UDB13_14_ST EQU 0x400068da + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ST +CYREG_B0_UDB14_15_ST EQU 0x400068dc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_CTL +CYREG_B0_UDB00_01_CTL EQU 0x400068e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_CTL +CYREG_B0_UDB01_02_CTL EQU 0x400068e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_CTL +CYREG_B0_UDB02_03_CTL EQU 0x400068e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_CTL +CYREG_B0_UDB03_04_CTL EQU 0x400068e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_CTL +CYREG_B0_UDB04_05_CTL EQU 0x400068e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_CTL +CYREG_B0_UDB05_06_CTL EQU 0x400068ea + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_CTL +CYREG_B0_UDB06_07_CTL EQU 0x400068ec + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_CTL +CYREG_B0_UDB07_08_CTL EQU 0x400068ee + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_CTL +CYREG_B0_UDB08_09_CTL EQU 0x400068f0 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_CTL +CYREG_B0_UDB09_10_CTL EQU 0x400068f2 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_CTL +CYREG_B0_UDB10_11_CTL EQU 0x400068f4 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_CTL +CYREG_B0_UDB11_12_CTL EQU 0x400068f6 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_CTL +CYREG_B0_UDB12_13_CTL EQU 0x400068f8 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_CTL +CYREG_B0_UDB13_14_CTL EQU 0x400068fa + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_CTL +CYREG_B0_UDB14_15_CTL EQU 0x400068fc + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MSK +CYREG_B0_UDB00_01_MSK EQU 0x40006900 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MSK +CYREG_B0_UDB01_02_MSK EQU 0x40006902 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MSK +CYREG_B0_UDB02_03_MSK EQU 0x40006904 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MSK +CYREG_B0_UDB03_04_MSK EQU 0x40006906 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MSK +CYREG_B0_UDB04_05_MSK EQU 0x40006908 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MSK +CYREG_B0_UDB05_06_MSK EQU 0x4000690a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MSK +CYREG_B0_UDB06_07_MSK EQU 0x4000690c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MSK +CYREG_B0_UDB07_08_MSK EQU 0x4000690e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MSK +CYREG_B0_UDB08_09_MSK EQU 0x40006910 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MSK +CYREG_B0_UDB09_10_MSK EQU 0x40006912 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MSK +CYREG_B0_UDB10_11_MSK EQU 0x40006914 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MSK +CYREG_B0_UDB11_12_MSK EQU 0x40006916 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MSK +CYREG_B0_UDB12_13_MSK EQU 0x40006918 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MSK +CYREG_B0_UDB13_14_MSK EQU 0x4000691a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MSK +CYREG_B0_UDB14_15_MSK EQU 0x4000691c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_ACTL +CYREG_B0_UDB00_01_ACTL EQU 0x40006920 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_ACTL +CYREG_B0_UDB01_02_ACTL EQU 0x40006922 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_ACTL +CYREG_B0_UDB02_03_ACTL EQU 0x40006924 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_ACTL +CYREG_B0_UDB03_04_ACTL EQU 0x40006926 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_ACTL +CYREG_B0_UDB04_05_ACTL EQU 0x40006928 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_ACTL +CYREG_B0_UDB05_06_ACTL EQU 0x4000692a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_ACTL +CYREG_B0_UDB06_07_ACTL EQU 0x4000692c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_ACTL +CYREG_B0_UDB07_08_ACTL EQU 0x4000692e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_ACTL +CYREG_B0_UDB08_09_ACTL EQU 0x40006930 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_ACTL +CYREG_B0_UDB09_10_ACTL EQU 0x40006932 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_ACTL +CYREG_B0_UDB10_11_ACTL EQU 0x40006934 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_ACTL +CYREG_B0_UDB11_12_ACTL EQU 0x40006936 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_ACTL +CYREG_B0_UDB12_13_ACTL EQU 0x40006938 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_ACTL +CYREG_B0_UDB13_14_ACTL EQU 0x4000693a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_ACTL +CYREG_B0_UDB14_15_ACTL EQU 0x4000693c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB00_01_MC +CYREG_B0_UDB00_01_MC EQU 0x40006940 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB01_02_MC +CYREG_B0_UDB01_02_MC EQU 0x40006942 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB02_03_MC +CYREG_B0_UDB02_03_MC EQU 0x40006944 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB03_04_MC +CYREG_B0_UDB03_04_MC EQU 0x40006946 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB04_05_MC +CYREG_B0_UDB04_05_MC EQU 0x40006948 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB05_06_MC +CYREG_B0_UDB05_06_MC EQU 0x4000694a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB06_07_MC +CYREG_B0_UDB06_07_MC EQU 0x4000694c + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB07_08_MC +CYREG_B0_UDB07_08_MC EQU 0x4000694e + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB08_09_MC +CYREG_B0_UDB08_09_MC EQU 0x40006950 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB09_10_MC +CYREG_B0_UDB09_10_MC EQU 0x40006952 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB10_11_MC +CYREG_B0_UDB10_11_MC EQU 0x40006954 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB11_12_MC +CYREG_B0_UDB11_12_MC EQU 0x40006956 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB12_13_MC +CYREG_B0_UDB12_13_MC EQU 0x40006958 + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB13_14_MC +CYREG_B0_UDB13_14_MC EQU 0x4000695a + ENDIF + IF :LNOT::DEF:CYREG_B0_UDB14_15_MC +CYREG_B0_UDB14_15_MC EQU 0x4000695c + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_BASE +CYDEV_UWRK_UWRK16_DEF_B1_BASE EQU 0x40006a00 + ENDIF + IF :LNOT::DEF:CYDEV_UWRK_UWRK16_DEF_B1_SIZE +CYDEV_UWRK_UWRK16_DEF_B1_SIZE EQU 0x0000015e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A0 +CYREG_B1_UDB04_05_A0 EQU 0x40006a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A0 +CYREG_B1_UDB05_06_A0 EQU 0x40006a0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A0 +CYREG_B1_UDB06_07_A0 EQU 0x40006a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A0 +CYREG_B1_UDB07_08_A0 EQU 0x40006a0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A0 +CYREG_B1_UDB08_09_A0 EQU 0x40006a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A0 +CYREG_B1_UDB09_10_A0 EQU 0x40006a12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A0 +CYREG_B1_UDB10_11_A0 EQU 0x40006a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A0 +CYREG_B1_UDB11_12_A0 EQU 0x40006a16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_A1 +CYREG_B1_UDB04_05_A1 EQU 0x40006a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_A1 +CYREG_B1_UDB05_06_A1 EQU 0x40006a2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_A1 +CYREG_B1_UDB06_07_A1 EQU 0x40006a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_A1 +CYREG_B1_UDB07_08_A1 EQU 0x40006a2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_A1 +CYREG_B1_UDB08_09_A1 EQU 0x40006a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_A1 +CYREG_B1_UDB09_10_A1 EQU 0x40006a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_A1 +CYREG_B1_UDB10_11_A1 EQU 0x40006a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_A1 +CYREG_B1_UDB11_12_A1 EQU 0x40006a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D0 +CYREG_B1_UDB04_05_D0 EQU 0x40006a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D0 +CYREG_B1_UDB05_06_D0 EQU 0x40006a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D0 +CYREG_B1_UDB06_07_D0 EQU 0x40006a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D0 +CYREG_B1_UDB07_08_D0 EQU 0x40006a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D0 +CYREG_B1_UDB08_09_D0 EQU 0x40006a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D0 +CYREG_B1_UDB09_10_D0 EQU 0x40006a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D0 +CYREG_B1_UDB10_11_D0 EQU 0x40006a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D0 +CYREG_B1_UDB11_12_D0 EQU 0x40006a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_D1 +CYREG_B1_UDB04_05_D1 EQU 0x40006a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_D1 +CYREG_B1_UDB05_06_D1 EQU 0x40006a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_D1 +CYREG_B1_UDB06_07_D1 EQU 0x40006a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_D1 +CYREG_B1_UDB07_08_D1 EQU 0x40006a6e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_D1 +CYREG_B1_UDB08_09_D1 EQU 0x40006a70 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_D1 +CYREG_B1_UDB09_10_D1 EQU 0x40006a72 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_D1 +CYREG_B1_UDB10_11_D1 EQU 0x40006a74 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_D1 +CYREG_B1_UDB11_12_D1 EQU 0x40006a76 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F0 +CYREG_B1_UDB04_05_F0 EQU 0x40006a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F0 +CYREG_B1_UDB05_06_F0 EQU 0x40006a8a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F0 +CYREG_B1_UDB06_07_F0 EQU 0x40006a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F0 +CYREG_B1_UDB07_08_F0 EQU 0x40006a8e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F0 +CYREG_B1_UDB08_09_F0 EQU 0x40006a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F0 +CYREG_B1_UDB09_10_F0 EQU 0x40006a92 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F0 +CYREG_B1_UDB10_11_F0 EQU 0x40006a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F0 +CYREG_B1_UDB11_12_F0 EQU 0x40006a96 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_F1 +CYREG_B1_UDB04_05_F1 EQU 0x40006aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_F1 +CYREG_B1_UDB05_06_F1 EQU 0x40006aaa + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_F1 +CYREG_B1_UDB06_07_F1 EQU 0x40006aac + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_F1 +CYREG_B1_UDB07_08_F1 EQU 0x40006aae + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_F1 +CYREG_B1_UDB08_09_F1 EQU 0x40006ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_F1 +CYREG_B1_UDB09_10_F1 EQU 0x40006ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_F1 +CYREG_B1_UDB10_11_F1 EQU 0x40006ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_F1 +CYREG_B1_UDB11_12_F1 EQU 0x40006ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ST +CYREG_B1_UDB04_05_ST EQU 0x40006ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ST +CYREG_B1_UDB05_06_ST EQU 0x40006aca + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ST +CYREG_B1_UDB06_07_ST EQU 0x40006acc + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ST +CYREG_B1_UDB07_08_ST EQU 0x40006ace + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ST +CYREG_B1_UDB08_09_ST EQU 0x40006ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ST +CYREG_B1_UDB09_10_ST EQU 0x40006ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ST +CYREG_B1_UDB10_11_ST EQU 0x40006ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ST +CYREG_B1_UDB11_12_ST EQU 0x40006ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_CTL +CYREG_B1_UDB04_05_CTL EQU 0x40006ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_CTL +CYREG_B1_UDB05_06_CTL EQU 0x40006aea + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_CTL +CYREG_B1_UDB06_07_CTL EQU 0x40006aec + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_CTL +CYREG_B1_UDB07_08_CTL EQU 0x40006aee + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_CTL +CYREG_B1_UDB08_09_CTL EQU 0x40006af0 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_CTL +CYREG_B1_UDB09_10_CTL EQU 0x40006af2 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_CTL +CYREG_B1_UDB10_11_CTL EQU 0x40006af4 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_CTL +CYREG_B1_UDB11_12_CTL EQU 0x40006af6 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MSK +CYREG_B1_UDB04_05_MSK EQU 0x40006b08 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MSK +CYREG_B1_UDB05_06_MSK EQU 0x40006b0a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MSK +CYREG_B1_UDB06_07_MSK EQU 0x40006b0c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MSK +CYREG_B1_UDB07_08_MSK EQU 0x40006b0e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MSK +CYREG_B1_UDB08_09_MSK EQU 0x40006b10 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MSK +CYREG_B1_UDB09_10_MSK EQU 0x40006b12 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MSK +CYREG_B1_UDB10_11_MSK EQU 0x40006b14 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MSK +CYREG_B1_UDB11_12_MSK EQU 0x40006b16 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_ACTL +CYREG_B1_UDB04_05_ACTL EQU 0x40006b28 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_ACTL +CYREG_B1_UDB05_06_ACTL EQU 0x40006b2a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_ACTL +CYREG_B1_UDB06_07_ACTL EQU 0x40006b2c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_ACTL +CYREG_B1_UDB07_08_ACTL EQU 0x40006b2e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_ACTL +CYREG_B1_UDB08_09_ACTL EQU 0x40006b30 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_ACTL +CYREG_B1_UDB09_10_ACTL EQU 0x40006b32 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_ACTL +CYREG_B1_UDB10_11_ACTL EQU 0x40006b34 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_ACTL +CYREG_B1_UDB11_12_ACTL EQU 0x40006b36 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB04_05_MC +CYREG_B1_UDB04_05_MC EQU 0x40006b48 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB05_06_MC +CYREG_B1_UDB05_06_MC EQU 0x40006b4a + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB06_07_MC +CYREG_B1_UDB06_07_MC EQU 0x40006b4c + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB07_08_MC +CYREG_B1_UDB07_08_MC EQU 0x40006b4e + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB08_09_MC +CYREG_B1_UDB08_09_MC EQU 0x40006b50 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB09_10_MC +CYREG_B1_UDB09_10_MC EQU 0x40006b52 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB10_11_MC +CYREG_B1_UDB10_11_MC EQU 0x40006b54 + ENDIF + IF :LNOT::DEF:CYREG_B1_UDB11_12_MC +CYREG_B1_UDB11_12_MC EQU 0x40006b56 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_BASE +CYDEV_PHUB_BASE EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_SIZE +CYDEV_PHUB_SIZE EQU 0x00000c00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFG +CYREG_PHUB_CFG EQU 0x40007000 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR +CYREG_PHUB_ERR EQU 0x40007004 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_ERR_ADR +CYREG_PHUB_ERR_ADR EQU 0x40007008 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_BASE +CYDEV_PHUB_CH0_BASE EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH0_SIZE +CYDEV_PHUB_CH0_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_CFG +CYREG_PHUB_CH0_BASIC_CFG EQU 0x40007010 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_ACTION +CYREG_PHUB_CH0_ACTION EQU 0x40007014 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH0_BASIC_STATUS +CYREG_PHUB_CH0_BASIC_STATUS EQU 0x40007018 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_BASE +CYDEV_PHUB_CH1_BASE EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH1_SIZE +CYDEV_PHUB_CH1_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_CFG +CYREG_PHUB_CH1_BASIC_CFG EQU 0x40007020 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_ACTION +CYREG_PHUB_CH1_ACTION EQU 0x40007024 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH1_BASIC_STATUS +CYREG_PHUB_CH1_BASIC_STATUS EQU 0x40007028 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_BASE +CYDEV_PHUB_CH2_BASE EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH2_SIZE +CYDEV_PHUB_CH2_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_CFG +CYREG_PHUB_CH2_BASIC_CFG EQU 0x40007030 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_ACTION +CYREG_PHUB_CH2_ACTION EQU 0x40007034 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH2_BASIC_STATUS +CYREG_PHUB_CH2_BASIC_STATUS EQU 0x40007038 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_BASE +CYDEV_PHUB_CH3_BASE EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH3_SIZE +CYDEV_PHUB_CH3_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_CFG +CYREG_PHUB_CH3_BASIC_CFG EQU 0x40007040 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_ACTION +CYREG_PHUB_CH3_ACTION EQU 0x40007044 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH3_BASIC_STATUS +CYREG_PHUB_CH3_BASIC_STATUS EQU 0x40007048 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_BASE +CYDEV_PHUB_CH4_BASE EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH4_SIZE +CYDEV_PHUB_CH4_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_CFG +CYREG_PHUB_CH4_BASIC_CFG EQU 0x40007050 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_ACTION +CYREG_PHUB_CH4_ACTION EQU 0x40007054 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH4_BASIC_STATUS +CYREG_PHUB_CH4_BASIC_STATUS EQU 0x40007058 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_BASE +CYDEV_PHUB_CH5_BASE EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH5_SIZE +CYDEV_PHUB_CH5_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_CFG +CYREG_PHUB_CH5_BASIC_CFG EQU 0x40007060 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_ACTION +CYREG_PHUB_CH5_ACTION EQU 0x40007064 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH5_BASIC_STATUS +CYREG_PHUB_CH5_BASIC_STATUS EQU 0x40007068 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_BASE +CYDEV_PHUB_CH6_BASE EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH6_SIZE +CYDEV_PHUB_CH6_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_CFG +CYREG_PHUB_CH6_BASIC_CFG EQU 0x40007070 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_ACTION +CYREG_PHUB_CH6_ACTION EQU 0x40007074 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH6_BASIC_STATUS +CYREG_PHUB_CH6_BASIC_STATUS EQU 0x40007078 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_BASE +CYDEV_PHUB_CH7_BASE EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH7_SIZE +CYDEV_PHUB_CH7_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_CFG +CYREG_PHUB_CH7_BASIC_CFG EQU 0x40007080 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_ACTION +CYREG_PHUB_CH7_ACTION EQU 0x40007084 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH7_BASIC_STATUS +CYREG_PHUB_CH7_BASIC_STATUS EQU 0x40007088 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_BASE +CYDEV_PHUB_CH8_BASE EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH8_SIZE +CYDEV_PHUB_CH8_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_CFG +CYREG_PHUB_CH8_BASIC_CFG EQU 0x40007090 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_ACTION +CYREG_PHUB_CH8_ACTION EQU 0x40007094 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH8_BASIC_STATUS +CYREG_PHUB_CH8_BASIC_STATUS EQU 0x40007098 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_BASE +CYDEV_PHUB_CH9_BASE EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH9_SIZE +CYDEV_PHUB_CH9_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_CFG +CYREG_PHUB_CH9_BASIC_CFG EQU 0x400070a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_ACTION +CYREG_PHUB_CH9_ACTION EQU 0x400070a4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH9_BASIC_STATUS +CYREG_PHUB_CH9_BASIC_STATUS EQU 0x400070a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_BASE +CYDEV_PHUB_CH10_BASE EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH10_SIZE +CYDEV_PHUB_CH10_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_CFG +CYREG_PHUB_CH10_BASIC_CFG EQU 0x400070b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_ACTION +CYREG_PHUB_CH10_ACTION EQU 0x400070b4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH10_BASIC_STATUS +CYREG_PHUB_CH10_BASIC_STATUS EQU 0x400070b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_BASE +CYDEV_PHUB_CH11_BASE EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH11_SIZE +CYDEV_PHUB_CH11_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_CFG +CYREG_PHUB_CH11_BASIC_CFG EQU 0x400070c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_ACTION +CYREG_PHUB_CH11_ACTION EQU 0x400070c4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH11_BASIC_STATUS +CYREG_PHUB_CH11_BASIC_STATUS EQU 0x400070c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_BASE +CYDEV_PHUB_CH12_BASE EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH12_SIZE +CYDEV_PHUB_CH12_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_CFG +CYREG_PHUB_CH12_BASIC_CFG EQU 0x400070d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_ACTION +CYREG_PHUB_CH12_ACTION EQU 0x400070d4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH12_BASIC_STATUS +CYREG_PHUB_CH12_BASIC_STATUS EQU 0x400070d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_BASE +CYDEV_PHUB_CH13_BASE EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH13_SIZE +CYDEV_PHUB_CH13_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_CFG +CYREG_PHUB_CH13_BASIC_CFG EQU 0x400070e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_ACTION +CYREG_PHUB_CH13_ACTION EQU 0x400070e4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH13_BASIC_STATUS +CYREG_PHUB_CH13_BASIC_STATUS EQU 0x400070e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_BASE +CYDEV_PHUB_CH14_BASE EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH14_SIZE +CYDEV_PHUB_CH14_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_CFG +CYREG_PHUB_CH14_BASIC_CFG EQU 0x400070f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_ACTION +CYREG_PHUB_CH14_ACTION EQU 0x400070f4 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH14_BASIC_STATUS +CYREG_PHUB_CH14_BASIC_STATUS EQU 0x400070f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_BASE +CYDEV_PHUB_CH15_BASE EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH15_SIZE +CYDEV_PHUB_CH15_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_CFG +CYREG_PHUB_CH15_BASIC_CFG EQU 0x40007100 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_ACTION +CYREG_PHUB_CH15_ACTION EQU 0x40007104 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH15_BASIC_STATUS +CYREG_PHUB_CH15_BASIC_STATUS EQU 0x40007108 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_BASE +CYDEV_PHUB_CH16_BASE EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH16_SIZE +CYDEV_PHUB_CH16_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_CFG +CYREG_PHUB_CH16_BASIC_CFG EQU 0x40007110 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_ACTION +CYREG_PHUB_CH16_ACTION EQU 0x40007114 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH16_BASIC_STATUS +CYREG_PHUB_CH16_BASIC_STATUS EQU 0x40007118 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_BASE +CYDEV_PHUB_CH17_BASE EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH17_SIZE +CYDEV_PHUB_CH17_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_CFG +CYREG_PHUB_CH17_BASIC_CFG EQU 0x40007120 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_ACTION +CYREG_PHUB_CH17_ACTION EQU 0x40007124 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH17_BASIC_STATUS +CYREG_PHUB_CH17_BASIC_STATUS EQU 0x40007128 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_BASE +CYDEV_PHUB_CH18_BASE EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH18_SIZE +CYDEV_PHUB_CH18_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_CFG +CYREG_PHUB_CH18_BASIC_CFG EQU 0x40007130 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_ACTION +CYREG_PHUB_CH18_ACTION EQU 0x40007134 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH18_BASIC_STATUS +CYREG_PHUB_CH18_BASIC_STATUS EQU 0x40007138 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_BASE +CYDEV_PHUB_CH19_BASE EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH19_SIZE +CYDEV_PHUB_CH19_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_CFG +CYREG_PHUB_CH19_BASIC_CFG EQU 0x40007140 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_ACTION +CYREG_PHUB_CH19_ACTION EQU 0x40007144 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH19_BASIC_STATUS +CYREG_PHUB_CH19_BASIC_STATUS EQU 0x40007148 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_BASE +CYDEV_PHUB_CH20_BASE EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH20_SIZE +CYDEV_PHUB_CH20_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_CFG +CYREG_PHUB_CH20_BASIC_CFG EQU 0x40007150 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_ACTION +CYREG_PHUB_CH20_ACTION EQU 0x40007154 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH20_BASIC_STATUS +CYREG_PHUB_CH20_BASIC_STATUS EQU 0x40007158 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_BASE +CYDEV_PHUB_CH21_BASE EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH21_SIZE +CYDEV_PHUB_CH21_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_CFG +CYREG_PHUB_CH21_BASIC_CFG EQU 0x40007160 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_ACTION +CYREG_PHUB_CH21_ACTION EQU 0x40007164 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH21_BASIC_STATUS +CYREG_PHUB_CH21_BASIC_STATUS EQU 0x40007168 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_BASE +CYDEV_PHUB_CH22_BASE EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH22_SIZE +CYDEV_PHUB_CH22_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_CFG +CYREG_PHUB_CH22_BASIC_CFG EQU 0x40007170 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_ACTION +CYREG_PHUB_CH22_ACTION EQU 0x40007174 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH22_BASIC_STATUS +CYREG_PHUB_CH22_BASIC_STATUS EQU 0x40007178 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_BASE +CYDEV_PHUB_CH23_BASE EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CH23_SIZE +CYDEV_PHUB_CH23_SIZE EQU 0x0000000c + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_CFG +CYREG_PHUB_CH23_BASIC_CFG EQU 0x40007180 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_ACTION +CYREG_PHUB_CH23_ACTION EQU 0x40007184 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CH23_BASIC_STATUS +CYREG_PHUB_CH23_BASIC_STATUS EQU 0x40007188 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_BASE +CYDEV_PHUB_CFGMEM0_BASE EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM0_SIZE +CYDEV_PHUB_CFGMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG0 +CYREG_PHUB_CFGMEM0_CFG0 EQU 0x40007600 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM0_CFG1 +CYREG_PHUB_CFGMEM0_CFG1 EQU 0x40007604 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_BASE +CYDEV_PHUB_CFGMEM1_BASE EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM1_SIZE +CYDEV_PHUB_CFGMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG0 +CYREG_PHUB_CFGMEM1_CFG0 EQU 0x40007608 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM1_CFG1 +CYREG_PHUB_CFGMEM1_CFG1 EQU 0x4000760c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_BASE +CYDEV_PHUB_CFGMEM2_BASE EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM2_SIZE +CYDEV_PHUB_CFGMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG0 +CYREG_PHUB_CFGMEM2_CFG0 EQU 0x40007610 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM2_CFG1 +CYREG_PHUB_CFGMEM2_CFG1 EQU 0x40007614 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_BASE +CYDEV_PHUB_CFGMEM3_BASE EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM3_SIZE +CYDEV_PHUB_CFGMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG0 +CYREG_PHUB_CFGMEM3_CFG0 EQU 0x40007618 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM3_CFG1 +CYREG_PHUB_CFGMEM3_CFG1 EQU 0x4000761c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_BASE +CYDEV_PHUB_CFGMEM4_BASE EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM4_SIZE +CYDEV_PHUB_CFGMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG0 +CYREG_PHUB_CFGMEM4_CFG0 EQU 0x40007620 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM4_CFG1 +CYREG_PHUB_CFGMEM4_CFG1 EQU 0x40007624 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_BASE +CYDEV_PHUB_CFGMEM5_BASE EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM5_SIZE +CYDEV_PHUB_CFGMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG0 +CYREG_PHUB_CFGMEM5_CFG0 EQU 0x40007628 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM5_CFG1 +CYREG_PHUB_CFGMEM5_CFG1 EQU 0x4000762c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_BASE +CYDEV_PHUB_CFGMEM6_BASE EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM6_SIZE +CYDEV_PHUB_CFGMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG0 +CYREG_PHUB_CFGMEM6_CFG0 EQU 0x40007630 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM6_CFG1 +CYREG_PHUB_CFGMEM6_CFG1 EQU 0x40007634 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_BASE +CYDEV_PHUB_CFGMEM7_BASE EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM7_SIZE +CYDEV_PHUB_CFGMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG0 +CYREG_PHUB_CFGMEM7_CFG0 EQU 0x40007638 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM7_CFG1 +CYREG_PHUB_CFGMEM7_CFG1 EQU 0x4000763c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_BASE +CYDEV_PHUB_CFGMEM8_BASE EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM8_SIZE +CYDEV_PHUB_CFGMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG0 +CYREG_PHUB_CFGMEM8_CFG0 EQU 0x40007640 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM8_CFG1 +CYREG_PHUB_CFGMEM8_CFG1 EQU 0x40007644 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_BASE +CYDEV_PHUB_CFGMEM9_BASE EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM9_SIZE +CYDEV_PHUB_CFGMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG0 +CYREG_PHUB_CFGMEM9_CFG0 EQU 0x40007648 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM9_CFG1 +CYREG_PHUB_CFGMEM9_CFG1 EQU 0x4000764c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_BASE +CYDEV_PHUB_CFGMEM10_BASE EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM10_SIZE +CYDEV_PHUB_CFGMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG0 +CYREG_PHUB_CFGMEM10_CFG0 EQU 0x40007650 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM10_CFG1 +CYREG_PHUB_CFGMEM10_CFG1 EQU 0x40007654 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_BASE +CYDEV_PHUB_CFGMEM11_BASE EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM11_SIZE +CYDEV_PHUB_CFGMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG0 +CYREG_PHUB_CFGMEM11_CFG0 EQU 0x40007658 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM11_CFG1 +CYREG_PHUB_CFGMEM11_CFG1 EQU 0x4000765c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_BASE +CYDEV_PHUB_CFGMEM12_BASE EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM12_SIZE +CYDEV_PHUB_CFGMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG0 +CYREG_PHUB_CFGMEM12_CFG0 EQU 0x40007660 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM12_CFG1 +CYREG_PHUB_CFGMEM12_CFG1 EQU 0x40007664 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_BASE +CYDEV_PHUB_CFGMEM13_BASE EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM13_SIZE +CYDEV_PHUB_CFGMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG0 +CYREG_PHUB_CFGMEM13_CFG0 EQU 0x40007668 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM13_CFG1 +CYREG_PHUB_CFGMEM13_CFG1 EQU 0x4000766c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_BASE +CYDEV_PHUB_CFGMEM14_BASE EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM14_SIZE +CYDEV_PHUB_CFGMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG0 +CYREG_PHUB_CFGMEM14_CFG0 EQU 0x40007670 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM14_CFG1 +CYREG_PHUB_CFGMEM14_CFG1 EQU 0x40007674 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_BASE +CYDEV_PHUB_CFGMEM15_BASE EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM15_SIZE +CYDEV_PHUB_CFGMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG0 +CYREG_PHUB_CFGMEM15_CFG0 EQU 0x40007678 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM15_CFG1 +CYREG_PHUB_CFGMEM15_CFG1 EQU 0x4000767c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_BASE +CYDEV_PHUB_CFGMEM16_BASE EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM16_SIZE +CYDEV_PHUB_CFGMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG0 +CYREG_PHUB_CFGMEM16_CFG0 EQU 0x40007680 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM16_CFG1 +CYREG_PHUB_CFGMEM16_CFG1 EQU 0x40007684 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_BASE +CYDEV_PHUB_CFGMEM17_BASE EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM17_SIZE +CYDEV_PHUB_CFGMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG0 +CYREG_PHUB_CFGMEM17_CFG0 EQU 0x40007688 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM17_CFG1 +CYREG_PHUB_CFGMEM17_CFG1 EQU 0x4000768c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_BASE +CYDEV_PHUB_CFGMEM18_BASE EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM18_SIZE +CYDEV_PHUB_CFGMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG0 +CYREG_PHUB_CFGMEM18_CFG0 EQU 0x40007690 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM18_CFG1 +CYREG_PHUB_CFGMEM18_CFG1 EQU 0x40007694 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_BASE +CYDEV_PHUB_CFGMEM19_BASE EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM19_SIZE +CYDEV_PHUB_CFGMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG0 +CYREG_PHUB_CFGMEM19_CFG0 EQU 0x40007698 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM19_CFG1 +CYREG_PHUB_CFGMEM19_CFG1 EQU 0x4000769c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_BASE +CYDEV_PHUB_CFGMEM20_BASE EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM20_SIZE +CYDEV_PHUB_CFGMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG0 +CYREG_PHUB_CFGMEM20_CFG0 EQU 0x400076a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM20_CFG1 +CYREG_PHUB_CFGMEM20_CFG1 EQU 0x400076a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_BASE +CYDEV_PHUB_CFGMEM21_BASE EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM21_SIZE +CYDEV_PHUB_CFGMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG0 +CYREG_PHUB_CFGMEM21_CFG0 EQU 0x400076a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM21_CFG1 +CYREG_PHUB_CFGMEM21_CFG1 EQU 0x400076ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_BASE +CYDEV_PHUB_CFGMEM22_BASE EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM22_SIZE +CYDEV_PHUB_CFGMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG0 +CYREG_PHUB_CFGMEM22_CFG0 EQU 0x400076b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM22_CFG1 +CYREG_PHUB_CFGMEM22_CFG1 EQU 0x400076b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_BASE +CYDEV_PHUB_CFGMEM23_BASE EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_CFGMEM23_SIZE +CYDEV_PHUB_CFGMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG0 +CYREG_PHUB_CFGMEM23_CFG0 EQU 0x400076b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_CFGMEM23_CFG1 +CYREG_PHUB_CFGMEM23_CFG1 EQU 0x400076bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_BASE +CYDEV_PHUB_TDMEM0_BASE EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM0_SIZE +CYDEV_PHUB_TDMEM0_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD0 +CYREG_PHUB_TDMEM0_ORIG_TD0 EQU 0x40007800 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM0_ORIG_TD1 +CYREG_PHUB_TDMEM0_ORIG_TD1 EQU 0x40007804 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_BASE +CYDEV_PHUB_TDMEM1_BASE EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM1_SIZE +CYDEV_PHUB_TDMEM1_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD0 +CYREG_PHUB_TDMEM1_ORIG_TD0 EQU 0x40007808 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM1_ORIG_TD1 +CYREG_PHUB_TDMEM1_ORIG_TD1 EQU 0x4000780c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_BASE +CYDEV_PHUB_TDMEM2_BASE EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM2_SIZE +CYDEV_PHUB_TDMEM2_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD0 +CYREG_PHUB_TDMEM2_ORIG_TD0 EQU 0x40007810 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM2_ORIG_TD1 +CYREG_PHUB_TDMEM2_ORIG_TD1 EQU 0x40007814 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_BASE +CYDEV_PHUB_TDMEM3_BASE EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM3_SIZE +CYDEV_PHUB_TDMEM3_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD0 +CYREG_PHUB_TDMEM3_ORIG_TD0 EQU 0x40007818 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM3_ORIG_TD1 +CYREG_PHUB_TDMEM3_ORIG_TD1 EQU 0x4000781c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_BASE +CYDEV_PHUB_TDMEM4_BASE EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM4_SIZE +CYDEV_PHUB_TDMEM4_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD0 +CYREG_PHUB_TDMEM4_ORIG_TD0 EQU 0x40007820 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM4_ORIG_TD1 +CYREG_PHUB_TDMEM4_ORIG_TD1 EQU 0x40007824 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_BASE +CYDEV_PHUB_TDMEM5_BASE EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM5_SIZE +CYDEV_PHUB_TDMEM5_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD0 +CYREG_PHUB_TDMEM5_ORIG_TD0 EQU 0x40007828 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM5_ORIG_TD1 +CYREG_PHUB_TDMEM5_ORIG_TD1 EQU 0x4000782c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_BASE +CYDEV_PHUB_TDMEM6_BASE EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM6_SIZE +CYDEV_PHUB_TDMEM6_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD0 +CYREG_PHUB_TDMEM6_ORIG_TD0 EQU 0x40007830 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM6_ORIG_TD1 +CYREG_PHUB_TDMEM6_ORIG_TD1 EQU 0x40007834 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_BASE +CYDEV_PHUB_TDMEM7_BASE EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM7_SIZE +CYDEV_PHUB_TDMEM7_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD0 +CYREG_PHUB_TDMEM7_ORIG_TD0 EQU 0x40007838 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM7_ORIG_TD1 +CYREG_PHUB_TDMEM7_ORIG_TD1 EQU 0x4000783c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_BASE +CYDEV_PHUB_TDMEM8_BASE EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM8_SIZE +CYDEV_PHUB_TDMEM8_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD0 +CYREG_PHUB_TDMEM8_ORIG_TD0 EQU 0x40007840 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM8_ORIG_TD1 +CYREG_PHUB_TDMEM8_ORIG_TD1 EQU 0x40007844 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_BASE +CYDEV_PHUB_TDMEM9_BASE EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM9_SIZE +CYDEV_PHUB_TDMEM9_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD0 +CYREG_PHUB_TDMEM9_ORIG_TD0 EQU 0x40007848 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM9_ORIG_TD1 +CYREG_PHUB_TDMEM9_ORIG_TD1 EQU 0x4000784c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_BASE +CYDEV_PHUB_TDMEM10_BASE EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM10_SIZE +CYDEV_PHUB_TDMEM10_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD0 +CYREG_PHUB_TDMEM10_ORIG_TD0 EQU 0x40007850 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM10_ORIG_TD1 +CYREG_PHUB_TDMEM10_ORIG_TD1 EQU 0x40007854 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_BASE +CYDEV_PHUB_TDMEM11_BASE EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM11_SIZE +CYDEV_PHUB_TDMEM11_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD0 +CYREG_PHUB_TDMEM11_ORIG_TD0 EQU 0x40007858 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM11_ORIG_TD1 +CYREG_PHUB_TDMEM11_ORIG_TD1 EQU 0x4000785c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_BASE +CYDEV_PHUB_TDMEM12_BASE EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM12_SIZE +CYDEV_PHUB_TDMEM12_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD0 +CYREG_PHUB_TDMEM12_ORIG_TD0 EQU 0x40007860 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM12_ORIG_TD1 +CYREG_PHUB_TDMEM12_ORIG_TD1 EQU 0x40007864 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_BASE +CYDEV_PHUB_TDMEM13_BASE EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM13_SIZE +CYDEV_PHUB_TDMEM13_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD0 +CYREG_PHUB_TDMEM13_ORIG_TD0 EQU 0x40007868 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM13_ORIG_TD1 +CYREG_PHUB_TDMEM13_ORIG_TD1 EQU 0x4000786c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_BASE +CYDEV_PHUB_TDMEM14_BASE EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM14_SIZE +CYDEV_PHUB_TDMEM14_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD0 +CYREG_PHUB_TDMEM14_ORIG_TD0 EQU 0x40007870 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM14_ORIG_TD1 +CYREG_PHUB_TDMEM14_ORIG_TD1 EQU 0x40007874 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_BASE +CYDEV_PHUB_TDMEM15_BASE EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM15_SIZE +CYDEV_PHUB_TDMEM15_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD0 +CYREG_PHUB_TDMEM15_ORIG_TD0 EQU 0x40007878 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM15_ORIG_TD1 +CYREG_PHUB_TDMEM15_ORIG_TD1 EQU 0x4000787c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_BASE +CYDEV_PHUB_TDMEM16_BASE EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM16_SIZE +CYDEV_PHUB_TDMEM16_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD0 +CYREG_PHUB_TDMEM16_ORIG_TD0 EQU 0x40007880 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM16_ORIG_TD1 +CYREG_PHUB_TDMEM16_ORIG_TD1 EQU 0x40007884 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_BASE +CYDEV_PHUB_TDMEM17_BASE EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM17_SIZE +CYDEV_PHUB_TDMEM17_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD0 +CYREG_PHUB_TDMEM17_ORIG_TD0 EQU 0x40007888 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM17_ORIG_TD1 +CYREG_PHUB_TDMEM17_ORIG_TD1 EQU 0x4000788c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_BASE +CYDEV_PHUB_TDMEM18_BASE EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM18_SIZE +CYDEV_PHUB_TDMEM18_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD0 +CYREG_PHUB_TDMEM18_ORIG_TD0 EQU 0x40007890 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM18_ORIG_TD1 +CYREG_PHUB_TDMEM18_ORIG_TD1 EQU 0x40007894 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_BASE +CYDEV_PHUB_TDMEM19_BASE EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM19_SIZE +CYDEV_PHUB_TDMEM19_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD0 +CYREG_PHUB_TDMEM19_ORIG_TD0 EQU 0x40007898 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM19_ORIG_TD1 +CYREG_PHUB_TDMEM19_ORIG_TD1 EQU 0x4000789c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_BASE +CYDEV_PHUB_TDMEM20_BASE EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM20_SIZE +CYDEV_PHUB_TDMEM20_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD0 +CYREG_PHUB_TDMEM20_ORIG_TD0 EQU 0x400078a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM20_ORIG_TD1 +CYREG_PHUB_TDMEM20_ORIG_TD1 EQU 0x400078a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_BASE +CYDEV_PHUB_TDMEM21_BASE EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM21_SIZE +CYDEV_PHUB_TDMEM21_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD0 +CYREG_PHUB_TDMEM21_ORIG_TD0 EQU 0x400078a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM21_ORIG_TD1 +CYREG_PHUB_TDMEM21_ORIG_TD1 EQU 0x400078ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_BASE +CYDEV_PHUB_TDMEM22_BASE EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM22_SIZE +CYDEV_PHUB_TDMEM22_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD0 +CYREG_PHUB_TDMEM22_ORIG_TD0 EQU 0x400078b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM22_ORIG_TD1 +CYREG_PHUB_TDMEM22_ORIG_TD1 EQU 0x400078b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_BASE +CYDEV_PHUB_TDMEM23_BASE EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM23_SIZE +CYDEV_PHUB_TDMEM23_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD0 +CYREG_PHUB_TDMEM23_ORIG_TD0 EQU 0x400078b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM23_ORIG_TD1 +CYREG_PHUB_TDMEM23_ORIG_TD1 EQU 0x400078bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_BASE +CYDEV_PHUB_TDMEM24_BASE EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM24_SIZE +CYDEV_PHUB_TDMEM24_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD0 +CYREG_PHUB_TDMEM24_ORIG_TD0 EQU 0x400078c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM24_ORIG_TD1 +CYREG_PHUB_TDMEM24_ORIG_TD1 EQU 0x400078c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_BASE +CYDEV_PHUB_TDMEM25_BASE EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM25_SIZE +CYDEV_PHUB_TDMEM25_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD0 +CYREG_PHUB_TDMEM25_ORIG_TD0 EQU 0x400078c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM25_ORIG_TD1 +CYREG_PHUB_TDMEM25_ORIG_TD1 EQU 0x400078cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_BASE +CYDEV_PHUB_TDMEM26_BASE EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM26_SIZE +CYDEV_PHUB_TDMEM26_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD0 +CYREG_PHUB_TDMEM26_ORIG_TD0 EQU 0x400078d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM26_ORIG_TD1 +CYREG_PHUB_TDMEM26_ORIG_TD1 EQU 0x400078d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_BASE +CYDEV_PHUB_TDMEM27_BASE EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM27_SIZE +CYDEV_PHUB_TDMEM27_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD0 +CYREG_PHUB_TDMEM27_ORIG_TD0 EQU 0x400078d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM27_ORIG_TD1 +CYREG_PHUB_TDMEM27_ORIG_TD1 EQU 0x400078dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_BASE +CYDEV_PHUB_TDMEM28_BASE EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM28_SIZE +CYDEV_PHUB_TDMEM28_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD0 +CYREG_PHUB_TDMEM28_ORIG_TD0 EQU 0x400078e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM28_ORIG_TD1 +CYREG_PHUB_TDMEM28_ORIG_TD1 EQU 0x400078e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_BASE +CYDEV_PHUB_TDMEM29_BASE EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM29_SIZE +CYDEV_PHUB_TDMEM29_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD0 +CYREG_PHUB_TDMEM29_ORIG_TD0 EQU 0x400078e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM29_ORIG_TD1 +CYREG_PHUB_TDMEM29_ORIG_TD1 EQU 0x400078ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_BASE +CYDEV_PHUB_TDMEM30_BASE EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM30_SIZE +CYDEV_PHUB_TDMEM30_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD0 +CYREG_PHUB_TDMEM30_ORIG_TD0 EQU 0x400078f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM30_ORIG_TD1 +CYREG_PHUB_TDMEM30_ORIG_TD1 EQU 0x400078f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_BASE +CYDEV_PHUB_TDMEM31_BASE EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM31_SIZE +CYDEV_PHUB_TDMEM31_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD0 +CYREG_PHUB_TDMEM31_ORIG_TD0 EQU 0x400078f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM31_ORIG_TD1 +CYREG_PHUB_TDMEM31_ORIG_TD1 EQU 0x400078fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_BASE +CYDEV_PHUB_TDMEM32_BASE EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM32_SIZE +CYDEV_PHUB_TDMEM32_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD0 +CYREG_PHUB_TDMEM32_ORIG_TD0 EQU 0x40007900 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM32_ORIG_TD1 +CYREG_PHUB_TDMEM32_ORIG_TD1 EQU 0x40007904 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_BASE +CYDEV_PHUB_TDMEM33_BASE EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM33_SIZE +CYDEV_PHUB_TDMEM33_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD0 +CYREG_PHUB_TDMEM33_ORIG_TD0 EQU 0x40007908 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM33_ORIG_TD1 +CYREG_PHUB_TDMEM33_ORIG_TD1 EQU 0x4000790c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_BASE +CYDEV_PHUB_TDMEM34_BASE EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM34_SIZE +CYDEV_PHUB_TDMEM34_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD0 +CYREG_PHUB_TDMEM34_ORIG_TD0 EQU 0x40007910 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM34_ORIG_TD1 +CYREG_PHUB_TDMEM34_ORIG_TD1 EQU 0x40007914 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_BASE +CYDEV_PHUB_TDMEM35_BASE EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM35_SIZE +CYDEV_PHUB_TDMEM35_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD0 +CYREG_PHUB_TDMEM35_ORIG_TD0 EQU 0x40007918 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM35_ORIG_TD1 +CYREG_PHUB_TDMEM35_ORIG_TD1 EQU 0x4000791c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_BASE +CYDEV_PHUB_TDMEM36_BASE EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM36_SIZE +CYDEV_PHUB_TDMEM36_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD0 +CYREG_PHUB_TDMEM36_ORIG_TD0 EQU 0x40007920 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM36_ORIG_TD1 +CYREG_PHUB_TDMEM36_ORIG_TD1 EQU 0x40007924 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_BASE +CYDEV_PHUB_TDMEM37_BASE EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM37_SIZE +CYDEV_PHUB_TDMEM37_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD0 +CYREG_PHUB_TDMEM37_ORIG_TD0 EQU 0x40007928 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM37_ORIG_TD1 +CYREG_PHUB_TDMEM37_ORIG_TD1 EQU 0x4000792c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_BASE +CYDEV_PHUB_TDMEM38_BASE EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM38_SIZE +CYDEV_PHUB_TDMEM38_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD0 +CYREG_PHUB_TDMEM38_ORIG_TD0 EQU 0x40007930 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM38_ORIG_TD1 +CYREG_PHUB_TDMEM38_ORIG_TD1 EQU 0x40007934 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_BASE +CYDEV_PHUB_TDMEM39_BASE EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM39_SIZE +CYDEV_PHUB_TDMEM39_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD0 +CYREG_PHUB_TDMEM39_ORIG_TD0 EQU 0x40007938 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM39_ORIG_TD1 +CYREG_PHUB_TDMEM39_ORIG_TD1 EQU 0x4000793c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_BASE +CYDEV_PHUB_TDMEM40_BASE EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM40_SIZE +CYDEV_PHUB_TDMEM40_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD0 +CYREG_PHUB_TDMEM40_ORIG_TD0 EQU 0x40007940 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM40_ORIG_TD1 +CYREG_PHUB_TDMEM40_ORIG_TD1 EQU 0x40007944 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_BASE +CYDEV_PHUB_TDMEM41_BASE EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM41_SIZE +CYDEV_PHUB_TDMEM41_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD0 +CYREG_PHUB_TDMEM41_ORIG_TD0 EQU 0x40007948 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM41_ORIG_TD1 +CYREG_PHUB_TDMEM41_ORIG_TD1 EQU 0x4000794c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_BASE +CYDEV_PHUB_TDMEM42_BASE EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM42_SIZE +CYDEV_PHUB_TDMEM42_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD0 +CYREG_PHUB_TDMEM42_ORIG_TD0 EQU 0x40007950 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM42_ORIG_TD1 +CYREG_PHUB_TDMEM42_ORIG_TD1 EQU 0x40007954 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_BASE +CYDEV_PHUB_TDMEM43_BASE EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM43_SIZE +CYDEV_PHUB_TDMEM43_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD0 +CYREG_PHUB_TDMEM43_ORIG_TD0 EQU 0x40007958 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM43_ORIG_TD1 +CYREG_PHUB_TDMEM43_ORIG_TD1 EQU 0x4000795c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_BASE +CYDEV_PHUB_TDMEM44_BASE EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM44_SIZE +CYDEV_PHUB_TDMEM44_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD0 +CYREG_PHUB_TDMEM44_ORIG_TD0 EQU 0x40007960 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM44_ORIG_TD1 +CYREG_PHUB_TDMEM44_ORIG_TD1 EQU 0x40007964 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_BASE +CYDEV_PHUB_TDMEM45_BASE EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM45_SIZE +CYDEV_PHUB_TDMEM45_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD0 +CYREG_PHUB_TDMEM45_ORIG_TD0 EQU 0x40007968 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM45_ORIG_TD1 +CYREG_PHUB_TDMEM45_ORIG_TD1 EQU 0x4000796c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_BASE +CYDEV_PHUB_TDMEM46_BASE EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM46_SIZE +CYDEV_PHUB_TDMEM46_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD0 +CYREG_PHUB_TDMEM46_ORIG_TD0 EQU 0x40007970 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM46_ORIG_TD1 +CYREG_PHUB_TDMEM46_ORIG_TD1 EQU 0x40007974 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_BASE +CYDEV_PHUB_TDMEM47_BASE EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM47_SIZE +CYDEV_PHUB_TDMEM47_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD0 +CYREG_PHUB_TDMEM47_ORIG_TD0 EQU 0x40007978 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM47_ORIG_TD1 +CYREG_PHUB_TDMEM47_ORIG_TD1 EQU 0x4000797c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_BASE +CYDEV_PHUB_TDMEM48_BASE EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM48_SIZE +CYDEV_PHUB_TDMEM48_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD0 +CYREG_PHUB_TDMEM48_ORIG_TD0 EQU 0x40007980 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM48_ORIG_TD1 +CYREG_PHUB_TDMEM48_ORIG_TD1 EQU 0x40007984 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_BASE +CYDEV_PHUB_TDMEM49_BASE EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM49_SIZE +CYDEV_PHUB_TDMEM49_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD0 +CYREG_PHUB_TDMEM49_ORIG_TD0 EQU 0x40007988 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM49_ORIG_TD1 +CYREG_PHUB_TDMEM49_ORIG_TD1 EQU 0x4000798c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_BASE +CYDEV_PHUB_TDMEM50_BASE EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM50_SIZE +CYDEV_PHUB_TDMEM50_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD0 +CYREG_PHUB_TDMEM50_ORIG_TD0 EQU 0x40007990 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM50_ORIG_TD1 +CYREG_PHUB_TDMEM50_ORIG_TD1 EQU 0x40007994 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_BASE +CYDEV_PHUB_TDMEM51_BASE EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM51_SIZE +CYDEV_PHUB_TDMEM51_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD0 +CYREG_PHUB_TDMEM51_ORIG_TD0 EQU 0x40007998 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM51_ORIG_TD1 +CYREG_PHUB_TDMEM51_ORIG_TD1 EQU 0x4000799c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_BASE +CYDEV_PHUB_TDMEM52_BASE EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM52_SIZE +CYDEV_PHUB_TDMEM52_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD0 +CYREG_PHUB_TDMEM52_ORIG_TD0 EQU 0x400079a0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM52_ORIG_TD1 +CYREG_PHUB_TDMEM52_ORIG_TD1 EQU 0x400079a4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_BASE +CYDEV_PHUB_TDMEM53_BASE EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM53_SIZE +CYDEV_PHUB_TDMEM53_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD0 +CYREG_PHUB_TDMEM53_ORIG_TD0 EQU 0x400079a8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM53_ORIG_TD1 +CYREG_PHUB_TDMEM53_ORIG_TD1 EQU 0x400079ac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_BASE +CYDEV_PHUB_TDMEM54_BASE EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM54_SIZE +CYDEV_PHUB_TDMEM54_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD0 +CYREG_PHUB_TDMEM54_ORIG_TD0 EQU 0x400079b0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM54_ORIG_TD1 +CYREG_PHUB_TDMEM54_ORIG_TD1 EQU 0x400079b4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_BASE +CYDEV_PHUB_TDMEM55_BASE EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM55_SIZE +CYDEV_PHUB_TDMEM55_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD0 +CYREG_PHUB_TDMEM55_ORIG_TD0 EQU 0x400079b8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM55_ORIG_TD1 +CYREG_PHUB_TDMEM55_ORIG_TD1 EQU 0x400079bc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_BASE +CYDEV_PHUB_TDMEM56_BASE EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM56_SIZE +CYDEV_PHUB_TDMEM56_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD0 +CYREG_PHUB_TDMEM56_ORIG_TD0 EQU 0x400079c0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM56_ORIG_TD1 +CYREG_PHUB_TDMEM56_ORIG_TD1 EQU 0x400079c4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_BASE +CYDEV_PHUB_TDMEM57_BASE EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM57_SIZE +CYDEV_PHUB_TDMEM57_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD0 +CYREG_PHUB_TDMEM57_ORIG_TD0 EQU 0x400079c8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM57_ORIG_TD1 +CYREG_PHUB_TDMEM57_ORIG_TD1 EQU 0x400079cc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_BASE +CYDEV_PHUB_TDMEM58_BASE EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM58_SIZE +CYDEV_PHUB_TDMEM58_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD0 +CYREG_PHUB_TDMEM58_ORIG_TD0 EQU 0x400079d0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM58_ORIG_TD1 +CYREG_PHUB_TDMEM58_ORIG_TD1 EQU 0x400079d4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_BASE +CYDEV_PHUB_TDMEM59_BASE EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM59_SIZE +CYDEV_PHUB_TDMEM59_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD0 +CYREG_PHUB_TDMEM59_ORIG_TD0 EQU 0x400079d8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM59_ORIG_TD1 +CYREG_PHUB_TDMEM59_ORIG_TD1 EQU 0x400079dc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_BASE +CYDEV_PHUB_TDMEM60_BASE EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM60_SIZE +CYDEV_PHUB_TDMEM60_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD0 +CYREG_PHUB_TDMEM60_ORIG_TD0 EQU 0x400079e0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM60_ORIG_TD1 +CYREG_PHUB_TDMEM60_ORIG_TD1 EQU 0x400079e4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_BASE +CYDEV_PHUB_TDMEM61_BASE EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM61_SIZE +CYDEV_PHUB_TDMEM61_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD0 +CYREG_PHUB_TDMEM61_ORIG_TD0 EQU 0x400079e8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM61_ORIG_TD1 +CYREG_PHUB_TDMEM61_ORIG_TD1 EQU 0x400079ec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_BASE +CYDEV_PHUB_TDMEM62_BASE EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM62_SIZE +CYDEV_PHUB_TDMEM62_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD0 +CYREG_PHUB_TDMEM62_ORIG_TD0 EQU 0x400079f0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM62_ORIG_TD1 +CYREG_PHUB_TDMEM62_ORIG_TD1 EQU 0x400079f4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_BASE +CYDEV_PHUB_TDMEM63_BASE EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM63_SIZE +CYDEV_PHUB_TDMEM63_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD0 +CYREG_PHUB_TDMEM63_ORIG_TD0 EQU 0x400079f8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM63_ORIG_TD1 +CYREG_PHUB_TDMEM63_ORIG_TD1 EQU 0x400079fc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_BASE +CYDEV_PHUB_TDMEM64_BASE EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM64_SIZE +CYDEV_PHUB_TDMEM64_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD0 +CYREG_PHUB_TDMEM64_ORIG_TD0 EQU 0x40007a00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM64_ORIG_TD1 +CYREG_PHUB_TDMEM64_ORIG_TD1 EQU 0x40007a04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_BASE +CYDEV_PHUB_TDMEM65_BASE EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM65_SIZE +CYDEV_PHUB_TDMEM65_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD0 +CYREG_PHUB_TDMEM65_ORIG_TD0 EQU 0x40007a08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM65_ORIG_TD1 +CYREG_PHUB_TDMEM65_ORIG_TD1 EQU 0x40007a0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_BASE +CYDEV_PHUB_TDMEM66_BASE EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM66_SIZE +CYDEV_PHUB_TDMEM66_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD0 +CYREG_PHUB_TDMEM66_ORIG_TD0 EQU 0x40007a10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM66_ORIG_TD1 +CYREG_PHUB_TDMEM66_ORIG_TD1 EQU 0x40007a14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_BASE +CYDEV_PHUB_TDMEM67_BASE EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM67_SIZE +CYDEV_PHUB_TDMEM67_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD0 +CYREG_PHUB_TDMEM67_ORIG_TD0 EQU 0x40007a18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM67_ORIG_TD1 +CYREG_PHUB_TDMEM67_ORIG_TD1 EQU 0x40007a1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_BASE +CYDEV_PHUB_TDMEM68_BASE EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM68_SIZE +CYDEV_PHUB_TDMEM68_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD0 +CYREG_PHUB_TDMEM68_ORIG_TD0 EQU 0x40007a20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM68_ORIG_TD1 +CYREG_PHUB_TDMEM68_ORIG_TD1 EQU 0x40007a24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_BASE +CYDEV_PHUB_TDMEM69_BASE EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM69_SIZE +CYDEV_PHUB_TDMEM69_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD0 +CYREG_PHUB_TDMEM69_ORIG_TD0 EQU 0x40007a28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM69_ORIG_TD1 +CYREG_PHUB_TDMEM69_ORIG_TD1 EQU 0x40007a2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_BASE +CYDEV_PHUB_TDMEM70_BASE EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM70_SIZE +CYDEV_PHUB_TDMEM70_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD0 +CYREG_PHUB_TDMEM70_ORIG_TD0 EQU 0x40007a30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM70_ORIG_TD1 +CYREG_PHUB_TDMEM70_ORIG_TD1 EQU 0x40007a34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_BASE +CYDEV_PHUB_TDMEM71_BASE EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM71_SIZE +CYDEV_PHUB_TDMEM71_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD0 +CYREG_PHUB_TDMEM71_ORIG_TD0 EQU 0x40007a38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM71_ORIG_TD1 +CYREG_PHUB_TDMEM71_ORIG_TD1 EQU 0x40007a3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_BASE +CYDEV_PHUB_TDMEM72_BASE EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM72_SIZE +CYDEV_PHUB_TDMEM72_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD0 +CYREG_PHUB_TDMEM72_ORIG_TD0 EQU 0x40007a40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM72_ORIG_TD1 +CYREG_PHUB_TDMEM72_ORIG_TD1 EQU 0x40007a44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_BASE +CYDEV_PHUB_TDMEM73_BASE EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM73_SIZE +CYDEV_PHUB_TDMEM73_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD0 +CYREG_PHUB_TDMEM73_ORIG_TD0 EQU 0x40007a48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM73_ORIG_TD1 +CYREG_PHUB_TDMEM73_ORIG_TD1 EQU 0x40007a4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_BASE +CYDEV_PHUB_TDMEM74_BASE EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM74_SIZE +CYDEV_PHUB_TDMEM74_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD0 +CYREG_PHUB_TDMEM74_ORIG_TD0 EQU 0x40007a50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM74_ORIG_TD1 +CYREG_PHUB_TDMEM74_ORIG_TD1 EQU 0x40007a54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_BASE +CYDEV_PHUB_TDMEM75_BASE EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM75_SIZE +CYDEV_PHUB_TDMEM75_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD0 +CYREG_PHUB_TDMEM75_ORIG_TD0 EQU 0x40007a58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM75_ORIG_TD1 +CYREG_PHUB_TDMEM75_ORIG_TD1 EQU 0x40007a5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_BASE +CYDEV_PHUB_TDMEM76_BASE EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM76_SIZE +CYDEV_PHUB_TDMEM76_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD0 +CYREG_PHUB_TDMEM76_ORIG_TD0 EQU 0x40007a60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM76_ORIG_TD1 +CYREG_PHUB_TDMEM76_ORIG_TD1 EQU 0x40007a64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_BASE +CYDEV_PHUB_TDMEM77_BASE EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM77_SIZE +CYDEV_PHUB_TDMEM77_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD0 +CYREG_PHUB_TDMEM77_ORIG_TD0 EQU 0x40007a68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM77_ORIG_TD1 +CYREG_PHUB_TDMEM77_ORIG_TD1 EQU 0x40007a6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_BASE +CYDEV_PHUB_TDMEM78_BASE EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM78_SIZE +CYDEV_PHUB_TDMEM78_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD0 +CYREG_PHUB_TDMEM78_ORIG_TD0 EQU 0x40007a70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM78_ORIG_TD1 +CYREG_PHUB_TDMEM78_ORIG_TD1 EQU 0x40007a74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_BASE +CYDEV_PHUB_TDMEM79_BASE EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM79_SIZE +CYDEV_PHUB_TDMEM79_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD0 +CYREG_PHUB_TDMEM79_ORIG_TD0 EQU 0x40007a78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM79_ORIG_TD1 +CYREG_PHUB_TDMEM79_ORIG_TD1 EQU 0x40007a7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_BASE +CYDEV_PHUB_TDMEM80_BASE EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM80_SIZE +CYDEV_PHUB_TDMEM80_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD0 +CYREG_PHUB_TDMEM80_ORIG_TD0 EQU 0x40007a80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM80_ORIG_TD1 +CYREG_PHUB_TDMEM80_ORIG_TD1 EQU 0x40007a84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_BASE +CYDEV_PHUB_TDMEM81_BASE EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM81_SIZE +CYDEV_PHUB_TDMEM81_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD0 +CYREG_PHUB_TDMEM81_ORIG_TD0 EQU 0x40007a88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM81_ORIG_TD1 +CYREG_PHUB_TDMEM81_ORIG_TD1 EQU 0x40007a8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_BASE +CYDEV_PHUB_TDMEM82_BASE EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM82_SIZE +CYDEV_PHUB_TDMEM82_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD0 +CYREG_PHUB_TDMEM82_ORIG_TD0 EQU 0x40007a90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM82_ORIG_TD1 +CYREG_PHUB_TDMEM82_ORIG_TD1 EQU 0x40007a94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_BASE +CYDEV_PHUB_TDMEM83_BASE EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM83_SIZE +CYDEV_PHUB_TDMEM83_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD0 +CYREG_PHUB_TDMEM83_ORIG_TD0 EQU 0x40007a98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM83_ORIG_TD1 +CYREG_PHUB_TDMEM83_ORIG_TD1 EQU 0x40007a9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_BASE +CYDEV_PHUB_TDMEM84_BASE EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM84_SIZE +CYDEV_PHUB_TDMEM84_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD0 +CYREG_PHUB_TDMEM84_ORIG_TD0 EQU 0x40007aa0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM84_ORIG_TD1 +CYREG_PHUB_TDMEM84_ORIG_TD1 EQU 0x40007aa4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_BASE +CYDEV_PHUB_TDMEM85_BASE EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM85_SIZE +CYDEV_PHUB_TDMEM85_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD0 +CYREG_PHUB_TDMEM85_ORIG_TD0 EQU 0x40007aa8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM85_ORIG_TD1 +CYREG_PHUB_TDMEM85_ORIG_TD1 EQU 0x40007aac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_BASE +CYDEV_PHUB_TDMEM86_BASE EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM86_SIZE +CYDEV_PHUB_TDMEM86_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD0 +CYREG_PHUB_TDMEM86_ORIG_TD0 EQU 0x40007ab0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM86_ORIG_TD1 +CYREG_PHUB_TDMEM86_ORIG_TD1 EQU 0x40007ab4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_BASE +CYDEV_PHUB_TDMEM87_BASE EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM87_SIZE +CYDEV_PHUB_TDMEM87_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD0 +CYREG_PHUB_TDMEM87_ORIG_TD0 EQU 0x40007ab8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM87_ORIG_TD1 +CYREG_PHUB_TDMEM87_ORIG_TD1 EQU 0x40007abc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_BASE +CYDEV_PHUB_TDMEM88_BASE EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM88_SIZE +CYDEV_PHUB_TDMEM88_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD0 +CYREG_PHUB_TDMEM88_ORIG_TD0 EQU 0x40007ac0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM88_ORIG_TD1 +CYREG_PHUB_TDMEM88_ORIG_TD1 EQU 0x40007ac4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_BASE +CYDEV_PHUB_TDMEM89_BASE EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM89_SIZE +CYDEV_PHUB_TDMEM89_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD0 +CYREG_PHUB_TDMEM89_ORIG_TD0 EQU 0x40007ac8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM89_ORIG_TD1 +CYREG_PHUB_TDMEM89_ORIG_TD1 EQU 0x40007acc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_BASE +CYDEV_PHUB_TDMEM90_BASE EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM90_SIZE +CYDEV_PHUB_TDMEM90_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD0 +CYREG_PHUB_TDMEM90_ORIG_TD0 EQU 0x40007ad0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM90_ORIG_TD1 +CYREG_PHUB_TDMEM90_ORIG_TD1 EQU 0x40007ad4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_BASE +CYDEV_PHUB_TDMEM91_BASE EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM91_SIZE +CYDEV_PHUB_TDMEM91_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD0 +CYREG_PHUB_TDMEM91_ORIG_TD0 EQU 0x40007ad8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM91_ORIG_TD1 +CYREG_PHUB_TDMEM91_ORIG_TD1 EQU 0x40007adc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_BASE +CYDEV_PHUB_TDMEM92_BASE EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM92_SIZE +CYDEV_PHUB_TDMEM92_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD0 +CYREG_PHUB_TDMEM92_ORIG_TD0 EQU 0x40007ae0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM92_ORIG_TD1 +CYREG_PHUB_TDMEM92_ORIG_TD1 EQU 0x40007ae4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_BASE +CYDEV_PHUB_TDMEM93_BASE EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM93_SIZE +CYDEV_PHUB_TDMEM93_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD0 +CYREG_PHUB_TDMEM93_ORIG_TD0 EQU 0x40007ae8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM93_ORIG_TD1 +CYREG_PHUB_TDMEM93_ORIG_TD1 EQU 0x40007aec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_BASE +CYDEV_PHUB_TDMEM94_BASE EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM94_SIZE +CYDEV_PHUB_TDMEM94_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD0 +CYREG_PHUB_TDMEM94_ORIG_TD0 EQU 0x40007af0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM94_ORIG_TD1 +CYREG_PHUB_TDMEM94_ORIG_TD1 EQU 0x40007af4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_BASE +CYDEV_PHUB_TDMEM95_BASE EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM95_SIZE +CYDEV_PHUB_TDMEM95_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD0 +CYREG_PHUB_TDMEM95_ORIG_TD0 EQU 0x40007af8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM95_ORIG_TD1 +CYREG_PHUB_TDMEM95_ORIG_TD1 EQU 0x40007afc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_BASE +CYDEV_PHUB_TDMEM96_BASE EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM96_SIZE +CYDEV_PHUB_TDMEM96_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD0 +CYREG_PHUB_TDMEM96_ORIG_TD0 EQU 0x40007b00 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM96_ORIG_TD1 +CYREG_PHUB_TDMEM96_ORIG_TD1 EQU 0x40007b04 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_BASE +CYDEV_PHUB_TDMEM97_BASE EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM97_SIZE +CYDEV_PHUB_TDMEM97_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD0 +CYREG_PHUB_TDMEM97_ORIG_TD0 EQU 0x40007b08 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM97_ORIG_TD1 +CYREG_PHUB_TDMEM97_ORIG_TD1 EQU 0x40007b0c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_BASE +CYDEV_PHUB_TDMEM98_BASE EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM98_SIZE +CYDEV_PHUB_TDMEM98_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD0 +CYREG_PHUB_TDMEM98_ORIG_TD0 EQU 0x40007b10 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM98_ORIG_TD1 +CYREG_PHUB_TDMEM98_ORIG_TD1 EQU 0x40007b14 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_BASE +CYDEV_PHUB_TDMEM99_BASE EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM99_SIZE +CYDEV_PHUB_TDMEM99_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD0 +CYREG_PHUB_TDMEM99_ORIG_TD0 EQU 0x40007b18 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM99_ORIG_TD1 +CYREG_PHUB_TDMEM99_ORIG_TD1 EQU 0x40007b1c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_BASE +CYDEV_PHUB_TDMEM100_BASE EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM100_SIZE +CYDEV_PHUB_TDMEM100_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD0 +CYREG_PHUB_TDMEM100_ORIG_TD0 EQU 0x40007b20 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM100_ORIG_TD1 +CYREG_PHUB_TDMEM100_ORIG_TD1 EQU 0x40007b24 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_BASE +CYDEV_PHUB_TDMEM101_BASE EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM101_SIZE +CYDEV_PHUB_TDMEM101_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD0 +CYREG_PHUB_TDMEM101_ORIG_TD0 EQU 0x40007b28 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM101_ORIG_TD1 +CYREG_PHUB_TDMEM101_ORIG_TD1 EQU 0x40007b2c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_BASE +CYDEV_PHUB_TDMEM102_BASE EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM102_SIZE +CYDEV_PHUB_TDMEM102_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD0 +CYREG_PHUB_TDMEM102_ORIG_TD0 EQU 0x40007b30 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM102_ORIG_TD1 +CYREG_PHUB_TDMEM102_ORIG_TD1 EQU 0x40007b34 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_BASE +CYDEV_PHUB_TDMEM103_BASE EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM103_SIZE +CYDEV_PHUB_TDMEM103_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD0 +CYREG_PHUB_TDMEM103_ORIG_TD0 EQU 0x40007b38 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM103_ORIG_TD1 +CYREG_PHUB_TDMEM103_ORIG_TD1 EQU 0x40007b3c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_BASE +CYDEV_PHUB_TDMEM104_BASE EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM104_SIZE +CYDEV_PHUB_TDMEM104_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD0 +CYREG_PHUB_TDMEM104_ORIG_TD0 EQU 0x40007b40 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM104_ORIG_TD1 +CYREG_PHUB_TDMEM104_ORIG_TD1 EQU 0x40007b44 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_BASE +CYDEV_PHUB_TDMEM105_BASE EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM105_SIZE +CYDEV_PHUB_TDMEM105_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD0 +CYREG_PHUB_TDMEM105_ORIG_TD0 EQU 0x40007b48 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM105_ORIG_TD1 +CYREG_PHUB_TDMEM105_ORIG_TD1 EQU 0x40007b4c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_BASE +CYDEV_PHUB_TDMEM106_BASE EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM106_SIZE +CYDEV_PHUB_TDMEM106_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD0 +CYREG_PHUB_TDMEM106_ORIG_TD0 EQU 0x40007b50 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM106_ORIG_TD1 +CYREG_PHUB_TDMEM106_ORIG_TD1 EQU 0x40007b54 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_BASE +CYDEV_PHUB_TDMEM107_BASE EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM107_SIZE +CYDEV_PHUB_TDMEM107_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD0 +CYREG_PHUB_TDMEM107_ORIG_TD0 EQU 0x40007b58 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM107_ORIG_TD1 +CYREG_PHUB_TDMEM107_ORIG_TD1 EQU 0x40007b5c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_BASE +CYDEV_PHUB_TDMEM108_BASE EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM108_SIZE +CYDEV_PHUB_TDMEM108_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD0 +CYREG_PHUB_TDMEM108_ORIG_TD0 EQU 0x40007b60 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM108_ORIG_TD1 +CYREG_PHUB_TDMEM108_ORIG_TD1 EQU 0x40007b64 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_BASE +CYDEV_PHUB_TDMEM109_BASE EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM109_SIZE +CYDEV_PHUB_TDMEM109_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD0 +CYREG_PHUB_TDMEM109_ORIG_TD0 EQU 0x40007b68 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM109_ORIG_TD1 +CYREG_PHUB_TDMEM109_ORIG_TD1 EQU 0x40007b6c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_BASE +CYDEV_PHUB_TDMEM110_BASE EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM110_SIZE +CYDEV_PHUB_TDMEM110_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD0 +CYREG_PHUB_TDMEM110_ORIG_TD0 EQU 0x40007b70 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM110_ORIG_TD1 +CYREG_PHUB_TDMEM110_ORIG_TD1 EQU 0x40007b74 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_BASE +CYDEV_PHUB_TDMEM111_BASE EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM111_SIZE +CYDEV_PHUB_TDMEM111_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD0 +CYREG_PHUB_TDMEM111_ORIG_TD0 EQU 0x40007b78 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM111_ORIG_TD1 +CYREG_PHUB_TDMEM111_ORIG_TD1 EQU 0x40007b7c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_BASE +CYDEV_PHUB_TDMEM112_BASE EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM112_SIZE +CYDEV_PHUB_TDMEM112_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD0 +CYREG_PHUB_TDMEM112_ORIG_TD0 EQU 0x40007b80 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM112_ORIG_TD1 +CYREG_PHUB_TDMEM112_ORIG_TD1 EQU 0x40007b84 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_BASE +CYDEV_PHUB_TDMEM113_BASE EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM113_SIZE +CYDEV_PHUB_TDMEM113_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD0 +CYREG_PHUB_TDMEM113_ORIG_TD0 EQU 0x40007b88 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM113_ORIG_TD1 +CYREG_PHUB_TDMEM113_ORIG_TD1 EQU 0x40007b8c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_BASE +CYDEV_PHUB_TDMEM114_BASE EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM114_SIZE +CYDEV_PHUB_TDMEM114_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD0 +CYREG_PHUB_TDMEM114_ORIG_TD0 EQU 0x40007b90 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM114_ORIG_TD1 +CYREG_PHUB_TDMEM114_ORIG_TD1 EQU 0x40007b94 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_BASE +CYDEV_PHUB_TDMEM115_BASE EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM115_SIZE +CYDEV_PHUB_TDMEM115_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD0 +CYREG_PHUB_TDMEM115_ORIG_TD0 EQU 0x40007b98 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM115_ORIG_TD1 +CYREG_PHUB_TDMEM115_ORIG_TD1 EQU 0x40007b9c + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_BASE +CYDEV_PHUB_TDMEM116_BASE EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM116_SIZE +CYDEV_PHUB_TDMEM116_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD0 +CYREG_PHUB_TDMEM116_ORIG_TD0 EQU 0x40007ba0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM116_ORIG_TD1 +CYREG_PHUB_TDMEM116_ORIG_TD1 EQU 0x40007ba4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_BASE +CYDEV_PHUB_TDMEM117_BASE EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM117_SIZE +CYDEV_PHUB_TDMEM117_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD0 +CYREG_PHUB_TDMEM117_ORIG_TD0 EQU 0x40007ba8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM117_ORIG_TD1 +CYREG_PHUB_TDMEM117_ORIG_TD1 EQU 0x40007bac + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_BASE +CYDEV_PHUB_TDMEM118_BASE EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM118_SIZE +CYDEV_PHUB_TDMEM118_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD0 +CYREG_PHUB_TDMEM118_ORIG_TD0 EQU 0x40007bb0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM118_ORIG_TD1 +CYREG_PHUB_TDMEM118_ORIG_TD1 EQU 0x40007bb4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_BASE +CYDEV_PHUB_TDMEM119_BASE EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM119_SIZE +CYDEV_PHUB_TDMEM119_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD0 +CYREG_PHUB_TDMEM119_ORIG_TD0 EQU 0x40007bb8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM119_ORIG_TD1 +CYREG_PHUB_TDMEM119_ORIG_TD1 EQU 0x40007bbc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_BASE +CYDEV_PHUB_TDMEM120_BASE EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM120_SIZE +CYDEV_PHUB_TDMEM120_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD0 +CYREG_PHUB_TDMEM120_ORIG_TD0 EQU 0x40007bc0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM120_ORIG_TD1 +CYREG_PHUB_TDMEM120_ORIG_TD1 EQU 0x40007bc4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_BASE +CYDEV_PHUB_TDMEM121_BASE EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM121_SIZE +CYDEV_PHUB_TDMEM121_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD0 +CYREG_PHUB_TDMEM121_ORIG_TD0 EQU 0x40007bc8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM121_ORIG_TD1 +CYREG_PHUB_TDMEM121_ORIG_TD1 EQU 0x40007bcc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_BASE +CYDEV_PHUB_TDMEM122_BASE EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM122_SIZE +CYDEV_PHUB_TDMEM122_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD0 +CYREG_PHUB_TDMEM122_ORIG_TD0 EQU 0x40007bd0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM122_ORIG_TD1 +CYREG_PHUB_TDMEM122_ORIG_TD1 EQU 0x40007bd4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_BASE +CYDEV_PHUB_TDMEM123_BASE EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM123_SIZE +CYDEV_PHUB_TDMEM123_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD0 +CYREG_PHUB_TDMEM123_ORIG_TD0 EQU 0x40007bd8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM123_ORIG_TD1 +CYREG_PHUB_TDMEM123_ORIG_TD1 EQU 0x40007bdc + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_BASE +CYDEV_PHUB_TDMEM124_BASE EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM124_SIZE +CYDEV_PHUB_TDMEM124_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD0 +CYREG_PHUB_TDMEM124_ORIG_TD0 EQU 0x40007be0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM124_ORIG_TD1 +CYREG_PHUB_TDMEM124_ORIG_TD1 EQU 0x40007be4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_BASE +CYDEV_PHUB_TDMEM125_BASE EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM125_SIZE +CYDEV_PHUB_TDMEM125_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD0 +CYREG_PHUB_TDMEM125_ORIG_TD0 EQU 0x40007be8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM125_ORIG_TD1 +CYREG_PHUB_TDMEM125_ORIG_TD1 EQU 0x40007bec + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_BASE +CYDEV_PHUB_TDMEM126_BASE EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM126_SIZE +CYDEV_PHUB_TDMEM126_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD0 +CYREG_PHUB_TDMEM126_ORIG_TD0 EQU 0x40007bf0 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM126_ORIG_TD1 +CYREG_PHUB_TDMEM126_ORIG_TD1 EQU 0x40007bf4 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_BASE +CYDEV_PHUB_TDMEM127_BASE EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYDEV_PHUB_TDMEM127_SIZE +CYDEV_PHUB_TDMEM127_SIZE EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD0 +CYREG_PHUB_TDMEM127_ORIG_TD0 EQU 0x40007bf8 + ENDIF + IF :LNOT::DEF:CYREG_PHUB_TDMEM127_ORIG_TD1 +CYREG_PHUB_TDMEM127_ORIG_TD1 EQU 0x40007bfc + ENDIF + IF :LNOT::DEF:CYDEV_EE_BASE +CYDEV_EE_BASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYDEV_EE_SIZE +CYDEV_EE_SIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MBASE +CYREG_EE_DATA_MBASE EQU 0x40008000 + ENDIF + IF :LNOT::DEF:CYREG_EE_DATA_MSIZE +CYREG_EE_DATA_MSIZE EQU 0x00000800 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_BASE +CYDEV_CAN0_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_SIZE +CYDEV_CAN0_SIZE EQU 0x000002a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_BASE +CYDEV_CAN0_CSR_BASE EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_CSR_SIZE +CYDEV_CAN0_CSR_SIZE EQU 0x00000018 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_SR +CYREG_CAN0_CSR_INT_SR EQU 0x4000a000 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_INT_EN +CYREG_CAN0_CSR_INT_EN EQU 0x4000a004 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_BUF_SR +CYREG_CAN0_CSR_BUF_SR EQU 0x4000a008 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_ERR_SR +CYREG_CAN0_CSR_ERR_SR EQU 0x4000a00c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CMD +CYREG_CAN0_CSR_CMD EQU 0x4000a010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_CSR_CFG +CYREG_CAN0_CSR_CFG EQU 0x4000a014 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_BASE +CYDEV_CAN0_TX0_BASE EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX0_SIZE +CYDEV_CAN0_TX0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_CMD +CYREG_CAN0_TX0_CMD EQU 0x4000a020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_ID +CYREG_CAN0_TX0_ID EQU 0x4000a024 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DH +CYREG_CAN0_TX0_DH EQU 0x4000a028 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX0_DL +CYREG_CAN0_TX0_DL EQU 0x4000a02c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_BASE +CYDEV_CAN0_TX1_BASE EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX1_SIZE +CYDEV_CAN0_TX1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_CMD +CYREG_CAN0_TX1_CMD EQU 0x4000a030 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_ID +CYREG_CAN0_TX1_ID EQU 0x4000a034 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DH +CYREG_CAN0_TX1_DH EQU 0x4000a038 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX1_DL +CYREG_CAN0_TX1_DL EQU 0x4000a03c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_BASE +CYDEV_CAN0_TX2_BASE EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX2_SIZE +CYDEV_CAN0_TX2_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_CMD +CYREG_CAN0_TX2_CMD EQU 0x4000a040 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_ID +CYREG_CAN0_TX2_ID EQU 0x4000a044 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DH +CYREG_CAN0_TX2_DH EQU 0x4000a048 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX2_DL +CYREG_CAN0_TX2_DL EQU 0x4000a04c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_BASE +CYDEV_CAN0_TX3_BASE EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX3_SIZE +CYDEV_CAN0_TX3_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_CMD +CYREG_CAN0_TX3_CMD EQU 0x4000a050 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_ID +CYREG_CAN0_TX3_ID EQU 0x4000a054 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DH +CYREG_CAN0_TX3_DH EQU 0x4000a058 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX3_DL +CYREG_CAN0_TX3_DL EQU 0x4000a05c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_BASE +CYDEV_CAN0_TX4_BASE EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX4_SIZE +CYDEV_CAN0_TX4_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_CMD +CYREG_CAN0_TX4_CMD EQU 0x4000a060 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_ID +CYREG_CAN0_TX4_ID EQU 0x4000a064 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DH +CYREG_CAN0_TX4_DH EQU 0x4000a068 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX4_DL +CYREG_CAN0_TX4_DL EQU 0x4000a06c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_BASE +CYDEV_CAN0_TX5_BASE EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX5_SIZE +CYDEV_CAN0_TX5_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_CMD +CYREG_CAN0_TX5_CMD EQU 0x4000a070 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_ID +CYREG_CAN0_TX5_ID EQU 0x4000a074 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DH +CYREG_CAN0_TX5_DH EQU 0x4000a078 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX5_DL +CYREG_CAN0_TX5_DL EQU 0x4000a07c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_BASE +CYDEV_CAN0_TX6_BASE EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX6_SIZE +CYDEV_CAN0_TX6_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_CMD +CYREG_CAN0_TX6_CMD EQU 0x4000a080 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_ID +CYREG_CAN0_TX6_ID EQU 0x4000a084 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DH +CYREG_CAN0_TX6_DH EQU 0x4000a088 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX6_DL +CYREG_CAN0_TX6_DL EQU 0x4000a08c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_BASE +CYDEV_CAN0_TX7_BASE EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_TX7_SIZE +CYDEV_CAN0_TX7_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_CMD +CYREG_CAN0_TX7_CMD EQU 0x4000a090 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_ID +CYREG_CAN0_TX7_ID EQU 0x4000a094 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DH +CYREG_CAN0_TX7_DH EQU 0x4000a098 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_TX7_DL +CYREG_CAN0_TX7_DL EQU 0x4000a09c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_BASE +CYDEV_CAN0_RX0_BASE EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX0_SIZE +CYDEV_CAN0_RX0_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_CMD +CYREG_CAN0_RX0_CMD EQU 0x4000a0a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ID +CYREG_CAN0_RX0_ID EQU 0x4000a0a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DH +CYREG_CAN0_RX0_DH EQU 0x4000a0a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_DL +CYREG_CAN0_RX0_DL EQU 0x4000a0ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMR +CYREG_CAN0_RX0_AMR EQU 0x4000a0b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACR +CYREG_CAN0_RX0_ACR EQU 0x4000a0b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_AMRD +CYREG_CAN0_RX0_AMRD EQU 0x4000a0b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX0_ACRD +CYREG_CAN0_RX0_ACRD EQU 0x4000a0bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_BASE +CYDEV_CAN0_RX1_BASE EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX1_SIZE +CYDEV_CAN0_RX1_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_CMD +CYREG_CAN0_RX1_CMD EQU 0x4000a0c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ID +CYREG_CAN0_RX1_ID EQU 0x4000a0c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DH +CYREG_CAN0_RX1_DH EQU 0x4000a0c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_DL +CYREG_CAN0_RX1_DL EQU 0x4000a0cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMR +CYREG_CAN0_RX1_AMR EQU 0x4000a0d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACR +CYREG_CAN0_RX1_ACR EQU 0x4000a0d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_AMRD +CYREG_CAN0_RX1_AMRD EQU 0x4000a0d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX1_ACRD +CYREG_CAN0_RX1_ACRD EQU 0x4000a0dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_BASE +CYDEV_CAN0_RX2_BASE EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX2_SIZE +CYDEV_CAN0_RX2_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_CMD +CYREG_CAN0_RX2_CMD EQU 0x4000a0e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ID +CYREG_CAN0_RX2_ID EQU 0x4000a0e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DH +CYREG_CAN0_RX2_DH EQU 0x4000a0e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_DL +CYREG_CAN0_RX2_DL EQU 0x4000a0ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMR +CYREG_CAN0_RX2_AMR EQU 0x4000a0f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACR +CYREG_CAN0_RX2_ACR EQU 0x4000a0f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_AMRD +CYREG_CAN0_RX2_AMRD EQU 0x4000a0f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX2_ACRD +CYREG_CAN0_RX2_ACRD EQU 0x4000a0fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_BASE +CYDEV_CAN0_RX3_BASE EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX3_SIZE +CYDEV_CAN0_RX3_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_CMD +CYREG_CAN0_RX3_CMD EQU 0x4000a100 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ID +CYREG_CAN0_RX3_ID EQU 0x4000a104 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DH +CYREG_CAN0_RX3_DH EQU 0x4000a108 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_DL +CYREG_CAN0_RX3_DL EQU 0x4000a10c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMR +CYREG_CAN0_RX3_AMR EQU 0x4000a110 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACR +CYREG_CAN0_RX3_ACR EQU 0x4000a114 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_AMRD +CYREG_CAN0_RX3_AMRD EQU 0x4000a118 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX3_ACRD +CYREG_CAN0_RX3_ACRD EQU 0x4000a11c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_BASE +CYDEV_CAN0_RX4_BASE EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX4_SIZE +CYDEV_CAN0_RX4_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_CMD +CYREG_CAN0_RX4_CMD EQU 0x4000a120 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ID +CYREG_CAN0_RX4_ID EQU 0x4000a124 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DH +CYREG_CAN0_RX4_DH EQU 0x4000a128 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_DL +CYREG_CAN0_RX4_DL EQU 0x4000a12c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMR +CYREG_CAN0_RX4_AMR EQU 0x4000a130 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACR +CYREG_CAN0_RX4_ACR EQU 0x4000a134 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_AMRD +CYREG_CAN0_RX4_AMRD EQU 0x4000a138 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX4_ACRD +CYREG_CAN0_RX4_ACRD EQU 0x4000a13c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_BASE +CYDEV_CAN0_RX5_BASE EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX5_SIZE +CYDEV_CAN0_RX5_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_CMD +CYREG_CAN0_RX5_CMD EQU 0x4000a140 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ID +CYREG_CAN0_RX5_ID EQU 0x4000a144 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DH +CYREG_CAN0_RX5_DH EQU 0x4000a148 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_DL +CYREG_CAN0_RX5_DL EQU 0x4000a14c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMR +CYREG_CAN0_RX5_AMR EQU 0x4000a150 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACR +CYREG_CAN0_RX5_ACR EQU 0x4000a154 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_AMRD +CYREG_CAN0_RX5_AMRD EQU 0x4000a158 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX5_ACRD +CYREG_CAN0_RX5_ACRD EQU 0x4000a15c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_BASE +CYDEV_CAN0_RX6_BASE EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX6_SIZE +CYDEV_CAN0_RX6_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_CMD +CYREG_CAN0_RX6_CMD EQU 0x4000a160 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ID +CYREG_CAN0_RX6_ID EQU 0x4000a164 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DH +CYREG_CAN0_RX6_DH EQU 0x4000a168 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_DL +CYREG_CAN0_RX6_DL EQU 0x4000a16c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMR +CYREG_CAN0_RX6_AMR EQU 0x4000a170 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACR +CYREG_CAN0_RX6_ACR EQU 0x4000a174 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_AMRD +CYREG_CAN0_RX6_AMRD EQU 0x4000a178 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX6_ACRD +CYREG_CAN0_RX6_ACRD EQU 0x4000a17c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_BASE +CYDEV_CAN0_RX7_BASE EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX7_SIZE +CYDEV_CAN0_RX7_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_CMD +CYREG_CAN0_RX7_CMD EQU 0x4000a180 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ID +CYREG_CAN0_RX7_ID EQU 0x4000a184 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DH +CYREG_CAN0_RX7_DH EQU 0x4000a188 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_DL +CYREG_CAN0_RX7_DL EQU 0x4000a18c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMR +CYREG_CAN0_RX7_AMR EQU 0x4000a190 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACR +CYREG_CAN0_RX7_ACR EQU 0x4000a194 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_AMRD +CYREG_CAN0_RX7_AMRD EQU 0x4000a198 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX7_ACRD +CYREG_CAN0_RX7_ACRD EQU 0x4000a19c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_BASE +CYDEV_CAN0_RX8_BASE EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX8_SIZE +CYDEV_CAN0_RX8_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_CMD +CYREG_CAN0_RX8_CMD EQU 0x4000a1a0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ID +CYREG_CAN0_RX8_ID EQU 0x4000a1a4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DH +CYREG_CAN0_RX8_DH EQU 0x4000a1a8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_DL +CYREG_CAN0_RX8_DL EQU 0x4000a1ac + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMR +CYREG_CAN0_RX8_AMR EQU 0x4000a1b0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACR +CYREG_CAN0_RX8_ACR EQU 0x4000a1b4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_AMRD +CYREG_CAN0_RX8_AMRD EQU 0x4000a1b8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX8_ACRD +CYREG_CAN0_RX8_ACRD EQU 0x4000a1bc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_BASE +CYDEV_CAN0_RX9_BASE EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX9_SIZE +CYDEV_CAN0_RX9_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_CMD +CYREG_CAN0_RX9_CMD EQU 0x4000a1c0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ID +CYREG_CAN0_RX9_ID EQU 0x4000a1c4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DH +CYREG_CAN0_RX9_DH EQU 0x4000a1c8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_DL +CYREG_CAN0_RX9_DL EQU 0x4000a1cc + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMR +CYREG_CAN0_RX9_AMR EQU 0x4000a1d0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACR +CYREG_CAN0_RX9_ACR EQU 0x4000a1d4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_AMRD +CYREG_CAN0_RX9_AMRD EQU 0x4000a1d8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX9_ACRD +CYREG_CAN0_RX9_ACRD EQU 0x4000a1dc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_BASE +CYDEV_CAN0_RX10_BASE EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX10_SIZE +CYDEV_CAN0_RX10_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_CMD +CYREG_CAN0_RX10_CMD EQU 0x4000a1e0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ID +CYREG_CAN0_RX10_ID EQU 0x4000a1e4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DH +CYREG_CAN0_RX10_DH EQU 0x4000a1e8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_DL +CYREG_CAN0_RX10_DL EQU 0x4000a1ec + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMR +CYREG_CAN0_RX10_AMR EQU 0x4000a1f0 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACR +CYREG_CAN0_RX10_ACR EQU 0x4000a1f4 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_AMRD +CYREG_CAN0_RX10_AMRD EQU 0x4000a1f8 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX10_ACRD +CYREG_CAN0_RX10_ACRD EQU 0x4000a1fc + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_BASE +CYDEV_CAN0_RX11_BASE EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX11_SIZE +CYDEV_CAN0_RX11_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_CMD +CYREG_CAN0_RX11_CMD EQU 0x4000a200 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ID +CYREG_CAN0_RX11_ID EQU 0x4000a204 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DH +CYREG_CAN0_RX11_DH EQU 0x4000a208 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_DL +CYREG_CAN0_RX11_DL EQU 0x4000a20c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMR +CYREG_CAN0_RX11_AMR EQU 0x4000a210 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACR +CYREG_CAN0_RX11_ACR EQU 0x4000a214 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_AMRD +CYREG_CAN0_RX11_AMRD EQU 0x4000a218 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX11_ACRD +CYREG_CAN0_RX11_ACRD EQU 0x4000a21c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_BASE +CYDEV_CAN0_RX12_BASE EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX12_SIZE +CYDEV_CAN0_RX12_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_CMD +CYREG_CAN0_RX12_CMD EQU 0x4000a220 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ID +CYREG_CAN0_RX12_ID EQU 0x4000a224 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DH +CYREG_CAN0_RX12_DH EQU 0x4000a228 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_DL +CYREG_CAN0_RX12_DL EQU 0x4000a22c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMR +CYREG_CAN0_RX12_AMR EQU 0x4000a230 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACR +CYREG_CAN0_RX12_ACR EQU 0x4000a234 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_AMRD +CYREG_CAN0_RX12_AMRD EQU 0x4000a238 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX12_ACRD +CYREG_CAN0_RX12_ACRD EQU 0x4000a23c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_BASE +CYDEV_CAN0_RX13_BASE EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX13_SIZE +CYDEV_CAN0_RX13_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_CMD +CYREG_CAN0_RX13_CMD EQU 0x4000a240 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ID +CYREG_CAN0_RX13_ID EQU 0x4000a244 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DH +CYREG_CAN0_RX13_DH EQU 0x4000a248 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_DL +CYREG_CAN0_RX13_DL EQU 0x4000a24c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMR +CYREG_CAN0_RX13_AMR EQU 0x4000a250 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACR +CYREG_CAN0_RX13_ACR EQU 0x4000a254 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_AMRD +CYREG_CAN0_RX13_AMRD EQU 0x4000a258 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX13_ACRD +CYREG_CAN0_RX13_ACRD EQU 0x4000a25c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_BASE +CYDEV_CAN0_RX14_BASE EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX14_SIZE +CYDEV_CAN0_RX14_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_CMD +CYREG_CAN0_RX14_CMD EQU 0x4000a260 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ID +CYREG_CAN0_RX14_ID EQU 0x4000a264 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DH +CYREG_CAN0_RX14_DH EQU 0x4000a268 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_DL +CYREG_CAN0_RX14_DL EQU 0x4000a26c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMR +CYREG_CAN0_RX14_AMR EQU 0x4000a270 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACR +CYREG_CAN0_RX14_ACR EQU 0x4000a274 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_AMRD +CYREG_CAN0_RX14_AMRD EQU 0x4000a278 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX14_ACRD +CYREG_CAN0_RX14_ACRD EQU 0x4000a27c + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_BASE +CYDEV_CAN0_RX15_BASE EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYDEV_CAN0_RX15_SIZE +CYDEV_CAN0_RX15_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_CMD +CYREG_CAN0_RX15_CMD EQU 0x4000a280 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ID +CYREG_CAN0_RX15_ID EQU 0x4000a284 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DH +CYREG_CAN0_RX15_DH EQU 0x4000a288 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_DL +CYREG_CAN0_RX15_DL EQU 0x4000a28c + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMR +CYREG_CAN0_RX15_AMR EQU 0x4000a290 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACR +CYREG_CAN0_RX15_ACR EQU 0x4000a294 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_AMRD +CYREG_CAN0_RX15_AMRD EQU 0x4000a298 + ENDIF + IF :LNOT::DEF:CYREG_CAN0_RX15_ACRD +CYREG_CAN0_RX15_ACRD EQU 0x4000a29c + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_BASE +CYDEV_DFB0_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_SIZE +CYDEV_DFB0_SIZE EQU 0x000007b5 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_BASE +CYDEV_DFB0_DPA_SRAM_BASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPA_SRAM_SIZE +CYDEV_DFB0_DPA_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MBASE +CYREG_DFB0_DPA_SRAM_DATA_MBASE EQU 0x4000c000 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPA_SRAM_DATA_MSIZE +CYREG_DFB0_DPA_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_BASE +CYDEV_DFB0_DPB_SRAM_BASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_DPB_SRAM_SIZE +CYDEV_DFB0_DPB_SRAM_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MBASE +CYREG_DFB0_DPB_SRAM_DATA_MBASE EQU 0x4000c200 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DPB_SRAM_DATA_MSIZE +CYREG_DFB0_DPB_SRAM_DATA_MSIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_BASE +CYDEV_DFB0_CSA_SRAM_BASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSA_SRAM_SIZE +CYDEV_DFB0_CSA_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MBASE +CYREG_DFB0_CSA_SRAM_DATA_MBASE EQU 0x4000c400 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSA_SRAM_DATA_MSIZE +CYREG_DFB0_CSA_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_BASE +CYDEV_DFB0_CSB_SRAM_BASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_CSB_SRAM_SIZE +CYDEV_DFB0_CSB_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MBASE +CYREG_DFB0_CSB_SRAM_DATA_MBASE EQU 0x4000c500 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CSB_SRAM_DATA_MSIZE +CYREG_DFB0_CSB_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_BASE +CYDEV_DFB0_FSM_SRAM_BASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_FSM_SRAM_SIZE +CYDEV_DFB0_FSM_SRAM_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MBASE +CYREG_DFB0_FSM_SRAM_DATA_MBASE EQU 0x4000c600 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_FSM_SRAM_DATA_MSIZE +CYREG_DFB0_FSM_SRAM_DATA_MSIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_BASE +CYDEV_DFB0_ACU_SRAM_BASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYDEV_DFB0_ACU_SRAM_SIZE +CYDEV_DFB0_ACU_SRAM_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MBASE +CYREG_DFB0_ACU_SRAM_DATA_MBASE EQU 0x4000c700 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_ACU_SRAM_DATA_MSIZE +CYREG_DFB0_ACU_SRAM_DATA_MSIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_CR +CYREG_DFB0_CR EQU 0x4000c780 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SR +CYREG_DFB0_SR EQU 0x4000c784 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_EN +CYREG_DFB0_RAM_EN EQU 0x4000c788 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_RAM_DIR +CYREG_DFB0_RAM_DIR EQU 0x4000c78c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_SEMA +CYREG_DFB0_SEMA EQU 0x4000c790 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DSI_CTRL +CYREG_DFB0_DSI_CTRL EQU 0x4000c794 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_INT_CTRL +CYREG_DFB0_INT_CTRL EQU 0x4000c798 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DMA_CTRL +CYREG_DFB0_DMA_CTRL EQU 0x4000c79c + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEA +CYREG_DFB0_STAGEA EQU 0x4000c7a0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAM +CYREG_DFB0_STAGEAM EQU 0x4000c7a1 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEAH +CYREG_DFB0_STAGEAH EQU 0x4000c7a2 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEB +CYREG_DFB0_STAGEB EQU 0x4000c7a4 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBM +CYREG_DFB0_STAGEBM EQU 0x4000c7a5 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_STAGEBH +CYREG_DFB0_STAGEBH EQU 0x4000c7a6 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDA +CYREG_DFB0_HOLDA EQU 0x4000c7a8 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAM +CYREG_DFB0_HOLDAM EQU 0x4000c7a9 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAH +CYREG_DFB0_HOLDAH EQU 0x4000c7aa + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDAS +CYREG_DFB0_HOLDAS EQU 0x4000c7ab + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDB +CYREG_DFB0_HOLDB EQU 0x4000c7ac + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBM +CYREG_DFB0_HOLDBM EQU 0x4000c7ad + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBH +CYREG_DFB0_HOLDBH EQU 0x4000c7ae + ENDIF + IF :LNOT::DEF:CYREG_DFB0_HOLDBS +CYREG_DFB0_HOLDBS EQU 0x4000c7af + ENDIF + IF :LNOT::DEF:CYREG_DFB0_COHER +CYREG_DFB0_COHER EQU 0x4000c7b0 + ENDIF + IF :LNOT::DEF:CYREG_DFB0_DALIGN +CYREG_DFB0_DALIGN EQU 0x4000c7b4 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BASE +CYDEV_UCFG_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_SIZE +CYDEV_UCFG_SIZE EQU 0x00005040 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_BASE +CYDEV_UCFG_B0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_SIZE +CYDEV_UCFG_B0_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_BASE +CYDEV_UCFG_B0_P0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_SIZE +CYDEV_UCFG_B0_P0_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_BASE +CYDEV_UCFG_B0_P0_U0_BASE EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U0_SIZE +CYDEV_UCFG_B0_P0_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT0 +CYREG_B0_P0_U0_PLD_IT0 EQU 0x40010000 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT1 +CYREG_B0_P0_U0_PLD_IT1 EQU 0x40010004 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT2 +CYREG_B0_P0_U0_PLD_IT2 EQU 0x40010008 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT3 +CYREG_B0_P0_U0_PLD_IT3 EQU 0x4001000c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT4 +CYREG_B0_P0_U0_PLD_IT4 EQU 0x40010010 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT5 +CYREG_B0_P0_U0_PLD_IT5 EQU 0x40010014 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT6 +CYREG_B0_P0_U0_PLD_IT6 EQU 0x40010018 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT7 +CYREG_B0_P0_U0_PLD_IT7 EQU 0x4001001c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT8 +CYREG_B0_P0_U0_PLD_IT8 EQU 0x40010020 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT9 +CYREG_B0_P0_U0_PLD_IT9 EQU 0x40010024 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT10 +CYREG_B0_P0_U0_PLD_IT10 EQU 0x40010028 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_IT11 +CYREG_B0_P0_U0_PLD_IT11 EQU 0x4001002c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT0 +CYREG_B0_P0_U0_PLD_ORT0 EQU 0x40010030 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT1 +CYREG_B0_P0_U0_PLD_ORT1 EQU 0x40010032 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT2 +CYREG_B0_P0_U0_PLD_ORT2 EQU 0x40010034 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_PLD_ORT3 +CYREG_B0_P0_U0_PLD_ORT3 EQU 0x40010036 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_CEN_CONST +CYREG_B0_P0_U0_MC_CFG_CEN_CONST EQU 0x40010038 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_XORFB +CYREG_B0_P0_U0_MC_CFG_XORFB EQU 0x4001003a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_SET_RESET +CYREG_B0_P0_U0_MC_CFG_SET_RESET EQU 0x4001003c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_MC_CFG_BYPASS +CYREG_B0_P0_U0_MC_CFG_BYPASS EQU 0x4001003e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG0 +CYREG_B0_P0_U0_CFG0 EQU 0x40010040 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG1 +CYREG_B0_P0_U0_CFG1 EQU 0x40010041 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG2 +CYREG_B0_P0_U0_CFG2 EQU 0x40010042 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG3 +CYREG_B0_P0_U0_CFG3 EQU 0x40010043 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG4 +CYREG_B0_P0_U0_CFG4 EQU 0x40010044 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG5 +CYREG_B0_P0_U0_CFG5 EQU 0x40010045 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG6 +CYREG_B0_P0_U0_CFG6 EQU 0x40010046 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG7 +CYREG_B0_P0_U0_CFG7 EQU 0x40010047 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG8 +CYREG_B0_P0_U0_CFG8 EQU 0x40010048 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG9 +CYREG_B0_P0_U0_CFG9 EQU 0x40010049 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG10 +CYREG_B0_P0_U0_CFG10 EQU 0x4001004a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG11 +CYREG_B0_P0_U0_CFG11 EQU 0x4001004b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG12 +CYREG_B0_P0_U0_CFG12 EQU 0x4001004c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG13 +CYREG_B0_P0_U0_CFG13 EQU 0x4001004d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG14 +CYREG_B0_P0_U0_CFG14 EQU 0x4001004e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG15 +CYREG_B0_P0_U0_CFG15 EQU 0x4001004f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG16 +CYREG_B0_P0_U0_CFG16 EQU 0x40010050 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG17 +CYREG_B0_P0_U0_CFG17 EQU 0x40010051 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG18 +CYREG_B0_P0_U0_CFG18 EQU 0x40010052 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG19 +CYREG_B0_P0_U0_CFG19 EQU 0x40010053 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG20 +CYREG_B0_P0_U0_CFG20 EQU 0x40010054 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG21 +CYREG_B0_P0_U0_CFG21 EQU 0x40010055 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG22 +CYREG_B0_P0_U0_CFG22 EQU 0x40010056 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG23 +CYREG_B0_P0_U0_CFG23 EQU 0x40010057 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG24 +CYREG_B0_P0_U0_CFG24 EQU 0x40010058 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG25 +CYREG_B0_P0_U0_CFG25 EQU 0x40010059 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG26 +CYREG_B0_P0_U0_CFG26 EQU 0x4001005a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG27 +CYREG_B0_P0_U0_CFG27 EQU 0x4001005b + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG28 +CYREG_B0_P0_U0_CFG28 EQU 0x4001005c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG29 +CYREG_B0_P0_U0_CFG29 EQU 0x4001005d + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG30 +CYREG_B0_P0_U0_CFG30 EQU 0x4001005e + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_CFG31 +CYREG_B0_P0_U0_CFG31 EQU 0x4001005f + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG0 +CYREG_B0_P0_U0_DCFG0 EQU 0x40010060 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG1 +CYREG_B0_P0_U0_DCFG1 EQU 0x40010062 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG2 +CYREG_B0_P0_U0_DCFG2 EQU 0x40010064 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG3 +CYREG_B0_P0_U0_DCFG3 EQU 0x40010066 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG4 +CYREG_B0_P0_U0_DCFG4 EQU 0x40010068 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG5 +CYREG_B0_P0_U0_DCFG5 EQU 0x4001006a + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG6 +CYREG_B0_P0_U0_DCFG6 EQU 0x4001006c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U0_DCFG7 +CYREG_B0_P0_U0_DCFG7 EQU 0x4001006e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_BASE +CYDEV_UCFG_B0_P0_U1_BASE EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_U1_SIZE +CYDEV_UCFG_B0_P0_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT0 +CYREG_B0_P0_U1_PLD_IT0 EQU 0x40010080 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT1 +CYREG_B0_P0_U1_PLD_IT1 EQU 0x40010084 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT2 +CYREG_B0_P0_U1_PLD_IT2 EQU 0x40010088 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT3 +CYREG_B0_P0_U1_PLD_IT3 EQU 0x4001008c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT4 +CYREG_B0_P0_U1_PLD_IT4 EQU 0x40010090 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT5 +CYREG_B0_P0_U1_PLD_IT5 EQU 0x40010094 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT6 +CYREG_B0_P0_U1_PLD_IT6 EQU 0x40010098 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT7 +CYREG_B0_P0_U1_PLD_IT7 EQU 0x4001009c + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT8 +CYREG_B0_P0_U1_PLD_IT8 EQU 0x400100a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT9 +CYREG_B0_P0_U1_PLD_IT9 EQU 0x400100a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT10 +CYREG_B0_P0_U1_PLD_IT10 EQU 0x400100a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_IT11 +CYREG_B0_P0_U1_PLD_IT11 EQU 0x400100ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT0 +CYREG_B0_P0_U1_PLD_ORT0 EQU 0x400100b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT1 +CYREG_B0_P0_U1_PLD_ORT1 EQU 0x400100b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT2 +CYREG_B0_P0_U1_PLD_ORT2 EQU 0x400100b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_PLD_ORT3 +CYREG_B0_P0_U1_PLD_ORT3 EQU 0x400100b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_CEN_CONST +CYREG_B0_P0_U1_MC_CFG_CEN_CONST EQU 0x400100b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_XORFB +CYREG_B0_P0_U1_MC_CFG_XORFB EQU 0x400100ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_SET_RESET +CYREG_B0_P0_U1_MC_CFG_SET_RESET EQU 0x400100bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_MC_CFG_BYPASS +CYREG_B0_P0_U1_MC_CFG_BYPASS EQU 0x400100be + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG0 +CYREG_B0_P0_U1_CFG0 EQU 0x400100c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG1 +CYREG_B0_P0_U1_CFG1 EQU 0x400100c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG2 +CYREG_B0_P0_U1_CFG2 EQU 0x400100c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG3 +CYREG_B0_P0_U1_CFG3 EQU 0x400100c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG4 +CYREG_B0_P0_U1_CFG4 EQU 0x400100c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG5 +CYREG_B0_P0_U1_CFG5 EQU 0x400100c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG6 +CYREG_B0_P0_U1_CFG6 EQU 0x400100c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG7 +CYREG_B0_P0_U1_CFG7 EQU 0x400100c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG8 +CYREG_B0_P0_U1_CFG8 EQU 0x400100c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG9 +CYREG_B0_P0_U1_CFG9 EQU 0x400100c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG10 +CYREG_B0_P0_U1_CFG10 EQU 0x400100ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG11 +CYREG_B0_P0_U1_CFG11 EQU 0x400100cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG12 +CYREG_B0_P0_U1_CFG12 EQU 0x400100cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG13 +CYREG_B0_P0_U1_CFG13 EQU 0x400100cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG14 +CYREG_B0_P0_U1_CFG14 EQU 0x400100ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG15 +CYREG_B0_P0_U1_CFG15 EQU 0x400100cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG16 +CYREG_B0_P0_U1_CFG16 EQU 0x400100d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG17 +CYREG_B0_P0_U1_CFG17 EQU 0x400100d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG18 +CYREG_B0_P0_U1_CFG18 EQU 0x400100d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG19 +CYREG_B0_P0_U1_CFG19 EQU 0x400100d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG20 +CYREG_B0_P0_U1_CFG20 EQU 0x400100d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG21 +CYREG_B0_P0_U1_CFG21 EQU 0x400100d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG22 +CYREG_B0_P0_U1_CFG22 EQU 0x400100d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG23 +CYREG_B0_P0_U1_CFG23 EQU 0x400100d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG24 +CYREG_B0_P0_U1_CFG24 EQU 0x400100d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG25 +CYREG_B0_P0_U1_CFG25 EQU 0x400100d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG26 +CYREG_B0_P0_U1_CFG26 EQU 0x400100da + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG27 +CYREG_B0_P0_U1_CFG27 EQU 0x400100db + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG28 +CYREG_B0_P0_U1_CFG28 EQU 0x400100dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG29 +CYREG_B0_P0_U1_CFG29 EQU 0x400100dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG30 +CYREG_B0_P0_U1_CFG30 EQU 0x400100de + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_CFG31 +CYREG_B0_P0_U1_CFG31 EQU 0x400100df + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG0 +CYREG_B0_P0_U1_DCFG0 EQU 0x400100e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG1 +CYREG_B0_P0_U1_DCFG1 EQU 0x400100e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG2 +CYREG_B0_P0_U1_DCFG2 EQU 0x400100e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG3 +CYREG_B0_P0_U1_DCFG3 EQU 0x400100e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG4 +CYREG_B0_P0_U1_DCFG4 EQU 0x400100e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG5 +CYREG_B0_P0_U1_DCFG5 EQU 0x400100ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG6 +CYREG_B0_P0_U1_DCFG6 EQU 0x400100ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P0_U1_DCFG7 +CYREG_B0_P0_U1_DCFG7 EQU 0x400100ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_BASE +CYDEV_UCFG_B0_P0_ROUTE_BASE EQU 0x40010100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P0_ROUTE_SIZE +CYDEV_UCFG_B0_P0_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_BASE +CYDEV_UCFG_B0_P1_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_SIZE +CYDEV_UCFG_B0_P1_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_BASE +CYDEV_UCFG_B0_P1_U0_BASE EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U0_SIZE +CYDEV_UCFG_B0_P1_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT0 +CYREG_B0_P1_U0_PLD_IT0 EQU 0x40010200 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT1 +CYREG_B0_P1_U0_PLD_IT1 EQU 0x40010204 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT2 +CYREG_B0_P1_U0_PLD_IT2 EQU 0x40010208 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT3 +CYREG_B0_P1_U0_PLD_IT3 EQU 0x4001020c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT4 +CYREG_B0_P1_U0_PLD_IT4 EQU 0x40010210 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT5 +CYREG_B0_P1_U0_PLD_IT5 EQU 0x40010214 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT6 +CYREG_B0_P1_U0_PLD_IT6 EQU 0x40010218 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT7 +CYREG_B0_P1_U0_PLD_IT7 EQU 0x4001021c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT8 +CYREG_B0_P1_U0_PLD_IT8 EQU 0x40010220 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT9 +CYREG_B0_P1_U0_PLD_IT9 EQU 0x40010224 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT10 +CYREG_B0_P1_U0_PLD_IT10 EQU 0x40010228 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_IT11 +CYREG_B0_P1_U0_PLD_IT11 EQU 0x4001022c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT0 +CYREG_B0_P1_U0_PLD_ORT0 EQU 0x40010230 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT1 +CYREG_B0_P1_U0_PLD_ORT1 EQU 0x40010232 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT2 +CYREG_B0_P1_U0_PLD_ORT2 EQU 0x40010234 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_PLD_ORT3 +CYREG_B0_P1_U0_PLD_ORT3 EQU 0x40010236 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_CEN_CONST +CYREG_B0_P1_U0_MC_CFG_CEN_CONST EQU 0x40010238 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_XORFB +CYREG_B0_P1_U0_MC_CFG_XORFB EQU 0x4001023a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_SET_RESET +CYREG_B0_P1_U0_MC_CFG_SET_RESET EQU 0x4001023c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_MC_CFG_BYPASS +CYREG_B0_P1_U0_MC_CFG_BYPASS EQU 0x4001023e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG0 +CYREG_B0_P1_U0_CFG0 EQU 0x40010240 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG1 +CYREG_B0_P1_U0_CFG1 EQU 0x40010241 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG2 +CYREG_B0_P1_U0_CFG2 EQU 0x40010242 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG3 +CYREG_B0_P1_U0_CFG3 EQU 0x40010243 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG4 +CYREG_B0_P1_U0_CFG4 EQU 0x40010244 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG5 +CYREG_B0_P1_U0_CFG5 EQU 0x40010245 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG6 +CYREG_B0_P1_U0_CFG6 EQU 0x40010246 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG7 +CYREG_B0_P1_U0_CFG7 EQU 0x40010247 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG8 +CYREG_B0_P1_U0_CFG8 EQU 0x40010248 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG9 +CYREG_B0_P1_U0_CFG9 EQU 0x40010249 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG10 +CYREG_B0_P1_U0_CFG10 EQU 0x4001024a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG11 +CYREG_B0_P1_U0_CFG11 EQU 0x4001024b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG12 +CYREG_B0_P1_U0_CFG12 EQU 0x4001024c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG13 +CYREG_B0_P1_U0_CFG13 EQU 0x4001024d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG14 +CYREG_B0_P1_U0_CFG14 EQU 0x4001024e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG15 +CYREG_B0_P1_U0_CFG15 EQU 0x4001024f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG16 +CYREG_B0_P1_U0_CFG16 EQU 0x40010250 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG17 +CYREG_B0_P1_U0_CFG17 EQU 0x40010251 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG18 +CYREG_B0_P1_U0_CFG18 EQU 0x40010252 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG19 +CYREG_B0_P1_U0_CFG19 EQU 0x40010253 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG20 +CYREG_B0_P1_U0_CFG20 EQU 0x40010254 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG21 +CYREG_B0_P1_U0_CFG21 EQU 0x40010255 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG22 +CYREG_B0_P1_U0_CFG22 EQU 0x40010256 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG23 +CYREG_B0_P1_U0_CFG23 EQU 0x40010257 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG24 +CYREG_B0_P1_U0_CFG24 EQU 0x40010258 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG25 +CYREG_B0_P1_U0_CFG25 EQU 0x40010259 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG26 +CYREG_B0_P1_U0_CFG26 EQU 0x4001025a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG27 +CYREG_B0_P1_U0_CFG27 EQU 0x4001025b + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG28 +CYREG_B0_P1_U0_CFG28 EQU 0x4001025c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG29 +CYREG_B0_P1_U0_CFG29 EQU 0x4001025d + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG30 +CYREG_B0_P1_U0_CFG30 EQU 0x4001025e + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_CFG31 +CYREG_B0_P1_U0_CFG31 EQU 0x4001025f + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG0 +CYREG_B0_P1_U0_DCFG0 EQU 0x40010260 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG1 +CYREG_B0_P1_U0_DCFG1 EQU 0x40010262 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG2 +CYREG_B0_P1_U0_DCFG2 EQU 0x40010264 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG3 +CYREG_B0_P1_U0_DCFG3 EQU 0x40010266 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG4 +CYREG_B0_P1_U0_DCFG4 EQU 0x40010268 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG5 +CYREG_B0_P1_U0_DCFG5 EQU 0x4001026a + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG6 +CYREG_B0_P1_U0_DCFG6 EQU 0x4001026c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U0_DCFG7 +CYREG_B0_P1_U0_DCFG7 EQU 0x4001026e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_BASE +CYDEV_UCFG_B0_P1_U1_BASE EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_U1_SIZE +CYDEV_UCFG_B0_P1_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT0 +CYREG_B0_P1_U1_PLD_IT0 EQU 0x40010280 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT1 +CYREG_B0_P1_U1_PLD_IT1 EQU 0x40010284 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT2 +CYREG_B0_P1_U1_PLD_IT2 EQU 0x40010288 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT3 +CYREG_B0_P1_U1_PLD_IT3 EQU 0x4001028c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT4 +CYREG_B0_P1_U1_PLD_IT4 EQU 0x40010290 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT5 +CYREG_B0_P1_U1_PLD_IT5 EQU 0x40010294 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT6 +CYREG_B0_P1_U1_PLD_IT6 EQU 0x40010298 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT7 +CYREG_B0_P1_U1_PLD_IT7 EQU 0x4001029c + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT8 +CYREG_B0_P1_U1_PLD_IT8 EQU 0x400102a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT9 +CYREG_B0_P1_U1_PLD_IT9 EQU 0x400102a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT10 +CYREG_B0_P1_U1_PLD_IT10 EQU 0x400102a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_IT11 +CYREG_B0_P1_U1_PLD_IT11 EQU 0x400102ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT0 +CYREG_B0_P1_U1_PLD_ORT0 EQU 0x400102b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT1 +CYREG_B0_P1_U1_PLD_ORT1 EQU 0x400102b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT2 +CYREG_B0_P1_U1_PLD_ORT2 EQU 0x400102b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_PLD_ORT3 +CYREG_B0_P1_U1_PLD_ORT3 EQU 0x400102b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_CEN_CONST +CYREG_B0_P1_U1_MC_CFG_CEN_CONST EQU 0x400102b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_XORFB +CYREG_B0_P1_U1_MC_CFG_XORFB EQU 0x400102ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_SET_RESET +CYREG_B0_P1_U1_MC_CFG_SET_RESET EQU 0x400102bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_MC_CFG_BYPASS +CYREG_B0_P1_U1_MC_CFG_BYPASS EQU 0x400102be + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG0 +CYREG_B0_P1_U1_CFG0 EQU 0x400102c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG1 +CYREG_B0_P1_U1_CFG1 EQU 0x400102c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG2 +CYREG_B0_P1_U1_CFG2 EQU 0x400102c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG3 +CYREG_B0_P1_U1_CFG3 EQU 0x400102c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG4 +CYREG_B0_P1_U1_CFG4 EQU 0x400102c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG5 +CYREG_B0_P1_U1_CFG5 EQU 0x400102c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG6 +CYREG_B0_P1_U1_CFG6 EQU 0x400102c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG7 +CYREG_B0_P1_U1_CFG7 EQU 0x400102c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG8 +CYREG_B0_P1_U1_CFG8 EQU 0x400102c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG9 +CYREG_B0_P1_U1_CFG9 EQU 0x400102c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG10 +CYREG_B0_P1_U1_CFG10 EQU 0x400102ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG11 +CYREG_B0_P1_U1_CFG11 EQU 0x400102cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG12 +CYREG_B0_P1_U1_CFG12 EQU 0x400102cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG13 +CYREG_B0_P1_U1_CFG13 EQU 0x400102cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG14 +CYREG_B0_P1_U1_CFG14 EQU 0x400102ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG15 +CYREG_B0_P1_U1_CFG15 EQU 0x400102cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG16 +CYREG_B0_P1_U1_CFG16 EQU 0x400102d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG17 +CYREG_B0_P1_U1_CFG17 EQU 0x400102d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG18 +CYREG_B0_P1_U1_CFG18 EQU 0x400102d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG19 +CYREG_B0_P1_U1_CFG19 EQU 0x400102d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG20 +CYREG_B0_P1_U1_CFG20 EQU 0x400102d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG21 +CYREG_B0_P1_U1_CFG21 EQU 0x400102d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG22 +CYREG_B0_P1_U1_CFG22 EQU 0x400102d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG23 +CYREG_B0_P1_U1_CFG23 EQU 0x400102d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG24 +CYREG_B0_P1_U1_CFG24 EQU 0x400102d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG25 +CYREG_B0_P1_U1_CFG25 EQU 0x400102d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG26 +CYREG_B0_P1_U1_CFG26 EQU 0x400102da + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG27 +CYREG_B0_P1_U1_CFG27 EQU 0x400102db + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG28 +CYREG_B0_P1_U1_CFG28 EQU 0x400102dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG29 +CYREG_B0_P1_U1_CFG29 EQU 0x400102dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG30 +CYREG_B0_P1_U1_CFG30 EQU 0x400102de + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_CFG31 +CYREG_B0_P1_U1_CFG31 EQU 0x400102df + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG0 +CYREG_B0_P1_U1_DCFG0 EQU 0x400102e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG1 +CYREG_B0_P1_U1_DCFG1 EQU 0x400102e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG2 +CYREG_B0_P1_U1_DCFG2 EQU 0x400102e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG3 +CYREG_B0_P1_U1_DCFG3 EQU 0x400102e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG4 +CYREG_B0_P1_U1_DCFG4 EQU 0x400102e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG5 +CYREG_B0_P1_U1_DCFG5 EQU 0x400102ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG6 +CYREG_B0_P1_U1_DCFG6 EQU 0x400102ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P1_U1_DCFG7 +CYREG_B0_P1_U1_DCFG7 EQU 0x400102ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_BASE +CYDEV_UCFG_B0_P1_ROUTE_BASE EQU 0x40010300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P1_ROUTE_SIZE +CYDEV_UCFG_B0_P1_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_BASE +CYDEV_UCFG_B0_P2_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_SIZE +CYDEV_UCFG_B0_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_BASE +CYDEV_UCFG_B0_P2_U0_BASE EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U0_SIZE +CYDEV_UCFG_B0_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT0 +CYREG_B0_P2_U0_PLD_IT0 EQU 0x40010400 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT1 +CYREG_B0_P2_U0_PLD_IT1 EQU 0x40010404 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT2 +CYREG_B0_P2_U0_PLD_IT2 EQU 0x40010408 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT3 +CYREG_B0_P2_U0_PLD_IT3 EQU 0x4001040c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT4 +CYREG_B0_P2_U0_PLD_IT4 EQU 0x40010410 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT5 +CYREG_B0_P2_U0_PLD_IT5 EQU 0x40010414 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT6 +CYREG_B0_P2_U0_PLD_IT6 EQU 0x40010418 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT7 +CYREG_B0_P2_U0_PLD_IT7 EQU 0x4001041c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT8 +CYREG_B0_P2_U0_PLD_IT8 EQU 0x40010420 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT9 +CYREG_B0_P2_U0_PLD_IT9 EQU 0x40010424 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT10 +CYREG_B0_P2_U0_PLD_IT10 EQU 0x40010428 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_IT11 +CYREG_B0_P2_U0_PLD_IT11 EQU 0x4001042c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT0 +CYREG_B0_P2_U0_PLD_ORT0 EQU 0x40010430 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT1 +CYREG_B0_P2_U0_PLD_ORT1 EQU 0x40010432 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT2 +CYREG_B0_P2_U0_PLD_ORT2 EQU 0x40010434 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_PLD_ORT3 +CYREG_B0_P2_U0_PLD_ORT3 EQU 0x40010436 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_CEN_CONST +CYREG_B0_P2_U0_MC_CFG_CEN_CONST EQU 0x40010438 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_XORFB +CYREG_B0_P2_U0_MC_CFG_XORFB EQU 0x4001043a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_SET_RESET +CYREG_B0_P2_U0_MC_CFG_SET_RESET EQU 0x4001043c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_MC_CFG_BYPASS +CYREG_B0_P2_U0_MC_CFG_BYPASS EQU 0x4001043e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG0 +CYREG_B0_P2_U0_CFG0 EQU 0x40010440 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG1 +CYREG_B0_P2_U0_CFG1 EQU 0x40010441 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG2 +CYREG_B0_P2_U0_CFG2 EQU 0x40010442 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG3 +CYREG_B0_P2_U0_CFG3 EQU 0x40010443 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG4 +CYREG_B0_P2_U0_CFG4 EQU 0x40010444 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG5 +CYREG_B0_P2_U0_CFG5 EQU 0x40010445 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG6 +CYREG_B0_P2_U0_CFG6 EQU 0x40010446 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG7 +CYREG_B0_P2_U0_CFG7 EQU 0x40010447 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG8 +CYREG_B0_P2_U0_CFG8 EQU 0x40010448 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG9 +CYREG_B0_P2_U0_CFG9 EQU 0x40010449 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG10 +CYREG_B0_P2_U0_CFG10 EQU 0x4001044a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG11 +CYREG_B0_P2_U0_CFG11 EQU 0x4001044b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG12 +CYREG_B0_P2_U0_CFG12 EQU 0x4001044c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG13 +CYREG_B0_P2_U0_CFG13 EQU 0x4001044d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG14 +CYREG_B0_P2_U0_CFG14 EQU 0x4001044e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG15 +CYREG_B0_P2_U0_CFG15 EQU 0x4001044f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG16 +CYREG_B0_P2_U0_CFG16 EQU 0x40010450 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG17 +CYREG_B0_P2_U0_CFG17 EQU 0x40010451 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG18 +CYREG_B0_P2_U0_CFG18 EQU 0x40010452 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG19 +CYREG_B0_P2_U0_CFG19 EQU 0x40010453 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG20 +CYREG_B0_P2_U0_CFG20 EQU 0x40010454 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG21 +CYREG_B0_P2_U0_CFG21 EQU 0x40010455 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG22 +CYREG_B0_P2_U0_CFG22 EQU 0x40010456 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG23 +CYREG_B0_P2_U0_CFG23 EQU 0x40010457 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG24 +CYREG_B0_P2_U0_CFG24 EQU 0x40010458 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG25 +CYREG_B0_P2_U0_CFG25 EQU 0x40010459 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG26 +CYREG_B0_P2_U0_CFG26 EQU 0x4001045a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG27 +CYREG_B0_P2_U0_CFG27 EQU 0x4001045b + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG28 +CYREG_B0_P2_U0_CFG28 EQU 0x4001045c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG29 +CYREG_B0_P2_U0_CFG29 EQU 0x4001045d + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG30 +CYREG_B0_P2_U0_CFG30 EQU 0x4001045e + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_CFG31 +CYREG_B0_P2_U0_CFG31 EQU 0x4001045f + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG0 +CYREG_B0_P2_U0_DCFG0 EQU 0x40010460 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG1 +CYREG_B0_P2_U0_DCFG1 EQU 0x40010462 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG2 +CYREG_B0_P2_U0_DCFG2 EQU 0x40010464 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG3 +CYREG_B0_P2_U0_DCFG3 EQU 0x40010466 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG4 +CYREG_B0_P2_U0_DCFG4 EQU 0x40010468 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG5 +CYREG_B0_P2_U0_DCFG5 EQU 0x4001046a + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG6 +CYREG_B0_P2_U0_DCFG6 EQU 0x4001046c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U0_DCFG7 +CYREG_B0_P2_U0_DCFG7 EQU 0x4001046e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_BASE +CYDEV_UCFG_B0_P2_U1_BASE EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_U1_SIZE +CYDEV_UCFG_B0_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT0 +CYREG_B0_P2_U1_PLD_IT0 EQU 0x40010480 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT1 +CYREG_B0_P2_U1_PLD_IT1 EQU 0x40010484 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT2 +CYREG_B0_P2_U1_PLD_IT2 EQU 0x40010488 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT3 +CYREG_B0_P2_U1_PLD_IT3 EQU 0x4001048c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT4 +CYREG_B0_P2_U1_PLD_IT4 EQU 0x40010490 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT5 +CYREG_B0_P2_U1_PLD_IT5 EQU 0x40010494 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT6 +CYREG_B0_P2_U1_PLD_IT6 EQU 0x40010498 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT7 +CYREG_B0_P2_U1_PLD_IT7 EQU 0x4001049c + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT8 +CYREG_B0_P2_U1_PLD_IT8 EQU 0x400104a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT9 +CYREG_B0_P2_U1_PLD_IT9 EQU 0x400104a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT10 +CYREG_B0_P2_U1_PLD_IT10 EQU 0x400104a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_IT11 +CYREG_B0_P2_U1_PLD_IT11 EQU 0x400104ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT0 +CYREG_B0_P2_U1_PLD_ORT0 EQU 0x400104b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT1 +CYREG_B0_P2_U1_PLD_ORT1 EQU 0x400104b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT2 +CYREG_B0_P2_U1_PLD_ORT2 EQU 0x400104b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_PLD_ORT3 +CYREG_B0_P2_U1_PLD_ORT3 EQU 0x400104b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_CEN_CONST +CYREG_B0_P2_U1_MC_CFG_CEN_CONST EQU 0x400104b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_XORFB +CYREG_B0_P2_U1_MC_CFG_XORFB EQU 0x400104ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_SET_RESET +CYREG_B0_P2_U1_MC_CFG_SET_RESET EQU 0x400104bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_MC_CFG_BYPASS +CYREG_B0_P2_U1_MC_CFG_BYPASS EQU 0x400104be + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG0 +CYREG_B0_P2_U1_CFG0 EQU 0x400104c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG1 +CYREG_B0_P2_U1_CFG1 EQU 0x400104c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG2 +CYREG_B0_P2_U1_CFG2 EQU 0x400104c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG3 +CYREG_B0_P2_U1_CFG3 EQU 0x400104c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG4 +CYREG_B0_P2_U1_CFG4 EQU 0x400104c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG5 +CYREG_B0_P2_U1_CFG5 EQU 0x400104c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG6 +CYREG_B0_P2_U1_CFG6 EQU 0x400104c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG7 +CYREG_B0_P2_U1_CFG7 EQU 0x400104c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG8 +CYREG_B0_P2_U1_CFG8 EQU 0x400104c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG9 +CYREG_B0_P2_U1_CFG9 EQU 0x400104c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG10 +CYREG_B0_P2_U1_CFG10 EQU 0x400104ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG11 +CYREG_B0_P2_U1_CFG11 EQU 0x400104cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG12 +CYREG_B0_P2_U1_CFG12 EQU 0x400104cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG13 +CYREG_B0_P2_U1_CFG13 EQU 0x400104cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG14 +CYREG_B0_P2_U1_CFG14 EQU 0x400104ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG15 +CYREG_B0_P2_U1_CFG15 EQU 0x400104cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG16 +CYREG_B0_P2_U1_CFG16 EQU 0x400104d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG17 +CYREG_B0_P2_U1_CFG17 EQU 0x400104d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG18 +CYREG_B0_P2_U1_CFG18 EQU 0x400104d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG19 +CYREG_B0_P2_U1_CFG19 EQU 0x400104d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG20 +CYREG_B0_P2_U1_CFG20 EQU 0x400104d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG21 +CYREG_B0_P2_U1_CFG21 EQU 0x400104d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG22 +CYREG_B0_P2_U1_CFG22 EQU 0x400104d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG23 +CYREG_B0_P2_U1_CFG23 EQU 0x400104d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG24 +CYREG_B0_P2_U1_CFG24 EQU 0x400104d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG25 +CYREG_B0_P2_U1_CFG25 EQU 0x400104d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG26 +CYREG_B0_P2_U1_CFG26 EQU 0x400104da + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG27 +CYREG_B0_P2_U1_CFG27 EQU 0x400104db + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG28 +CYREG_B0_P2_U1_CFG28 EQU 0x400104dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG29 +CYREG_B0_P2_U1_CFG29 EQU 0x400104dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG30 +CYREG_B0_P2_U1_CFG30 EQU 0x400104de + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_CFG31 +CYREG_B0_P2_U1_CFG31 EQU 0x400104df + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG0 +CYREG_B0_P2_U1_DCFG0 EQU 0x400104e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG1 +CYREG_B0_P2_U1_DCFG1 EQU 0x400104e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG2 +CYREG_B0_P2_U1_DCFG2 EQU 0x400104e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG3 +CYREG_B0_P2_U1_DCFG3 EQU 0x400104e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG4 +CYREG_B0_P2_U1_DCFG4 EQU 0x400104e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG5 +CYREG_B0_P2_U1_DCFG5 EQU 0x400104ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG6 +CYREG_B0_P2_U1_DCFG6 EQU 0x400104ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P2_U1_DCFG7 +CYREG_B0_P2_U1_DCFG7 EQU 0x400104ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_BASE +CYDEV_UCFG_B0_P2_ROUTE_BASE EQU 0x40010500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P2_ROUTE_SIZE +CYDEV_UCFG_B0_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_BASE +CYDEV_UCFG_B0_P3_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_SIZE +CYDEV_UCFG_B0_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_BASE +CYDEV_UCFG_B0_P3_U0_BASE EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U0_SIZE +CYDEV_UCFG_B0_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT0 +CYREG_B0_P3_U0_PLD_IT0 EQU 0x40010600 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT1 +CYREG_B0_P3_U0_PLD_IT1 EQU 0x40010604 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT2 +CYREG_B0_P3_U0_PLD_IT2 EQU 0x40010608 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT3 +CYREG_B0_P3_U0_PLD_IT3 EQU 0x4001060c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT4 +CYREG_B0_P3_U0_PLD_IT4 EQU 0x40010610 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT5 +CYREG_B0_P3_U0_PLD_IT5 EQU 0x40010614 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT6 +CYREG_B0_P3_U0_PLD_IT6 EQU 0x40010618 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT7 +CYREG_B0_P3_U0_PLD_IT7 EQU 0x4001061c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT8 +CYREG_B0_P3_U0_PLD_IT8 EQU 0x40010620 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT9 +CYREG_B0_P3_U0_PLD_IT9 EQU 0x40010624 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT10 +CYREG_B0_P3_U0_PLD_IT10 EQU 0x40010628 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_IT11 +CYREG_B0_P3_U0_PLD_IT11 EQU 0x4001062c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT0 +CYREG_B0_P3_U0_PLD_ORT0 EQU 0x40010630 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT1 +CYREG_B0_P3_U0_PLD_ORT1 EQU 0x40010632 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT2 +CYREG_B0_P3_U0_PLD_ORT2 EQU 0x40010634 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_PLD_ORT3 +CYREG_B0_P3_U0_PLD_ORT3 EQU 0x40010636 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_CEN_CONST +CYREG_B0_P3_U0_MC_CFG_CEN_CONST EQU 0x40010638 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_XORFB +CYREG_B0_P3_U0_MC_CFG_XORFB EQU 0x4001063a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_SET_RESET +CYREG_B0_P3_U0_MC_CFG_SET_RESET EQU 0x4001063c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_MC_CFG_BYPASS +CYREG_B0_P3_U0_MC_CFG_BYPASS EQU 0x4001063e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG0 +CYREG_B0_P3_U0_CFG0 EQU 0x40010640 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG1 +CYREG_B0_P3_U0_CFG1 EQU 0x40010641 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG2 +CYREG_B0_P3_U0_CFG2 EQU 0x40010642 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG3 +CYREG_B0_P3_U0_CFG3 EQU 0x40010643 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG4 +CYREG_B0_P3_U0_CFG4 EQU 0x40010644 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG5 +CYREG_B0_P3_U0_CFG5 EQU 0x40010645 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG6 +CYREG_B0_P3_U0_CFG6 EQU 0x40010646 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG7 +CYREG_B0_P3_U0_CFG7 EQU 0x40010647 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG8 +CYREG_B0_P3_U0_CFG8 EQU 0x40010648 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG9 +CYREG_B0_P3_U0_CFG9 EQU 0x40010649 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG10 +CYREG_B0_P3_U0_CFG10 EQU 0x4001064a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG11 +CYREG_B0_P3_U0_CFG11 EQU 0x4001064b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG12 +CYREG_B0_P3_U0_CFG12 EQU 0x4001064c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG13 +CYREG_B0_P3_U0_CFG13 EQU 0x4001064d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG14 +CYREG_B0_P3_U0_CFG14 EQU 0x4001064e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG15 +CYREG_B0_P3_U0_CFG15 EQU 0x4001064f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG16 +CYREG_B0_P3_U0_CFG16 EQU 0x40010650 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG17 +CYREG_B0_P3_U0_CFG17 EQU 0x40010651 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG18 +CYREG_B0_P3_U0_CFG18 EQU 0x40010652 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG19 +CYREG_B0_P3_U0_CFG19 EQU 0x40010653 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG20 +CYREG_B0_P3_U0_CFG20 EQU 0x40010654 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG21 +CYREG_B0_P3_U0_CFG21 EQU 0x40010655 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG22 +CYREG_B0_P3_U0_CFG22 EQU 0x40010656 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG23 +CYREG_B0_P3_U0_CFG23 EQU 0x40010657 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG24 +CYREG_B0_P3_U0_CFG24 EQU 0x40010658 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG25 +CYREG_B0_P3_U0_CFG25 EQU 0x40010659 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG26 +CYREG_B0_P3_U0_CFG26 EQU 0x4001065a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG27 +CYREG_B0_P3_U0_CFG27 EQU 0x4001065b + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG28 +CYREG_B0_P3_U0_CFG28 EQU 0x4001065c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG29 +CYREG_B0_P3_U0_CFG29 EQU 0x4001065d + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG30 +CYREG_B0_P3_U0_CFG30 EQU 0x4001065e + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_CFG31 +CYREG_B0_P3_U0_CFG31 EQU 0x4001065f + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG0 +CYREG_B0_P3_U0_DCFG0 EQU 0x40010660 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG1 +CYREG_B0_P3_U0_DCFG1 EQU 0x40010662 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG2 +CYREG_B0_P3_U0_DCFG2 EQU 0x40010664 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG3 +CYREG_B0_P3_U0_DCFG3 EQU 0x40010666 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG4 +CYREG_B0_P3_U0_DCFG4 EQU 0x40010668 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG5 +CYREG_B0_P3_U0_DCFG5 EQU 0x4001066a + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG6 +CYREG_B0_P3_U0_DCFG6 EQU 0x4001066c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U0_DCFG7 +CYREG_B0_P3_U0_DCFG7 EQU 0x4001066e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_BASE +CYDEV_UCFG_B0_P3_U1_BASE EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_U1_SIZE +CYDEV_UCFG_B0_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT0 +CYREG_B0_P3_U1_PLD_IT0 EQU 0x40010680 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT1 +CYREG_B0_P3_U1_PLD_IT1 EQU 0x40010684 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT2 +CYREG_B0_P3_U1_PLD_IT2 EQU 0x40010688 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT3 +CYREG_B0_P3_U1_PLD_IT3 EQU 0x4001068c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT4 +CYREG_B0_P3_U1_PLD_IT4 EQU 0x40010690 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT5 +CYREG_B0_P3_U1_PLD_IT5 EQU 0x40010694 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT6 +CYREG_B0_P3_U1_PLD_IT6 EQU 0x40010698 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT7 +CYREG_B0_P3_U1_PLD_IT7 EQU 0x4001069c + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT8 +CYREG_B0_P3_U1_PLD_IT8 EQU 0x400106a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT9 +CYREG_B0_P3_U1_PLD_IT9 EQU 0x400106a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT10 +CYREG_B0_P3_U1_PLD_IT10 EQU 0x400106a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_IT11 +CYREG_B0_P3_U1_PLD_IT11 EQU 0x400106ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT0 +CYREG_B0_P3_U1_PLD_ORT0 EQU 0x400106b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT1 +CYREG_B0_P3_U1_PLD_ORT1 EQU 0x400106b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT2 +CYREG_B0_P3_U1_PLD_ORT2 EQU 0x400106b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_PLD_ORT3 +CYREG_B0_P3_U1_PLD_ORT3 EQU 0x400106b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_CEN_CONST +CYREG_B0_P3_U1_MC_CFG_CEN_CONST EQU 0x400106b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_XORFB +CYREG_B0_P3_U1_MC_CFG_XORFB EQU 0x400106ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_SET_RESET +CYREG_B0_P3_U1_MC_CFG_SET_RESET EQU 0x400106bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_MC_CFG_BYPASS +CYREG_B0_P3_U1_MC_CFG_BYPASS EQU 0x400106be + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG0 +CYREG_B0_P3_U1_CFG0 EQU 0x400106c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG1 +CYREG_B0_P3_U1_CFG1 EQU 0x400106c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG2 +CYREG_B0_P3_U1_CFG2 EQU 0x400106c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG3 +CYREG_B0_P3_U1_CFG3 EQU 0x400106c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG4 +CYREG_B0_P3_U1_CFG4 EQU 0x400106c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG5 +CYREG_B0_P3_U1_CFG5 EQU 0x400106c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG6 +CYREG_B0_P3_U1_CFG6 EQU 0x400106c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG7 +CYREG_B0_P3_U1_CFG7 EQU 0x400106c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG8 +CYREG_B0_P3_U1_CFG8 EQU 0x400106c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG9 +CYREG_B0_P3_U1_CFG9 EQU 0x400106c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG10 +CYREG_B0_P3_U1_CFG10 EQU 0x400106ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG11 +CYREG_B0_P3_U1_CFG11 EQU 0x400106cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG12 +CYREG_B0_P3_U1_CFG12 EQU 0x400106cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG13 +CYREG_B0_P3_U1_CFG13 EQU 0x400106cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG14 +CYREG_B0_P3_U1_CFG14 EQU 0x400106ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG15 +CYREG_B0_P3_U1_CFG15 EQU 0x400106cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG16 +CYREG_B0_P3_U1_CFG16 EQU 0x400106d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG17 +CYREG_B0_P3_U1_CFG17 EQU 0x400106d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG18 +CYREG_B0_P3_U1_CFG18 EQU 0x400106d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG19 +CYREG_B0_P3_U1_CFG19 EQU 0x400106d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG20 +CYREG_B0_P3_U1_CFG20 EQU 0x400106d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG21 +CYREG_B0_P3_U1_CFG21 EQU 0x400106d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG22 +CYREG_B0_P3_U1_CFG22 EQU 0x400106d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG23 +CYREG_B0_P3_U1_CFG23 EQU 0x400106d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG24 +CYREG_B0_P3_U1_CFG24 EQU 0x400106d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG25 +CYREG_B0_P3_U1_CFG25 EQU 0x400106d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG26 +CYREG_B0_P3_U1_CFG26 EQU 0x400106da + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG27 +CYREG_B0_P3_U1_CFG27 EQU 0x400106db + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG28 +CYREG_B0_P3_U1_CFG28 EQU 0x400106dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG29 +CYREG_B0_P3_U1_CFG29 EQU 0x400106dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG30 +CYREG_B0_P3_U1_CFG30 EQU 0x400106de + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_CFG31 +CYREG_B0_P3_U1_CFG31 EQU 0x400106df + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG0 +CYREG_B0_P3_U1_DCFG0 EQU 0x400106e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG1 +CYREG_B0_P3_U1_DCFG1 EQU 0x400106e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG2 +CYREG_B0_P3_U1_DCFG2 EQU 0x400106e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG3 +CYREG_B0_P3_U1_DCFG3 EQU 0x400106e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG4 +CYREG_B0_P3_U1_DCFG4 EQU 0x400106e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG5 +CYREG_B0_P3_U1_DCFG5 EQU 0x400106ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG6 +CYREG_B0_P3_U1_DCFG6 EQU 0x400106ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P3_U1_DCFG7 +CYREG_B0_P3_U1_DCFG7 EQU 0x400106ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_BASE +CYDEV_UCFG_B0_P3_ROUTE_BASE EQU 0x40010700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P3_ROUTE_SIZE +CYDEV_UCFG_B0_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_BASE +CYDEV_UCFG_B0_P4_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_SIZE +CYDEV_UCFG_B0_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_BASE +CYDEV_UCFG_B0_P4_U0_BASE EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U0_SIZE +CYDEV_UCFG_B0_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT0 +CYREG_B0_P4_U0_PLD_IT0 EQU 0x40010800 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT1 +CYREG_B0_P4_U0_PLD_IT1 EQU 0x40010804 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT2 +CYREG_B0_P4_U0_PLD_IT2 EQU 0x40010808 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT3 +CYREG_B0_P4_U0_PLD_IT3 EQU 0x4001080c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT4 +CYREG_B0_P4_U0_PLD_IT4 EQU 0x40010810 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT5 +CYREG_B0_P4_U0_PLD_IT5 EQU 0x40010814 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT6 +CYREG_B0_P4_U0_PLD_IT6 EQU 0x40010818 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT7 +CYREG_B0_P4_U0_PLD_IT7 EQU 0x4001081c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT8 +CYREG_B0_P4_U0_PLD_IT8 EQU 0x40010820 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT9 +CYREG_B0_P4_U0_PLD_IT9 EQU 0x40010824 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT10 +CYREG_B0_P4_U0_PLD_IT10 EQU 0x40010828 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_IT11 +CYREG_B0_P4_U0_PLD_IT11 EQU 0x4001082c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT0 +CYREG_B0_P4_U0_PLD_ORT0 EQU 0x40010830 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT1 +CYREG_B0_P4_U0_PLD_ORT1 EQU 0x40010832 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT2 +CYREG_B0_P4_U0_PLD_ORT2 EQU 0x40010834 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_PLD_ORT3 +CYREG_B0_P4_U0_PLD_ORT3 EQU 0x40010836 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_CEN_CONST +CYREG_B0_P4_U0_MC_CFG_CEN_CONST EQU 0x40010838 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_XORFB +CYREG_B0_P4_U0_MC_CFG_XORFB EQU 0x4001083a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_SET_RESET +CYREG_B0_P4_U0_MC_CFG_SET_RESET EQU 0x4001083c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_MC_CFG_BYPASS +CYREG_B0_P4_U0_MC_CFG_BYPASS EQU 0x4001083e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG0 +CYREG_B0_P4_U0_CFG0 EQU 0x40010840 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG1 +CYREG_B0_P4_U0_CFG1 EQU 0x40010841 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG2 +CYREG_B0_P4_U0_CFG2 EQU 0x40010842 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG3 +CYREG_B0_P4_U0_CFG3 EQU 0x40010843 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG4 +CYREG_B0_P4_U0_CFG4 EQU 0x40010844 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG5 +CYREG_B0_P4_U0_CFG5 EQU 0x40010845 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG6 +CYREG_B0_P4_U0_CFG6 EQU 0x40010846 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG7 +CYREG_B0_P4_U0_CFG7 EQU 0x40010847 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG8 +CYREG_B0_P4_U0_CFG8 EQU 0x40010848 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG9 +CYREG_B0_P4_U0_CFG9 EQU 0x40010849 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG10 +CYREG_B0_P4_U0_CFG10 EQU 0x4001084a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG11 +CYREG_B0_P4_U0_CFG11 EQU 0x4001084b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG12 +CYREG_B0_P4_U0_CFG12 EQU 0x4001084c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG13 +CYREG_B0_P4_U0_CFG13 EQU 0x4001084d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG14 +CYREG_B0_P4_U0_CFG14 EQU 0x4001084e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG15 +CYREG_B0_P4_U0_CFG15 EQU 0x4001084f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG16 +CYREG_B0_P4_U0_CFG16 EQU 0x40010850 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG17 +CYREG_B0_P4_U0_CFG17 EQU 0x40010851 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG18 +CYREG_B0_P4_U0_CFG18 EQU 0x40010852 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG19 +CYREG_B0_P4_U0_CFG19 EQU 0x40010853 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG20 +CYREG_B0_P4_U0_CFG20 EQU 0x40010854 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG21 +CYREG_B0_P4_U0_CFG21 EQU 0x40010855 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG22 +CYREG_B0_P4_U0_CFG22 EQU 0x40010856 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG23 +CYREG_B0_P4_U0_CFG23 EQU 0x40010857 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG24 +CYREG_B0_P4_U0_CFG24 EQU 0x40010858 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG25 +CYREG_B0_P4_U0_CFG25 EQU 0x40010859 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG26 +CYREG_B0_P4_U0_CFG26 EQU 0x4001085a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG27 +CYREG_B0_P4_U0_CFG27 EQU 0x4001085b + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG28 +CYREG_B0_P4_U0_CFG28 EQU 0x4001085c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG29 +CYREG_B0_P4_U0_CFG29 EQU 0x4001085d + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG30 +CYREG_B0_P4_U0_CFG30 EQU 0x4001085e + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_CFG31 +CYREG_B0_P4_U0_CFG31 EQU 0x4001085f + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG0 +CYREG_B0_P4_U0_DCFG0 EQU 0x40010860 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG1 +CYREG_B0_P4_U0_DCFG1 EQU 0x40010862 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG2 +CYREG_B0_P4_U0_DCFG2 EQU 0x40010864 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG3 +CYREG_B0_P4_U0_DCFG3 EQU 0x40010866 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG4 +CYREG_B0_P4_U0_DCFG4 EQU 0x40010868 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG5 +CYREG_B0_P4_U0_DCFG5 EQU 0x4001086a + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG6 +CYREG_B0_P4_U0_DCFG6 EQU 0x4001086c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U0_DCFG7 +CYREG_B0_P4_U0_DCFG7 EQU 0x4001086e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_BASE +CYDEV_UCFG_B0_P4_U1_BASE EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_U1_SIZE +CYDEV_UCFG_B0_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT0 +CYREG_B0_P4_U1_PLD_IT0 EQU 0x40010880 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT1 +CYREG_B0_P4_U1_PLD_IT1 EQU 0x40010884 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT2 +CYREG_B0_P4_U1_PLD_IT2 EQU 0x40010888 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT3 +CYREG_B0_P4_U1_PLD_IT3 EQU 0x4001088c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT4 +CYREG_B0_P4_U1_PLD_IT4 EQU 0x40010890 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT5 +CYREG_B0_P4_U1_PLD_IT5 EQU 0x40010894 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT6 +CYREG_B0_P4_U1_PLD_IT6 EQU 0x40010898 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT7 +CYREG_B0_P4_U1_PLD_IT7 EQU 0x4001089c + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT8 +CYREG_B0_P4_U1_PLD_IT8 EQU 0x400108a0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT9 +CYREG_B0_P4_U1_PLD_IT9 EQU 0x400108a4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT10 +CYREG_B0_P4_U1_PLD_IT10 EQU 0x400108a8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_IT11 +CYREG_B0_P4_U1_PLD_IT11 EQU 0x400108ac + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT0 +CYREG_B0_P4_U1_PLD_ORT0 EQU 0x400108b0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT1 +CYREG_B0_P4_U1_PLD_ORT1 EQU 0x400108b2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT2 +CYREG_B0_P4_U1_PLD_ORT2 EQU 0x400108b4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_PLD_ORT3 +CYREG_B0_P4_U1_PLD_ORT3 EQU 0x400108b6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_CEN_CONST +CYREG_B0_P4_U1_MC_CFG_CEN_CONST EQU 0x400108b8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_XORFB +CYREG_B0_P4_U1_MC_CFG_XORFB EQU 0x400108ba + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_SET_RESET +CYREG_B0_P4_U1_MC_CFG_SET_RESET EQU 0x400108bc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_MC_CFG_BYPASS +CYREG_B0_P4_U1_MC_CFG_BYPASS EQU 0x400108be + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG0 +CYREG_B0_P4_U1_CFG0 EQU 0x400108c0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG1 +CYREG_B0_P4_U1_CFG1 EQU 0x400108c1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG2 +CYREG_B0_P4_U1_CFG2 EQU 0x400108c2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG3 +CYREG_B0_P4_U1_CFG3 EQU 0x400108c3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG4 +CYREG_B0_P4_U1_CFG4 EQU 0x400108c4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG5 +CYREG_B0_P4_U1_CFG5 EQU 0x400108c5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG6 +CYREG_B0_P4_U1_CFG6 EQU 0x400108c6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG7 +CYREG_B0_P4_U1_CFG7 EQU 0x400108c7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG8 +CYREG_B0_P4_U1_CFG8 EQU 0x400108c8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG9 +CYREG_B0_P4_U1_CFG9 EQU 0x400108c9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG10 +CYREG_B0_P4_U1_CFG10 EQU 0x400108ca + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG11 +CYREG_B0_P4_U1_CFG11 EQU 0x400108cb + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG12 +CYREG_B0_P4_U1_CFG12 EQU 0x400108cc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG13 +CYREG_B0_P4_U1_CFG13 EQU 0x400108cd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG14 +CYREG_B0_P4_U1_CFG14 EQU 0x400108ce + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG15 +CYREG_B0_P4_U1_CFG15 EQU 0x400108cf + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG16 +CYREG_B0_P4_U1_CFG16 EQU 0x400108d0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG17 +CYREG_B0_P4_U1_CFG17 EQU 0x400108d1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG18 +CYREG_B0_P4_U1_CFG18 EQU 0x400108d2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG19 +CYREG_B0_P4_U1_CFG19 EQU 0x400108d3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG20 +CYREG_B0_P4_U1_CFG20 EQU 0x400108d4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG21 +CYREG_B0_P4_U1_CFG21 EQU 0x400108d5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG22 +CYREG_B0_P4_U1_CFG22 EQU 0x400108d6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG23 +CYREG_B0_P4_U1_CFG23 EQU 0x400108d7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG24 +CYREG_B0_P4_U1_CFG24 EQU 0x400108d8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG25 +CYREG_B0_P4_U1_CFG25 EQU 0x400108d9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG26 +CYREG_B0_P4_U1_CFG26 EQU 0x400108da + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG27 +CYREG_B0_P4_U1_CFG27 EQU 0x400108db + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG28 +CYREG_B0_P4_U1_CFG28 EQU 0x400108dc + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG29 +CYREG_B0_P4_U1_CFG29 EQU 0x400108dd + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG30 +CYREG_B0_P4_U1_CFG30 EQU 0x400108de + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_CFG31 +CYREG_B0_P4_U1_CFG31 EQU 0x400108df + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG0 +CYREG_B0_P4_U1_DCFG0 EQU 0x400108e0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG1 +CYREG_B0_P4_U1_DCFG1 EQU 0x400108e2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG2 +CYREG_B0_P4_U1_DCFG2 EQU 0x400108e4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG3 +CYREG_B0_P4_U1_DCFG3 EQU 0x400108e6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG4 +CYREG_B0_P4_U1_DCFG4 EQU 0x400108e8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG5 +CYREG_B0_P4_U1_DCFG5 EQU 0x400108ea + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG6 +CYREG_B0_P4_U1_DCFG6 EQU 0x400108ec + ENDIF + IF :LNOT::DEF:CYREG_B0_P4_U1_DCFG7 +CYREG_B0_P4_U1_DCFG7 EQU 0x400108ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_BASE +CYDEV_UCFG_B0_P4_ROUTE_BASE EQU 0x40010900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P4_ROUTE_SIZE +CYDEV_UCFG_B0_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_BASE +CYDEV_UCFG_B0_P5_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_SIZE +CYDEV_UCFG_B0_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_BASE +CYDEV_UCFG_B0_P5_U0_BASE EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U0_SIZE +CYDEV_UCFG_B0_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT0 +CYREG_B0_P5_U0_PLD_IT0 EQU 0x40010a00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT1 +CYREG_B0_P5_U0_PLD_IT1 EQU 0x40010a04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT2 +CYREG_B0_P5_U0_PLD_IT2 EQU 0x40010a08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT3 +CYREG_B0_P5_U0_PLD_IT3 EQU 0x40010a0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT4 +CYREG_B0_P5_U0_PLD_IT4 EQU 0x40010a10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT5 +CYREG_B0_P5_U0_PLD_IT5 EQU 0x40010a14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT6 +CYREG_B0_P5_U0_PLD_IT6 EQU 0x40010a18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT7 +CYREG_B0_P5_U0_PLD_IT7 EQU 0x40010a1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT8 +CYREG_B0_P5_U0_PLD_IT8 EQU 0x40010a20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT9 +CYREG_B0_P5_U0_PLD_IT9 EQU 0x40010a24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT10 +CYREG_B0_P5_U0_PLD_IT10 EQU 0x40010a28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_IT11 +CYREG_B0_P5_U0_PLD_IT11 EQU 0x40010a2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT0 +CYREG_B0_P5_U0_PLD_ORT0 EQU 0x40010a30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT1 +CYREG_B0_P5_U0_PLD_ORT1 EQU 0x40010a32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT2 +CYREG_B0_P5_U0_PLD_ORT2 EQU 0x40010a34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_PLD_ORT3 +CYREG_B0_P5_U0_PLD_ORT3 EQU 0x40010a36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_CEN_CONST +CYREG_B0_P5_U0_MC_CFG_CEN_CONST EQU 0x40010a38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_XORFB +CYREG_B0_P5_U0_MC_CFG_XORFB EQU 0x40010a3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_SET_RESET +CYREG_B0_P5_U0_MC_CFG_SET_RESET EQU 0x40010a3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_MC_CFG_BYPASS +CYREG_B0_P5_U0_MC_CFG_BYPASS EQU 0x40010a3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG0 +CYREG_B0_P5_U0_CFG0 EQU 0x40010a40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG1 +CYREG_B0_P5_U0_CFG1 EQU 0x40010a41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG2 +CYREG_B0_P5_U0_CFG2 EQU 0x40010a42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG3 +CYREG_B0_P5_U0_CFG3 EQU 0x40010a43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG4 +CYREG_B0_P5_U0_CFG4 EQU 0x40010a44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG5 +CYREG_B0_P5_U0_CFG5 EQU 0x40010a45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG6 +CYREG_B0_P5_U0_CFG6 EQU 0x40010a46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG7 +CYREG_B0_P5_U0_CFG7 EQU 0x40010a47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG8 +CYREG_B0_P5_U0_CFG8 EQU 0x40010a48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG9 +CYREG_B0_P5_U0_CFG9 EQU 0x40010a49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG10 +CYREG_B0_P5_U0_CFG10 EQU 0x40010a4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG11 +CYREG_B0_P5_U0_CFG11 EQU 0x40010a4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG12 +CYREG_B0_P5_U0_CFG12 EQU 0x40010a4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG13 +CYREG_B0_P5_U0_CFG13 EQU 0x40010a4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG14 +CYREG_B0_P5_U0_CFG14 EQU 0x40010a4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG15 +CYREG_B0_P5_U0_CFG15 EQU 0x40010a4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG16 +CYREG_B0_P5_U0_CFG16 EQU 0x40010a50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG17 +CYREG_B0_P5_U0_CFG17 EQU 0x40010a51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG18 +CYREG_B0_P5_U0_CFG18 EQU 0x40010a52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG19 +CYREG_B0_P5_U0_CFG19 EQU 0x40010a53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG20 +CYREG_B0_P5_U0_CFG20 EQU 0x40010a54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG21 +CYREG_B0_P5_U0_CFG21 EQU 0x40010a55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG22 +CYREG_B0_P5_U0_CFG22 EQU 0x40010a56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG23 +CYREG_B0_P5_U0_CFG23 EQU 0x40010a57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG24 +CYREG_B0_P5_U0_CFG24 EQU 0x40010a58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG25 +CYREG_B0_P5_U0_CFG25 EQU 0x40010a59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG26 +CYREG_B0_P5_U0_CFG26 EQU 0x40010a5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG27 +CYREG_B0_P5_U0_CFG27 EQU 0x40010a5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG28 +CYREG_B0_P5_U0_CFG28 EQU 0x40010a5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG29 +CYREG_B0_P5_U0_CFG29 EQU 0x40010a5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG30 +CYREG_B0_P5_U0_CFG30 EQU 0x40010a5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_CFG31 +CYREG_B0_P5_U0_CFG31 EQU 0x40010a5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG0 +CYREG_B0_P5_U0_DCFG0 EQU 0x40010a60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG1 +CYREG_B0_P5_U0_DCFG1 EQU 0x40010a62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG2 +CYREG_B0_P5_U0_DCFG2 EQU 0x40010a64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG3 +CYREG_B0_P5_U0_DCFG3 EQU 0x40010a66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG4 +CYREG_B0_P5_U0_DCFG4 EQU 0x40010a68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG5 +CYREG_B0_P5_U0_DCFG5 EQU 0x40010a6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG6 +CYREG_B0_P5_U0_DCFG6 EQU 0x40010a6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U0_DCFG7 +CYREG_B0_P5_U0_DCFG7 EQU 0x40010a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_BASE +CYDEV_UCFG_B0_P5_U1_BASE EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_U1_SIZE +CYDEV_UCFG_B0_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT0 +CYREG_B0_P5_U1_PLD_IT0 EQU 0x40010a80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT1 +CYREG_B0_P5_U1_PLD_IT1 EQU 0x40010a84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT2 +CYREG_B0_P5_U1_PLD_IT2 EQU 0x40010a88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT3 +CYREG_B0_P5_U1_PLD_IT3 EQU 0x40010a8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT4 +CYREG_B0_P5_U1_PLD_IT4 EQU 0x40010a90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT5 +CYREG_B0_P5_U1_PLD_IT5 EQU 0x40010a94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT6 +CYREG_B0_P5_U1_PLD_IT6 EQU 0x40010a98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT7 +CYREG_B0_P5_U1_PLD_IT7 EQU 0x40010a9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT8 +CYREG_B0_P5_U1_PLD_IT8 EQU 0x40010aa0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT9 +CYREG_B0_P5_U1_PLD_IT9 EQU 0x40010aa4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT10 +CYREG_B0_P5_U1_PLD_IT10 EQU 0x40010aa8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_IT11 +CYREG_B0_P5_U1_PLD_IT11 EQU 0x40010aac + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT0 +CYREG_B0_P5_U1_PLD_ORT0 EQU 0x40010ab0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT1 +CYREG_B0_P5_U1_PLD_ORT1 EQU 0x40010ab2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT2 +CYREG_B0_P5_U1_PLD_ORT2 EQU 0x40010ab4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_PLD_ORT3 +CYREG_B0_P5_U1_PLD_ORT3 EQU 0x40010ab6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_CEN_CONST +CYREG_B0_P5_U1_MC_CFG_CEN_CONST EQU 0x40010ab8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_XORFB +CYREG_B0_P5_U1_MC_CFG_XORFB EQU 0x40010aba + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_SET_RESET +CYREG_B0_P5_U1_MC_CFG_SET_RESET EQU 0x40010abc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_MC_CFG_BYPASS +CYREG_B0_P5_U1_MC_CFG_BYPASS EQU 0x40010abe + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG0 +CYREG_B0_P5_U1_CFG0 EQU 0x40010ac0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG1 +CYREG_B0_P5_U1_CFG1 EQU 0x40010ac1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG2 +CYREG_B0_P5_U1_CFG2 EQU 0x40010ac2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG3 +CYREG_B0_P5_U1_CFG3 EQU 0x40010ac3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG4 +CYREG_B0_P5_U1_CFG4 EQU 0x40010ac4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG5 +CYREG_B0_P5_U1_CFG5 EQU 0x40010ac5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG6 +CYREG_B0_P5_U1_CFG6 EQU 0x40010ac6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG7 +CYREG_B0_P5_U1_CFG7 EQU 0x40010ac7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG8 +CYREG_B0_P5_U1_CFG8 EQU 0x40010ac8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG9 +CYREG_B0_P5_U1_CFG9 EQU 0x40010ac9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG10 +CYREG_B0_P5_U1_CFG10 EQU 0x40010aca + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG11 +CYREG_B0_P5_U1_CFG11 EQU 0x40010acb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG12 +CYREG_B0_P5_U1_CFG12 EQU 0x40010acc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG13 +CYREG_B0_P5_U1_CFG13 EQU 0x40010acd + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG14 +CYREG_B0_P5_U1_CFG14 EQU 0x40010ace + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG15 +CYREG_B0_P5_U1_CFG15 EQU 0x40010acf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG16 +CYREG_B0_P5_U1_CFG16 EQU 0x40010ad0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG17 +CYREG_B0_P5_U1_CFG17 EQU 0x40010ad1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG18 +CYREG_B0_P5_U1_CFG18 EQU 0x40010ad2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG19 +CYREG_B0_P5_U1_CFG19 EQU 0x40010ad3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG20 +CYREG_B0_P5_U1_CFG20 EQU 0x40010ad4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG21 +CYREG_B0_P5_U1_CFG21 EQU 0x40010ad5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG22 +CYREG_B0_P5_U1_CFG22 EQU 0x40010ad6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG23 +CYREG_B0_P5_U1_CFG23 EQU 0x40010ad7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG24 +CYREG_B0_P5_U1_CFG24 EQU 0x40010ad8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG25 +CYREG_B0_P5_U1_CFG25 EQU 0x40010ad9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG26 +CYREG_B0_P5_U1_CFG26 EQU 0x40010ada + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG27 +CYREG_B0_P5_U1_CFG27 EQU 0x40010adb + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG28 +CYREG_B0_P5_U1_CFG28 EQU 0x40010adc + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG29 +CYREG_B0_P5_U1_CFG29 EQU 0x40010add + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG30 +CYREG_B0_P5_U1_CFG30 EQU 0x40010ade + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_CFG31 +CYREG_B0_P5_U1_CFG31 EQU 0x40010adf + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG0 +CYREG_B0_P5_U1_DCFG0 EQU 0x40010ae0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG1 +CYREG_B0_P5_U1_DCFG1 EQU 0x40010ae2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG2 +CYREG_B0_P5_U1_DCFG2 EQU 0x40010ae4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG3 +CYREG_B0_P5_U1_DCFG3 EQU 0x40010ae6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG4 +CYREG_B0_P5_U1_DCFG4 EQU 0x40010ae8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG5 +CYREG_B0_P5_U1_DCFG5 EQU 0x40010aea + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG6 +CYREG_B0_P5_U1_DCFG6 EQU 0x40010aec + ENDIF + IF :LNOT::DEF:CYREG_B0_P5_U1_DCFG7 +CYREG_B0_P5_U1_DCFG7 EQU 0x40010aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_BASE +CYDEV_UCFG_B0_P5_ROUTE_BASE EQU 0x40010b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P5_ROUTE_SIZE +CYDEV_UCFG_B0_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_BASE +CYDEV_UCFG_B0_P6_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_SIZE +CYDEV_UCFG_B0_P6_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_BASE +CYDEV_UCFG_B0_P6_U0_BASE EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U0_SIZE +CYDEV_UCFG_B0_P6_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT0 +CYREG_B0_P6_U0_PLD_IT0 EQU 0x40010c00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT1 +CYREG_B0_P6_U0_PLD_IT1 EQU 0x40010c04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT2 +CYREG_B0_P6_U0_PLD_IT2 EQU 0x40010c08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT3 +CYREG_B0_P6_U0_PLD_IT3 EQU 0x40010c0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT4 +CYREG_B0_P6_U0_PLD_IT4 EQU 0x40010c10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT5 +CYREG_B0_P6_U0_PLD_IT5 EQU 0x40010c14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT6 +CYREG_B0_P6_U0_PLD_IT6 EQU 0x40010c18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT7 +CYREG_B0_P6_U0_PLD_IT7 EQU 0x40010c1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT8 +CYREG_B0_P6_U0_PLD_IT8 EQU 0x40010c20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT9 +CYREG_B0_P6_U0_PLD_IT9 EQU 0x40010c24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT10 +CYREG_B0_P6_U0_PLD_IT10 EQU 0x40010c28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_IT11 +CYREG_B0_P6_U0_PLD_IT11 EQU 0x40010c2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT0 +CYREG_B0_P6_U0_PLD_ORT0 EQU 0x40010c30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT1 +CYREG_B0_P6_U0_PLD_ORT1 EQU 0x40010c32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT2 +CYREG_B0_P6_U0_PLD_ORT2 EQU 0x40010c34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_PLD_ORT3 +CYREG_B0_P6_U0_PLD_ORT3 EQU 0x40010c36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_CEN_CONST +CYREG_B0_P6_U0_MC_CFG_CEN_CONST EQU 0x40010c38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_XORFB +CYREG_B0_P6_U0_MC_CFG_XORFB EQU 0x40010c3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_SET_RESET +CYREG_B0_P6_U0_MC_CFG_SET_RESET EQU 0x40010c3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_MC_CFG_BYPASS +CYREG_B0_P6_U0_MC_CFG_BYPASS EQU 0x40010c3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG0 +CYREG_B0_P6_U0_CFG0 EQU 0x40010c40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG1 +CYREG_B0_P6_U0_CFG1 EQU 0x40010c41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG2 +CYREG_B0_P6_U0_CFG2 EQU 0x40010c42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG3 +CYREG_B0_P6_U0_CFG3 EQU 0x40010c43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG4 +CYREG_B0_P6_U0_CFG4 EQU 0x40010c44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG5 +CYREG_B0_P6_U0_CFG5 EQU 0x40010c45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG6 +CYREG_B0_P6_U0_CFG6 EQU 0x40010c46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG7 +CYREG_B0_P6_U0_CFG7 EQU 0x40010c47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG8 +CYREG_B0_P6_U0_CFG8 EQU 0x40010c48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG9 +CYREG_B0_P6_U0_CFG9 EQU 0x40010c49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG10 +CYREG_B0_P6_U0_CFG10 EQU 0x40010c4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG11 +CYREG_B0_P6_U0_CFG11 EQU 0x40010c4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG12 +CYREG_B0_P6_U0_CFG12 EQU 0x40010c4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG13 +CYREG_B0_P6_U0_CFG13 EQU 0x40010c4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG14 +CYREG_B0_P6_U0_CFG14 EQU 0x40010c4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG15 +CYREG_B0_P6_U0_CFG15 EQU 0x40010c4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG16 +CYREG_B0_P6_U0_CFG16 EQU 0x40010c50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG17 +CYREG_B0_P6_U0_CFG17 EQU 0x40010c51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG18 +CYREG_B0_P6_U0_CFG18 EQU 0x40010c52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG19 +CYREG_B0_P6_U0_CFG19 EQU 0x40010c53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG20 +CYREG_B0_P6_U0_CFG20 EQU 0x40010c54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG21 +CYREG_B0_P6_U0_CFG21 EQU 0x40010c55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG22 +CYREG_B0_P6_U0_CFG22 EQU 0x40010c56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG23 +CYREG_B0_P6_U0_CFG23 EQU 0x40010c57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG24 +CYREG_B0_P6_U0_CFG24 EQU 0x40010c58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG25 +CYREG_B0_P6_U0_CFG25 EQU 0x40010c59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG26 +CYREG_B0_P6_U0_CFG26 EQU 0x40010c5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG27 +CYREG_B0_P6_U0_CFG27 EQU 0x40010c5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG28 +CYREG_B0_P6_U0_CFG28 EQU 0x40010c5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG29 +CYREG_B0_P6_U0_CFG29 EQU 0x40010c5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG30 +CYREG_B0_P6_U0_CFG30 EQU 0x40010c5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_CFG31 +CYREG_B0_P6_U0_CFG31 EQU 0x40010c5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG0 +CYREG_B0_P6_U0_DCFG0 EQU 0x40010c60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG1 +CYREG_B0_P6_U0_DCFG1 EQU 0x40010c62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG2 +CYREG_B0_P6_U0_DCFG2 EQU 0x40010c64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG3 +CYREG_B0_P6_U0_DCFG3 EQU 0x40010c66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG4 +CYREG_B0_P6_U0_DCFG4 EQU 0x40010c68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG5 +CYREG_B0_P6_U0_DCFG5 EQU 0x40010c6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG6 +CYREG_B0_P6_U0_DCFG6 EQU 0x40010c6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U0_DCFG7 +CYREG_B0_P6_U0_DCFG7 EQU 0x40010c6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_BASE +CYDEV_UCFG_B0_P6_U1_BASE EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_U1_SIZE +CYDEV_UCFG_B0_P6_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT0 +CYREG_B0_P6_U1_PLD_IT0 EQU 0x40010c80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT1 +CYREG_B0_P6_U1_PLD_IT1 EQU 0x40010c84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT2 +CYREG_B0_P6_U1_PLD_IT2 EQU 0x40010c88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT3 +CYREG_B0_P6_U1_PLD_IT3 EQU 0x40010c8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT4 +CYREG_B0_P6_U1_PLD_IT4 EQU 0x40010c90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT5 +CYREG_B0_P6_U1_PLD_IT5 EQU 0x40010c94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT6 +CYREG_B0_P6_U1_PLD_IT6 EQU 0x40010c98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT7 +CYREG_B0_P6_U1_PLD_IT7 EQU 0x40010c9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT8 +CYREG_B0_P6_U1_PLD_IT8 EQU 0x40010ca0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT9 +CYREG_B0_P6_U1_PLD_IT9 EQU 0x40010ca4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT10 +CYREG_B0_P6_U1_PLD_IT10 EQU 0x40010ca8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_IT11 +CYREG_B0_P6_U1_PLD_IT11 EQU 0x40010cac + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT0 +CYREG_B0_P6_U1_PLD_ORT0 EQU 0x40010cb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT1 +CYREG_B0_P6_U1_PLD_ORT1 EQU 0x40010cb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT2 +CYREG_B0_P6_U1_PLD_ORT2 EQU 0x40010cb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_PLD_ORT3 +CYREG_B0_P6_U1_PLD_ORT3 EQU 0x40010cb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_CEN_CONST +CYREG_B0_P6_U1_MC_CFG_CEN_CONST EQU 0x40010cb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_XORFB +CYREG_B0_P6_U1_MC_CFG_XORFB EQU 0x40010cba + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_SET_RESET +CYREG_B0_P6_U1_MC_CFG_SET_RESET EQU 0x40010cbc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_MC_CFG_BYPASS +CYREG_B0_P6_U1_MC_CFG_BYPASS EQU 0x40010cbe + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG0 +CYREG_B0_P6_U1_CFG0 EQU 0x40010cc0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG1 +CYREG_B0_P6_U1_CFG1 EQU 0x40010cc1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG2 +CYREG_B0_P6_U1_CFG2 EQU 0x40010cc2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG3 +CYREG_B0_P6_U1_CFG3 EQU 0x40010cc3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG4 +CYREG_B0_P6_U1_CFG4 EQU 0x40010cc4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG5 +CYREG_B0_P6_U1_CFG5 EQU 0x40010cc5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG6 +CYREG_B0_P6_U1_CFG6 EQU 0x40010cc6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG7 +CYREG_B0_P6_U1_CFG7 EQU 0x40010cc7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG8 +CYREG_B0_P6_U1_CFG8 EQU 0x40010cc8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG9 +CYREG_B0_P6_U1_CFG9 EQU 0x40010cc9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG10 +CYREG_B0_P6_U1_CFG10 EQU 0x40010cca + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG11 +CYREG_B0_P6_U1_CFG11 EQU 0x40010ccb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG12 +CYREG_B0_P6_U1_CFG12 EQU 0x40010ccc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG13 +CYREG_B0_P6_U1_CFG13 EQU 0x40010ccd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG14 +CYREG_B0_P6_U1_CFG14 EQU 0x40010cce + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG15 +CYREG_B0_P6_U1_CFG15 EQU 0x40010ccf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG16 +CYREG_B0_P6_U1_CFG16 EQU 0x40010cd0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG17 +CYREG_B0_P6_U1_CFG17 EQU 0x40010cd1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG18 +CYREG_B0_P6_U1_CFG18 EQU 0x40010cd2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG19 +CYREG_B0_P6_U1_CFG19 EQU 0x40010cd3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG20 +CYREG_B0_P6_U1_CFG20 EQU 0x40010cd4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG21 +CYREG_B0_P6_U1_CFG21 EQU 0x40010cd5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG22 +CYREG_B0_P6_U1_CFG22 EQU 0x40010cd6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG23 +CYREG_B0_P6_U1_CFG23 EQU 0x40010cd7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG24 +CYREG_B0_P6_U1_CFG24 EQU 0x40010cd8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG25 +CYREG_B0_P6_U1_CFG25 EQU 0x40010cd9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG26 +CYREG_B0_P6_U1_CFG26 EQU 0x40010cda + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG27 +CYREG_B0_P6_U1_CFG27 EQU 0x40010cdb + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG28 +CYREG_B0_P6_U1_CFG28 EQU 0x40010cdc + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG29 +CYREG_B0_P6_U1_CFG29 EQU 0x40010cdd + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG30 +CYREG_B0_P6_U1_CFG30 EQU 0x40010cde + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_CFG31 +CYREG_B0_P6_U1_CFG31 EQU 0x40010cdf + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG0 +CYREG_B0_P6_U1_DCFG0 EQU 0x40010ce0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG1 +CYREG_B0_P6_U1_DCFG1 EQU 0x40010ce2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG2 +CYREG_B0_P6_U1_DCFG2 EQU 0x40010ce4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG3 +CYREG_B0_P6_U1_DCFG3 EQU 0x40010ce6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG4 +CYREG_B0_P6_U1_DCFG4 EQU 0x40010ce8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG5 +CYREG_B0_P6_U1_DCFG5 EQU 0x40010cea + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG6 +CYREG_B0_P6_U1_DCFG6 EQU 0x40010cec + ENDIF + IF :LNOT::DEF:CYREG_B0_P6_U1_DCFG7 +CYREG_B0_P6_U1_DCFG7 EQU 0x40010cee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_BASE +CYDEV_UCFG_B0_P6_ROUTE_BASE EQU 0x40010d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P6_ROUTE_SIZE +CYDEV_UCFG_B0_P6_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_BASE +CYDEV_UCFG_B0_P7_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_SIZE +CYDEV_UCFG_B0_P7_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_BASE +CYDEV_UCFG_B0_P7_U0_BASE EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U0_SIZE +CYDEV_UCFG_B0_P7_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT0 +CYREG_B0_P7_U0_PLD_IT0 EQU 0x40010e00 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT1 +CYREG_B0_P7_U0_PLD_IT1 EQU 0x40010e04 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT2 +CYREG_B0_P7_U0_PLD_IT2 EQU 0x40010e08 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT3 +CYREG_B0_P7_U0_PLD_IT3 EQU 0x40010e0c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT4 +CYREG_B0_P7_U0_PLD_IT4 EQU 0x40010e10 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT5 +CYREG_B0_P7_U0_PLD_IT5 EQU 0x40010e14 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT6 +CYREG_B0_P7_U0_PLD_IT6 EQU 0x40010e18 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT7 +CYREG_B0_P7_U0_PLD_IT7 EQU 0x40010e1c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT8 +CYREG_B0_P7_U0_PLD_IT8 EQU 0x40010e20 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT9 +CYREG_B0_P7_U0_PLD_IT9 EQU 0x40010e24 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT10 +CYREG_B0_P7_U0_PLD_IT10 EQU 0x40010e28 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_IT11 +CYREG_B0_P7_U0_PLD_IT11 EQU 0x40010e2c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT0 +CYREG_B0_P7_U0_PLD_ORT0 EQU 0x40010e30 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT1 +CYREG_B0_P7_U0_PLD_ORT1 EQU 0x40010e32 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT2 +CYREG_B0_P7_U0_PLD_ORT2 EQU 0x40010e34 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_PLD_ORT3 +CYREG_B0_P7_U0_PLD_ORT3 EQU 0x40010e36 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_CEN_CONST +CYREG_B0_P7_U0_MC_CFG_CEN_CONST EQU 0x40010e38 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_XORFB +CYREG_B0_P7_U0_MC_CFG_XORFB EQU 0x40010e3a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_SET_RESET +CYREG_B0_P7_U0_MC_CFG_SET_RESET EQU 0x40010e3c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_MC_CFG_BYPASS +CYREG_B0_P7_U0_MC_CFG_BYPASS EQU 0x40010e3e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG0 +CYREG_B0_P7_U0_CFG0 EQU 0x40010e40 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG1 +CYREG_B0_P7_U0_CFG1 EQU 0x40010e41 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG2 +CYREG_B0_P7_U0_CFG2 EQU 0x40010e42 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG3 +CYREG_B0_P7_U0_CFG3 EQU 0x40010e43 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG4 +CYREG_B0_P7_U0_CFG4 EQU 0x40010e44 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG5 +CYREG_B0_P7_U0_CFG5 EQU 0x40010e45 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG6 +CYREG_B0_P7_U0_CFG6 EQU 0x40010e46 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG7 +CYREG_B0_P7_U0_CFG7 EQU 0x40010e47 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG8 +CYREG_B0_P7_U0_CFG8 EQU 0x40010e48 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG9 +CYREG_B0_P7_U0_CFG9 EQU 0x40010e49 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG10 +CYREG_B0_P7_U0_CFG10 EQU 0x40010e4a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG11 +CYREG_B0_P7_U0_CFG11 EQU 0x40010e4b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG12 +CYREG_B0_P7_U0_CFG12 EQU 0x40010e4c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG13 +CYREG_B0_P7_U0_CFG13 EQU 0x40010e4d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG14 +CYREG_B0_P7_U0_CFG14 EQU 0x40010e4e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG15 +CYREG_B0_P7_U0_CFG15 EQU 0x40010e4f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG16 +CYREG_B0_P7_U0_CFG16 EQU 0x40010e50 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG17 +CYREG_B0_P7_U0_CFG17 EQU 0x40010e51 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG18 +CYREG_B0_P7_U0_CFG18 EQU 0x40010e52 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG19 +CYREG_B0_P7_U0_CFG19 EQU 0x40010e53 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG20 +CYREG_B0_P7_U0_CFG20 EQU 0x40010e54 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG21 +CYREG_B0_P7_U0_CFG21 EQU 0x40010e55 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG22 +CYREG_B0_P7_U0_CFG22 EQU 0x40010e56 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG23 +CYREG_B0_P7_U0_CFG23 EQU 0x40010e57 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG24 +CYREG_B0_P7_U0_CFG24 EQU 0x40010e58 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG25 +CYREG_B0_P7_U0_CFG25 EQU 0x40010e59 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG26 +CYREG_B0_P7_U0_CFG26 EQU 0x40010e5a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG27 +CYREG_B0_P7_U0_CFG27 EQU 0x40010e5b + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG28 +CYREG_B0_P7_U0_CFG28 EQU 0x40010e5c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG29 +CYREG_B0_P7_U0_CFG29 EQU 0x40010e5d + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG30 +CYREG_B0_P7_U0_CFG30 EQU 0x40010e5e + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_CFG31 +CYREG_B0_P7_U0_CFG31 EQU 0x40010e5f + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG0 +CYREG_B0_P7_U0_DCFG0 EQU 0x40010e60 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG1 +CYREG_B0_P7_U0_DCFG1 EQU 0x40010e62 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG2 +CYREG_B0_P7_U0_DCFG2 EQU 0x40010e64 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG3 +CYREG_B0_P7_U0_DCFG3 EQU 0x40010e66 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG4 +CYREG_B0_P7_U0_DCFG4 EQU 0x40010e68 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG5 +CYREG_B0_P7_U0_DCFG5 EQU 0x40010e6a + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG6 +CYREG_B0_P7_U0_DCFG6 EQU 0x40010e6c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U0_DCFG7 +CYREG_B0_P7_U0_DCFG7 EQU 0x40010e6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_BASE +CYDEV_UCFG_B0_P7_U1_BASE EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_U1_SIZE +CYDEV_UCFG_B0_P7_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT0 +CYREG_B0_P7_U1_PLD_IT0 EQU 0x40010e80 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT1 +CYREG_B0_P7_U1_PLD_IT1 EQU 0x40010e84 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT2 +CYREG_B0_P7_U1_PLD_IT2 EQU 0x40010e88 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT3 +CYREG_B0_P7_U1_PLD_IT3 EQU 0x40010e8c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT4 +CYREG_B0_P7_U1_PLD_IT4 EQU 0x40010e90 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT5 +CYREG_B0_P7_U1_PLD_IT5 EQU 0x40010e94 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT6 +CYREG_B0_P7_U1_PLD_IT6 EQU 0x40010e98 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT7 +CYREG_B0_P7_U1_PLD_IT7 EQU 0x40010e9c + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT8 +CYREG_B0_P7_U1_PLD_IT8 EQU 0x40010ea0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT9 +CYREG_B0_P7_U1_PLD_IT9 EQU 0x40010ea4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT10 +CYREG_B0_P7_U1_PLD_IT10 EQU 0x40010ea8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_IT11 +CYREG_B0_P7_U1_PLD_IT11 EQU 0x40010eac + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT0 +CYREG_B0_P7_U1_PLD_ORT0 EQU 0x40010eb0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT1 +CYREG_B0_P7_U1_PLD_ORT1 EQU 0x40010eb2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT2 +CYREG_B0_P7_U1_PLD_ORT2 EQU 0x40010eb4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_PLD_ORT3 +CYREG_B0_P7_U1_PLD_ORT3 EQU 0x40010eb6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_CEN_CONST +CYREG_B0_P7_U1_MC_CFG_CEN_CONST EQU 0x40010eb8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_XORFB +CYREG_B0_P7_U1_MC_CFG_XORFB EQU 0x40010eba + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_SET_RESET +CYREG_B0_P7_U1_MC_CFG_SET_RESET EQU 0x40010ebc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_MC_CFG_BYPASS +CYREG_B0_P7_U1_MC_CFG_BYPASS EQU 0x40010ebe + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG0 +CYREG_B0_P7_U1_CFG0 EQU 0x40010ec0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG1 +CYREG_B0_P7_U1_CFG1 EQU 0x40010ec1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG2 +CYREG_B0_P7_U1_CFG2 EQU 0x40010ec2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG3 +CYREG_B0_P7_U1_CFG3 EQU 0x40010ec3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG4 +CYREG_B0_P7_U1_CFG4 EQU 0x40010ec4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG5 +CYREG_B0_P7_U1_CFG5 EQU 0x40010ec5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG6 +CYREG_B0_P7_U1_CFG6 EQU 0x40010ec6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG7 +CYREG_B0_P7_U1_CFG7 EQU 0x40010ec7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG8 +CYREG_B0_P7_U1_CFG8 EQU 0x40010ec8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG9 +CYREG_B0_P7_U1_CFG9 EQU 0x40010ec9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG10 +CYREG_B0_P7_U1_CFG10 EQU 0x40010eca + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG11 +CYREG_B0_P7_U1_CFG11 EQU 0x40010ecb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG12 +CYREG_B0_P7_U1_CFG12 EQU 0x40010ecc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG13 +CYREG_B0_P7_U1_CFG13 EQU 0x40010ecd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG14 +CYREG_B0_P7_U1_CFG14 EQU 0x40010ece + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG15 +CYREG_B0_P7_U1_CFG15 EQU 0x40010ecf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG16 +CYREG_B0_P7_U1_CFG16 EQU 0x40010ed0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG17 +CYREG_B0_P7_U1_CFG17 EQU 0x40010ed1 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG18 +CYREG_B0_P7_U1_CFG18 EQU 0x40010ed2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG19 +CYREG_B0_P7_U1_CFG19 EQU 0x40010ed3 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG20 +CYREG_B0_P7_U1_CFG20 EQU 0x40010ed4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG21 +CYREG_B0_P7_U1_CFG21 EQU 0x40010ed5 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG22 +CYREG_B0_P7_U1_CFG22 EQU 0x40010ed6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG23 +CYREG_B0_P7_U1_CFG23 EQU 0x40010ed7 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG24 +CYREG_B0_P7_U1_CFG24 EQU 0x40010ed8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG25 +CYREG_B0_P7_U1_CFG25 EQU 0x40010ed9 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG26 +CYREG_B0_P7_U1_CFG26 EQU 0x40010eda + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG27 +CYREG_B0_P7_U1_CFG27 EQU 0x40010edb + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG28 +CYREG_B0_P7_U1_CFG28 EQU 0x40010edc + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG29 +CYREG_B0_P7_U1_CFG29 EQU 0x40010edd + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG30 +CYREG_B0_P7_U1_CFG30 EQU 0x40010ede + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_CFG31 +CYREG_B0_P7_U1_CFG31 EQU 0x40010edf + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG0 +CYREG_B0_P7_U1_DCFG0 EQU 0x40010ee0 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG1 +CYREG_B0_P7_U1_DCFG1 EQU 0x40010ee2 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG2 +CYREG_B0_P7_U1_DCFG2 EQU 0x40010ee4 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG3 +CYREG_B0_P7_U1_DCFG3 EQU 0x40010ee6 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG4 +CYREG_B0_P7_U1_DCFG4 EQU 0x40010ee8 + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG5 +CYREG_B0_P7_U1_DCFG5 EQU 0x40010eea + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG6 +CYREG_B0_P7_U1_DCFG6 EQU 0x40010eec + ENDIF + IF :LNOT::DEF:CYREG_B0_P7_U1_DCFG7 +CYREG_B0_P7_U1_DCFG7 EQU 0x40010eee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_BASE +CYDEV_UCFG_B0_P7_ROUTE_BASE EQU 0x40010f00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B0_P7_ROUTE_SIZE +CYDEV_UCFG_B0_P7_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_BASE +CYDEV_UCFG_B1_BASE EQU 0x40011000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_SIZE +CYDEV_UCFG_B1_SIZE EQU 0x00000fef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_BASE +CYDEV_UCFG_B1_P2_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_SIZE +CYDEV_UCFG_B1_P2_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_BASE +CYDEV_UCFG_B1_P2_U0_BASE EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U0_SIZE +CYDEV_UCFG_B1_P2_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT0 +CYREG_B1_P2_U0_PLD_IT0 EQU 0x40011400 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT1 +CYREG_B1_P2_U0_PLD_IT1 EQU 0x40011404 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT2 +CYREG_B1_P2_U0_PLD_IT2 EQU 0x40011408 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT3 +CYREG_B1_P2_U0_PLD_IT3 EQU 0x4001140c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT4 +CYREG_B1_P2_U0_PLD_IT4 EQU 0x40011410 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT5 +CYREG_B1_P2_U0_PLD_IT5 EQU 0x40011414 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT6 +CYREG_B1_P2_U0_PLD_IT6 EQU 0x40011418 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT7 +CYREG_B1_P2_U0_PLD_IT7 EQU 0x4001141c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT8 +CYREG_B1_P2_U0_PLD_IT8 EQU 0x40011420 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT9 +CYREG_B1_P2_U0_PLD_IT9 EQU 0x40011424 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT10 +CYREG_B1_P2_U0_PLD_IT10 EQU 0x40011428 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_IT11 +CYREG_B1_P2_U0_PLD_IT11 EQU 0x4001142c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT0 +CYREG_B1_P2_U0_PLD_ORT0 EQU 0x40011430 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT1 +CYREG_B1_P2_U0_PLD_ORT1 EQU 0x40011432 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT2 +CYREG_B1_P2_U0_PLD_ORT2 EQU 0x40011434 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_PLD_ORT3 +CYREG_B1_P2_U0_PLD_ORT3 EQU 0x40011436 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_CEN_CONST +CYREG_B1_P2_U0_MC_CFG_CEN_CONST EQU 0x40011438 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_XORFB +CYREG_B1_P2_U0_MC_CFG_XORFB EQU 0x4001143a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_SET_RESET +CYREG_B1_P2_U0_MC_CFG_SET_RESET EQU 0x4001143c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_MC_CFG_BYPASS +CYREG_B1_P2_U0_MC_CFG_BYPASS EQU 0x4001143e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG0 +CYREG_B1_P2_U0_CFG0 EQU 0x40011440 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG1 +CYREG_B1_P2_U0_CFG1 EQU 0x40011441 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG2 +CYREG_B1_P2_U0_CFG2 EQU 0x40011442 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG3 +CYREG_B1_P2_U0_CFG3 EQU 0x40011443 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG4 +CYREG_B1_P2_U0_CFG4 EQU 0x40011444 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG5 +CYREG_B1_P2_U0_CFG5 EQU 0x40011445 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG6 +CYREG_B1_P2_U0_CFG6 EQU 0x40011446 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG7 +CYREG_B1_P2_U0_CFG7 EQU 0x40011447 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG8 +CYREG_B1_P2_U0_CFG8 EQU 0x40011448 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG9 +CYREG_B1_P2_U0_CFG9 EQU 0x40011449 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG10 +CYREG_B1_P2_U0_CFG10 EQU 0x4001144a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG11 +CYREG_B1_P2_U0_CFG11 EQU 0x4001144b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG12 +CYREG_B1_P2_U0_CFG12 EQU 0x4001144c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG13 +CYREG_B1_P2_U0_CFG13 EQU 0x4001144d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG14 +CYREG_B1_P2_U0_CFG14 EQU 0x4001144e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG15 +CYREG_B1_P2_U0_CFG15 EQU 0x4001144f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG16 +CYREG_B1_P2_U0_CFG16 EQU 0x40011450 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG17 +CYREG_B1_P2_U0_CFG17 EQU 0x40011451 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG18 +CYREG_B1_P2_U0_CFG18 EQU 0x40011452 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG19 +CYREG_B1_P2_U0_CFG19 EQU 0x40011453 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG20 +CYREG_B1_P2_U0_CFG20 EQU 0x40011454 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG21 +CYREG_B1_P2_U0_CFG21 EQU 0x40011455 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG22 +CYREG_B1_P2_U0_CFG22 EQU 0x40011456 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG23 +CYREG_B1_P2_U0_CFG23 EQU 0x40011457 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG24 +CYREG_B1_P2_U0_CFG24 EQU 0x40011458 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG25 +CYREG_B1_P2_U0_CFG25 EQU 0x40011459 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG26 +CYREG_B1_P2_U0_CFG26 EQU 0x4001145a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG27 +CYREG_B1_P2_U0_CFG27 EQU 0x4001145b + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG28 +CYREG_B1_P2_U0_CFG28 EQU 0x4001145c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG29 +CYREG_B1_P2_U0_CFG29 EQU 0x4001145d + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG30 +CYREG_B1_P2_U0_CFG30 EQU 0x4001145e + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_CFG31 +CYREG_B1_P2_U0_CFG31 EQU 0x4001145f + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG0 +CYREG_B1_P2_U0_DCFG0 EQU 0x40011460 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG1 +CYREG_B1_P2_U0_DCFG1 EQU 0x40011462 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG2 +CYREG_B1_P2_U0_DCFG2 EQU 0x40011464 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG3 +CYREG_B1_P2_U0_DCFG3 EQU 0x40011466 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG4 +CYREG_B1_P2_U0_DCFG4 EQU 0x40011468 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG5 +CYREG_B1_P2_U0_DCFG5 EQU 0x4001146a + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG6 +CYREG_B1_P2_U0_DCFG6 EQU 0x4001146c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U0_DCFG7 +CYREG_B1_P2_U0_DCFG7 EQU 0x4001146e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_BASE +CYDEV_UCFG_B1_P2_U1_BASE EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_U1_SIZE +CYDEV_UCFG_B1_P2_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT0 +CYREG_B1_P2_U1_PLD_IT0 EQU 0x40011480 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT1 +CYREG_B1_P2_U1_PLD_IT1 EQU 0x40011484 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT2 +CYREG_B1_P2_U1_PLD_IT2 EQU 0x40011488 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT3 +CYREG_B1_P2_U1_PLD_IT3 EQU 0x4001148c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT4 +CYREG_B1_P2_U1_PLD_IT4 EQU 0x40011490 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT5 +CYREG_B1_P2_U1_PLD_IT5 EQU 0x40011494 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT6 +CYREG_B1_P2_U1_PLD_IT6 EQU 0x40011498 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT7 +CYREG_B1_P2_U1_PLD_IT7 EQU 0x4001149c + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT8 +CYREG_B1_P2_U1_PLD_IT8 EQU 0x400114a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT9 +CYREG_B1_P2_U1_PLD_IT9 EQU 0x400114a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT10 +CYREG_B1_P2_U1_PLD_IT10 EQU 0x400114a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_IT11 +CYREG_B1_P2_U1_PLD_IT11 EQU 0x400114ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT0 +CYREG_B1_P2_U1_PLD_ORT0 EQU 0x400114b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT1 +CYREG_B1_P2_U1_PLD_ORT1 EQU 0x400114b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT2 +CYREG_B1_P2_U1_PLD_ORT2 EQU 0x400114b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_PLD_ORT3 +CYREG_B1_P2_U1_PLD_ORT3 EQU 0x400114b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_CEN_CONST +CYREG_B1_P2_U1_MC_CFG_CEN_CONST EQU 0x400114b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_XORFB +CYREG_B1_P2_U1_MC_CFG_XORFB EQU 0x400114ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_SET_RESET +CYREG_B1_P2_U1_MC_CFG_SET_RESET EQU 0x400114bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_MC_CFG_BYPASS +CYREG_B1_P2_U1_MC_CFG_BYPASS EQU 0x400114be + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG0 +CYREG_B1_P2_U1_CFG0 EQU 0x400114c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG1 +CYREG_B1_P2_U1_CFG1 EQU 0x400114c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG2 +CYREG_B1_P2_U1_CFG2 EQU 0x400114c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG3 +CYREG_B1_P2_U1_CFG3 EQU 0x400114c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG4 +CYREG_B1_P2_U1_CFG4 EQU 0x400114c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG5 +CYREG_B1_P2_U1_CFG5 EQU 0x400114c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG6 +CYREG_B1_P2_U1_CFG6 EQU 0x400114c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG7 +CYREG_B1_P2_U1_CFG7 EQU 0x400114c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG8 +CYREG_B1_P2_U1_CFG8 EQU 0x400114c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG9 +CYREG_B1_P2_U1_CFG9 EQU 0x400114c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG10 +CYREG_B1_P2_U1_CFG10 EQU 0x400114ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG11 +CYREG_B1_P2_U1_CFG11 EQU 0x400114cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG12 +CYREG_B1_P2_U1_CFG12 EQU 0x400114cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG13 +CYREG_B1_P2_U1_CFG13 EQU 0x400114cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG14 +CYREG_B1_P2_U1_CFG14 EQU 0x400114ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG15 +CYREG_B1_P2_U1_CFG15 EQU 0x400114cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG16 +CYREG_B1_P2_U1_CFG16 EQU 0x400114d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG17 +CYREG_B1_P2_U1_CFG17 EQU 0x400114d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG18 +CYREG_B1_P2_U1_CFG18 EQU 0x400114d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG19 +CYREG_B1_P2_U1_CFG19 EQU 0x400114d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG20 +CYREG_B1_P2_U1_CFG20 EQU 0x400114d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG21 +CYREG_B1_P2_U1_CFG21 EQU 0x400114d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG22 +CYREG_B1_P2_U1_CFG22 EQU 0x400114d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG23 +CYREG_B1_P2_U1_CFG23 EQU 0x400114d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG24 +CYREG_B1_P2_U1_CFG24 EQU 0x400114d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG25 +CYREG_B1_P2_U1_CFG25 EQU 0x400114d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG26 +CYREG_B1_P2_U1_CFG26 EQU 0x400114da + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG27 +CYREG_B1_P2_U1_CFG27 EQU 0x400114db + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG28 +CYREG_B1_P2_U1_CFG28 EQU 0x400114dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG29 +CYREG_B1_P2_U1_CFG29 EQU 0x400114dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG30 +CYREG_B1_P2_U1_CFG30 EQU 0x400114de + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_CFG31 +CYREG_B1_P2_U1_CFG31 EQU 0x400114df + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG0 +CYREG_B1_P2_U1_DCFG0 EQU 0x400114e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG1 +CYREG_B1_P2_U1_DCFG1 EQU 0x400114e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG2 +CYREG_B1_P2_U1_DCFG2 EQU 0x400114e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG3 +CYREG_B1_P2_U1_DCFG3 EQU 0x400114e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG4 +CYREG_B1_P2_U1_DCFG4 EQU 0x400114e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG5 +CYREG_B1_P2_U1_DCFG5 EQU 0x400114ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG6 +CYREG_B1_P2_U1_DCFG6 EQU 0x400114ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P2_U1_DCFG7 +CYREG_B1_P2_U1_DCFG7 EQU 0x400114ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_BASE +CYDEV_UCFG_B1_P2_ROUTE_BASE EQU 0x40011500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P2_ROUTE_SIZE +CYDEV_UCFG_B1_P2_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_BASE +CYDEV_UCFG_B1_P3_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_SIZE +CYDEV_UCFG_B1_P3_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_BASE +CYDEV_UCFG_B1_P3_U0_BASE EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U0_SIZE +CYDEV_UCFG_B1_P3_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT0 +CYREG_B1_P3_U0_PLD_IT0 EQU 0x40011600 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT1 +CYREG_B1_P3_U0_PLD_IT1 EQU 0x40011604 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT2 +CYREG_B1_P3_U0_PLD_IT2 EQU 0x40011608 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT3 +CYREG_B1_P3_U0_PLD_IT3 EQU 0x4001160c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT4 +CYREG_B1_P3_U0_PLD_IT4 EQU 0x40011610 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT5 +CYREG_B1_P3_U0_PLD_IT5 EQU 0x40011614 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT6 +CYREG_B1_P3_U0_PLD_IT6 EQU 0x40011618 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT7 +CYREG_B1_P3_U0_PLD_IT7 EQU 0x4001161c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT8 +CYREG_B1_P3_U0_PLD_IT8 EQU 0x40011620 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT9 +CYREG_B1_P3_U0_PLD_IT9 EQU 0x40011624 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT10 +CYREG_B1_P3_U0_PLD_IT10 EQU 0x40011628 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_IT11 +CYREG_B1_P3_U0_PLD_IT11 EQU 0x4001162c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT0 +CYREG_B1_P3_U0_PLD_ORT0 EQU 0x40011630 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT1 +CYREG_B1_P3_U0_PLD_ORT1 EQU 0x40011632 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT2 +CYREG_B1_P3_U0_PLD_ORT2 EQU 0x40011634 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_PLD_ORT3 +CYREG_B1_P3_U0_PLD_ORT3 EQU 0x40011636 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_CEN_CONST +CYREG_B1_P3_U0_MC_CFG_CEN_CONST EQU 0x40011638 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_XORFB +CYREG_B1_P3_U0_MC_CFG_XORFB EQU 0x4001163a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_SET_RESET +CYREG_B1_P3_U0_MC_CFG_SET_RESET EQU 0x4001163c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_MC_CFG_BYPASS +CYREG_B1_P3_U0_MC_CFG_BYPASS EQU 0x4001163e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG0 +CYREG_B1_P3_U0_CFG0 EQU 0x40011640 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG1 +CYREG_B1_P3_U0_CFG1 EQU 0x40011641 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG2 +CYREG_B1_P3_U0_CFG2 EQU 0x40011642 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG3 +CYREG_B1_P3_U0_CFG3 EQU 0x40011643 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG4 +CYREG_B1_P3_U0_CFG4 EQU 0x40011644 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG5 +CYREG_B1_P3_U0_CFG5 EQU 0x40011645 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG6 +CYREG_B1_P3_U0_CFG6 EQU 0x40011646 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG7 +CYREG_B1_P3_U0_CFG7 EQU 0x40011647 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG8 +CYREG_B1_P3_U0_CFG8 EQU 0x40011648 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG9 +CYREG_B1_P3_U0_CFG9 EQU 0x40011649 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG10 +CYREG_B1_P3_U0_CFG10 EQU 0x4001164a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG11 +CYREG_B1_P3_U0_CFG11 EQU 0x4001164b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG12 +CYREG_B1_P3_U0_CFG12 EQU 0x4001164c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG13 +CYREG_B1_P3_U0_CFG13 EQU 0x4001164d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG14 +CYREG_B1_P3_U0_CFG14 EQU 0x4001164e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG15 +CYREG_B1_P3_U0_CFG15 EQU 0x4001164f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG16 +CYREG_B1_P3_U0_CFG16 EQU 0x40011650 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG17 +CYREG_B1_P3_U0_CFG17 EQU 0x40011651 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG18 +CYREG_B1_P3_U0_CFG18 EQU 0x40011652 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG19 +CYREG_B1_P3_U0_CFG19 EQU 0x40011653 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG20 +CYREG_B1_P3_U0_CFG20 EQU 0x40011654 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG21 +CYREG_B1_P3_U0_CFG21 EQU 0x40011655 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG22 +CYREG_B1_P3_U0_CFG22 EQU 0x40011656 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG23 +CYREG_B1_P3_U0_CFG23 EQU 0x40011657 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG24 +CYREG_B1_P3_U0_CFG24 EQU 0x40011658 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG25 +CYREG_B1_P3_U0_CFG25 EQU 0x40011659 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG26 +CYREG_B1_P3_U0_CFG26 EQU 0x4001165a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG27 +CYREG_B1_P3_U0_CFG27 EQU 0x4001165b + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG28 +CYREG_B1_P3_U0_CFG28 EQU 0x4001165c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG29 +CYREG_B1_P3_U0_CFG29 EQU 0x4001165d + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG30 +CYREG_B1_P3_U0_CFG30 EQU 0x4001165e + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_CFG31 +CYREG_B1_P3_U0_CFG31 EQU 0x4001165f + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG0 +CYREG_B1_P3_U0_DCFG0 EQU 0x40011660 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG1 +CYREG_B1_P3_U0_DCFG1 EQU 0x40011662 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG2 +CYREG_B1_P3_U0_DCFG2 EQU 0x40011664 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG3 +CYREG_B1_P3_U0_DCFG3 EQU 0x40011666 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG4 +CYREG_B1_P3_U0_DCFG4 EQU 0x40011668 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG5 +CYREG_B1_P3_U0_DCFG5 EQU 0x4001166a + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG6 +CYREG_B1_P3_U0_DCFG6 EQU 0x4001166c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U0_DCFG7 +CYREG_B1_P3_U0_DCFG7 EQU 0x4001166e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_BASE +CYDEV_UCFG_B1_P3_U1_BASE EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_U1_SIZE +CYDEV_UCFG_B1_P3_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT0 +CYREG_B1_P3_U1_PLD_IT0 EQU 0x40011680 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT1 +CYREG_B1_P3_U1_PLD_IT1 EQU 0x40011684 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT2 +CYREG_B1_P3_U1_PLD_IT2 EQU 0x40011688 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT3 +CYREG_B1_P3_U1_PLD_IT3 EQU 0x4001168c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT4 +CYREG_B1_P3_U1_PLD_IT4 EQU 0x40011690 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT5 +CYREG_B1_P3_U1_PLD_IT5 EQU 0x40011694 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT6 +CYREG_B1_P3_U1_PLD_IT6 EQU 0x40011698 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT7 +CYREG_B1_P3_U1_PLD_IT7 EQU 0x4001169c + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT8 +CYREG_B1_P3_U1_PLD_IT8 EQU 0x400116a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT9 +CYREG_B1_P3_U1_PLD_IT9 EQU 0x400116a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT10 +CYREG_B1_P3_U1_PLD_IT10 EQU 0x400116a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_IT11 +CYREG_B1_P3_U1_PLD_IT11 EQU 0x400116ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT0 +CYREG_B1_P3_U1_PLD_ORT0 EQU 0x400116b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT1 +CYREG_B1_P3_U1_PLD_ORT1 EQU 0x400116b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT2 +CYREG_B1_P3_U1_PLD_ORT2 EQU 0x400116b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_PLD_ORT3 +CYREG_B1_P3_U1_PLD_ORT3 EQU 0x400116b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_CEN_CONST +CYREG_B1_P3_U1_MC_CFG_CEN_CONST EQU 0x400116b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_XORFB +CYREG_B1_P3_U1_MC_CFG_XORFB EQU 0x400116ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_SET_RESET +CYREG_B1_P3_U1_MC_CFG_SET_RESET EQU 0x400116bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_MC_CFG_BYPASS +CYREG_B1_P3_U1_MC_CFG_BYPASS EQU 0x400116be + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG0 +CYREG_B1_P3_U1_CFG0 EQU 0x400116c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG1 +CYREG_B1_P3_U1_CFG1 EQU 0x400116c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG2 +CYREG_B1_P3_U1_CFG2 EQU 0x400116c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG3 +CYREG_B1_P3_U1_CFG3 EQU 0x400116c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG4 +CYREG_B1_P3_U1_CFG4 EQU 0x400116c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG5 +CYREG_B1_P3_U1_CFG5 EQU 0x400116c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG6 +CYREG_B1_P3_U1_CFG6 EQU 0x400116c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG7 +CYREG_B1_P3_U1_CFG7 EQU 0x400116c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG8 +CYREG_B1_P3_U1_CFG8 EQU 0x400116c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG9 +CYREG_B1_P3_U1_CFG9 EQU 0x400116c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG10 +CYREG_B1_P3_U1_CFG10 EQU 0x400116ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG11 +CYREG_B1_P3_U1_CFG11 EQU 0x400116cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG12 +CYREG_B1_P3_U1_CFG12 EQU 0x400116cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG13 +CYREG_B1_P3_U1_CFG13 EQU 0x400116cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG14 +CYREG_B1_P3_U1_CFG14 EQU 0x400116ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG15 +CYREG_B1_P3_U1_CFG15 EQU 0x400116cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG16 +CYREG_B1_P3_U1_CFG16 EQU 0x400116d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG17 +CYREG_B1_P3_U1_CFG17 EQU 0x400116d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG18 +CYREG_B1_P3_U1_CFG18 EQU 0x400116d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG19 +CYREG_B1_P3_U1_CFG19 EQU 0x400116d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG20 +CYREG_B1_P3_U1_CFG20 EQU 0x400116d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG21 +CYREG_B1_P3_U1_CFG21 EQU 0x400116d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG22 +CYREG_B1_P3_U1_CFG22 EQU 0x400116d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG23 +CYREG_B1_P3_U1_CFG23 EQU 0x400116d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG24 +CYREG_B1_P3_U1_CFG24 EQU 0x400116d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG25 +CYREG_B1_P3_U1_CFG25 EQU 0x400116d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG26 +CYREG_B1_P3_U1_CFG26 EQU 0x400116da + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG27 +CYREG_B1_P3_U1_CFG27 EQU 0x400116db + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG28 +CYREG_B1_P3_U1_CFG28 EQU 0x400116dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG29 +CYREG_B1_P3_U1_CFG29 EQU 0x400116dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG30 +CYREG_B1_P3_U1_CFG30 EQU 0x400116de + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_CFG31 +CYREG_B1_P3_U1_CFG31 EQU 0x400116df + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG0 +CYREG_B1_P3_U1_DCFG0 EQU 0x400116e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG1 +CYREG_B1_P3_U1_DCFG1 EQU 0x400116e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG2 +CYREG_B1_P3_U1_DCFG2 EQU 0x400116e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG3 +CYREG_B1_P3_U1_DCFG3 EQU 0x400116e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG4 +CYREG_B1_P3_U1_DCFG4 EQU 0x400116e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG5 +CYREG_B1_P3_U1_DCFG5 EQU 0x400116ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG6 +CYREG_B1_P3_U1_DCFG6 EQU 0x400116ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P3_U1_DCFG7 +CYREG_B1_P3_U1_DCFG7 EQU 0x400116ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_BASE +CYDEV_UCFG_B1_P3_ROUTE_BASE EQU 0x40011700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P3_ROUTE_SIZE +CYDEV_UCFG_B1_P3_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_BASE +CYDEV_UCFG_B1_P4_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_SIZE +CYDEV_UCFG_B1_P4_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_BASE +CYDEV_UCFG_B1_P4_U0_BASE EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U0_SIZE +CYDEV_UCFG_B1_P4_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT0 +CYREG_B1_P4_U0_PLD_IT0 EQU 0x40011800 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT1 +CYREG_B1_P4_U0_PLD_IT1 EQU 0x40011804 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT2 +CYREG_B1_P4_U0_PLD_IT2 EQU 0x40011808 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT3 +CYREG_B1_P4_U0_PLD_IT3 EQU 0x4001180c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT4 +CYREG_B1_P4_U0_PLD_IT4 EQU 0x40011810 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT5 +CYREG_B1_P4_U0_PLD_IT5 EQU 0x40011814 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT6 +CYREG_B1_P4_U0_PLD_IT6 EQU 0x40011818 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT7 +CYREG_B1_P4_U0_PLD_IT7 EQU 0x4001181c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT8 +CYREG_B1_P4_U0_PLD_IT8 EQU 0x40011820 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT9 +CYREG_B1_P4_U0_PLD_IT9 EQU 0x40011824 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT10 +CYREG_B1_P4_U0_PLD_IT10 EQU 0x40011828 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_IT11 +CYREG_B1_P4_U0_PLD_IT11 EQU 0x4001182c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT0 +CYREG_B1_P4_U0_PLD_ORT0 EQU 0x40011830 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT1 +CYREG_B1_P4_U0_PLD_ORT1 EQU 0x40011832 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT2 +CYREG_B1_P4_U0_PLD_ORT2 EQU 0x40011834 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_PLD_ORT3 +CYREG_B1_P4_U0_PLD_ORT3 EQU 0x40011836 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_CEN_CONST +CYREG_B1_P4_U0_MC_CFG_CEN_CONST EQU 0x40011838 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_XORFB +CYREG_B1_P4_U0_MC_CFG_XORFB EQU 0x4001183a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_SET_RESET +CYREG_B1_P4_U0_MC_CFG_SET_RESET EQU 0x4001183c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_MC_CFG_BYPASS +CYREG_B1_P4_U0_MC_CFG_BYPASS EQU 0x4001183e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG0 +CYREG_B1_P4_U0_CFG0 EQU 0x40011840 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG1 +CYREG_B1_P4_U0_CFG1 EQU 0x40011841 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG2 +CYREG_B1_P4_U0_CFG2 EQU 0x40011842 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG3 +CYREG_B1_P4_U0_CFG3 EQU 0x40011843 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG4 +CYREG_B1_P4_U0_CFG4 EQU 0x40011844 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG5 +CYREG_B1_P4_U0_CFG5 EQU 0x40011845 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG6 +CYREG_B1_P4_U0_CFG6 EQU 0x40011846 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG7 +CYREG_B1_P4_U0_CFG7 EQU 0x40011847 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG8 +CYREG_B1_P4_U0_CFG8 EQU 0x40011848 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG9 +CYREG_B1_P4_U0_CFG9 EQU 0x40011849 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG10 +CYREG_B1_P4_U0_CFG10 EQU 0x4001184a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG11 +CYREG_B1_P4_U0_CFG11 EQU 0x4001184b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG12 +CYREG_B1_P4_U0_CFG12 EQU 0x4001184c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG13 +CYREG_B1_P4_U0_CFG13 EQU 0x4001184d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG14 +CYREG_B1_P4_U0_CFG14 EQU 0x4001184e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG15 +CYREG_B1_P4_U0_CFG15 EQU 0x4001184f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG16 +CYREG_B1_P4_U0_CFG16 EQU 0x40011850 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG17 +CYREG_B1_P4_U0_CFG17 EQU 0x40011851 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG18 +CYREG_B1_P4_U0_CFG18 EQU 0x40011852 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG19 +CYREG_B1_P4_U0_CFG19 EQU 0x40011853 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG20 +CYREG_B1_P4_U0_CFG20 EQU 0x40011854 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG21 +CYREG_B1_P4_U0_CFG21 EQU 0x40011855 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG22 +CYREG_B1_P4_U0_CFG22 EQU 0x40011856 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG23 +CYREG_B1_P4_U0_CFG23 EQU 0x40011857 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG24 +CYREG_B1_P4_U0_CFG24 EQU 0x40011858 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG25 +CYREG_B1_P4_U0_CFG25 EQU 0x40011859 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG26 +CYREG_B1_P4_U0_CFG26 EQU 0x4001185a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG27 +CYREG_B1_P4_U0_CFG27 EQU 0x4001185b + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG28 +CYREG_B1_P4_U0_CFG28 EQU 0x4001185c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG29 +CYREG_B1_P4_U0_CFG29 EQU 0x4001185d + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG30 +CYREG_B1_P4_U0_CFG30 EQU 0x4001185e + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_CFG31 +CYREG_B1_P4_U0_CFG31 EQU 0x4001185f + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG0 +CYREG_B1_P4_U0_DCFG0 EQU 0x40011860 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG1 +CYREG_B1_P4_U0_DCFG1 EQU 0x40011862 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG2 +CYREG_B1_P4_U0_DCFG2 EQU 0x40011864 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG3 +CYREG_B1_P4_U0_DCFG3 EQU 0x40011866 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG4 +CYREG_B1_P4_U0_DCFG4 EQU 0x40011868 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG5 +CYREG_B1_P4_U0_DCFG5 EQU 0x4001186a + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG6 +CYREG_B1_P4_U0_DCFG6 EQU 0x4001186c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U0_DCFG7 +CYREG_B1_P4_U0_DCFG7 EQU 0x4001186e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_BASE +CYDEV_UCFG_B1_P4_U1_BASE EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_U1_SIZE +CYDEV_UCFG_B1_P4_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT0 +CYREG_B1_P4_U1_PLD_IT0 EQU 0x40011880 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT1 +CYREG_B1_P4_U1_PLD_IT1 EQU 0x40011884 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT2 +CYREG_B1_P4_U1_PLD_IT2 EQU 0x40011888 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT3 +CYREG_B1_P4_U1_PLD_IT3 EQU 0x4001188c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT4 +CYREG_B1_P4_U1_PLD_IT4 EQU 0x40011890 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT5 +CYREG_B1_P4_U1_PLD_IT5 EQU 0x40011894 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT6 +CYREG_B1_P4_U1_PLD_IT6 EQU 0x40011898 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT7 +CYREG_B1_P4_U1_PLD_IT7 EQU 0x4001189c + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT8 +CYREG_B1_P4_U1_PLD_IT8 EQU 0x400118a0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT9 +CYREG_B1_P4_U1_PLD_IT9 EQU 0x400118a4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT10 +CYREG_B1_P4_U1_PLD_IT10 EQU 0x400118a8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_IT11 +CYREG_B1_P4_U1_PLD_IT11 EQU 0x400118ac + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT0 +CYREG_B1_P4_U1_PLD_ORT0 EQU 0x400118b0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT1 +CYREG_B1_P4_U1_PLD_ORT1 EQU 0x400118b2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT2 +CYREG_B1_P4_U1_PLD_ORT2 EQU 0x400118b4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_PLD_ORT3 +CYREG_B1_P4_U1_PLD_ORT3 EQU 0x400118b6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_CEN_CONST +CYREG_B1_P4_U1_MC_CFG_CEN_CONST EQU 0x400118b8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_XORFB +CYREG_B1_P4_U1_MC_CFG_XORFB EQU 0x400118ba + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_SET_RESET +CYREG_B1_P4_U1_MC_CFG_SET_RESET EQU 0x400118bc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_MC_CFG_BYPASS +CYREG_B1_P4_U1_MC_CFG_BYPASS EQU 0x400118be + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG0 +CYREG_B1_P4_U1_CFG0 EQU 0x400118c0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG1 +CYREG_B1_P4_U1_CFG1 EQU 0x400118c1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG2 +CYREG_B1_P4_U1_CFG2 EQU 0x400118c2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG3 +CYREG_B1_P4_U1_CFG3 EQU 0x400118c3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG4 +CYREG_B1_P4_U1_CFG4 EQU 0x400118c4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG5 +CYREG_B1_P4_U1_CFG5 EQU 0x400118c5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG6 +CYREG_B1_P4_U1_CFG6 EQU 0x400118c6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG7 +CYREG_B1_P4_U1_CFG7 EQU 0x400118c7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG8 +CYREG_B1_P4_U1_CFG8 EQU 0x400118c8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG9 +CYREG_B1_P4_U1_CFG9 EQU 0x400118c9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG10 +CYREG_B1_P4_U1_CFG10 EQU 0x400118ca + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG11 +CYREG_B1_P4_U1_CFG11 EQU 0x400118cb + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG12 +CYREG_B1_P4_U1_CFG12 EQU 0x400118cc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG13 +CYREG_B1_P4_U1_CFG13 EQU 0x400118cd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG14 +CYREG_B1_P4_U1_CFG14 EQU 0x400118ce + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG15 +CYREG_B1_P4_U1_CFG15 EQU 0x400118cf + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG16 +CYREG_B1_P4_U1_CFG16 EQU 0x400118d0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG17 +CYREG_B1_P4_U1_CFG17 EQU 0x400118d1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG18 +CYREG_B1_P4_U1_CFG18 EQU 0x400118d2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG19 +CYREG_B1_P4_U1_CFG19 EQU 0x400118d3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG20 +CYREG_B1_P4_U1_CFG20 EQU 0x400118d4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG21 +CYREG_B1_P4_U1_CFG21 EQU 0x400118d5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG22 +CYREG_B1_P4_U1_CFG22 EQU 0x400118d6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG23 +CYREG_B1_P4_U1_CFG23 EQU 0x400118d7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG24 +CYREG_B1_P4_U1_CFG24 EQU 0x400118d8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG25 +CYREG_B1_P4_U1_CFG25 EQU 0x400118d9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG26 +CYREG_B1_P4_U1_CFG26 EQU 0x400118da + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG27 +CYREG_B1_P4_U1_CFG27 EQU 0x400118db + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG28 +CYREG_B1_P4_U1_CFG28 EQU 0x400118dc + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG29 +CYREG_B1_P4_U1_CFG29 EQU 0x400118dd + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG30 +CYREG_B1_P4_U1_CFG30 EQU 0x400118de + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_CFG31 +CYREG_B1_P4_U1_CFG31 EQU 0x400118df + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG0 +CYREG_B1_P4_U1_DCFG0 EQU 0x400118e0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG1 +CYREG_B1_P4_U1_DCFG1 EQU 0x400118e2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG2 +CYREG_B1_P4_U1_DCFG2 EQU 0x400118e4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG3 +CYREG_B1_P4_U1_DCFG3 EQU 0x400118e6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG4 +CYREG_B1_P4_U1_DCFG4 EQU 0x400118e8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG5 +CYREG_B1_P4_U1_DCFG5 EQU 0x400118ea + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG6 +CYREG_B1_P4_U1_DCFG6 EQU 0x400118ec + ENDIF + IF :LNOT::DEF:CYREG_B1_P4_U1_DCFG7 +CYREG_B1_P4_U1_DCFG7 EQU 0x400118ee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_BASE +CYDEV_UCFG_B1_P4_ROUTE_BASE EQU 0x40011900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P4_ROUTE_SIZE +CYDEV_UCFG_B1_P4_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_BASE +CYDEV_UCFG_B1_P5_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_SIZE +CYDEV_UCFG_B1_P5_SIZE EQU 0x000001ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_BASE +CYDEV_UCFG_B1_P5_U0_BASE EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U0_SIZE +CYDEV_UCFG_B1_P5_U0_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT0 +CYREG_B1_P5_U0_PLD_IT0 EQU 0x40011a00 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT1 +CYREG_B1_P5_U0_PLD_IT1 EQU 0x40011a04 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT2 +CYREG_B1_P5_U0_PLD_IT2 EQU 0x40011a08 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT3 +CYREG_B1_P5_U0_PLD_IT3 EQU 0x40011a0c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT4 +CYREG_B1_P5_U0_PLD_IT4 EQU 0x40011a10 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT5 +CYREG_B1_P5_U0_PLD_IT5 EQU 0x40011a14 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT6 +CYREG_B1_P5_U0_PLD_IT6 EQU 0x40011a18 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT7 +CYREG_B1_P5_U0_PLD_IT7 EQU 0x40011a1c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT8 +CYREG_B1_P5_U0_PLD_IT8 EQU 0x40011a20 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT9 +CYREG_B1_P5_U0_PLD_IT9 EQU 0x40011a24 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT10 +CYREG_B1_P5_U0_PLD_IT10 EQU 0x40011a28 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_IT11 +CYREG_B1_P5_U0_PLD_IT11 EQU 0x40011a2c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT0 +CYREG_B1_P5_U0_PLD_ORT0 EQU 0x40011a30 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT1 +CYREG_B1_P5_U0_PLD_ORT1 EQU 0x40011a32 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT2 +CYREG_B1_P5_U0_PLD_ORT2 EQU 0x40011a34 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_PLD_ORT3 +CYREG_B1_P5_U0_PLD_ORT3 EQU 0x40011a36 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_CEN_CONST +CYREG_B1_P5_U0_MC_CFG_CEN_CONST EQU 0x40011a38 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_XORFB +CYREG_B1_P5_U0_MC_CFG_XORFB EQU 0x40011a3a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_SET_RESET +CYREG_B1_P5_U0_MC_CFG_SET_RESET EQU 0x40011a3c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_MC_CFG_BYPASS +CYREG_B1_P5_U0_MC_CFG_BYPASS EQU 0x40011a3e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG0 +CYREG_B1_P5_U0_CFG0 EQU 0x40011a40 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG1 +CYREG_B1_P5_U0_CFG1 EQU 0x40011a41 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG2 +CYREG_B1_P5_U0_CFG2 EQU 0x40011a42 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG3 +CYREG_B1_P5_U0_CFG3 EQU 0x40011a43 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG4 +CYREG_B1_P5_U0_CFG4 EQU 0x40011a44 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG5 +CYREG_B1_P5_U0_CFG5 EQU 0x40011a45 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG6 +CYREG_B1_P5_U0_CFG6 EQU 0x40011a46 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG7 +CYREG_B1_P5_U0_CFG7 EQU 0x40011a47 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG8 +CYREG_B1_P5_U0_CFG8 EQU 0x40011a48 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG9 +CYREG_B1_P5_U0_CFG9 EQU 0x40011a49 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG10 +CYREG_B1_P5_U0_CFG10 EQU 0x40011a4a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG11 +CYREG_B1_P5_U0_CFG11 EQU 0x40011a4b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG12 +CYREG_B1_P5_U0_CFG12 EQU 0x40011a4c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG13 +CYREG_B1_P5_U0_CFG13 EQU 0x40011a4d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG14 +CYREG_B1_P5_U0_CFG14 EQU 0x40011a4e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG15 +CYREG_B1_P5_U0_CFG15 EQU 0x40011a4f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG16 +CYREG_B1_P5_U0_CFG16 EQU 0x40011a50 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG17 +CYREG_B1_P5_U0_CFG17 EQU 0x40011a51 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG18 +CYREG_B1_P5_U0_CFG18 EQU 0x40011a52 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG19 +CYREG_B1_P5_U0_CFG19 EQU 0x40011a53 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG20 +CYREG_B1_P5_U0_CFG20 EQU 0x40011a54 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG21 +CYREG_B1_P5_U0_CFG21 EQU 0x40011a55 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG22 +CYREG_B1_P5_U0_CFG22 EQU 0x40011a56 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG23 +CYREG_B1_P5_U0_CFG23 EQU 0x40011a57 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG24 +CYREG_B1_P5_U0_CFG24 EQU 0x40011a58 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG25 +CYREG_B1_P5_U0_CFG25 EQU 0x40011a59 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG26 +CYREG_B1_P5_U0_CFG26 EQU 0x40011a5a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG27 +CYREG_B1_P5_U0_CFG27 EQU 0x40011a5b + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG28 +CYREG_B1_P5_U0_CFG28 EQU 0x40011a5c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG29 +CYREG_B1_P5_U0_CFG29 EQU 0x40011a5d + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG30 +CYREG_B1_P5_U0_CFG30 EQU 0x40011a5e + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_CFG31 +CYREG_B1_P5_U0_CFG31 EQU 0x40011a5f + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG0 +CYREG_B1_P5_U0_DCFG0 EQU 0x40011a60 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG1 +CYREG_B1_P5_U0_DCFG1 EQU 0x40011a62 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG2 +CYREG_B1_P5_U0_DCFG2 EQU 0x40011a64 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG3 +CYREG_B1_P5_U0_DCFG3 EQU 0x40011a66 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG4 +CYREG_B1_P5_U0_DCFG4 EQU 0x40011a68 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG5 +CYREG_B1_P5_U0_DCFG5 EQU 0x40011a6a + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG6 +CYREG_B1_P5_U0_DCFG6 EQU 0x40011a6c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U0_DCFG7 +CYREG_B1_P5_U0_DCFG7 EQU 0x40011a6e + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_BASE +CYDEV_UCFG_B1_P5_U1_BASE EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_U1_SIZE +CYDEV_UCFG_B1_P5_U1_SIZE EQU 0x00000070 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT0 +CYREG_B1_P5_U1_PLD_IT0 EQU 0x40011a80 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT1 +CYREG_B1_P5_U1_PLD_IT1 EQU 0x40011a84 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT2 +CYREG_B1_P5_U1_PLD_IT2 EQU 0x40011a88 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT3 +CYREG_B1_P5_U1_PLD_IT3 EQU 0x40011a8c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT4 +CYREG_B1_P5_U1_PLD_IT4 EQU 0x40011a90 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT5 +CYREG_B1_P5_U1_PLD_IT5 EQU 0x40011a94 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT6 +CYREG_B1_P5_U1_PLD_IT6 EQU 0x40011a98 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT7 +CYREG_B1_P5_U1_PLD_IT7 EQU 0x40011a9c + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT8 +CYREG_B1_P5_U1_PLD_IT8 EQU 0x40011aa0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT9 +CYREG_B1_P5_U1_PLD_IT9 EQU 0x40011aa4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT10 +CYREG_B1_P5_U1_PLD_IT10 EQU 0x40011aa8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_IT11 +CYREG_B1_P5_U1_PLD_IT11 EQU 0x40011aac + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT0 +CYREG_B1_P5_U1_PLD_ORT0 EQU 0x40011ab0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT1 +CYREG_B1_P5_U1_PLD_ORT1 EQU 0x40011ab2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT2 +CYREG_B1_P5_U1_PLD_ORT2 EQU 0x40011ab4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_PLD_ORT3 +CYREG_B1_P5_U1_PLD_ORT3 EQU 0x40011ab6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_CEN_CONST +CYREG_B1_P5_U1_MC_CFG_CEN_CONST EQU 0x40011ab8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_XORFB +CYREG_B1_P5_U1_MC_CFG_XORFB EQU 0x40011aba + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_SET_RESET +CYREG_B1_P5_U1_MC_CFG_SET_RESET EQU 0x40011abc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_MC_CFG_BYPASS +CYREG_B1_P5_U1_MC_CFG_BYPASS EQU 0x40011abe + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG0 +CYREG_B1_P5_U1_CFG0 EQU 0x40011ac0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG1 +CYREG_B1_P5_U1_CFG1 EQU 0x40011ac1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG2 +CYREG_B1_P5_U1_CFG2 EQU 0x40011ac2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG3 +CYREG_B1_P5_U1_CFG3 EQU 0x40011ac3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG4 +CYREG_B1_P5_U1_CFG4 EQU 0x40011ac4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG5 +CYREG_B1_P5_U1_CFG5 EQU 0x40011ac5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG6 +CYREG_B1_P5_U1_CFG6 EQU 0x40011ac6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG7 +CYREG_B1_P5_U1_CFG7 EQU 0x40011ac7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG8 +CYREG_B1_P5_U1_CFG8 EQU 0x40011ac8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG9 +CYREG_B1_P5_U1_CFG9 EQU 0x40011ac9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG10 +CYREG_B1_P5_U1_CFG10 EQU 0x40011aca + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG11 +CYREG_B1_P5_U1_CFG11 EQU 0x40011acb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG12 +CYREG_B1_P5_U1_CFG12 EQU 0x40011acc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG13 +CYREG_B1_P5_U1_CFG13 EQU 0x40011acd + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG14 +CYREG_B1_P5_U1_CFG14 EQU 0x40011ace + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG15 +CYREG_B1_P5_U1_CFG15 EQU 0x40011acf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG16 +CYREG_B1_P5_U1_CFG16 EQU 0x40011ad0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG17 +CYREG_B1_P5_U1_CFG17 EQU 0x40011ad1 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG18 +CYREG_B1_P5_U1_CFG18 EQU 0x40011ad2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG19 +CYREG_B1_P5_U1_CFG19 EQU 0x40011ad3 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG20 +CYREG_B1_P5_U1_CFG20 EQU 0x40011ad4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG21 +CYREG_B1_P5_U1_CFG21 EQU 0x40011ad5 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG22 +CYREG_B1_P5_U1_CFG22 EQU 0x40011ad6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG23 +CYREG_B1_P5_U1_CFG23 EQU 0x40011ad7 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG24 +CYREG_B1_P5_U1_CFG24 EQU 0x40011ad8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG25 +CYREG_B1_P5_U1_CFG25 EQU 0x40011ad9 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG26 +CYREG_B1_P5_U1_CFG26 EQU 0x40011ada + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG27 +CYREG_B1_P5_U1_CFG27 EQU 0x40011adb + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG28 +CYREG_B1_P5_U1_CFG28 EQU 0x40011adc + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG29 +CYREG_B1_P5_U1_CFG29 EQU 0x40011add + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG30 +CYREG_B1_P5_U1_CFG30 EQU 0x40011ade + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_CFG31 +CYREG_B1_P5_U1_CFG31 EQU 0x40011adf + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG0 +CYREG_B1_P5_U1_DCFG0 EQU 0x40011ae0 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG1 +CYREG_B1_P5_U1_DCFG1 EQU 0x40011ae2 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG2 +CYREG_B1_P5_U1_DCFG2 EQU 0x40011ae4 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG3 +CYREG_B1_P5_U1_DCFG3 EQU 0x40011ae6 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG4 +CYREG_B1_P5_U1_DCFG4 EQU 0x40011ae8 + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG5 +CYREG_B1_P5_U1_DCFG5 EQU 0x40011aea + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG6 +CYREG_B1_P5_U1_DCFG6 EQU 0x40011aec + ENDIF + IF :LNOT::DEF:CYREG_B1_P5_U1_DCFG7 +CYREG_B1_P5_U1_DCFG7 EQU 0x40011aee + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_BASE +CYDEV_UCFG_B1_P5_ROUTE_BASE EQU 0x40011b00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_B1_P5_ROUTE_SIZE +CYDEV_UCFG_B1_P5_ROUTE_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_BASE +CYDEV_UCFG_DSI0_BASE EQU 0x40014000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI0_SIZE +CYDEV_UCFG_DSI0_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_BASE +CYDEV_UCFG_DSI1_BASE EQU 0x40014100 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI1_SIZE +CYDEV_UCFG_DSI1_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_BASE +CYDEV_UCFG_DSI2_BASE EQU 0x40014200 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI2_SIZE +CYDEV_UCFG_DSI2_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_BASE +CYDEV_UCFG_DSI3_BASE EQU 0x40014300 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI3_SIZE +CYDEV_UCFG_DSI3_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_BASE +CYDEV_UCFG_DSI4_BASE EQU 0x40014400 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI4_SIZE +CYDEV_UCFG_DSI4_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_BASE +CYDEV_UCFG_DSI5_BASE EQU 0x40014500 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI5_SIZE +CYDEV_UCFG_DSI5_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_BASE +CYDEV_UCFG_DSI6_BASE EQU 0x40014600 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI6_SIZE +CYDEV_UCFG_DSI6_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_BASE +CYDEV_UCFG_DSI7_BASE EQU 0x40014700 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI7_SIZE +CYDEV_UCFG_DSI7_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_BASE +CYDEV_UCFG_DSI8_BASE EQU 0x40014800 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI8_SIZE +CYDEV_UCFG_DSI8_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_BASE +CYDEV_UCFG_DSI9_BASE EQU 0x40014900 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI9_SIZE +CYDEV_UCFG_DSI9_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_BASE +CYDEV_UCFG_DSI12_BASE EQU 0x40014c00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI12_SIZE +CYDEV_UCFG_DSI12_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_BASE +CYDEV_UCFG_DSI13_BASE EQU 0x40014d00 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_DSI13_SIZE +CYDEV_UCFG_DSI13_SIZE EQU 0x000000ef + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_BASE +CYDEV_UCFG_BCTL0_BASE EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL0_SIZE +CYDEV_UCFG_BCTL0_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MDCLK_EN +CYREG_BCTL0_MDCLK_EN EQU 0x40015000 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_MBCLK_EN +CYREG_BCTL0_MBCLK_EN EQU 0x40015001 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_WAIT_CFG +CYREG_BCTL0_WAIT_CFG EQU 0x40015002 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BANK_CTL +CYREG_BCTL0_BANK_CTL EQU 0x40015003 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_UDB_TEST_3 +CYREG_BCTL0_UDB_TEST_3 EQU 0x40015007 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN0 +CYREG_BCTL0_DCLK_EN0 EQU 0x40015008 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN0 +CYREG_BCTL0_BCLK_EN0 EQU 0x40015009 + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN1 +CYREG_BCTL0_DCLK_EN1 EQU 0x4001500a + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN1 +CYREG_BCTL0_BCLK_EN1 EQU 0x4001500b + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN2 +CYREG_BCTL0_DCLK_EN2 EQU 0x4001500c + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN2 +CYREG_BCTL0_BCLK_EN2 EQU 0x4001500d + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_DCLK_EN3 +CYREG_BCTL0_DCLK_EN3 EQU 0x4001500e + ENDIF + IF :LNOT::DEF:CYREG_BCTL0_BCLK_EN3 +CYREG_BCTL0_BCLK_EN3 EQU 0x4001500f + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_BASE +CYDEV_UCFG_BCTL1_BASE EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYDEV_UCFG_BCTL1_SIZE +CYDEV_UCFG_BCTL1_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MDCLK_EN +CYREG_BCTL1_MDCLK_EN EQU 0x40015010 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_MBCLK_EN +CYREG_BCTL1_MBCLK_EN EQU 0x40015011 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_WAIT_CFG +CYREG_BCTL1_WAIT_CFG EQU 0x40015012 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BANK_CTL +CYREG_BCTL1_BANK_CTL EQU 0x40015013 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_UDB_TEST_3 +CYREG_BCTL1_UDB_TEST_3 EQU 0x40015017 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN0 +CYREG_BCTL1_DCLK_EN0 EQU 0x40015018 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN0 +CYREG_BCTL1_BCLK_EN0 EQU 0x40015019 + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN1 +CYREG_BCTL1_DCLK_EN1 EQU 0x4001501a + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN1 +CYREG_BCTL1_BCLK_EN1 EQU 0x4001501b + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN2 +CYREG_BCTL1_DCLK_EN2 EQU 0x4001501c + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN2 +CYREG_BCTL1_BCLK_EN2 EQU 0x4001501d + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_DCLK_EN3 +CYREG_BCTL1_DCLK_EN3 EQU 0x4001501e + ENDIF + IF :LNOT::DEF:CYREG_BCTL1_BCLK_EN3 +CYREG_BCTL1_BCLK_EN3 EQU 0x4001501f + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_BASE +CYDEV_IDMUX_BASE EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYDEV_IDMUX_SIZE +CYDEV_IDMUX_SIZE EQU 0x00000016 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL0 +CYREG_IDMUX_IRQ_CTL0 EQU 0x40015100 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL1 +CYREG_IDMUX_IRQ_CTL1 EQU 0x40015101 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL2 +CYREG_IDMUX_IRQ_CTL2 EQU 0x40015102 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL3 +CYREG_IDMUX_IRQ_CTL3 EQU 0x40015103 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL4 +CYREG_IDMUX_IRQ_CTL4 EQU 0x40015104 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL5 +CYREG_IDMUX_IRQ_CTL5 EQU 0x40015105 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL6 +CYREG_IDMUX_IRQ_CTL6 EQU 0x40015106 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_IRQ_CTL7 +CYREG_IDMUX_IRQ_CTL7 EQU 0x40015107 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL0 +CYREG_IDMUX_DRQ_CTL0 EQU 0x40015110 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL1 +CYREG_IDMUX_DRQ_CTL1 EQU 0x40015111 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL2 +CYREG_IDMUX_DRQ_CTL2 EQU 0x40015112 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL3 +CYREG_IDMUX_DRQ_CTL3 EQU 0x40015113 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL4 +CYREG_IDMUX_DRQ_CTL4 EQU 0x40015114 + ENDIF + IF :LNOT::DEF:CYREG_IDMUX_DRQ_CTL5 +CYREG_IDMUX_DRQ_CTL5 EQU 0x40015115 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_BASE +CYDEV_CACHERAM_BASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYDEV_CACHERAM_SIZE +CYDEV_CACHERAM_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MBASE +CYREG_CACHERAM_DATA_MBASE EQU 0x40030000 + ENDIF + IF :LNOT::DEF:CYREG_CACHERAM_DATA_MSIZE +CYREG_CACHERAM_DATA_MSIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_BASE +CYDEV_SFR_BASE EQU 0x40050100 + ENDIF + IF :LNOT::DEF:CYDEV_SFR_SIZE +CYDEV_SFR_SIZE EQU 0x000000fb + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0 +CYREG_SFR_GPIO0 EQU 0x40050180 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD0 +CYREG_SFR_GPIRD0 EQU 0x40050189 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO0_SEL +CYREG_SFR_GPIO0_SEL EQU 0x4005018a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1 +CYREG_SFR_GPIO1 EQU 0x40050190 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD1 +CYREG_SFR_GPIRD1 EQU 0x40050191 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2 +CYREG_SFR_GPIO2 EQU 0x40050198 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD2 +CYREG_SFR_GPIRD2 EQU 0x40050199 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO2_SEL +CYREG_SFR_GPIO2_SEL EQU 0x4005019a + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO1_SEL +CYREG_SFR_GPIO1_SEL EQU 0x400501a2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3 +CYREG_SFR_GPIO3 EQU 0x400501b0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD3 +CYREG_SFR_GPIRD3 EQU 0x400501b1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO3_SEL +CYREG_SFR_GPIO3_SEL EQU 0x400501b2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4 +CYREG_SFR_GPIO4 EQU 0x400501c0 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD4 +CYREG_SFR_GPIRD4 EQU 0x400501c1 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO4_SEL +CYREG_SFR_GPIO4_SEL EQU 0x400501c2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5 +CYREG_SFR_GPIO5 EQU 0x400501c8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD5 +CYREG_SFR_GPIRD5 EQU 0x400501c9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO5_SEL +CYREG_SFR_GPIO5_SEL EQU 0x400501ca + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6 +CYREG_SFR_GPIO6 EQU 0x400501d8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD6 +CYREG_SFR_GPIRD6 EQU 0x400501d9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO6_SEL +CYREG_SFR_GPIO6_SEL EQU 0x400501da + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12 +CYREG_SFR_GPIO12 EQU 0x400501e8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD12 +CYREG_SFR_GPIRD12 EQU 0x400501e9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO12_SEL +CYREG_SFR_GPIO12_SEL EQU 0x400501f2 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15 +CYREG_SFR_GPIO15 EQU 0x400501f8 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIRD15 +CYREG_SFR_GPIRD15 EQU 0x400501f9 + ENDIF + IF :LNOT::DEF:CYREG_SFR_GPIO15_SEL +CYREG_SFR_GPIO15_SEL EQU 0x400501fa + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_BASE +CYDEV_P3BA_BASE EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYDEV_P3BA_SIZE +CYDEV_P3BA_SIZE EQU 0x0000002b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_START +CYREG_P3BA_Y_START EQU 0x40050300 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YROLL +CYREG_P3BA_YROLL EQU 0x40050301 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_YCFG +CYREG_P3BA_YCFG EQU 0x40050302 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START1 +CYREG_P3BA_X_START1 EQU 0x40050303 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_START2 +CYREG_P3BA_X_START2 EQU 0x40050304 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL1 +CYREG_P3BA_XROLL1 EQU 0x40050305 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XROLL2 +CYREG_P3BA_XROLL2 EQU 0x40050306 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XINC +CYREG_P3BA_XINC EQU 0x40050307 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_XCFG +CYREG_P3BA_XCFG EQU 0x40050308 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR1 +CYREG_P3BA_OFFSETADDR1 EQU 0x40050309 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR2 +CYREG_P3BA_OFFSETADDR2 EQU 0x4005030a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_OFFSETADDR3 +CYREG_P3BA_OFFSETADDR3 EQU 0x4005030b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR1 +CYREG_P3BA_ABSADDR1 EQU 0x4005030c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR2 +CYREG_P3BA_ABSADDR2 EQU 0x4005030d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR3 +CYREG_P3BA_ABSADDR3 EQU 0x4005030e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_ABSADDR4 +CYREG_P3BA_ABSADDR4 EQU 0x4005030f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG1 +CYREG_P3BA_DATCFG1 EQU 0x40050310 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATCFG2 +CYREG_P3BA_DATCFG2 EQU 0x40050311 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT1 +CYREG_P3BA_CMP_RSLT1 EQU 0x40050314 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT2 +CYREG_P3BA_CMP_RSLT2 EQU 0x40050315 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT3 +CYREG_P3BA_CMP_RSLT3 EQU 0x40050316 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_CMP_RSLT4 +CYREG_P3BA_CMP_RSLT4 EQU 0x40050317 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG1 +CYREG_P3BA_DATA_REG1 EQU 0x40050318 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG2 +CYREG_P3BA_DATA_REG2 EQU 0x40050319 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG3 +CYREG_P3BA_DATA_REG3 EQU 0x4005031a + ENDIF + IF :LNOT::DEF:CYREG_P3BA_DATA_REG4 +CYREG_P3BA_DATA_REG4 EQU 0x4005031b + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA1 +CYREG_P3BA_EXP_DATA1 EQU 0x4005031c + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA2 +CYREG_P3BA_EXP_DATA2 EQU 0x4005031d + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA3 +CYREG_P3BA_EXP_DATA3 EQU 0x4005031e + ENDIF + IF :LNOT::DEF:CYREG_P3BA_EXP_DATA4 +CYREG_P3BA_EXP_DATA4 EQU 0x4005031f + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA1 +CYREG_P3BA_MSTR_HRDATA1 EQU 0x40050320 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA2 +CYREG_P3BA_MSTR_HRDATA2 EQU 0x40050321 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA3 +CYREG_P3BA_MSTR_HRDATA3 EQU 0x40050322 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_MSTR_HRDATA4 +CYREG_P3BA_MSTR_HRDATA4 EQU 0x40050323 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_BIST_EN +CYREG_P3BA_BIST_EN EQU 0x40050324 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_PHUB_MASTER_SSR +CYREG_P3BA_PHUB_MASTER_SSR EQU 0x40050325 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG1 +CYREG_P3BA_SEQCFG1 EQU 0x40050326 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_SEQCFG2 +CYREG_P3BA_SEQCFG2 EQU 0x40050327 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_Y_CURR +CYREG_P3BA_Y_CURR EQU 0x40050328 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR1 +CYREG_P3BA_X_CURR1 EQU 0x40050329 + ENDIF + IF :LNOT::DEF:CYREG_P3BA_X_CURR2 +CYREG_P3BA_X_CURR2 EQU 0x4005032a + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_BASE +CYDEV_PANTHER_BASE EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYDEV_PANTHER_SIZE +CYDEV_PANTHER_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_STCALIB_CFG +CYREG_PANTHER_STCALIB_CFG EQU 0x40080000 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_WAITPIPE +CYREG_PANTHER_WAITPIPE EQU 0x40080004 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_TRACE_CFG +CYREG_PANTHER_TRACE_CFG EQU 0x40080008 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DBG_CFG +CYREG_PANTHER_DBG_CFG EQU 0x4008000c + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_CM3_LCKRST_STAT +CYREG_PANTHER_CM3_LCKRST_STAT EQU 0x40080018 + ENDIF + IF :LNOT::DEF:CYREG_PANTHER_DEVICE_ID +CYREG_PANTHER_DEVICE_ID EQU 0x4008001c + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_BASE +CYDEV_FLSECC_BASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSECC_SIZE +CYDEV_FLSECC_SIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MBASE +CYREG_FLSECC_DATA_MBASE EQU 0x48000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSECC_DATA_MSIZE +CYREG_FLSECC_DATA_MSIZE EQU 0x00008000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_BASE +CYDEV_FLSHID_BASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_SIZE +CYDEV_FLSHID_SIZE EQU 0x00000200 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MBASE +CYREG_FLSHID_RSVD_MBASE EQU 0x49000000 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_RSVD_MSIZE +CYREG_FLSHID_RSVD_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MBASE +CYREG_FLSHID_CUST_MDATA_MBASE EQU 0x49000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_MDATA_MSIZE +CYREG_FLSHID_CUST_MDATA_MSIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_BASE +CYDEV_FLSHID_CUST_TABLES_BASE EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_CUST_TABLES_SIZE +CYDEV_FLSHID_CUST_TABLES_SIZE EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_Y_LOC +CYREG_FLSHID_CUST_TABLES_Y_LOC EQU 0x49000100 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_X_LOC +CYREG_FLSHID_CUST_TABLES_X_LOC EQU 0x49000101 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WAFER_NUM +CYREG_FLSHID_CUST_TABLES_WAFER_NUM EQU 0x49000102 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_LSB +CYREG_FLSHID_CUST_TABLES_LOT_LSB EQU 0x49000103 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_LOT_MSB +CYREG_FLSHID_CUST_TABLES_LOT_MSB EQU 0x49000104 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_WRK_WK +CYREG_FLSHID_CUST_TABLES_WRK_WK EQU 0x49000105 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_FAB_YR +CYREG_FLSHID_CUST_TABLES_FAB_YR EQU 0x49000106 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_MINOR +CYREG_FLSHID_CUST_TABLES_MINOR EQU 0x49000107 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_3MHZ +CYREG_FLSHID_CUST_TABLES_IMO_3MHZ EQU 0x49000108 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_6MHZ +CYREG_FLSHID_CUST_TABLES_IMO_6MHZ EQU 0x49000109 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_12MHZ +CYREG_FLSHID_CUST_TABLES_IMO_12MHZ EQU 0x4900010a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_24MHZ +CYREG_FLSHID_CUST_TABLES_IMO_24MHZ EQU 0x4900010b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_67MHZ +CYREG_FLSHID_CUST_TABLES_IMO_67MHZ EQU 0x4900010c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_80MHZ +CYREG_FLSHID_CUST_TABLES_IMO_80MHZ EQU 0x4900010d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_92MHZ +CYREG_FLSHID_CUST_TABLES_IMO_92MHZ EQU 0x4900010e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_IMO_USB +CYREG_FLSHID_CUST_TABLES_IMO_USB EQU 0x4900010f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR0_HS EQU 0x49000110 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR0_HS EQU 0x49000111 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR0_HS EQU 0x49000112 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR0_HS EQU 0x49000113 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP0_TR1_HS EQU 0x49000114 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP1_TR1_HS EQU 0x49000115 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP2_TR1_HS EQU 0x49000116 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS +CYREG_FLSHID_CUST_TABLES_CMP3_TR1_HS EQU 0x49000117 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M1 +CYREG_FLSHID_CUST_TABLES_DEC_M1 EQU 0x49000118 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M2 +CYREG_FLSHID_CUST_TABLES_DEC_M2 EQU 0x49000119 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M3 +CYREG_FLSHID_CUST_TABLES_DEC_M3 EQU 0x4900011a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M4 +CYREG_FLSHID_CUST_TABLES_DEC_M4 EQU 0x4900011b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M5 +CYREG_FLSHID_CUST_TABLES_DEC_M5 EQU 0x4900011c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M6 +CYREG_FLSHID_CUST_TABLES_DEC_M6 EQU 0x4900011d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M7 +CYREG_FLSHID_CUST_TABLES_DEC_M7 EQU 0x4900011e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DEC_M8 +CYREG_FLSHID_CUST_TABLES_DEC_M8 EQU 0x4900011f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M1 +CYREG_FLSHID_CUST_TABLES_DAC0_M1 EQU 0x49000120 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M2 +CYREG_FLSHID_CUST_TABLES_DAC0_M2 EQU 0x49000121 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M3 +CYREG_FLSHID_CUST_TABLES_DAC0_M3 EQU 0x49000122 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M4 +CYREG_FLSHID_CUST_TABLES_DAC0_M4 EQU 0x49000123 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M5 +CYREG_FLSHID_CUST_TABLES_DAC0_M5 EQU 0x49000124 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M6 +CYREG_FLSHID_CUST_TABLES_DAC0_M6 EQU 0x49000125 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M7 +CYREG_FLSHID_CUST_TABLES_DAC0_M7 EQU 0x49000126 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC0_M8 +CYREG_FLSHID_CUST_TABLES_DAC0_M8 EQU 0x49000127 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M1 +CYREG_FLSHID_CUST_TABLES_DAC2_M1 EQU 0x49000128 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M2 +CYREG_FLSHID_CUST_TABLES_DAC2_M2 EQU 0x49000129 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M3 +CYREG_FLSHID_CUST_TABLES_DAC2_M3 EQU 0x4900012a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M4 +CYREG_FLSHID_CUST_TABLES_DAC2_M4 EQU 0x4900012b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M5 +CYREG_FLSHID_CUST_TABLES_DAC2_M5 EQU 0x4900012c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M6 +CYREG_FLSHID_CUST_TABLES_DAC2_M6 EQU 0x4900012d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M7 +CYREG_FLSHID_CUST_TABLES_DAC2_M7 EQU 0x4900012e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC2_M8 +CYREG_FLSHID_CUST_TABLES_DAC2_M8 EQU 0x4900012f + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M1 +CYREG_FLSHID_CUST_TABLES_DAC1_M1 EQU 0x49000130 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M2 +CYREG_FLSHID_CUST_TABLES_DAC1_M2 EQU 0x49000131 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M3 +CYREG_FLSHID_CUST_TABLES_DAC1_M3 EQU 0x49000132 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M4 +CYREG_FLSHID_CUST_TABLES_DAC1_M4 EQU 0x49000133 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M5 +CYREG_FLSHID_CUST_TABLES_DAC1_M5 EQU 0x49000134 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M6 +CYREG_FLSHID_CUST_TABLES_DAC1_M6 EQU 0x49000135 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M7 +CYREG_FLSHID_CUST_TABLES_DAC1_M7 EQU 0x49000136 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC1_M8 +CYREG_FLSHID_CUST_TABLES_DAC1_M8 EQU 0x49000137 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M1 +CYREG_FLSHID_CUST_TABLES_DAC3_M1 EQU 0x49000138 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M2 +CYREG_FLSHID_CUST_TABLES_DAC3_M2 EQU 0x49000139 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M3 +CYREG_FLSHID_CUST_TABLES_DAC3_M3 EQU 0x4900013a + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M4 +CYREG_FLSHID_CUST_TABLES_DAC3_M4 EQU 0x4900013b + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M5 +CYREG_FLSHID_CUST_TABLES_DAC3_M5 EQU 0x4900013c + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M6 +CYREG_FLSHID_CUST_TABLES_DAC3_M6 EQU 0x4900013d + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M7 +CYREG_FLSHID_CUST_TABLES_DAC3_M7 EQU 0x4900013e + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_CUST_TABLES_DAC3_M8 +CYREG_FLSHID_CUST_TABLES_DAC3_M8 EQU 0x4900013f + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_BASE +CYDEV_FLSHID_MFG_CFG_BASE EQU 0x49000180 + ENDIF + IF :LNOT::DEF:CYDEV_FLSHID_MFG_CFG_SIZE +CYDEV_FLSHID_MFG_CFG_SIZE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_IMO_TR1 +CYREG_FLSHID_MFG_CFG_IMO_TR1 EQU 0x49000188 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR0 +CYREG_FLSHID_MFG_CFG_CMP0_TR0 EQU 0x490001ac + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR0 +CYREG_FLSHID_MFG_CFG_CMP1_TR0 EQU 0x490001ae + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR0 +CYREG_FLSHID_MFG_CFG_CMP2_TR0 EQU 0x490001b0 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR0 +CYREG_FLSHID_MFG_CFG_CMP3_TR0 EQU 0x490001b2 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP0_TR1 +CYREG_FLSHID_MFG_CFG_CMP0_TR1 EQU 0x490001b4 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP1_TR1 +CYREG_FLSHID_MFG_CFG_CMP1_TR1 EQU 0x490001b6 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP2_TR1 +CYREG_FLSHID_MFG_CFG_CMP2_TR1 EQU 0x490001b8 + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_CMP3_TR1 +CYREG_FLSHID_MFG_CFG_CMP3_TR1 EQU 0x490001ba + ENDIF + IF :LNOT::DEF:CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM +CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM EQU 0x490001ce + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_BASE +CYDEV_EXTMEM_BASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYDEV_EXTMEM_SIZE +CYDEV_EXTMEM_SIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MBASE +CYREG_EXTMEM_DATA_MBASE EQU 0x60000000 + ENDIF + IF :LNOT::DEF:CYREG_EXTMEM_DATA_MSIZE +CYREG_EXTMEM_DATA_MSIZE EQU 0x00800000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_BASE +CYDEV_ITM_BASE EQU 0xe0000000 + ENDIF + IF :LNOT::DEF:CYDEV_ITM_SIZE +CYDEV_ITM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_EN +CYREG_ITM_TRACE_EN EQU 0xe0000e00 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_PRIVILEGE +CYREG_ITM_TRACE_PRIVILEGE EQU 0xe0000e40 + ENDIF + IF :LNOT::DEF:CYREG_ITM_TRACE_CTRL +CYREG_ITM_TRACE_CTRL EQU 0xe0000e80 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_ACCESS +CYREG_ITM_LOCK_ACCESS EQU 0xe0000fb0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_LOCK_STATUS +CYREG_ITM_LOCK_STATUS EQU 0xe0000fb4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID4 +CYREG_ITM_PID4 EQU 0xe0000fd0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID5 +CYREG_ITM_PID5 EQU 0xe0000fd4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID6 +CYREG_ITM_PID6 EQU 0xe0000fd8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID7 +CYREG_ITM_PID7 EQU 0xe0000fdc + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID0 +CYREG_ITM_PID0 EQU 0xe0000fe0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID1 +CYREG_ITM_PID1 EQU 0xe0000fe4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID2 +CYREG_ITM_PID2 EQU 0xe0000fe8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_PID3 +CYREG_ITM_PID3 EQU 0xe0000fec + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID0 +CYREG_ITM_CID0 EQU 0xe0000ff0 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID1 +CYREG_ITM_CID1 EQU 0xe0000ff4 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID2 +CYREG_ITM_CID2 EQU 0xe0000ff8 + ENDIF + IF :LNOT::DEF:CYREG_ITM_CID3 +CYREG_ITM_CID3 EQU 0xe0000ffc + ENDIF + IF :LNOT::DEF:CYDEV_DWT_BASE +CYDEV_DWT_BASE EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYDEV_DWT_SIZE +CYDEV_DWT_SIZE EQU 0x0000005c + ENDIF + IF :LNOT::DEF:CYREG_DWT_CTRL +CYREG_DWT_CTRL EQU 0xe0001000 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CYCLE_COUNT +CYREG_DWT_CYCLE_COUNT EQU 0xe0001004 + ENDIF + IF :LNOT::DEF:CYREG_DWT_CPI_COUNT +CYREG_DWT_CPI_COUNT EQU 0xe0001008 + ENDIF + IF :LNOT::DEF:CYREG_DWT_EXC_OVHD_COUNT +CYREG_DWT_EXC_OVHD_COUNT EQU 0xe000100c + ENDIF + IF :LNOT::DEF:CYREG_DWT_SLEEP_COUNT +CYREG_DWT_SLEEP_COUNT EQU 0xe0001010 + ENDIF + IF :LNOT::DEF:CYREG_DWT_LSU_COUNT +CYREG_DWT_LSU_COUNT EQU 0xe0001014 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FOLD_COUNT +CYREG_DWT_FOLD_COUNT EQU 0xe0001018 + ENDIF + IF :LNOT::DEF:CYREG_DWT_PC_SAMPLE +CYREG_DWT_PC_SAMPLE EQU 0xe000101c + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_0 +CYREG_DWT_COMP_0 EQU 0xe0001020 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_0 +CYREG_DWT_MASK_0 EQU 0xe0001024 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_0 +CYREG_DWT_FUNCTION_0 EQU 0xe0001028 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_1 +CYREG_DWT_COMP_1 EQU 0xe0001030 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_1 +CYREG_DWT_MASK_1 EQU 0xe0001034 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_1 +CYREG_DWT_FUNCTION_1 EQU 0xe0001038 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_2 +CYREG_DWT_COMP_2 EQU 0xe0001040 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_2 +CYREG_DWT_MASK_2 EQU 0xe0001044 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_2 +CYREG_DWT_FUNCTION_2 EQU 0xe0001048 + ENDIF + IF :LNOT::DEF:CYREG_DWT_COMP_3 +CYREG_DWT_COMP_3 EQU 0xe0001050 + ENDIF + IF :LNOT::DEF:CYREG_DWT_MASK_3 +CYREG_DWT_MASK_3 EQU 0xe0001054 + ENDIF + IF :LNOT::DEF:CYREG_DWT_FUNCTION_3 +CYREG_DWT_FUNCTION_3 EQU 0xe0001058 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_BASE +CYDEV_FPB_BASE EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYDEV_FPB_SIZE +CYDEV_FPB_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CTRL +CYREG_FPB_CTRL EQU 0xe0002000 + ENDIF + IF :LNOT::DEF:CYREG_FPB_REMAP +CYREG_FPB_REMAP EQU 0xe0002004 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_0 +CYREG_FPB_FP_COMP_0 EQU 0xe0002008 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_1 +CYREG_FPB_FP_COMP_1 EQU 0xe000200c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_2 +CYREG_FPB_FP_COMP_2 EQU 0xe0002010 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_3 +CYREG_FPB_FP_COMP_3 EQU 0xe0002014 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_4 +CYREG_FPB_FP_COMP_4 EQU 0xe0002018 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_5 +CYREG_FPB_FP_COMP_5 EQU 0xe000201c + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_6 +CYREG_FPB_FP_COMP_6 EQU 0xe0002020 + ENDIF + IF :LNOT::DEF:CYREG_FPB_FP_COMP_7 +CYREG_FPB_FP_COMP_7 EQU 0xe0002024 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID4 +CYREG_FPB_PID4 EQU 0xe0002fd0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID5 +CYREG_FPB_PID5 EQU 0xe0002fd4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID6 +CYREG_FPB_PID6 EQU 0xe0002fd8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID7 +CYREG_FPB_PID7 EQU 0xe0002fdc + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID0 +CYREG_FPB_PID0 EQU 0xe0002fe0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID1 +CYREG_FPB_PID1 EQU 0xe0002fe4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID2 +CYREG_FPB_PID2 EQU 0xe0002fe8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_PID3 +CYREG_FPB_PID3 EQU 0xe0002fec + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID0 +CYREG_FPB_CID0 EQU 0xe0002ff0 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID1 +CYREG_FPB_CID1 EQU 0xe0002ff4 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID2 +CYREG_FPB_CID2 EQU 0xe0002ff8 + ENDIF + IF :LNOT::DEF:CYREG_FPB_CID3 +CYREG_FPB_CID3 EQU 0xe0002ffc + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_BASE +CYDEV_NVIC_BASE EQU 0xe000e000 + ENDIF + IF :LNOT::DEF:CYDEV_NVIC_SIZE +CYDEV_NVIC_SIZE EQU 0x00000d3c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INT_CTL_TYPE +CYREG_NVIC_INT_CTL_TYPE EQU 0xe000e004 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CTL +CYREG_NVIC_SYSTICK_CTL EQU 0xe000e010 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_RELOAD +CYREG_NVIC_SYSTICK_RELOAD EQU 0xe000e014 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CURRENT +CYREG_NVIC_SYSTICK_CURRENT EQU 0xe000e018 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTICK_CAL +CYREG_NVIC_SYSTICK_CAL EQU 0xe000e01c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETENA0 +CYREG_NVIC_SETENA0 EQU 0xe000e100 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRENA0 +CYREG_NVIC_CLRENA0 EQU 0xe000e180 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SETPEND0 +CYREG_NVIC_SETPEND0 EQU 0xe000e200 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CLRPEND0 +CYREG_NVIC_CLRPEND0 EQU 0xe000e280 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_ACTIVE0 +CYREG_NVIC_ACTIVE0 EQU 0xe000e300 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_0 +CYREG_NVIC_PRI_0 EQU 0xe000e400 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_1 +CYREG_NVIC_PRI_1 EQU 0xe000e401 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_2 +CYREG_NVIC_PRI_2 EQU 0xe000e402 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_3 +CYREG_NVIC_PRI_3 EQU 0xe000e403 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_4 +CYREG_NVIC_PRI_4 EQU 0xe000e404 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_5 +CYREG_NVIC_PRI_5 EQU 0xe000e405 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_6 +CYREG_NVIC_PRI_6 EQU 0xe000e406 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_7 +CYREG_NVIC_PRI_7 EQU 0xe000e407 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_8 +CYREG_NVIC_PRI_8 EQU 0xe000e408 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_9 +CYREG_NVIC_PRI_9 EQU 0xe000e409 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_10 +CYREG_NVIC_PRI_10 EQU 0xe000e40a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_11 +CYREG_NVIC_PRI_11 EQU 0xe000e40b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_12 +CYREG_NVIC_PRI_12 EQU 0xe000e40c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_13 +CYREG_NVIC_PRI_13 EQU 0xe000e40d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_14 +CYREG_NVIC_PRI_14 EQU 0xe000e40e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_15 +CYREG_NVIC_PRI_15 EQU 0xe000e40f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_16 +CYREG_NVIC_PRI_16 EQU 0xe000e410 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_17 +CYREG_NVIC_PRI_17 EQU 0xe000e411 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_18 +CYREG_NVIC_PRI_18 EQU 0xe000e412 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_19 +CYREG_NVIC_PRI_19 EQU 0xe000e413 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_20 +CYREG_NVIC_PRI_20 EQU 0xe000e414 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_21 +CYREG_NVIC_PRI_21 EQU 0xe000e415 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_22 +CYREG_NVIC_PRI_22 EQU 0xe000e416 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_23 +CYREG_NVIC_PRI_23 EQU 0xe000e417 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_24 +CYREG_NVIC_PRI_24 EQU 0xe000e418 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_25 +CYREG_NVIC_PRI_25 EQU 0xe000e419 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_26 +CYREG_NVIC_PRI_26 EQU 0xe000e41a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_27 +CYREG_NVIC_PRI_27 EQU 0xe000e41b + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_28 +CYREG_NVIC_PRI_28 EQU 0xe000e41c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_29 +CYREG_NVIC_PRI_29 EQU 0xe000e41d + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_30 +CYREG_NVIC_PRI_30 EQU 0xe000e41e + ENDIF + IF :LNOT::DEF:CYREG_NVIC_PRI_31 +CYREG_NVIC_PRI_31 EQU 0xe000e41f + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CPUID_BASE +CYREG_NVIC_CPUID_BASE EQU 0xe000ed00 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_INTR_CTRL_STATE +CYREG_NVIC_INTR_CTRL_STATE EQU 0xe000ed04 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_VECT_OFFSET +CYREG_NVIC_VECT_OFFSET EQU 0xe000ed08 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_APPLN_INTR +CYREG_NVIC_APPLN_INTR EQU 0xe000ed0c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYSTEM_CONTROL +CYREG_NVIC_SYSTEM_CONTROL EQU 0xe000ed10 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_CFG_CONTROL +CYREG_NVIC_CFG_CONTROL EQU 0xe000ed14 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_4_7 +CYREG_NVIC_SYS_PRIO_HANDLER_4_7 EQU 0xe000ed18 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_8_11 +CYREG_NVIC_SYS_PRIO_HANDLER_8_11 EQU 0xe000ed1c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_PRIO_HANDLER_12_15 +CYREG_NVIC_SYS_PRIO_HANDLER_12_15 EQU 0xe000ed20 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_SYS_HANDLER_CSR +CYREG_NVIC_SYS_HANDLER_CSR EQU 0xe000ed24 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_STATUS +CYREG_NVIC_MEMMAN_FAULT_STATUS EQU 0xe000ed28 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_STATUS +CYREG_NVIC_BUS_FAULT_STATUS EQU 0xe000ed29 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_USAGE_FAULT_STATUS +CYREG_NVIC_USAGE_FAULT_STATUS EQU 0xe000ed2a + ENDIF + IF :LNOT::DEF:CYREG_NVIC_HARD_FAULT_STATUS +CYREG_NVIC_HARD_FAULT_STATUS EQU 0xe000ed2c + ENDIF + IF :LNOT::DEF:CYREG_NVIC_DEBUG_FAULT_STATUS +CYREG_NVIC_DEBUG_FAULT_STATUS EQU 0xe000ed30 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_MEMMAN_FAULT_ADD +CYREG_NVIC_MEMMAN_FAULT_ADD EQU 0xe000ed34 + ENDIF + IF :LNOT::DEF:CYREG_NVIC_BUS_FAULT_ADD +CYREG_NVIC_BUS_FAULT_ADD EQU 0xe000ed38 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_BASE +CYDEV_CORE_DBG_BASE EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYDEV_CORE_DBG_SIZE +CYDEV_CORE_DBG_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_HLT_CS +CYREG_CORE_DBG_DBG_HLT_CS EQU 0xe000edf0 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_SEL +CYREG_CORE_DBG_DBG_REG_SEL EQU 0xe000edf4 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_DBG_REG_DATA +CYREG_CORE_DBG_DBG_REG_DATA EQU 0xe000edf8 + ENDIF + IF :LNOT::DEF:CYREG_CORE_DBG_EXC_MON_CTL +CYREG_CORE_DBG_EXC_MON_CTL EQU 0xe000edfc + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_BASE +CYDEV_TPIU_BASE EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYDEV_TPIU_SIZE +CYDEV_TPIU_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ +CYREG_TPIU_SUPPORTED_SYNC_PRT_SZ EQU 0xe0040000 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CURRENT_SYNC_PRT_SZ +CYREG_TPIU_CURRENT_SYNC_PRT_SZ EQU 0xe0040004 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ASYNC_CLK_PRESCALER +CYREG_TPIU_ASYNC_CLK_PRESCALER EQU 0xe0040010 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PROTOCOL +CYREG_TPIU_PROTOCOL EQU 0xe00400f0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_STAT +CYREG_TPIU_FORM_FLUSH_STAT EQU 0xe0040300 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_FORM_FLUSH_CTRL +CYREG_TPIU_FORM_FLUSH_CTRL EQU 0xe0040304 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_TRIGGER +CYREG_TPIU_TRIGGER EQU 0xe0040ee8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITETMDATA +CYREG_TPIU_ITETMDATA EQU 0xe0040eec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR2 +CYREG_TPIU_ITATBCTR2 EQU 0xe0040ef0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITATBCTR0 +CYREG_TPIU_ITATBCTR0 EQU 0xe0040ef8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITITMDATA +CYREG_TPIU_ITITMDATA EQU 0xe0040efc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_ITCTRL +CYREG_TPIU_ITCTRL EQU 0xe0040f00 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVID +CYREG_TPIU_DEVID EQU 0xe0040fc8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_DEVTYPE +CYREG_TPIU_DEVTYPE EQU 0xe0040fcc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID4 +CYREG_TPIU_PID4 EQU 0xe0040fd0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID5 +CYREG_TPIU_PID5 EQU 0xe0040fd4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID6 +CYREG_TPIU_PID6 EQU 0xe0040fd8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID7 +CYREG_TPIU_PID7 EQU 0xe0040fdc + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID0 +CYREG_TPIU_PID0 EQU 0xe0040fe0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID1 +CYREG_TPIU_PID1 EQU 0xe0040fe4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID2 +CYREG_TPIU_PID2 EQU 0xe0040fe8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_PID3 +CYREG_TPIU_PID3 EQU 0xe0040fec + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID0 +CYREG_TPIU_CID0 EQU 0xe0040ff0 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID1 +CYREG_TPIU_CID1 EQU 0xe0040ff4 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID2 +CYREG_TPIU_CID2 EQU 0xe0040ff8 + ENDIF + IF :LNOT::DEF:CYREG_TPIU_CID3 +CYREG_TPIU_CID3 EQU 0xe0040ffc + ENDIF + IF :LNOT::DEF:CYDEV_ETM_BASE +CYDEV_ETM_BASE EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYDEV_ETM_SIZE +CYDEV_ETM_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CTL +CYREG_ETM_CTL EQU 0xe0041000 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE +CYREG_ETM_CFG_CODE EQU 0xe0041004 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRIG_EVENT +CYREG_ETM_TRIG_EVENT EQU 0xe0041008 + ENDIF + IF :LNOT::DEF:CYREG_ETM_STATUS +CYREG_ETM_STATUS EQU 0xe0041010 + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYS_CFG +CYREG_ETM_SYS_CFG EQU 0xe0041014 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_ENB_EVENT +CYREG_ETM_TRACE_ENB_EVENT EQU 0xe0041020 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TRACE_EN_CTRL1 +CYREG_ETM_TRACE_EN_CTRL1 EQU 0xe0041024 + ENDIF + IF :LNOT::DEF:CYREG_ETM_FIFOFULL_LEVEL +CYREG_ETM_FIFOFULL_LEVEL EQU 0xe004102c + ENDIF + IF :LNOT::DEF:CYREG_ETM_SYNC_FREQ +CYREG_ETM_SYNC_FREQ EQU 0xe00411e0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ETM_ID +CYREG_ETM_ETM_ID EQU 0xe00411e4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CFG_CODE_EXT +CYREG_ETM_CFG_CODE_EXT EQU 0xe00411e8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_TR_SS_EMBICE_CTRL +CYREG_ETM_TR_SS_EMBICE_CTRL EQU 0xe00411f0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CS_TRACE_ID +CYREG_ETM_CS_TRACE_ID EQU 0xe0041200 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_ACCESS +CYREG_ETM_OS_LOCK_ACCESS EQU 0xe0041300 + ENDIF + IF :LNOT::DEF:CYREG_ETM_OS_LOCK_STATUS +CYREG_ETM_OS_LOCK_STATUS EQU 0xe0041304 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PDSR +CYREG_ETM_PDSR EQU 0xe0041314 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITMISCIN +CYREG_ETM_ITMISCIN EQU 0xe0041ee0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITTRIGOUT +CYREG_ETM_ITTRIGOUT EQU 0xe0041ee8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR2 +CYREG_ETM_ITATBCTR2 EQU 0xe0041ef0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_ITATBCTR0 +CYREG_ETM_ITATBCTR0 EQU 0xe0041ef8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_INT_MODE_CTRL +CYREG_ETM_INT_MODE_CTRL EQU 0xe0041f00 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_SET +CYREG_ETM_CLM_TAG_SET EQU 0xe0041fa0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CLM_TAG_CLR +CYREG_ETM_CLM_TAG_CLR EQU 0xe0041fa4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_ACCESS +CYREG_ETM_LOCK_ACCESS EQU 0xe0041fb0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_LOCK_STATUS +CYREG_ETM_LOCK_STATUS EQU 0xe0041fb4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_AUTH_STATUS +CYREG_ETM_AUTH_STATUS EQU 0xe0041fb8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_DEV_TYPE +CYREG_ETM_DEV_TYPE EQU 0xe0041fcc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID4 +CYREG_ETM_PID4 EQU 0xe0041fd0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID5 +CYREG_ETM_PID5 EQU 0xe0041fd4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID6 +CYREG_ETM_PID6 EQU 0xe0041fd8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID7 +CYREG_ETM_PID7 EQU 0xe0041fdc + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID0 +CYREG_ETM_PID0 EQU 0xe0041fe0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID1 +CYREG_ETM_PID1 EQU 0xe0041fe4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID2 +CYREG_ETM_PID2 EQU 0xe0041fe8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_PID3 +CYREG_ETM_PID3 EQU 0xe0041fec + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID0 +CYREG_ETM_CID0 EQU 0xe0041ff0 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID1 +CYREG_ETM_CID1 EQU 0xe0041ff4 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID2 +CYREG_ETM_CID2 EQU 0xe0041ff8 + ENDIF + IF :LNOT::DEF:CYREG_ETM_CID3 +CYREG_ETM_CID3 EQU 0xe0041ffc + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_BASE +CYDEV_ROM_TABLE_BASE EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYDEV_ROM_TABLE_SIZE +CYDEV_ROM_TABLE_SIZE EQU 0x00001000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_NVIC +CYREG_ROM_TABLE_NVIC EQU 0xe00ff000 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_DWT +CYREG_ROM_TABLE_DWT EQU 0xe00ff004 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_FPB +CYREG_ROM_TABLE_FPB EQU 0xe00ff008 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ITM +CYREG_ROM_TABLE_ITM EQU 0xe00ff00c + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_TPIU +CYREG_ROM_TABLE_TPIU EQU 0xe00ff010 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_ETM +CYREG_ROM_TABLE_ETM EQU 0xe00ff014 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_END +CYREG_ROM_TABLE_END EQU 0xe00ff018 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_MEMTYPE +CYREG_ROM_TABLE_MEMTYPE EQU 0xe00fffcc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID4 +CYREG_ROM_TABLE_PID4 EQU 0xe00fffd0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID5 +CYREG_ROM_TABLE_PID5 EQU 0xe00fffd4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID6 +CYREG_ROM_TABLE_PID6 EQU 0xe00fffd8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID7 +CYREG_ROM_TABLE_PID7 EQU 0xe00fffdc + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID0 +CYREG_ROM_TABLE_PID0 EQU 0xe00fffe0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID1 +CYREG_ROM_TABLE_PID1 EQU 0xe00fffe4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID2 +CYREG_ROM_TABLE_PID2 EQU 0xe00fffe8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_PID3 +CYREG_ROM_TABLE_PID3 EQU 0xe00fffec + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID0 +CYREG_ROM_TABLE_CID0 EQU 0xe00ffff0 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID1 +CYREG_ROM_TABLE_CID1 EQU 0xe00ffff4 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID2 +CYREG_ROM_TABLE_CID2 EQU 0xe00ffff8 + ENDIF + IF :LNOT::DEF:CYREG_ROM_TABLE_CID3 +CYREG_ROM_TABLE_CID3 EQU 0xe00ffffc + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SIZE +CYDEV_FLS_SIZE EQU CYDEV_FLASH_SIZE + ENDIF + IF :LNOT::DEF:CYDEV_ECC_BASE +CYDEV_ECC_BASE EQU CYDEV_FLSECC_BASE + ENDIF + IF :LNOT::DEF:CYDEV_FLS_SECTOR_SIZE +CYDEV_FLS_SECTOR_SIZE EQU 0x00010000 + ENDIF + IF :LNOT::DEF:CYDEV_FLS_ROW_SIZE +CYDEV_FLS_ROW_SIZE EQU 0x00000100 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_SECTOR_SIZE +CYDEV_ECC_SECTOR_SIZE EQU 0x00002000 + ENDIF + IF :LNOT::DEF:CYDEV_ECC_ROW_SIZE +CYDEV_ECC_ROW_SIZE EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_SECTOR_SIZE +CYDEV_EEPROM_SECTOR_SIZE EQU 0x00000400 + ENDIF + IF :LNOT::DEF:CYDEV_EEPROM_ROW_SIZE +CYDEV_EEPROM_ROW_SIZE EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYDEV_PERIPH_BASE +CYDEV_PERIPH_BASE EQU CYDEV_CLKDIST_BASE + ENDIF + IF :LNOT::DEF:CYCLK_LD_DISABLE +CYCLK_LD_DISABLE EQU 0x00000004 + ENDIF + IF :LNOT::DEF:CYCLK_LD_SYNC_EN +CYCLK_LD_SYNC_EN EQU 0x00000002 + ENDIF + IF :LNOT::DEF:CYCLK_LD_LOAD +CYCLK_LD_LOAD EQU 0x00000001 + ENDIF + IF :LNOT::DEF:CYCLK_PIPE +CYCLK_PIPE EQU 0x00000080 + ENDIF + IF :LNOT::DEF:CYCLK_SSS +CYCLK_SSS EQU 0x00000040 + ENDIF + IF :LNOT::DEF:CYCLK_EARLY +CYCLK_EARLY EQU 0x00000020 + ENDIF + IF :LNOT::DEF:CYCLK_DUTY +CYCLK_DUTY EQU 0x00000010 + ENDIF + IF :LNOT::DEF:CYCLK_SYNC +CYCLK_SYNC EQU 0x00000008 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_D +CYCLK_SRC_SEL_CLK_SYNC_D EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_SYNC_DIG +CYCLK_SRC_SEL_SYNC_DIG EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_IMO +CYCLK_SRC_SEL_IMO EQU 1 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_MHZ +CYCLK_SRC_SEL_XTAL_MHZ EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALM +CYCLK_SRC_SEL_XTALM EQU 2 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_ILO +CYCLK_SRC_SEL_ILO EQU 3 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_PLL +CYCLK_SRC_SEL_PLL EQU 4 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTAL_KHZ +CYCLK_SRC_SEL_XTAL_KHZ EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_XTALK +CYCLK_SRC_SEL_XTALK EQU 5 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_G +CYCLK_SRC_SEL_DSI_G EQU 6 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_D +CYCLK_SRC_SEL_DSI_D EQU 7 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_CLK_SYNC_A +CYCLK_SRC_SEL_CLK_SYNC_A EQU 0 + ENDIF + IF :LNOT::DEF:CYCLK_SRC_SEL_DSI_A +CYCLK_SRC_SEL_DSI_A EQU 7 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h new file mode 100644 index 0000000..8178873 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cydisabledsheets.h @@ -0,0 +1,5 @@ +#ifndef INCLUDED_CYDISABLEDSHEETS_H +#define INCLUDED_CYDISABLEDSHEETS_H + + +#endif /* INCLUDED_CYDISABLEDSHEETS_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h new file mode 100644 index 0000000..f1c21ce --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -0,0 +1,1615 @@ +/******************************************************************************* +* File Name: cyfitter.h +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef INCLUDED_CYFITTER_H +#define INCLUDED_CYFITTER_H +#include "cydevice.h" +#include "cydevice_trm.h" + +/* LED */ +#define LED__0__INTTYPE CYREG_PICU12_INTTYPE2 +#define LED__0__MASK 0x04u +#define LED__0__PC CYREG_PRT12_PC2 +#define LED__0__PORT 12u +#define LED__0__SHIFT 2u +#define LED__1__INTTYPE CYREG_PICU12_INTTYPE3 +#define LED__1__MASK 0x08u +#define LED__1__PC CYREG_PRT12_PC3 +#define LED__1__PORT 12u +#define LED__1__SHIFT 3u +#define LED__AG CYREG_PRT12_AG +#define LED__BIE CYREG_PRT12_BIE +#define LED__BIT_MASK CYREG_PRT12_BIT_MASK +#define LED__BYP CYREG_PRT12_BYP +#define LED__DM0 CYREG_PRT12_DM0 +#define LED__DM1 CYREG_PRT12_DM1 +#define LED__DM2 CYREG_PRT12_DM2 +#define LED__DR CYREG_PRT12_DR +#define LED__INP_DIS CYREG_PRT12_INP_DIS +#define LED__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define LED__MASK 0x0Cu +#define LED__PORT 12u +#define LED__PRT CYREG_PRT12_PRT +#define LED__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define LED__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define LED__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define LED__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define LED__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define LED__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define LED__PS CYREG_PRT12_PS +#define LED__SHIFT 2u +#define LED__SIO_CFG CYREG_PRT12_SIO_CFG +#define LED__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define LED__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define LED__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define LED__SLW CYREG_PRT12_SLW + +/* USBFS */ +#define USBFS_arb_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_arb_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_arb_int__INTC_MASK 0x400000u +#define USBFS_arb_int__INTC_NUMBER 22u +#define USBFS_arb_int__INTC_PRIOR_NUM 7u +#define USBFS_arb_int__INTC_PRIOR_REG CYREG_NVIC_PRI_22 +#define USBFS_arb_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_arb_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_bus_reset__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_bus_reset__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_bus_reset__INTC_MASK 0x800000u +#define USBFS_bus_reset__INTC_NUMBER 23u +#define USBFS_bus_reset__INTC_PRIOR_NUM 7u +#define USBFS_bus_reset__INTC_PRIOR_REG CYREG_NVIC_PRI_23 +#define USBFS_bus_reset__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_bus_reset__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_Dm__0__INTTYPE CYREG_PICU15_INTTYPE7 +#define USBFS_Dm__0__MASK 0x80u +#define USBFS_Dm__0__PC CYREG_IO_PC_PRT15_7_6_PC1 +#define USBFS_Dm__0__PORT 15u +#define USBFS_Dm__0__SHIFT 7u +#define USBFS_Dm__AG CYREG_PRT15_AG +#define USBFS_Dm__AMUX CYREG_PRT15_AMUX +#define USBFS_Dm__BIE CYREG_PRT15_BIE +#define USBFS_Dm__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dm__BYP CYREG_PRT15_BYP +#define USBFS_Dm__CTL CYREG_PRT15_CTL +#define USBFS_Dm__DM0 CYREG_PRT15_DM0 +#define USBFS_Dm__DM1 CYREG_PRT15_DM1 +#define USBFS_Dm__DM2 CYREG_PRT15_DM2 +#define USBFS_Dm__DR CYREG_PRT15_DR +#define USBFS_Dm__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dm__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dm__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dm__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dm__MASK 0x80u +#define USBFS_Dm__PORT 15u +#define USBFS_Dm__PRT CYREG_PRT15_PRT +#define USBFS_Dm__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dm__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dm__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dm__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dm__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dm__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dm__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dm__PS CYREG_PRT15_PS +#define USBFS_Dm__SHIFT 7u +#define USBFS_Dm__SLW CYREG_PRT15_SLW +#define USBFS_Dp__0__INTTYPE CYREG_PICU15_INTTYPE6 +#define USBFS_Dp__0__MASK 0x40u +#define USBFS_Dp__0__PC CYREG_IO_PC_PRT15_7_6_PC0 +#define USBFS_Dp__0__PORT 15u +#define USBFS_Dp__0__SHIFT 6u +#define USBFS_Dp__AG CYREG_PRT15_AG +#define USBFS_Dp__AMUX CYREG_PRT15_AMUX +#define USBFS_Dp__BIE CYREG_PRT15_BIE +#define USBFS_Dp__BIT_MASK CYREG_PRT15_BIT_MASK +#define USBFS_Dp__BYP CYREG_PRT15_BYP +#define USBFS_Dp__CTL CYREG_PRT15_CTL +#define USBFS_Dp__DM0 CYREG_PRT15_DM0 +#define USBFS_Dp__DM1 CYREG_PRT15_DM1 +#define USBFS_Dp__DM2 CYREG_PRT15_DM2 +#define USBFS_Dp__DR CYREG_PRT15_DR +#define USBFS_Dp__INP_DIS CYREG_PRT15_INP_DIS +#define USBFS_Dp__INTSTAT CYREG_PICU15_INTSTAT +#define USBFS_Dp__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define USBFS_Dp__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define USBFS_Dp__LCD_EN CYREG_PRT15_LCD_EN +#define USBFS_Dp__MASK 0x40u +#define USBFS_Dp__PORT 15u +#define USBFS_Dp__PRT CYREG_PRT15_PRT +#define USBFS_Dp__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define USBFS_Dp__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define USBFS_Dp__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define USBFS_Dp__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define USBFS_Dp__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define USBFS_Dp__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define USBFS_Dp__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define USBFS_Dp__PS CYREG_PRT15_PS +#define USBFS_Dp__SHIFT 6u +#define USBFS_Dp__SLW CYREG_PRT15_SLW +#define USBFS_Dp__SNAP CYREG_PICU_15_SNAP_15 +#define USBFS_dp_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_dp_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_dp_int__INTC_MASK 0x1000u +#define USBFS_dp_int__INTC_NUMBER 12u +#define USBFS_dp_int__INTC_PRIOR_NUM 7u +#define USBFS_dp_int__INTC_PRIOR_REG CYREG_NVIC_PRI_12 +#define USBFS_dp_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_dp_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_0__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_0__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_0__INTC_MASK 0x1000000u +#define USBFS_ep_0__INTC_NUMBER 24u +#define USBFS_ep_0__INTC_PRIOR_NUM 7u +#define USBFS_ep_0__INTC_PRIOR_REG CYREG_NVIC_PRI_24 +#define USBFS_ep_0__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_0__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_1__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_1__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_1__INTC_MASK 0x01u +#define USBFS_ep_1__INTC_NUMBER 0u +#define USBFS_ep_1__INTC_PRIOR_NUM 7u +#define USBFS_ep_1__INTC_PRIOR_REG CYREG_NVIC_PRI_0 +#define USBFS_ep_1__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_1__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_ep_2__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_ep_2__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_ep_2__INTC_MASK 0x02u +#define USBFS_ep_2__INTC_NUMBER 1u +#define USBFS_ep_2__INTC_PRIOR_NUM 7u +#define USBFS_ep_2__INTC_PRIOR_REG CYREG_NVIC_PRI_1 +#define USBFS_ep_2__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_ep_2__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_sof_int__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 +#define USBFS_sof_int__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0 +#define USBFS_sof_int__INTC_MASK 0x200000u +#define USBFS_sof_int__INTC_NUMBER 21u +#define USBFS_sof_int__INTC_PRIOR_NUM 7u +#define USBFS_sof_int__INTC_PRIOR_REG CYREG_NVIC_PRI_21 +#define USBFS_sof_int__INTC_SET_EN_REG CYREG_NVIC_SETENA0 +#define USBFS_sof_int__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +#define USBFS_USB__ARB_CFG CYREG_USB_ARB_CFG +#define USBFS_USB__ARB_EP1_CFG CYREG_USB_ARB_EP1_CFG +#define USBFS_USB__ARB_EP1_INT_EN CYREG_USB_ARB_EP1_INT_EN +#define USBFS_USB__ARB_EP1_SR CYREG_USB_ARB_EP1_SR +#define USBFS_USB__ARB_EP2_CFG CYREG_USB_ARB_EP2_CFG +#define USBFS_USB__ARB_EP2_INT_EN CYREG_USB_ARB_EP2_INT_EN +#define USBFS_USB__ARB_EP2_SR CYREG_USB_ARB_EP2_SR +#define USBFS_USB__ARB_EP3_CFG CYREG_USB_ARB_EP3_CFG +#define USBFS_USB__ARB_EP3_INT_EN CYREG_USB_ARB_EP3_INT_EN +#define USBFS_USB__ARB_EP3_SR CYREG_USB_ARB_EP3_SR +#define USBFS_USB__ARB_EP4_CFG CYREG_USB_ARB_EP4_CFG +#define USBFS_USB__ARB_EP4_INT_EN CYREG_USB_ARB_EP4_INT_EN +#define USBFS_USB__ARB_EP4_SR CYREG_USB_ARB_EP4_SR +#define USBFS_USB__ARB_EP5_CFG CYREG_USB_ARB_EP5_CFG +#define USBFS_USB__ARB_EP5_INT_EN CYREG_USB_ARB_EP5_INT_EN +#define USBFS_USB__ARB_EP5_SR CYREG_USB_ARB_EP5_SR +#define USBFS_USB__ARB_EP6_CFG CYREG_USB_ARB_EP6_CFG +#define USBFS_USB__ARB_EP6_INT_EN CYREG_USB_ARB_EP6_INT_EN +#define USBFS_USB__ARB_EP6_SR CYREG_USB_ARB_EP6_SR +#define USBFS_USB__ARB_EP7_CFG CYREG_USB_ARB_EP7_CFG +#define USBFS_USB__ARB_EP7_INT_EN CYREG_USB_ARB_EP7_INT_EN +#define USBFS_USB__ARB_EP7_SR CYREG_USB_ARB_EP7_SR +#define USBFS_USB__ARB_EP8_CFG CYREG_USB_ARB_EP8_CFG +#define USBFS_USB__ARB_EP8_INT_EN CYREG_USB_ARB_EP8_INT_EN +#define USBFS_USB__ARB_EP8_SR CYREG_USB_ARB_EP8_SR +#define USBFS_USB__ARB_INT_EN CYREG_USB_ARB_INT_EN +#define USBFS_USB__ARB_INT_SR CYREG_USB_ARB_INT_SR +#define USBFS_USB__ARB_RW1_DR CYREG_USB_ARB_RW1_DR +#define USBFS_USB__ARB_RW1_RA CYREG_USB_ARB_RW1_RA +#define USBFS_USB__ARB_RW1_RA_MSB CYREG_USB_ARB_RW1_RA_MSB +#define USBFS_USB__ARB_RW1_WA CYREG_USB_ARB_RW1_WA +#define USBFS_USB__ARB_RW1_WA_MSB CYREG_USB_ARB_RW1_WA_MSB +#define USBFS_USB__ARB_RW2_DR CYREG_USB_ARB_RW2_DR +#define USBFS_USB__ARB_RW2_RA CYREG_USB_ARB_RW2_RA +#define USBFS_USB__ARB_RW2_RA_MSB CYREG_USB_ARB_RW2_RA_MSB +#define USBFS_USB__ARB_RW2_WA CYREG_USB_ARB_RW2_WA +#define USBFS_USB__ARB_RW2_WA_MSB CYREG_USB_ARB_RW2_WA_MSB +#define USBFS_USB__ARB_RW3_DR CYREG_USB_ARB_RW3_DR +#define USBFS_USB__ARB_RW3_RA CYREG_USB_ARB_RW3_RA +#define USBFS_USB__ARB_RW3_RA_MSB CYREG_USB_ARB_RW3_RA_MSB +#define USBFS_USB__ARB_RW3_WA CYREG_USB_ARB_RW3_WA +#define USBFS_USB__ARB_RW3_WA_MSB CYREG_USB_ARB_RW3_WA_MSB +#define USBFS_USB__ARB_RW4_DR CYREG_USB_ARB_RW4_DR +#define USBFS_USB__ARB_RW4_RA CYREG_USB_ARB_RW4_RA +#define USBFS_USB__ARB_RW4_RA_MSB CYREG_USB_ARB_RW4_RA_MSB +#define USBFS_USB__ARB_RW4_WA CYREG_USB_ARB_RW4_WA +#define USBFS_USB__ARB_RW4_WA_MSB CYREG_USB_ARB_RW4_WA_MSB +#define USBFS_USB__ARB_RW5_DR CYREG_USB_ARB_RW5_DR +#define USBFS_USB__ARB_RW5_RA CYREG_USB_ARB_RW5_RA +#define USBFS_USB__ARB_RW5_RA_MSB CYREG_USB_ARB_RW5_RA_MSB +#define USBFS_USB__ARB_RW5_WA CYREG_USB_ARB_RW5_WA +#define USBFS_USB__ARB_RW5_WA_MSB CYREG_USB_ARB_RW5_WA_MSB +#define USBFS_USB__ARB_RW6_DR CYREG_USB_ARB_RW6_DR +#define USBFS_USB__ARB_RW6_RA CYREG_USB_ARB_RW6_RA +#define USBFS_USB__ARB_RW6_RA_MSB CYREG_USB_ARB_RW6_RA_MSB +#define USBFS_USB__ARB_RW6_WA CYREG_USB_ARB_RW6_WA +#define USBFS_USB__ARB_RW6_WA_MSB CYREG_USB_ARB_RW6_WA_MSB +#define USBFS_USB__ARB_RW7_DR CYREG_USB_ARB_RW7_DR +#define USBFS_USB__ARB_RW7_RA CYREG_USB_ARB_RW7_RA +#define USBFS_USB__ARB_RW7_RA_MSB CYREG_USB_ARB_RW7_RA_MSB +#define USBFS_USB__ARB_RW7_WA CYREG_USB_ARB_RW7_WA +#define USBFS_USB__ARB_RW7_WA_MSB CYREG_USB_ARB_RW7_WA_MSB +#define USBFS_USB__ARB_RW8_DR CYREG_USB_ARB_RW8_DR +#define USBFS_USB__ARB_RW8_RA CYREG_USB_ARB_RW8_RA +#define USBFS_USB__ARB_RW8_RA_MSB CYREG_USB_ARB_RW8_RA_MSB +#define USBFS_USB__ARB_RW8_WA CYREG_USB_ARB_RW8_WA +#define USBFS_USB__ARB_RW8_WA_MSB CYREG_USB_ARB_RW8_WA_MSB +#define USBFS_USB__BUF_SIZE CYREG_USB_BUF_SIZE +#define USBFS_USB__BUS_RST_CNT CYREG_USB_BUS_RST_CNT +#define USBFS_USB__CR0 CYREG_USB_CR0 +#define USBFS_USB__CR1 CYREG_USB_CR1 +#define USBFS_USB__CWA CYREG_USB_CWA +#define USBFS_USB__CWA_MSB CYREG_USB_CWA_MSB +#define USBFS_USB__DMA_THRES CYREG_USB_DMA_THRES +#define USBFS_USB__DMA_THRES_MSB CYREG_USB_DMA_THRES_MSB +#define USBFS_USB__DYN_RECONFIG CYREG_USB_DYN_RECONFIG +#define USBFS_USB__EP_ACTIVE CYREG_USB_EP_ACTIVE +#define USBFS_USB__EP_TYPE CYREG_USB_EP_TYPE +#define USBFS_USB__EP0_CNT CYREG_USB_EP0_CNT +#define USBFS_USB__EP0_CR CYREG_USB_EP0_CR +#define USBFS_USB__EP0_DR0 CYREG_USB_EP0_DR0 +#define USBFS_USB__EP0_DR1 CYREG_USB_EP0_DR1 +#define USBFS_USB__EP0_DR2 CYREG_USB_EP0_DR2 +#define USBFS_USB__EP0_DR3 CYREG_USB_EP0_DR3 +#define USBFS_USB__EP0_DR4 CYREG_USB_EP0_DR4 +#define USBFS_USB__EP0_DR5 CYREG_USB_EP0_DR5 +#define USBFS_USB__EP0_DR6 CYREG_USB_EP0_DR6 +#define USBFS_USB__EP0_DR7 CYREG_USB_EP0_DR7 +#define USBFS_USB__MEM_DATA CYREG_USB_MEM_DATA_MBASE +#define USBFS_USB__PM_ACT_CFG CYREG_PM_ACT_CFG5 +#define USBFS_USB__PM_ACT_MSK 0x01u +#define USBFS_USB__PM_STBY_CFG CYREG_PM_STBY_CFG5 +#define USBFS_USB__PM_STBY_MSK 0x01u +#define USBFS_USB__SIE_EP_INT_EN CYREG_USB_SIE_EP_INT_EN +#define USBFS_USB__SIE_EP_INT_SR CYREG_USB_SIE_EP_INT_SR +#define USBFS_USB__SIE_EP1_CNT0 CYREG_USB_SIE_EP1_CNT0 +#define USBFS_USB__SIE_EP1_CNT1 CYREG_USB_SIE_EP1_CNT1 +#define USBFS_USB__SIE_EP1_CR0 CYREG_USB_SIE_EP1_CR0 +#define USBFS_USB__SIE_EP2_CNT0 CYREG_USB_SIE_EP2_CNT0 +#define USBFS_USB__SIE_EP2_CNT1 CYREG_USB_SIE_EP2_CNT1 +#define USBFS_USB__SIE_EP2_CR0 CYREG_USB_SIE_EP2_CR0 +#define USBFS_USB__SIE_EP3_CNT0 CYREG_USB_SIE_EP3_CNT0 +#define USBFS_USB__SIE_EP3_CNT1 CYREG_USB_SIE_EP3_CNT1 +#define USBFS_USB__SIE_EP3_CR0 CYREG_USB_SIE_EP3_CR0 +#define USBFS_USB__SIE_EP4_CNT0 CYREG_USB_SIE_EP4_CNT0 +#define USBFS_USB__SIE_EP4_CNT1 CYREG_USB_SIE_EP4_CNT1 +#define USBFS_USB__SIE_EP4_CR0 CYREG_USB_SIE_EP4_CR0 +#define USBFS_USB__SIE_EP5_CNT0 CYREG_USB_SIE_EP5_CNT0 +#define USBFS_USB__SIE_EP5_CNT1 CYREG_USB_SIE_EP5_CNT1 +#define USBFS_USB__SIE_EP5_CR0 CYREG_USB_SIE_EP5_CR0 +#define USBFS_USB__SIE_EP6_CNT0 CYREG_USB_SIE_EP6_CNT0 +#define USBFS_USB__SIE_EP6_CNT1 CYREG_USB_SIE_EP6_CNT1 +#define USBFS_USB__SIE_EP6_CR0 CYREG_USB_SIE_EP6_CR0 +#define USBFS_USB__SIE_EP7_CNT0 CYREG_USB_SIE_EP7_CNT0 +#define USBFS_USB__SIE_EP7_CNT1 CYREG_USB_SIE_EP7_CNT1 +#define USBFS_USB__SIE_EP7_CR0 CYREG_USB_SIE_EP7_CR0 +#define USBFS_USB__SIE_EP8_CNT0 CYREG_USB_SIE_EP8_CNT0 +#define USBFS_USB__SIE_EP8_CNT1 CYREG_USB_SIE_EP8_CNT1 +#define USBFS_USB__SIE_EP8_CR0 CYREG_USB_SIE_EP8_CR0 +#define USBFS_USB__SOF0 CYREG_USB_SOF0 +#define USBFS_USB__SOF1 CYREG_USB_SOF1 +#define USBFS_USB__USB_CLK_EN CYREG_USB_USB_CLK_EN +#define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 +#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 + +/* BOOTLDR */ +#define BOOTLDR__0__INTTYPE CYREG_PICU0_INTTYPE0 +#define BOOTLDR__0__MASK 0x01u +#define BOOTLDR__0__PC CYREG_PRT0_PC0 +#define BOOTLDR__0__PORT 0u +#define BOOTLDR__0__SHIFT 0u +#define BOOTLDR__AG CYREG_PRT0_AG +#define BOOTLDR__AMUX CYREG_PRT0_AMUX +#define BOOTLDR__BIE CYREG_PRT0_BIE +#define BOOTLDR__BIT_MASK CYREG_PRT0_BIT_MASK +#define BOOTLDR__BYP CYREG_PRT0_BYP +#define BOOTLDR__CTL CYREG_PRT0_CTL +#define BOOTLDR__DM0 CYREG_PRT0_DM0 +#define BOOTLDR__DM1 CYREG_PRT0_DM1 +#define BOOTLDR__DM2 CYREG_PRT0_DM2 +#define BOOTLDR__DR CYREG_PRT0_DR +#define BOOTLDR__INP_DIS CYREG_PRT0_INP_DIS +#define BOOTLDR__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU0_BASE +#define BOOTLDR__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define BOOTLDR__LCD_EN CYREG_PRT0_LCD_EN +#define BOOTLDR__MASK 0x01u +#define BOOTLDR__PORT 0u +#define BOOTLDR__PRT CYREG_PRT0_PRT +#define BOOTLDR__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define BOOTLDR__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define BOOTLDR__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define BOOTLDR__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define BOOTLDR__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define BOOTLDR__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define BOOTLDR__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define BOOTLDR__PS CYREG_PRT0_PS +#define BOOTLDR__SHIFT 0u +#define BOOTLDR__SLW CYREG_PRT0_SLW + +/* TERM_EN */ +#define TERM_EN__0__INTTYPE CYREG_PICU15_INTTYPE3 +#define TERM_EN__0__MASK 0x08u +#define TERM_EN__0__PC CYREG_IO_PC_PRT15_PC3 +#define TERM_EN__0__PORT 15u +#define TERM_EN__0__SHIFT 3u +#define TERM_EN__AG CYREG_PRT15_AG +#define TERM_EN__AMUX CYREG_PRT15_AMUX +#define TERM_EN__BIE CYREG_PRT15_BIE +#define TERM_EN__BIT_MASK CYREG_PRT15_BIT_MASK +#define TERM_EN__BYP CYREG_PRT15_BYP +#define TERM_EN__CTL CYREG_PRT15_CTL +#define TERM_EN__DM0 CYREG_PRT15_DM0 +#define TERM_EN__DM1 CYREG_PRT15_DM1 +#define TERM_EN__DM2 CYREG_PRT15_DM2 +#define TERM_EN__DR CYREG_PRT15_DR +#define TERM_EN__INP_DIS CYREG_PRT15_INP_DIS +#define TERM_EN__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define TERM_EN__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define TERM_EN__LCD_EN CYREG_PRT15_LCD_EN +#define TERM_EN__MASK 0x08u +#define TERM_EN__PORT 15u +#define TERM_EN__PRT CYREG_PRT15_PRT +#define TERM_EN__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define TERM_EN__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define TERM_EN__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define TERM_EN__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define TERM_EN__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define TERM_EN__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define TERM_EN__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define TERM_EN__PS CYREG_PRT15_PS +#define TERM_EN__SHIFT 3u +#define TERM_EN__SLW CYREG_PRT15_SLW + +/* SCSI_Out */ +#define SCSI_Out__0__AG CYREG_PRT6_AG +#define SCSI_Out__0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__0__BIE CYREG_PRT6_BIE +#define SCSI_Out__0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__0__BYP CYREG_PRT6_BYP +#define SCSI_Out__0__CTL CYREG_PRT6_CTL +#define SCSI_Out__0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__0__DR CYREG_PRT6_DR +#define SCSI_Out__0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__0__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Out__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__0__MASK 0x04u +#define SCSI_Out__0__PC CYREG_PRT6_PC2 +#define SCSI_Out__0__PORT 6u +#define SCSI_Out__0__PRT CYREG_PRT6_PRT +#define SCSI_Out__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__0__PS CYREG_PRT6_PS +#define SCSI_Out__0__SHIFT 2u +#define SCSI_Out__0__SLW CYREG_PRT6_SLW +#define SCSI_Out__1__AG CYREG_PRT4_AG +#define SCSI_Out__1__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__1__BIE CYREG_PRT4_BIE +#define SCSI_Out__1__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__1__BYP CYREG_PRT4_BYP +#define SCSI_Out__1__CTL CYREG_PRT4_CTL +#define SCSI_Out__1__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__1__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__1__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__1__DR CYREG_PRT4_DR +#define SCSI_Out__1__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__1__INTTYPE CYREG_PICU4_INTTYPE6 +#define SCSI_Out__1__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__1__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__1__MASK 0x40u +#define SCSI_Out__1__PC CYREG_PRT4_PC6 +#define SCSI_Out__1__PORT 4u +#define SCSI_Out__1__PRT CYREG_PRT4_PRT +#define SCSI_Out__1__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__1__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__1__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__1__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__1__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__1__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__1__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__1__PS CYREG_PRT4_PS +#define SCSI_Out__1__SHIFT 6u +#define SCSI_Out__1__SLW CYREG_PRT4_SLW +#define SCSI_Out__2__AG CYREG_PRT0_AG +#define SCSI_Out__2__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__2__BIE CYREG_PRT0_BIE +#define SCSI_Out__2__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__2__BYP CYREG_PRT0_BYP +#define SCSI_Out__2__CTL CYREG_PRT0_CTL +#define SCSI_Out__2__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__2__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__2__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__2__DR CYREG_PRT0_DR +#define SCSI_Out__2__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__2__INTTYPE CYREG_PICU0_INTTYPE7 +#define SCSI_Out__2__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__2__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__2__MASK 0x80u +#define SCSI_Out__2__PC CYREG_PRT0_PC7 +#define SCSI_Out__2__PORT 0u +#define SCSI_Out__2__PRT CYREG_PRT0_PRT +#define SCSI_Out__2__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__2__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__2__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__2__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__2__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__2__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__2__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__2__PS CYREG_PRT0_PS +#define SCSI_Out__2__SHIFT 7u +#define SCSI_Out__2__SLW CYREG_PRT0_SLW +#define SCSI_Out__3__AG CYREG_PRT0_AG +#define SCSI_Out__3__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__3__BIE CYREG_PRT0_BIE +#define SCSI_Out__3__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__3__BYP CYREG_PRT0_BYP +#define SCSI_Out__3__CTL CYREG_PRT0_CTL +#define SCSI_Out__3__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__3__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__3__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__3__DR CYREG_PRT0_DR +#define SCSI_Out__3__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__3__INTTYPE CYREG_PICU0_INTTYPE5 +#define SCSI_Out__3__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__3__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__3__MASK 0x20u +#define SCSI_Out__3__PC CYREG_PRT0_PC5 +#define SCSI_Out__3__PORT 0u +#define SCSI_Out__3__PRT CYREG_PRT0_PRT +#define SCSI_Out__3__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__3__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__3__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__3__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__3__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__3__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__3__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__3__PS CYREG_PRT0_PS +#define SCSI_Out__3__SHIFT 5u +#define SCSI_Out__3__SLW CYREG_PRT0_SLW +#define SCSI_Out__4__AG CYREG_PRT0_AG +#define SCSI_Out__4__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__4__BIE CYREG_PRT0_BIE +#define SCSI_Out__4__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__4__BYP CYREG_PRT0_BYP +#define SCSI_Out__4__CTL CYREG_PRT0_CTL +#define SCSI_Out__4__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__4__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__4__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__4__DR CYREG_PRT0_DR +#define SCSI_Out__4__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__4__INTTYPE CYREG_PICU0_INTTYPE3 +#define SCSI_Out__4__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__4__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__4__MASK 0x08u +#define SCSI_Out__4__PC CYREG_PRT0_PC3 +#define SCSI_Out__4__PORT 0u +#define SCSI_Out__4__PRT CYREG_PRT0_PRT +#define SCSI_Out__4__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__4__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__4__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__4__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__4__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__4__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__4__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__4__PS CYREG_PRT0_PS +#define SCSI_Out__4__SHIFT 3u +#define SCSI_Out__4__SLW CYREG_PRT0_SLW +#define SCSI_Out__5__AG CYREG_PRT0_AG +#define SCSI_Out__5__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__5__BIE CYREG_PRT0_BIE +#define SCSI_Out__5__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__5__BYP CYREG_PRT0_BYP +#define SCSI_Out__5__CTL CYREG_PRT0_CTL +#define SCSI_Out__5__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__5__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__5__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__5__DR CYREG_PRT0_DR +#define SCSI_Out__5__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__5__INTTYPE CYREG_PICU0_INTTYPE1 +#define SCSI_Out__5__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__5__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__5__MASK 0x02u +#define SCSI_Out__5__PC CYREG_PRT0_PC1 +#define SCSI_Out__5__PORT 0u +#define SCSI_Out__5__PRT CYREG_PRT0_PRT +#define SCSI_Out__5__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__5__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__5__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__5__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__5__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__5__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__5__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__5__PS CYREG_PRT0_PS +#define SCSI_Out__5__SHIFT 1u +#define SCSI_Out__5__SLW CYREG_PRT0_SLW +#define SCSI_Out__6__AG CYREG_PRT4_AG +#define SCSI_Out__6__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__6__BIE CYREG_PRT4_BIE +#define SCSI_Out__6__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__6__BYP CYREG_PRT4_BYP +#define SCSI_Out__6__CTL CYREG_PRT4_CTL +#define SCSI_Out__6__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__6__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__6__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__6__DR CYREG_PRT4_DR +#define SCSI_Out__6__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__6__INTTYPE CYREG_PICU4_INTTYPE1 +#define SCSI_Out__6__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__6__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__6__MASK 0x02u +#define SCSI_Out__6__PC CYREG_PRT4_PC1 +#define SCSI_Out__6__PORT 4u +#define SCSI_Out__6__PRT CYREG_PRT4_PRT +#define SCSI_Out__6__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__6__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__6__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__6__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__6__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__6__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__6__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__6__PS CYREG_PRT4_PS +#define SCSI_Out__6__SHIFT 1u +#define SCSI_Out__6__SLW CYREG_PRT4_SLW +#define SCSI_Out__7__AG CYREG_PRT4_AG +#define SCSI_Out__7__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__7__BIE CYREG_PRT4_BIE +#define SCSI_Out__7__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__7__BYP CYREG_PRT4_BYP +#define SCSI_Out__7__CTL CYREG_PRT4_CTL +#define SCSI_Out__7__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__7__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__7__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__7__DR CYREG_PRT4_DR +#define SCSI_Out__7__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__7__INTTYPE CYREG_PICU4_INTTYPE0 +#define SCSI_Out__7__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__7__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__7__MASK 0x01u +#define SCSI_Out__7__PC CYREG_PRT4_PC0 +#define SCSI_Out__7__PORT 4u +#define SCSI_Out__7__PRT CYREG_PRT4_PRT +#define SCSI_Out__7__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__7__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__7__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__7__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__7__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__7__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__7__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__7__PS CYREG_PRT4_PS +#define SCSI_Out__7__SHIFT 0u +#define SCSI_Out__7__SLW CYREG_PRT4_SLW +#define SCSI_Out__BSY__AG CYREG_PRT4_AG +#define SCSI_Out__BSY__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__BSY__BIE CYREG_PRT4_BIE +#define SCSI_Out__BSY__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__BSY__BYP CYREG_PRT4_BYP +#define SCSI_Out__BSY__CTL CYREG_PRT4_CTL +#define SCSI_Out__BSY__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__BSY__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__BSY__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__BSY__DR CYREG_PRT4_DR +#define SCSI_Out__BSY__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__BSY__INTTYPE CYREG_PICU4_INTTYPE6 +#define SCSI_Out__BSY__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__BSY__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__BSY__MASK 0x40u +#define SCSI_Out__BSY__PC CYREG_PRT4_PC6 +#define SCSI_Out__BSY__PORT 4u +#define SCSI_Out__BSY__PRT CYREG_PRT4_PRT +#define SCSI_Out__BSY__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__BSY__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__BSY__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__BSY__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__BSY__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__BSY__PS CYREG_PRT4_PS +#define SCSI_Out__BSY__SHIFT 6u +#define SCSI_Out__BSY__SLW CYREG_PRT4_SLW +#define SCSI_Out__CD__AG CYREG_PRT0_AG +#define SCSI_Out__CD__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__CD__BIE CYREG_PRT0_BIE +#define SCSI_Out__CD__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__CD__BYP CYREG_PRT0_BYP +#define SCSI_Out__CD__CTL CYREG_PRT0_CTL +#define SCSI_Out__CD__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__CD__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__CD__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__CD__DR CYREG_PRT0_DR +#define SCSI_Out__CD__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__CD__INTTYPE CYREG_PICU0_INTTYPE1 +#define SCSI_Out__CD__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__CD__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__CD__MASK 0x02u +#define SCSI_Out__CD__PC CYREG_PRT0_PC1 +#define SCSI_Out__CD__PORT 0u +#define SCSI_Out__CD__PRT CYREG_PRT0_PRT +#define SCSI_Out__CD__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__CD__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__CD__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__CD__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__CD__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__CD__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__CD__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__CD__PS CYREG_PRT0_PS +#define SCSI_Out__CD__SHIFT 1u +#define SCSI_Out__CD__SLW CYREG_PRT0_SLW +#define SCSI_Out__DBP_raw__AG CYREG_PRT6_AG +#define SCSI_Out__DBP_raw__AMUX CYREG_PRT6_AMUX +#define SCSI_Out__DBP_raw__BIE CYREG_PRT6_BIE +#define SCSI_Out__DBP_raw__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out__DBP_raw__BYP CYREG_PRT6_BYP +#define SCSI_Out__DBP_raw__CTL CYREG_PRT6_CTL +#define SCSI_Out__DBP_raw__DM0 CYREG_PRT6_DM0 +#define SCSI_Out__DBP_raw__DM1 CYREG_PRT6_DM1 +#define SCSI_Out__DBP_raw__DM2 CYREG_PRT6_DM2 +#define SCSI_Out__DBP_raw__DR CYREG_PRT6_DR +#define SCSI_Out__DBP_raw__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out__DBP_raw__INTTYPE CYREG_PICU6_INTTYPE2 +#define SCSI_Out__DBP_raw__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out__DBP_raw__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out__DBP_raw__MASK 0x04u +#define SCSI_Out__DBP_raw__PC CYREG_PRT6_PC2 +#define SCSI_Out__DBP_raw__PORT 6u +#define SCSI_Out__DBP_raw__PRT CYREG_PRT6_PRT +#define SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out__DBP_raw__PS CYREG_PRT6_PS +#define SCSI_Out__DBP_raw__SHIFT 2u +#define SCSI_Out__DBP_raw__SLW CYREG_PRT6_SLW +#define SCSI_Out__IO_raw__AG CYREG_PRT4_AG +#define SCSI_Out__IO_raw__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__IO_raw__BIE CYREG_PRT4_BIE +#define SCSI_Out__IO_raw__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__IO_raw__BYP CYREG_PRT4_BYP +#define SCSI_Out__IO_raw__CTL CYREG_PRT4_CTL +#define SCSI_Out__IO_raw__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__IO_raw__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__IO_raw__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__IO_raw__DR CYREG_PRT4_DR +#define SCSI_Out__IO_raw__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__IO_raw__INTTYPE CYREG_PICU4_INTTYPE0 +#define SCSI_Out__IO_raw__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__IO_raw__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__IO_raw__MASK 0x01u +#define SCSI_Out__IO_raw__PC CYREG_PRT4_PC0 +#define SCSI_Out__IO_raw__PORT 4u +#define SCSI_Out__IO_raw__PRT CYREG_PRT4_PRT +#define SCSI_Out__IO_raw__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__IO_raw__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__IO_raw__PS CYREG_PRT4_PS +#define SCSI_Out__IO_raw__SHIFT 0u +#define SCSI_Out__IO_raw__SLW CYREG_PRT4_SLW +#define SCSI_Out__MSG__AG CYREG_PRT0_AG +#define SCSI_Out__MSG__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__MSG__BIE CYREG_PRT0_BIE +#define SCSI_Out__MSG__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__MSG__BYP CYREG_PRT0_BYP +#define SCSI_Out__MSG__CTL CYREG_PRT0_CTL +#define SCSI_Out__MSG__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__MSG__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__MSG__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__MSG__DR CYREG_PRT0_DR +#define SCSI_Out__MSG__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__MSG__INTTYPE CYREG_PICU0_INTTYPE5 +#define SCSI_Out__MSG__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__MSG__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__MSG__MASK 0x20u +#define SCSI_Out__MSG__PC CYREG_PRT0_PC5 +#define SCSI_Out__MSG__PORT 0u +#define SCSI_Out__MSG__PRT CYREG_PRT0_PRT +#define SCSI_Out__MSG__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__MSG__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__MSG__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__MSG__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__MSG__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__MSG__PS CYREG_PRT0_PS +#define SCSI_Out__MSG__SHIFT 5u +#define SCSI_Out__MSG__SLW CYREG_PRT0_SLW +#define SCSI_Out__REQ__AG CYREG_PRT4_AG +#define SCSI_Out__REQ__AMUX CYREG_PRT4_AMUX +#define SCSI_Out__REQ__BIE CYREG_PRT4_BIE +#define SCSI_Out__REQ__BIT_MASK CYREG_PRT4_BIT_MASK +#define SCSI_Out__REQ__BYP CYREG_PRT4_BYP +#define SCSI_Out__REQ__CTL CYREG_PRT4_CTL +#define SCSI_Out__REQ__DM0 CYREG_PRT4_DM0 +#define SCSI_Out__REQ__DM1 CYREG_PRT4_DM1 +#define SCSI_Out__REQ__DM2 CYREG_PRT4_DM2 +#define SCSI_Out__REQ__DR CYREG_PRT4_DR +#define SCSI_Out__REQ__INP_DIS CYREG_PRT4_INP_DIS +#define SCSI_Out__REQ__INTTYPE CYREG_PICU4_INTTYPE1 +#define SCSI_Out__REQ__LCD_COM_SEG CYREG_PRT4_LCD_COM_SEG +#define SCSI_Out__REQ__LCD_EN CYREG_PRT4_LCD_EN +#define SCSI_Out__REQ__MASK 0x02u +#define SCSI_Out__REQ__PC CYREG_PRT4_PC1 +#define SCSI_Out__REQ__PORT 4u +#define SCSI_Out__REQ__PRT CYREG_PRT4_PRT +#define SCSI_Out__REQ__PRTDSI__CAPS_SEL CYREG_PRT4_CAPS_SEL +#define SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN CYREG_PRT4_DBL_SYNC_IN +#define SCSI_Out__REQ__PRTDSI__OE_SEL0 CYREG_PRT4_OE_SEL0 +#define SCSI_Out__REQ__PRTDSI__OE_SEL1 CYREG_PRT4_OE_SEL1 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL0 CYREG_PRT4_OUT_SEL0 +#define SCSI_Out__REQ__PRTDSI__OUT_SEL1 CYREG_PRT4_OUT_SEL1 +#define SCSI_Out__REQ__PRTDSI__SYNC_OUT CYREG_PRT4_SYNC_OUT +#define SCSI_Out__REQ__PS CYREG_PRT4_PS +#define SCSI_Out__REQ__SHIFT 1u +#define SCSI_Out__REQ__SLW CYREG_PRT4_SLW +#define SCSI_Out__RST__AG CYREG_PRT0_AG +#define SCSI_Out__RST__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__RST__BIE CYREG_PRT0_BIE +#define SCSI_Out__RST__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__RST__BYP CYREG_PRT0_BYP +#define SCSI_Out__RST__CTL CYREG_PRT0_CTL +#define SCSI_Out__RST__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__RST__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__RST__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__RST__DR CYREG_PRT0_DR +#define SCSI_Out__RST__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__RST__INTTYPE CYREG_PICU0_INTTYPE7 +#define SCSI_Out__RST__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__RST__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__RST__MASK 0x80u +#define SCSI_Out__RST__PC CYREG_PRT0_PC7 +#define SCSI_Out__RST__PORT 0u +#define SCSI_Out__RST__PRT CYREG_PRT0_PRT +#define SCSI_Out__RST__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__RST__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__RST__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__RST__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__RST__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__RST__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__RST__PS CYREG_PRT0_PS +#define SCSI_Out__RST__SHIFT 7u +#define SCSI_Out__RST__SLW CYREG_PRT0_SLW +#define SCSI_Out__SEL__AG CYREG_PRT0_AG +#define SCSI_Out__SEL__AMUX CYREG_PRT0_AMUX +#define SCSI_Out__SEL__BIE CYREG_PRT0_BIE +#define SCSI_Out__SEL__BIT_MASK CYREG_PRT0_BIT_MASK +#define SCSI_Out__SEL__BYP CYREG_PRT0_BYP +#define SCSI_Out__SEL__CTL CYREG_PRT0_CTL +#define SCSI_Out__SEL__DM0 CYREG_PRT0_DM0 +#define SCSI_Out__SEL__DM1 CYREG_PRT0_DM1 +#define SCSI_Out__SEL__DM2 CYREG_PRT0_DM2 +#define SCSI_Out__SEL__DR CYREG_PRT0_DR +#define SCSI_Out__SEL__INP_DIS CYREG_PRT0_INP_DIS +#define SCSI_Out__SEL__INTTYPE CYREG_PICU0_INTTYPE3 +#define SCSI_Out__SEL__LCD_COM_SEG CYREG_PRT0_LCD_COM_SEG +#define SCSI_Out__SEL__LCD_EN CYREG_PRT0_LCD_EN +#define SCSI_Out__SEL__MASK 0x08u +#define SCSI_Out__SEL__PC CYREG_PRT0_PC3 +#define SCSI_Out__SEL__PORT 0u +#define SCSI_Out__SEL__PRT CYREG_PRT0_PRT +#define SCSI_Out__SEL__PRTDSI__CAPS_SEL CYREG_PRT0_CAPS_SEL +#define SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN CYREG_PRT0_DBL_SYNC_IN +#define SCSI_Out__SEL__PRTDSI__OE_SEL0 CYREG_PRT0_OE_SEL0 +#define SCSI_Out__SEL__PRTDSI__OE_SEL1 CYREG_PRT0_OE_SEL1 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL0 CYREG_PRT0_OUT_SEL0 +#define SCSI_Out__SEL__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1 +#define SCSI_Out__SEL__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT +#define SCSI_Out__SEL__PS CYREG_PRT0_PS +#define SCSI_Out__SEL__SHIFT 3u +#define SCSI_Out__SEL__SLW CYREG_PRT0_SLW +#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__0__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__0__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__0__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__0__INTTYPE CYREG_PICU6_INTTYPE7 +#define SCSI_Out_DBx__0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__0__MASK 0x80u +#define SCSI_Out_DBx__0__PC CYREG_PRT6_PC7 +#define SCSI_Out_DBx__0__PORT 6u +#define SCSI_Out_DBx__0__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__0__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__0__SHIFT 7u +#define SCSI_Out_DBx__0__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__1__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__1__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__1__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__1__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__1__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__1__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__1__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__1__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__1__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__1__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Out_DBx__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__1__MASK 0x20u +#define SCSI_Out_DBx__1__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__1__PORT 6u +#define SCSI_Out_DBx__1__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__1__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__1__SHIFT 5u +#define SCSI_Out_DBx__1__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__2__AG CYREG_PRT12_AG +#define SCSI_Out_DBx__2__BIE CYREG_PRT12_BIE +#define SCSI_Out_DBx__2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Out_DBx__2__BYP CYREG_PRT12_BYP +#define SCSI_Out_DBx__2__DM0 CYREG_PRT12_DM0 +#define SCSI_Out_DBx__2__DM1 CYREG_PRT12_DM1 +#define SCSI_Out_DBx__2__DM2 CYREG_PRT12_DM2 +#define SCSI_Out_DBx__2__DR CYREG_PRT12_DR +#define SCSI_Out_DBx__2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Out_DBx__2__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Out_DBx__2__MASK 0x20u +#define SCSI_Out_DBx__2__PC CYREG_PRT12_PC5 +#define SCSI_Out_DBx__2__PORT 12u +#define SCSI_Out_DBx__2__PRT CYREG_PRT12_PRT +#define SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Out_DBx__2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Out_DBx__2__PS CYREG_PRT12_PS +#define SCSI_Out_DBx__2__SHIFT 5u +#define SCSI_Out_DBx__2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Out_DBx__2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Out_DBx__2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Out_DBx__2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Out_DBx__2__SLW CYREG_PRT12_SLW +#define SCSI_Out_DBx__3__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__3__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__3__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__3__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__3__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__3__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__3__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__3__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__3__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__3__INTTYPE CYREG_PICU2_INTTYPE7 +#define SCSI_Out_DBx__3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__3__MASK 0x80u +#define SCSI_Out_DBx__3__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__3__PORT 2u +#define SCSI_Out_DBx__3__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__3__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__3__SHIFT 7u +#define SCSI_Out_DBx__3__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__4__INTTYPE CYREG_PICU2_INTTYPE5 +#define SCSI_Out_DBx__4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__4__MASK 0x20u +#define SCSI_Out_DBx__4__PC CYREG_PRT2_PC5 +#define SCSI_Out_DBx__4__PORT 2u +#define SCSI_Out_DBx__4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__4__SHIFT 5u +#define SCSI_Out_DBx__4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__5__INTTYPE CYREG_PICU2_INTTYPE3 +#define SCSI_Out_DBx__5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__5__MASK 0x08u +#define SCSI_Out_DBx__5__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__5__PORT 2u +#define SCSI_Out_DBx__5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__5__SHIFT 3u +#define SCSI_Out_DBx__5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__6__INTTYPE CYREG_PICU2_INTTYPE1 +#define SCSI_Out_DBx__6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__6__MASK 0x02u +#define SCSI_Out_DBx__6__PC CYREG_PRT2_PC1 +#define SCSI_Out_DBx__6__PORT 2u +#define SCSI_Out_DBx__6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__6__SHIFT 1u +#define SCSI_Out_DBx__6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__7__AG CYREG_PRT15_AG +#define SCSI_Out_DBx__7__AMUX CYREG_PRT15_AMUX +#define SCSI_Out_DBx__7__BIE CYREG_PRT15_BIE +#define SCSI_Out_DBx__7__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out_DBx__7__BYP CYREG_PRT15_BYP +#define SCSI_Out_DBx__7__CTL CYREG_PRT15_CTL +#define SCSI_Out_DBx__7__DM0 CYREG_PRT15_DM0 +#define SCSI_Out_DBx__7__DM1 CYREG_PRT15_DM1 +#define SCSI_Out_DBx__7__DM2 CYREG_PRT15_DM2 +#define SCSI_Out_DBx__7__DR CYREG_PRT15_DR +#define SCSI_Out_DBx__7__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out_DBx__7__INTTYPE CYREG_PICU15_INTTYPE5 +#define SCSI_Out_DBx__7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out_DBx__7__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out_DBx__7__MASK 0x20u +#define SCSI_Out_DBx__7__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out_DBx__7__PORT 15u +#define SCSI_Out_DBx__7__PRT CYREG_PRT15_PRT +#define SCSI_Out_DBx__7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out_DBx__7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out_DBx__7__PS CYREG_PRT15_PS +#define SCSI_Out_DBx__7__SHIFT 5u +#define SCSI_Out_DBx__7__SLW CYREG_PRT15_SLW +#define SCSI_Out_DBx__DB0__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB0__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB0__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB0__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB0__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB0__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB0__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB0__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB0__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB0__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB0__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB0__INTTYPE CYREG_PICU6_INTTYPE7 +#define SCSI_Out_DBx__DB0__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB0__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB0__MASK 0x80u +#define SCSI_Out_DBx__DB0__PC CYREG_PRT6_PC7 +#define SCSI_Out_DBx__DB0__PORT 6u +#define SCSI_Out_DBx__DB0__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB0__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB0__SHIFT 7u +#define SCSI_Out_DBx__DB0__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB1__AG CYREG_PRT6_AG +#define SCSI_Out_DBx__DB1__AMUX CYREG_PRT6_AMUX +#define SCSI_Out_DBx__DB1__BIE CYREG_PRT6_BIE +#define SCSI_Out_DBx__DB1__BIT_MASK CYREG_PRT6_BIT_MASK +#define SCSI_Out_DBx__DB1__BYP CYREG_PRT6_BYP +#define SCSI_Out_DBx__DB1__CTL CYREG_PRT6_CTL +#define SCSI_Out_DBx__DB1__DM0 CYREG_PRT6_DM0 +#define SCSI_Out_DBx__DB1__DM1 CYREG_PRT6_DM1 +#define SCSI_Out_DBx__DB1__DM2 CYREG_PRT6_DM2 +#define SCSI_Out_DBx__DB1__DR CYREG_PRT6_DR +#define SCSI_Out_DBx__DB1__INP_DIS CYREG_PRT6_INP_DIS +#define SCSI_Out_DBx__DB1__INTTYPE CYREG_PICU6_INTTYPE5 +#define SCSI_Out_DBx__DB1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG +#define SCSI_Out_DBx__DB1__LCD_EN CYREG_PRT6_LCD_EN +#define SCSI_Out_DBx__DB1__MASK 0x20u +#define SCSI_Out_DBx__DB1__PC CYREG_PRT6_PC5 +#define SCSI_Out_DBx__DB1__PORT 6u +#define SCSI_Out_DBx__DB1__PRT CYREG_PRT6_PRT +#define SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL +#define SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0 +#define SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1 +#define SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT +#define SCSI_Out_DBx__DB1__PS CYREG_PRT6_PS +#define SCSI_Out_DBx__DB1__SHIFT 5u +#define SCSI_Out_DBx__DB1__SLW CYREG_PRT6_SLW +#define SCSI_Out_DBx__DB2__AG CYREG_PRT12_AG +#define SCSI_Out_DBx__DB2__BIE CYREG_PRT12_BIE +#define SCSI_Out_DBx__DB2__BIT_MASK CYREG_PRT12_BIT_MASK +#define SCSI_Out_DBx__DB2__BYP CYREG_PRT12_BYP +#define SCSI_Out_DBx__DB2__DM0 CYREG_PRT12_DM0 +#define SCSI_Out_DBx__DB2__DM1 CYREG_PRT12_DM1 +#define SCSI_Out_DBx__DB2__DM2 CYREG_PRT12_DM2 +#define SCSI_Out_DBx__DB2__DR CYREG_PRT12_DR +#define SCSI_Out_DBx__DB2__INP_DIS CYREG_PRT12_INP_DIS +#define SCSI_Out_DBx__DB2__INTTYPE CYREG_PICU12_INTTYPE5 +#define SCSI_Out_DBx__DB2__MASK 0x20u +#define SCSI_Out_DBx__DB2__PC CYREG_PRT12_PC5 +#define SCSI_Out_DBx__DB2__PORT 12u +#define SCSI_Out_DBx__DB2__PRT CYREG_PRT12_PRT +#define SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SCSI_Out_DBx__DB2__PS CYREG_PRT12_PS +#define SCSI_Out_DBx__DB2__SHIFT 5u +#define SCSI_Out_DBx__DB2__SIO_CFG CYREG_PRT12_SIO_CFG +#define SCSI_Out_DBx__DB2__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SCSI_Out_DBx__DB2__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SCSI_Out_DBx__DB2__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SCSI_Out_DBx__DB2__SLW CYREG_PRT12_SLW +#define SCSI_Out_DBx__DB3__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB3__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB3__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB3__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB3__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB3__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB3__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB3__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB3__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB3__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB3__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB3__INTTYPE CYREG_PICU2_INTTYPE7 +#define SCSI_Out_DBx__DB3__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB3__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB3__MASK 0x80u +#define SCSI_Out_DBx__DB3__PC CYREG_PRT2_PC7 +#define SCSI_Out_DBx__DB3__PORT 2u +#define SCSI_Out_DBx__DB3__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB3__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB3__SHIFT 7u +#define SCSI_Out_DBx__DB3__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB4__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB4__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB4__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB4__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB4__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB4__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB4__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB4__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB4__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB4__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB4__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB4__INTTYPE CYREG_PICU2_INTTYPE5 +#define SCSI_Out_DBx__DB4__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB4__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB4__MASK 0x20u +#define SCSI_Out_DBx__DB4__PC CYREG_PRT2_PC5 +#define SCSI_Out_DBx__DB4__PORT 2u +#define SCSI_Out_DBx__DB4__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB4__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB4__SHIFT 5u +#define SCSI_Out_DBx__DB4__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB5__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB5__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB5__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB5__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB5__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB5__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB5__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB5__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB5__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB5__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB5__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB5__INTTYPE CYREG_PICU2_INTTYPE3 +#define SCSI_Out_DBx__DB5__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB5__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB5__MASK 0x08u +#define SCSI_Out_DBx__DB5__PC CYREG_PRT2_PC3 +#define SCSI_Out_DBx__DB5__PORT 2u +#define SCSI_Out_DBx__DB5__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB5__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB5__SHIFT 3u +#define SCSI_Out_DBx__DB5__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB6__AG CYREG_PRT2_AG +#define SCSI_Out_DBx__DB6__AMUX CYREG_PRT2_AMUX +#define SCSI_Out_DBx__DB6__BIE CYREG_PRT2_BIE +#define SCSI_Out_DBx__DB6__BIT_MASK CYREG_PRT2_BIT_MASK +#define SCSI_Out_DBx__DB6__BYP CYREG_PRT2_BYP +#define SCSI_Out_DBx__DB6__CTL CYREG_PRT2_CTL +#define SCSI_Out_DBx__DB6__DM0 CYREG_PRT2_DM0 +#define SCSI_Out_DBx__DB6__DM1 CYREG_PRT2_DM1 +#define SCSI_Out_DBx__DB6__DM2 CYREG_PRT2_DM2 +#define SCSI_Out_DBx__DB6__DR CYREG_PRT2_DR +#define SCSI_Out_DBx__DB6__INP_DIS CYREG_PRT2_INP_DIS +#define SCSI_Out_DBx__DB6__INTTYPE CYREG_PICU2_INTTYPE1 +#define SCSI_Out_DBx__DB6__LCD_COM_SEG CYREG_PRT2_LCD_COM_SEG +#define SCSI_Out_DBx__DB6__LCD_EN CYREG_PRT2_LCD_EN +#define SCSI_Out_DBx__DB6__MASK 0x02u +#define SCSI_Out_DBx__DB6__PC CYREG_PRT2_PC1 +#define SCSI_Out_DBx__DB6__PORT 2u +#define SCSI_Out_DBx__DB6__PRT CYREG_PRT2_PRT +#define SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL CYREG_PRT2_CAPS_SEL +#define SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN CYREG_PRT2_DBL_SYNC_IN +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 CYREG_PRT2_OE_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 CYREG_PRT2_OE_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 CYREG_PRT2_OUT_SEL0 +#define SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1 +#define SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT +#define SCSI_Out_DBx__DB6__PS CYREG_PRT2_PS +#define SCSI_Out_DBx__DB6__SHIFT 1u +#define SCSI_Out_DBx__DB6__SLW CYREG_PRT2_SLW +#define SCSI_Out_DBx__DB7__AG CYREG_PRT15_AG +#define SCSI_Out_DBx__DB7__AMUX CYREG_PRT15_AMUX +#define SCSI_Out_DBx__DB7__BIE CYREG_PRT15_BIE +#define SCSI_Out_DBx__DB7__BIT_MASK CYREG_PRT15_BIT_MASK +#define SCSI_Out_DBx__DB7__BYP CYREG_PRT15_BYP +#define SCSI_Out_DBx__DB7__CTL CYREG_PRT15_CTL +#define SCSI_Out_DBx__DB7__DM0 CYREG_PRT15_DM0 +#define SCSI_Out_DBx__DB7__DM1 CYREG_PRT15_DM1 +#define SCSI_Out_DBx__DB7__DM2 CYREG_PRT15_DM2 +#define SCSI_Out_DBx__DB7__DR CYREG_PRT15_DR +#define SCSI_Out_DBx__DB7__INP_DIS CYREG_PRT15_INP_DIS +#define SCSI_Out_DBx__DB7__INTTYPE CYREG_PICU15_INTTYPE5 +#define SCSI_Out_DBx__DB7__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define SCSI_Out_DBx__DB7__LCD_EN CYREG_PRT15_LCD_EN +#define SCSI_Out_DBx__DB7__MASK 0x20u +#define SCSI_Out_DBx__DB7__PC CYREG_IO_PC_PRT15_PC5 +#define SCSI_Out_DBx__DB7__PORT 15u +#define SCSI_Out_DBx__DB7__PRT CYREG_PRT15_PRT +#define SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define SCSI_Out_DBx__DB7__PS CYREG_PRT15_PS +#define SCSI_Out_DBx__DB7__SHIFT 5u +#define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW + +/* SD_PULLUP */ +#define SD_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE0 +#define SD_PULLUP__0__MASK 0x01u +#define SD_PULLUP__0__PC CYREG_PRT3_PC0 +#define SD_PULLUP__0__PORT 3u +#define SD_PULLUP__0__SHIFT 0u +#define SD_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE1 +#define SD_PULLUP__1__MASK 0x02u +#define SD_PULLUP__1__PC CYREG_PRT3_PC1 +#define SD_PULLUP__1__PORT 3u +#define SD_PULLUP__1__SHIFT 1u +#define SD_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE2 +#define SD_PULLUP__2__MASK 0x04u +#define SD_PULLUP__2__PC CYREG_PRT3_PC2 +#define SD_PULLUP__2__PORT 3u +#define SD_PULLUP__2__SHIFT 2u +#define SD_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE3 +#define SD_PULLUP__3__MASK 0x08u +#define SD_PULLUP__3__PC CYREG_PRT3_PC3 +#define SD_PULLUP__3__PORT 3u +#define SD_PULLUP__3__SHIFT 3u +#define SD_PULLUP__AG CYREG_PRT3_AG +#define SD_PULLUP__AMUX CYREG_PRT3_AMUX +#define SD_PULLUP__BIE CYREG_PRT3_BIE +#define SD_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SD_PULLUP__BYP CYREG_PRT3_BYP +#define SD_PULLUP__CTL CYREG_PRT3_CTL +#define SD_PULLUP__DM0 CYREG_PRT3_DM0 +#define SD_PULLUP__DM1 CYREG_PRT3_DM1 +#define SD_PULLUP__DM2 CYREG_PRT3_DM2 +#define SD_PULLUP__DR CYREG_PRT3_DR +#define SD_PULLUP__INP_DIS CYREG_PRT3_INP_DIS +#define SD_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SD_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SD_PULLUP__LCD_EN CYREG_PRT3_LCD_EN +#define SD_PULLUP__MASK 0x0Fu +#define SD_PULLUP__PORT 3u +#define SD_PULLUP__PRT CYREG_PRT3_PRT +#define SD_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SD_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SD_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SD_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SD_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SD_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SD_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SD_PULLUP__PS CYREG_PRT3_PS +#define SD_PULLUP__SHIFT 0u +#define SD_PULLUP__SLW CYREG_PRT3_SLW + +/* SPI_PULLUP */ +#define SPI_PULLUP__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define SPI_PULLUP__0__MASK 0x10u +#define SPI_PULLUP__0__PC CYREG_PRT3_PC4 +#define SPI_PULLUP__0__PORT 3u +#define SPI_PULLUP__0__SHIFT 4u +#define SPI_PULLUP__1__INTTYPE CYREG_PICU3_INTTYPE5 +#define SPI_PULLUP__1__MASK 0x20u +#define SPI_PULLUP__1__PC CYREG_PRT3_PC5 +#define SPI_PULLUP__1__PORT 3u +#define SPI_PULLUP__1__SHIFT 5u +#define SPI_PULLUP__2__INTTYPE CYREG_PICU3_INTTYPE6 +#define SPI_PULLUP__2__MASK 0x40u +#define SPI_PULLUP__2__PC CYREG_PRT3_PC6 +#define SPI_PULLUP__2__PORT 3u +#define SPI_PULLUP__2__SHIFT 6u +#define SPI_PULLUP__3__INTTYPE CYREG_PICU3_INTTYPE7 +#define SPI_PULLUP__3__MASK 0x80u +#define SPI_PULLUP__3__PC CYREG_PRT3_PC7 +#define SPI_PULLUP__3__PORT 3u +#define SPI_PULLUP__3__SHIFT 7u +#define SPI_PULLUP__AG CYREG_PRT3_AG +#define SPI_PULLUP__AMUX CYREG_PRT3_AMUX +#define SPI_PULLUP__BIE CYREG_PRT3_BIE +#define SPI_PULLUP__BIT_MASK CYREG_PRT3_BIT_MASK +#define SPI_PULLUP__BYP CYREG_PRT3_BYP +#define SPI_PULLUP__CTL CYREG_PRT3_CTL +#define SPI_PULLUP__DM0 CYREG_PRT3_DM0 +#define SPI_PULLUP__DM1 CYREG_PRT3_DM1 +#define SPI_PULLUP__DM2 CYREG_PRT3_DM2 +#define SPI_PULLUP__DR CYREG_PRT3_DR +#define SPI_PULLUP__INP_DIS CYREG_PRT3_INP_DIS +#define SPI_PULLUP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define SPI_PULLUP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define SPI_PULLUP__LCD_EN CYREG_PRT3_LCD_EN +#define SPI_PULLUP__MASK 0xF0u +#define SPI_PULLUP__PORT 3u +#define SPI_PULLUP__PRT CYREG_PRT3_PRT +#define SPI_PULLUP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define SPI_PULLUP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define SPI_PULLUP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define SPI_PULLUP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define SPI_PULLUP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define SPI_PULLUP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define SPI_PULLUP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define SPI_PULLUP__PS CYREG_PRT3_PS +#define SPI_PULLUP__SHIFT 4u +#define SPI_PULLUP__SLW CYREG_PRT3_SLW +#define SPI_PULLUP_1__0__INTTYPE CYREG_PICU12_INTTYPE0 +#define SPI_PULLUP_1__0__MASK 0x01u +#define SPI_PULLUP_1__0__PC CYREG_PRT12_PC0 +#define SPI_PULLUP_1__0__PORT 12u +#define SPI_PULLUP_1__0__SHIFT 0u +#define SPI_PULLUP_1__1__INTTYPE CYREG_PICU12_INTTYPE1 +#define SPI_PULLUP_1__1__MASK 0x02u +#define SPI_PULLUP_1__1__PC CYREG_PRT12_PC1 +#define SPI_PULLUP_1__1__PORT 12u +#define SPI_PULLUP_1__1__SHIFT 1u +#define SPI_PULLUP_1__AG CYREG_PRT12_AG +#define SPI_PULLUP_1__BIE CYREG_PRT12_BIE +#define SPI_PULLUP_1__BIT_MASK CYREG_PRT12_BIT_MASK +#define SPI_PULLUP_1__BYP CYREG_PRT12_BYP +#define SPI_PULLUP_1__DM0 CYREG_PRT12_DM0 +#define SPI_PULLUP_1__DM1 CYREG_PRT12_DM1 +#define SPI_PULLUP_1__DM2 CYREG_PRT12_DM2 +#define SPI_PULLUP_1__DR CYREG_PRT12_DR +#define SPI_PULLUP_1__INP_DIS CYREG_PRT12_INP_DIS +#define SPI_PULLUP_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define SPI_PULLUP_1__MASK 0x03u +#define SPI_PULLUP_1__PORT 12u +#define SPI_PULLUP_1__PRT CYREG_PRT12_PRT +#define SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define SPI_PULLUP_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define SPI_PULLUP_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define SPI_PULLUP_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define SPI_PULLUP_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define SPI_PULLUP_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define SPI_PULLUP_1__PS CYREG_PRT12_PS +#define SPI_PULLUP_1__SHIFT 0u +#define SPI_PULLUP_1__SIO_CFG CYREG_PRT12_SIO_CFG +#define SPI_PULLUP_1__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define SPI_PULLUP_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define SPI_PULLUP_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define SPI_PULLUP_1__SLW CYREG_PRT12_SLW + +/* Miscellaneous */ +#define BCLK__BUS_CLK__HZ 64000000U +#define BCLK__BUS_CLK__KHZ 64000U +#define BCLK__BUS_CLK__MHZ 64U +#define CY_PROJECT_NAME "USB_Bootloader" +#define CY_VERSION "PSoC Creator 4.2" +#define CYDEV_BOOTLOADER_APPLICATIONS 1u +#define CYDEV_BOOTLOADER_CHECKSUM_BASIC 0 +#define CYDEV_BOOTLOADER_CHECKSUM_CRC 1 +#define CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO 0 +#define CyBtldr_Custom_Interface CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +#define CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY 1 +#define CyBtldr_LAUNCHER_ONLY CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY +#define CYDEV_BOOTLOADER_IO_COMP_USBFS 2 +#define CyBtldr_USBFS CYDEV_BOOTLOADER_IO_COMP_USBFS +#define CYDEV_BOOTLOADER_IO_COMP CYDEV_BOOTLOADER_IO_COMP_USBFS +#define CYDEV_CHIP_DIE_LEOPARD 1u +#define CYDEV_CHIP_DIE_PSOC4A 18u +#define CYDEV_CHIP_DIE_PSOC5LP 2u +#define CYDEV_CHIP_DIE_PSOC5TM 3u +#define CYDEV_CHIP_DIE_TMA4 4u +#define CYDEV_CHIP_DIE_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_FM0P 5u +#define CYDEV_CHIP_FAMILY_FM3 6u +#define CYDEV_CHIP_FAMILY_FM4 7u +#define CYDEV_CHIP_FAMILY_PSOC3 1u +#define CYDEV_CHIP_FAMILY_PSOC4 2u +#define CYDEV_CHIP_FAMILY_PSOC5 3u +#define CYDEV_CHIP_FAMILY_PSOC6 4u +#define CYDEV_CHIP_FAMILY_UNKNOWN 0u +#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC5 +#define CYDEV_CHIP_JTAG_ID 0x2E133069u +#define CYDEV_CHIP_MEMBER_3A 1u +#define CYDEV_CHIP_MEMBER_4A 18u +#define CYDEV_CHIP_MEMBER_4D 13u +#define CYDEV_CHIP_MEMBER_4E 6u +#define CYDEV_CHIP_MEMBER_4F 19u +#define CYDEV_CHIP_MEMBER_4G 4u +#define CYDEV_CHIP_MEMBER_4H 17u +#define CYDEV_CHIP_MEMBER_4I 23u +#define CYDEV_CHIP_MEMBER_4J 14u +#define CYDEV_CHIP_MEMBER_4K 15u +#define CYDEV_CHIP_MEMBER_4L 22u +#define CYDEV_CHIP_MEMBER_4M 21u +#define CYDEV_CHIP_MEMBER_4N 10u +#define CYDEV_CHIP_MEMBER_4O 7u +#define CYDEV_CHIP_MEMBER_4P 20u +#define CYDEV_CHIP_MEMBER_4Q 12u +#define CYDEV_CHIP_MEMBER_4R 8u +#define CYDEV_CHIP_MEMBER_4S 11u +#define CYDEV_CHIP_MEMBER_4T 9u +#define CYDEV_CHIP_MEMBER_4U 5u +#define CYDEV_CHIP_MEMBER_4V 16u +#define CYDEV_CHIP_MEMBER_5A 3u +#define CYDEV_CHIP_MEMBER_5B 2u +#define CYDEV_CHIP_MEMBER_6A 24u +#define CYDEV_CHIP_MEMBER_FM3 28u +#define CYDEV_CHIP_MEMBER_FM4 29u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 25u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 26u +#define CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 27u +#define CYDEV_CHIP_MEMBER_UNKNOWN 0u +#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_5B +#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED +#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT +#define CYDEV_CHIP_REV_LEOPARD_ES1 0u +#define CYDEV_CHIP_REV_LEOPARD_ES2 1u +#define CYDEV_CHIP_REV_LEOPARD_ES3 3u +#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u +#define CYDEV_CHIP_REV_PSOC4A_ES0 17u +#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u +#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u +#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES0 0u +#define CYDEV_CHIP_REV_PSOC5TM_ES1 1u +#define CYDEV_CHIP_REV_PSOC5TM_PRODUCTION 1u +#define CYDEV_CHIP_REV_TMA4_ES 17u +#define CYDEV_CHIP_REV_TMA4_ES2 33u +#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_3A_ES1 0u +#define CYDEV_CHIP_REVISION_3A_ES2 1u +#define CYDEV_CHIP_REVISION_3A_ES3 3u +#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u +#define CYDEV_CHIP_REVISION_4A_ES0 17u +#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD 0u +#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u +#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u +#define CYDEV_CHIP_REVISION_4G_ES 17u +#define CYDEV_CHIP_REVISION_4G_ES2 33u +#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u +#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4O_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4P_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4Q_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4R_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4S_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4T_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_4V_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_5A_ES0 0u +#define CYDEV_CHIP_REVISION_5A_ES1 1u +#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u +#define CYDEV_CHIP_REVISION_5B_ES0 0u +#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_6A_ES 17u +#define CYDEV_CHIP_REVISION_6A_NO_UDB 33u +#define CYDEV_CHIP_REVISION_6A_PRODUCTION 33u +#define CYDEV_CHIP_REVISION_FM3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_FM4_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION 0u +#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_5B_PRODUCTION +#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED +#define CYDEV_CONFIG_FASTBOOT_ENABLED 1 +#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0 +#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn +#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1 +#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2 +#define CYDEV_CONFIGURATION_COMPRESSED 1 +#define CYDEV_CONFIGURATION_DMA 0 +#define CYDEV_CONFIGURATION_ECC 1 +#define CYDEV_CONFIGURATION_IMOENABLED CYDEV_CONFIG_FASTBOOT_ENABLED +#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0 +#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED +#define CYDEV_CONFIGURATION_MODE_DMA 2 +#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1 +#define CYDEV_DEBUG_ENABLE_MASK 0x20u +#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG +#define CYDEV_DEBUGGING_DPS_Disable 3 +#define CYDEV_DEBUGGING_DPS_JTAG_4 1 +#define CYDEV_DEBUGGING_DPS_JTAG_5 0 +#define CYDEV_DEBUGGING_DPS_SWD 2 +#define CYDEV_DEBUGGING_DPS_SWD_SWV 6 +#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_SWD_SWV +#define CYDEV_DEBUGGING_ENABLE 1 +#define CYDEV_DEBUGGING_XRES 0 +#define CYDEV_DMA_CHANNELS_AVAILABLE 24u +#define CYDEV_ECC_ENABLE 0 +#define CYDEV_HEAP_SIZE 0x0800 +#define CYDEV_INSTRUCT_CACHE_ENABLED 1 +#define CYDEV_INTR_RISING 0x00000000u +#define CYDEV_IS_EXPORTING_CODE 0 +#define CYDEV_IS_IMPORTING_CODE 0 +#define CYDEV_PROJ_TYPE 1 +#define CYDEV_PROJ_TYPE_BOOTLOADER 1 +#define CYDEV_PROJ_TYPE_LAUNCHER 5 +#define CYDEV_PROJ_TYPE_LOADABLE 2 +#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4 +#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3 +#define CYDEV_PROJ_TYPE_STANDARD 0 +#define CYDEV_PROTECTION_ENABLE 0 +#define CYDEV_STACK_SIZE 0x2000 +#define CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP +#define CYDEV_USE_BUNDLED_CMSIS 1 +#define CYDEV_VARIABLE_VDDA 0 +#define CYDEV_VDDA 5.0 +#define CYDEV_VDDA_MV 5000 +#define CYDEV_VDDD 5.0 +#define CYDEV_VDDD_MV 5000 +#define CYDEV_VDDIO0 5.0 +#define CYDEV_VDDIO0_MV 5000 +#define CYDEV_VDDIO1 5.0 +#define CYDEV_VDDIO1_MV 5000 +#define CYDEV_VDDIO2 5.0 +#define CYDEV_VDDIO2_MV 5000 +#define CYDEV_VDDIO3 3.0 +#define CYDEV_VDDIO3_MV 3000 +#define CYDEV_VIO0 5.0 +#define CYDEV_VIO0_MV 5000 +#define CYDEV_VIO1 5.0 +#define CYDEV_VIO1_MV 5000 +#define CYDEV_VIO2 5.0 +#define CYDEV_VIO2_MV 5000 +#define CYDEV_VIO3 3.0 +#define CYDEV_VIO3_MV 3000 +#define CYIPBLOCK_ARM_CM3_VERSION 0 +#define CYIPBLOCK_P3_ANAIF_VERSION 0 +#define CYIPBLOCK_P3_CAPSENSE_VERSION 0 +#define CYIPBLOCK_P3_COMP_VERSION 0 +#define CYIPBLOCK_P3_DMA_VERSION 0 +#define CYIPBLOCK_P3_DRQ_VERSION 0 +#define CYIPBLOCK_P3_EMIF_VERSION 0 +#define CYIPBLOCK_P3_I2C_VERSION 0 +#define CYIPBLOCK_P3_LCD_VERSION 0 +#define CYIPBLOCK_P3_LPF_VERSION 0 +#define CYIPBLOCK_P3_PM_VERSION 0 +#define CYIPBLOCK_P3_TIMER_VERSION 0 +#define CYIPBLOCK_P3_USB_VERSION 0 +#define CYIPBLOCK_P3_VIDAC_VERSION 0 +#define CYIPBLOCK_P3_VREF_VERSION 0 +#define CYIPBLOCK_S8_GPIO_VERSION 0 +#define CYIPBLOCK_S8_IRQ_VERSION 0 +#define CYIPBLOCK_S8_SAR_VERSION 0 +#define CYIPBLOCK_S8_SIO_VERSION 0 +#define CYIPBLOCK_S8_UDB_VERSION 0 +#define DMA_CHANNELS_USED__MASK0 0x00000000u +#define CYDEV_BOOTLOADER_ENABLE 1 + +#endif /* INCLUDED_CYFITTER_H */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c new file mode 100644 index 0000000..4375ff9 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -0,0 +1,476 @@ + +/******************************************************************************* +* File Name: cyfitter_cfg.c +* +* PSoC Creator 4.2 +* +* Description: +* This file contains device initialization code. +* Except for the user defined sections in CyClockStartupError(), this file should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include +#include "cytypes.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "CyLib.h" +#include "cyfitter_cfg.h" + +#define CY_NEED_CYCLOCKSTARTUPERROR 1 + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) + #define CYPACKED + #define CYPACKED_ATTR __attribute__ ((packed)) + #define CYALIGNED __attribute__ ((aligned)) + #define CY_CFG_UNUSED __attribute__ ((unused)) + #ifndef CY_CFG_SECTION + #define CY_CFG_SECTION __attribute__ ((section(".psocinit"))) + #endif + + #if defined(__ARMCC_VERSION) + #define CY_CFG_MEMORY_BARRIER() __memory_changed() + #else + #define CY_CFG_MEMORY_BARRIER() __sync_synchronize() + #endif + +#elif defined(__ICCARM__) + #include + + #define CYPACKED __packed + #define CYPACKED_ATTR + #define CYALIGNED _Pragma("data_alignment=4") + #define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177") + #define CY_CFG_SECTION _Pragma("location=\".psocinit\"") + + #define CY_CFG_MEMORY_BARRIER() __DMB() + +#else + #error Unsupported toolchain +#endif + +#ifndef CYCODE + #define CYCODE +#endif +#ifndef CYDATA + #define CYDATA +#endif +#ifndef CYFAR + #define CYFAR +#endif +#ifndef CYXDATA + #define CYXDATA +#endif + + +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n); +CY_CFG_UNUSED +static void CYMEMZERO(void *s, size_t n) +{ + (void)memset(s, 0, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPY(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n); +CY_CFG_UNUSED +static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n) +{ + (void)memcpy(dest, src, n); +} + + + + +/* Clock startup error codes */ +#define CYCLOCKSTART_NO_ERROR 0u +#define CYCLOCKSTART_XTAL_ERROR 1u +#define CYCLOCKSTART_32KHZ_ERROR 2u +#define CYCLOCKSTART_PLL_ERROR 3u +#define CYCLOCKSTART_FLL_ERROR 4u +#define CYCLOCKSTART_WCO_ERROR 5u + + +#ifdef CY_NEED_CYCLOCKSTARTUPERROR +/******************************************************************************* +* Function Name: CyClockStartupError +******************************************************************************** +* Summary: +* If an error is encountered during clock configuration (crystal startup error, +* PLL lock error, etc.), the system will end up here. Unless reimplemented by +* the customer, this function will stop in an infinite loop. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode); +CY_CFG_UNUSED +static void CyClockStartupError(uint8 errorCode) +{ + /* To remove the compiler warning if errorCode not used. */ + errorCode = errorCode; + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + +#ifdef CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK + CY_CFG_Clock_Startup_ErrorCallback(); +#else + /* If not using CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK, place your clock startup code here. */ + /* `#START CyClockStartupError` */ + + /* If we have a clock startup error (bad MHz crystal, PLL lock, etc.), */ + /* we will end up here to allow the customer to implement something to */ + /* deal with the clock condition. */ + + /* `#END` */ + + while(1) {} +#endif /* CY_CFG_CLOCK_STARTUP_ERROR_CALLBACK */ +} +#endif + +#define CY_CFG_BASE_ADDR_COUNT 12u +CYPACKED typedef struct +{ + uint8 offset; + uint8 value; +} CYPACKED_ATTR cy_cfg_addrvalue_t; + + + +/******************************************************************************* +* Function Name: cfg_write_bytes32 +******************************************************************************** +* Summary: +* This function is used for setting up the chip configuration areas that +* contain relatively sparse data. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]); +static void cfg_write_bytes32(const uint32 addr_table[], const cy_cfg_addrvalue_t data_table[]) +{ + /* For 32-bit little-endian architectures */ + uint32 i, j = 0u; + for (i = 0u; i < CY_CFG_BASE_ADDR_COUNT; i++) + { + uint32 baseAddr = addr_table[i]; + uint8 count = (uint8)baseAddr; + baseAddr &= 0xFFFFFF00u; + while (count != 0u) + { + CY_SET_REG8((void *)(baseAddr + data_table[j].offset), data_table[j].value); + j++; + count--; + } + } +} + +/******************************************************************************* +* Function Name: ClockSetup +******************************************************************************** +* +* Summary: +* Performs the initialization of all of the clocks in the device based on the +* settings in the Clock tab of the DWR. This includes enabling the requested +* clocks and setting the necessary dividers to produce the desired frequency. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void ClockSetup(void); +static void ClockSetup(void) +{ + uint32 timeout; + uint8 pllLock; + + + /* Configure ILO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); + + /* Configure IMO based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_FASTCLK_IMO_CR), 0x52u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_IMO_TR1), (CY_GET_XTND_REG8((void CYFAR *)CYREG_FLSHID_CUST_TABLES_IMO_USB))); + + /* Configure PLL based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0818u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u); + /* Wait up to 250us for the PLL to lock */ + pllLock = 0u; + for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) + { + pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0)); + CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */ + } + /* If we ran out of time the PLL didn't lock so go to the error function */ + if (timeout == 0u) + { + CyClockStartupError(CYCLOCKSTART_PLL_ERROR); + } + + /* Configure Bus/Master Clock based on settings from Clock DWR */ + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x07u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG0), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_BCFG2), 0x48u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x00u); + + /* Configure USB Clock based on settings from Clock DWR */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); +} + + +/* Analog API Functions */ + + +/******************************************************************************* +* Function Name: AnalogSetDefault +******************************************************************************** +* +* Summary: +* Sets up the analog portions of the chip to default values based on chip +* configuration options from the project. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ +static void AnalogSetDefault(void); +static void AnalogSetDefault(void) +{ + uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u)); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu)); + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u); +} + + +/******************************************************************************* +* Function Name: SetAnalogRoutingPumps +******************************************************************************** +* +* Summary: +* Enables or disables the analog pumps feeding analog routing switches. +* Intended to be called at startup, based on the Vdda system configuration; +* may be called during operation when the user informs us that the Vdda voltage +* crossed the pump threshold. +* +* Parameters: +* enabled - 1 to enable the pumps, 0 to disable the pumps +* +* Return: +* void +* +*******************************************************************************/ +void SetAnalogRoutingPumps(uint8 enabled) +{ + uint8 regValue = CY_GET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0); + if (enabled != 0u) + { + regValue |= 0x00u; + } + else + { + regValue &= (uint8)~0x00u; + } + CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, regValue); +} + + + + +/******************************************************************************* +* Function Name: cyfitter_cfg +******************************************************************************** +* Summary: +* This function is called by the start-up code for the selected device. It +* performs all of the necessary device configuration based on the design +* settings. This includes settings from the Design Wide Resources (DWR) such +* as Clocks and Pins as well as any component configuration that is necessary. +* +* Parameters: +* void +* +* Return: +* void +* +*******************************************************************************/ + +void cyfitter_cfg(void) +{ + /* IOPINS0_0 Address: CYREG_PRT0_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_0_VAL[] = { + 0x01u, 0x00u, 0x00u, 0xABu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_7_VAL[] = { + 0x0Fu, 0x00u, 0x00u, 0x2Fu, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ + static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { + 0x00u, 0x00u, 0x00u, 0x28u, 0x28u, 0x00u, 0x00u, 0x00u, 0xC0u, 0x00u}; + + /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_1_VAL[] = { + 0x00u, 0x0Bu, 0x0Bu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_2_VAL[] = { + 0x00u, 0xAAu, 0xAAu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_3 Address: CYREG_PRT3_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { + 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { + 0x00u, 0x43u, 0x43u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + + /* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */ + static const uint8 CYCODE BS_IOPINS0_6_VAL[] = { + 0x00u, 0xA4u, 0xA4u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; + +#ifdef CYGlobalIntDisable + /* Disable interrupts by default. Let user enable if/when they want. */ + CYGlobalIntDisable +#endif + + + /* Set Flash Cycles based on max possible frequency in case a glitch occurs during ClockSetup(). */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x61u : 0x60u)); + /* Setup clocks based on selections from Clock DWR */ + ClockSetup(); + /* Set Flash Cycles based on newly configured 64.00MHz Bus Clock. */ + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CACHE_CC_CTL), (((CYDEV_INSTRUCT_CACHE_ENABLED) != 0) ? 0x01u : 0x00u)); + /* Enable/Disable Debug functionality based on settings from System DWR */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG, (CY_GET_XTND_REG8((void CYFAR *)CYREG_MLOGIC_DEBUG) | 0x04u)); + + { + static const uint32 CYCODE cy_cfg_addr_table[] = { + 0x40004501u, /* Base address: 0x40004500 Count: 1 */ + 0x40005204u, /* Base address: 0x40005200 Count: 4 */ + 0x40011701u, /* Base address: 0x40011700 Count: 1 */ + 0x40011901u, /* Base address: 0x40011900 Count: 1 */ + 0x40014003u, /* Base address: 0x40014000 Count: 3 */ + 0x40014102u, /* Base address: 0x40014100 Count: 2 */ + 0x40014202u, /* Base address: 0x40014200 Count: 2 */ + 0x40014302u, /* Base address: 0x40014300 Count: 2 */ + 0x40014703u, /* Base address: 0x40014700 Count: 3 */ + 0x40014803u, /* Base address: 0x40014800 Count: 3 */ + 0x40014C02u, /* Base address: 0x40014C00 Count: 2 */ + 0x40015101u, /* Base address: 0x40015100 Count: 1 */ + }; + + static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { + {0x7Eu, 0x02u}, + {0x04u, 0x01u}, + {0x1Cu, 0xFFu}, + {0x64u, 0x03u}, + {0x7Cu, 0x40u}, + {0xEEu, 0x0Au}, + {0xEEu, 0x0Au}, + {0x33u, 0x80u}, + {0x36u, 0x40u}, + {0xCCu, 0x30u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0xA6u, 0x40u}, + {0xA7u, 0x80u}, + {0x08u, 0x08u}, + {0x0Fu, 0x40u}, + {0xC2u, 0x0Cu}, + {0xAEu, 0x40u}, + {0xAFu, 0x80u}, + {0xEEu, 0x50u}, + {0xACu, 0x08u}, + {0xAFu, 0x40u}, + {0x00u, 0x0Au}, + }; + + + + CYPACKED typedef struct { + void CYFAR *address; + uint16 size; + } CYPACKED_ATTR cfg_memset_t; + + static const cfg_memset_t CYCODE cfg_memset_list[] = { + /* address, size */ + {(void CYFAR *)(CYREG_PRT5_DR), 16u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, + {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, + {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, + {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u}, + }; + + uint8 CYDATA i; + + /* Zero out critical memory blocks before beginning configuration */ + for (i = 0u; i < (sizeof(cfg_memset_list)/sizeof(cfg_memset_list[0])); i++) + { + const cfg_memset_t CYCODE * CYDATA ms = &cfg_memset_list[i]; + CYMEMZERO(ms->address, (size_t)(uint32)(ms->size)); + } + + cfg_write_bytes32(cy_cfg_addr_table, cy_cfg_data_table); + + /* Enable digital routing */ + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL0_BANK_CTL) | 0x02u); + CY_SET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL, CY_GET_XTND_REG8((void CYFAR *)CYREG_BCTL1_BANK_CTL) | 0x02u); + } + + + /* Perform second pass device configuration. These items must be configured in specific order after the regular configuration is done. */ + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT0_DR), (const void CYCODE *)(BS_IOPINS0_0_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT12_DR), (const void CYCODE *)(BS_IOPINS0_7_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT15_DR), (const void CYCODE *)(BS_IOPINS0_8_VAL), 10u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT1_DM0), (const void CYCODE *)(BS_IOPINS0_1_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT2_DM0), (const void CYCODE *)(BS_IOPINS0_2_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT3_DM0), (const void CYCODE *)(BS_IOPINS0_3_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT4_DM0), (const void CYCODE *)(BS_IOPINS0_4_VAL), 8u); + CYCONFIGCPYCODE((void CYFAR *)(CYREG_PRT6_DM0), (const void CYCODE *)(BS_IOPINS0_6_VAL), 8u); + /* Switch Boost to the precision bandgap reference from its internal reference */ + CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u)); + + /* Perform basic analog initialization to defaults */ + AnalogSetDefault(); + + /* Configure alternate active mode */ + CYCONFIGCPY((void CYFAR *)CYDEV_PM_STBY_BASE, (const void CYFAR *)CYDEV_PM_ACT_BASE, 14u); +} diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h new file mode 100644 index 0000000..eefc440 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cyfitter_cfg.h +* +* PSoC Creator 4.2 +* +* Description: +* This file provides basic startup and mux configuration settings +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#ifndef CYFITTER_CFG_H +#define CYFITTER_CFG_H + +#include "cytypes.h" + +extern void cyfitter_cfg(void); + +/* Analog Set/Unset methods */ +extern void SetAnalogRoutingPumps(uint8 enabled); + + +#endif /* CYFITTER_CFG_H */ + +/*[]*/ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc new file mode 100644 index 0000000..1667be7 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -0,0 +1,1602 @@ +/******************************************************************************* +* File Name: cyfittergnu.inc +* +* PSoC Creator 4.2 +* +* Description: +* +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +.ifndef INCLUDED_CYFITTERGNU_INC +.set INCLUDED_CYFITTERGNU_INC, 1 +.include "cydevicegnu.inc" +.include "cydevicegnu_trm.inc" + +/* LED */ +.set LED__0__INTTYPE, CYREG_PICU12_INTTYPE2 +.set LED__0__MASK, 0x04 +.set LED__0__PC, CYREG_PRT12_PC2 +.set LED__0__PORT, 12 +.set LED__0__SHIFT, 2 +.set LED__1__INTTYPE, CYREG_PICU12_INTTYPE3 +.set LED__1__MASK, 0x08 +.set LED__1__PC, CYREG_PRT12_PC3 +.set LED__1__PORT, 12 +.set LED__1__SHIFT, 3 +.set LED__AG, CYREG_PRT12_AG +.set LED__BIE, CYREG_PRT12_BIE +.set LED__BIT_MASK, CYREG_PRT12_BIT_MASK +.set LED__BYP, CYREG_PRT12_BYP +.set LED__DM0, CYREG_PRT12_DM0 +.set LED__DM1, CYREG_PRT12_DM1 +.set LED__DM2, CYREG_PRT12_DM2 +.set LED__DR, CYREG_PRT12_DR +.set LED__INP_DIS, CYREG_PRT12_INP_DIS +.set LED__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE +.set LED__MASK, 0x0C +.set LED__PORT, 12 +.set LED__PRT, CYREG_PRT12_PRT +.set LED__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set LED__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set LED__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set LED__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set LED__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set LED__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set LED__PS, CYREG_PRT12_PS +.set LED__SHIFT, 2 +.set LED__SIO_CFG, CYREG_PRT12_SIO_CFG +.set LED__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set LED__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set LED__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set LED__SLW, CYREG_PRT12_SLW + +/* USBFS */ +.set USBFS_arb_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_arb_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_arb_int__INTC_MASK, 0x400000 +.set USBFS_arb_int__INTC_NUMBER, 22 +.set USBFS_arb_int__INTC_PRIOR_NUM, 7 +.set USBFS_arb_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_22 +.set USBFS_arb_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_arb_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_bus_reset__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_bus_reset__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_bus_reset__INTC_MASK, 0x800000 +.set USBFS_bus_reset__INTC_NUMBER, 23 +.set USBFS_bus_reset__INTC_PRIOR_NUM, 7 +.set USBFS_bus_reset__INTC_PRIOR_REG, CYREG_NVIC_PRI_23 +.set USBFS_bus_reset__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_bus_reset__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_Dm__0__INTTYPE, CYREG_PICU15_INTTYPE7 +.set USBFS_Dm__0__MASK, 0x80 +.set USBFS_Dm__0__PC, CYREG_IO_PC_PRT15_7_6_PC1 +.set USBFS_Dm__0__PORT, 15 +.set USBFS_Dm__0__SHIFT, 7 +.set USBFS_Dm__AG, CYREG_PRT15_AG +.set USBFS_Dm__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dm__BIE, CYREG_PRT15_BIE +.set USBFS_Dm__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dm__BYP, CYREG_PRT15_BYP +.set USBFS_Dm__CTL, CYREG_PRT15_CTL +.set USBFS_Dm__DM0, CYREG_PRT15_DM0 +.set USBFS_Dm__DM1, CYREG_PRT15_DM1 +.set USBFS_Dm__DM2, CYREG_PRT15_DM2 +.set USBFS_Dm__DR, CYREG_PRT15_DR +.set USBFS_Dm__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dm__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dm__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dm__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dm__MASK, 0x80 +.set USBFS_Dm__PORT, 15 +.set USBFS_Dm__PRT, CYREG_PRT15_PRT +.set USBFS_Dm__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dm__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dm__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dm__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dm__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dm__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dm__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dm__PS, CYREG_PRT15_PS +.set USBFS_Dm__SHIFT, 7 +.set USBFS_Dm__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__0__INTTYPE, CYREG_PICU15_INTTYPE6 +.set USBFS_Dp__0__MASK, 0x40 +.set USBFS_Dp__0__PC, CYREG_IO_PC_PRT15_7_6_PC0 +.set USBFS_Dp__0__PORT, 15 +.set USBFS_Dp__0__SHIFT, 6 +.set USBFS_Dp__AG, CYREG_PRT15_AG +.set USBFS_Dp__AMUX, CYREG_PRT15_AMUX +.set USBFS_Dp__BIE, CYREG_PRT15_BIE +.set USBFS_Dp__BIT_MASK, CYREG_PRT15_BIT_MASK +.set USBFS_Dp__BYP, CYREG_PRT15_BYP +.set USBFS_Dp__CTL, CYREG_PRT15_CTL +.set USBFS_Dp__DM0, CYREG_PRT15_DM0 +.set USBFS_Dp__DM1, CYREG_PRT15_DM1 +.set USBFS_Dp__DM2, CYREG_PRT15_DM2 +.set USBFS_Dp__DR, CYREG_PRT15_DR +.set USBFS_Dp__INP_DIS, CYREG_PRT15_INP_DIS +.set USBFS_Dp__INTSTAT, CYREG_PICU15_INTSTAT +.set USBFS_Dp__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set USBFS_Dp__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set USBFS_Dp__LCD_EN, CYREG_PRT15_LCD_EN +.set USBFS_Dp__MASK, 0x40 +.set USBFS_Dp__PORT, 15 +.set USBFS_Dp__PRT, CYREG_PRT15_PRT +.set USBFS_Dp__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set USBFS_Dp__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set USBFS_Dp__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set USBFS_Dp__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set USBFS_Dp__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set USBFS_Dp__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set USBFS_Dp__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set USBFS_Dp__PS, CYREG_PRT15_PS +.set USBFS_Dp__SHIFT, 6 +.set USBFS_Dp__SLW, CYREG_PRT15_SLW +.set USBFS_Dp__SNAP, CYREG_PICU_15_SNAP_15 +.set USBFS_dp_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_dp_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_dp_int__INTC_MASK, 0x1000 +.set USBFS_dp_int__INTC_NUMBER, 12 +.set USBFS_dp_int__INTC_PRIOR_NUM, 7 +.set USBFS_dp_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_12 +.set USBFS_dp_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_dp_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_0__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_0__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_0__INTC_MASK, 0x1000000 +.set USBFS_ep_0__INTC_NUMBER, 24 +.set USBFS_ep_0__INTC_PRIOR_NUM, 7 +.set USBFS_ep_0__INTC_PRIOR_REG, CYREG_NVIC_PRI_24 +.set USBFS_ep_0__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_0__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_1__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_1__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_1__INTC_MASK, 0x01 +.set USBFS_ep_1__INTC_NUMBER, 0 +.set USBFS_ep_1__INTC_PRIOR_NUM, 7 +.set USBFS_ep_1__INTC_PRIOR_REG, CYREG_NVIC_PRI_0 +.set USBFS_ep_1__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_1__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_ep_2__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_ep_2__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_ep_2__INTC_MASK, 0x02 +.set USBFS_ep_2__INTC_NUMBER, 1 +.set USBFS_ep_2__INTC_PRIOR_NUM, 7 +.set USBFS_ep_2__INTC_PRIOR_REG, CYREG_NVIC_PRI_1 +.set USBFS_ep_2__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_ep_2__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_sof_int__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 +.set USBFS_sof_int__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0 +.set USBFS_sof_int__INTC_MASK, 0x200000 +.set USBFS_sof_int__INTC_NUMBER, 21 +.set USBFS_sof_int__INTC_PRIOR_NUM, 7 +.set USBFS_sof_int__INTC_PRIOR_REG, CYREG_NVIC_PRI_21 +.set USBFS_sof_int__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 +.set USBFS_sof_int__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +.set USBFS_USB__ARB_CFG, CYREG_USB_ARB_CFG +.set USBFS_USB__ARB_EP1_CFG, CYREG_USB_ARB_EP1_CFG +.set USBFS_USB__ARB_EP1_INT_EN, CYREG_USB_ARB_EP1_INT_EN +.set USBFS_USB__ARB_EP1_SR, CYREG_USB_ARB_EP1_SR +.set USBFS_USB__ARB_EP2_CFG, CYREG_USB_ARB_EP2_CFG +.set USBFS_USB__ARB_EP2_INT_EN, CYREG_USB_ARB_EP2_INT_EN +.set USBFS_USB__ARB_EP2_SR, CYREG_USB_ARB_EP2_SR +.set USBFS_USB__ARB_EP3_CFG, CYREG_USB_ARB_EP3_CFG +.set USBFS_USB__ARB_EP3_INT_EN, CYREG_USB_ARB_EP3_INT_EN +.set USBFS_USB__ARB_EP3_SR, CYREG_USB_ARB_EP3_SR +.set USBFS_USB__ARB_EP4_CFG, CYREG_USB_ARB_EP4_CFG +.set USBFS_USB__ARB_EP4_INT_EN, CYREG_USB_ARB_EP4_INT_EN +.set USBFS_USB__ARB_EP4_SR, CYREG_USB_ARB_EP4_SR +.set USBFS_USB__ARB_EP5_CFG, CYREG_USB_ARB_EP5_CFG +.set USBFS_USB__ARB_EP5_INT_EN, CYREG_USB_ARB_EP5_INT_EN +.set USBFS_USB__ARB_EP5_SR, CYREG_USB_ARB_EP5_SR +.set USBFS_USB__ARB_EP6_CFG, CYREG_USB_ARB_EP6_CFG +.set USBFS_USB__ARB_EP6_INT_EN, CYREG_USB_ARB_EP6_INT_EN +.set USBFS_USB__ARB_EP6_SR, CYREG_USB_ARB_EP6_SR +.set USBFS_USB__ARB_EP7_CFG, CYREG_USB_ARB_EP7_CFG +.set USBFS_USB__ARB_EP7_INT_EN, CYREG_USB_ARB_EP7_INT_EN +.set USBFS_USB__ARB_EP7_SR, CYREG_USB_ARB_EP7_SR +.set USBFS_USB__ARB_EP8_CFG, CYREG_USB_ARB_EP8_CFG +.set USBFS_USB__ARB_EP8_INT_EN, CYREG_USB_ARB_EP8_INT_EN +.set USBFS_USB__ARB_EP8_SR, CYREG_USB_ARB_EP8_SR +.set USBFS_USB__ARB_INT_EN, CYREG_USB_ARB_INT_EN +.set USBFS_USB__ARB_INT_SR, CYREG_USB_ARB_INT_SR +.set USBFS_USB__ARB_RW1_DR, CYREG_USB_ARB_RW1_DR +.set USBFS_USB__ARB_RW1_RA, CYREG_USB_ARB_RW1_RA +.set USBFS_USB__ARB_RW1_RA_MSB, CYREG_USB_ARB_RW1_RA_MSB +.set USBFS_USB__ARB_RW1_WA, CYREG_USB_ARB_RW1_WA +.set USBFS_USB__ARB_RW1_WA_MSB, CYREG_USB_ARB_RW1_WA_MSB +.set USBFS_USB__ARB_RW2_DR, CYREG_USB_ARB_RW2_DR +.set USBFS_USB__ARB_RW2_RA, CYREG_USB_ARB_RW2_RA +.set USBFS_USB__ARB_RW2_RA_MSB, CYREG_USB_ARB_RW2_RA_MSB +.set USBFS_USB__ARB_RW2_WA, CYREG_USB_ARB_RW2_WA +.set USBFS_USB__ARB_RW2_WA_MSB, CYREG_USB_ARB_RW2_WA_MSB +.set USBFS_USB__ARB_RW3_DR, CYREG_USB_ARB_RW3_DR +.set USBFS_USB__ARB_RW3_RA, CYREG_USB_ARB_RW3_RA +.set USBFS_USB__ARB_RW3_RA_MSB, CYREG_USB_ARB_RW3_RA_MSB +.set USBFS_USB__ARB_RW3_WA, CYREG_USB_ARB_RW3_WA +.set USBFS_USB__ARB_RW3_WA_MSB, CYREG_USB_ARB_RW3_WA_MSB +.set USBFS_USB__ARB_RW4_DR, CYREG_USB_ARB_RW4_DR +.set USBFS_USB__ARB_RW4_RA, CYREG_USB_ARB_RW4_RA +.set USBFS_USB__ARB_RW4_RA_MSB, CYREG_USB_ARB_RW4_RA_MSB +.set USBFS_USB__ARB_RW4_WA, CYREG_USB_ARB_RW4_WA +.set USBFS_USB__ARB_RW4_WA_MSB, CYREG_USB_ARB_RW4_WA_MSB +.set USBFS_USB__ARB_RW5_DR, CYREG_USB_ARB_RW5_DR +.set USBFS_USB__ARB_RW5_RA, CYREG_USB_ARB_RW5_RA +.set USBFS_USB__ARB_RW5_RA_MSB, CYREG_USB_ARB_RW5_RA_MSB +.set USBFS_USB__ARB_RW5_WA, CYREG_USB_ARB_RW5_WA +.set USBFS_USB__ARB_RW5_WA_MSB, CYREG_USB_ARB_RW5_WA_MSB +.set USBFS_USB__ARB_RW6_DR, CYREG_USB_ARB_RW6_DR +.set USBFS_USB__ARB_RW6_RA, CYREG_USB_ARB_RW6_RA +.set USBFS_USB__ARB_RW6_RA_MSB, CYREG_USB_ARB_RW6_RA_MSB +.set USBFS_USB__ARB_RW6_WA, CYREG_USB_ARB_RW6_WA +.set USBFS_USB__ARB_RW6_WA_MSB, CYREG_USB_ARB_RW6_WA_MSB +.set USBFS_USB__ARB_RW7_DR, CYREG_USB_ARB_RW7_DR +.set USBFS_USB__ARB_RW7_RA, CYREG_USB_ARB_RW7_RA +.set USBFS_USB__ARB_RW7_RA_MSB, CYREG_USB_ARB_RW7_RA_MSB +.set USBFS_USB__ARB_RW7_WA, CYREG_USB_ARB_RW7_WA +.set USBFS_USB__ARB_RW7_WA_MSB, CYREG_USB_ARB_RW7_WA_MSB +.set USBFS_USB__ARB_RW8_DR, CYREG_USB_ARB_RW8_DR +.set USBFS_USB__ARB_RW8_RA, CYREG_USB_ARB_RW8_RA +.set USBFS_USB__ARB_RW8_RA_MSB, CYREG_USB_ARB_RW8_RA_MSB +.set USBFS_USB__ARB_RW8_WA, CYREG_USB_ARB_RW8_WA +.set USBFS_USB__ARB_RW8_WA_MSB, CYREG_USB_ARB_RW8_WA_MSB +.set USBFS_USB__BUF_SIZE, CYREG_USB_BUF_SIZE +.set USBFS_USB__BUS_RST_CNT, CYREG_USB_BUS_RST_CNT +.set USBFS_USB__CR0, CYREG_USB_CR0 +.set USBFS_USB__CR1, CYREG_USB_CR1 +.set USBFS_USB__CWA, CYREG_USB_CWA +.set USBFS_USB__CWA_MSB, CYREG_USB_CWA_MSB +.set USBFS_USB__DMA_THRES, CYREG_USB_DMA_THRES +.set USBFS_USB__DMA_THRES_MSB, CYREG_USB_DMA_THRES_MSB +.set USBFS_USB__DYN_RECONFIG, CYREG_USB_DYN_RECONFIG +.set USBFS_USB__EP_ACTIVE, CYREG_USB_EP_ACTIVE +.set USBFS_USB__EP_TYPE, CYREG_USB_EP_TYPE +.set USBFS_USB__EP0_CNT, CYREG_USB_EP0_CNT +.set USBFS_USB__EP0_CR, CYREG_USB_EP0_CR +.set USBFS_USB__EP0_DR0, CYREG_USB_EP0_DR0 +.set USBFS_USB__EP0_DR1, CYREG_USB_EP0_DR1 +.set USBFS_USB__EP0_DR2, CYREG_USB_EP0_DR2 +.set USBFS_USB__EP0_DR3, CYREG_USB_EP0_DR3 +.set USBFS_USB__EP0_DR4, CYREG_USB_EP0_DR4 +.set USBFS_USB__EP0_DR5, CYREG_USB_EP0_DR5 +.set USBFS_USB__EP0_DR6, CYREG_USB_EP0_DR6 +.set USBFS_USB__EP0_DR7, CYREG_USB_EP0_DR7 +.set USBFS_USB__MEM_DATA, CYREG_USB_MEM_DATA_MBASE +.set USBFS_USB__PM_ACT_CFG, CYREG_PM_ACT_CFG5 +.set USBFS_USB__PM_ACT_MSK, 0x01 +.set USBFS_USB__PM_STBY_CFG, CYREG_PM_STBY_CFG5 +.set USBFS_USB__PM_STBY_MSK, 0x01 +.set USBFS_USB__SIE_EP_INT_EN, CYREG_USB_SIE_EP_INT_EN +.set USBFS_USB__SIE_EP_INT_SR, CYREG_USB_SIE_EP_INT_SR +.set USBFS_USB__SIE_EP1_CNT0, CYREG_USB_SIE_EP1_CNT0 +.set USBFS_USB__SIE_EP1_CNT1, CYREG_USB_SIE_EP1_CNT1 +.set USBFS_USB__SIE_EP1_CR0, CYREG_USB_SIE_EP1_CR0 +.set USBFS_USB__SIE_EP2_CNT0, CYREG_USB_SIE_EP2_CNT0 +.set USBFS_USB__SIE_EP2_CNT1, CYREG_USB_SIE_EP2_CNT1 +.set USBFS_USB__SIE_EP2_CR0, CYREG_USB_SIE_EP2_CR0 +.set USBFS_USB__SIE_EP3_CNT0, CYREG_USB_SIE_EP3_CNT0 +.set USBFS_USB__SIE_EP3_CNT1, CYREG_USB_SIE_EP3_CNT1 +.set USBFS_USB__SIE_EP3_CR0, CYREG_USB_SIE_EP3_CR0 +.set USBFS_USB__SIE_EP4_CNT0, CYREG_USB_SIE_EP4_CNT0 +.set USBFS_USB__SIE_EP4_CNT1, CYREG_USB_SIE_EP4_CNT1 +.set USBFS_USB__SIE_EP4_CR0, CYREG_USB_SIE_EP4_CR0 +.set USBFS_USB__SIE_EP5_CNT0, CYREG_USB_SIE_EP5_CNT0 +.set USBFS_USB__SIE_EP5_CNT1, CYREG_USB_SIE_EP5_CNT1 +.set USBFS_USB__SIE_EP5_CR0, CYREG_USB_SIE_EP5_CR0 +.set USBFS_USB__SIE_EP6_CNT0, CYREG_USB_SIE_EP6_CNT0 +.set USBFS_USB__SIE_EP6_CNT1, CYREG_USB_SIE_EP6_CNT1 +.set USBFS_USB__SIE_EP6_CR0, CYREG_USB_SIE_EP6_CR0 +.set USBFS_USB__SIE_EP7_CNT0, CYREG_USB_SIE_EP7_CNT0 +.set USBFS_USB__SIE_EP7_CNT1, CYREG_USB_SIE_EP7_CNT1 +.set USBFS_USB__SIE_EP7_CR0, CYREG_USB_SIE_EP7_CR0 +.set USBFS_USB__SIE_EP8_CNT0, CYREG_USB_SIE_EP8_CNT0 +.set USBFS_USB__SIE_EP8_CNT1, CYREG_USB_SIE_EP8_CNT1 +.set USBFS_USB__SIE_EP8_CR0, CYREG_USB_SIE_EP8_CR0 +.set USBFS_USB__SOF0, CYREG_USB_SOF0 +.set USBFS_USB__SOF1, CYREG_USB_SOF1 +.set USBFS_USB__USB_CLK_EN, CYREG_USB_USB_CLK_EN +.set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 +.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 + +/* BOOTLDR */ +.set BOOTLDR__0__INTTYPE, CYREG_PICU0_INTTYPE0 +.set BOOTLDR__0__MASK, 0x01 +.set BOOTLDR__0__PC, CYREG_PRT0_PC0 +.set BOOTLDR__0__PORT, 0 +.set BOOTLDR__0__SHIFT, 0 +.set BOOTLDR__AG, CYREG_PRT0_AG +.set BOOTLDR__AMUX, CYREG_PRT0_AMUX +.set BOOTLDR__BIE, CYREG_PRT0_BIE +.set BOOTLDR__BIT_MASK, CYREG_PRT0_BIT_MASK +.set BOOTLDR__BYP, CYREG_PRT0_BYP +.set BOOTLDR__CTL, CYREG_PRT0_CTL +.set BOOTLDR__DM0, CYREG_PRT0_DM0 +.set BOOTLDR__DM1, CYREG_PRT0_DM1 +.set BOOTLDR__DM2, CYREG_PRT0_DM2 +.set BOOTLDR__DR, CYREG_PRT0_DR +.set BOOTLDR__INP_DIS, CYREG_PRT0_INP_DIS +.set BOOTLDR__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU0_BASE +.set BOOTLDR__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set BOOTLDR__LCD_EN, CYREG_PRT0_LCD_EN +.set BOOTLDR__MASK, 0x01 +.set BOOTLDR__PORT, 0 +.set BOOTLDR__PRT, CYREG_PRT0_PRT +.set BOOTLDR__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set BOOTLDR__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set BOOTLDR__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set BOOTLDR__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set BOOTLDR__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set BOOTLDR__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set BOOTLDR__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set BOOTLDR__PS, CYREG_PRT0_PS +.set BOOTLDR__SHIFT, 0 +.set BOOTLDR__SLW, CYREG_PRT0_SLW + +/* TERM_EN */ +.set TERM_EN__0__INTTYPE, CYREG_PICU15_INTTYPE3 +.set TERM_EN__0__MASK, 0x08 +.set TERM_EN__0__PC, CYREG_IO_PC_PRT15_PC3 +.set TERM_EN__0__PORT, 15 +.set TERM_EN__0__SHIFT, 3 +.set TERM_EN__AG, CYREG_PRT15_AG +.set TERM_EN__AMUX, CYREG_PRT15_AMUX +.set TERM_EN__BIE, CYREG_PRT15_BIE +.set TERM_EN__BIT_MASK, CYREG_PRT15_BIT_MASK +.set TERM_EN__BYP, CYREG_PRT15_BYP +.set TERM_EN__CTL, CYREG_PRT15_CTL +.set TERM_EN__DM0, CYREG_PRT15_DM0 +.set TERM_EN__DM1, CYREG_PRT15_DM1 +.set TERM_EN__DM2, CYREG_PRT15_DM2 +.set TERM_EN__DR, CYREG_PRT15_DR +.set TERM_EN__INP_DIS, CYREG_PRT15_INP_DIS +.set TERM_EN__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set TERM_EN__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set TERM_EN__LCD_EN, CYREG_PRT15_LCD_EN +.set TERM_EN__MASK, 0x08 +.set TERM_EN__PORT, 15 +.set TERM_EN__PRT, CYREG_PRT15_PRT +.set TERM_EN__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set TERM_EN__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set TERM_EN__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set TERM_EN__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set TERM_EN__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set TERM_EN__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set TERM_EN__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set TERM_EN__PS, CYREG_PRT15_PS +.set TERM_EN__SHIFT, 3 +.set TERM_EN__SLW, CYREG_PRT15_SLW + +/* SCSI_Out */ +.set SCSI_Out__0__AG, CYREG_PRT6_AG +.set SCSI_Out__0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__0__BIE, CYREG_PRT6_BIE +.set SCSI_Out__0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__0__BYP, CYREG_PRT6_BYP +.set SCSI_Out__0__CTL, CYREG_PRT6_CTL +.set SCSI_Out__0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__0__DR, CYREG_PRT6_DR +.set SCSI_Out__0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__0__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Out__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__0__MASK, 0x04 +.set SCSI_Out__0__PC, CYREG_PRT6_PC2 +.set SCSI_Out__0__PORT, 6 +.set SCSI_Out__0__PRT, CYREG_PRT6_PRT +.set SCSI_Out__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__0__PS, CYREG_PRT6_PS +.set SCSI_Out__0__SHIFT, 2 +.set SCSI_Out__0__SLW, CYREG_PRT6_SLW +.set SCSI_Out__1__AG, CYREG_PRT4_AG +.set SCSI_Out__1__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__1__BIE, CYREG_PRT4_BIE +.set SCSI_Out__1__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__1__BYP, CYREG_PRT4_BYP +.set SCSI_Out__1__CTL, CYREG_PRT4_CTL +.set SCSI_Out__1__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__1__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__1__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__1__DR, CYREG_PRT4_DR +.set SCSI_Out__1__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__1__INTTYPE, CYREG_PICU4_INTTYPE6 +.set SCSI_Out__1__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__1__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__1__MASK, 0x40 +.set SCSI_Out__1__PC, CYREG_PRT4_PC6 +.set SCSI_Out__1__PORT, 4 +.set SCSI_Out__1__PRT, CYREG_PRT4_PRT +.set SCSI_Out__1__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__1__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__1__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__1__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__1__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__1__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__1__PS, CYREG_PRT4_PS +.set SCSI_Out__1__SHIFT, 6 +.set SCSI_Out__1__SLW, CYREG_PRT4_SLW +.set SCSI_Out__2__AG, CYREG_PRT0_AG +.set SCSI_Out__2__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__2__BIE, CYREG_PRT0_BIE +.set SCSI_Out__2__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__2__BYP, CYREG_PRT0_BYP +.set SCSI_Out__2__CTL, CYREG_PRT0_CTL +.set SCSI_Out__2__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__2__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__2__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__2__DR, CYREG_PRT0_DR +.set SCSI_Out__2__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__2__INTTYPE, CYREG_PICU0_INTTYPE7 +.set SCSI_Out__2__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__2__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__2__MASK, 0x80 +.set SCSI_Out__2__PC, CYREG_PRT0_PC7 +.set SCSI_Out__2__PORT, 0 +.set SCSI_Out__2__PRT, CYREG_PRT0_PRT +.set SCSI_Out__2__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__2__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__2__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__2__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__2__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__2__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__2__PS, CYREG_PRT0_PS +.set SCSI_Out__2__SHIFT, 7 +.set SCSI_Out__2__SLW, CYREG_PRT0_SLW +.set SCSI_Out__3__AG, CYREG_PRT0_AG +.set SCSI_Out__3__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__3__BIE, CYREG_PRT0_BIE +.set SCSI_Out__3__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__3__BYP, CYREG_PRT0_BYP +.set SCSI_Out__3__CTL, CYREG_PRT0_CTL +.set SCSI_Out__3__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__3__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__3__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__3__DR, CYREG_PRT0_DR +.set SCSI_Out__3__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__3__INTTYPE, CYREG_PICU0_INTTYPE5 +.set SCSI_Out__3__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__3__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__3__MASK, 0x20 +.set SCSI_Out__3__PC, CYREG_PRT0_PC5 +.set SCSI_Out__3__PORT, 0 +.set SCSI_Out__3__PRT, CYREG_PRT0_PRT +.set SCSI_Out__3__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__3__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__3__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__3__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__3__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__3__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__3__PS, CYREG_PRT0_PS +.set SCSI_Out__3__SHIFT, 5 +.set SCSI_Out__3__SLW, CYREG_PRT0_SLW +.set SCSI_Out__4__AG, CYREG_PRT0_AG +.set SCSI_Out__4__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__4__BIE, CYREG_PRT0_BIE +.set SCSI_Out__4__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__4__BYP, CYREG_PRT0_BYP +.set SCSI_Out__4__CTL, CYREG_PRT0_CTL +.set SCSI_Out__4__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__4__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__4__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__4__DR, CYREG_PRT0_DR +.set SCSI_Out__4__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__4__INTTYPE, CYREG_PICU0_INTTYPE3 +.set SCSI_Out__4__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__4__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__4__MASK, 0x08 +.set SCSI_Out__4__PC, CYREG_PRT0_PC3 +.set SCSI_Out__4__PORT, 0 +.set SCSI_Out__4__PRT, CYREG_PRT0_PRT +.set SCSI_Out__4__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__4__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__4__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__4__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__4__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__4__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__4__PS, CYREG_PRT0_PS +.set SCSI_Out__4__SHIFT, 3 +.set SCSI_Out__4__SLW, CYREG_PRT0_SLW +.set SCSI_Out__5__AG, CYREG_PRT0_AG +.set SCSI_Out__5__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__5__BIE, CYREG_PRT0_BIE +.set SCSI_Out__5__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__5__BYP, CYREG_PRT0_BYP +.set SCSI_Out__5__CTL, CYREG_PRT0_CTL +.set SCSI_Out__5__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__5__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__5__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__5__DR, CYREG_PRT0_DR +.set SCSI_Out__5__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__5__INTTYPE, CYREG_PICU0_INTTYPE1 +.set SCSI_Out__5__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__5__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__5__MASK, 0x02 +.set SCSI_Out__5__PC, CYREG_PRT0_PC1 +.set SCSI_Out__5__PORT, 0 +.set SCSI_Out__5__PRT, CYREG_PRT0_PRT +.set SCSI_Out__5__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__5__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__5__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__5__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__5__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__5__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__5__PS, CYREG_PRT0_PS +.set SCSI_Out__5__SHIFT, 1 +.set SCSI_Out__5__SLW, CYREG_PRT0_SLW +.set SCSI_Out__6__AG, CYREG_PRT4_AG +.set SCSI_Out__6__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__6__BIE, CYREG_PRT4_BIE +.set SCSI_Out__6__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__6__BYP, CYREG_PRT4_BYP +.set SCSI_Out__6__CTL, CYREG_PRT4_CTL +.set SCSI_Out__6__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__6__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__6__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__6__DR, CYREG_PRT4_DR +.set SCSI_Out__6__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__6__INTTYPE, CYREG_PICU4_INTTYPE1 +.set SCSI_Out__6__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__6__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__6__MASK, 0x02 +.set SCSI_Out__6__PC, CYREG_PRT4_PC1 +.set SCSI_Out__6__PORT, 4 +.set SCSI_Out__6__PRT, CYREG_PRT4_PRT +.set SCSI_Out__6__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__6__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__6__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__6__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__6__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__6__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__6__PS, CYREG_PRT4_PS +.set SCSI_Out__6__SHIFT, 1 +.set SCSI_Out__6__SLW, CYREG_PRT4_SLW +.set SCSI_Out__7__AG, CYREG_PRT4_AG +.set SCSI_Out__7__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__7__BIE, CYREG_PRT4_BIE +.set SCSI_Out__7__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__7__BYP, CYREG_PRT4_BYP +.set SCSI_Out__7__CTL, CYREG_PRT4_CTL +.set SCSI_Out__7__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__7__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__7__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__7__DR, CYREG_PRT4_DR +.set SCSI_Out__7__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__7__INTTYPE, CYREG_PICU4_INTTYPE0 +.set SCSI_Out__7__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__7__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__7__MASK, 0x01 +.set SCSI_Out__7__PC, CYREG_PRT4_PC0 +.set SCSI_Out__7__PORT, 4 +.set SCSI_Out__7__PRT, CYREG_PRT4_PRT +.set SCSI_Out__7__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__7__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__7__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__7__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__7__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__7__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__7__PS, CYREG_PRT4_PS +.set SCSI_Out__7__SHIFT, 0 +.set SCSI_Out__7__SLW, CYREG_PRT4_SLW +.set SCSI_Out__BSY__AG, CYREG_PRT4_AG +.set SCSI_Out__BSY__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__BSY__BIE, CYREG_PRT4_BIE +.set SCSI_Out__BSY__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__BSY__BYP, CYREG_PRT4_BYP +.set SCSI_Out__BSY__CTL, CYREG_PRT4_CTL +.set SCSI_Out__BSY__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__BSY__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__BSY__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__BSY__DR, CYREG_PRT4_DR +.set SCSI_Out__BSY__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__BSY__INTTYPE, CYREG_PICU4_INTTYPE6 +.set SCSI_Out__BSY__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__BSY__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__BSY__MASK, 0x40 +.set SCSI_Out__BSY__PC, CYREG_PRT4_PC6 +.set SCSI_Out__BSY__PORT, 4 +.set SCSI_Out__BSY__PRT, CYREG_PRT4_PRT +.set SCSI_Out__BSY__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__BSY__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__BSY__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__BSY__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__BSY__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__BSY__PS, CYREG_PRT4_PS +.set SCSI_Out__BSY__SHIFT, 6 +.set SCSI_Out__BSY__SLW, CYREG_PRT4_SLW +.set SCSI_Out__CD__AG, CYREG_PRT0_AG +.set SCSI_Out__CD__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__CD__BIE, CYREG_PRT0_BIE +.set SCSI_Out__CD__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__CD__BYP, CYREG_PRT0_BYP +.set SCSI_Out__CD__CTL, CYREG_PRT0_CTL +.set SCSI_Out__CD__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__CD__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__CD__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__CD__DR, CYREG_PRT0_DR +.set SCSI_Out__CD__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__CD__INTTYPE, CYREG_PICU0_INTTYPE1 +.set SCSI_Out__CD__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__CD__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__CD__MASK, 0x02 +.set SCSI_Out__CD__PC, CYREG_PRT0_PC1 +.set SCSI_Out__CD__PORT, 0 +.set SCSI_Out__CD__PRT, CYREG_PRT0_PRT +.set SCSI_Out__CD__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__CD__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__CD__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__CD__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__CD__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__CD__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__CD__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__CD__PS, CYREG_PRT0_PS +.set SCSI_Out__CD__SHIFT, 1 +.set SCSI_Out__CD__SLW, CYREG_PRT0_SLW +.set SCSI_Out__DBP_raw__AG, CYREG_PRT6_AG +.set SCSI_Out__DBP_raw__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out__DBP_raw__BIE, CYREG_PRT6_BIE +.set SCSI_Out__DBP_raw__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out__DBP_raw__BYP, CYREG_PRT6_BYP +.set SCSI_Out__DBP_raw__CTL, CYREG_PRT6_CTL +.set SCSI_Out__DBP_raw__DM0, CYREG_PRT6_DM0 +.set SCSI_Out__DBP_raw__DM1, CYREG_PRT6_DM1 +.set SCSI_Out__DBP_raw__DM2, CYREG_PRT6_DM2 +.set SCSI_Out__DBP_raw__DR, CYREG_PRT6_DR +.set SCSI_Out__DBP_raw__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out__DBP_raw__INTTYPE, CYREG_PICU6_INTTYPE2 +.set SCSI_Out__DBP_raw__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out__DBP_raw__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out__DBP_raw__MASK, 0x04 +.set SCSI_Out__DBP_raw__PC, CYREG_PRT6_PC2 +.set SCSI_Out__DBP_raw__PORT, 6 +.set SCSI_Out__DBP_raw__PRT, CYREG_PRT6_PRT +.set SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out__DBP_raw__PS, CYREG_PRT6_PS +.set SCSI_Out__DBP_raw__SHIFT, 2 +.set SCSI_Out__DBP_raw__SLW, CYREG_PRT6_SLW +.set SCSI_Out__IO_raw__AG, CYREG_PRT4_AG +.set SCSI_Out__IO_raw__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__IO_raw__BIE, CYREG_PRT4_BIE +.set SCSI_Out__IO_raw__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__IO_raw__BYP, CYREG_PRT4_BYP +.set SCSI_Out__IO_raw__CTL, CYREG_PRT4_CTL +.set SCSI_Out__IO_raw__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__IO_raw__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__IO_raw__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__IO_raw__DR, CYREG_PRT4_DR +.set SCSI_Out__IO_raw__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__IO_raw__INTTYPE, CYREG_PICU4_INTTYPE0 +.set SCSI_Out__IO_raw__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__IO_raw__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__IO_raw__MASK, 0x01 +.set SCSI_Out__IO_raw__PC, CYREG_PRT4_PC0 +.set SCSI_Out__IO_raw__PORT, 4 +.set SCSI_Out__IO_raw__PRT, CYREG_PRT4_PRT +.set SCSI_Out__IO_raw__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__IO_raw__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__IO_raw__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__IO_raw__PS, CYREG_PRT4_PS +.set SCSI_Out__IO_raw__SHIFT, 0 +.set SCSI_Out__IO_raw__SLW, CYREG_PRT4_SLW +.set SCSI_Out__MSG__AG, CYREG_PRT0_AG +.set SCSI_Out__MSG__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__MSG__BIE, CYREG_PRT0_BIE +.set SCSI_Out__MSG__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__MSG__BYP, CYREG_PRT0_BYP +.set SCSI_Out__MSG__CTL, CYREG_PRT0_CTL +.set SCSI_Out__MSG__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__MSG__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__MSG__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__MSG__DR, CYREG_PRT0_DR +.set SCSI_Out__MSG__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__MSG__INTTYPE, CYREG_PICU0_INTTYPE5 +.set SCSI_Out__MSG__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__MSG__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__MSG__MASK, 0x20 +.set SCSI_Out__MSG__PC, CYREG_PRT0_PC5 +.set SCSI_Out__MSG__PORT, 0 +.set SCSI_Out__MSG__PRT, CYREG_PRT0_PRT +.set SCSI_Out__MSG__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__MSG__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__MSG__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__MSG__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__MSG__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__MSG__PS, CYREG_PRT0_PS +.set SCSI_Out__MSG__SHIFT, 5 +.set SCSI_Out__MSG__SLW, CYREG_PRT0_SLW +.set SCSI_Out__REQ__AG, CYREG_PRT4_AG +.set SCSI_Out__REQ__AMUX, CYREG_PRT4_AMUX +.set SCSI_Out__REQ__BIE, CYREG_PRT4_BIE +.set SCSI_Out__REQ__BIT_MASK, CYREG_PRT4_BIT_MASK +.set SCSI_Out__REQ__BYP, CYREG_PRT4_BYP +.set SCSI_Out__REQ__CTL, CYREG_PRT4_CTL +.set SCSI_Out__REQ__DM0, CYREG_PRT4_DM0 +.set SCSI_Out__REQ__DM1, CYREG_PRT4_DM1 +.set SCSI_Out__REQ__DM2, CYREG_PRT4_DM2 +.set SCSI_Out__REQ__DR, CYREG_PRT4_DR +.set SCSI_Out__REQ__INP_DIS, CYREG_PRT4_INP_DIS +.set SCSI_Out__REQ__INTTYPE, CYREG_PICU4_INTTYPE1 +.set SCSI_Out__REQ__LCD_COM_SEG, CYREG_PRT4_LCD_COM_SEG +.set SCSI_Out__REQ__LCD_EN, CYREG_PRT4_LCD_EN +.set SCSI_Out__REQ__MASK, 0x02 +.set SCSI_Out__REQ__PC, CYREG_PRT4_PC1 +.set SCSI_Out__REQ__PORT, 4 +.set SCSI_Out__REQ__PRT, CYREG_PRT4_PRT +.set SCSI_Out__REQ__PRTDSI__CAPS_SEL, CYREG_PRT4_CAPS_SEL +.set SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN, CYREG_PRT4_DBL_SYNC_IN +.set SCSI_Out__REQ__PRTDSI__OE_SEL0, CYREG_PRT4_OE_SEL0 +.set SCSI_Out__REQ__PRTDSI__OE_SEL1, CYREG_PRT4_OE_SEL1 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL0, CYREG_PRT4_OUT_SEL0 +.set SCSI_Out__REQ__PRTDSI__OUT_SEL1, CYREG_PRT4_OUT_SEL1 +.set SCSI_Out__REQ__PRTDSI__SYNC_OUT, CYREG_PRT4_SYNC_OUT +.set SCSI_Out__REQ__PS, CYREG_PRT4_PS +.set SCSI_Out__REQ__SHIFT, 1 +.set SCSI_Out__REQ__SLW, CYREG_PRT4_SLW +.set SCSI_Out__RST__AG, CYREG_PRT0_AG +.set SCSI_Out__RST__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__RST__BIE, CYREG_PRT0_BIE +.set SCSI_Out__RST__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__RST__BYP, CYREG_PRT0_BYP +.set SCSI_Out__RST__CTL, CYREG_PRT0_CTL +.set SCSI_Out__RST__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__RST__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__RST__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__RST__DR, CYREG_PRT0_DR +.set SCSI_Out__RST__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__RST__INTTYPE, CYREG_PICU0_INTTYPE7 +.set SCSI_Out__RST__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__RST__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__RST__MASK, 0x80 +.set SCSI_Out__RST__PC, CYREG_PRT0_PC7 +.set SCSI_Out__RST__PORT, 0 +.set SCSI_Out__RST__PRT, CYREG_PRT0_PRT +.set SCSI_Out__RST__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__RST__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__RST__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__RST__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__RST__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__RST__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__RST__PS, CYREG_PRT0_PS +.set SCSI_Out__RST__SHIFT, 7 +.set SCSI_Out__RST__SLW, CYREG_PRT0_SLW +.set SCSI_Out__SEL__AG, CYREG_PRT0_AG +.set SCSI_Out__SEL__AMUX, CYREG_PRT0_AMUX +.set SCSI_Out__SEL__BIE, CYREG_PRT0_BIE +.set SCSI_Out__SEL__BIT_MASK, CYREG_PRT0_BIT_MASK +.set SCSI_Out__SEL__BYP, CYREG_PRT0_BYP +.set SCSI_Out__SEL__CTL, CYREG_PRT0_CTL +.set SCSI_Out__SEL__DM0, CYREG_PRT0_DM0 +.set SCSI_Out__SEL__DM1, CYREG_PRT0_DM1 +.set SCSI_Out__SEL__DM2, CYREG_PRT0_DM2 +.set SCSI_Out__SEL__DR, CYREG_PRT0_DR +.set SCSI_Out__SEL__INP_DIS, CYREG_PRT0_INP_DIS +.set SCSI_Out__SEL__INTTYPE, CYREG_PICU0_INTTYPE3 +.set SCSI_Out__SEL__LCD_COM_SEG, CYREG_PRT0_LCD_COM_SEG +.set SCSI_Out__SEL__LCD_EN, CYREG_PRT0_LCD_EN +.set SCSI_Out__SEL__MASK, 0x08 +.set SCSI_Out__SEL__PC, CYREG_PRT0_PC3 +.set SCSI_Out__SEL__PORT, 0 +.set SCSI_Out__SEL__PRT, CYREG_PRT0_PRT +.set SCSI_Out__SEL__PRTDSI__CAPS_SEL, CYREG_PRT0_CAPS_SEL +.set SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN, CYREG_PRT0_DBL_SYNC_IN +.set SCSI_Out__SEL__PRTDSI__OE_SEL0, CYREG_PRT0_OE_SEL0 +.set SCSI_Out__SEL__PRTDSI__OE_SEL1, CYREG_PRT0_OE_SEL1 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL0, CYREG_PRT0_OUT_SEL0 +.set SCSI_Out__SEL__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1 +.set SCSI_Out__SEL__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT +.set SCSI_Out__SEL__PS, CYREG_PRT0_PS +.set SCSI_Out__SEL__SHIFT, 3 +.set SCSI_Out__SEL__SLW, CYREG_PRT0_SLW +.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__0__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__0__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__0__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__0__INTTYPE, CYREG_PICU6_INTTYPE7 +.set SCSI_Out_DBx__0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__0__MASK, 0x80 +.set SCSI_Out_DBx__0__PC, CYREG_PRT6_PC7 +.set SCSI_Out_DBx__0__PORT, 6 +.set SCSI_Out_DBx__0__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__0__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__0__SHIFT, 7 +.set SCSI_Out_DBx__0__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__1__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__1__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__1__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__1__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__1__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__1__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__1__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__1__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__1__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Out_DBx__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__1__MASK, 0x20 +.set SCSI_Out_DBx__1__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__1__PORT, 6 +.set SCSI_Out_DBx__1__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__1__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__1__SHIFT, 5 +.set SCSI_Out_DBx__1__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__2__AG, CYREG_PRT12_AG +.set SCSI_Out_DBx__2__BIE, CYREG_PRT12_BIE +.set SCSI_Out_DBx__2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Out_DBx__2__BYP, CYREG_PRT12_BYP +.set SCSI_Out_DBx__2__DM0, CYREG_PRT12_DM0 +.set SCSI_Out_DBx__2__DM1, CYREG_PRT12_DM1 +.set SCSI_Out_DBx__2__DM2, CYREG_PRT12_DM2 +.set SCSI_Out_DBx__2__DR, CYREG_PRT12_DR +.set SCSI_Out_DBx__2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Out_DBx__2__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Out_DBx__2__MASK, 0x20 +.set SCSI_Out_DBx__2__PC, CYREG_PRT12_PC5 +.set SCSI_Out_DBx__2__PORT, 12 +.set SCSI_Out_DBx__2__PRT, CYREG_PRT12_PRT +.set SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Out_DBx__2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Out_DBx__2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Out_DBx__2__PS, CYREG_PRT12_PS +.set SCSI_Out_DBx__2__SHIFT, 5 +.set SCSI_Out_DBx__2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Out_DBx__2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Out_DBx__2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Out_DBx__2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Out_DBx__2__SLW, CYREG_PRT12_SLW +.set SCSI_Out_DBx__3__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__3__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__3__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__3__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__3__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__3__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__3__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__3__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__3__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__3__INTTYPE, CYREG_PICU2_INTTYPE7 +.set SCSI_Out_DBx__3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__3__MASK, 0x80 +.set SCSI_Out_DBx__3__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__3__PORT, 2 +.set SCSI_Out_DBx__3__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__3__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__3__SHIFT, 7 +.set SCSI_Out_DBx__3__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__4__INTTYPE, CYREG_PICU2_INTTYPE5 +.set SCSI_Out_DBx__4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__4__MASK, 0x20 +.set SCSI_Out_DBx__4__PC, CYREG_PRT2_PC5 +.set SCSI_Out_DBx__4__PORT, 2 +.set SCSI_Out_DBx__4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__4__SHIFT, 5 +.set SCSI_Out_DBx__4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__5__INTTYPE, CYREG_PICU2_INTTYPE3 +.set SCSI_Out_DBx__5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__5__MASK, 0x08 +.set SCSI_Out_DBx__5__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__5__PORT, 2 +.set SCSI_Out_DBx__5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__5__SHIFT, 3 +.set SCSI_Out_DBx__5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__6__INTTYPE, CYREG_PICU2_INTTYPE1 +.set SCSI_Out_DBx__6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__6__MASK, 0x02 +.set SCSI_Out_DBx__6__PC, CYREG_PRT2_PC1 +.set SCSI_Out_DBx__6__PORT, 2 +.set SCSI_Out_DBx__6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__6__SHIFT, 1 +.set SCSI_Out_DBx__6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__7__AG, CYREG_PRT15_AG +.set SCSI_Out_DBx__7__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out_DBx__7__BIE, CYREG_PRT15_BIE +.set SCSI_Out_DBx__7__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out_DBx__7__BYP, CYREG_PRT15_BYP +.set SCSI_Out_DBx__7__CTL, CYREG_PRT15_CTL +.set SCSI_Out_DBx__7__DM0, CYREG_PRT15_DM0 +.set SCSI_Out_DBx__7__DM1, CYREG_PRT15_DM1 +.set SCSI_Out_DBx__7__DM2, CYREG_PRT15_DM2 +.set SCSI_Out_DBx__7__DR, CYREG_PRT15_DR +.set SCSI_Out_DBx__7__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out_DBx__7__INTTYPE, CYREG_PICU15_INTTYPE5 +.set SCSI_Out_DBx__7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out_DBx__7__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out_DBx__7__MASK, 0x20 +.set SCSI_Out_DBx__7__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out_DBx__7__PORT, 15 +.set SCSI_Out_DBx__7__PRT, CYREG_PRT15_PRT +.set SCSI_Out_DBx__7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out_DBx__7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out_DBx__7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out_DBx__7__PS, CYREG_PRT15_PS +.set SCSI_Out_DBx__7__SHIFT, 5 +.set SCSI_Out_DBx__7__SLW, CYREG_PRT15_SLW +.set SCSI_Out_DBx__DB0__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB0__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB0__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB0__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB0__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB0__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB0__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB0__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB0__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB0__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB0__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB0__INTTYPE, CYREG_PICU6_INTTYPE7 +.set SCSI_Out_DBx__DB0__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB0__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB0__MASK, 0x80 +.set SCSI_Out_DBx__DB0__PC, CYREG_PRT6_PC7 +.set SCSI_Out_DBx__DB0__PORT, 6 +.set SCSI_Out_DBx__DB0__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB0__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB0__SHIFT, 7 +.set SCSI_Out_DBx__DB0__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB1__AG, CYREG_PRT6_AG +.set SCSI_Out_DBx__DB1__AMUX, CYREG_PRT6_AMUX +.set SCSI_Out_DBx__DB1__BIE, CYREG_PRT6_BIE +.set SCSI_Out_DBx__DB1__BIT_MASK, CYREG_PRT6_BIT_MASK +.set SCSI_Out_DBx__DB1__BYP, CYREG_PRT6_BYP +.set SCSI_Out_DBx__DB1__CTL, CYREG_PRT6_CTL +.set SCSI_Out_DBx__DB1__DM0, CYREG_PRT6_DM0 +.set SCSI_Out_DBx__DB1__DM1, CYREG_PRT6_DM1 +.set SCSI_Out_DBx__DB1__DM2, CYREG_PRT6_DM2 +.set SCSI_Out_DBx__DB1__DR, CYREG_PRT6_DR +.set SCSI_Out_DBx__DB1__INP_DIS, CYREG_PRT6_INP_DIS +.set SCSI_Out_DBx__DB1__INTTYPE, CYREG_PICU6_INTTYPE5 +.set SCSI_Out_DBx__DB1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG +.set SCSI_Out_DBx__DB1__LCD_EN, CYREG_PRT6_LCD_EN +.set SCSI_Out_DBx__DB1__MASK, 0x20 +.set SCSI_Out_DBx__DB1__PC, CYREG_PRT6_PC5 +.set SCSI_Out_DBx__DB1__PORT, 6 +.set SCSI_Out_DBx__DB1__PRT, CYREG_PRT6_PRT +.set SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL +.set SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0 +.set SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1 +.set SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT +.set SCSI_Out_DBx__DB1__PS, CYREG_PRT6_PS +.set SCSI_Out_DBx__DB1__SHIFT, 5 +.set SCSI_Out_DBx__DB1__SLW, CYREG_PRT6_SLW +.set SCSI_Out_DBx__DB2__AG, CYREG_PRT12_AG +.set SCSI_Out_DBx__DB2__BIE, CYREG_PRT12_BIE +.set SCSI_Out_DBx__DB2__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SCSI_Out_DBx__DB2__BYP, CYREG_PRT12_BYP +.set SCSI_Out_DBx__DB2__DM0, CYREG_PRT12_DM0 +.set SCSI_Out_DBx__DB2__DM1, CYREG_PRT12_DM1 +.set SCSI_Out_DBx__DB2__DM2, CYREG_PRT12_DM2 +.set SCSI_Out_DBx__DB2__DR, CYREG_PRT12_DR +.set SCSI_Out_DBx__DB2__INP_DIS, CYREG_PRT12_INP_DIS +.set SCSI_Out_DBx__DB2__INTTYPE, CYREG_PICU12_INTTYPE5 +.set SCSI_Out_DBx__DB2__MASK, 0x20 +.set SCSI_Out_DBx__DB2__PC, CYREG_PRT12_PC5 +.set SCSI_Out_DBx__DB2__PORT, 12 +.set SCSI_Out_DBx__DB2__PRT, CYREG_PRT12_PRT +.set SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SCSI_Out_DBx__DB2__PS, CYREG_PRT12_PS +.set SCSI_Out_DBx__DB2__SHIFT, 5 +.set SCSI_Out_DBx__DB2__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SCSI_Out_DBx__DB2__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SCSI_Out_DBx__DB2__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SCSI_Out_DBx__DB2__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SCSI_Out_DBx__DB2__SLW, CYREG_PRT12_SLW +.set SCSI_Out_DBx__DB3__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB3__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB3__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB3__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB3__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB3__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB3__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB3__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB3__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB3__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB3__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB3__INTTYPE, CYREG_PICU2_INTTYPE7 +.set SCSI_Out_DBx__DB3__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB3__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB3__MASK, 0x80 +.set SCSI_Out_DBx__DB3__PC, CYREG_PRT2_PC7 +.set SCSI_Out_DBx__DB3__PORT, 2 +.set SCSI_Out_DBx__DB3__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB3__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB3__SHIFT, 7 +.set SCSI_Out_DBx__DB3__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB4__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB4__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB4__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB4__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB4__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB4__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB4__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB4__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB4__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB4__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB4__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB4__INTTYPE, CYREG_PICU2_INTTYPE5 +.set SCSI_Out_DBx__DB4__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB4__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB4__MASK, 0x20 +.set SCSI_Out_DBx__DB4__PC, CYREG_PRT2_PC5 +.set SCSI_Out_DBx__DB4__PORT, 2 +.set SCSI_Out_DBx__DB4__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB4__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB4__SHIFT, 5 +.set SCSI_Out_DBx__DB4__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB5__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB5__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB5__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB5__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB5__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB5__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB5__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB5__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB5__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB5__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB5__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB5__INTTYPE, CYREG_PICU2_INTTYPE3 +.set SCSI_Out_DBx__DB5__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB5__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB5__MASK, 0x08 +.set SCSI_Out_DBx__DB5__PC, CYREG_PRT2_PC3 +.set SCSI_Out_DBx__DB5__PORT, 2 +.set SCSI_Out_DBx__DB5__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB5__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB5__SHIFT, 3 +.set SCSI_Out_DBx__DB5__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB6__AG, CYREG_PRT2_AG +.set SCSI_Out_DBx__DB6__AMUX, CYREG_PRT2_AMUX +.set SCSI_Out_DBx__DB6__BIE, CYREG_PRT2_BIE +.set SCSI_Out_DBx__DB6__BIT_MASK, CYREG_PRT2_BIT_MASK +.set SCSI_Out_DBx__DB6__BYP, CYREG_PRT2_BYP +.set SCSI_Out_DBx__DB6__CTL, CYREG_PRT2_CTL +.set SCSI_Out_DBx__DB6__DM0, CYREG_PRT2_DM0 +.set SCSI_Out_DBx__DB6__DM1, CYREG_PRT2_DM1 +.set SCSI_Out_DBx__DB6__DM2, CYREG_PRT2_DM2 +.set SCSI_Out_DBx__DB6__DR, CYREG_PRT2_DR +.set SCSI_Out_DBx__DB6__INP_DIS, CYREG_PRT2_INP_DIS +.set SCSI_Out_DBx__DB6__INTTYPE, CYREG_PICU2_INTTYPE1 +.set SCSI_Out_DBx__DB6__LCD_COM_SEG, CYREG_PRT2_LCD_COM_SEG +.set SCSI_Out_DBx__DB6__LCD_EN, CYREG_PRT2_LCD_EN +.set SCSI_Out_DBx__DB6__MASK, 0x02 +.set SCSI_Out_DBx__DB6__PC, CYREG_PRT2_PC1 +.set SCSI_Out_DBx__DB6__PORT, 2 +.set SCSI_Out_DBx__DB6__PRT, CYREG_PRT2_PRT +.set SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL, CYREG_PRT2_CAPS_SEL +.set SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN, CYREG_PRT2_DBL_SYNC_IN +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0, CYREG_PRT2_OE_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1, CYREG_PRT2_OE_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0, CYREG_PRT2_OUT_SEL0 +.set SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1 +.set SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT +.set SCSI_Out_DBx__DB6__PS, CYREG_PRT2_PS +.set SCSI_Out_DBx__DB6__SHIFT, 1 +.set SCSI_Out_DBx__DB6__SLW, CYREG_PRT2_SLW +.set SCSI_Out_DBx__DB7__AG, CYREG_PRT15_AG +.set SCSI_Out_DBx__DB7__AMUX, CYREG_PRT15_AMUX +.set SCSI_Out_DBx__DB7__BIE, CYREG_PRT15_BIE +.set SCSI_Out_DBx__DB7__BIT_MASK, CYREG_PRT15_BIT_MASK +.set SCSI_Out_DBx__DB7__BYP, CYREG_PRT15_BYP +.set SCSI_Out_DBx__DB7__CTL, CYREG_PRT15_CTL +.set SCSI_Out_DBx__DB7__DM0, CYREG_PRT15_DM0 +.set SCSI_Out_DBx__DB7__DM1, CYREG_PRT15_DM1 +.set SCSI_Out_DBx__DB7__DM2, CYREG_PRT15_DM2 +.set SCSI_Out_DBx__DB7__DR, CYREG_PRT15_DR +.set SCSI_Out_DBx__DB7__INP_DIS, CYREG_PRT15_INP_DIS +.set SCSI_Out_DBx__DB7__INTTYPE, CYREG_PICU15_INTTYPE5 +.set SCSI_Out_DBx__DB7__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set SCSI_Out_DBx__DB7__LCD_EN, CYREG_PRT15_LCD_EN +.set SCSI_Out_DBx__DB7__MASK, 0x20 +.set SCSI_Out_DBx__DB7__PC, CYREG_IO_PC_PRT15_PC5 +.set SCSI_Out_DBx__DB7__PORT, 15 +.set SCSI_Out_DBx__DB7__PRT, CYREG_PRT15_PRT +.set SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set SCSI_Out_DBx__DB7__PS, CYREG_PRT15_PS +.set SCSI_Out_DBx__DB7__SHIFT, 5 +.set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW + +/* SD_PULLUP */ +.set SD_PULLUP__0__INTTYPE, CYREG_PICU3_INTTYPE0 +.set SD_PULLUP__0__MASK, 0x01 +.set SD_PULLUP__0__PC, CYREG_PRT3_PC0 +.set SD_PULLUP__0__PORT, 3 +.set SD_PULLUP__0__SHIFT, 0 +.set SD_PULLUP__1__INTTYPE, CYREG_PICU3_INTTYPE1 +.set SD_PULLUP__1__MASK, 0x02 +.set SD_PULLUP__1__PC, CYREG_PRT3_PC1 +.set SD_PULLUP__1__PORT, 3 +.set SD_PULLUP__1__SHIFT, 1 +.set SD_PULLUP__2__INTTYPE, CYREG_PICU3_INTTYPE2 +.set SD_PULLUP__2__MASK, 0x04 +.set SD_PULLUP__2__PC, CYREG_PRT3_PC2 +.set SD_PULLUP__2__PORT, 3 +.set SD_PULLUP__2__SHIFT, 2 +.set SD_PULLUP__3__INTTYPE, CYREG_PICU3_INTTYPE3 +.set SD_PULLUP__3__MASK, 0x08 +.set SD_PULLUP__3__PC, CYREG_PRT3_PC3 +.set SD_PULLUP__3__PORT, 3 +.set SD_PULLUP__3__SHIFT, 3 +.set SD_PULLUP__AG, CYREG_PRT3_AG +.set SD_PULLUP__AMUX, CYREG_PRT3_AMUX +.set SD_PULLUP__BIE, CYREG_PRT3_BIE +.set SD_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SD_PULLUP__BYP, CYREG_PRT3_BYP +.set SD_PULLUP__CTL, CYREG_PRT3_CTL +.set SD_PULLUP__DM0, CYREG_PRT3_DM0 +.set SD_PULLUP__DM1, CYREG_PRT3_DM1 +.set SD_PULLUP__DM2, CYREG_PRT3_DM2 +.set SD_PULLUP__DR, CYREG_PRT3_DR +.set SD_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS +.set SD_PULLUP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SD_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SD_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN +.set SD_PULLUP__MASK, 0x0F +.set SD_PULLUP__PORT, 3 +.set SD_PULLUP__PRT, CYREG_PRT3_PRT +.set SD_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SD_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SD_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SD_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SD_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SD_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SD_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SD_PULLUP__PS, CYREG_PRT3_PS +.set SD_PULLUP__SHIFT, 0 +.set SD_PULLUP__SLW, CYREG_PRT3_SLW + +/* SPI_PULLUP */ +.set SPI_PULLUP__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set SPI_PULLUP__0__MASK, 0x10 +.set SPI_PULLUP__0__PC, CYREG_PRT3_PC4 +.set SPI_PULLUP__0__PORT, 3 +.set SPI_PULLUP__0__SHIFT, 4 +.set SPI_PULLUP__1__INTTYPE, CYREG_PICU3_INTTYPE5 +.set SPI_PULLUP__1__MASK, 0x20 +.set SPI_PULLUP__1__PC, CYREG_PRT3_PC5 +.set SPI_PULLUP__1__PORT, 3 +.set SPI_PULLUP__1__SHIFT, 5 +.set SPI_PULLUP__2__INTTYPE, CYREG_PICU3_INTTYPE6 +.set SPI_PULLUP__2__MASK, 0x40 +.set SPI_PULLUP__2__PC, CYREG_PRT3_PC6 +.set SPI_PULLUP__2__PORT, 3 +.set SPI_PULLUP__2__SHIFT, 6 +.set SPI_PULLUP__3__INTTYPE, CYREG_PICU3_INTTYPE7 +.set SPI_PULLUP__3__MASK, 0x80 +.set SPI_PULLUP__3__PC, CYREG_PRT3_PC7 +.set SPI_PULLUP__3__PORT, 3 +.set SPI_PULLUP__3__SHIFT, 7 +.set SPI_PULLUP__AG, CYREG_PRT3_AG +.set SPI_PULLUP__AMUX, CYREG_PRT3_AMUX +.set SPI_PULLUP__BIE, CYREG_PRT3_BIE +.set SPI_PULLUP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set SPI_PULLUP__BYP, CYREG_PRT3_BYP +.set SPI_PULLUP__CTL, CYREG_PRT3_CTL +.set SPI_PULLUP__DM0, CYREG_PRT3_DM0 +.set SPI_PULLUP__DM1, CYREG_PRT3_DM1 +.set SPI_PULLUP__DM2, CYREG_PRT3_DM2 +.set SPI_PULLUP__DR, CYREG_PRT3_DR +.set SPI_PULLUP__INP_DIS, CYREG_PRT3_INP_DIS +.set SPI_PULLUP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set SPI_PULLUP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set SPI_PULLUP__LCD_EN, CYREG_PRT3_LCD_EN +.set SPI_PULLUP__MASK, 0xF0 +.set SPI_PULLUP__PORT, 3 +.set SPI_PULLUP__PRT, CYREG_PRT3_PRT +.set SPI_PULLUP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set SPI_PULLUP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set SPI_PULLUP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set SPI_PULLUP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set SPI_PULLUP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set SPI_PULLUP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set SPI_PULLUP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set SPI_PULLUP__PS, CYREG_PRT3_PS +.set SPI_PULLUP__SHIFT, 4 +.set SPI_PULLUP__SLW, CYREG_PRT3_SLW +.set SPI_PULLUP_1__0__INTTYPE, CYREG_PICU12_INTTYPE0 +.set SPI_PULLUP_1__0__MASK, 0x01 +.set SPI_PULLUP_1__0__PC, CYREG_PRT12_PC0 +.set SPI_PULLUP_1__0__PORT, 12 +.set SPI_PULLUP_1__0__SHIFT, 0 +.set SPI_PULLUP_1__1__INTTYPE, CYREG_PICU12_INTTYPE1 +.set SPI_PULLUP_1__1__MASK, 0x02 +.set SPI_PULLUP_1__1__PC, CYREG_PRT12_PC1 +.set SPI_PULLUP_1__1__PORT, 12 +.set SPI_PULLUP_1__1__SHIFT, 1 +.set SPI_PULLUP_1__AG, CYREG_PRT12_AG +.set SPI_PULLUP_1__BIE, CYREG_PRT12_BIE +.set SPI_PULLUP_1__BIT_MASK, CYREG_PRT12_BIT_MASK +.set SPI_PULLUP_1__BYP, CYREG_PRT12_BYP +.set SPI_PULLUP_1__DM0, CYREG_PRT12_DM0 +.set SPI_PULLUP_1__DM1, CYREG_PRT12_DM1 +.set SPI_PULLUP_1__DM2, CYREG_PRT12_DM2 +.set SPI_PULLUP_1__DR, CYREG_PRT12_DR +.set SPI_PULLUP_1__INP_DIS, CYREG_PRT12_INP_DIS +.set SPI_PULLUP_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE +.set SPI_PULLUP_1__MASK, 0x03 +.set SPI_PULLUP_1__PORT, 12 +.set SPI_PULLUP_1__PRT, CYREG_PRT12_PRT +.set SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set SPI_PULLUP_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set SPI_PULLUP_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set SPI_PULLUP_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set SPI_PULLUP_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set SPI_PULLUP_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set SPI_PULLUP_1__PS, CYREG_PRT12_PS +.set SPI_PULLUP_1__SHIFT, 0 +.set SPI_PULLUP_1__SIO_CFG, CYREG_PRT12_SIO_CFG +.set SPI_PULLUP_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set SPI_PULLUP_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set SPI_PULLUP_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set SPI_PULLUP_1__SLW, CYREG_PRT12_SLW + +/* Miscellaneous */ +.set BCLK__BUS_CLK__HZ, 64000000 +.set BCLK__BUS_CLK__KHZ, 64000 +.set BCLK__BUS_CLK__MHZ, 64 +.set CYDEV_BOOTLOADER_APPLICATIONS, 1 +.set CYDEV_BOOTLOADER_CHECKSUM_BASIC, 0 +.set CYDEV_BOOTLOADER_CHECKSUM_CRC, 1 +.set CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO, 0 +.set CyBtldr_Custom_Interface, CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +.set CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY, 1 +.set CyBtldr_LAUNCHER_ONLY, CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY +.set CYDEV_BOOTLOADER_IO_COMP_USBFS, 2 +.set CyBtldr_USBFS, CYDEV_BOOTLOADER_IO_COMP_USBFS +.set CYDEV_BOOTLOADER_IO_COMP, CYDEV_BOOTLOADER_IO_COMP_USBFS +.set CYDEV_CHIP_DIE_LEOPARD, 1 +.set CYDEV_CHIP_DIE_PSOC4A, 18 +.set CYDEV_CHIP_DIE_PSOC5LP, 2 +.set CYDEV_CHIP_DIE_PSOC5TM, 3 +.set CYDEV_CHIP_DIE_TMA4, 4 +.set CYDEV_CHIP_DIE_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_FM0P, 5 +.set CYDEV_CHIP_FAMILY_FM3, 6 +.set CYDEV_CHIP_FAMILY_FM4, 7 +.set CYDEV_CHIP_FAMILY_PSOC3, 1 +.set CYDEV_CHIP_FAMILY_PSOC4, 2 +.set CYDEV_CHIP_FAMILY_PSOC5, 3 +.set CYDEV_CHIP_FAMILY_PSOC6, 4 +.set CYDEV_CHIP_FAMILY_UNKNOWN, 0 +.set CYDEV_CHIP_FAMILY_USED, CYDEV_CHIP_FAMILY_PSOC5 +.set CYDEV_CHIP_JTAG_ID, 0x2E133069 +.set CYDEV_CHIP_MEMBER_3A, 1 +.set CYDEV_CHIP_MEMBER_4A, 18 +.set CYDEV_CHIP_MEMBER_4D, 13 +.set CYDEV_CHIP_MEMBER_4E, 6 +.set CYDEV_CHIP_MEMBER_4F, 19 +.set CYDEV_CHIP_MEMBER_4G, 4 +.set CYDEV_CHIP_MEMBER_4H, 17 +.set CYDEV_CHIP_MEMBER_4I, 23 +.set CYDEV_CHIP_MEMBER_4J, 14 +.set CYDEV_CHIP_MEMBER_4K, 15 +.set CYDEV_CHIP_MEMBER_4L, 22 +.set CYDEV_CHIP_MEMBER_4M, 21 +.set CYDEV_CHIP_MEMBER_4N, 10 +.set CYDEV_CHIP_MEMBER_4O, 7 +.set CYDEV_CHIP_MEMBER_4P, 20 +.set CYDEV_CHIP_MEMBER_4Q, 12 +.set CYDEV_CHIP_MEMBER_4R, 8 +.set CYDEV_CHIP_MEMBER_4S, 11 +.set CYDEV_CHIP_MEMBER_4T, 9 +.set CYDEV_CHIP_MEMBER_4U, 5 +.set CYDEV_CHIP_MEMBER_4V, 16 +.set CYDEV_CHIP_MEMBER_5A, 3 +.set CYDEV_CHIP_MEMBER_5B, 2 +.set CYDEV_CHIP_MEMBER_6A, 24 +.set CYDEV_CHIP_MEMBER_FM3, 28 +.set CYDEV_CHIP_MEMBER_FM4, 29 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1, 25 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2, 26 +.set CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3, 27 +.set CYDEV_CHIP_MEMBER_UNKNOWN, 0 +.set CYDEV_CHIP_MEMBER_USED, CYDEV_CHIP_MEMBER_5B +.set CYDEV_CHIP_DIE_EXPECT, CYDEV_CHIP_MEMBER_USED +.set CYDEV_CHIP_DIE_ACTUAL, CYDEV_CHIP_DIE_EXPECT +.set CYDEV_CHIP_REV_LEOPARD_ES1, 0 +.set CYDEV_CHIP_REV_LEOPARD_ES2, 1 +.set CYDEV_CHIP_REV_LEOPARD_ES3, 3 +.set CYDEV_CHIP_REV_LEOPARD_PRODUCTION, 3 +.set CYDEV_CHIP_REV_PSOC4A_ES0, 17 +.set CYDEV_CHIP_REV_PSOC4A_PRODUCTION, 17 +.set CYDEV_CHIP_REV_PSOC5LP_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5LP_PRODUCTION, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES0, 0 +.set CYDEV_CHIP_REV_PSOC5TM_ES1, 1 +.set CYDEV_CHIP_REV_PSOC5TM_PRODUCTION, 1 +.set CYDEV_CHIP_REV_TMA4_ES, 17 +.set CYDEV_CHIP_REV_TMA4_ES2, 33 +.set CYDEV_CHIP_REV_TMA4_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_3A_ES1, 0 +.set CYDEV_CHIP_REVISION_3A_ES2, 1 +.set CYDEV_CHIP_REVISION_3A_ES3, 3 +.set CYDEV_CHIP_REVISION_3A_PRODUCTION, 3 +.set CYDEV_CHIP_REVISION_4A_ES0, 17 +.set CYDEV_CHIP_REVISION_4A_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4D_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD, 0 +.set CYDEV_CHIP_REVISION_4E_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA, 0 +.set CYDEV_CHIP_REVISION_4F_PRODUCTION_256K, 0 +.set CYDEV_CHIP_REVISION_4G_ES, 17 +.set CYDEV_CHIP_REVISION_4G_ES2, 33 +.set CYDEV_CHIP_REVISION_4G_PRODUCTION, 17 +.set CYDEV_CHIP_REVISION_4H_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4I_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4J_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4K_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4L_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4M_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4N_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4O_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4P_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4Q_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4R_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4S_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4T_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4U_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_4V_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_5A_ES0, 0 +.set CYDEV_CHIP_REVISION_5A_ES1, 1 +.set CYDEV_CHIP_REVISION_5A_PRODUCTION, 1 +.set CYDEV_CHIP_REVISION_5B_ES0, 0 +.set CYDEV_CHIP_REVISION_5B_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_6A_ES, 17 +.set CYDEV_CHIP_REVISION_6A_NO_UDB, 33 +.set CYDEV_CHIP_REVISION_6A_PRODUCTION, 33 +.set CYDEV_CHIP_REVISION_FM3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_FM4_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION, 0 +.set CYDEV_CHIP_REVISION_USED, CYDEV_CHIP_REVISION_5B_PRODUCTION +.set CYDEV_CHIP_REV_EXPECT, CYDEV_CHIP_REVISION_USED +.set CYDEV_CONFIG_FASTBOOT_ENABLED, 1 +.set CYDEV_CONFIG_UNUSED_IO_AllowButWarn, 0 +.set CYDEV_CONFIG_UNUSED_IO, CYDEV_CONFIG_UNUSED_IO_AllowButWarn +.set CYDEV_CONFIG_UNUSED_IO_AllowWithInfo, 1 +.set CYDEV_CONFIG_UNUSED_IO_Disallowed, 2 +.set CYDEV_CONFIGURATION_COMPRESSED, 1 +.set CYDEV_CONFIGURATION_DMA, 0 +.set CYDEV_CONFIGURATION_ECC, 1 +.set CYDEV_CONFIGURATION_IMOENABLED, CYDEV_CONFIG_FASTBOOT_ENABLED +.set CYDEV_CONFIGURATION_MODE_COMPRESSED, 0 +.set CYDEV_CONFIGURATION_MODE, CYDEV_CONFIGURATION_MODE_COMPRESSED +.set CYDEV_CONFIGURATION_MODE_DMA, 2 +.set CYDEV_CONFIGURATION_MODE_UNCOMPRESSED, 1 +.set CYDEV_DEBUG_ENABLE_MASK, 0x20 +.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG +.set CYDEV_DEBUGGING_DPS_Disable, 3 +.set CYDEV_DEBUGGING_DPS_JTAG_4, 1 +.set CYDEV_DEBUGGING_DPS_JTAG_5, 0 +.set CYDEV_DEBUGGING_DPS_SWD, 2 +.set CYDEV_DEBUGGING_DPS_SWD_SWV, 6 +.set CYDEV_DEBUGGING_DPS, CYDEV_DEBUGGING_DPS_SWD_SWV +.set CYDEV_DEBUGGING_ENABLE, 1 +.set CYDEV_DEBUGGING_XRES, 0 +.set CYDEV_DMA_CHANNELS_AVAILABLE, 24 +.set CYDEV_ECC_ENABLE, 0 +.set CYDEV_HEAP_SIZE, 0x0800 +.set CYDEV_INSTRUCT_CACHE_ENABLED, 1 +.set CYDEV_INTR_RISING, 0x00000000 +.set CYDEV_IS_EXPORTING_CODE, 0 +.set CYDEV_IS_IMPORTING_CODE, 0 +.set CYDEV_PROJ_TYPE, 1 +.set CYDEV_PROJ_TYPE_BOOTLOADER, 1 +.set CYDEV_PROJ_TYPE_LAUNCHER, 5 +.set CYDEV_PROJ_TYPE_LOADABLE, 2 +.set CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER, 4 +.set CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER, 3 +.set CYDEV_PROJ_TYPE_STANDARD, 0 +.set CYDEV_PROTECTION_ENABLE, 0 +.set CYDEV_STACK_SIZE, 0x2000 +.set CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP, 1 +.set CYDEV_USE_BUNDLED_CMSIS, 1 +.set CYDEV_VARIABLE_VDDA, 0 +.set CYDEV_VDDA_MV, 5000 +.set CYDEV_VDDD_MV, 5000 +.set CYDEV_VDDIO0_MV, 5000 +.set CYDEV_VDDIO1_MV, 5000 +.set CYDEV_VDDIO2_MV, 5000 +.set CYDEV_VDDIO3_MV, 3000 +.set CYDEV_VIO0_MV, 5000 +.set CYDEV_VIO1_MV, 5000 +.set CYDEV_VIO2_MV, 5000 +.set CYDEV_VIO3_MV, 3000 +.set CYIPBLOCK_ARM_CM3_VERSION, 0 +.set CYIPBLOCK_P3_ANAIF_VERSION, 0 +.set CYIPBLOCK_P3_CAPSENSE_VERSION, 0 +.set CYIPBLOCK_P3_COMP_VERSION, 0 +.set CYIPBLOCK_P3_DMA_VERSION, 0 +.set CYIPBLOCK_P3_DRQ_VERSION, 0 +.set CYIPBLOCK_P3_EMIF_VERSION, 0 +.set CYIPBLOCK_P3_I2C_VERSION, 0 +.set CYIPBLOCK_P3_LCD_VERSION, 0 +.set CYIPBLOCK_P3_LPF_VERSION, 0 +.set CYIPBLOCK_P3_PM_VERSION, 0 +.set CYIPBLOCK_P3_TIMER_VERSION, 0 +.set CYIPBLOCK_P3_USB_VERSION, 0 +.set CYIPBLOCK_P3_VIDAC_VERSION, 0 +.set CYIPBLOCK_P3_VREF_VERSION, 0 +.set CYIPBLOCK_S8_GPIO_VERSION, 0 +.set CYIPBLOCK_S8_IRQ_VERSION, 0 +.set CYIPBLOCK_S8_SAR_VERSION, 0 +.set CYIPBLOCK_S8_SIO_VERSION, 0 +.set CYIPBLOCK_S8_UDB_VERSION, 0 +.set DMA_CHANNELS_USED__MASK0, 0x00000000 +.set CYDEV_BOOTLOADER_ENABLE, 1 +.endif diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc new file mode 100644 index 0000000..4fb9f0a --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -0,0 +1,1602 @@ +; +; File Name: cyfitteriar.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + +#ifndef INCLUDED_CYFITTERIAR_INC +#define INCLUDED_CYFITTERIAR_INC + INCLUDE cydeviceiar.inc + INCLUDE cydeviceiar_trm.inc + +/* LED */ +LED__0__INTTYPE EQU CYREG_PICU12_INTTYPE2 +LED__0__MASK EQU 0x04 +LED__0__PC EQU CYREG_PRT12_PC2 +LED__0__PORT EQU 12 +LED__0__SHIFT EQU 2 +LED__1__INTTYPE EQU CYREG_PICU12_INTTYPE3 +LED__1__MASK EQU 0x08 +LED__1__PC EQU CYREG_PRT12_PC3 +LED__1__PORT EQU 12 +LED__1__SHIFT EQU 3 +LED__AG EQU CYREG_PRT12_AG +LED__BIE EQU CYREG_PRT12_BIE +LED__BIT_MASK EQU CYREG_PRT12_BIT_MASK +LED__BYP EQU CYREG_PRT12_BYP +LED__DM0 EQU CYREG_PRT12_DM0 +LED__DM1 EQU CYREG_PRT12_DM1 +LED__DM2 EQU CYREG_PRT12_DM2 +LED__DR EQU CYREG_PRT12_DR +LED__INP_DIS EQU CYREG_PRT12_INP_DIS +LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +LED__MASK EQU 0x0C +LED__PORT EQU 12 +LED__PRT EQU CYREG_PRT12_PRT +LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +LED__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +LED__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +LED__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +LED__PS EQU CYREG_PRT12_PS +LED__SHIFT EQU 2 +LED__SIO_CFG EQU CYREG_PRT12_SIO_CFG +LED__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +LED__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +LED__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +LED__SLW EQU CYREG_PRT12_SLW + +/* USBFS */ +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 + +/* BOOTLDR */ +BOOTLDR__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 +BOOTLDR__0__MASK EQU 0x01 +BOOTLDR__0__PC EQU CYREG_PRT0_PC0 +BOOTLDR__0__PORT EQU 0 +BOOTLDR__0__SHIFT EQU 0 +BOOTLDR__AG EQU CYREG_PRT0_AG +BOOTLDR__AMUX EQU CYREG_PRT0_AMUX +BOOTLDR__BIE EQU CYREG_PRT0_BIE +BOOTLDR__BIT_MASK EQU CYREG_PRT0_BIT_MASK +BOOTLDR__BYP EQU CYREG_PRT0_BYP +BOOTLDR__CTL EQU CYREG_PRT0_CTL +BOOTLDR__DM0 EQU CYREG_PRT0_DM0 +BOOTLDR__DM1 EQU CYREG_PRT0_DM1 +BOOTLDR__DM2 EQU CYREG_PRT0_DM2 +BOOTLDR__DR EQU CYREG_PRT0_DR +BOOTLDR__INP_DIS EQU CYREG_PRT0_INP_DIS +BOOTLDR__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +BOOTLDR__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +BOOTLDR__LCD_EN EQU CYREG_PRT0_LCD_EN +BOOTLDR__MASK EQU 0x01 +BOOTLDR__PORT EQU 0 +BOOTLDR__PRT EQU CYREG_PRT0_PRT +BOOTLDR__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +BOOTLDR__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +BOOTLDR__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +BOOTLDR__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +BOOTLDR__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +BOOTLDR__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +BOOTLDR__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +BOOTLDR__PS EQU CYREG_PRT0_PS +BOOTLDR__SHIFT EQU 0 +BOOTLDR__SLW EQU CYREG_PRT0_SLW + +/* TERM_EN */ +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +/* SCSI_Out */ +SCSI_Out__0__AG EQU CYREG_PRT6_AG +SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__0__DR EQU CYREG_PRT6_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__0__MASK EQU 0x04 +SCSI_Out__0__PC EQU CYREG_PRT6_PC2 +SCSI_Out__0__PORT EQU 6 +SCSI_Out__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT6_PS +SCSI_Out__0__SHIFT EQU 2 +SCSI_Out__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out__1__AG EQU CYREG_PRT4_AG +SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT4_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT4_BYP +SCSI_Out__1__CTL EQU CYREG_PRT4_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__1__DR EQU CYREG_PRT4_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__1__MASK EQU 0x40 +SCSI_Out__1__PC EQU CYREG_PRT4_PC6 +SCSI_Out__1__PORT EQU 4 +SCSI_Out__1__PRT EQU CYREG_PRT4_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT4_PS +SCSI_Out__1__SHIFT EQU 6 +SCSI_Out__1__SLW EQU CYREG_PRT4_SLW +SCSI_Out__2__AG EQU CYREG_PRT0_AG +SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT0_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT0_BYP +SCSI_Out__2__CTL EQU CYREG_PRT0_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__2__DR EQU CYREG_PRT0_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__2__MASK EQU 0x80 +SCSI_Out__2__PC EQU CYREG_PRT0_PC7 +SCSI_Out__2__PORT EQU 0 +SCSI_Out__2__PRT EQU CYREG_PRT0_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT0_PS +SCSI_Out__2__SHIFT EQU 7 +SCSI_Out__2__SLW EQU CYREG_PRT0_SLW +SCSI_Out__3__AG EQU CYREG_PRT0_AG +SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT0_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT0_BYP +SCSI_Out__3__CTL EQU CYREG_PRT0_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__3__DR EQU CYREG_PRT0_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__3__MASK EQU 0x20 +SCSI_Out__3__PC EQU CYREG_PRT0_PC5 +SCSI_Out__3__PORT EQU 0 +SCSI_Out__3__PRT EQU CYREG_PRT0_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT0_PS +SCSI_Out__3__SHIFT EQU 5 +SCSI_Out__3__SLW EQU CYREG_PRT0_SLW +SCSI_Out__4__AG EQU CYREG_PRT0_AG +SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT0_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT0_BYP +SCSI_Out__4__CTL EQU CYREG_PRT0_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__4__DR EQU CYREG_PRT0_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__4__MASK EQU 0x08 +SCSI_Out__4__PC EQU CYREG_PRT0_PC3 +SCSI_Out__4__PORT EQU 0 +SCSI_Out__4__PRT EQU CYREG_PRT0_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT0_PS +SCSI_Out__4__SHIFT EQU 3 +SCSI_Out__4__SLW EQU CYREG_PRT0_SLW +SCSI_Out__5__AG EQU CYREG_PRT0_AG +SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT0_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT0_BYP +SCSI_Out__5__CTL EQU CYREG_PRT0_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__5__DR EQU CYREG_PRT0_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__5__MASK EQU 0x02 +SCSI_Out__5__PC EQU CYREG_PRT0_PC1 +SCSI_Out__5__PORT EQU 0 +SCSI_Out__5__PRT EQU CYREG_PRT0_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT0_PS +SCSI_Out__5__SHIFT EQU 1 +SCSI_Out__5__SLW EQU CYREG_PRT0_SLW +SCSI_Out__6__AG EQU CYREG_PRT4_AG +SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT4_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT4_BYP +SCSI_Out__6__CTL EQU CYREG_PRT4_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__6__DR EQU CYREG_PRT4_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__6__MASK EQU 0x02 +SCSI_Out__6__PC EQU CYREG_PRT4_PC1 +SCSI_Out__6__PORT EQU 4 +SCSI_Out__6__PRT EQU CYREG_PRT4_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT4_PS +SCSI_Out__6__SHIFT EQU 1 +SCSI_Out__6__SLW EQU CYREG_PRT4_SLW +SCSI_Out__7__AG EQU CYREG_PRT4_AG +SCSI_Out__7__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT4_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT4_BYP +SCSI_Out__7__CTL EQU CYREG_PRT4_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__7__DR EQU CYREG_PRT4_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__7__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__7__MASK EQU 0x01 +SCSI_Out__7__PC EQU CYREG_PRT4_PC0 +SCSI_Out__7__PORT EQU 4 +SCSI_Out__7__PRT EQU CYREG_PRT4_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT4_PS +SCSI_Out__7__SHIFT EQU 0 +SCSI_Out__7__SLW EQU CYREG_PRT4_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT4_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT4_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__BSY__MASK EQU 0x40 +SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6 +SCSI_Out__BSY__PORT EQU 4 +SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT4_PS +SCSI_Out__BSY__SHIFT EQU 6 +SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x02 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC1 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 1 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x04 +SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2 +SCSI_Out__DBP_raw__PORT EQU 6 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS +SCSI_Out__DBP_raw__SHIFT EQU 2 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT4_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT4_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT4_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT4_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT4_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x01 +SCSI_Out__IO_raw__PC EQU CYREG_PRT4_PC0 +SCSI_Out__IO_raw__PORT EQU 4 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT4_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT4_PS +SCSI_Out__IO_raw__SHIFT EQU 0 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT4_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT0_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT0_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__MSG__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__MSG__MASK EQU 0x20 +SCSI_Out__MSG__PC EQU CYREG_PRT0_PC5 +SCSI_Out__MSG__PORT EQU 0 +SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT0_PS +SCSI_Out__MSG__SHIFT EQU 5 +SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT4_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT4_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__REQ__MASK EQU 0x02 +SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1 +SCSI_Out__REQ__PORT EQU 4 +SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT4_PS +SCSI_Out__REQ__SHIFT EQU 1 +SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW +SCSI_Out__RST__AG EQU CYREG_PRT0_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT0_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__RST__MASK EQU 0x80 +SCSI_Out__RST__PC EQU CYREG_PRT0_PC7 +SCSI_Out__RST__PORT EQU 0 +SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT0_PS +SCSI_Out__RST__SHIFT EQU 7 +SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x08 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 3 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW +SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x80 +SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__0__PORT EQU 6 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__0__SHIFT EQU 7 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x20 +SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__1__PORT EQU 6 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__1__SHIFT EQU 5 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__2__PORT EQU 12 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x80 +SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__3__PORT EQU 2 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__3__SHIFT EQU 7 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x20 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 5 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x08 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 3 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x02 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 1 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x20 +SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__7__PORT EQU 15 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__7__SHIFT EQU 5 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x80 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__DB0__PORT EQU 6 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB0__SHIFT EQU 7 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x20 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB1__PORT EQU 6 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB1__SHIFT EQU 5 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__DB2__PORT EQU 12 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x80 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB3__PORT EQU 2 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB3__SHIFT EQU 7 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x20 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 5 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x08 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 3 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x02 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 1 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x20 +SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__DB7__PORT EQU 15 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__DB7__SHIFT EQU 5 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW + +/* SD_PULLUP */ +SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_PULLUP__0__MASK EQU 0x01 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC0 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 0 +SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_PULLUP__1__MASK EQU 0x02 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 1 +SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_PULLUP__2__MASK EQU 0x04 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 2 +SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_PULLUP__3__MASK EQU 0x08 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 3 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x0F +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 0 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + +/* SPI_PULLUP */ +SPI_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SPI_PULLUP__0__MASK EQU 0x10 +SPI_PULLUP__0__PC EQU CYREG_PRT3_PC4 +SPI_PULLUP__0__PORT EQU 3 +SPI_PULLUP__0__SHIFT EQU 4 +SPI_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SPI_PULLUP__1__MASK EQU 0x20 +SPI_PULLUP__1__PC EQU CYREG_PRT3_PC5 +SPI_PULLUP__1__PORT EQU 3 +SPI_PULLUP__1__SHIFT EQU 5 +SPI_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SPI_PULLUP__2__MASK EQU 0x40 +SPI_PULLUP__2__PC EQU CYREG_PRT3_PC6 +SPI_PULLUP__2__PORT EQU 3 +SPI_PULLUP__2__SHIFT EQU 6 +SPI_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 +SPI_PULLUP__3__MASK EQU 0x80 +SPI_PULLUP__3__PC EQU CYREG_PRT3_PC7 +SPI_PULLUP__3__PORT EQU 3 +SPI_PULLUP__3__SHIFT EQU 7 +SPI_PULLUP__AG EQU CYREG_PRT3_AG +SPI_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SPI_PULLUP__BIE EQU CYREG_PRT3_BIE +SPI_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_PULLUP__BYP EQU CYREG_PRT3_BYP +SPI_PULLUP__CTL EQU CYREG_PRT3_CTL +SPI_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SPI_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SPI_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SPI_PULLUP__DR EQU CYREG_PRT3_DR +SPI_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_PULLUP__MASK EQU 0xF0 +SPI_PULLUP__PORT EQU 3 +SPI_PULLUP__PRT EQU CYREG_PRT3_PRT +SPI_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_PULLUP__PS EQU CYREG_PRT3_PS +SPI_PULLUP__SHIFT EQU 4 +SPI_PULLUP__SLW EQU CYREG_PRT3_SLW +SPI_PULLUP_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 +SPI_PULLUP_1__0__MASK EQU 0x01 +SPI_PULLUP_1__0__PC EQU CYREG_PRT12_PC0 +SPI_PULLUP_1__0__PORT EQU 12 +SPI_PULLUP_1__0__SHIFT EQU 0 +SPI_PULLUP_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 +SPI_PULLUP_1__1__MASK EQU 0x02 +SPI_PULLUP_1__1__PC EQU CYREG_PRT12_PC1 +SPI_PULLUP_1__1__PORT EQU 12 +SPI_PULLUP_1__1__SHIFT EQU 1 +SPI_PULLUP_1__AG EQU CYREG_PRT12_AG +SPI_PULLUP_1__BIE EQU CYREG_PRT12_BIE +SPI_PULLUP_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SPI_PULLUP_1__BYP EQU CYREG_PRT12_BYP +SPI_PULLUP_1__DM0 EQU CYREG_PRT12_DM0 +SPI_PULLUP_1__DM1 EQU CYREG_PRT12_DM1 +SPI_PULLUP_1__DM2 EQU CYREG_PRT12_DM2 +SPI_PULLUP_1__DR EQU CYREG_PRT12_DR +SPI_PULLUP_1__INP_DIS EQU CYREG_PRT12_INP_DIS +SPI_PULLUP_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SPI_PULLUP_1__MASK EQU 0x03 +SPI_PULLUP_1__PORT EQU 12 +SPI_PULLUP_1__PRT EQU CYREG_PRT12_PRT +SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SPI_PULLUP_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SPI_PULLUP_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SPI_PULLUP_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SPI_PULLUP_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SPI_PULLUP_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SPI_PULLUP_1__PS EQU CYREG_PRT12_PS +SPI_PULLUP_1__SHIFT EQU 0 +SPI_PULLUP_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SPI_PULLUP_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SPI_PULLUP_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SPI_PULLUP_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SPI_PULLUP_1__SLW EQU CYREG_PRT12_SLW + +/* Miscellaneous */ +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_BOOTLOADER_APPLICATIONS EQU 1 +CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 +CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 +CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 +CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY EQU 1 +CyBtldr_LAUNCHER_ONLY EQU CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY +CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 2 +CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 1 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0800 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 1 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x2000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3000 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3000 +CYIPBLOCK_ARM_CM3_VERSION EQU 0 +CYIPBLOCK_P3_ANAIF_VERSION EQU 0 +CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0 +CYIPBLOCK_P3_COMP_VERSION EQU 0 +CYIPBLOCK_P3_DMA_VERSION EQU 0 +CYIPBLOCK_P3_DRQ_VERSION EQU 0 +CYIPBLOCK_P3_EMIF_VERSION EQU 0 +CYIPBLOCK_P3_I2C_VERSION EQU 0 +CYIPBLOCK_P3_LCD_VERSION EQU 0 +CYIPBLOCK_P3_LPF_VERSION EQU 0 +CYIPBLOCK_P3_PM_VERSION EQU 0 +CYIPBLOCK_P3_TIMER_VERSION EQU 0 +CYIPBLOCK_P3_USB_VERSION EQU 0 +CYIPBLOCK_P3_VIDAC_VERSION EQU 0 +CYIPBLOCK_P3_VREF_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 0 +CYIPBLOCK_S8_IRQ_VERSION EQU 0 +CYIPBLOCK_S8_SAR_VERSION EQU 0 +CYIPBLOCK_S8_SIO_VERSION EQU 0 +CYIPBLOCK_S8_UDB_VERSION EQU 0 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 1 + +#endif /* INCLUDED_CYFITTERIAR_INC */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc new file mode 100644 index 0000000..21c6360 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -0,0 +1,1602 @@ +; +; File Name: cyfitterrv.inc +; +; PSoC Creator 4.2 +; +; Description: +; +; +;------------------------------------------------------------------------------- +; Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +; You may use this file only in accordance with the license, terms, conditions, +; disclaimers, and limitations in the end user license agreement accompanying +; the software package with which this file was provided. +;------------------------------------------------------------------------------- + + IF :LNOT::DEF:INCLUDED_CYFITTERRV_INC +INCLUDED_CYFITTERRV_INC EQU 1 + GET cydevicerv.inc + GET cydevicerv_trm.inc + +; LED +LED__0__INTTYPE EQU CYREG_PICU12_INTTYPE2 +LED__0__MASK EQU 0x04 +LED__0__PC EQU CYREG_PRT12_PC2 +LED__0__PORT EQU 12 +LED__0__SHIFT EQU 2 +LED__1__INTTYPE EQU CYREG_PICU12_INTTYPE3 +LED__1__MASK EQU 0x08 +LED__1__PC EQU CYREG_PRT12_PC3 +LED__1__PORT EQU 12 +LED__1__SHIFT EQU 3 +LED__AG EQU CYREG_PRT12_AG +LED__BIE EQU CYREG_PRT12_BIE +LED__BIT_MASK EQU CYREG_PRT12_BIT_MASK +LED__BYP EQU CYREG_PRT12_BYP +LED__DM0 EQU CYREG_PRT12_DM0 +LED__DM1 EQU CYREG_PRT12_DM1 +LED__DM2 EQU CYREG_PRT12_DM2 +LED__DR EQU CYREG_PRT12_DR +LED__INP_DIS EQU CYREG_PRT12_INP_DIS +LED__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +LED__MASK EQU 0x0C +LED__PORT EQU 12 +LED__PRT EQU CYREG_PRT12_PRT +LED__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +LED__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +LED__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +LED__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +LED__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +LED__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +LED__PS EQU CYREG_PRT12_PS +LED__SHIFT EQU 2 +LED__SIO_CFG EQU CYREG_PRT12_SIO_CFG +LED__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +LED__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +LED__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +LED__SLW EQU CYREG_PRT12_SLW + +; USBFS +USBFS_arb_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_arb_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_arb_int__INTC_MASK EQU 0x400000 +USBFS_arb_int__INTC_NUMBER EQU 22 +USBFS_arb_int__INTC_PRIOR_NUM EQU 7 +USBFS_arb_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_22 +USBFS_arb_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_arb_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_bus_reset__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_bus_reset__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_bus_reset__INTC_MASK EQU 0x800000 +USBFS_bus_reset__INTC_NUMBER EQU 23 +USBFS_bus_reset__INTC_PRIOR_NUM EQU 7 +USBFS_bus_reset__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_23 +USBFS_bus_reset__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_bus_reset__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_Dm__0__INTTYPE EQU CYREG_PICU15_INTTYPE7 +USBFS_Dm__0__MASK EQU 0x80 +USBFS_Dm__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC1 +USBFS_Dm__0__PORT EQU 15 +USBFS_Dm__0__SHIFT EQU 7 +USBFS_Dm__AG EQU CYREG_PRT15_AG +USBFS_Dm__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dm__BIE EQU CYREG_PRT15_BIE +USBFS_Dm__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dm__BYP EQU CYREG_PRT15_BYP +USBFS_Dm__CTL EQU CYREG_PRT15_CTL +USBFS_Dm__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dm__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dm__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dm__DR EQU CYREG_PRT15_DR +USBFS_Dm__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dm__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dm__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dm__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dm__MASK EQU 0x80 +USBFS_Dm__PORT EQU 15 +USBFS_Dm__PRT EQU CYREG_PRT15_PRT +USBFS_Dm__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dm__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dm__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dm__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dm__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dm__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dm__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dm__PS EQU CYREG_PRT15_PS +USBFS_Dm__SHIFT EQU 7 +USBFS_Dm__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__0__INTTYPE EQU CYREG_PICU15_INTTYPE6 +USBFS_Dp__0__MASK EQU 0x40 +USBFS_Dp__0__PC EQU CYREG_IO_PC_PRT15_7_6_PC0 +USBFS_Dp__0__PORT EQU 15 +USBFS_Dp__0__SHIFT EQU 6 +USBFS_Dp__AG EQU CYREG_PRT15_AG +USBFS_Dp__AMUX EQU CYREG_PRT15_AMUX +USBFS_Dp__BIE EQU CYREG_PRT15_BIE +USBFS_Dp__BIT_MASK EQU CYREG_PRT15_BIT_MASK +USBFS_Dp__BYP EQU CYREG_PRT15_BYP +USBFS_Dp__CTL EQU CYREG_PRT15_CTL +USBFS_Dp__DM0 EQU CYREG_PRT15_DM0 +USBFS_Dp__DM1 EQU CYREG_PRT15_DM1 +USBFS_Dp__DM2 EQU CYREG_PRT15_DM2 +USBFS_Dp__DR EQU CYREG_PRT15_DR +USBFS_Dp__INP_DIS EQU CYREG_PRT15_INP_DIS +USBFS_Dp__INTSTAT EQU CYREG_PICU15_INTSTAT +USBFS_Dp__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +USBFS_Dp__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +USBFS_Dp__LCD_EN EQU CYREG_PRT15_LCD_EN +USBFS_Dp__MASK EQU 0x40 +USBFS_Dp__PORT EQU 15 +USBFS_Dp__PRT EQU CYREG_PRT15_PRT +USBFS_Dp__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +USBFS_Dp__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +USBFS_Dp__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +USBFS_Dp__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +USBFS_Dp__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +USBFS_Dp__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +USBFS_Dp__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +USBFS_Dp__PS EQU CYREG_PRT15_PS +USBFS_Dp__SHIFT EQU 6 +USBFS_Dp__SLW EQU CYREG_PRT15_SLW +USBFS_Dp__SNAP EQU CYREG_PICU_15_SNAP_15 +USBFS_dp_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_dp_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_dp_int__INTC_MASK EQU 0x1000 +USBFS_dp_int__INTC_NUMBER EQU 12 +USBFS_dp_int__INTC_PRIOR_NUM EQU 7 +USBFS_dp_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_12 +USBFS_dp_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_dp_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_0__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_0__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_0__INTC_MASK EQU 0x1000000 +USBFS_ep_0__INTC_NUMBER EQU 24 +USBFS_ep_0__INTC_PRIOR_NUM EQU 7 +USBFS_ep_0__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_24 +USBFS_ep_0__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_0__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_1__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_1__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_1__INTC_MASK EQU 0x01 +USBFS_ep_1__INTC_NUMBER EQU 0 +USBFS_ep_1__INTC_PRIOR_NUM EQU 7 +USBFS_ep_1__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0 +USBFS_ep_1__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_1__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_ep_2__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_ep_2__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_ep_2__INTC_MASK EQU 0x02 +USBFS_ep_2__INTC_NUMBER EQU 1 +USBFS_ep_2__INTC_PRIOR_NUM EQU 7 +USBFS_ep_2__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1 +USBFS_ep_2__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_ep_2__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_sof_int__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 +USBFS_sof_int__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0 +USBFS_sof_int__INTC_MASK EQU 0x200000 +USBFS_sof_int__INTC_NUMBER EQU 21 +USBFS_sof_int__INTC_PRIOR_NUM EQU 7 +USBFS_sof_int__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_21 +USBFS_sof_int__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 +USBFS_sof_int__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +USBFS_USB__ARB_CFG EQU CYREG_USB_ARB_CFG +USBFS_USB__ARB_EP1_CFG EQU CYREG_USB_ARB_EP1_CFG +USBFS_USB__ARB_EP1_INT_EN EQU CYREG_USB_ARB_EP1_INT_EN +USBFS_USB__ARB_EP1_SR EQU CYREG_USB_ARB_EP1_SR +USBFS_USB__ARB_EP2_CFG EQU CYREG_USB_ARB_EP2_CFG +USBFS_USB__ARB_EP2_INT_EN EQU CYREG_USB_ARB_EP2_INT_EN +USBFS_USB__ARB_EP2_SR EQU CYREG_USB_ARB_EP2_SR +USBFS_USB__ARB_EP3_CFG EQU CYREG_USB_ARB_EP3_CFG +USBFS_USB__ARB_EP3_INT_EN EQU CYREG_USB_ARB_EP3_INT_EN +USBFS_USB__ARB_EP3_SR EQU CYREG_USB_ARB_EP3_SR +USBFS_USB__ARB_EP4_CFG EQU CYREG_USB_ARB_EP4_CFG +USBFS_USB__ARB_EP4_INT_EN EQU CYREG_USB_ARB_EP4_INT_EN +USBFS_USB__ARB_EP4_SR EQU CYREG_USB_ARB_EP4_SR +USBFS_USB__ARB_EP5_CFG EQU CYREG_USB_ARB_EP5_CFG +USBFS_USB__ARB_EP5_INT_EN EQU CYREG_USB_ARB_EP5_INT_EN +USBFS_USB__ARB_EP5_SR EQU CYREG_USB_ARB_EP5_SR +USBFS_USB__ARB_EP6_CFG EQU CYREG_USB_ARB_EP6_CFG +USBFS_USB__ARB_EP6_INT_EN EQU CYREG_USB_ARB_EP6_INT_EN +USBFS_USB__ARB_EP6_SR EQU CYREG_USB_ARB_EP6_SR +USBFS_USB__ARB_EP7_CFG EQU CYREG_USB_ARB_EP7_CFG +USBFS_USB__ARB_EP7_INT_EN EQU CYREG_USB_ARB_EP7_INT_EN +USBFS_USB__ARB_EP7_SR EQU CYREG_USB_ARB_EP7_SR +USBFS_USB__ARB_EP8_CFG EQU CYREG_USB_ARB_EP8_CFG +USBFS_USB__ARB_EP8_INT_EN EQU CYREG_USB_ARB_EP8_INT_EN +USBFS_USB__ARB_EP8_SR EQU CYREG_USB_ARB_EP8_SR +USBFS_USB__ARB_INT_EN EQU CYREG_USB_ARB_INT_EN +USBFS_USB__ARB_INT_SR EQU CYREG_USB_ARB_INT_SR +USBFS_USB__ARB_RW1_DR EQU CYREG_USB_ARB_RW1_DR +USBFS_USB__ARB_RW1_RA EQU CYREG_USB_ARB_RW1_RA +USBFS_USB__ARB_RW1_RA_MSB EQU CYREG_USB_ARB_RW1_RA_MSB +USBFS_USB__ARB_RW1_WA EQU CYREG_USB_ARB_RW1_WA +USBFS_USB__ARB_RW1_WA_MSB EQU CYREG_USB_ARB_RW1_WA_MSB +USBFS_USB__ARB_RW2_DR EQU CYREG_USB_ARB_RW2_DR +USBFS_USB__ARB_RW2_RA EQU CYREG_USB_ARB_RW2_RA +USBFS_USB__ARB_RW2_RA_MSB EQU CYREG_USB_ARB_RW2_RA_MSB +USBFS_USB__ARB_RW2_WA EQU CYREG_USB_ARB_RW2_WA +USBFS_USB__ARB_RW2_WA_MSB EQU CYREG_USB_ARB_RW2_WA_MSB +USBFS_USB__ARB_RW3_DR EQU CYREG_USB_ARB_RW3_DR +USBFS_USB__ARB_RW3_RA EQU CYREG_USB_ARB_RW3_RA +USBFS_USB__ARB_RW3_RA_MSB EQU CYREG_USB_ARB_RW3_RA_MSB +USBFS_USB__ARB_RW3_WA EQU CYREG_USB_ARB_RW3_WA +USBFS_USB__ARB_RW3_WA_MSB EQU CYREG_USB_ARB_RW3_WA_MSB +USBFS_USB__ARB_RW4_DR EQU CYREG_USB_ARB_RW4_DR +USBFS_USB__ARB_RW4_RA EQU CYREG_USB_ARB_RW4_RA +USBFS_USB__ARB_RW4_RA_MSB EQU CYREG_USB_ARB_RW4_RA_MSB +USBFS_USB__ARB_RW4_WA EQU CYREG_USB_ARB_RW4_WA +USBFS_USB__ARB_RW4_WA_MSB EQU CYREG_USB_ARB_RW4_WA_MSB +USBFS_USB__ARB_RW5_DR EQU CYREG_USB_ARB_RW5_DR +USBFS_USB__ARB_RW5_RA EQU CYREG_USB_ARB_RW5_RA +USBFS_USB__ARB_RW5_RA_MSB EQU CYREG_USB_ARB_RW5_RA_MSB +USBFS_USB__ARB_RW5_WA EQU CYREG_USB_ARB_RW5_WA +USBFS_USB__ARB_RW5_WA_MSB EQU CYREG_USB_ARB_RW5_WA_MSB +USBFS_USB__ARB_RW6_DR EQU CYREG_USB_ARB_RW6_DR +USBFS_USB__ARB_RW6_RA EQU CYREG_USB_ARB_RW6_RA +USBFS_USB__ARB_RW6_RA_MSB EQU CYREG_USB_ARB_RW6_RA_MSB +USBFS_USB__ARB_RW6_WA EQU CYREG_USB_ARB_RW6_WA +USBFS_USB__ARB_RW6_WA_MSB EQU CYREG_USB_ARB_RW6_WA_MSB +USBFS_USB__ARB_RW7_DR EQU CYREG_USB_ARB_RW7_DR +USBFS_USB__ARB_RW7_RA EQU CYREG_USB_ARB_RW7_RA +USBFS_USB__ARB_RW7_RA_MSB EQU CYREG_USB_ARB_RW7_RA_MSB +USBFS_USB__ARB_RW7_WA EQU CYREG_USB_ARB_RW7_WA +USBFS_USB__ARB_RW7_WA_MSB EQU CYREG_USB_ARB_RW7_WA_MSB +USBFS_USB__ARB_RW8_DR EQU CYREG_USB_ARB_RW8_DR +USBFS_USB__ARB_RW8_RA EQU CYREG_USB_ARB_RW8_RA +USBFS_USB__ARB_RW8_RA_MSB EQU CYREG_USB_ARB_RW8_RA_MSB +USBFS_USB__ARB_RW8_WA EQU CYREG_USB_ARB_RW8_WA +USBFS_USB__ARB_RW8_WA_MSB EQU CYREG_USB_ARB_RW8_WA_MSB +USBFS_USB__BUF_SIZE EQU CYREG_USB_BUF_SIZE +USBFS_USB__BUS_RST_CNT EQU CYREG_USB_BUS_RST_CNT +USBFS_USB__CR0 EQU CYREG_USB_CR0 +USBFS_USB__CR1 EQU CYREG_USB_CR1 +USBFS_USB__CWA EQU CYREG_USB_CWA +USBFS_USB__CWA_MSB EQU CYREG_USB_CWA_MSB +USBFS_USB__DMA_THRES EQU CYREG_USB_DMA_THRES +USBFS_USB__DMA_THRES_MSB EQU CYREG_USB_DMA_THRES_MSB +USBFS_USB__DYN_RECONFIG EQU CYREG_USB_DYN_RECONFIG +USBFS_USB__EP_ACTIVE EQU CYREG_USB_EP_ACTIVE +USBFS_USB__EP_TYPE EQU CYREG_USB_EP_TYPE +USBFS_USB__EP0_CNT EQU CYREG_USB_EP0_CNT +USBFS_USB__EP0_CR EQU CYREG_USB_EP0_CR +USBFS_USB__EP0_DR0 EQU CYREG_USB_EP0_DR0 +USBFS_USB__EP0_DR1 EQU CYREG_USB_EP0_DR1 +USBFS_USB__EP0_DR2 EQU CYREG_USB_EP0_DR2 +USBFS_USB__EP0_DR3 EQU CYREG_USB_EP0_DR3 +USBFS_USB__EP0_DR4 EQU CYREG_USB_EP0_DR4 +USBFS_USB__EP0_DR5 EQU CYREG_USB_EP0_DR5 +USBFS_USB__EP0_DR6 EQU CYREG_USB_EP0_DR6 +USBFS_USB__EP0_DR7 EQU CYREG_USB_EP0_DR7 +USBFS_USB__MEM_DATA EQU CYREG_USB_MEM_DATA_MBASE +USBFS_USB__PM_ACT_CFG EQU CYREG_PM_ACT_CFG5 +USBFS_USB__PM_ACT_MSK EQU 0x01 +USBFS_USB__PM_STBY_CFG EQU CYREG_PM_STBY_CFG5 +USBFS_USB__PM_STBY_MSK EQU 0x01 +USBFS_USB__SIE_EP_INT_EN EQU CYREG_USB_SIE_EP_INT_EN +USBFS_USB__SIE_EP_INT_SR EQU CYREG_USB_SIE_EP_INT_SR +USBFS_USB__SIE_EP1_CNT0 EQU CYREG_USB_SIE_EP1_CNT0 +USBFS_USB__SIE_EP1_CNT1 EQU CYREG_USB_SIE_EP1_CNT1 +USBFS_USB__SIE_EP1_CR0 EQU CYREG_USB_SIE_EP1_CR0 +USBFS_USB__SIE_EP2_CNT0 EQU CYREG_USB_SIE_EP2_CNT0 +USBFS_USB__SIE_EP2_CNT1 EQU CYREG_USB_SIE_EP2_CNT1 +USBFS_USB__SIE_EP2_CR0 EQU CYREG_USB_SIE_EP2_CR0 +USBFS_USB__SIE_EP3_CNT0 EQU CYREG_USB_SIE_EP3_CNT0 +USBFS_USB__SIE_EP3_CNT1 EQU CYREG_USB_SIE_EP3_CNT1 +USBFS_USB__SIE_EP3_CR0 EQU CYREG_USB_SIE_EP3_CR0 +USBFS_USB__SIE_EP4_CNT0 EQU CYREG_USB_SIE_EP4_CNT0 +USBFS_USB__SIE_EP4_CNT1 EQU CYREG_USB_SIE_EP4_CNT1 +USBFS_USB__SIE_EP4_CR0 EQU CYREG_USB_SIE_EP4_CR0 +USBFS_USB__SIE_EP5_CNT0 EQU CYREG_USB_SIE_EP5_CNT0 +USBFS_USB__SIE_EP5_CNT1 EQU CYREG_USB_SIE_EP5_CNT1 +USBFS_USB__SIE_EP5_CR0 EQU CYREG_USB_SIE_EP5_CR0 +USBFS_USB__SIE_EP6_CNT0 EQU CYREG_USB_SIE_EP6_CNT0 +USBFS_USB__SIE_EP6_CNT1 EQU CYREG_USB_SIE_EP6_CNT1 +USBFS_USB__SIE_EP6_CR0 EQU CYREG_USB_SIE_EP6_CR0 +USBFS_USB__SIE_EP7_CNT0 EQU CYREG_USB_SIE_EP7_CNT0 +USBFS_USB__SIE_EP7_CNT1 EQU CYREG_USB_SIE_EP7_CNT1 +USBFS_USB__SIE_EP7_CR0 EQU CYREG_USB_SIE_EP7_CR0 +USBFS_USB__SIE_EP8_CNT0 EQU CYREG_USB_SIE_EP8_CNT0 +USBFS_USB__SIE_EP8_CNT1 EQU CYREG_USB_SIE_EP8_CNT1 +USBFS_USB__SIE_EP8_CR0 EQU CYREG_USB_SIE_EP8_CR0 +USBFS_USB__SOF0 EQU CYREG_USB_SOF0 +USBFS_USB__SOF1 EQU CYREG_USB_SOF1 +USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN +USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 +USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 + +; BOOTLDR +BOOTLDR__0__INTTYPE EQU CYREG_PICU0_INTTYPE0 +BOOTLDR__0__MASK EQU 0x01 +BOOTLDR__0__PC EQU CYREG_PRT0_PC0 +BOOTLDR__0__PORT EQU 0 +BOOTLDR__0__SHIFT EQU 0 +BOOTLDR__AG EQU CYREG_PRT0_AG +BOOTLDR__AMUX EQU CYREG_PRT0_AMUX +BOOTLDR__BIE EQU CYREG_PRT0_BIE +BOOTLDR__BIT_MASK EQU CYREG_PRT0_BIT_MASK +BOOTLDR__BYP EQU CYREG_PRT0_BYP +BOOTLDR__CTL EQU CYREG_PRT0_CTL +BOOTLDR__DM0 EQU CYREG_PRT0_DM0 +BOOTLDR__DM1 EQU CYREG_PRT0_DM1 +BOOTLDR__DM2 EQU CYREG_PRT0_DM2 +BOOTLDR__DR EQU CYREG_PRT0_DR +BOOTLDR__INP_DIS EQU CYREG_PRT0_INP_DIS +BOOTLDR__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU0_BASE +BOOTLDR__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +BOOTLDR__LCD_EN EQU CYREG_PRT0_LCD_EN +BOOTLDR__MASK EQU 0x01 +BOOTLDR__PORT EQU 0 +BOOTLDR__PRT EQU CYREG_PRT0_PRT +BOOTLDR__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +BOOTLDR__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +BOOTLDR__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +BOOTLDR__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +BOOTLDR__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +BOOTLDR__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +BOOTLDR__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +BOOTLDR__PS EQU CYREG_PRT0_PS +BOOTLDR__SHIFT EQU 0 +BOOTLDR__SLW EQU CYREG_PRT0_SLW + +; TERM_EN +TERM_EN__0__INTTYPE EQU CYREG_PICU15_INTTYPE3 +TERM_EN__0__MASK EQU 0x08 +TERM_EN__0__PC EQU CYREG_IO_PC_PRT15_PC3 +TERM_EN__0__PORT EQU 15 +TERM_EN__0__SHIFT EQU 3 +TERM_EN__AG EQU CYREG_PRT15_AG +TERM_EN__AMUX EQU CYREG_PRT15_AMUX +TERM_EN__BIE EQU CYREG_PRT15_BIE +TERM_EN__BIT_MASK EQU CYREG_PRT15_BIT_MASK +TERM_EN__BYP EQU CYREG_PRT15_BYP +TERM_EN__CTL EQU CYREG_PRT15_CTL +TERM_EN__DM0 EQU CYREG_PRT15_DM0 +TERM_EN__DM1 EQU CYREG_PRT15_DM1 +TERM_EN__DM2 EQU CYREG_PRT15_DM2 +TERM_EN__DR EQU CYREG_PRT15_DR +TERM_EN__INP_DIS EQU CYREG_PRT15_INP_DIS +TERM_EN__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +TERM_EN__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +TERM_EN__LCD_EN EQU CYREG_PRT15_LCD_EN +TERM_EN__MASK EQU 0x08 +TERM_EN__PORT EQU 15 +TERM_EN__PRT EQU CYREG_PRT15_PRT +TERM_EN__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +TERM_EN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +TERM_EN__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +TERM_EN__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +TERM_EN__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +TERM_EN__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +TERM_EN__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +TERM_EN__PS EQU CYREG_PRT15_PS +TERM_EN__SHIFT EQU 3 +TERM_EN__SLW EQU CYREG_PRT15_SLW + +; SCSI_Out +SCSI_Out__0__AG EQU CYREG_PRT6_AG +SCSI_Out__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__0__DR EQU CYREG_PRT6_DR +SCSI_Out__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__0__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__0__MASK EQU 0x04 +SCSI_Out__0__PC EQU CYREG_PRT6_PC2 +SCSI_Out__0__PORT EQU 6 +SCSI_Out__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__0__PS EQU CYREG_PRT6_PS +SCSI_Out__0__SHIFT EQU 2 +SCSI_Out__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out__1__AG EQU CYREG_PRT4_AG +SCSI_Out__1__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__1__BIE EQU CYREG_PRT4_BIE +SCSI_Out__1__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__1__BYP EQU CYREG_PRT4_BYP +SCSI_Out__1__CTL EQU CYREG_PRT4_CTL +SCSI_Out__1__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__1__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__1__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__1__DR EQU CYREG_PRT4_DR +SCSI_Out__1__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__1__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__1__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__1__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__1__MASK EQU 0x40 +SCSI_Out__1__PC EQU CYREG_PRT4_PC6 +SCSI_Out__1__PORT EQU 4 +SCSI_Out__1__PRT EQU CYREG_PRT4_PRT +SCSI_Out__1__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__1__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__1__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__1__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__1__PS EQU CYREG_PRT4_PS +SCSI_Out__1__SHIFT EQU 6 +SCSI_Out__1__SLW EQU CYREG_PRT4_SLW +SCSI_Out__2__AG EQU CYREG_PRT0_AG +SCSI_Out__2__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__2__BIE EQU CYREG_PRT0_BIE +SCSI_Out__2__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__2__BYP EQU CYREG_PRT0_BYP +SCSI_Out__2__CTL EQU CYREG_PRT0_CTL +SCSI_Out__2__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__2__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__2__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__2__DR EQU CYREG_PRT0_DR +SCSI_Out__2__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__2__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__2__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__2__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__2__MASK EQU 0x80 +SCSI_Out__2__PC EQU CYREG_PRT0_PC7 +SCSI_Out__2__PORT EQU 0 +SCSI_Out__2__PRT EQU CYREG_PRT0_PRT +SCSI_Out__2__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__2__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__2__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__2__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__2__PS EQU CYREG_PRT0_PS +SCSI_Out__2__SHIFT EQU 7 +SCSI_Out__2__SLW EQU CYREG_PRT0_SLW +SCSI_Out__3__AG EQU CYREG_PRT0_AG +SCSI_Out__3__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__3__BIE EQU CYREG_PRT0_BIE +SCSI_Out__3__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__3__BYP EQU CYREG_PRT0_BYP +SCSI_Out__3__CTL EQU CYREG_PRT0_CTL +SCSI_Out__3__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__3__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__3__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__3__DR EQU CYREG_PRT0_DR +SCSI_Out__3__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__3__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__3__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__3__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__3__MASK EQU 0x20 +SCSI_Out__3__PC EQU CYREG_PRT0_PC5 +SCSI_Out__3__PORT EQU 0 +SCSI_Out__3__PRT EQU CYREG_PRT0_PRT +SCSI_Out__3__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__3__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__3__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__3__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__3__PS EQU CYREG_PRT0_PS +SCSI_Out__3__SHIFT EQU 5 +SCSI_Out__3__SLW EQU CYREG_PRT0_SLW +SCSI_Out__4__AG EQU CYREG_PRT0_AG +SCSI_Out__4__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__4__BIE EQU CYREG_PRT0_BIE +SCSI_Out__4__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__4__BYP EQU CYREG_PRT0_BYP +SCSI_Out__4__CTL EQU CYREG_PRT0_CTL +SCSI_Out__4__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__4__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__4__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__4__DR EQU CYREG_PRT0_DR +SCSI_Out__4__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__4__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__4__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__4__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__4__MASK EQU 0x08 +SCSI_Out__4__PC EQU CYREG_PRT0_PC3 +SCSI_Out__4__PORT EQU 0 +SCSI_Out__4__PRT EQU CYREG_PRT0_PRT +SCSI_Out__4__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__4__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__4__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__4__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__4__PS EQU CYREG_PRT0_PS +SCSI_Out__4__SHIFT EQU 3 +SCSI_Out__4__SLW EQU CYREG_PRT0_SLW +SCSI_Out__5__AG EQU CYREG_PRT0_AG +SCSI_Out__5__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__5__BIE EQU CYREG_PRT0_BIE +SCSI_Out__5__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__5__BYP EQU CYREG_PRT0_BYP +SCSI_Out__5__CTL EQU CYREG_PRT0_CTL +SCSI_Out__5__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__5__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__5__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__5__DR EQU CYREG_PRT0_DR +SCSI_Out__5__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__5__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__5__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__5__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__5__MASK EQU 0x02 +SCSI_Out__5__PC EQU CYREG_PRT0_PC1 +SCSI_Out__5__PORT EQU 0 +SCSI_Out__5__PRT EQU CYREG_PRT0_PRT +SCSI_Out__5__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__5__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__5__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__5__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__5__PS EQU CYREG_PRT0_PS +SCSI_Out__5__SHIFT EQU 1 +SCSI_Out__5__SLW EQU CYREG_PRT0_SLW +SCSI_Out__6__AG EQU CYREG_PRT4_AG +SCSI_Out__6__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__6__BIE EQU CYREG_PRT4_BIE +SCSI_Out__6__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__6__BYP EQU CYREG_PRT4_BYP +SCSI_Out__6__CTL EQU CYREG_PRT4_CTL +SCSI_Out__6__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__6__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__6__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__6__DR EQU CYREG_PRT4_DR +SCSI_Out__6__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__6__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__6__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__6__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__6__MASK EQU 0x02 +SCSI_Out__6__PC EQU CYREG_PRT4_PC1 +SCSI_Out__6__PORT EQU 4 +SCSI_Out__6__PRT EQU CYREG_PRT4_PRT +SCSI_Out__6__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__6__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__6__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__6__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__6__PS EQU CYREG_PRT4_PS +SCSI_Out__6__SHIFT EQU 1 +SCSI_Out__6__SLW EQU CYREG_PRT4_SLW +SCSI_Out__7__AG EQU CYREG_PRT4_AG +SCSI_Out__7__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__7__BIE EQU CYREG_PRT4_BIE +SCSI_Out__7__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__7__BYP EQU CYREG_PRT4_BYP +SCSI_Out__7__CTL EQU CYREG_PRT4_CTL +SCSI_Out__7__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__7__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__7__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__7__DR EQU CYREG_PRT4_DR +SCSI_Out__7__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__7__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__7__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__7__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__7__MASK EQU 0x01 +SCSI_Out__7__PC EQU CYREG_PRT4_PC0 +SCSI_Out__7__PORT EQU 4 +SCSI_Out__7__PRT EQU CYREG_PRT4_PRT +SCSI_Out__7__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__7__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__7__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__7__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__7__PS EQU CYREG_PRT4_PS +SCSI_Out__7__SHIFT EQU 0 +SCSI_Out__7__SLW EQU CYREG_PRT4_SLW +SCSI_Out__BSY__AG EQU CYREG_PRT4_AG +SCSI_Out__BSY__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__BSY__BIE EQU CYREG_PRT4_BIE +SCSI_Out__BSY__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__BSY__BYP EQU CYREG_PRT4_BYP +SCSI_Out__BSY__CTL EQU CYREG_PRT4_CTL +SCSI_Out__BSY__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__BSY__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__BSY__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__BSY__DR EQU CYREG_PRT4_DR +SCSI_Out__BSY__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__BSY__INTTYPE EQU CYREG_PICU4_INTTYPE6 +SCSI_Out__BSY__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__BSY__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__BSY__MASK EQU 0x40 +SCSI_Out__BSY__PC EQU CYREG_PRT4_PC6 +SCSI_Out__BSY__PORT EQU 4 +SCSI_Out__BSY__PRT EQU CYREG_PRT4_PRT +SCSI_Out__BSY__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__BSY__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__BSY__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__BSY__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__BSY__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__BSY__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__BSY__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__BSY__PS EQU CYREG_PRT4_PS +SCSI_Out__BSY__SHIFT EQU 6 +SCSI_Out__BSY__SLW EQU CYREG_PRT4_SLW +SCSI_Out__CD__AG EQU CYREG_PRT0_AG +SCSI_Out__CD__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__CD__BIE EQU CYREG_PRT0_BIE +SCSI_Out__CD__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__CD__BYP EQU CYREG_PRT0_BYP +SCSI_Out__CD__CTL EQU CYREG_PRT0_CTL +SCSI_Out__CD__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__CD__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__CD__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__CD__DR EQU CYREG_PRT0_DR +SCSI_Out__CD__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__CD__INTTYPE EQU CYREG_PICU0_INTTYPE1 +SCSI_Out__CD__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__CD__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__CD__MASK EQU 0x02 +SCSI_Out__CD__PC EQU CYREG_PRT0_PC1 +SCSI_Out__CD__PORT EQU 0 +SCSI_Out__CD__PRT EQU CYREG_PRT0_PRT +SCSI_Out__CD__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__CD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__CD__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__CD__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__CD__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__CD__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__CD__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__CD__PS EQU CYREG_PRT0_PS +SCSI_Out__CD__SHIFT EQU 1 +SCSI_Out__CD__SLW EQU CYREG_PRT0_SLW +SCSI_Out__DBP_raw__AG EQU CYREG_PRT6_AG +SCSI_Out__DBP_raw__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out__DBP_raw__BIE EQU CYREG_PRT6_BIE +SCSI_Out__DBP_raw__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out__DBP_raw__BYP EQU CYREG_PRT6_BYP +SCSI_Out__DBP_raw__CTL EQU CYREG_PRT6_CTL +SCSI_Out__DBP_raw__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out__DBP_raw__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out__DBP_raw__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out__DBP_raw__DR EQU CYREG_PRT6_DR +SCSI_Out__DBP_raw__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out__DBP_raw__INTTYPE EQU CYREG_PICU6_INTTYPE2 +SCSI_Out__DBP_raw__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out__DBP_raw__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out__DBP_raw__MASK EQU 0x04 +SCSI_Out__DBP_raw__PC EQU CYREG_PRT6_PC2 +SCSI_Out__DBP_raw__PORT EQU 6 +SCSI_Out__DBP_raw__PRT EQU CYREG_PRT6_PRT +SCSI_Out__DBP_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out__DBP_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out__DBP_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out__DBP_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out__DBP_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out__DBP_raw__PS EQU CYREG_PRT6_PS +SCSI_Out__DBP_raw__SHIFT EQU 2 +SCSI_Out__DBP_raw__SLW EQU CYREG_PRT6_SLW +SCSI_Out__IO_raw__AG EQU CYREG_PRT4_AG +SCSI_Out__IO_raw__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__IO_raw__BIE EQU CYREG_PRT4_BIE +SCSI_Out__IO_raw__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__IO_raw__BYP EQU CYREG_PRT4_BYP +SCSI_Out__IO_raw__CTL EQU CYREG_PRT4_CTL +SCSI_Out__IO_raw__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__IO_raw__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__IO_raw__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__IO_raw__DR EQU CYREG_PRT4_DR +SCSI_Out__IO_raw__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__IO_raw__INTTYPE EQU CYREG_PICU4_INTTYPE0 +SCSI_Out__IO_raw__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__IO_raw__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__IO_raw__MASK EQU 0x01 +SCSI_Out__IO_raw__PC EQU CYREG_PRT4_PC0 +SCSI_Out__IO_raw__PORT EQU 4 +SCSI_Out__IO_raw__PRT EQU CYREG_PRT4_PRT +SCSI_Out__IO_raw__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__IO_raw__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__IO_raw__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__IO_raw__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__IO_raw__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__IO_raw__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__IO_raw__PS EQU CYREG_PRT4_PS +SCSI_Out__IO_raw__SHIFT EQU 0 +SCSI_Out__IO_raw__SLW EQU CYREG_PRT4_SLW +SCSI_Out__MSG__AG EQU CYREG_PRT0_AG +SCSI_Out__MSG__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__MSG__BIE EQU CYREG_PRT0_BIE +SCSI_Out__MSG__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__MSG__BYP EQU CYREG_PRT0_BYP +SCSI_Out__MSG__CTL EQU CYREG_PRT0_CTL +SCSI_Out__MSG__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__MSG__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__MSG__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__MSG__DR EQU CYREG_PRT0_DR +SCSI_Out__MSG__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__MSG__INTTYPE EQU CYREG_PICU0_INTTYPE5 +SCSI_Out__MSG__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__MSG__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__MSG__MASK EQU 0x20 +SCSI_Out__MSG__PC EQU CYREG_PRT0_PC5 +SCSI_Out__MSG__PORT EQU 0 +SCSI_Out__MSG__PRT EQU CYREG_PRT0_PRT +SCSI_Out__MSG__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__MSG__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__MSG__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__MSG__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__MSG__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__MSG__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__MSG__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__MSG__PS EQU CYREG_PRT0_PS +SCSI_Out__MSG__SHIFT EQU 5 +SCSI_Out__MSG__SLW EQU CYREG_PRT0_SLW +SCSI_Out__REQ__AG EQU CYREG_PRT4_AG +SCSI_Out__REQ__AMUX EQU CYREG_PRT4_AMUX +SCSI_Out__REQ__BIE EQU CYREG_PRT4_BIE +SCSI_Out__REQ__BIT_MASK EQU CYREG_PRT4_BIT_MASK +SCSI_Out__REQ__BYP EQU CYREG_PRT4_BYP +SCSI_Out__REQ__CTL EQU CYREG_PRT4_CTL +SCSI_Out__REQ__DM0 EQU CYREG_PRT4_DM0 +SCSI_Out__REQ__DM1 EQU CYREG_PRT4_DM1 +SCSI_Out__REQ__DM2 EQU CYREG_PRT4_DM2 +SCSI_Out__REQ__DR EQU CYREG_PRT4_DR +SCSI_Out__REQ__INP_DIS EQU CYREG_PRT4_INP_DIS +SCSI_Out__REQ__INTTYPE EQU CYREG_PICU4_INTTYPE1 +SCSI_Out__REQ__LCD_COM_SEG EQU CYREG_PRT4_LCD_COM_SEG +SCSI_Out__REQ__LCD_EN EQU CYREG_PRT4_LCD_EN +SCSI_Out__REQ__MASK EQU 0x02 +SCSI_Out__REQ__PC EQU CYREG_PRT4_PC1 +SCSI_Out__REQ__PORT EQU 4 +SCSI_Out__REQ__PRT EQU CYREG_PRT4_PRT +SCSI_Out__REQ__PRTDSI__CAPS_SEL EQU CYREG_PRT4_CAPS_SEL +SCSI_Out__REQ__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT4_DBL_SYNC_IN +SCSI_Out__REQ__PRTDSI__OE_SEL0 EQU CYREG_PRT4_OE_SEL0 +SCSI_Out__REQ__PRTDSI__OE_SEL1 EQU CYREG_PRT4_OE_SEL1 +SCSI_Out__REQ__PRTDSI__OUT_SEL0 EQU CYREG_PRT4_OUT_SEL0 +SCSI_Out__REQ__PRTDSI__OUT_SEL1 EQU CYREG_PRT4_OUT_SEL1 +SCSI_Out__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT4_SYNC_OUT +SCSI_Out__REQ__PS EQU CYREG_PRT4_PS +SCSI_Out__REQ__SHIFT EQU 1 +SCSI_Out__REQ__SLW EQU CYREG_PRT4_SLW +SCSI_Out__RST__AG EQU CYREG_PRT0_AG +SCSI_Out__RST__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__RST__BIE EQU CYREG_PRT0_BIE +SCSI_Out__RST__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__RST__BYP EQU CYREG_PRT0_BYP +SCSI_Out__RST__CTL EQU CYREG_PRT0_CTL +SCSI_Out__RST__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__RST__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__RST__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__RST__DR EQU CYREG_PRT0_DR +SCSI_Out__RST__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__RST__INTTYPE EQU CYREG_PICU0_INTTYPE7 +SCSI_Out__RST__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__RST__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__RST__MASK EQU 0x80 +SCSI_Out__RST__PC EQU CYREG_PRT0_PC7 +SCSI_Out__RST__PORT EQU 0 +SCSI_Out__RST__PRT EQU CYREG_PRT0_PRT +SCSI_Out__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__RST__PS EQU CYREG_PRT0_PS +SCSI_Out__RST__SHIFT EQU 7 +SCSI_Out__RST__SLW EQU CYREG_PRT0_SLW +SCSI_Out__SEL__AG EQU CYREG_PRT0_AG +SCSI_Out__SEL__AMUX EQU CYREG_PRT0_AMUX +SCSI_Out__SEL__BIE EQU CYREG_PRT0_BIE +SCSI_Out__SEL__BIT_MASK EQU CYREG_PRT0_BIT_MASK +SCSI_Out__SEL__BYP EQU CYREG_PRT0_BYP +SCSI_Out__SEL__CTL EQU CYREG_PRT0_CTL +SCSI_Out__SEL__DM0 EQU CYREG_PRT0_DM0 +SCSI_Out__SEL__DM1 EQU CYREG_PRT0_DM1 +SCSI_Out__SEL__DM2 EQU CYREG_PRT0_DM2 +SCSI_Out__SEL__DR EQU CYREG_PRT0_DR +SCSI_Out__SEL__INP_DIS EQU CYREG_PRT0_INP_DIS +SCSI_Out__SEL__INTTYPE EQU CYREG_PICU0_INTTYPE3 +SCSI_Out__SEL__LCD_COM_SEG EQU CYREG_PRT0_LCD_COM_SEG +SCSI_Out__SEL__LCD_EN EQU CYREG_PRT0_LCD_EN +SCSI_Out__SEL__MASK EQU 0x08 +SCSI_Out__SEL__PC EQU CYREG_PRT0_PC3 +SCSI_Out__SEL__PORT EQU 0 +SCSI_Out__SEL__PRT EQU CYREG_PRT0_PRT +SCSI_Out__SEL__PRTDSI__CAPS_SEL EQU CYREG_PRT0_CAPS_SEL +SCSI_Out__SEL__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT0_DBL_SYNC_IN +SCSI_Out__SEL__PRTDSI__OE_SEL0 EQU CYREG_PRT0_OE_SEL0 +SCSI_Out__SEL__PRTDSI__OE_SEL1 EQU CYREG_PRT0_OE_SEL1 +SCSI_Out__SEL__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0 +SCSI_Out__SEL__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1 +SCSI_Out__SEL__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT +SCSI_Out__SEL__PS EQU CYREG_PRT0_PS +SCSI_Out__SEL__SHIFT EQU 3 +SCSI_Out__SEL__SLW EQU CYREG_PRT0_SLW +SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__0__MASK EQU 0x80 +SCSI_Out_DBx__0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__0__PORT EQU 6 +SCSI_Out_DBx__0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__0__SHIFT EQU 7 +SCSI_Out_DBx__0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__1__MASK EQU 0x20 +SCSI_Out_DBx__1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__1__PORT EQU 6 +SCSI_Out_DBx__1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__1__SHIFT EQU 5 +SCSI_Out_DBx__1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__2__MASK EQU 0x20 +SCSI_Out_DBx__2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__2__PORT EQU 12 +SCSI_Out_DBx__2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__2__SHIFT EQU 5 +SCSI_Out_DBx__2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__3__MASK EQU 0x80 +SCSI_Out_DBx__3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__3__PORT EQU 2 +SCSI_Out_DBx__3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__3__SHIFT EQU 7 +SCSI_Out_DBx__3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__4__MASK EQU 0x20 +SCSI_Out_DBx__4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__4__PORT EQU 2 +SCSI_Out_DBx__4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__4__SHIFT EQU 5 +SCSI_Out_DBx__4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__5__MASK EQU 0x08 +SCSI_Out_DBx__5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__5__PORT EQU 2 +SCSI_Out_DBx__5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__5__SHIFT EQU 3 +SCSI_Out_DBx__5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__6__MASK EQU 0x02 +SCSI_Out_DBx__6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__6__PORT EQU 2 +SCSI_Out_DBx__6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__6__SHIFT EQU 1 +SCSI_Out_DBx__6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__7__MASK EQU 0x20 +SCSI_Out_DBx__7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__7__PORT EQU 15 +SCSI_Out_DBx__7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__7__SHIFT EQU 5 +SCSI_Out_DBx__7__SLW EQU CYREG_PRT15_SLW +SCSI_Out_DBx__DB0__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB0__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB0__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB0__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB0__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB0__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB0__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB0__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB0__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB0__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB0__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB0__INTTYPE EQU CYREG_PICU6_INTTYPE7 +SCSI_Out_DBx__DB0__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB0__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB0__MASK EQU 0x80 +SCSI_Out_DBx__DB0__PC EQU CYREG_PRT6_PC7 +SCSI_Out_DBx__DB0__PORT EQU 6 +SCSI_Out_DBx__DB0__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB0__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB0__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB0__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB0__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB0__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB0__SHIFT EQU 7 +SCSI_Out_DBx__DB0__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB1__AG EQU CYREG_PRT6_AG +SCSI_Out_DBx__DB1__AMUX EQU CYREG_PRT6_AMUX +SCSI_Out_DBx__DB1__BIE EQU CYREG_PRT6_BIE +SCSI_Out_DBx__DB1__BIT_MASK EQU CYREG_PRT6_BIT_MASK +SCSI_Out_DBx__DB1__BYP EQU CYREG_PRT6_BYP +SCSI_Out_DBx__DB1__CTL EQU CYREG_PRT6_CTL +SCSI_Out_DBx__DB1__DM0 EQU CYREG_PRT6_DM0 +SCSI_Out_DBx__DB1__DM1 EQU CYREG_PRT6_DM1 +SCSI_Out_DBx__DB1__DM2 EQU CYREG_PRT6_DM2 +SCSI_Out_DBx__DB1__DR EQU CYREG_PRT6_DR +SCSI_Out_DBx__DB1__INP_DIS EQU CYREG_PRT6_INP_DIS +SCSI_Out_DBx__DB1__INTTYPE EQU CYREG_PICU6_INTTYPE5 +SCSI_Out_DBx__DB1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG +SCSI_Out_DBx__DB1__LCD_EN EQU CYREG_PRT6_LCD_EN +SCSI_Out_DBx__DB1__MASK EQU 0x20 +SCSI_Out_DBx__DB1__PC EQU CYREG_PRT6_PC5 +SCSI_Out_DBx__DB1__PORT EQU 6 +SCSI_Out_DBx__DB1__PRT EQU CYREG_PRT6_PRT +SCSI_Out_DBx__DB1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL +SCSI_Out_DBx__DB1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0 +SCSI_Out_DBx__DB1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1 +SCSI_Out_DBx__DB1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT +SCSI_Out_DBx__DB1__PS EQU CYREG_PRT6_PS +SCSI_Out_DBx__DB1__SHIFT EQU 5 +SCSI_Out_DBx__DB1__SLW EQU CYREG_PRT6_SLW +SCSI_Out_DBx__DB2__AG EQU CYREG_PRT12_AG +SCSI_Out_DBx__DB2__BIE EQU CYREG_PRT12_BIE +SCSI_Out_DBx__DB2__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SCSI_Out_DBx__DB2__BYP EQU CYREG_PRT12_BYP +SCSI_Out_DBx__DB2__DM0 EQU CYREG_PRT12_DM0 +SCSI_Out_DBx__DB2__DM1 EQU CYREG_PRT12_DM1 +SCSI_Out_DBx__DB2__DM2 EQU CYREG_PRT12_DM2 +SCSI_Out_DBx__DB2__DR EQU CYREG_PRT12_DR +SCSI_Out_DBx__DB2__INP_DIS EQU CYREG_PRT12_INP_DIS +SCSI_Out_DBx__DB2__INTTYPE EQU CYREG_PICU12_INTTYPE5 +SCSI_Out_DBx__DB2__MASK EQU 0x20 +SCSI_Out_DBx__DB2__PC EQU CYREG_PRT12_PC5 +SCSI_Out_DBx__DB2__PORT EQU 12 +SCSI_Out_DBx__DB2__PRT EQU CYREG_PRT12_PRT +SCSI_Out_DBx__DB2__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SCSI_Out_DBx__DB2__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SCSI_Out_DBx__DB2__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SCSI_Out_DBx__DB2__PS EQU CYREG_PRT12_PS +SCSI_Out_DBx__DB2__SHIFT EQU 5 +SCSI_Out_DBx__DB2__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SCSI_Out_DBx__DB2__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SCSI_Out_DBx__DB2__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SCSI_Out_DBx__DB2__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SCSI_Out_DBx__DB2__SLW EQU CYREG_PRT12_SLW +SCSI_Out_DBx__DB3__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB3__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB3__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB3__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB3__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB3__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB3__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB3__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB3__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB3__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB3__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB3__INTTYPE EQU CYREG_PICU2_INTTYPE7 +SCSI_Out_DBx__DB3__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB3__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB3__MASK EQU 0x80 +SCSI_Out_DBx__DB3__PC EQU CYREG_PRT2_PC7 +SCSI_Out_DBx__DB3__PORT EQU 2 +SCSI_Out_DBx__DB3__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB3__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB3__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB3__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB3__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB3__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB3__SHIFT EQU 7 +SCSI_Out_DBx__DB3__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB4__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB4__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB4__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB4__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB4__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB4__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB4__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB4__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB4__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB4__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB4__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB4__INTTYPE EQU CYREG_PICU2_INTTYPE5 +SCSI_Out_DBx__DB4__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB4__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB4__MASK EQU 0x20 +SCSI_Out_DBx__DB4__PC EQU CYREG_PRT2_PC5 +SCSI_Out_DBx__DB4__PORT EQU 2 +SCSI_Out_DBx__DB4__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB4__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB4__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB4__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB4__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB4__SHIFT EQU 5 +SCSI_Out_DBx__DB4__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB5__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB5__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB5__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB5__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB5__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB5__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB5__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB5__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB5__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB5__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB5__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB5__INTTYPE EQU CYREG_PICU2_INTTYPE3 +SCSI_Out_DBx__DB5__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB5__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB5__MASK EQU 0x08 +SCSI_Out_DBx__DB5__PC EQU CYREG_PRT2_PC3 +SCSI_Out_DBx__DB5__PORT EQU 2 +SCSI_Out_DBx__DB5__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB5__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB5__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB5__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB5__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB5__SHIFT EQU 3 +SCSI_Out_DBx__DB5__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB6__AG EQU CYREG_PRT2_AG +SCSI_Out_DBx__DB6__AMUX EQU CYREG_PRT2_AMUX +SCSI_Out_DBx__DB6__BIE EQU CYREG_PRT2_BIE +SCSI_Out_DBx__DB6__BIT_MASK EQU CYREG_PRT2_BIT_MASK +SCSI_Out_DBx__DB6__BYP EQU CYREG_PRT2_BYP +SCSI_Out_DBx__DB6__CTL EQU CYREG_PRT2_CTL +SCSI_Out_DBx__DB6__DM0 EQU CYREG_PRT2_DM0 +SCSI_Out_DBx__DB6__DM1 EQU CYREG_PRT2_DM1 +SCSI_Out_DBx__DB6__DM2 EQU CYREG_PRT2_DM2 +SCSI_Out_DBx__DB6__DR EQU CYREG_PRT2_DR +SCSI_Out_DBx__DB6__INP_DIS EQU CYREG_PRT2_INP_DIS +SCSI_Out_DBx__DB6__INTTYPE EQU CYREG_PICU2_INTTYPE1 +SCSI_Out_DBx__DB6__LCD_COM_SEG EQU CYREG_PRT2_LCD_COM_SEG +SCSI_Out_DBx__DB6__LCD_EN EQU CYREG_PRT2_LCD_EN +SCSI_Out_DBx__DB6__MASK EQU 0x02 +SCSI_Out_DBx__DB6__PC EQU CYREG_PRT2_PC1 +SCSI_Out_DBx__DB6__PORT EQU 2 +SCSI_Out_DBx__DB6__PRT EQU CYREG_PRT2_PRT +SCSI_Out_DBx__DB6__PRTDSI__CAPS_SEL EQU CYREG_PRT2_CAPS_SEL +SCSI_Out_DBx__DB6__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT2_DBL_SYNC_IN +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL0 EQU CYREG_PRT2_OE_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OE_SEL1 EQU CYREG_PRT2_OE_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0 +SCSI_Out_DBx__DB6__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1 +SCSI_Out_DBx__DB6__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT +SCSI_Out_DBx__DB6__PS EQU CYREG_PRT2_PS +SCSI_Out_DBx__DB6__SHIFT EQU 1 +SCSI_Out_DBx__DB6__SLW EQU CYREG_PRT2_SLW +SCSI_Out_DBx__DB7__AG EQU CYREG_PRT15_AG +SCSI_Out_DBx__DB7__AMUX EQU CYREG_PRT15_AMUX +SCSI_Out_DBx__DB7__BIE EQU CYREG_PRT15_BIE +SCSI_Out_DBx__DB7__BIT_MASK EQU CYREG_PRT15_BIT_MASK +SCSI_Out_DBx__DB7__BYP EQU CYREG_PRT15_BYP +SCSI_Out_DBx__DB7__CTL EQU CYREG_PRT15_CTL +SCSI_Out_DBx__DB7__DM0 EQU CYREG_PRT15_DM0 +SCSI_Out_DBx__DB7__DM1 EQU CYREG_PRT15_DM1 +SCSI_Out_DBx__DB7__DM2 EQU CYREG_PRT15_DM2 +SCSI_Out_DBx__DB7__DR EQU CYREG_PRT15_DR +SCSI_Out_DBx__DB7__INP_DIS EQU CYREG_PRT15_INP_DIS +SCSI_Out_DBx__DB7__INTTYPE EQU CYREG_PICU15_INTTYPE5 +SCSI_Out_DBx__DB7__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +SCSI_Out_DBx__DB7__LCD_EN EQU CYREG_PRT15_LCD_EN +SCSI_Out_DBx__DB7__MASK EQU 0x20 +SCSI_Out_DBx__DB7__PC EQU CYREG_IO_PC_PRT15_PC5 +SCSI_Out_DBx__DB7__PORT EQU 15 +SCSI_Out_DBx__DB7__PRT EQU CYREG_PRT15_PRT +SCSI_Out_DBx__DB7__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +SCSI_Out_DBx__DB7__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +SCSI_Out_DBx__DB7__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +SCSI_Out_DBx__DB7__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS +SCSI_Out_DBx__DB7__SHIFT EQU 5 +SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW + +; SD_PULLUP +SD_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE0 +SD_PULLUP__0__MASK EQU 0x01 +SD_PULLUP__0__PC EQU CYREG_PRT3_PC0 +SD_PULLUP__0__PORT EQU 3 +SD_PULLUP__0__SHIFT EQU 0 +SD_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE1 +SD_PULLUP__1__MASK EQU 0x02 +SD_PULLUP__1__PC EQU CYREG_PRT3_PC1 +SD_PULLUP__1__PORT EQU 3 +SD_PULLUP__1__SHIFT EQU 1 +SD_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE2 +SD_PULLUP__2__MASK EQU 0x04 +SD_PULLUP__2__PC EQU CYREG_PRT3_PC2 +SD_PULLUP__2__PORT EQU 3 +SD_PULLUP__2__SHIFT EQU 2 +SD_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE3 +SD_PULLUP__3__MASK EQU 0x08 +SD_PULLUP__3__PC EQU CYREG_PRT3_PC3 +SD_PULLUP__3__PORT EQU 3 +SD_PULLUP__3__SHIFT EQU 3 +SD_PULLUP__AG EQU CYREG_PRT3_AG +SD_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SD_PULLUP__BIE EQU CYREG_PRT3_BIE +SD_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SD_PULLUP__BYP EQU CYREG_PRT3_BYP +SD_PULLUP__CTL EQU CYREG_PRT3_CTL +SD_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SD_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SD_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SD_PULLUP__DR EQU CYREG_PRT3_DR +SD_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SD_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SD_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SD_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SD_PULLUP__MASK EQU 0x0F +SD_PULLUP__PORT EQU 3 +SD_PULLUP__PRT EQU CYREG_PRT3_PRT +SD_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SD_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SD_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SD_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SD_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SD_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SD_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SD_PULLUP__PS EQU CYREG_PRT3_PS +SD_PULLUP__SHIFT EQU 0 +SD_PULLUP__SLW EQU CYREG_PRT3_SLW + +; SPI_PULLUP +SPI_PULLUP__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +SPI_PULLUP__0__MASK EQU 0x10 +SPI_PULLUP__0__PC EQU CYREG_PRT3_PC4 +SPI_PULLUP__0__PORT EQU 3 +SPI_PULLUP__0__SHIFT EQU 4 +SPI_PULLUP__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 +SPI_PULLUP__1__MASK EQU 0x20 +SPI_PULLUP__1__PC EQU CYREG_PRT3_PC5 +SPI_PULLUP__1__PORT EQU 3 +SPI_PULLUP__1__SHIFT EQU 5 +SPI_PULLUP__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 +SPI_PULLUP__2__MASK EQU 0x40 +SPI_PULLUP__2__PC EQU CYREG_PRT3_PC6 +SPI_PULLUP__2__PORT EQU 3 +SPI_PULLUP__2__SHIFT EQU 6 +SPI_PULLUP__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 +SPI_PULLUP__3__MASK EQU 0x80 +SPI_PULLUP__3__PC EQU CYREG_PRT3_PC7 +SPI_PULLUP__3__PORT EQU 3 +SPI_PULLUP__3__SHIFT EQU 7 +SPI_PULLUP__AG EQU CYREG_PRT3_AG +SPI_PULLUP__AMUX EQU CYREG_PRT3_AMUX +SPI_PULLUP__BIE EQU CYREG_PRT3_BIE +SPI_PULLUP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +SPI_PULLUP__BYP EQU CYREG_PRT3_BYP +SPI_PULLUP__CTL EQU CYREG_PRT3_CTL +SPI_PULLUP__DM0 EQU CYREG_PRT3_DM0 +SPI_PULLUP__DM1 EQU CYREG_PRT3_DM1 +SPI_PULLUP__DM2 EQU CYREG_PRT3_DM2 +SPI_PULLUP__DR EQU CYREG_PRT3_DR +SPI_PULLUP__INP_DIS EQU CYREG_PRT3_INP_DIS +SPI_PULLUP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +SPI_PULLUP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +SPI_PULLUP__LCD_EN EQU CYREG_PRT3_LCD_EN +SPI_PULLUP__MASK EQU 0xF0 +SPI_PULLUP__PORT EQU 3 +SPI_PULLUP__PRT EQU CYREG_PRT3_PRT +SPI_PULLUP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +SPI_PULLUP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +SPI_PULLUP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +SPI_PULLUP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +SPI_PULLUP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +SPI_PULLUP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +SPI_PULLUP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +SPI_PULLUP__PS EQU CYREG_PRT3_PS +SPI_PULLUP__SHIFT EQU 4 +SPI_PULLUP__SLW EQU CYREG_PRT3_SLW +SPI_PULLUP_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 +SPI_PULLUP_1__0__MASK EQU 0x01 +SPI_PULLUP_1__0__PC EQU CYREG_PRT12_PC0 +SPI_PULLUP_1__0__PORT EQU 12 +SPI_PULLUP_1__0__SHIFT EQU 0 +SPI_PULLUP_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 +SPI_PULLUP_1__1__MASK EQU 0x02 +SPI_PULLUP_1__1__PC EQU CYREG_PRT12_PC1 +SPI_PULLUP_1__1__PORT EQU 12 +SPI_PULLUP_1__1__SHIFT EQU 1 +SPI_PULLUP_1__AG EQU CYREG_PRT12_AG +SPI_PULLUP_1__BIE EQU CYREG_PRT12_BIE +SPI_PULLUP_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK +SPI_PULLUP_1__BYP EQU CYREG_PRT12_BYP +SPI_PULLUP_1__DM0 EQU CYREG_PRT12_DM0 +SPI_PULLUP_1__DM1 EQU CYREG_PRT12_DM1 +SPI_PULLUP_1__DM2 EQU CYREG_PRT12_DM2 +SPI_PULLUP_1__DR EQU CYREG_PRT12_DR +SPI_PULLUP_1__INP_DIS EQU CYREG_PRT12_INP_DIS +SPI_PULLUP_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +SPI_PULLUP_1__MASK EQU 0x03 +SPI_PULLUP_1__PORT EQU 12 +SPI_PULLUP_1__PRT EQU CYREG_PRT12_PRT +SPI_PULLUP_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +SPI_PULLUP_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +SPI_PULLUP_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +SPI_PULLUP_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +SPI_PULLUP_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +SPI_PULLUP_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +SPI_PULLUP_1__PS EQU CYREG_PRT12_PS +SPI_PULLUP_1__SHIFT EQU 0 +SPI_PULLUP_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG +SPI_PULLUP_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +SPI_PULLUP_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +SPI_PULLUP_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +SPI_PULLUP_1__SLW EQU CYREG_PRT12_SLW + +; Miscellaneous +BCLK__BUS_CLK__HZ EQU 64000000 +BCLK__BUS_CLK__KHZ EQU 64000 +BCLK__BUS_CLK__MHZ EQU 64 +CYDEV_BOOTLOADER_APPLICATIONS EQU 1 +CYDEV_BOOTLOADER_CHECKSUM_BASIC EQU 0 +CYDEV_BOOTLOADER_CHECKSUM_CRC EQU 1 +CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO EQU 0 +CyBtldr_Custom_Interface EQU CYDEV_BOOTLOADER_IO_COMP_CUSTOM_IO +CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY EQU 1 +CyBtldr_LAUNCHER_ONLY EQU CYDEV_BOOTLOADER_IO_COMP_LAUNCHER_ONLY +CYDEV_BOOTLOADER_IO_COMP_USBFS EQU 2 +CyBtldr_USBFS EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_BOOTLOADER_IO_COMP EQU CYDEV_BOOTLOADER_IO_COMP_USBFS +CYDEV_CHIP_DIE_LEOPARD EQU 1 +CYDEV_CHIP_DIE_PSOC4A EQU 18 +CYDEV_CHIP_DIE_PSOC5LP EQU 2 +CYDEV_CHIP_DIE_PSOC5TM EQU 3 +CYDEV_CHIP_DIE_TMA4 EQU 4 +CYDEV_CHIP_DIE_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_FM0P EQU 5 +CYDEV_CHIP_FAMILY_FM3 EQU 6 +CYDEV_CHIP_FAMILY_FM4 EQU 7 +CYDEV_CHIP_FAMILY_PSOC3 EQU 1 +CYDEV_CHIP_FAMILY_PSOC4 EQU 2 +CYDEV_CHIP_FAMILY_PSOC5 EQU 3 +CYDEV_CHIP_FAMILY_PSOC6 EQU 4 +CYDEV_CHIP_FAMILY_UNKNOWN EQU 0 +CYDEV_CHIP_FAMILY_USED EQU CYDEV_CHIP_FAMILY_PSOC5 +CYDEV_CHIP_JTAG_ID EQU 0x2E133069 +CYDEV_CHIP_MEMBER_3A EQU 1 +CYDEV_CHIP_MEMBER_4A EQU 18 +CYDEV_CHIP_MEMBER_4D EQU 13 +CYDEV_CHIP_MEMBER_4E EQU 6 +CYDEV_CHIP_MEMBER_4F EQU 19 +CYDEV_CHIP_MEMBER_4G EQU 4 +CYDEV_CHIP_MEMBER_4H EQU 17 +CYDEV_CHIP_MEMBER_4I EQU 23 +CYDEV_CHIP_MEMBER_4J EQU 14 +CYDEV_CHIP_MEMBER_4K EQU 15 +CYDEV_CHIP_MEMBER_4L EQU 22 +CYDEV_CHIP_MEMBER_4M EQU 21 +CYDEV_CHIP_MEMBER_4N EQU 10 +CYDEV_CHIP_MEMBER_4O EQU 7 +CYDEV_CHIP_MEMBER_4P EQU 20 +CYDEV_CHIP_MEMBER_4Q EQU 12 +CYDEV_CHIP_MEMBER_4R EQU 8 +CYDEV_CHIP_MEMBER_4S EQU 11 +CYDEV_CHIP_MEMBER_4T EQU 9 +CYDEV_CHIP_MEMBER_4U EQU 5 +CYDEV_CHIP_MEMBER_4V EQU 16 +CYDEV_CHIP_MEMBER_5A EQU 3 +CYDEV_CHIP_MEMBER_5B EQU 2 +CYDEV_CHIP_MEMBER_6A EQU 24 +CYDEV_CHIP_MEMBER_FM3 EQU 28 +CYDEV_CHIP_MEMBER_FM4 EQU 29 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE1 EQU 25 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE2 EQU 26 +CYDEV_CHIP_MEMBER_PDL_FM0P_TYPE3 EQU 27 +CYDEV_CHIP_MEMBER_UNKNOWN EQU 0 +CYDEV_CHIP_MEMBER_USED EQU CYDEV_CHIP_MEMBER_5B +CYDEV_CHIP_DIE_EXPECT EQU CYDEV_CHIP_MEMBER_USED +CYDEV_CHIP_DIE_ACTUAL EQU CYDEV_CHIP_DIE_EXPECT +CYDEV_CHIP_REV_LEOPARD_ES1 EQU 0 +CYDEV_CHIP_REV_LEOPARD_ES2 EQU 1 +CYDEV_CHIP_REV_LEOPARD_ES3 EQU 3 +CYDEV_CHIP_REV_LEOPARD_PRODUCTION EQU 3 +CYDEV_CHIP_REV_PSOC4A_ES0 EQU 17 +CYDEV_CHIP_REV_PSOC4A_PRODUCTION EQU 17 +CYDEV_CHIP_REV_PSOC5LP_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5LP_PRODUCTION EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES0 EQU 0 +CYDEV_CHIP_REV_PSOC5TM_ES1 EQU 1 +CYDEV_CHIP_REV_PSOC5TM_PRODUCTION EQU 1 +CYDEV_CHIP_REV_TMA4_ES EQU 17 +CYDEV_CHIP_REV_TMA4_ES2 EQU 33 +CYDEV_CHIP_REV_TMA4_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_3A_ES1 EQU 0 +CYDEV_CHIP_REVISION_3A_ES2 EQU 1 +CYDEV_CHIP_REVISION_3A_ES3 EQU 3 +CYDEV_CHIP_REVISION_3A_PRODUCTION EQU 3 +CYDEV_CHIP_REVISION_4A_ES0 EQU 17 +CYDEV_CHIP_REVISION_4A_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4D_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4E_CCG2_NO_USBPD EQU 0 +CYDEV_CHIP_REVISION_4E_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA EQU 0 +CYDEV_CHIP_REVISION_4F_PRODUCTION_256K EQU 0 +CYDEV_CHIP_REVISION_4G_ES EQU 17 +CYDEV_CHIP_REVISION_4G_ES2 EQU 33 +CYDEV_CHIP_REVISION_4G_PRODUCTION EQU 17 +CYDEV_CHIP_REVISION_4H_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4I_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4J_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4K_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4L_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4M_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4N_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4O_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4P_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4Q_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4R_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4S_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4T_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4U_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_4V_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_5A_ES0 EQU 0 +CYDEV_CHIP_REVISION_5A_ES1 EQU 1 +CYDEV_CHIP_REVISION_5A_PRODUCTION EQU 1 +CYDEV_CHIP_REVISION_5B_ES0 EQU 0 +CYDEV_CHIP_REVISION_5B_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_6A_ES EQU 17 +CYDEV_CHIP_REVISION_6A_NO_UDB EQU 33 +CYDEV_CHIP_REVISION_6A_PRODUCTION EQU 33 +CYDEV_CHIP_REVISION_FM3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_FM4_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE1_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE2_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_PDL_FM0P_TYPE3_PRODUCTION EQU 0 +CYDEV_CHIP_REVISION_USED EQU CYDEV_CHIP_REVISION_5B_PRODUCTION +CYDEV_CHIP_REV_EXPECT EQU CYDEV_CHIP_REVISION_USED +CYDEV_CONFIG_FASTBOOT_ENABLED EQU 1 +CYDEV_CONFIG_UNUSED_IO_AllowButWarn EQU 0 +CYDEV_CONFIG_UNUSED_IO EQU CYDEV_CONFIG_UNUSED_IO_AllowButWarn +CYDEV_CONFIG_UNUSED_IO_AllowWithInfo EQU 1 +CYDEV_CONFIG_UNUSED_IO_Disallowed EQU 2 +CYDEV_CONFIGURATION_COMPRESSED EQU 1 +CYDEV_CONFIGURATION_DMA EQU 0 +CYDEV_CONFIGURATION_ECC EQU 1 +CYDEV_CONFIGURATION_IMOENABLED EQU CYDEV_CONFIG_FASTBOOT_ENABLED +CYDEV_CONFIGURATION_MODE_COMPRESSED EQU 0 +CYDEV_CONFIGURATION_MODE EQU CYDEV_CONFIGURATION_MODE_COMPRESSED +CYDEV_CONFIGURATION_MODE_DMA EQU 2 +CYDEV_CONFIGURATION_MODE_UNCOMPRESSED EQU 1 +CYDEV_DEBUG_ENABLE_MASK EQU 0x20 +CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG +CYDEV_DEBUGGING_DPS_Disable EQU 3 +CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1 +CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0 +CYDEV_DEBUGGING_DPS_SWD EQU 2 +CYDEV_DEBUGGING_DPS_SWD_SWV EQU 6 +CYDEV_DEBUGGING_DPS EQU CYDEV_DEBUGGING_DPS_SWD_SWV +CYDEV_DEBUGGING_ENABLE EQU 1 +CYDEV_DEBUGGING_XRES EQU 0 +CYDEV_DMA_CHANNELS_AVAILABLE EQU 24 +CYDEV_ECC_ENABLE EQU 0 +CYDEV_HEAP_SIZE EQU 0x0800 +CYDEV_INSTRUCT_CACHE_ENABLED EQU 1 +CYDEV_INTR_RISING EQU 0x00000000 +CYDEV_IS_EXPORTING_CODE EQU 0 +CYDEV_IS_IMPORTING_CODE EQU 0 +CYDEV_PROJ_TYPE EQU 1 +CYDEV_PROJ_TYPE_BOOTLOADER EQU 1 +CYDEV_PROJ_TYPE_LAUNCHER EQU 5 +CYDEV_PROJ_TYPE_LOADABLE EQU 2 +CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER EQU 4 +CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER EQU 3 +CYDEV_PROJ_TYPE_STANDARD EQU 0 +CYDEV_PROTECTION_ENABLE EQU 0 +CYDEV_STACK_SIZE EQU 0x2000 +CYDEV_USB_CLK_OSC_LOCKING_ENABLED_AT_PWR_UP EQU 1 +CYDEV_USE_BUNDLED_CMSIS EQU 1 +CYDEV_VARIABLE_VDDA EQU 0 +CYDEV_VDDA_MV EQU 5000 +CYDEV_VDDD_MV EQU 5000 +CYDEV_VDDIO0_MV EQU 5000 +CYDEV_VDDIO1_MV EQU 5000 +CYDEV_VDDIO2_MV EQU 5000 +CYDEV_VDDIO3_MV EQU 3000 +CYDEV_VIO0_MV EQU 5000 +CYDEV_VIO1_MV EQU 5000 +CYDEV_VIO2_MV EQU 5000 +CYDEV_VIO3_MV EQU 3000 +CYIPBLOCK_ARM_CM3_VERSION EQU 0 +CYIPBLOCK_P3_ANAIF_VERSION EQU 0 +CYIPBLOCK_P3_CAPSENSE_VERSION EQU 0 +CYIPBLOCK_P3_COMP_VERSION EQU 0 +CYIPBLOCK_P3_DMA_VERSION EQU 0 +CYIPBLOCK_P3_DRQ_VERSION EQU 0 +CYIPBLOCK_P3_EMIF_VERSION EQU 0 +CYIPBLOCK_P3_I2C_VERSION EQU 0 +CYIPBLOCK_P3_LCD_VERSION EQU 0 +CYIPBLOCK_P3_LPF_VERSION EQU 0 +CYIPBLOCK_P3_PM_VERSION EQU 0 +CYIPBLOCK_P3_TIMER_VERSION EQU 0 +CYIPBLOCK_P3_USB_VERSION EQU 0 +CYIPBLOCK_P3_VIDAC_VERSION EQU 0 +CYIPBLOCK_P3_VREF_VERSION EQU 0 +CYIPBLOCK_S8_GPIO_VERSION EQU 0 +CYIPBLOCK_S8_IRQ_VERSION EQU 0 +CYIPBLOCK_S8_SAR_VERSION EQU 0 +CYIPBLOCK_S8_SIO_VERSION EQU 0 +CYIPBLOCK_S8_UDB_VERSION EQU 0 +DMA_CHANNELS_USED__MASK0 EQU 0x00000000 +CYDEV_BOOTLOADER_ENABLE EQU 1 + ENDIF + END diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c new file mode 100644 index 0000000..5cb139f --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cymetadata.c @@ -0,0 +1,126 @@ +/******************************************************************************* +* File Name: cymetadata.c +* +* PSoC Creator 4.2 +* +* Description: +* This file defines all extra memory spaces that need to be included. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + + +#include "stdint.h" + + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_LOADER_META_SECTION +#define CY_LOADER_META_SECTION __attribute__ ((__section__(".cyloadermeta"), used)) +#endif +CY_LOADER_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyloadermeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_loader[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x51u, 0x01u, 0x00u, 0x01u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CONFIG_ECC_SECTION +#define CY_CONFIG_ECC_SECTION __attribute__ ((__section__(".cyconfigecc"), used)) +#endif +CY_CONFIG_ECC_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyconfigecc" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_configecc[] = { + 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_CUST_NVL_SECTION +#define CY_CUST_NVL_SECTION __attribute__ ((__section__(".cycustnvl"), used)) +#endif +CY_CUST_NVL_SECTION +#elif defined(__ICCARM__) +#pragma location=".cycustnvl" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_custnvl[] = { + 0x80u, 0x80u, 0x40u, 0x05u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_WO_NVL_SECTION +#define CY_WO_NVL_SECTION __attribute__ ((__section__(".cywolatch"), used)) +#endif +CY_WO_NVL_SECTION +#elif defined(__ICCARM__) +#pragma location=".cywolatch" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_wonvl[] = { + 0xBCu, 0x90u, 0xACu, 0xAFu +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_FLASH_PROT_SECTION +#define CY_FLASH_PROT_SECTION __attribute__ ((__section__(".cyflashprotect"), used)) +#endif +CY_FLASH_PROT_SECTION +#elif defined(__ICCARM__) +#pragma location=".cyflashprotect" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_meta_flashprotect[] = { + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, + 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u +}; + +#if defined(__GNUC__) || defined(__ARMCC_VERSION) +#ifndef CY_META_SECTION +#define CY_META_SECTION __attribute__ ((__section__(".cymeta"), used)) +#endif +CY_META_SECTION +#elif defined(__ICCARM__) +#pragma location=".cymeta" +#else +#error "Unsupported toolchain" +#endif +const uint8_t cy_metadata[] = { + 0x00u, 0x01u, 0x2Eu, 0x13u, 0x30u, 0x69u, 0x00u, 0x01u, + 0x00u, 0x00u, 0x00u, 0x00u +}; diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h new file mode 100644 index 0000000..b7525d1 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cypins.h @@ -0,0 +1,341 @@ +/******************************************************************************* +* File Name: cypins.h +* Version 4.20 +* +* Description: +* This file contains the function prototypes and constants used for a port/pin +* in access and control. +* +* Note: +* Documentation of the API's in this file is located in the +* System Reference Guide provided with PSoC Creator. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYPINS_H) +#define CY_BOOT_CYPINS_H + +#include "cyfitter.h" +#include "cytypes.h" + + +/************************************** +* API Parameter Constants +**************************************/ + +#define CY_PINS_PC_DRIVE_MODE_SHIFT (0x01u) +#define CY_PINS_PC_DRIVE_MODE_MASK ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_0 ((uint8)(0x00u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_1 ((uint8)(0x01u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_2 ((uint8)(0x02u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_3 ((uint8)(0x03u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_4 ((uint8)(0x04u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_5 ((uint8)(0x05u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_6 ((uint8)(0x06u << CY_PINS_PC_DRIVE_MODE_SHIFT)) +#define CY_PINS_PC_DRIVE_MODE_7 ((uint8)(0x07u << CY_PINS_PC_DRIVE_MODE_SHIFT)) + + +/* SetPinDriveMode */ +#define CY_PINS_DM_ALG_HIZ (CY_PINS_PC_DRIVE_MODE_0) +#define CY_PINS_DM_DIG_HIZ (CY_PINS_PC_DRIVE_MODE_1) +#define CY_PINS_DM_RES_UP (CY_PINS_PC_DRIVE_MODE_2) +#define CY_PINS_DM_RES_DWN (CY_PINS_PC_DRIVE_MODE_3) +#define CY_PINS_DM_OD_LO (CY_PINS_PC_DRIVE_MODE_4) +#define CY_PINS_DM_OD_HI (CY_PINS_PC_DRIVE_MODE_5) +#define CY_PINS_DM_STRONG (CY_PINS_PC_DRIVE_MODE_6) +#define CY_PINS_DM_RES_UPDWN (CY_PINS_PC_DRIVE_MODE_7) + + +/************************************** +* Register Constants +**************************************/ + +/* Port Pin Configuration Register */ +#define CY_PINS_PC_DATAOUT (0x01u) +#define CY_PINS_PC_PIN_FASTSLEW (0xBFu) +#define CY_PINS_PC_PIN_SLOWSLEW (0x40u) +#define CY_PINS_PC_PIN_STATE (0x10u) +#define CY_PINS_PC_BIDIR_EN (0x20u) +#define CY_PINS_PC_SLEW (0x40u) +#define CY_PINS_PC_BYPASS (0x80u) + + +/************************************** +* Pin API Macros +**************************************/ + +/******************************************************************************* +* Macro Name: CyPins_ReadPin +******************************************************************************** +* +* Summary: +* Reads the current value on the pin (pin state, PS). +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* Pin state +* 0: Logic low value +* Non-0: Logic high value +* +*******************************************************************************/ +#define CyPins_ReadPin(pinPC) ( *(reg8 *)(pinPC) & CY_PINS_PC_PIN_STATE ) + + +/******************************************************************************* +* Macro Name: CyPins_SetPin +******************************************************************************** +* +* Summary: +* Set the output value for the pin (data register, DR) to a logic high. +* +* Note that this only has an effect for pins configured as software pins that +* are not driven by hardware. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* Parameters: +* pinPC: Port pin configuration register (uint16). +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPin(pinPC) ( *(reg8 *)(pinPC) |= CY_PINS_PC_DATAOUT) + + +/******************************************************************************* +* Macro Name: CyPins_ClearPin +******************************************************************************** +* +* Summary: +* This macro sets the state of the specified pin to 0. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_ClearPin(pinPC) ( *(reg8 *)(pinPC) &= ((uint8)(~CY_PINS_PC_DATAOUT))) + + +/******************************************************************************* +* Macro Name: CyPins_SetPinDriveMode +******************************************************************************** +* +* Summary: +* Sets the drive mode for the pin (DM). +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* mode: Desired drive mode +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SetPinDriveMode(pinPC, mode) \ + ( *(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & ((uint8)(~CY_PINS_PC_DRIVE_MODE_MASK))) | \ + ((mode) & CY_PINS_PC_DRIVE_MODE_MASK)) + + +/******************************************************************************* +* Macro Name: CyPins_ReadPinDriveMode +******************************************************************************** +* +* Summary: +* Reads the drive mode for the pin (DM). +* +* Parameters: +* pinPC: Port pin configuration register (uint16) +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* mode: The current drive mode for the pin +* +* Define Source +* PIN_DM_ALG_HIZ Analog HiZ +* PIN_DM_DIG_HIZ Digital HiZ +* PIN_DM_RES_UP Resistive pull up +* PIN_DM_RES_DWN Resistive pull down +* PIN_DM_OD_LO Open drain - drive low +* PIN_DM_OD_HI Open drain - drive high +* PIN_DM_STRONG Strong CMOS Output +* PIN_DM_RES_UPDWN Resistive pull up/down +* +*******************************************************************************/ +#define CyPins_ReadPinDriveMode(pinPC) (*(reg8 *)(pinPC) & CY_PINS_PC_DRIVE_MODE_MASK) + + +/******************************************************************************* +* Macro Name: CyPins_FastSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to fast the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_FastSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) & CY_PINS_PC_PIN_FASTSLEW)) + + +/******************************************************************************* +* Macro Name: CyPins_SlowSlew +******************************************************************************** +* +* Summary: +* Set the slew rate for the pin to slow the edge rate. +* Note that this only applies for pins in strong output drive modes, +* not to resistive drive modes. +* +* The macro operation is not atomic. It is not guaranteed that shared register +* will remain uncorrupted during simultaneous read-modify-write operations +* performed by two threads (main and interrupt threads). To guarantee data +* integrity in such cases, the macro should be invoked while the specific +* interrupt is disabled or within critical section (all interrupts are +* disabled). +* +* Parameters: +* pinPC: address of a Pin Configuration register. +* #defines for each pin on a chip are provided in the cydevice_trm.h file +* in the form: +* CYREG_PRTx_PCy +* +* where x is a port number 0 - 15 and y is a pin number 0 - 7 +* +* Return: +* None +* +*******************************************************************************/ +#define CyPins_SlowSlew(pinPC) (*(reg8 *)(pinPC) = (*(reg8 *)(pinPC) | CY_PINS_PC_PIN_SLOWSLEW)) + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used. +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define PC_DRIVE_MODE_SHIFT (CY_PINS_PC_DRIVE_MODE_SHIFT) +#define PC_DRIVE_MODE_MASK (CY_PINS_PC_DRIVE_MODE_MASK) +#define PC_DRIVE_MODE_0 (CY_PINS_PC_DRIVE_MODE_0) +#define PC_DRIVE_MODE_1 (CY_PINS_PC_DRIVE_MODE_1) +#define PC_DRIVE_MODE_2 (CY_PINS_PC_DRIVE_MODE_2) +#define PC_DRIVE_MODE_3 (CY_PINS_PC_DRIVE_MODE_3) +#define PC_DRIVE_MODE_4 (CY_PINS_PC_DRIVE_MODE_4) +#define PC_DRIVE_MODE_5 (CY_PINS_PC_DRIVE_MODE_5) +#define PC_DRIVE_MODE_6 (CY_PINS_PC_DRIVE_MODE_6) +#define PC_DRIVE_MODE_7 (CY_PINS_PC_DRIVE_MODE_7) + +#define PIN_DM_ALG_HIZ (CY_PINS_DM_ALG_HIZ) +#define PIN_DM_DIG_HIZ (CY_PINS_DM_DIG_HIZ) +#define PIN_DM_RES_UP (CY_PINS_DM_RES_UP) +#define PIN_DM_RES_DWN (CY_PINS_DM_RES_DWN) +#define PIN_DM_OD_LO (CY_PINS_DM_OD_LO) +#define PIN_DM_OD_HI (CY_PINS_DM_OD_HI) +#define PIN_DM_STRONG (CY_PINS_DM_STRONG) +#define PIN_DM_RES_UPDWN (CY_PINS_DM_RES_UPDWN) + +#define PC_DATAOUT (CY_PINS_PC_DATAOUT) +#define PC_PIN_FASTSLEW (CY_PINS_PC_PIN_FASTSLEW) +#define PC_PIN_SLOWSLEW (CY_PINS_PC_PIN_SLOWSLEW) +#define PC_PIN_STATE (CY_PINS_PC_PIN_STATE) +#define PC_BIDIR_EN (CY_PINS_PC_BIDIR_EN) +#define PC_SLEW (CY_PINS_PC_SLEW) +#define PC_BYPASS (CY_PINS_PC_BYPASS) + +#endif /* (CY_BOOT_CYPINS_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h new file mode 100644 index 0000000..528f949 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cytypes.h @@ -0,0 +1,560 @@ +/******************************************************************************* +* FILENAME: cytypes.h +* Version 4.20 +* +* Description: +* CyTypes provides register access macros and approved types for use in +* firmware. +* +* Note: +* Due to endiannesses of the hardware and some compilers, the register +* access macros for big endian compilers use some library calls to arrange +* data the correct way. +* +* Register Access macros and functions perform their operations on an +* input of the type pointer to void. The arguments passed to it should be +* pointers to the type associated with the register size. +* (i.e. a "uint8 *" shouldn't be passed to obtain a 16-bit register value) +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_BOOT_CYTYPES_H) +#define CY_BOOT_CYTYPES_H + +#if defined(__C51__) + #include +#endif /* (__C51__) */ + +/* ARM and C99 or later */ +#if defined(__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) + #include +#endif /* (__GNUC__) || defined(__ARMCC_VERSION) || (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) */ + +#include "cyfitter.h" + + +#if defined( __ICCARM__ ) + /* Suppress warning for multiple volatile variables in an expression. */ + /* This is common in component code and usage is not order dependent. */ + #pragma diag_suppress=Pa082 +#endif /* defined( __ICCARM__ ) */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + + +/******************************************************************************* +* FAMILY encodes the overall architectural family +*******************************************************************************/ +#define CY_PSOC3 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) +#define CY_PSOC4 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) +#define CY_PSOC5 (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5) + + +/******************************************************************************* +* MEMBER encodes both the family and the detailed architecture +*******************************************************************************/ +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4_4000 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) +#else + #define CY_PSOC4_4000 (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4D */ + +#define CY_PSOC4_4100 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#define CY_PSOC4_4200 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) + +#ifdef CYDEV_CHIP_MEMBER_4F + #define CY_PSOC4_4100BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) + #define CY_PSOC4_4200BL (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4F) +#else + #define CY_PSOC4_4100BL (0u != 0u) + #define CY_PSOC4_4200BL (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_4F */ + + +/******************************************************************************* +* IP blocks +*******************************************************************************/ +#if (CY_PSOC4) + + /* Using SRSSv2 or SRS-Lite */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_SRSSV2 (0u == 0u) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #else + #define CY_IP_SRSSV2 (0u != 0u) + #define CY_IP_SRSSLT (!CY_IP_SRSSV2) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_CPUSSV2 (0u != 0u) + #define CY_IP_CPUSS (0u == 0u) + #else + #define CY_IP_CPUSSV2 (0u != 0u) + #define CY_IP_CPUSS (!CY_IP_CPUSSV2) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + /* Product uses FLASH-Lite or regular FLASH */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_FMLT (0u != 0u) /* FLASH-Lite */ + #define CY_IP_FM (!CY_IP_FMLT) /* Regular FLASH */ + #else + #define CY_IP_FMLT (-1u != 0u) + #define CY_IP_FM (!CY_IP_FMLT) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + /* Number of interrupt request inputs to CM0 */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_INT_NR (32u) + #else + #define CY_IP_INT_NR (-1u) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_FLASH_MACROS (1u) + #else + #define CY_IP_FLASH_MACROS (-1u) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + + /* Number of Flash macros used in the device (0, 1 or 2) */ + #if (CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_BLESS (0u != 0u) + #else + #define CY_IP_BLESS (0u != 0u) + #endif /* (CY_PSOC4_4100 || CY_PSOC4_4200) */ + + /* Watch Crystal Oscillator (WCO) is present (32kHz) */ + #if (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) + #define CY_IP_WCO (0u != 0u) + #elif CY_IP_BLESS || defined (CYIPBLOCK_s8swco_VERSION) + #define CY_IP_WCO (0u == 0u) + #elif (CY_IP_SRSSV2) + #define CY_IP_WCO (-1u) + #else + #define CY_IP_WCO (0u != 0u) + #endif /* (CY_PSOC4_4000 || CY_PSOC4_4100 || CY_PSOC4_4200) */ + +#endif /* (CY_PSOC4) */ + + +/******************************************************************************* +* The components version defines. Available started from cy_boot 4.20 +* Use the following construction in order to identify cy_boot version: +* (defined(CY_BOOT_VERSION) && CY_BOOT_VERSION >= CY_BOOT_4_20) +*******************************************************************************/ +#define CY_BOOT_4_20 (420u) +#define CY_BOOT_VERSION (CY_BOOT_4_20) + + +/******************************************************************************* +* Base Types. Acceptable types from MISRA-C specifying signedness and size. +*******************************************************************************/ +typedef unsigned char uint8; +typedef unsigned short uint16; +typedef unsigned long uint32; +typedef signed char int8; +typedef signed short int16; +typedef signed long int32; +typedef float float32; + +#if(!CY_PSOC3) + + typedef double float64; + typedef long long int64; + typedef unsigned long long uint64; + +#endif /* (!CY_PSOC3) */ + +/* Signed or unsigned depending on compiler selection */ +typedef char char8; + + +/******************************************************************************* +* Memory address functions prototypes +*******************************************************************************/ +#if(CY_PSOC3) + + /*************************************************************************** + * Prototypes for absolute memory address functions (cymem.a51) with built-in + * endian conversion. These functions should be called through the + * CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros. + ***************************************************************************/ + extern uint8 cyread8 (const volatile void far *addr); + extern void cywrite8 (volatile void far *addr, uint8 value); + + extern uint16 cyread16 (const volatile void far *addr); + extern uint16 cyread16_nodpx(const volatile void far *addr); + + extern void cywrite16 (volatile void far *addr, uint16 value); + extern void cywrite16_nodpx(volatile void far *addr, uint16 value); + + extern uint32 cyread24 (const volatile void far *addr); + extern uint32 cyread24_nodpx(const volatile void far *addr); + + extern void cywrite24 (volatile void far *addr, uint32 value); + extern void cywrite24_nodpx(volatile void far *addr, uint32 value); + + extern uint32 cyread32 (const volatile void far *addr); + extern uint32 cyread32_nodpx(const volatile void far *addr); + + extern void cywrite32 (volatile void far *addr, uint32 value); + extern void cywrite32_nodpx(volatile void far *addr, uint32 value); + + + /*************************************************************************** + * Memory access routines from cymem.a51 for the generated device + * configuration code. These functions may be subject to change in future + * revisions of the cy_boot component and they are not available for all + * devices. Most code should use memset or memcpy instead. + ***************************************************************************/ + void cymemzero(void far *addr, uint16 size); + void cyconfigcpy(uint16 size, const void far *src, void far *dest) large; + void cyconfigcpycode(uint16 size, const void code *src, void far *dest); + + #define CYCONFIGCPY_DECLARED (1) + +#else + + /* Prototype for function to set 24-bit register. Located at cyutils.c */ + extern void CySetReg24(uint32 volatile * addr, uint32 value); + + #if(CY_PSOC4) + + extern uint32 CyGetReg24(uint32 const volatile * addr); + + #endif /* (CY_PSOC4) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Memory model definitions. To allow code to be 8051-ARM agnostic. +*******************************************************************************/ +#if(CY_PSOC3) + + #define CYBDATA bdata + #define CYBIT bit + #define CYCODE code + #define CYCOMPACT compact + #define CYDATA data + #define CYFAR far + #define CYIDATA idata + #define CYLARGE large + #define CYPDATA pdata + #define CYREENTRANT reentrant + #define CYSMALL small + #define CYXDATA xdata + #define XDATA xdata + + #define CY_NOINIT + +#else + + #define CYBDATA + #define CYBIT uint8 + #define CYCODE + #define CYCOMPACT + #define CYDATA + #define CYFAR + #define CYIDATA + #define CYLARGE + #define CYPDATA + #define CYREENTRANT + #define CYSMALL + #define CYXDATA + #define XDATA + + #if defined(__ARMCC_VERSION) + + #define CY_NOINIT __attribute__ ((section(".noinit"), zero_init)) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + + /* Specifies a minimum alignment (in bytes) for variables of the + * specified type. + */ + #define CY_ALIGN(align) __align(align) + + + /* Attached to an enum, struct, or union type definition, specified that + * the minimum required memory be used to represent the type. + */ + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE __inline + #elif defined (__GNUC__) + + #define CY_NOINIT __attribute__ ((section(".noinit"))) + #define CY_NORETURN __attribute__ ((noreturn)) + #define CY_SECTION(name) __attribute__ ((section(name))) + #define CY_ALIGN(align) __attribute__ ((aligned(align))) + #define CY_PACKED + #define CY_PACKED_ATTR __attribute__ ((packed)) + #define CY_INLINE inline + #elif defined (__ICCARM__) + + #define CY_NOINIT __no_init + #define CY_NORETURN __noreturn + #define CY_PACKED __packed + #define CY_PACKED_ATTR + #define CY_INLINE inline + #endif /* (__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +#if(CY_PSOC3) + + /* 8051 naturally returns 8 bit value. */ + typedef unsigned char cystatus; + +#else + + /* ARM naturally returns 32 bit value. */ + typedef unsigned long cystatus; + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Hardware Register Types. +*******************************************************************************/ +typedef volatile uint8 CYXDATA reg8; +typedef volatile uint16 CYXDATA reg16; +typedef volatile uint32 CYXDATA reg32; + + +/******************************************************************************* +* Interrupt Types and Macros +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_ISR(FuncName) void FuncName (void) interrupt 0 + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (CYCODE * cyisraddress)(void); + +#else + + #define CY_ISR(FuncName) void FuncName (void) + #define CY_ISR_PROTO(FuncName) void FuncName (void) + typedef void (* cyisraddress)(void); + + #if defined (__ICCARM__) + typedef union { cyisraddress __fun; void * __ptr; } intvec_elem; + #endif /* defined (__ICCARM__) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* Register Access +*******************************************************************************/ +#if(CY_PSOC3) + + + /******************************************************************************* + * KEIL for the 8051 is a big endian compiler This causes problems as the on chip + * registers are little endian. Byte swapping for two and four byte registers is + * implemented in the functions below. This will require conditional compilation + * of function prototypes in the code. + *******************************************************************************/ + + /* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */ + + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr)) + #define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value) + + #define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value) + + #define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr)) + #define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value) + + /* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */ + #define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr)) + #define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr)) + #define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr)) + #define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value) + + #define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr)) + #define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value) + +#else + + /* 8, 16, 24 and 32-bit register access macros */ + #define CY_GET_REG8(addr) (*((const reg8 *)(addr))) + #define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value)) + + #define CY_GET_REG16(addr) (*((const reg16 *)(addr))) + #define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value)) + + + #define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value)) + #if(CY_PSOC4) + #define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr)) + #else + #define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu) + #endif /* (CY_PSOC4) */ + + + #define CY_GET_REG32(addr) (*((const reg32 *)(addr))) + #define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value)) + + + /* To allow code to be 8051-ARM agnostic. */ + #define CY_GET_XTND_REG8(addr) CY_GET_REG8(addr) + #define CY_SET_XTND_REG8(addr, value) CY_SET_REG8(addr, value) + + #define CY_GET_XTND_REG16(addr) CY_GET_REG16(addr) + #define CY_SET_XTND_REG16(addr, value) CY_SET_REG16(addr, value) + + #define CY_GET_XTND_REG24(addr) CY_GET_REG24(addr) + #define CY_SET_XTND_REG24(addr, value) CY_SET_REG24(addr, value) + + #define CY_GET_XTND_REG32(addr) CY_GET_REG32(addr) + #define CY_SET_XTND_REG32(addr, value) CY_SET_REG32(addr, value) + +#endif /* (CY_PSOC3) */ + + + +/******************************************************************************* +* Data manipulation defines +*******************************************************************************/ + +/* Get 8 bits of 16 bit value. */ +#define LO8(x) ((uint8) ((x) & 0xFFu)) +#define HI8(x) ((uint8) ((uint16)(x) >> 8)) + +/* Get 16 bits of 32 bit value. */ +#define LO16(x) ((uint16) ((x) & 0xFFFFu)) +#define HI16(x) ((uint16) ((uint32)(x) >> 16)) + +/* Swap the byte ordering of 32 bit value */ +#define CYSWAP_ENDIAN32(x) \ + ((uint32)(((x) >> 24) | (((x) & 0x00FF0000u) >> 8) | (((x) & 0x0000FF00u) << 8) | ((x) << 24))) + +/* Swap the byte ordering of 16 bit value */ +#define CYSWAP_ENDIAN16(x) ((uint16)(((x) << 8) | ((x) >> 8))) + + +/******************************************************************************* +* Defines the standard return values used in PSoC content. A function is +* not limited to these return values but can use them when returning standard +* error values. Return values can be overloaded if documented in the function +* header. On the 8051 a function can use a larger return type but still use the +* defined return codes. +* +* Zero is successful, all other values indicate some form of failure. 1 - 0x7F - +* standard defined values; 0x80 - ... - user or content defined values. +*******************************************************************************/ +#define CYRET_SUCCESS (0x00u) /* Successful */ +#define CYRET_BAD_PARAM (0x01u) /* One or more invalid parameters */ +#define CYRET_INVALID_OBJECT (0x02u) /* Invalid object specified */ +#define CYRET_MEMORY (0x03u) /* Memory related failure */ +#define CYRET_LOCKED (0x04u) /* Resource lock failure */ +#define CYRET_EMPTY (0x05u) /* No more objects available */ +#define CYRET_BAD_DATA (0x06u) /* Bad data received (CRC or other error check) */ +#define CYRET_STARTED (0x07u) /* Operation started, but not necessarily completed yet */ +#define CYRET_FINISHED (0x08u) /* Operation completed */ +#define CYRET_CANCELED (0x09u) /* Operation canceled */ +#define CYRET_TIMEOUT (0x10u) /* Operation timed out */ +#define CYRET_INVALID_STATE (0x11u) /* Operation not setup or is in an improper state */ +#define CYRET_UNKNOWN ((cystatus) 0xFFFFFFFFu) /* Unknown failure */ + + +/******************************************************************************* +* Intrinsic Defines: Processor NOP instruction +*******************************************************************************/ +#if(CY_PSOC3) + + #define CY_NOP _nop_() + +#else + + #if defined(__ARMCC_VERSION) + + /* RealView */ + #define CY_NOP __nop() + + #else + + /* GCC */ + #define CY_NOP __asm("NOP\n") + + #endif /* defined(__ARMCC_VERSION) */ + +#endif /* (CY_PSOC3) */ + + +/******************************************************************************* +* The following code is OBSOLETE and must not be used starting from cy_boot 3.10 +* +* If the obsoleted macro definitions intended for use in the application use the +* following scheme, redefine your own versions of these definitions: +* #ifdef +* #undef +* #define () +* #endif +* +* Note: Redefine obsoleted macro definitions with caution. They might still be +* used in the application and their modification might lead to unexpected +* consequences. +*******************************************************************************/ +#define CY_UDB_V0 (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#define CY_UDB_V1 (!CY_UDB_V0) +#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A) +#ifdef CYDEV_CHIP_MEMBER_4D + #define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D) + #define CY_PSOC4SF (CY_PSOC4D) +#else + #define CY_PSOC4D (0u != 0u) + #define CY_PSOC4SF (CY_PSOC4D) +#endif /* CYDEV_CHIP_MEMBER_4D */ +#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A) +#ifdef CYDEV_CHIP_MEMBER_5B + #define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B) +#else + #define CY_PSOC5LP (0u != 0u) +#endif /* CYDEV_CHIP_MEMBER_5B */ + +#if (!CY_PSOC4) + + /* Device is PSoC 3 and the revision is ES2 or earlier */ + #define CY_PSOC3_ES2 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_3A_ES2)) + + /* Device is PSoC 3 and the revision is ES3 or later */ + #define CY_PSOC3_ES3 ((CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_3A) && \ + (CYDEV_CHIP_REVISION_USED >= CYDEV_CHIP_REVISION_3A_ES3)) + + /* Device is PSoC 5 and the revision is ES1 or earlier */ + #define CY_PSOC5_ES1 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED <= CYDEV_CHIP_REVISION_5A_ES1)) + + /* Device is PSoC 5 and the revision is ES2 or later */ + #define CY_PSOC5_ES2 (CY_PSOC5A && \ + (CYDEV_CHIP_REVISION_USED > CYDEV_CHIP_REVISION_5A_ES1)) + +#endif /* (!CY_PSOC4) */ + +#endif /* CY_BOOT_CYTYPES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c new file mode 100644 index 0000000..dcfe346 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/cyutils.c @@ -0,0 +1,87 @@ +/******************************************************************************* +* FILENAME: cyutils.c +* Version 4.20 +* +* Description: +* CyUtils provides a function to handle 24-bit value writes. +* +******************************************************************************** +* Copyright 2008-2014, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" + +#if (!CY_PSOC3) + + /*************************************************************************** + * Function Name: CySetReg24 + **************************************************************************** + * + * Summary: + * Writes a 24-bit value to the specified register. + * + * Parameters: + * addr : the address where data must be written. + * value: the data that must be written. + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + void CySetReg24(uint32 volatile * addr, uint32 value) + { + uint8 volatile *tmpAddr; + + tmpAddr = (uint8 volatile *) addr; + + tmpAddr[0u] = (uint8) value; + tmpAddr[1u] = (uint8) (value >> 8u); + tmpAddr[2u] = (uint8) (value >> 16u); + } + + + #if(CY_PSOC4) + + /*************************************************************************** + * Function Name: CyGetReg24 + **************************************************************************** + * + * Summary: + * Reads the 24-bit value from the specified register. + * + * Parameters: + * addr : the address where data must be read. + * + * Return: + * None + * + * Reentrant: + * No + * + ***************************************************************************/ + uint32 CyGetReg24(uint32 const volatile * addr) + { + uint8 const volatile *tmpAddr; + uint32 value; + + tmpAddr = (uint8 const volatile *) addr; + + value = (uint32) tmpAddr[0u]; + value |= ((uint32) tmpAddr[1u] << 8u ); + value |= ((uint32) tmpAddr[2u] << 16u); + + return(value); + } + + #endif /*(CY_PSOC4)*/ + +#endif /* (!CY_PSOC3) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/eeprom.hex new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/exported_symbols.txt b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/exported_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h new file mode 100644 index 0000000..ef7e5ab --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/project.h @@ -0,0 +1,62 @@ +/******************************************************************************* +* File Name: project.h +* +* PSoC Creator 4.2 +* +* Description: +* It contains references to all generated header files and should not be modified. +* This file is automatically generated by PSoC Creator. +* +******************************************************************************** +* Copyright (c) 2007-2018 Cypress Semiconductor. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +********************************************************************************/ + +#include "cyfitter_cfg.h" +#include "cydevice.h" +#include "cydevice_trm.h" +#include "cyfitter.h" +#include "cydisabledsheets.h" +#include "USBFS.h" +#include "USBFS_audio.h" +#include "USBFS_cdc.h" +#include "USBFS_hid.h" +#include "USBFS_midi.h" +#include "USBFS_pvt.h" +#include "BL.h" +#include "BL_PVT.h" +#include "SCSI_Out_DBx_aliases.h" +#include "SCSI_Out_aliases.h" +#include "SD_PULLUP_aliases.h" +#include "SD_PULLUP.h" +#include "LED_aliases.h" +#include "LED.h" +#include "TERM_EN_aliases.h" +#include "TERM_EN.h" +#include "BOOTLDR_aliases.h" +#include "BOOTLDR.h" +#include "SPI_PULLUP_aliases.h" +#include "SPI_PULLUP.h" +#include "SPI_PULLUP_1_aliases.h" +#include "SPI_PULLUP_1.h" +#include "USBFS_Dm_aliases.h" +#include "USBFS_Dm.h" +#include "USBFS_Dp_aliases.h" +#include "USBFS_Dp.h" +#include "core_cm3_psoc5.h" +#include "core_cm3.h" +#include "CyDmac.h" +#include "CyFlash.h" +#include "CyLib.h" +#include "cypins.h" +#include "cyPm.h" +#include "CySpc.h" +#include "cytypes.h" +#include "core_cmFunc.h" +#include "core_cmInstr.h" +#include "cy_em_eeprom.h" + +/*[]*/ + diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/protect.hex b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/protect.hex new file mode 100644 index 0000000..deab42f --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/protect.hex @@ -0,0 +1,3 @@ +:4000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000C0 +:400040000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080 +:00000001FF diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/renamed_symbols.txt b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoC5/renamed_symbols.txt new file mode 100644 index 0000000..e69de29 diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml new file mode 100644 index 0000000..e956f2c --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/Generated_Source/PSoCCreatorExportIDE.xml @@ -0,0 +1,155 @@ + + + + + + + + + + + + + + + + + + + + + + USB_Bootloader.svd + + + .\Generated_Source\PSoC5\cm3gcc.ld + .\Generated_Source\PSoC5\Cm3RealView.scat + .\Generated_Source\PSoC5\Cm3Iar.icf + + + + + .\main.c + + + + + .\Generated_Source\PSoC5\cyfitter_cfg.h + .\Generated_Source\PSoC5\cyfitter_cfg.c + .\Generated_Source\PSoC5\cymetadata.c + .\Generated_Source\PSoC5\cydevice.h + .\Generated_Source\PSoC5\cydevicegnu.inc + .\Generated_Source\PSoC5\cydevicerv.inc + .\Generated_Source\PSoC5\cydeviceiar.inc + .\Generated_Source\PSoC5\cydevice_trm.h + .\Generated_Source\PSoC5\cydevicegnu_trm.inc + .\Generated_Source\PSoC5\cydevicerv_trm.inc + .\Generated_Source\PSoC5\cydeviceiar_trm.inc + .\Generated_Source\PSoC5\cyfittergnu.inc + .\Generated_Source\PSoC5\cyfitterrv.inc + .\Generated_Source\PSoC5\cyfitteriar.inc + .\Generated_Source\PSoC5\cyfitter.h + .\Generated_Source\PSoC5\cydisabledsheets.h + .\Generated_Source\PSoC5\USBFS.c + .\Generated_Source\PSoC5\USBFS.h + .\Generated_Source\PSoC5\USBFS_audio.c + .\Generated_Source\PSoC5\USBFS_audio.h + .\Generated_Source\PSoC5\USBFS_boot.c + .\Generated_Source\PSoC5\USBFS_cdc.c + .\Generated_Source\PSoC5\USBFS_cdc.h + .\Generated_Source\PSoC5\USBFS_cls.c + .\Generated_Source\PSoC5\USBFS_descr.c + .\Generated_Source\PSoC5\USBFS_drv.c + .\Generated_Source\PSoC5\USBFS_episr.c + .\Generated_Source\PSoC5\USBFS_hid.c + .\Generated_Source\PSoC5\USBFS_hid.h + .\Generated_Source\PSoC5\USBFS_pm.c + .\Generated_Source\PSoC5\USBFS_std.c + .\Generated_Source\PSoC5\USBFS_vnd.c + .\Generated_Source\PSoC5\USBFS_midi.c + .\Generated_Source\PSoC5\USBFS_midi.h + .\Generated_Source\PSoC5\USBFS_pvt.h + .\Generated_Source\PSoC5\BL.c + .\Generated_Source\PSoC5\BL.h + .\Generated_Source\PSoC5\BL_PVT.h + .\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h + .\Generated_Source\PSoC5\SCSI_Out_aliases.h + .\Generated_Source\PSoC5\USBFS_Dm_aliases.h + .\Generated_Source\PSoC5\USBFS_Dm.c + .\Generated_Source\PSoC5\USBFS_Dm.h + .\Generated_Source\PSoC5\USBFS_Dp_aliases.h + .\Generated_Source\PSoC5\USBFS_Dp.c + .\Generated_Source\PSoC5\USBFS_Dp.h + .\Generated_Source\PSoC5\Cm3Start.c + .\Generated_Source\PSoC5\core_cm3_psoc5.h + .\Generated_Source\PSoC5\core_cm3.h + .\Generated_Source\PSoC5\CyBootAsmGnu.s + .\Generated_Source\PSoC5\CyBootAsmRv.s + .\Generated_Source\PSoC5\CyDmac.c + .\Generated_Source\PSoC5\CyDmac.h + .\Generated_Source\PSoC5\CyFlash.c + .\Generated_Source\PSoC5\CyFlash.h + .\Generated_Source\PSoC5\CyLib.c + .\Generated_Source\PSoC5\CyLib.h + .\Generated_Source\PSoC5\cypins.h + .\Generated_Source\PSoC5\cyPm.c + .\Generated_Source\PSoC5\cyPm.h + .\Generated_Source\PSoC5\CySpc.c + .\Generated_Source\PSoC5\CySpc.h + .\Generated_Source\PSoC5\cytypes.h + .\Generated_Source\PSoC5\cyutils.c + .\Generated_Source\PSoC5\core_cmFunc.h + .\Generated_Source\PSoC5\core_cmInstr.h + .\Generated_Source\PSoC5\CyBootAsmIar.s + .\Generated_Source\PSoC5\project.h + .\Generated_Source\PSoC5\SD_PULLUP_aliases.h + .\Generated_Source\PSoC5\SD_PULLUP.c + .\Generated_Source\PSoC5\SD_PULLUP.h + .\Generated_Source\PSoC5\LED_aliases.h + .\Generated_Source\PSoC5\LED.c + .\Generated_Source\PSoC5\LED.h + .\Generated_Source\PSoC5\prebuild.bat + .\Generated_Source\PSoC5\postbuild.bat + .\Generated_Source\PSoC5\CyElfTool.exe + .\Generated_Source\PSoC5\libelf.dll + + + + + .\Generated_Source\PSoC5\ARM_GCC\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\ARM_Keil_MDK\CyComponentLibrary.a + + + + + .\Generated_Source\PSoC5\IAR\CyComponentLibrary.a + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch new file mode 100644 index 0000000..4925ad2 Binary files /dev/null and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/TopDesign/TopDesign.cysch differ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cycdx b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cycdx new file mode 100644 index 0000000..ed76ff2 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cycdx @@ -0,0 +1,108 @@ + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cydwr b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cydwr new file mode 100644 index 0000000..4cb0217 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cydwr @@ -0,0 +1,1993 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit new file mode 100644 index 0000000..2d60b76 Binary files /dev/null and b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyfit differ diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj new file mode 100644 index 0000000..7859b10 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.cyprj @@ -0,0 +1,1364 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt new file mode 100644 index 0000000..3ca2f53 --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.rpt @@ -0,0 +1,3368 @@ +Loading plugins phase: Elapsed time ==> 0s.111ms + +cydsfit arguments: -.fdsnotice -.fdswarpdepfile=warp_dependencies.txt -.fdselabdepfile=elab_dependencies.txt -.fdsbldfile=generated_files.txt -.fdsreffile=referenced_files.txt -p C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 -s C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\Generated_Source\PSoC5 -- -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE + + + +Elaboration phase: Elapsed time ==> 1s.455ms + + +HDL generation phase: Elapsed time ==> 0s.042ms + + + | | | | | | | + _________________ + -| |- + -| |- + -| |- + -| CYPRESS |- + -| |- + -| |- Warp Verilog Synthesis Compiler: Version 6.3 IR 41 + -| |- Copyright (C) 1991-2001 Cypress Semiconductor + |_______________| + | | | | | | | + +====================================================================== +Compiling: USB_Bootloader.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +====================================================================== + +====================================================================== +Compiling: USB_Bootloader.v +Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog +====================================================================== + +====================================================================== +Compiling: USB_Bootloader.v +Program : vlogfe +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +====================================================================== + +vlogfe V6.3 IR 41: Verilog parser +Tue Sep 29 22:08:40 2020 + + +====================================================================== +Compiling: USB_Bootloader.v +Program : vpp +Options : -yv2 -q10 USB_Bootloader.v +====================================================================== + +vpp V6.3 IR 41: Verilog Pre-Processor +Tue Sep 29 22:08:40 2020 + +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v' +Flattening file 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v' + +vpp: No errors. + +Library 'work' => directory 'lcpsoc3' +General_symbol_table +General_symbol_table +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Using control file 'USB_Bootloader.ctl'. + +vlogfe: No errors. + + +====================================================================== +Compiling: USB_Bootloader.v +Program : tovif +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +====================================================================== + +tovif V6.3 IR 41: High-level synthesis +Tue Sep 29 22:08:40 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. + +tovif: No errors. + + +====================================================================== +Compiling: USB_Bootloader.v +Program : topld +Options : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 -verilog USB_Bootloader.v +====================================================================== + +topld V6.3 IR 41: Synthesis and optimization +Tue Sep 29 22:08:40 2020 + +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\std.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\cypress.vhd'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\work\cypress.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\ieee\work\stdlogic.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\lpmpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\rtlpkg.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_cnst.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_mthv.vif'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\common\stdlogic\mod_genv.vif'. +Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.ctl'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\cy_virtualmux_v1_0\cy_virtualmux_v1_0.v'. +Linking 'C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\codegentemp\USB_Bootloader.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\psoc\content\CyPrimitives\cyprimitives.cylib\ZeroTerminal\ZeroTerminal.v'. +Linking 'C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\lib\lcpsoc3\stdlogic\cpsoc3.vif'. + +---------------------------------------------------------- +Detecting unused logic. +---------------------------------------------------------- + User names + \USBFS:dma_nrq_0\ + \USBFS:Net_1800\ + \USBFS:dma_nrq_3\ + \USBFS:Net_1803\ + \USBFS:Net_1801\ + \USBFS:dma_nrq_1\ + \USBFS:dma_nrq_4\ + \USBFS:Net_1804\ + \USBFS:dma_nrq_5\ + \USBFS:Net_1805\ + \USBFS:dma_nrq_6\ + \USBFS:Net_1806\ + \USBFS:dma_nrq_7\ + \USBFS:Net_1807\ + \USBFS:dma_nrq_2\ + \USBFS:Net_1802\ + + +Deleted 16 User equations/components. +Deleted 0 Synthesized equations/components. + +------------------------------------------------------ +Alias Detection +------------------------------------------------------ +Aliasing one to \USBFS:tmpOE__Dm_net_0\ +Aliasing \USBFS:tmpOE__Dp_net_0\ to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_7 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_6 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_5 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_4 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_DBx_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_7 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_6 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_5 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_4 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SCSI_Out_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SD_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__LED_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__LED_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__TERM_EN_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__BOOTLDR_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_net_3 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_net_2 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_net_0 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_1_net_1 to \USBFS:tmpOE__Dm_net_0\ +Aliasing tmpOE__SPI_PULLUP_1_net_0 to \USBFS:tmpOE__Dm_net_0\ +Removing Rhs of wire one[37] = \USBFS:tmpOE__Dm_net_0\[31] +Removing Lhs of wire \USBFS:tmpOE__Dp_net_0\[40] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_7[65] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_6[66] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_5[67] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_4[68] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_3[69] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_2[70] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_1[71] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_DBx_net_0[72] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_7[100] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_6[101] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_5[102] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_4[103] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_3[104] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_2[105] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_1[106] = one[37] +Removing Lhs of wire tmpOE__SCSI_Out_net_0[107] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_3[135] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_2[136] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_1[137] = one[37] +Removing Lhs of wire tmpOE__SD_PULLUP_net_0[138] = one[37] +Removing Lhs of wire tmpOE__LED_net_1[150] = one[37] +Removing Lhs of wire tmpOE__LED_net_0[151] = one[37] +Removing Lhs of wire tmpOE__TERM_EN_net_0[159] = one[37] +Removing Lhs of wire tmpOE__BOOTLDR_net_0[166] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_net_3[172] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_net_2[173] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_net_1[174] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_net_0[175] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_1_net_1[187] = one[37] +Removing Lhs of wire tmpOE__SPI_PULLUP_1_net_0[188] = one[37] + +------------------------------------------------------ +Aliased 0 equations, 32 wires. +------------------------------------------------------ + +---------------------------------------------------------- +Circuit simplification +---------------------------------------------------------- + +Substituting virtuals - pass 1: + + +---------------------------------------------------------- +Circuit simplification results: + + Expanded 0 signals. + Turned 0 signals into soft nodes. + Maximum default expansion cost was set at 3. +---------------------------------------------------------- + +topld: No errors. + +CYPRESS_DIR : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp +Warp Program : C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\warp\bin\warp.exe +Warp Arguments : -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -dcpsoc3 USB_Bootloader.v -verilog + +Warp synthesis phase: Elapsed time ==> 0s.454ms + + +cyp3fit: V4.2.0.641, Family: PSoC3, Started at: Tuesday, 29 September 2020 22:08:40 +Options: -yv2 -q10 -ygs -o2 -v3 -.fftcfgtype=LE -ya -.fftprj=C:\Users\Michael\projects\SCSI2SD\software\SCSI2SD\v5.2\USB_Bootloader.cydsn\USB_Bootloader.cyprj -d CY8C5267AXI-LP051 USB_Bootloader.v -verilog + + +Design parsing phase: Elapsed time ==> 0s.010ms + + + +Assigning clock USBFS_Clock_vbus to clock BUS_CLK because it is a pass-through + + + + + + + + + + + +------------------------------------------------------------ +Design Equations +------------------------------------------------------------ + + + ------------------------------------------------------------ + Pin listing + ------------------------------------------------------------ + + Pin : Name = \USBFS:Dm(0)\ + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: USB_D_MINUS + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => \USBFS:Dm(0)\__PA , + analog_term => \USBFS:Net_597\ , + pad => \USBFS:Dm(0)_PAD\ ); + Properties: + { + } + + Pin : Name = \USBFS:Dp(0)\ + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: True + Interrupt mode: FALLING + Drive mode: HI_Z_ANALOG + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: True + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: USB_D_PLUS + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => \USBFS:Dp(0)\__PA , + analog_term => \USBFS:Net_1000\ , + pad => \USBFS:Dp(0)_PAD\ ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(0) + Attributes: + Alias: DB0 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(0)__PA , + pad => SCSI_Out_DBx(0)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(1) + Attributes: + Alias: DB1 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(1)__PA , + pad => SCSI_Out_DBx(1)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(2) + Attributes: + Alias: DB2 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(2)__PA , + pad => SCSI_Out_DBx(2)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(3) + Attributes: + Alias: DB3 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(3)__PA , + pad => SCSI_Out_DBx(3)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(4) + Attributes: + Alias: DB4 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(4)__PA , + pad => SCSI_Out_DBx(4)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(5) + Attributes: + Alias: DB5 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(5)__PA , + pad => SCSI_Out_DBx(5)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(6) + Attributes: + Alias: DB6 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(6)__PA , + pad => SCSI_Out_DBx(6)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out_DBx(7) + Attributes: + Alias: DB7 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(7)__PA , + pad => SCSI_Out_DBx(7)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(0) + Attributes: + Alias: DBP_raw + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(0)__PA , + pad => SCSI_Out(0)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(1) + Attributes: + Alias: BSY + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(1)__PA , + pad => SCSI_Out(1)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(2) + Attributes: + Alias: RST + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(2)__PA , + pad => SCSI_Out(2)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(3) + Attributes: + Alias: MSG + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(3)__PA , + pad => SCSI_Out(3)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(4) + Attributes: + Alias: SEL + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(4)__PA , + pad => SCSI_Out(4)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(5) + Attributes: + Alias: CD + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(5)__PA , + pad => SCSI_Out(5)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(6) + Attributes: + Alias: REQ + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(6)__PA , + pad => SCSI_Out(6)_PAD ); + Properties: + { + } + + Pin : Name = SCSI_Out(7) + Attributes: + Alias: IO_raw + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(7)__PA , + pad => SCSI_Out(7)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + + Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + + Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + pad => LED(0)_PAD ); + Properties: + { + } + + Pin : Name = LED(1) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(1)__PA , + pad => LED(1)_PAD ); + Properties: + { + } + + Pin : Name = TERM_EN(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => TERM_EN(0)__PA , + pad => TERM_EN(0)_PAD ); + Properties: + { + } + + Pin : Name = BOOTLDR(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => BOOTLDR(0)__PA , + pad => BOOTLDR(0)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(0)__PA , + pad => SPI_PULLUP(0)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(1)__PA , + pad => SPI_PULLUP(1)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(2)__PA , + pad => SPI_PULLUP(2)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(3)__PA , + pad => SPI_PULLUP(3)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP_1(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP_1(0)__PA , + pad => SPI_PULLUP_1(0)_PAD ); + Properties: + { + } + + Pin : Name = SPI_PULLUP_1(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP_1(1)__PA , + pad => SPI_PULLUP_1(1)_PAD ); + Properties: + { + } + + + + + + + + + + + + + + + + + + + + ------------------------------------------------------------ + Interrupt listing + ------------------------------------------------------------ + + interrupt: Name =\USBFS:ep_0\ + PORT MAP ( + interrupt => \USBFS:ept_int_0\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:bus_reset\ + PORT MAP ( + interrupt => \USBFS:Net_81\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:arb_int\ + PORT MAP ( + interrupt => \USBFS:Net_79\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:ep_2\ + PORT MAP ( + interrupt => \USBFS:ept_int_2\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:ep_1\ + PORT MAP ( + interrupt => \USBFS:ept_int_1\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:dp_int\ + PORT MAP ( + interrupt => \USBFS:Net_1010\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + interrupt: Name =\USBFS:sof_int\ + PORT MAP ( + interrupt => Net_40 ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + + + + +------------------------------------------------------------ +Technology mapping summary +------------------------------------------------------------ + +Resource Type : Used : Free : Max : % Used +============================================================ +Digital Clocks : 0 : 8 : 8 : 0.00 % +Analog Clocks : 0 : 4 : 4 : 0.00 % +CapSense Buffers : 0 : 2 : 2 : 0.00 % +Interrupts : 7 : 25 : 32 : 21.88 % +IO : 35 : 37 : 72 : 48.61 % +Segment LCD : 0 : 1 : 1 : 0.00 % +I2C : 0 : 1 : 1 : 0.00 % +USB : 1 : 0 : 1 : 100.00 % +DMA Channels : 0 : 24 : 24 : 0.00 % +Timer : 0 : 4 : 4 : 0.00 % +UDB : : : : + Macrocells : 0 : 192 : 192 : 0.00 % + Unique P-terms : 0 : 384 : 384 : 0.00 % + Total P-terms : 0 : : : + Datapath Cells : 0 : 24 : 24 : 0.00 % + Status Cells : 0 : 24 : 24 : 0.00 % + Control Cells : 0 : 24 : 24 : 0.00 % +Comparator : 0 : 2 : 2 : 0.00 % +Delta-Sigma ADC : 0 : 1 : 1 : 0.00 % +LPF : 0 : 2 : 2 : 0.00 % +SAR ADC : 0 : 1 : 1 : 0.00 % +DAC : : : : + VIDAC : 0 : 1 : 1 : 0.00 % + +Technology Mapping: Elapsed time ==> 0s.071ms +Tech Mapping phase: Elapsed time ==> 0s.129ms + + +Initial Analog Placement Results: +IO_0@[IOP=(0)][IoId=(0)] : BOOTLDR(0) (fixed) +IO_2@[IOP=(12)][IoId=(2)] : LED(0) (fixed) +IO_3@[IOP=(12)][IoId=(3)] : LED(1) (fixed) +IO_2@[IOP=(6)][IoId=(2)] : SCSI_Out(0) (fixed) +IO_6@[IOP=(4)][IoId=(6)] : SCSI_Out(1) (fixed) +IO_7@[IOP=(0)][IoId=(7)] : SCSI_Out(2) (fixed) +IO_5@[IOP=(0)][IoId=(5)] : SCSI_Out(3) (fixed) +IO_3@[IOP=(0)][IoId=(3)] : SCSI_Out(4) (fixed) +IO_1@[IOP=(0)][IoId=(1)] : SCSI_Out(5) (fixed) +IO_1@[IOP=(4)][IoId=(1)] : SCSI_Out(6) (fixed) +IO_0@[IOP=(4)][IoId=(0)] : SCSI_Out(7) (fixed) +IO_7@[IOP=(6)][IoId=(7)] : SCSI_Out_DBx(0) (fixed) +IO_5@[IOP=(6)][IoId=(5)] : SCSI_Out_DBx(1) (fixed) +IO_5@[IOP=(12)][IoId=(5)] : SCSI_Out_DBx(2) (fixed) +IO_7@[IOP=(2)][IoId=(7)] : SCSI_Out_DBx(3) (fixed) +IO_5@[IOP=(2)][IoId=(5)] : SCSI_Out_DBx(4) (fixed) +IO_3@[IOP=(2)][IoId=(3)] : SCSI_Out_DBx(5) (fixed) +IO_1@[IOP=(2)][IoId=(1)] : SCSI_Out_DBx(6) (fixed) +IO_5@[IOP=(15)][IoId=(5)] : SCSI_Out_DBx(7) (fixed) +IO_0@[IOP=(3)][IoId=(0)] : SD_PULLUP(0) (fixed) +IO_1@[IOP=(3)][IoId=(1)] : SD_PULLUP(1) (fixed) +IO_2@[IOP=(3)][IoId=(2)] : SD_PULLUP(2) (fixed) +IO_3@[IOP=(3)][IoId=(3)] : SD_PULLUP(3) (fixed) +IO_4@[IOP=(3)][IoId=(4)] : SPI_PULLUP(0) (fixed) +IO_5@[IOP=(3)][IoId=(5)] : SPI_PULLUP(1) (fixed) +IO_6@[IOP=(3)][IoId=(6)] : SPI_PULLUP(2) (fixed) +IO_7@[IOP=(3)][IoId=(7)] : SPI_PULLUP(3) (fixed) +IO_0@[IOP=(12)][IoId=(0)] : SPI_PULLUP_1(0) (fixed) +IO_1@[IOP=(12)][IoId=(1)] : SPI_PULLUP_1(1) (fixed) +IO_3@[IOP=(15)][IoId=(3)] : TERM_EN(0) (fixed) +IO_7@[IOP=(15)][IoId=(7)] : \USBFS:Dm(0)\ (fixed) +IO_6@[IOP=(15)][IoId=(6)] : \USBFS:Dp(0)\ (fixed) +USB[0]@[FFB(USB,0)] : \USBFS:USB\ +Analog Placement phase: Elapsed time ==> 0s.049ms + + +Analog Routing phase: Elapsed time ==> 0s.000ms + + +============ Analog Final Answer Routes ============ +Dump of CyAnalogRoutingResultsDB +Map of net to items { +} +Map of item to net { +} +Mux Info { +} +Dump of CyP35AnalogRoutingResultsDB +IsVddaHalfUsedForComp = False +IsVddaHalfUsedForSar0 = False +IsVddaHalfUsedForSar1 = False +Analog Code Generation phase: Elapsed time ==> 0s.253ms + + + +I2659: No Constrained paths were found. The placer will run in non-timing driven mode. +I2076: Total run-time: 0.6 sec. + + + + +No PLDs were packed. + +PLD Packing: Elapsed time ==> 0s.000ms + + + +Initial Partitioning Summary not displayed at this verbose level. + +Final Partitioning Summary not displayed at this verbose level. +Partitioning: Elapsed time ==> 0s.029ms + + + +------------------------------------------------------------ +Final Placement Summary +------------------------------------------------------------ + + Resource Type : Count : Avg Inputs : Avg Outputs + ======================================================== + UDB : 0 : 0.00 : 0.00 + + + +------------------------------------------------------------ +Component Placement Details +------------------------------------------------------------ +UDB [UDB=(0,0)] is empty. +UDB [UDB=(0,1)] is empty. +UDB [UDB=(0,2)] is empty. +UDB [UDB=(0,3)] is empty. +UDB [UDB=(0,4)] is empty. +UDB [UDB=(0,5)] is empty. +UDB [UDB=(1,0)] is empty. +UDB [UDB=(1,1)] is empty. +UDB [UDB=(1,2)] is empty. +UDB [UDB=(1,3)] is empty. +UDB [UDB=(1,4)] is empty. +UDB [UDB=(1,5)] is empty. +UDB [UDB=(2,0)] is empty. +UDB [UDB=(2,1)] is empty. +UDB [UDB=(2,2)] is empty. +UDB [UDB=(2,3)] is empty. +UDB [UDB=(2,4)] is empty. +UDB [UDB=(2,5)] is empty. +UDB [UDB=(3,0)] is empty. +UDB [UDB=(3,1)] is empty. +UDB [UDB=(3,2)] is empty. +UDB [UDB=(3,3)] is empty. +UDB [UDB=(3,4)] is empty. +UDB [UDB=(3,5)] is empty. +Intr container @ [IntrContainer=(0)]: + Intr@ [IntrContainer=(0)][IntrId=(0)] + interrupt: Name =\USBFS:ep_1\ + PORT MAP ( + interrupt => \USBFS:ept_int_1\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(1)] + interrupt: Name =\USBFS:ep_2\ + PORT MAP ( + interrupt => \USBFS:ept_int_2\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(12)] + interrupt: Name =\USBFS:dp_int\ + PORT MAP ( + interrupt => \USBFS:Net_1010\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(21)] + interrupt: Name =\USBFS:sof_int\ + PORT MAP ( + interrupt => Net_40 ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(22)] + interrupt: Name =\USBFS:arb_int\ + PORT MAP ( + interrupt => \USBFS:Net_79\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(23)] + interrupt: Name =\USBFS:bus_reset\ + PORT MAP ( + interrupt => \USBFS:Net_81\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } + Intr@ [IntrContainer=(0)][IntrId=(24)] + interrupt: Name =\USBFS:ep_0\ + PORT MAP ( + interrupt => \USBFS:ept_int_0\ ); + Properties: + { + int_type = "10" + is_nmi = 0 + } +Drq container @ [DrqContainer=(0)]: empty +Port 0 contains the following IO cells: +[IoId=0]: +Pin : Name = BOOTLDR(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => BOOTLDR(0)__PA , + pad => BOOTLDR(0)_PAD ); + Properties: + { + } + +[IoId=1]: +Pin : Name = SCSI_Out(5) + Attributes: + Alias: CD + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(5)__PA , + pad => SCSI_Out(5)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = SCSI_Out(4) + Attributes: + Alias: SEL + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(4)__PA , + pad => SCSI_Out(4)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SCSI_Out(3) + Attributes: + Alias: MSG + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(3)__PA , + pad => SCSI_Out(3)_PAD ); + Properties: + { + } + +[IoId=7]: +Pin : Name = SCSI_Out(2) + Attributes: + Alias: RST + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(2)__PA , + pad => SCSI_Out(2)_PAD ); + Properties: + { + } + +Port 1 contains the following IO cells: +Port 2 contains the following IO cells: +[IoId=1]: +Pin : Name = SCSI_Out_DBx(6) + Attributes: + Alias: DB6 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(6)__PA , + pad => SCSI_Out_DBx(6)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = SCSI_Out_DBx(5) + Attributes: + Alias: DB5 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(5)__PA , + pad => SCSI_Out_DBx(5)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SCSI_Out_DBx(4) + Attributes: + Alias: DB4 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(4)__PA , + pad => SCSI_Out_DBx(4)_PAD ); + Properties: + { + } + +[IoId=7]: +Pin : Name = SCSI_Out_DBx(3) + Attributes: + Alias: DB3 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(3)__PA , + pad => SCSI_Out_DBx(3)_PAD ); + Properties: + { + } + +Port 3 contains the following IO cells: +[IoId=0]: +Pin : Name = SD_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(0)__PA , + pad => SD_PULLUP(0)_PAD ); + Properties: + { + } + +[IoId=1]: +Pin : Name = SD_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(1)__PA , + pad => SD_PULLUP(1)_PAD ); + Properties: + { + } + +[IoId=2]: +Pin : Name = SD_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(2)__PA , + pad => SD_PULLUP(2)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = SD_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SD_PULLUP(3)__PA , + pad => SD_PULLUP(3)_PAD ); + Properties: + { + } + +[IoId=4]: +Pin : Name = SPI_PULLUP(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(0)__PA , + pad => SPI_PULLUP(0)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SPI_PULLUP(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(1)__PA , + pad => SPI_PULLUP(1)_PAD ); + Properties: + { + } + +[IoId=6]: +Pin : Name = SPI_PULLUP(2) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(2)__PA , + pad => SPI_PULLUP(2)_PAD ); + Properties: + { + } + +[IoId=7]: +Pin : Name = SPI_PULLUP(3) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP(3)__PA , + pad => SPI_PULLUP(3)_PAD ); + Properties: + { + } + +Port 4 contains the following IO cells: +[IoId=0]: +Pin : Name = SCSI_Out(7) + Attributes: + Alias: IO_raw + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(7)__PA , + pad => SCSI_Out(7)_PAD ); + Properties: + { + } + +[IoId=1]: +Pin : Name = SCSI_Out(6) + Attributes: + Alias: REQ + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(6)__PA , + pad => SCSI_Out(6)_PAD ); + Properties: + { + } + +[IoId=6]: +Pin : Name = SCSI_Out(1) + Attributes: + Alias: BSY + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(1)__PA , + pad => SCSI_Out(1)_PAD ); + Properties: + { + } + +Port 5 contains the following IO cells: +Port 6 contains the following IO cells: +[IoId=2]: +Pin : Name = SCSI_Out(0) + Attributes: + Alias: DBP_raw + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out(0)__PA , + pad => SCSI_Out(0)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SCSI_Out_DBx(1) + Attributes: + Alias: DB1 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(1)__PA , + pad => SCSI_Out_DBx(1)_PAD ); + Properties: + { + } + +[IoId=7]: +Pin : Name = SCSI_Out_DBx(0) + Attributes: + Alias: DB0 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(0)__PA , + pad => SCSI_Out_DBx(0)_PAD ); + Properties: + { + } + +Port 12 contains the following IO cells: +[IoId=0]: +Pin : Name = SPI_PULLUP_1(0) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP_1(0)__PA , + pad => SPI_PULLUP_1(0)_PAD ); + Properties: + { + } + +[IoId=1]: +Pin : Name = SPI_PULLUP_1(1) + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: INP_DIS_LO + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL, ROUTABLE + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => SPI_PULLUP_1(1)__PA , + pad => SPI_PULLUP_1(1)_PAD ); + Properties: + { + } + +[IoId=2]: +Pin : Name = LED(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(0)__PA , + pad => LED(0)_PAD ); + Properties: + { + } + +[IoId=3]: +Pin : Name = LED(1) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: RES_PULL_UP + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 1 + IO Voltage: 0 + PORT MAP ( + pa_out => LED(1)__PA , + pad => LED(1)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SCSI_Out_DBx(2) + Attributes: + Alias: DB2 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(2)__PA , + pad => SCSI_Out_DBx(2)_PAD ); + Properties: + { + } + +Port 15 generates interrupt for logical port: + logicalport: Name =\USBFS:Dp\ + PORT MAP ( + in_clock_en => one , + in_reset => zero , + out_clock_en => one , + out_reset => zero , + interrupt => \USBFS:Net_1010\ , + in_clock => ClockBlock_BUS_CLK ); + Properties: + { + drive_mode = "000" + ibuf_enabled = "0" + id = "f9248435-5d3e-4e4d-bbae-bdae8795c3dd/618a72fc-5ddd-4df5-958f-a3d55102db42" + init_dr_st = "0" + input_buffer_sel = "00" + input_clk_en = 0 + input_sync = "1" + input_sync_mode = "0" + intr_mode = "10" + invert_in_clock = 0 + invert_in_clock_en = 0 + invert_in_reset = 0 + invert_out_clock = 0 + invert_out_clock_en = 0 + invert_out_reset = 0 + io_voltage = "" + layout_mode = "CONTIGUOUS" + oe_conn = "0" + oe_reset = 0 + oe_sync = "0" + output_clk_en = 0 + output_clock_mode = "0" + output_conn = "0" + output_mode = "0" + output_reset = 0 + output_sync = "0" + ovt_hyst_trim = "0" + ovt_needed = "0" + ovt_slew_control = "00" + pa_in_clock = -1 + pa_in_clock_en = -1 + pa_in_reset = -1 + pa_out_clock = -1 + pa_out_clock_en = -1 + pa_out_reset = -1 + pin_aliases = "" + pin_mode = "I" + por_state = 4 + port_alias_group = "" + port_alias_required = 0 + sio_group_cnt = 0 + sio_hifreq = "" + sio_hyst = "1" + sio_ibuf = "00000000" + sio_info = "00" + sio_obuf = "00000000" + sio_refsel = "00000000" + sio_vohsel = "" + sio_vtrip = "00000000" + slew_rate = "0" + spanning = 0 + sw_only = 0 + use_annotation = "0" + vtrip = "00" + width = 1 + } + and contains the following IO cells: +[IoId=3]: +Pin : Name = TERM_EN(0) + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => TERM_EN(0)__PA , + pad => TERM_EN(0)_PAD ); + Properties: + { + } + +[IoId=5]: +Pin : Name = SCSI_Out_DBx(7) + Attributes: + Alias: DB7 + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: NOSYNC + Interrupt generated: False + Interrupt mode: NONE + Drive mode: CMOS_OUT + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: False + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: DIGITAL + Initial Value: 0 + IO Voltage: 5 + PORT MAP ( + pa_out => SCSI_Out_DBx(7)__PA , + pad => SCSI_Out_DBx(7)_PAD ); + Properties: + { + } + +[IoId=6]: +Pin : Name = \USBFS:Dp(0)\ + Attributes: + In Group/Port: True + In Sync Option: SYNC + Out Sync Option: AUTO + Interrupt generated: True + Interrupt mode: FALLING + Drive mode: HI_Z_ANALOG + VTrip: CMOS + Slew: FAST + Input Sync needed: True + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: False + Is OE Registered: False + Uses Analog: True + Can contain Digital: True + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: USB_D_PLUS + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => \USBFS:Dp(0)\__PA , + analog_term => \USBFS:Net_1000\ , + pad => \USBFS:Dp(0)_PAD\ ); + Properties: + { + } + +[IoId=7]: +Pin : Name = \USBFS:Dm(0)\ + Attributes: + In Group/Port: True + In Sync Option: AUTO + Out Sync Option: AUTO + Interrupt generated: False + Interrupt mode: NONE + Drive mode: HI_Z_ANALOG + VTrip: EITHER + Slew: FAST + Input Sync needed: False + Output Sync needed: False + SC shield enabled: False + POR State: ANY + LCD Mode: COMMON + Register Mode: RegComb + CaSense Mode: NEITHER + Treat as pin: True + Is OE Registered: False + Uses Analog: True + Can contain Digital: False + Is SIO: False + SIO Output Buf: NONREGULATED + SIO Input Buf: SINGLE_ENDED + SIO HiFreq: LOW + SIO Hyst: DISABLED + SIO Vtrip: MULTIPLIER_0_5 + SIO Multiplier Index: 0 + SIO RefSel: VCC_IO + Required Capabilities: USB_D_MINUS + Initial Value: 0 + IO Voltage: 0 + PORT MAP ( + pa_out => \USBFS:Dm(0)\__PA , + analog_term => \USBFS:Net_597\ , + pad => \USBFS:Dm(0)_PAD\ ); + Properties: + { + } + +ARM group 0: empty +Cache group 0: empty +CapSense group 0: empty +Clock group 0: + Clock Block @ F(Clock,0): + clockblockcell: Name =ClockBlock + PORT MAP ( + imo => ClockBlock_IMO , + pllout => ClockBlock_PLL_OUT , + ilo => ClockBlock_ILO , + clk_100k => ClockBlock_100k , + clk_1k => ClockBlock_1k , + clk_32k => ClockBlock_32k , + xtal => ClockBlock_XTAL , + clk_32k_xtal => ClockBlock_XTAL_32KHZ , + clk_sync => ClockBlock_MASTER_CLK , + clk_bus_glb => ClockBlock_BUS_CLK , + clk_bus => ClockBlock_BUS_CLK_local ); + Properties: + { + } +Comparator group 0: empty +DSM group 0: empty +Decimator group 0: empty +EMIF group 0: empty +I2C group 0: empty +LCD group 0: empty +LVD group 0: empty +PICU group 0: empty +PM group 0: empty +SPC group 0: empty +Timer group 0: empty +USB group 0: + USB Block @ F(USB,0): + usbcell: Name =\USBFS:USB\ + PORT MAP ( + dp => \USBFS:Net_1000\ , + dm => \USBFS:Net_597\ , + sof_int => Net_40 , + arb_int => \USBFS:Net_79\ , + usb_int => \USBFS:Net_81\ , + ept_int_8 => \USBFS:ept_int_8\ , + ept_int_7 => \USBFS:ept_int_7\ , + ept_int_6 => \USBFS:ept_int_6\ , + ept_int_5 => \USBFS:ept_int_5\ , + ept_int_4 => \USBFS:ept_int_4\ , + ept_int_3 => \USBFS:ept_int_3\ , + ept_int_2 => \USBFS:ept_int_2\ , + ept_int_1 => \USBFS:ept_int_1\ , + ept_int_0 => \USBFS:ept_int_0\ , + ord_int => \USBFS:Net_95\ , + dma_req_7 => \USBFS:dma_req_7\ , + dma_req_6 => \USBFS:dma_req_6\ , + dma_req_5 => \USBFS:dma_req_5\ , + dma_req_4 => \USBFS:dma_req_4\ , + dma_req_3 => \USBFS:dma_req_3\ , + dma_req_2 => \USBFS:dma_req_2\ , + dma_req_1 => \USBFS:dma_req_1\ , + dma_req_0 => \USBFS:dma_req_0\ , + dma_termin => \USBFS:Net_824\ ); + Properties: + { + cy_registers = "" + } +VIDAC group 0: empty +CsAbuf group 0: empty +Vref group 0: empty +LPF group 0: empty +SAR group 0: empty +ANAIF group 0: empty +PHUB group 0: empty + + + +------------------------------------------------------------ +Port Configuration report +------------------------------------------------------------ + | | | Interrupt | | | +Port | Pin | Fixed | Type | Drive Mode | Name | Connections +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 0 | 0 | * | NONE | RES_PULL_UP | BOOTLDR(0) | + | 1 | * | NONE | CMOS_OUT | SCSI_Out(5) | + | 3 | * | NONE | CMOS_OUT | SCSI_Out(4) | + | 5 | * | NONE | CMOS_OUT | SCSI_Out(3) | + | 7 | * | NONE | CMOS_OUT | SCSI_Out(2) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 2 | 1 | * | NONE | CMOS_OUT | SCSI_Out_DBx(6) | + | 3 | * | NONE | CMOS_OUT | SCSI_Out_DBx(5) | + | 5 | * | NONE | CMOS_OUT | SCSI_Out_DBx(4) | + | 7 | * | NONE | CMOS_OUT | SCSI_Out_DBx(3) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 3 | 0 | * | NONE | RES_PULL_UP | SD_PULLUP(0) | + | 1 | * | NONE | RES_PULL_UP | SD_PULLUP(1) | + | 2 | * | NONE | RES_PULL_UP | SD_PULLUP(2) | + | 3 | * | NONE | RES_PULL_UP | SD_PULLUP(3) | + | 4 | * | NONE | RES_PULL_UP | SPI_PULLUP(0) | + | 5 | * | NONE | RES_PULL_UP | SPI_PULLUP(1) | + | 6 | * | NONE | RES_PULL_UP | SPI_PULLUP(2) | + | 7 | * | NONE | RES_PULL_UP | SPI_PULLUP(3) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 4 | 0 | * | NONE | CMOS_OUT | SCSI_Out(7) | + | 1 | * | NONE | CMOS_OUT | SCSI_Out(6) | + | 6 | * | NONE | CMOS_OUT | SCSI_Out(1) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 6 | 2 | * | NONE | CMOS_OUT | SCSI_Out(0) | + | 5 | * | NONE | CMOS_OUT | SCSI_Out_DBx(1) | + | 7 | * | NONE | CMOS_OUT | SCSI_Out_DBx(0) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 12 | 0 | * | NONE | RES_PULL_UP | SPI_PULLUP_1(0) | + | 1 | * | NONE | RES_PULL_UP | SPI_PULLUP_1(1) | + | 2 | * | NONE | RES_PULL_UP | LED(0) | + | 3 | * | NONE | RES_PULL_UP | LED(1) | + | 5 | * | NONE | CMOS_OUT | SCSI_Out_DBx(2) | +-----+-----+-------+-----------+------------------+-----------------+------------------------- + 15 | 3 | * | NONE | CMOS_OUT | TERM_EN(0) | + | 5 | * | NONE | CMOS_OUT | SCSI_Out_DBx(7) | + | 6 | * | FALLING | HI_Z_ANALOG | \USBFS:Dp(0)\ | Analog(\USBFS:Net_1000\) + | 7 | * | NONE | HI_Z_ANALOG | \USBFS:Dm(0)\ | Analog(\USBFS:Net_597\) +---------------------------------------------------------------------------------------------- + + + +Digital component placer commit/Report: Elapsed time ==> 0s.047ms +Digital Placement phase: Elapsed time ==> 0s.979ms + + +"C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\bin/sjrouter.exe" --xml-path "C:\Program Files (x86)\Cypress\PSoC Creator\4.2\PSoC Creator\dev\psoc5/psoc5lp/route_arch-rrg.cydata" --vh2-path "USB_Bootloader_r.vh2" --pcf-path "USB_Bootloader.pco" --des-name "USB_Bootloader" --dsf-path "USB_Bootloader.dsf" --sdc-path "USB_Bootloader.sdc" --lib-path "USB_Bootloader_r.lib" +Routing successful. +Digital Routing phase: Elapsed time ==> 1s.052ms + + +Bitstream Generation phase: Elapsed time ==> 0s.154ms + + +Bitstream Verification phase: Elapsed time ==> 0s.030ms + + +Timing report is in USB_Bootloader_timing.html. +Static timing analysis phase: Elapsed time ==> 0s.224ms + + +Data reporting phase: Elapsed time ==> 0s.000ms + + +Design database save phase: Elapsed time ==> 0s.163ms + +cydsfit: Elapsed time ==> 3s.066ms + +Fitter phase: Elapsed time ==> 3s.068ms +API generation phase: Elapsed time ==> 1s.280ms +Dependency generation phase: Elapsed time ==> 0s.006ms +Cleanup phase: Elapsed time ==> 0s.000ms diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.svd b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.svd new file mode 100644 index 0000000..72130dc --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader.svd @@ -0,0 +1,494 @@ + + + CY8C5267AXI_LP051 + 0.1 + CY8C52LP + 8 + 32 + + + USBFS + USBFS + 0x0 + + 0 + 0x0 + registers + + + + USBFS_PM_USB_CR0 + USB Power Mode Control Register 0 + 0x40004394 + 8 + read-write + 0 + 0 + + + fsusbio_ref_en + No description available + 0 + 0 + read-write + + + fsusbio_pd_n + No description available + 1 + 1 + read-write + + + fsusbio_pd_pullup_n + No description available + 2 + 2 + read-write + + + + + USBFS_PM_ACT_CFG + Active Power Mode Configuration Register + 0x400043A5 + 8 + read-write + 0 + 0 + + + USBFS_PM_STBY_CFG + Standby Power Mode Configuration Register + 0x400043B5 + 8 + read-write + 0 + 0 + + + USBFS_PRT_PS + Port Pin State Register + 0x400051F1 + 8 + read-write + 0 + 0 + + + PinState_DP + No description available + 6 + 6 + read-only + + + PinState_DM + No description available + 7 + 7 + read-only + + + + + USBFS_PRT_DM0 + Port Drive Mode Register + 0x400051F2 + 8 + read-write + 0 + 0 + + + DriveMode_DP + No description available + 6 + 6 + read-write + + + DriveMode_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_DM1 + Port Drive Mode Register + 0x400051F3 + 8 + read-write + 0 + 0 + + + PullUp_en_DP + No description available + 6 + 6 + read-write + + + PullUp_en_DM + No description available + 7 + 7 + read-write + + + + + USBFS_PRT_INP_DIS + Input buffer disable override + 0x400051F8 + 8 + read-write + 0 + 0 + + + seinput_dis_dp + No description available + 6 + 6 + read-write + + + seinput_dis_dm + No description available + 7 + 7 + read-write + + + + + USBFS_EP0_DR0 + bmRequestType + 0x40006000 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR1 + bRequest + 0x40006001 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR2 + wValueLo + 0x40006002 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR3 + wValueHi + 0x40006003 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR4 + wIndexLo + 0x40006004 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR5 + wIndexHi + 0x40006005 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR6 + lengthLo + 0x40006006 + 8 + read-write + 0 + 0 + + + USBFS_EP0_DR7 + lengthHi + 0x40006007 + 8 + read-write + 0 + 0 + + + USBFS_CR0 + USB Control Register 0 + 0x40006008 + 8 + read-write + 0 + 0 + + + device_address + No description available + 0 + 6 + read-only + + + usb_enable + No description available + 7 + 7 + read-write + + + + + USBFS_CR1 + USB Control Register 1 + 0x40006009 + 8 + read-write + 0 + 0 + + + reg_enable + No description available + 0 + 0 + read-write + + + enable_lock + No description available + 1 + 1 + read-write + + + bus_activity + No description available + 2 + 2 + read-write + + + trim_offset_msb + No description available + 3 + 3 + read-write + + + + + USBFS_SIE_EP1_CR0 + The Endpoint1 Control Register + 0x4000600E + 8 + read-write + 0 + 0 + + + USBFS_USBIO_CR0 + USBIO Control Register 0 + 0x40006010 + 8 + read-write + 0 + 0 + + + rd + No description available + 0 + 0 + read-only + + + td + No description available + 5 + 5 + read-write + + + tse0 + No description available + 6 + 6 + read-write + + + ten + No description available + 7 + 7 + read-write + + + + + USBFS_USBIO_CR1 + USBIO Control Register 1 + 0x40006012 + 8 + read-write + 0 + 0 + + + dmo + No description available + 0 + 0 + read-only + + + dpo + No description available + 1 + 1 + read-only + + + usbpuen + No description available + 2 + 2 + read-write + + + iomode + No description available + 5 + 5 + read-write + + + + + USBFS_SIE_EP2_CR0 + The Endpoint2 Control Register + 0x4000601E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP3_CR0 + The Endpoint3 Control Register + 0x4000602E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP4_CR0 + The Endpoint4 Control Register + 0x4000603E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP5_CR0 + The Endpoint5 Control Register + 0x4000604E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP6_CR0 + The Endpoint6 Control Register + 0x4000605E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP7_CR0 + The Endpoint7 Control Register + 0x4000606E + 8 + read-write + 0 + 0 + + + USBFS_SIE_EP8_CR0 + The Endpoint8 Control Register + 0x4000607E + 8 + read-write + 0 + 0 + + + USBFS_BUF_SIZE + Dedicated Endpoint Buffer Size Register + 0x4000608C + 8 + read-write + 0 + 0 + + + USBFS_EP_ACTIVE + Endpoint Active Indication Register + 0x4000608E + 8 + read-write + 0 + 0 + + + USBFS_EP_TYPE + Endpoint Type (IN/OUT) Indication + 0x4000608F + 8 + read-write + 0 + 0 + + + USBFS_USB_CLK_EN + USB Block Clock Enable Register + 0x4000609D + 8 + read-write + 0 + 0 + + + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html new file mode 100644 index 0000000..a6b325d --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/USB_Bootloader_timing.html @@ -0,0 +1,644 @@ + + + + +Static Timing Analysis Report + + + + + + +

Static Timing Analysis

+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
Project : USB_Bootloader
Build Time : 09/29/20 22:08:43
Device : CY8C5267AXI-LP051
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 3.00
VUSB : 5.00
Voltage : 5.0
+ +
+
No Timing Violations
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+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ClockDomainNominal FrequencyRequired FrequencyMaximum FrequencyViolation
CyILOCyILO100.000 kHz100.000 kHz N/A
CyIMOCyIMO24.000 MHz24.000 MHz N/A
CyMASTER_CLKCyMASTER_CLK64.000 MHz64.000 MHz N/A
CyBUS_CLKCyMASTER_CLK64.000 MHz64.000 MHz N/A
CyPLL_OUTCyPLL_OUT64.000 MHz64.000 MHz N/A
+
+
+ + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/main.c b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/main.c new file mode 100644 index 0000000..d36b0ed --- /dev/null +++ b/software/SCSI2SD/v5.2/USB_Bootloader.cydsn/main.c @@ -0,0 +1,79 @@ +// Copyright (C) 2013 Michael McMaster +// +// This file is part of SCSI2SD. +// +// SCSI2SD is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// SCSI2SD is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with SCSI2SD. If not, see . +#include + +static void resetSCSI() +{ + CyPins_SetPin(TERM_EN_0); // Active low + + CyPins_ClearPin(SCSI_Out_IO_raw); + CyPins_ClearPin(SCSI_Out_BSY); + CyPins_ClearPin(SCSI_Out_RST); + CyPins_ClearPin(SCSI_Out_SEL); + CyPins_ClearPin(SCSI_Out_REQ); + CyPins_ClearPin(SCSI_Out_MSG); + CyPins_ClearPin(SCSI_Out_CD); + CyPins_ClearPin(SCSI_Out_DBx_DB0); + CyPins_ClearPin(SCSI_Out_DBx_DB1); + CyPins_ClearPin(SCSI_Out_DBx_DB2); + CyPins_ClearPin(SCSI_Out_DBx_DB3); + CyPins_ClearPin(SCSI_Out_DBx_DB4); + CyPins_ClearPin(SCSI_Out_DBx_DB5); + CyPins_ClearPin(SCSI_Out_DBx_DB6); + CyPins_ClearPin(SCSI_Out_DBx_DB7); + CyPins_ClearPin(SCSI_Out_DBP_raw); + + // active low + CyPins_SetPin(LED_0); + CyPins_SetPin(LED_1); +} + +int main() +{ + resetSCSI(); + + // We need some delay before reading the BOOTLDR pin gives us the correct + // answer. I don't know if it's due to the pullup enabled, or use of the + // 32k xtal pins as GPIO immediately after power on. + // Try to startup as fast as possible in the normal case of no-bootloader-jumper + int limit = 100; + while (limit > 0 && BOOTLDR_Read() == 0) // active low + { + CyDelayUs(100); + limit--; + } + + if (BOOTLDR_Read() == 0) + { + CyPins_ClearPin(LED_0); + CyPins_ClearPin(LED_1); + BL_SET_RUN_TYPE(BL_START_BTLDR); + } + + // The call to the bootloader should not return + BL_Start(); + + /* CyGlobalIntEnable; */ /* Uncomment this line to enable global interrupts. */ + for(;;) + { + CyPins_ClearPin(LED_0); + CyPins_ClearPin(LED_1); + /* Place your application code here. */ + } + return 0; +} +