diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.c new file mode 100644 index 0000000..a7a2cdd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.c @@ -0,0 +1,65 @@ +/******************************************************************************* +* File Name: NOR_CTL.c +* Version 1.80 +* +* Description: +* This file contains API to enable firmware control of a Control Register. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "NOR_CTL.h" + +/* Check for removal by optimization */ +#if !defined(NOR_CTL_Sync_ctrl_reg__REMOVED) + + +/******************************************************************************* +* Function Name: NOR_CTL_Write +******************************************************************************** +* +* Summary: +* Write a byte to the Control Register. +* +* Parameters: +* control: The value to be assigned to the Control Register. +* +* Return: +* None. +* +*******************************************************************************/ +void NOR_CTL_Write(uint8 control) +{ + NOR_CTL_Control = control; +} + + +/******************************************************************************* +* Function Name: NOR_CTL_Read +******************************************************************************** +* +* Summary: +* Reads the current value assigned to the Control Register. +* +* Parameters: +* None. +* +* Return: +* Returns the current value in the Control Register. +* +*******************************************************************************/ +uint8 NOR_CTL_Read(void) +{ + return NOR_CTL_Control; +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.h new file mode 100644 index 0000000..b545356 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL.h @@ -0,0 +1,67 @@ +/******************************************************************************* +* File Name: NOR_CTL.h +* Version 1.80 +* +* Description: +* This file containts Control Register function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CONTROL_REG_NOR_CTL_H) /* CY_CONTROL_REG_NOR_CTL_H */ +#define CY_CONTROL_REG_NOR_CTL_H + +#include "cyfitter.h" + +#if ((CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC3) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC4) || \ + (CYDEV_CHIP_FAMILY_USED == CYDEV_CHIP_FAMILY_PSOC5)) + #include "cytypes.h" +#else + #include "syslib/cy_syslib.h" +#endif + + +/*************************************** +* Data Struct Definitions +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 controlState; + +} NOR_CTL_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void NOR_CTL_Write(uint8 control) ; +uint8 NOR_CTL_Read(void) ; + +void NOR_CTL_SaveConfig(void) ; +void NOR_CTL_RestoreConfig(void) ; +void NOR_CTL_Sleep(void) ; +void NOR_CTL_Wakeup(void) ; + + +/*************************************** +* Registers +***************************************/ + +/* Control Register */ +#define NOR_CTL_Control (* (reg8 *) NOR_CTL_Sync_ctrl_reg__CONTROL_REG ) +#define NOR_CTL_Control_PTR ( (reg8 *) NOR_CTL_Sync_ctrl_reg__CONTROL_REG ) + +#endif /* End CY_CONTROL_REG_NOR_CTL_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL_PM.c new file mode 100644 index 0000000..47f2d88 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_CTL_PM.c @@ -0,0 +1,109 @@ +/******************************************************************************* +* File Name: NOR_CTL_PM.c +* Version 1.80 +* +* Description: +* This file contains the setup, control, and status commands to support +* the component operation in the low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "NOR_CTL.h" + +/* Check for removal by optimization */ +#if !defined(NOR_CTL_Sync_ctrl_reg__REMOVED) + +static NOR_CTL_BACKUP_STRUCT NOR_CTL_backup = {0u}; + + +/******************************************************************************* +* Function Name: NOR_CTL_SaveConfig +******************************************************************************** +* +* Summary: +* Saves the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void NOR_CTL_SaveConfig(void) +{ + NOR_CTL_backup.controlState = NOR_CTL_Control; +} + + +/******************************************************************************* +* Function Name: NOR_CTL_RestoreConfig +******************************************************************************** +* +* Summary: +* Restores the control register value. +* +* Parameters: +* None +* +* Return: +* None +* +* +*******************************************************************************/ +void NOR_CTL_RestoreConfig(void) +{ + NOR_CTL_Control = NOR_CTL_backup.controlState; +} + + +/******************************************************************************* +* Function Name: NOR_CTL_Sleep +******************************************************************************** +* +* Summary: +* Prepares the component for entering the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void NOR_CTL_Sleep(void) +{ + NOR_CTL_SaveConfig(); +} + + +/******************************************************************************* +* Function Name: NOR_CTL_Wakeup +******************************************************************************** +* +* Summary: +* Restores the component after waking up from the low power mode. +* +* Parameters: +* None +* +* Return: +* None +* +*******************************************************************************/ +void NOR_CTL_Wakeup(void) +{ + NOR_CTL_RestoreConfig(); +} + +#endif /* End check for removal by optimization */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.c new file mode 100644 index 0000000..10c1a16 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.c @@ -0,0 +1,521 @@ +/******************************************************************************* +* File Name: NOR_Clock.c +* Version 2.20 +* +* Description: +* This file provides the source code to the API for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include +#include "NOR_Clock.h" + +/* Clock Distribution registers. */ +#define CLK_DIST_LD (* (reg8 *) CYREG_CLKDIST_LD) +#define CLK_DIST_BCFG2 (* (reg8 *) CYREG_CLKDIST_BCFG2) +#define BCFG2_MASK (0x80u) +#define CLK_DIST_DMASK (* (reg8 *) CYREG_CLKDIST_DMASK) +#define CLK_DIST_AMASK (* (reg8 *) CYREG_CLKDIST_AMASK) + +#define HAS_CLKDIST_LD_DISABLE (CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: NOR_Clock_Start +******************************************************************************** +* +* Summary: +* Starts the clock. Note that on startup, clocks may be already running if the +* "Start on Reset" option is enabled in the DWR. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_Start(void) +{ + /* Set the bit to enable the clock. */ + NOR_Clock_CLKEN |= NOR_Clock_CLKEN_MASK; + NOR_Clock_CLKSTBY |= NOR_Clock_CLKSTBY_MASK; +} + + +/******************************************************************************* +* Function Name: NOR_Clock_Stop +******************************************************************************** +* +* Summary: +* Stops the clock and returns immediately. This API does not require the +* source clock to be running but may return before the hardware is actually +* disabled. If the settings of the clock are changed after calling this +* function, the clock may glitch when it is started. To avoid the clock +* glitch, use the StopBlock function. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_Stop(void) +{ + /* Clear the bit to disable the clock. */ + NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK); + NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK); +} + + +#if(CY_PSOC3 || CY_PSOC5LP) + + +/******************************************************************************* +* Function Name: NOR_Clock_StopBlock +******************************************************************************** +* +* Summary: +* Stops the clock and waits for the hardware to actually be disabled before +* returning. This ensures that the clock is never truncated (high part of the +* cycle will terminate before the clock is disabled and the API returns). +* Note that the source clock must be running or this API will never return as +* a stopped clock cannot be disabled. +* +* Parameters: +* None +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_StopBlock(void) +{ + if ((NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK) != 0u) + { +#if HAS_CLKDIST_LD_DISABLE + uint16 oldDivider; + + CLK_DIST_LD = 0u; + + /* Clear all the mask bits except ours. */ +#if defined(NOR_Clock__CFG3) + CLK_DIST_AMASK = NOR_Clock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = NOR_Clock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* NOR_Clock__CFG3 */ + + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + oldDivider = CY_GET_REG16(NOR_Clock_DIV_PTR); + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE | CYCLK_LD_SYNC_EN | CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + /* Clear the bit to disable the clock. */ + NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK); + NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; + CY_SET_REG16(NOR_Clock_DIV_PTR, oldDivider); +#endif /* HAS_CLKDIST_LD_DISABLE */ + } +} +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + + +/******************************************************************************* +* Function Name: NOR_Clock_StandbyPower +******************************************************************************** +* +* Summary: +* Sets whether the clock is active in standby mode. +* +* Parameters: +* state: 0 to disable clock during standby, nonzero to enable. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_StandbyPower(uint8 state) +{ + if(state == 0u) + { + NOR_Clock_CLKSTBY &= (uint8)(~NOR_Clock_CLKSTBY_MASK); + } + else + { + NOR_Clock_CLKSTBY |= NOR_Clock_CLKSTBY_MASK; + } +} + + +/******************************************************************************* +* Function Name: NOR_Clock_SetDividerRegister +******************************************************************************** +* +* Summary: +* Modifies the clock divider and, thus, the frequency. When the clock divider +* register is set to zero or changed from zero, the clock will be temporarily +* disabled in order to change the SSS mode bit. If the clock is enabled when +* SetDividerRegister is called, then the source clock must be running. +* +* Parameters: +* clkDivider: Divider register value (0-65,535). This value is NOT the +* divider; the clock hardware divides by clkDivider plus one. For example, +* to divide the clock by 2, this parameter should be set to 1. +* restart: If nonzero, restarts the clock divider: the current clock cycle +* will be truncated and the new divide value will take effect immediately. If +* zero, the new divide value will take effect at the end of the current clock +* cycle. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_SetDividerRegister(uint16 clkDivider, uint8 restart) + +{ + uint8 enabled; + + uint8 currSrc = NOR_Clock_GetSourceRegister(); + uint16 oldDivider = NOR_Clock_GetDividerRegister(); + + if (clkDivider != oldDivider) + { + enabled = NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK; + + if ((currSrc == (uint8)CYCLK_SRC_SEL_CLK_SYNC_D) && ((oldDivider == 0u) || (clkDivider == 0u))) + { + /* Moving to/from SSS requires correct ordering to prevent halting the clock */ + if (oldDivider == 0u) + { + /* Moving away from SSS, set the divider first so when SSS is cleared we */ + /* don't halt the clock. Using the shadow load isn't required as the */ + /* divider is ignored while SSS is set. */ + CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider); + NOR_Clock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + /* Moving to SSS, set SSS which then ignores the divider and we can set */ + /* it without bothering with the shadow load. */ + NOR_Clock_MOD_SRC |= CYCLK_SSS; + CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider); + } + } + else + { + + if (enabled != 0u) + { + CLK_DIST_LD = 0x00u; + + /* Clear all the mask bits except ours. */ +#if defined(NOR_Clock__CFG3) + CLK_DIST_AMASK = NOR_Clock_CLKEN_MASK; + CLK_DIST_DMASK = 0x00u; +#else + CLK_DIST_DMASK = NOR_Clock_CLKEN_MASK; + CLK_DIST_AMASK = 0x00u; +#endif /* NOR_Clock__CFG3 */ + /* Clear mask of bus clock. */ + CLK_DIST_BCFG2 &= (uint8)(~BCFG2_MASK); + + /* If clock is currently enabled, disable it if async or going from N-to-1*/ + if (((NOR_Clock_MOD_SRC & CYCLK_SYNC) == 0u) || (clkDivider == 0u)) + { +#if HAS_CLKDIST_LD_DISABLE + CY_SET_REG16(CYREG_CLKDIST_WRK0, oldDivider); + CLK_DIST_LD = CYCLK_LD_DISABLE|CYCLK_LD_SYNC_EN|CYCLK_LD_LOAD; + + /* Wait for clock to be disabled */ + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } +#endif /* HAS_CLKDIST_LD_DISABLE */ + + NOR_Clock_CLKEN &= (uint8)(~NOR_Clock_CLKEN_MASK); + +#if HAS_CLKDIST_LD_DISABLE + /* Clear the disable bit */ + CLK_DIST_LD = 0x00u; +#endif /* HAS_CLKDIST_LD_DISABLE */ + } + } + + /* Load divide value. */ + if ((NOR_Clock_CLKEN & NOR_Clock_CLKEN_MASK) != 0u) + { + /* If the clock is still enabled, use the shadow registers */ + CY_SET_REG16(CYREG_CLKDIST_WRK0, clkDivider); + + CLK_DIST_LD = (CYCLK_LD_LOAD | ((restart != 0u) ? CYCLK_LD_SYNC_EN : 0x00u)); + while ((CLK_DIST_LD & CYCLK_LD_LOAD) != 0u) { } + } + else + { + /* If the clock is disabled, set the divider directly */ + CY_SET_REG16(NOR_Clock_DIV_PTR, clkDivider); + NOR_Clock_CLKEN |= enabled; + } + } + } +} + + +/******************************************************************************* +* Function Name: NOR_Clock_GetDividerRegister +******************************************************************************** +* +* Summary: +* Gets the clock divider register value. +* +* Parameters: +* None +* +* Returns: +* Divide value of the clock minus 1. For example, if the clock is set to +* divide by 2, the return value will be 1. +* +*******************************************************************************/ +uint16 NOR_Clock_GetDividerRegister(void) +{ + return CY_GET_REG16(NOR_Clock_DIV_PTR); +} + + +/******************************************************************************* +* Function Name: NOR_Clock_SetModeRegister +******************************************************************************** +* +* Summary: +* Sets flags that control the operating mode of the clock. This function only +* changes flags from 0 to 1; flags that are already 1 will remain unchanged. +* To clear flags, use the ClearModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to set. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_SetModeRegister(uint8 modeBitMask) +{ + NOR_Clock_MOD_SRC |= modeBitMask & (uint8)NOR_Clock_MODE_MASK; +} + + +/******************************************************************************* +* Function Name: NOR_Clock_ClearModeRegister +******************************************************************************** +* +* Summary: +* Clears flags that control the operating mode of the clock. This function +* only changes flags from 1 to 0; flags that are already 0 will remain +* unchanged. To set flags, use the SetModeRegister function. The clock must be +* disabled before changing the mode. +* +* Parameters: +* clkMode: Bit mask containing the bits to clear. For PSoC 3 and PSoC 5, +* clkMode should be a set of the following optional bits or'ed together. +* - CYCLK_EARLY Enable early phase mode. Rising edge of output clock will +* occur when the divider count reaches half of the divide +* value. +* - CYCLK_DUTY Enable 50% duty cycle output. When enabled, the output clock +* is asserted for approximately half of its period. When +* disabled, the output clock is asserted for one period of the +* source clock. +* - CYCLK_SYNC Enable output synchronization to master clock. This should +* be enabled for all synchronous clocks. +* See the Technical Reference Manual for details about setting the mode of +* the clock. Specifically, see the CLKDIST.DCFG.CFG2 register. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_ClearModeRegister(uint8 modeBitMask) +{ + NOR_Clock_MOD_SRC &= (uint8)(~modeBitMask) | (uint8)(~(uint8)(NOR_Clock_MODE_MASK)); +} + + +/******************************************************************************* +* Function Name: NOR_Clock_GetModeRegister +******************************************************************************** +* +* Summary: +* Gets the clock mode register value. +* +* Parameters: +* None +* +* Returns: +* Bit mask representing the enabled mode bits. See the SetModeRegister and +* ClearModeRegister descriptions for details about the mode bits. +* +*******************************************************************************/ +uint8 NOR_Clock_GetModeRegister(void) +{ + return NOR_Clock_MOD_SRC & (uint8)(NOR_Clock_MODE_MASK); +} + + +/******************************************************************************* +* Function Name: NOR_Clock_SetSourceRegister +******************************************************************************** +* +* Summary: +* Sets the input source of the clock. The clock must be disabled before +* changing the source. The old and new clock sources must be running. +* +* Parameters: +* clkSource: For PSoC 3 and PSoC 5 devices, clkSource should be one of the +* following input sources: +* - CYCLK_SRC_SEL_SYNC_DIG +* - CYCLK_SRC_SEL_IMO +* - CYCLK_SRC_SEL_XTALM +* - CYCLK_SRC_SEL_ILO +* - CYCLK_SRC_SEL_PLL +* - CYCLK_SRC_SEL_XTALK +* - CYCLK_SRC_SEL_DSI_G +* - CYCLK_SRC_SEL_DSI_D/CYCLK_SRC_SEL_DSI_A +* See the Technical Reference Manual for details on clock sources. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_SetSourceRegister(uint8 clkSource) +{ + uint16 currDiv = NOR_Clock_GetDividerRegister(); + uint8 oldSrc = NOR_Clock_GetSourceRegister(); + + if (((oldSrc != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching to Master and divider is 1, set SSS, which will output master, */ + /* then set the source so we are consistent. */ + NOR_Clock_MOD_SRC |= CYCLK_SSS; + NOR_Clock_MOD_SRC = + (NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource; + } + else if (((oldSrc == ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D)) && + (clkSource != ((uint8)CYCLK_SRC_SEL_CLK_SYNC_D))) && (currDiv == 0u)) + { + /* Switching from Master to not and divider is 1, set source, so we don't */ + /* lock when we clear SSS. */ + NOR_Clock_MOD_SRC = + (NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource; + NOR_Clock_MOD_SRC &= (uint8)(~CYCLK_SSS); + } + else + { + NOR_Clock_MOD_SRC = + (NOR_Clock_MOD_SRC & (uint8)(~NOR_Clock_SRC_SEL_MSK)) | clkSource; + } +} + + +/******************************************************************************* +* Function Name: NOR_Clock_GetSourceRegister +******************************************************************************** +* +* Summary: +* Gets the input source of the clock. +* +* Parameters: +* None +* +* Returns: +* The input source of the clock. See SetSourceRegister for details. +* +*******************************************************************************/ +uint8 NOR_Clock_GetSourceRegister(void) +{ + return NOR_Clock_MOD_SRC & NOR_Clock_SRC_SEL_MSK; +} + + +#if defined(NOR_Clock__CFG3) + + +/******************************************************************************* +* Function Name: NOR_Clock_SetPhaseRegister +******************************************************************************** +* +* Summary: +* Sets the phase delay of the analog clock. This function is only available +* for analog clocks. The clock must be disabled before changing the phase +* delay to avoid glitches. +* +* Parameters: +* clkPhase: Amount to delay the phase of the clock, in 1.0ns increments. +* clkPhase must be from 1 to 11 inclusive. Other values, including 0, +* disable the clock. clkPhase = 1 produces a 0ns delay and clkPhase = 11 +* produces a 10ns delay. +* +* Returns: +* None +* +*******************************************************************************/ +void NOR_Clock_SetPhaseRegister(uint8 clkPhase) +{ + NOR_Clock_PHASE = clkPhase & NOR_Clock_PHASE_MASK; +} + + +/******************************************************************************* +* Function Name: NOR_Clock_GetPhase +******************************************************************************** +* +* Summary: +* Gets the phase delay of the analog clock. This function is only available +* for analog clocks. +* +* Parameters: +* None +* +* Returns: +* Phase of the analog clock. See SetPhaseRegister for details. +* +*******************************************************************************/ +uint8 NOR_Clock_GetPhaseRegister(void) +{ + return NOR_Clock_PHASE & NOR_Clock_PHASE_MASK; +} + +#endif /* NOR_Clock__CFG3 */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.h new file mode 100644 index 0000000..837e277 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_Clock.h @@ -0,0 +1,124 @@ +/******************************************************************************* +* File Name: NOR_Clock.h +* Version 2.20 +* +* Description: +* Provides the function and constant definitions for the clock component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_CLOCK_NOR_Clock_H) +#define CY_CLOCK_NOR_Clock_H + +#include +#include + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +/* Check to see if required defines such as CY_PSOC5LP are available */ +/* They are defined starting with cy_boot v3.0 */ +#if !defined (CY_PSOC5LP) + #error Component cy_clock_v2_20 requires cy_boot v3.0 or later +#endif /* (CY_PSOC5LP) */ + + +/*************************************** +* Function Prototypes +***************************************/ + +void NOR_Clock_Start(void) ; +void NOR_Clock_Stop(void) ; + +#if(CY_PSOC3 || CY_PSOC5LP) +void NOR_Clock_StopBlock(void) ; +#endif /* (CY_PSOC3 || CY_PSOC5LP) */ + +void NOR_Clock_StandbyPower(uint8 state) ; +void NOR_Clock_SetDividerRegister(uint16 clkDivider, uint8 restart) + ; +uint16 NOR_Clock_GetDividerRegister(void) ; +void NOR_Clock_SetModeRegister(uint8 modeBitMask) ; +void NOR_Clock_ClearModeRegister(uint8 modeBitMask) ; +uint8 NOR_Clock_GetModeRegister(void) ; +void NOR_Clock_SetSourceRegister(uint8 clkSource) ; +uint8 NOR_Clock_GetSourceRegister(void) ; +#if defined(NOR_Clock__CFG3) +void NOR_Clock_SetPhaseRegister(uint8 clkPhase) ; +uint8 NOR_Clock_GetPhaseRegister(void) ; +#endif /* defined(NOR_Clock__CFG3) */ + +#define NOR_Clock_Enable() NOR_Clock_Start() +#define NOR_Clock_Disable() NOR_Clock_Stop() +#define NOR_Clock_SetDivider(clkDivider) NOR_Clock_SetDividerRegister(clkDivider, 1u) +#define NOR_Clock_SetDividerValue(clkDivider) NOR_Clock_SetDividerRegister((clkDivider) - 1u, 1u) +#define NOR_Clock_SetMode(clkMode) NOR_Clock_SetModeRegister(clkMode) +#define NOR_Clock_SetSource(clkSource) NOR_Clock_SetSourceRegister(clkSource) +#if defined(NOR_Clock__CFG3) +#define NOR_Clock_SetPhase(clkPhase) NOR_Clock_SetPhaseRegister(clkPhase) +#define NOR_Clock_SetPhaseValue(clkPhase) NOR_Clock_SetPhaseRegister((clkPhase) + 1u) +#endif /* defined(NOR_Clock__CFG3) */ + + +/*************************************** +* Registers +***************************************/ + +/* Register to enable or disable the clock */ +#define NOR_Clock_CLKEN (* (reg8 *) NOR_Clock__PM_ACT_CFG) +#define NOR_Clock_CLKEN_PTR ((reg8 *) NOR_Clock__PM_ACT_CFG) + +/* Register to enable or disable the clock */ +#define NOR_Clock_CLKSTBY (* (reg8 *) NOR_Clock__PM_STBY_CFG) +#define NOR_Clock_CLKSTBY_PTR ((reg8 *) NOR_Clock__PM_STBY_CFG) + +/* Clock LSB divider configuration register. */ +#define NOR_Clock_DIV_LSB (* (reg8 *) NOR_Clock__CFG0) +#define NOR_Clock_DIV_LSB_PTR ((reg8 *) NOR_Clock__CFG0) +#define NOR_Clock_DIV_PTR ((reg16 *) NOR_Clock__CFG0) + +/* Clock MSB divider configuration register. */ +#define NOR_Clock_DIV_MSB (* (reg8 *) NOR_Clock__CFG1) +#define NOR_Clock_DIV_MSB_PTR ((reg8 *) NOR_Clock__CFG1) + +/* Mode and source configuration register */ +#define NOR_Clock_MOD_SRC (* (reg8 *) NOR_Clock__CFG2) +#define NOR_Clock_MOD_SRC_PTR ((reg8 *) NOR_Clock__CFG2) + +#if defined(NOR_Clock__CFG3) +/* Analog clock phase configuration register */ +#define NOR_Clock_PHASE (* (reg8 *) NOR_Clock__CFG3) +#define NOR_Clock_PHASE_PTR ((reg8 *) NOR_Clock__CFG3) +#endif /* defined(NOR_Clock__CFG3) */ + + +/************************************** +* Register Constants +**************************************/ + +/* Power manager register masks */ +#define NOR_Clock_CLKEN_MASK NOR_Clock__PM_ACT_MSK +#define NOR_Clock_CLKSTBY_MASK NOR_Clock__PM_STBY_MSK + +/* CFG2 field masks */ +#define NOR_Clock_SRC_SEL_MSK NOR_Clock__CFG2_SRC_SEL_MASK +#define NOR_Clock_MODE_MASK (~(NOR_Clock_SRC_SEL_MSK)) + +#if defined(NOR_Clock__CFG3) +/* CFG3 phase mask */ +#define NOR_Clock_PHASE_MASK NOR_Clock__CFG3_PHASE_DLY_MASK +#endif /* defined(NOR_Clock__CFG3) */ + +#endif /* CY_CLOCK_NOR_Clock_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.c new file mode 100644 index 0000000..fa4f937 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: NOR_SCK.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "NOR_SCK.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + NOR_SCK__PORT == 15 && ((NOR_SCK__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: NOR_SCK_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet NOR_SCK_SUT.c usage_NOR_SCK_Write +*******************************************************************************/ +void NOR_SCK_Write(uint8 value) +{ + uint8 staticBits = (NOR_SCK_DR & (uint8)(~NOR_SCK_MASK)); + NOR_SCK_DR = staticBits | ((uint8)(value << NOR_SCK_SHIFT) & NOR_SCK_MASK); +} + + +/******************************************************************************* +* Function Name: NOR_SCK_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet NOR_SCK_SUT.c usage_NOR_SCK_SetDriveMode +*******************************************************************************/ +void NOR_SCK_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(NOR_SCK_0, mode); +} + + +/******************************************************************************* +* Function Name: NOR_SCK_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet NOR_SCK_SUT.c usage_NOR_SCK_Read +*******************************************************************************/ +uint8 NOR_SCK_Read(void) +{ + return (NOR_SCK_PS & NOR_SCK_MASK) >> NOR_SCK_SHIFT; +} + + +/******************************************************************************* +* Function Name: NOR_SCK_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred NOR_SCK_Read() API because the +* NOR_SCK_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet NOR_SCK_SUT.c usage_NOR_SCK_ReadDataReg +*******************************************************************************/ +uint8 NOR_SCK_ReadDataReg(void) +{ + return (NOR_SCK_DR & NOR_SCK_MASK) >> NOR_SCK_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(NOR_SCK_INTSTAT) + + /******************************************************************************* + * Function Name: NOR_SCK_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use NOR_SCK_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - NOR_SCK_0_INTR (First pin in the list) + * - NOR_SCK_1_INTR (Second pin in the list) + * - ... + * - NOR_SCK_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet NOR_SCK_SUT.c usage_NOR_SCK_SetInterruptMode + *******************************************************************************/ + void NOR_SCK_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & NOR_SCK_0_INTR) != 0u) + { + NOR_SCK_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: NOR_SCK_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet NOR_SCK_SUT.c usage_NOR_SCK_ClearInterrupt + *******************************************************************************/ + uint8 NOR_SCK_ClearInterrupt(void) + { + return (NOR_SCK_INTSTAT & NOR_SCK_MASK) >> NOR_SCK_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.h new file mode 100644 index 0000000..40db117 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: NOR_SCK.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SCK_H) /* Pins NOR_SCK_H */ +#define CY_PINS_NOR_SCK_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "NOR_SCK_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + NOR_SCK__PORT == 15 && ((NOR_SCK__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void NOR_SCK_Write(uint8 value); +void NOR_SCK_SetDriveMode(uint8 mode); +uint8 NOR_SCK_ReadDataReg(void); +uint8 NOR_SCK_Read(void); +void NOR_SCK_SetInterruptMode(uint16 position, uint16 mode); +uint8 NOR_SCK_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the NOR_SCK_SetDriveMode() function. + * @{ + */ + #define NOR_SCK_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define NOR_SCK_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define NOR_SCK_DM_RES_UP PIN_DM_RES_UP + #define NOR_SCK_DM_RES_DWN PIN_DM_RES_DWN + #define NOR_SCK_DM_OD_LO PIN_DM_OD_LO + #define NOR_SCK_DM_OD_HI PIN_DM_OD_HI + #define NOR_SCK_DM_STRONG PIN_DM_STRONG + #define NOR_SCK_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define NOR_SCK_MASK NOR_SCK__MASK +#define NOR_SCK_SHIFT NOR_SCK__SHIFT +#define NOR_SCK_WIDTH 1u + +/* Interrupt constants */ +#if defined(NOR_SCK__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in NOR_SCK_SetInterruptMode() function. + * @{ + */ + #define NOR_SCK_INTR_NONE (uint16)(0x0000u) + #define NOR_SCK_INTR_RISING (uint16)(0x0001u) + #define NOR_SCK_INTR_FALLING (uint16)(0x0002u) + #define NOR_SCK_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define NOR_SCK_INTR_MASK (0x01u) +#endif /* (NOR_SCK__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define NOR_SCK_PS (* (reg8 *) NOR_SCK__PS) +/* Data Register */ +#define NOR_SCK_DR (* (reg8 *) NOR_SCK__DR) +/* Port Number */ +#define NOR_SCK_PRT_NUM (* (reg8 *) NOR_SCK__PRT) +/* Connect to Analog Globals */ +#define NOR_SCK_AG (* (reg8 *) NOR_SCK__AG) +/* Analog MUX bux enable */ +#define NOR_SCK_AMUX (* (reg8 *) NOR_SCK__AMUX) +/* Bidirectional Enable */ +#define NOR_SCK_BIE (* (reg8 *) NOR_SCK__BIE) +/* Bit-mask for Aliased Register Access */ +#define NOR_SCK_BIT_MASK (* (reg8 *) NOR_SCK__BIT_MASK) +/* Bypass Enable */ +#define NOR_SCK_BYP (* (reg8 *) NOR_SCK__BYP) +/* Port wide control signals */ +#define NOR_SCK_CTL (* (reg8 *) NOR_SCK__CTL) +/* Drive Modes */ +#define NOR_SCK_DM0 (* (reg8 *) NOR_SCK__DM0) +#define NOR_SCK_DM1 (* (reg8 *) NOR_SCK__DM1) +#define NOR_SCK_DM2 (* (reg8 *) NOR_SCK__DM2) +/* Input Buffer Disable Override */ +#define NOR_SCK_INP_DIS (* (reg8 *) NOR_SCK__INP_DIS) +/* LCD Common or Segment Drive */ +#define NOR_SCK_LCD_COM_SEG (* (reg8 *) NOR_SCK__LCD_COM_SEG) +/* Enable Segment LCD */ +#define NOR_SCK_LCD_EN (* (reg8 *) NOR_SCK__LCD_EN) +/* Slew Rate Control */ +#define NOR_SCK_SLW (* (reg8 *) NOR_SCK__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define NOR_SCK_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SCK__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define NOR_SCK_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SCK__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define NOR_SCK_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SCK__PRTDSI__OE_SEL0) +#define NOR_SCK_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SCK__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define NOR_SCK_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SCK__PRTDSI__OUT_SEL0) +#define NOR_SCK_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SCK__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define NOR_SCK_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SCK__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(NOR_SCK__SIO_CFG) + #define NOR_SCK_SIO_HYST_EN (* (reg8 *) NOR_SCK__SIO_HYST_EN) + #define NOR_SCK_SIO_REG_HIFREQ (* (reg8 *) NOR_SCK__SIO_REG_HIFREQ) + #define NOR_SCK_SIO_CFG (* (reg8 *) NOR_SCK__SIO_CFG) + #define NOR_SCK_SIO_DIFF (* (reg8 *) NOR_SCK__SIO_DIFF) +#endif /* (NOR_SCK__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(NOR_SCK__INTSTAT) + #define NOR_SCK_INTSTAT (* (reg8 *) NOR_SCK__INTSTAT) + #define NOR_SCK_SNAP (* (reg8 *) NOR_SCK__SNAP) + + #define NOR_SCK_0_INTTYPE_REG (* (reg8 *) NOR_SCK__0__INTTYPE) +#endif /* (NOR_SCK__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_NOR_SCK_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK_aliases.h new file mode 100644 index 0000000..3801382 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SCK_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: NOR_SCK.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SCK_ALIASES_H) /* Pins NOR_SCK_ALIASES_H */ +#define CY_PINS_NOR_SCK_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define NOR_SCK_0 (NOR_SCK__0__PC) +#define NOR_SCK_0_INTR ((uint16)((uint16)0x0001u << NOR_SCK__0__SHIFT)) + +#define NOR_SCK_INTR_ALL ((uint16)(NOR_SCK_0_INTR)) + +#endif /* End Pins NOR_SCK_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.c new file mode 100644 index 0000000..bc9aaff --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: NOR_SI.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "NOR_SI.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + NOR_SI__PORT == 15 && ((NOR_SI__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: NOR_SI_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet NOR_SI_SUT.c usage_NOR_SI_Write +*******************************************************************************/ +void NOR_SI_Write(uint8 value) +{ + uint8 staticBits = (NOR_SI_DR & (uint8)(~NOR_SI_MASK)); + NOR_SI_DR = staticBits | ((uint8)(value << NOR_SI_SHIFT) & NOR_SI_MASK); +} + + +/******************************************************************************* +* Function Name: NOR_SI_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet NOR_SI_SUT.c usage_NOR_SI_SetDriveMode +*******************************************************************************/ +void NOR_SI_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(NOR_SI_0, mode); +} + + +/******************************************************************************* +* Function Name: NOR_SI_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet NOR_SI_SUT.c usage_NOR_SI_Read +*******************************************************************************/ +uint8 NOR_SI_Read(void) +{ + return (NOR_SI_PS & NOR_SI_MASK) >> NOR_SI_SHIFT; +} + + +/******************************************************************************* +* Function Name: NOR_SI_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred NOR_SI_Read() API because the +* NOR_SI_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet NOR_SI_SUT.c usage_NOR_SI_ReadDataReg +*******************************************************************************/ +uint8 NOR_SI_ReadDataReg(void) +{ + return (NOR_SI_DR & NOR_SI_MASK) >> NOR_SI_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(NOR_SI_INTSTAT) + + /******************************************************************************* + * Function Name: NOR_SI_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use NOR_SI_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - NOR_SI_0_INTR (First pin in the list) + * - NOR_SI_1_INTR (Second pin in the list) + * - ... + * - NOR_SI_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet NOR_SI_SUT.c usage_NOR_SI_SetInterruptMode + *******************************************************************************/ + void NOR_SI_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & NOR_SI_0_INTR) != 0u) + { + NOR_SI_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: NOR_SI_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet NOR_SI_SUT.c usage_NOR_SI_ClearInterrupt + *******************************************************************************/ + uint8 NOR_SI_ClearInterrupt(void) + { + return (NOR_SI_INTSTAT & NOR_SI_MASK) >> NOR_SI_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.h new file mode 100644 index 0000000..be45b97 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: NOR_SI.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SI_H) /* Pins NOR_SI_H */ +#define CY_PINS_NOR_SI_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "NOR_SI_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + NOR_SI__PORT == 15 && ((NOR_SI__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void NOR_SI_Write(uint8 value); +void NOR_SI_SetDriveMode(uint8 mode); +uint8 NOR_SI_ReadDataReg(void); +uint8 NOR_SI_Read(void); +void NOR_SI_SetInterruptMode(uint16 position, uint16 mode); +uint8 NOR_SI_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the NOR_SI_SetDriveMode() function. + * @{ + */ + #define NOR_SI_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define NOR_SI_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define NOR_SI_DM_RES_UP PIN_DM_RES_UP + #define NOR_SI_DM_RES_DWN PIN_DM_RES_DWN + #define NOR_SI_DM_OD_LO PIN_DM_OD_LO + #define NOR_SI_DM_OD_HI PIN_DM_OD_HI + #define NOR_SI_DM_STRONG PIN_DM_STRONG + #define NOR_SI_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define NOR_SI_MASK NOR_SI__MASK +#define NOR_SI_SHIFT NOR_SI__SHIFT +#define NOR_SI_WIDTH 1u + +/* Interrupt constants */ +#if defined(NOR_SI__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in NOR_SI_SetInterruptMode() function. + * @{ + */ + #define NOR_SI_INTR_NONE (uint16)(0x0000u) + #define NOR_SI_INTR_RISING (uint16)(0x0001u) + #define NOR_SI_INTR_FALLING (uint16)(0x0002u) + #define NOR_SI_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define NOR_SI_INTR_MASK (0x01u) +#endif /* (NOR_SI__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define NOR_SI_PS (* (reg8 *) NOR_SI__PS) +/* Data Register */ +#define NOR_SI_DR (* (reg8 *) NOR_SI__DR) +/* Port Number */ +#define NOR_SI_PRT_NUM (* (reg8 *) NOR_SI__PRT) +/* Connect to Analog Globals */ +#define NOR_SI_AG (* (reg8 *) NOR_SI__AG) +/* Analog MUX bux enable */ +#define NOR_SI_AMUX (* (reg8 *) NOR_SI__AMUX) +/* Bidirectional Enable */ +#define NOR_SI_BIE (* (reg8 *) NOR_SI__BIE) +/* Bit-mask for Aliased Register Access */ +#define NOR_SI_BIT_MASK (* (reg8 *) NOR_SI__BIT_MASK) +/* Bypass Enable */ +#define NOR_SI_BYP (* (reg8 *) NOR_SI__BYP) +/* Port wide control signals */ +#define NOR_SI_CTL (* (reg8 *) NOR_SI__CTL) +/* Drive Modes */ +#define NOR_SI_DM0 (* (reg8 *) NOR_SI__DM0) +#define NOR_SI_DM1 (* (reg8 *) NOR_SI__DM1) +#define NOR_SI_DM2 (* (reg8 *) NOR_SI__DM2) +/* Input Buffer Disable Override */ +#define NOR_SI_INP_DIS (* (reg8 *) NOR_SI__INP_DIS) +/* LCD Common or Segment Drive */ +#define NOR_SI_LCD_COM_SEG (* (reg8 *) NOR_SI__LCD_COM_SEG) +/* Enable Segment LCD */ +#define NOR_SI_LCD_EN (* (reg8 *) NOR_SI__LCD_EN) +/* Slew Rate Control */ +#define NOR_SI_SLW (* (reg8 *) NOR_SI__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define NOR_SI_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SI__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define NOR_SI_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SI__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define NOR_SI_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SI__PRTDSI__OE_SEL0) +#define NOR_SI_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SI__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define NOR_SI_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SI__PRTDSI__OUT_SEL0) +#define NOR_SI_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SI__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define NOR_SI_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SI__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(NOR_SI__SIO_CFG) + #define NOR_SI_SIO_HYST_EN (* (reg8 *) NOR_SI__SIO_HYST_EN) + #define NOR_SI_SIO_REG_HIFREQ (* (reg8 *) NOR_SI__SIO_REG_HIFREQ) + #define NOR_SI_SIO_CFG (* (reg8 *) NOR_SI__SIO_CFG) + #define NOR_SI_SIO_DIFF (* (reg8 *) NOR_SI__SIO_DIFF) +#endif /* (NOR_SI__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(NOR_SI__INTSTAT) + #define NOR_SI_INTSTAT (* (reg8 *) NOR_SI__INTSTAT) + #define NOR_SI_SNAP (* (reg8 *) NOR_SI__SNAP) + + #define NOR_SI_0_INTTYPE_REG (* (reg8 *) NOR_SI__0__INTTYPE) +#endif /* (NOR_SI__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_NOR_SI_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI_aliases.h new file mode 100644 index 0000000..03d953f --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SI_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: NOR_SI.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SI_ALIASES_H) /* Pins NOR_SI_ALIASES_H */ +#define CY_PINS_NOR_SI_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define NOR_SI_0 (NOR_SI__0__PC) +#define NOR_SI_0_INTR ((uint16)((uint16)0x0001u << NOR_SI__0__SHIFT)) + +#define NOR_SI_INTR_ALL ((uint16)(NOR_SI_0_INTR)) + +#endif /* End Pins NOR_SI_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.c new file mode 100644 index 0000000..4a0a554 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: NOR_SO.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "NOR_SO.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + NOR_SO__PORT == 15 && ((NOR_SO__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: NOR_SO_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet NOR_SO_SUT.c usage_NOR_SO_Write +*******************************************************************************/ +void NOR_SO_Write(uint8 value) +{ + uint8 staticBits = (NOR_SO_DR & (uint8)(~NOR_SO_MASK)); + NOR_SO_DR = staticBits | ((uint8)(value << NOR_SO_SHIFT) & NOR_SO_MASK); +} + + +/******************************************************************************* +* Function Name: NOR_SO_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet NOR_SO_SUT.c usage_NOR_SO_SetDriveMode +*******************************************************************************/ +void NOR_SO_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(NOR_SO_0, mode); +} + + +/******************************************************************************* +* Function Name: NOR_SO_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet NOR_SO_SUT.c usage_NOR_SO_Read +*******************************************************************************/ +uint8 NOR_SO_Read(void) +{ + return (NOR_SO_PS & NOR_SO_MASK) >> NOR_SO_SHIFT; +} + + +/******************************************************************************* +* Function Name: NOR_SO_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred NOR_SO_Read() API because the +* NOR_SO_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet NOR_SO_SUT.c usage_NOR_SO_ReadDataReg +*******************************************************************************/ +uint8 NOR_SO_ReadDataReg(void) +{ + return (NOR_SO_DR & NOR_SO_MASK) >> NOR_SO_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(NOR_SO_INTSTAT) + + /******************************************************************************* + * Function Name: NOR_SO_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use NOR_SO_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - NOR_SO_0_INTR (First pin in the list) + * - NOR_SO_1_INTR (Second pin in the list) + * - ... + * - NOR_SO_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet NOR_SO_SUT.c usage_NOR_SO_SetInterruptMode + *******************************************************************************/ + void NOR_SO_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & NOR_SO_0_INTR) != 0u) + { + NOR_SO_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: NOR_SO_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet NOR_SO_SUT.c usage_NOR_SO_ClearInterrupt + *******************************************************************************/ + uint8 NOR_SO_ClearInterrupt(void) + { + return (NOR_SO_INTSTAT & NOR_SO_MASK) >> NOR_SO_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.h new file mode 100644 index 0000000..970ffaf --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: NOR_SO.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SO_H) /* Pins NOR_SO_H */ +#define CY_PINS_NOR_SO_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "NOR_SO_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + NOR_SO__PORT == 15 && ((NOR_SO__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void NOR_SO_Write(uint8 value); +void NOR_SO_SetDriveMode(uint8 mode); +uint8 NOR_SO_ReadDataReg(void); +uint8 NOR_SO_Read(void); +void NOR_SO_SetInterruptMode(uint16 position, uint16 mode); +uint8 NOR_SO_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the NOR_SO_SetDriveMode() function. + * @{ + */ + #define NOR_SO_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define NOR_SO_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define NOR_SO_DM_RES_UP PIN_DM_RES_UP + #define NOR_SO_DM_RES_DWN PIN_DM_RES_DWN + #define NOR_SO_DM_OD_LO PIN_DM_OD_LO + #define NOR_SO_DM_OD_HI PIN_DM_OD_HI + #define NOR_SO_DM_STRONG PIN_DM_STRONG + #define NOR_SO_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define NOR_SO_MASK NOR_SO__MASK +#define NOR_SO_SHIFT NOR_SO__SHIFT +#define NOR_SO_WIDTH 1u + +/* Interrupt constants */ +#if defined(NOR_SO__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in NOR_SO_SetInterruptMode() function. + * @{ + */ + #define NOR_SO_INTR_NONE (uint16)(0x0000u) + #define NOR_SO_INTR_RISING (uint16)(0x0001u) + #define NOR_SO_INTR_FALLING (uint16)(0x0002u) + #define NOR_SO_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define NOR_SO_INTR_MASK (0x01u) +#endif /* (NOR_SO__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define NOR_SO_PS (* (reg8 *) NOR_SO__PS) +/* Data Register */ +#define NOR_SO_DR (* (reg8 *) NOR_SO__DR) +/* Port Number */ +#define NOR_SO_PRT_NUM (* (reg8 *) NOR_SO__PRT) +/* Connect to Analog Globals */ +#define NOR_SO_AG (* (reg8 *) NOR_SO__AG) +/* Analog MUX bux enable */ +#define NOR_SO_AMUX (* (reg8 *) NOR_SO__AMUX) +/* Bidirectional Enable */ +#define NOR_SO_BIE (* (reg8 *) NOR_SO__BIE) +/* Bit-mask for Aliased Register Access */ +#define NOR_SO_BIT_MASK (* (reg8 *) NOR_SO__BIT_MASK) +/* Bypass Enable */ +#define NOR_SO_BYP (* (reg8 *) NOR_SO__BYP) +/* Port wide control signals */ +#define NOR_SO_CTL (* (reg8 *) NOR_SO__CTL) +/* Drive Modes */ +#define NOR_SO_DM0 (* (reg8 *) NOR_SO__DM0) +#define NOR_SO_DM1 (* (reg8 *) NOR_SO__DM1) +#define NOR_SO_DM2 (* (reg8 *) NOR_SO__DM2) +/* Input Buffer Disable Override */ +#define NOR_SO_INP_DIS (* (reg8 *) NOR_SO__INP_DIS) +/* LCD Common or Segment Drive */ +#define NOR_SO_LCD_COM_SEG (* (reg8 *) NOR_SO__LCD_COM_SEG) +/* Enable Segment LCD */ +#define NOR_SO_LCD_EN (* (reg8 *) NOR_SO__LCD_EN) +/* Slew Rate Control */ +#define NOR_SO_SLW (* (reg8 *) NOR_SO__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define NOR_SO_PRTDSI__CAPS_SEL (* (reg8 *) NOR_SO__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define NOR_SO_PRTDSI__DBL_SYNC_IN (* (reg8 *) NOR_SO__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define NOR_SO_PRTDSI__OE_SEL0 (* (reg8 *) NOR_SO__PRTDSI__OE_SEL0) +#define NOR_SO_PRTDSI__OE_SEL1 (* (reg8 *) NOR_SO__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define NOR_SO_PRTDSI__OUT_SEL0 (* (reg8 *) NOR_SO__PRTDSI__OUT_SEL0) +#define NOR_SO_PRTDSI__OUT_SEL1 (* (reg8 *) NOR_SO__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define NOR_SO_PRTDSI__SYNC_OUT (* (reg8 *) NOR_SO__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(NOR_SO__SIO_CFG) + #define NOR_SO_SIO_HYST_EN (* (reg8 *) NOR_SO__SIO_HYST_EN) + #define NOR_SO_SIO_REG_HIFREQ (* (reg8 *) NOR_SO__SIO_REG_HIFREQ) + #define NOR_SO_SIO_CFG (* (reg8 *) NOR_SO__SIO_CFG) + #define NOR_SO_SIO_DIFF (* (reg8 *) NOR_SO__SIO_DIFF) +#endif /* (NOR_SO__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(NOR_SO__INTSTAT) + #define NOR_SO_INTSTAT (* (reg8 *) NOR_SO__INTSTAT) + #define NOR_SO_SNAP (* (reg8 *) NOR_SO__SNAP) + + #define NOR_SO_0_INTTYPE_REG (* (reg8 *) NOR_SO__0__INTTYPE) +#endif /* (NOR_SO__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_NOR_SO_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO_aliases.h new file mode 100644 index 0000000..46f455c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SO_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: NOR_SO.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_NOR_SO_ALIASES_H) /* Pins NOR_SO_ALIASES_H */ +#define CY_PINS_NOR_SO_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define NOR_SO_0 (NOR_SO__0__PC) +#define NOR_SO_0_INTR ((uint16)((uint16)0x0001u << NOR_SO__0__SHIFT)) + +#define NOR_SO_INTR_ALL ((uint16)(NOR_SO_0_INTR)) + +#endif /* End Pins NOR_SO_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.c new file mode 100644 index 0000000..5a93af1 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.c @@ -0,0 +1,1154 @@ +/******************************************************************************* +* File Name: NOR_SPI.c +* Version 2.50 +* +* Description: +* This file provides all API functionality of the SPI Master component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "NOR_SPI_PVT.h" + +#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + volatile uint8 NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE]; + volatile uint8 NOR_SPI_txBufferFull; + volatile uint8 NOR_SPI_txBufferRead; + volatile uint8 NOR_SPI_txBufferWrite; +#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + +#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + volatile uint8 NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE]; + volatile uint8 NOR_SPI_rxBufferFull; + volatile uint8 NOR_SPI_rxBufferRead; + volatile uint8 NOR_SPI_rxBufferWrite; +#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + +uint8 NOR_SPI_initVar = 0u; + +volatile uint8 NOR_SPI_swStatusTx; +volatile uint8 NOR_SPI_swStatusRx; + + +/******************************************************************************* +* Function Name: NOR_SPI_Init +******************************************************************************** +* +* Summary: +* Inits/Restores default SPIM configuration provided with customizer. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* When this function is called it initializes all of the necessary parameters +* for execution. i.e. setting the initial interrupt mask, configuring the +* interrupt service routine, configuring the bit-counter parameters and +* clearing the FIFO and Status Register. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_Init(void) +{ + /* Initialize the Bit counter */ + NOR_SPI_COUNTER_PERIOD_REG = NOR_SPI_BITCTR_INIT; + + /* Init TX ISR */ + #if(0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) + CyIntDisable (NOR_SPI_TX_ISR_NUMBER); + CyIntSetPriority (NOR_SPI_TX_ISR_NUMBER, NOR_SPI_TX_ISR_PRIORITY); + (void) CyIntSetVector(NOR_SPI_TX_ISR_NUMBER, &NOR_SPI_TX_ISR); + #endif /* (0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) */ + + /* Init RX ISR */ + #if(0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) + CyIntDisable (NOR_SPI_RX_ISR_NUMBER); + CyIntSetPriority (NOR_SPI_RX_ISR_NUMBER, NOR_SPI_RX_ISR_PRIORITY); + (void) CyIntSetVector(NOR_SPI_RX_ISR_NUMBER, &NOR_SPI_RX_ISR); + #endif /* (0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) */ + + /* Clear any stray data from the RX and TX FIFO */ + NOR_SPI_ClearFIFO(); + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + NOR_SPI_rxBufferFull = 0u; + NOR_SPI_rxBufferRead = 0u; + NOR_SPI_rxBufferWrite = 0u; + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + NOR_SPI_txBufferFull = 0u; + NOR_SPI_txBufferRead = 0u; + NOR_SPI_txBufferWrite = 0u; + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + (void) NOR_SPI_ReadTxStatus(); /* Clear Tx status and swStatusTx */ + (void) NOR_SPI_ReadRxStatus(); /* Clear Rx status and swStatusRx */ + + /* Configure TX and RX interrupt mask */ + NOR_SPI_TX_STATUS_MASK_REG = NOR_SPI_TX_INIT_INTERRUPTS_MASK; + NOR_SPI_RX_STATUS_MASK_REG = NOR_SPI_RX_INIT_INTERRUPTS_MASK; +} + + +/******************************************************************************* +* Function Name: NOR_SPI_Enable +******************************************************************************** +* +* Summary: +* Enable SPIM component. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void NOR_SPI_Enable(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + NOR_SPI_COUNTER_CONTROL_REG |= NOR_SPI_CNTR_ENABLE; + NOR_SPI_TX_STATUS_ACTL_REG |= NOR_SPI_INT_ENABLE; + NOR_SPI_RX_STATUS_ACTL_REG |= NOR_SPI_INT_ENABLE; + CyExitCriticalSection(enableInterrupts); + + #if(0u != NOR_SPI_INTERNAL_CLOCK) + NOR_SPI_IntClock_Enable(); + #endif /* (0u != NOR_SPI_INTERNAL_CLOCK) */ + + NOR_SPI_EnableTxInt(); + NOR_SPI_EnableRxInt(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_Start +******************************************************************************** +* +* Summary: +* Initialize and Enable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_initVar - used to check initial configuration, modified on +* first function call. +* +* Theory: +* Enable the clock input to enable operation. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_Start(void) +{ + if(0u == NOR_SPI_initVar) + { + NOR_SPI_Init(); + NOR_SPI_initVar = 1u; + } + + NOR_SPI_Enable(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_Stop +******************************************************************************** +* +* Summary: +* Disable the SPI Master component. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the clock input to enable operation. +* +*******************************************************************************/ +void NOR_SPI_Stop(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + NOR_SPI_TX_STATUS_ACTL_REG &= ((uint8) ~NOR_SPI_INT_ENABLE); + NOR_SPI_RX_STATUS_ACTL_REG &= ((uint8) ~NOR_SPI_INT_ENABLE); + CyExitCriticalSection(enableInterrupts); + + #if(0u != NOR_SPI_INTERNAL_CLOCK) + NOR_SPI_IntClock_Disable(); + #endif /* (0u != NOR_SPI_INTERNAL_CLOCK) */ + + NOR_SPI_DisableTxInt(); + NOR_SPI_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_EnableTxInt +******************************************************************************** +* +* Summary: +* Enable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_EnableTxInt(void) +{ + #if(0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) + CyIntEnable(NOR_SPI_TX_ISR_NUMBER); + #endif /* (0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_EnableRxInt +******************************************************************************** +* +* Summary: +* Enable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_EnableRxInt(void) +{ + #if(0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) + CyIntEnable(NOR_SPI_RX_ISR_NUMBER); + #endif /* (0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_DisableTxInt +******************************************************************************** +* +* Summary: +* Disable internal Tx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Tx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_DisableTxInt(void) +{ + #if(0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) + CyIntDisable(NOR_SPI_TX_ISR_NUMBER); + #endif /* (0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_DisableRxInt +******************************************************************************** +* +* Summary: +* Disable internal Rx interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal Rx interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_DisableRxInt(void) +{ + #if(0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) + CyIntDisable(NOR_SPI_RX_ISR_NUMBER); + #endif /* (0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_SetTxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void NOR_SPI_SetTxInterruptMode(uint8 intSrc) +{ + NOR_SPI_TX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: NOR_SPI_SetRxInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void NOR_SPI_SetRxInterruptMode(uint8 intSrc) +{ + NOR_SPI_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ReadTxStatus +******************************************************************************** +* +* Summary: +* Read the Tx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Tx status register. +* +* Global variables: +* NOR_SPI_swStatusTx - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Tx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 NOR_SPI_ReadTxStatus(void) +{ + uint8 tmpStatus; + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + NOR_SPI_DisableTxInt(); + + tmpStatus = NOR_SPI_GET_STATUS_TX(NOR_SPI_swStatusTx); + NOR_SPI_swStatusTx = 0u; + + NOR_SPI_EnableTxInt(); + + #else + + tmpStatus = NOR_SPI_TX_STATUS_REG; + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ReadRxStatus +******************************************************************************** +* +* Summary: +* Read the Rx status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the Rx status register. +* +* Global variables: +* NOR_SPI_swStatusRx - used to store in software Rx status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the Rx status register for error +* detection and flow control. +* +* Side Effects: +* Clear Rx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 NOR_SPI_ReadRxStatus(void) +{ + uint8 tmpStatus; + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + NOR_SPI_DisableRxInt(); + + tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx); + NOR_SPI_swStatusRx = 0u; + + NOR_SPI_EnableRxInt(); + + #else + + tmpStatus = NOR_SPI_RX_STATUS_REG; + + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_WriteTxData +******************************************************************************** +* +* Summary: +* Write a byte of data to be sent across the SPI. +* +* Parameters: +* txDataByte: The data value to send across the SPI. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call if TX Software Buffer is used. +* NOR_SPI_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE] - used to store +* data to sending, modified every function call if TX Software Buffer is used. +* +* Theory: +* Allows the user to transmit any byte of data in a single transfer. +* +* Side Effects: +* If this function is called again before the previous byte is finished then +* the next byte will be appended to the transfer with no time between +* the byte transfers. Clear Tx status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_WriteTxData(uint8 txData) +{ + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + + uint8 tempStatus; + uint8 tmpTxBufferRead; + + /* Block if TX buffer is FULL: don't overwrite */ + do + { + tmpTxBufferRead = NOR_SPI_txBufferRead; + if(0u == tmpTxBufferRead) + { + tmpTxBufferRead = (NOR_SPI_TX_BUFFER_SIZE - 1u); + } + else + { + tmpTxBufferRead--; + } + + }while(tmpTxBufferRead == NOR_SPI_txBufferWrite); + + /* Disable TX interrupt to protect global veriables */ + NOR_SPI_DisableTxInt(); + + tempStatus = NOR_SPI_GET_STATUS_TX(NOR_SPI_swStatusTx); + NOR_SPI_swStatusTx = tempStatus; + + + if((NOR_SPI_txBufferRead == NOR_SPI_txBufferWrite) && + (0u != (NOR_SPI_swStatusTx & NOR_SPI_STS_TX_FIFO_NOT_FULL))) + { + /* Put data element into the TX FIFO */ + CY_SET_REG8(NOR_SPI_TXDATA_PTR, txData); + } + else + { + /* Add to the TX software buffer */ + NOR_SPI_txBufferWrite++; + if(NOR_SPI_txBufferWrite >= NOR_SPI_TX_BUFFER_SIZE) + { + NOR_SPI_txBufferWrite = 0u; + } + + if(NOR_SPI_txBufferWrite == NOR_SPI_txBufferRead) + { + NOR_SPI_txBufferRead++; + if(NOR_SPI_txBufferRead >= NOR_SPI_TX_BUFFER_SIZE) + { + NOR_SPI_txBufferRead = 0u; + } + NOR_SPI_txBufferFull = 1u; + } + + NOR_SPI_txBuffer[NOR_SPI_txBufferWrite] = txData; + + NOR_SPI_TX_STATUS_MASK_REG |= NOR_SPI_STS_TX_FIFO_NOT_FULL; + } + + NOR_SPI_EnableTxInt(); + + #else + /* Wait until TX FIFO has a place */ + while(0u == (NOR_SPI_TX_STATUS_REG & NOR_SPI_STS_TX_FIFO_NOT_FULL)) + { + } + + /* Put data element into the TX FIFO */ + CY_SET_REG8(NOR_SPI_TXDATA_PTR, txData); + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ReadRxData +******************************************************************************** +* +* Summary: +* Read the next byte of data received across the SPI. +* +* Parameters: +* None. +* +* Return: +* The next byte of data read from the FIFO. +* +* Global variables: +* NOR_SPI_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* NOR_SPI_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function +* call if RX Software Buffer is used. +* NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE] - used to store +* received data. +* +* Theory: +* Allows the user to read a byte of data received. +* +* Side Effects: +* Will return invalid data if the FIFO is empty. The user should Call +* GetRxBufferSize() and if it returns a non-zero value then it is safe to call +* ReadByte() function. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 NOR_SPI_ReadRxData(void) +{ + uint8 rxData; + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + NOR_SPI_DisableRxInt(); + + if(NOR_SPI_rxBufferRead != NOR_SPI_rxBufferWrite) + { + if(0u == NOR_SPI_rxBufferFull) + { + NOR_SPI_rxBufferRead++; + if(NOR_SPI_rxBufferRead >= NOR_SPI_RX_BUFFER_SIZE) + { + NOR_SPI_rxBufferRead = 0u; + } + } + else + { + NOR_SPI_rxBufferFull = 0u; + } + } + + rxData = NOR_SPI_rxBuffer[NOR_SPI_rxBufferRead]; + + NOR_SPI_EnableRxInt(); + + #else + + rxData = CY_GET_REG8(NOR_SPI_RXDATA_PTR); + + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + return(rxData); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_GetRxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the RX buffer. +* If RX Software Buffer not used then function return 0 if FIFO empty or 1 if +* FIFO not empty. In another case function return size of RX Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the RX buffer. +* +* Global variables: +* NOR_SPI_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer. +* NOR_SPI_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 NOR_SPI_GetRxBufferSize(void) +{ + uint8 size; + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + + /* Disable RX interrupt to protect global veriables */ + NOR_SPI_DisableRxInt(); + + if(NOR_SPI_rxBufferRead == NOR_SPI_rxBufferWrite) + { + size = 0u; + } + else if(NOR_SPI_rxBufferRead < NOR_SPI_rxBufferWrite) + { + size = (NOR_SPI_rxBufferWrite - NOR_SPI_rxBufferRead); + } + else + { + size = (NOR_SPI_RX_BUFFER_SIZE - NOR_SPI_rxBufferRead) + NOR_SPI_rxBufferWrite; + } + + NOR_SPI_EnableRxInt(); + + #else + + /* We can only know if there is data in the RX FIFO */ + size = (0u != (NOR_SPI_RX_STATUS_REG & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) ? 1u : 0u; + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_GetTxBufferSize +******************************************************************************** +* +* Summary: +* Returns the number of bytes/words of data currently held in the TX buffer. +* If TX Software Buffer not used then function return 0 - if FIFO empty, 1 - if +* FIFO not full, 4 - if FIFO full. In another case function return size of TX +* Software Buffer. +* +* Parameters: +* None. +* +* Return: +* Integer count of the number of bytes/words in the TX buffer. +* +* Global variables: +* NOR_SPI_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* NOR_SPI_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +uint8 NOR_SPI_GetTxBufferSize(void) +{ + uint8 size; + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + NOR_SPI_DisableTxInt(); + + if(NOR_SPI_txBufferRead == NOR_SPI_txBufferWrite) + { + size = 0u; + } + else if(NOR_SPI_txBufferRead < NOR_SPI_txBufferWrite) + { + size = (NOR_SPI_txBufferWrite - NOR_SPI_txBufferRead); + } + else + { + size = (NOR_SPI_TX_BUFFER_SIZE - NOR_SPI_txBufferRead) + NOR_SPI_txBufferWrite; + } + + NOR_SPI_EnableTxInt(); + + #else + + size = NOR_SPI_TX_STATUS_REG; + + if(0u != (size & NOR_SPI_STS_TX_FIFO_EMPTY)) + { + size = 0u; + } + else if(0u != (size & NOR_SPI_STS_TX_FIFO_NOT_FULL)) + { + size = 1u; + } + else + { + size = NOR_SPI_FIFO_SIZE; + } + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + return(size); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ClearRxBuffer +******************************************************************************** +* +* Summary: +* Clear the RX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer, modified every function +* call - resets to zero. +* NOR_SPI_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any received data not read from the RAM buffer will be lost when overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_ClearRxBuffer(void) +{ + /* Clear Hardware RX FIFO */ + while(0u !=(NOR_SPI_RX_STATUS_REG & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(NOR_SPI_RXDATA_PTR); + } + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + /* Disable RX interrupt to protect global veriables */ + NOR_SPI_DisableRxInt(); + + NOR_SPI_rxBufferFull = 0u; + NOR_SPI_rxBufferRead = 0u; + NOR_SPI_rxBufferWrite = 0u; + + NOR_SPI_EnableRxInt(); + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ClearTxBuffer +******************************************************************************** +* +* Summary: +* Clear the TX RAM buffer by setting the read and write pointers both to zero. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer, modified every function +* call - resets to zero. +* NOR_SPI_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified every function call - +* resets to zero. +* +* Theory: +* Setting the pointers to zero makes the system believe there is no data to +* read and writing will resume at address 0 overwriting any data that may have +* remained in the RAM. +* +* Side Effects: +* Any data not yet transmitted from the RAM buffer will be lost when +* overwritten. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_ClearTxBuffer(void) +{ + uint8 enableInterrupts; + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + NOR_SPI_AUX_CONTROL_DP0_REG |= ((uint8) NOR_SPI_TX_FIFO_CLR); + NOR_SPI_AUX_CONTROL_DP0_REG &= ((uint8) ~NOR_SPI_TX_FIFO_CLR); + + #if(NOR_SPI_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + NOR_SPI_AUX_CONTROL_DP1_REG |= ((uint8) NOR_SPI_TX_FIFO_CLR); + NOR_SPI_AUX_CONTROL_DP1_REG &= ((uint8) ~NOR_SPI_TX_FIFO_CLR); + #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + /* Disable TX interrupt to protect global veriables */ + NOR_SPI_DisableTxInt(); + + NOR_SPI_txBufferFull = 0u; + NOR_SPI_txBufferRead = 0u; + NOR_SPI_txBufferWrite = 0u; + + /* Buffer is EMPTY: disable TX FIFO NOT FULL interrupt */ + NOR_SPI_TX_STATUS_MASK_REG &= ((uint8) ~NOR_SPI_STS_TX_FIFO_NOT_FULL); + + NOR_SPI_EnableTxInt(); + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ +} + + +#if(0u != NOR_SPI_BIDIRECTIONAL_MODE) + /******************************************************************************* + * Function Name: NOR_SPI_TxEnable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to transmit. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void NOR_SPI_TxEnable(void) + { + NOR_SPI_CONTROL_REG |= NOR_SPI_CTRL_TX_SIGNAL_EN; + } + + + /******************************************************************************* + * Function Name: NOR_SPI_TxDisable + ******************************************************************************** + * + * Summary: + * If the SPI master is configured to use a single bi-directional pin then this + * will set the bi-directional pin to receive. + * + * Parameters: + * None. + * + * Return: + * None. + * + *******************************************************************************/ + void NOR_SPI_TxDisable(void) + { + NOR_SPI_CONTROL_REG &= ((uint8) ~NOR_SPI_CTRL_TX_SIGNAL_EN); + } + +#endif /* (0u != NOR_SPI_BIDIRECTIONAL_MODE) */ + + +/******************************************************************************* +* Function Name: NOR_SPI_PutArray +******************************************************************************** +* +* Summary: +* Write available data from ROM/RAM to the TX buffer while space is available +* in the TX buffer. Keep trying until all data is passed to the TX buffer. +* +* Parameters: +* *buffer: Pointer to the location in RAM containing the data to send +* byteCount: The number of bytes to move to the transmit buffer. +* +* Return: +* None. +* +* Side Effects: +* Will stay in this routine until all data has been sent. May get locked in +* this loop if data is not being initiated by the master if there is not +* enough room in the TX FIFO. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_PutArray(const uint8 buffer[], uint8 byteCount) + +{ + uint8 bufIndex; + + bufIndex = 0u; + + while(byteCount > 0u) + { + NOR_SPI_WriteTxData(buffer[bufIndex]); + bufIndex++; + byteCount--; + } +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ClearFIFO +******************************************************************************** +* +* Summary: +* Clear the RX and TX FIFO's of all data for a fresh start. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Side Effects: +* Clear status register of the component. +* +*******************************************************************************/ +void NOR_SPI_ClearFIFO(void) +{ + uint8 enableInterrupts; + + /* Clear Hardware RX FIFO */ + while(0u !=(NOR_SPI_RX_STATUS_REG & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) + { + (void) CY_GET_REG8(NOR_SPI_RXDATA_PTR); + } + + enableInterrupts = CyEnterCriticalSection(); + /* Clear TX FIFO */ + NOR_SPI_AUX_CONTROL_DP0_REG |= ((uint8) NOR_SPI_TX_FIFO_CLR); + NOR_SPI_AUX_CONTROL_DP0_REG &= ((uint8) ~NOR_SPI_TX_FIFO_CLR); + + #if(NOR_SPI_USE_SECOND_DATAPATH) + /* Clear TX FIFO for 2nd Datapath */ + NOR_SPI_AUX_CONTROL_DP1_REG |= ((uint8) NOR_SPI_TX_FIFO_CLR); + NOR_SPI_AUX_CONTROL_DP1_REG &= ((uint8) ~NOR_SPI_TX_FIFO_CLR); + #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */ + CyExitCriticalSection(enableInterrupts); +} + + +/* Following functions are for version Compatibility, they are obsolete. +* Please do not use it in new projects. +*/ + + +/******************************************************************************* +* Function Name: NOR_SPI_EnableInt +******************************************************************************** +* +* Summary: +* Enable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Enable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_EnableInt(void) +{ + NOR_SPI_EnableRxInt(); + NOR_SPI_EnableTxInt(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_DisableInt +******************************************************************************** +* +* Summary: +* Disable internal interrupt generation. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Theory: +* Disable the internal interrupt output -or- the interrupt component itself. +* +*******************************************************************************/ +void NOR_SPI_DisableInt(void) +{ + NOR_SPI_DisableTxInt(); + NOR_SPI_DisableRxInt(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_SetInterruptMode +******************************************************************************** +* +* Summary: +* Configure which status bits trigger an interrupt event. +* +* Parameters: +* intSrc: An or'd combination of the desired status bit masks (defined in the +* header file). +* +* Return: +* None. +* +* Theory: +* Enables the output of specific status bits to the interrupt controller. +* +*******************************************************************************/ +void NOR_SPI_SetInterruptMode(uint8 intSrc) +{ + NOR_SPI_TX_STATUS_MASK_REG = (intSrc & ((uint8) ~NOR_SPI_STS_SPI_IDLE)); + NOR_SPI_RX_STATUS_MASK_REG = intSrc; +} + + +/******************************************************************************* +* Function Name: NOR_SPI_ReadStatus +******************************************************************************** +* +* Summary: +* Read the status register for the component. +* +* Parameters: +* None. +* +* Return: +* Contents of the status register. +* +* Global variables: +* NOR_SPI_swStatus - used to store in software status register, +* modified every function call - resets to zero. +* +* Theory: +* Allows the user and the API to read the status register for error detection +* and flow control. +* +* Side Effects: +* Clear status register of the component. +* +* Reentrant: +* No. +* +*******************************************************************************/ +uint8 NOR_SPI_ReadStatus(void) +{ + uint8 tmpStatus; + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED || NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + + NOR_SPI_DisableInt(); + + tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx); + tmpStatus |= NOR_SPI_GET_STATUS_TX(NOR_SPI_swStatusTx); + tmpStatus &= ((uint8) ~NOR_SPI_STS_SPI_IDLE); + + NOR_SPI_swStatusTx = 0u; + NOR_SPI_swStatusRx = 0u; + + NOR_SPI_EnableInt(); + + #else + + tmpStatus = NOR_SPI_RX_STATUS_REG; + tmpStatus |= NOR_SPI_TX_STATUS_REG; + tmpStatus &= ((uint8) ~NOR_SPI_STS_SPI_IDLE); + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED || NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + return(tmpStatus); +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h new file mode 100644 index 0000000..c0f90bd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI.h @@ -0,0 +1,367 @@ +/******************************************************************************* +* File Name: NOR_SPI.h +* Version 2.50 +* +* Description: +* Contains the function prototypes, constants and register definition +* of the SPI Master Component. +* +* Note: +* None +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_NOR_SPI_H) +#define CY_SPIM_NOR_SPI_H + +#include "cyfitter.h" +#include "cytypes.h" +#include "CyLib.h" /* For CyEnterCriticalSection() and CyExitCriticalSection() functions */ + + +/*************************************** +* Conditional Compilation Parameters +***************************************/ + +#define NOR_SPI_INTERNAL_CLOCK (0u) + +#if(0u != NOR_SPI_INTERNAL_CLOCK) + #include "NOR_SPI_IntClock.h" +#endif /* (0u != NOR_SPI_INTERNAL_CLOCK) */ + +#define NOR_SPI_MODE (1u) +#define NOR_SPI_DATA_WIDTH (8u) +#define NOR_SPI_MODE_USE_ZERO (1u) +#define NOR_SPI_BIDIRECTIONAL_MODE (0u) + +/* Internal interrupt handling */ +#define NOR_SPI_TX_BUFFER_SIZE (4u) +#define NOR_SPI_RX_BUFFER_SIZE (4u) +#define NOR_SPI_INTERNAL_TX_INT_ENABLED (0u) +#define NOR_SPI_INTERNAL_RX_INT_ENABLED (0u) + +#define NOR_SPI_SINGLE_REG_SIZE (8u) +#define NOR_SPI_USE_SECOND_DATAPATH (NOR_SPI_DATA_WIDTH > NOR_SPI_SINGLE_REG_SIZE) + +#define NOR_SPI_FIFO_SIZE (4u) +#define NOR_SPI_TX_SOFTWARE_BUF_ENABLED ((0u != NOR_SPI_INTERNAL_TX_INT_ENABLED) && \ + (NOR_SPI_TX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE)) + +#define NOR_SPI_RX_SOFTWARE_BUF_ENABLED ((0u != NOR_SPI_INTERNAL_RX_INT_ENABLED) && \ + (NOR_SPI_RX_BUFFER_SIZE > NOR_SPI_FIFO_SIZE)) + + +/*************************************** +* Data Struct Definition +***************************************/ + +/* Sleep Mode API Support */ +typedef struct +{ + uint8 enableState; + uint8 cntrPeriod; +} NOR_SPI_BACKUP_STRUCT; + + +/*************************************** +* Function Prototypes +***************************************/ + +void NOR_SPI_Init(void) ; +void NOR_SPI_Enable(void) ; +void NOR_SPI_Start(void) ; +void NOR_SPI_Stop(void) ; + +void NOR_SPI_EnableTxInt(void) ; +void NOR_SPI_EnableRxInt(void) ; +void NOR_SPI_DisableTxInt(void) ; +void NOR_SPI_DisableRxInt(void) ; + +void NOR_SPI_Sleep(void) ; +void NOR_SPI_Wakeup(void) ; +void NOR_SPI_SaveConfig(void) ; +void NOR_SPI_RestoreConfig(void) ; + +void NOR_SPI_SetTxInterruptMode(uint8 intSrc) ; +void NOR_SPI_SetRxInterruptMode(uint8 intSrc) ; +uint8 NOR_SPI_ReadTxStatus(void) ; +uint8 NOR_SPI_ReadRxStatus(void) ; +void NOR_SPI_WriteTxData(uint8 txData) \ + ; +uint8 NOR_SPI_ReadRxData(void) \ + ; +uint8 NOR_SPI_GetRxBufferSize(void) ; +uint8 NOR_SPI_GetTxBufferSize(void) ; +void NOR_SPI_ClearRxBuffer(void) ; +void NOR_SPI_ClearTxBuffer(void) ; +void NOR_SPI_ClearFIFO(void) ; +void NOR_SPI_PutArray(const uint8 buffer[], uint8 byteCount) \ + ; + +#if(0u != NOR_SPI_BIDIRECTIONAL_MODE) + void NOR_SPI_TxEnable(void) ; + void NOR_SPI_TxDisable(void) ; +#endif /* (0u != NOR_SPI_BIDIRECTIONAL_MODE) */ + +CY_ISR_PROTO(NOR_SPI_TX_ISR); +CY_ISR_PROTO(NOR_SPI_RX_ISR); + + +/*************************************** +* Variable with external linkage +***************************************/ + +extern uint8 NOR_SPI_initVar; + + +/*************************************** +* API Constants +***************************************/ + +#define NOR_SPI_TX_ISR_NUMBER ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_NUMBER)) +#define NOR_SPI_RX_ISR_NUMBER ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_NUMBER)) + +#define NOR_SPI_TX_ISR_PRIORITY ((uint8) (NOR_SPI_TxInternalInterrupt__INTC_PRIOR_NUM)) +#define NOR_SPI_RX_ISR_PRIORITY ((uint8) (NOR_SPI_RxInternalInterrupt__INTC_PRIOR_NUM)) + + +/*************************************** +* Initial Parameter Constants +***************************************/ + +#define NOR_SPI_INT_ON_SPI_DONE ((uint8) (0u << NOR_SPI_STS_SPI_DONE_SHIFT)) +#define NOR_SPI_INT_ON_TX_EMPTY ((uint8) (0u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) +#define NOR_SPI_INT_ON_TX_NOT_FULL ((uint8) (0u << \ + NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define NOR_SPI_INT_ON_BYTE_COMP ((uint8) (0u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT)) +#define NOR_SPI_INT_ON_SPI_IDLE ((uint8) (0u << NOR_SPI_STS_SPI_IDLE_SHIFT)) + +/* Disable TX_NOT_FULL if software buffer is used */ +#define NOR_SPI_INT_ON_TX_NOT_FULL_DEF ((NOR_SPI_TX_SOFTWARE_BUF_ENABLED) ? \ + (0u) : (NOR_SPI_INT_ON_TX_NOT_FULL)) + +/* TX interrupt mask */ +#define NOR_SPI_TX_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_SPI_DONE | \ + NOR_SPI_INT_ON_TX_EMPTY | \ + NOR_SPI_INT_ON_TX_NOT_FULL_DEF | \ + NOR_SPI_INT_ON_BYTE_COMP | \ + NOR_SPI_INT_ON_SPI_IDLE) + +#define NOR_SPI_INT_ON_RX_FULL ((uint8) (0u << \ + NOR_SPI_STS_RX_FIFO_FULL_SHIFT)) +#define NOR_SPI_INT_ON_RX_NOT_EMPTY ((uint8) (0u << \ + NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define NOR_SPI_INT_ON_RX_OVER ((uint8) (0u << \ + NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* RX interrupt mask */ +#define NOR_SPI_RX_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_RX_FULL | \ + NOR_SPI_INT_ON_RX_NOT_EMPTY | \ + NOR_SPI_INT_ON_RX_OVER) +/* Nubmer of bits to receive/transmit */ +#define NOR_SPI_BITCTR_INIT (((uint8) (NOR_SPI_DATA_WIDTH << 1u)) - 1u) + + +/*************************************** +* Registers +***************************************/ +#if(CY_PSOC3 || CY_PSOC5) + #define NOR_SPI_TXDATA_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG) + #define NOR_SPI_TXDATA_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG) + #define NOR_SPI_RXDATA_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG) + #define NOR_SPI_RXDATA_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG) +#else /* PSOC4 */ + #if(NOR_SPI_USE_SECOND_DATAPATH) + #define NOR_SPI_TXDATA_REG (* (reg16 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define NOR_SPI_TXDATA_PTR ( (reg16 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG) + #define NOR_SPI_RXDATA_REG (* (reg16 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #define NOR_SPI_RXDATA_PTR ( (reg16 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG) + #else + #define NOR_SPI_TXDATA_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG) + #define NOR_SPI_TXDATA_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG) + #define NOR_SPI_RXDATA_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG) + #define NOR_SPI_RXDATA_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG) + #endif /* (NOR_SPI_USE_SECOND_DATAPATH) */ +#endif /* (CY_PSOC3 || CY_PSOC5) */ + +#define NOR_SPI_AUX_CONTROL_DP0_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) +#define NOR_SPI_AUX_CONTROL_DP0_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG) + +#if(NOR_SPI_USE_SECOND_DATAPATH) + #define NOR_SPI_AUX_CONTROL_DP1_REG (* (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) + #define NOR_SPI_AUX_CONTROL_DP1_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_sR8_Dp_u1__DP_AUX_CTL_REG) +#endif /* (NOR_SPI_USE_SECOND_DATAPATH) */ + +#define NOR_SPI_COUNTER_PERIOD_REG (* (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG) +#define NOR_SPI_COUNTER_PERIOD_PTR ( (reg8 *) NOR_SPI_BSPIM_BitCounter__PERIOD_REG) +#define NOR_SPI_COUNTER_CONTROL_REG (* (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) +#define NOR_SPI_COUNTER_CONTROL_PTR ( (reg8 *) NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG) + +#define NOR_SPI_TX_STATUS_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG) +#define NOR_SPI_TX_STATUS_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_REG) +#define NOR_SPI_RX_STATUS_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG) +#define NOR_SPI_RX_STATUS_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_REG) + +#define NOR_SPI_CONTROL_REG (* (reg8 *) \ + NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG) +#define NOR_SPI_CONTROL_PTR ( (reg8 *) \ + NOR_SPI_BSPIM_BidirMode_CtrlReg__CONTROL_REG) + +#define NOR_SPI_TX_STATUS_MASK_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG) +#define NOR_SPI_TX_STATUS_MASK_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__MASK_REG) +#define NOR_SPI_RX_STATUS_MASK_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG) +#define NOR_SPI_RX_STATUS_MASK_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__MASK_REG) + +#define NOR_SPI_TX_STATUS_ACTL_REG (* (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define NOR_SPI_TX_STATUS_ACTL_PTR ( (reg8 *) NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG) +#define NOR_SPI_RX_STATUS_ACTL_REG (* (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) +#define NOR_SPI_RX_STATUS_ACTL_PTR ( (reg8 *) NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG) + +#if(NOR_SPI_USE_SECOND_DATAPATH) + #define NOR_SPI_AUX_CONTROLDP1 (NOR_SPI_AUX_CONTROL_DP1_REG) +#endif /* (NOR_SPI_USE_SECOND_DATAPATH) */ + + +/*************************************** +* Register Constants +***************************************/ + +/* Status Register Definitions */ +#define NOR_SPI_STS_SPI_DONE_SHIFT (0x00u) +#define NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT (0x01u) +#define NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT (0x02u) +#define NOR_SPI_STS_BYTE_COMPLETE_SHIFT (0x03u) +#define NOR_SPI_STS_SPI_IDLE_SHIFT (0x04u) +#define NOR_SPI_STS_RX_FIFO_FULL_SHIFT (0x04u) +#define NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT (0x05u) +#define NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT (0x06u) + +#define NOR_SPI_STS_SPI_DONE ((uint8) (0x01u << NOR_SPI_STS_SPI_DONE_SHIFT)) +#define NOR_SPI_STS_TX_FIFO_EMPTY ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_EMPTY_SHIFT)) +#define NOR_SPI_STS_TX_FIFO_NOT_FULL ((uint8) (0x01u << NOR_SPI_STS_TX_FIFO_NOT_FULL_SHIFT)) +#define NOR_SPI_STS_BYTE_COMPLETE ((uint8) (0x01u << NOR_SPI_STS_BYTE_COMPLETE_SHIFT)) +#define NOR_SPI_STS_SPI_IDLE ((uint8) (0x01u << NOR_SPI_STS_SPI_IDLE_SHIFT)) +#define NOR_SPI_STS_RX_FIFO_FULL ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_FULL_SHIFT)) +#define NOR_SPI_STS_RX_FIFO_NOT_EMPTY ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_NOT_EMPTY_SHIFT)) +#define NOR_SPI_STS_RX_FIFO_OVERRUN ((uint8) (0x01u << NOR_SPI_STS_RX_FIFO_OVERRUN_SHIFT)) + +/* TX and RX masks for clear on read bits */ +#define NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK (0x09u) +#define NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK (0x40u) + +/* StatusI Register Interrupt Enable Control Bits */ +/* As defined by the Register map for the AUX Control Register */ +#define NOR_SPI_INT_ENABLE (0x10u) /* Enable interrupt from statusi */ +#define NOR_SPI_TX_FIFO_CLR (0x01u) /* F0 - TX FIFO */ +#define NOR_SPI_RX_FIFO_CLR (0x02u) /* F1 - RX FIFO */ +#define NOR_SPI_FIFO_CLR (NOR_SPI_TX_FIFO_CLR | NOR_SPI_RX_FIFO_CLR) + +/* Bit Counter (7-bit) Control Register Bit Definitions */ +/* As defined by the Register map for the AUX Control Register */ +#define NOR_SPI_CNTR_ENABLE (0x20u) /* Enable CNT7 */ + +/* Bi-Directional mode control bit */ +#define NOR_SPI_CTRL_TX_SIGNAL_EN (0x01u) + +/* Datapath Auxillary Control Register definitions */ +#define NOR_SPI_AUX_CTRL_FIFO0_CLR (0x01u) +#define NOR_SPI_AUX_CTRL_FIFO1_CLR (0x02u) +#define NOR_SPI_AUX_CTRL_FIFO0_LVL (0x04u) +#define NOR_SPI_AUX_CTRL_FIFO1_LVL (0x08u) +#define NOR_SPI_STATUS_ACTL_INT_EN_MASK (0x10u) + +/* Component disabled */ +#define NOR_SPI_DISABLED (0u) + + +/*************************************** +* Macros +***************************************/ + +/* Returns true if componentn enabled */ +#define NOR_SPI_IS_ENABLED (0u != (NOR_SPI_TX_STATUS_ACTL_REG & NOR_SPI_INT_ENABLE)) + +/* Retuns TX status register */ +#define NOR_SPI_GET_STATUS_TX(swTxSts) ( (uint8)(NOR_SPI_TX_STATUS_REG | \ + ((swTxSts) & NOR_SPI_TX_STS_CLR_ON_RD_BYTES_MASK)) ) +/* Retuns RX status register */ +#define NOR_SPI_GET_STATUS_RX(swRxSts) ( (uint8)(NOR_SPI_RX_STATUS_REG | \ + ((swRxSts) & NOR_SPI_RX_STS_CLR_ON_RD_BYTES_MASK)) ) + + +/*************************************** +* The following code is DEPRECATED and +* should not be used in new projects. +***************************************/ + +#define NOR_SPI_WriteByte NOR_SPI_WriteTxData +#define NOR_SPI_ReadByte NOR_SPI_ReadRxData +void NOR_SPI_SetInterruptMode(uint8 intSrc) ; +uint8 NOR_SPI_ReadStatus(void) ; +void NOR_SPI_EnableInt(void) ; +void NOR_SPI_DisableInt(void) ; + +#define NOR_SPI_TXDATA (NOR_SPI_TXDATA_REG) +#define NOR_SPI_RXDATA (NOR_SPI_RXDATA_REG) +#define NOR_SPI_AUX_CONTROLDP0 (NOR_SPI_AUX_CONTROL_DP0_REG) +#define NOR_SPI_TXBUFFERREAD (NOR_SPI_txBufferRead) +#define NOR_SPI_TXBUFFERWRITE (NOR_SPI_txBufferWrite) +#define NOR_SPI_RXBUFFERREAD (NOR_SPI_rxBufferRead) +#define NOR_SPI_RXBUFFERWRITE (NOR_SPI_rxBufferWrite) + +#define NOR_SPI_COUNTER_PERIOD (NOR_SPI_COUNTER_PERIOD_REG) +#define NOR_SPI_COUNTER_CONTROL (NOR_SPI_COUNTER_CONTROL_REG) +#define NOR_SPI_STATUS (NOR_SPI_TX_STATUS_REG) +#define NOR_SPI_CONTROL (NOR_SPI_CONTROL_REG) +#define NOR_SPI_STATUS_MASK (NOR_SPI_TX_STATUS_MASK_REG) +#define NOR_SPI_STATUS_ACTL (NOR_SPI_TX_STATUS_ACTL_REG) + +#define NOR_SPI_INIT_INTERRUPTS_MASK (NOR_SPI_INT_ON_SPI_DONE | \ + NOR_SPI_INT_ON_TX_EMPTY | \ + NOR_SPI_INT_ON_TX_NOT_FULL_DEF | \ + NOR_SPI_INT_ON_RX_FULL | \ + NOR_SPI_INT_ON_RX_NOT_EMPTY | \ + NOR_SPI_INT_ON_RX_OVER | \ + NOR_SPI_INT_ON_BYTE_COMP) + +#define NOR_SPI_DataWidth (NOR_SPI_DATA_WIDTH) +#define NOR_SPI_InternalClockUsed (NOR_SPI_INTERNAL_CLOCK) +#define NOR_SPI_InternalTxInterruptEnabled (NOR_SPI_INTERNAL_TX_INT_ENABLED) +#define NOR_SPI_InternalRxInterruptEnabled (NOR_SPI_INTERNAL_RX_INT_ENABLED) +#define NOR_SPI_ModeUseZero (NOR_SPI_MODE_USE_ZERO) +#define NOR_SPI_BidirectionalMode (NOR_SPI_BIDIRECTIONAL_MODE) +#define NOR_SPI_Mode (NOR_SPI_MODE) +#define NOR_SPI_DATAWIDHT (NOR_SPI_DATA_WIDTH) +#define NOR_SPI_InternalInterruptEnabled (0u) + +#define NOR_SPI_TXBUFFERSIZE (NOR_SPI_TX_BUFFER_SIZE) +#define NOR_SPI_RXBUFFERSIZE (NOR_SPI_RX_BUFFER_SIZE) + +#define NOR_SPI_TXBUFFER NOR_SPI_txBuffer +#define NOR_SPI_RXBUFFER NOR_SPI_rxBuffer + +#endif /* (CY_SPIM_NOR_SPI_H) */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_INT.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_INT.c new file mode 100644 index 0000000..05fa53b --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_INT.c @@ -0,0 +1,206 @@ +/******************************************************************************* +* File Name: NOR_SPI_INT.c +* Version 2.50 +* +* Description: +* This file provides all Interrupt Service Routine (ISR) for the SPI Master +* component. +* +* Note: +* None. +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "NOR_SPI_PVT.h" + + +/* User code required at start of ISR */ +/* `#START NOR_SPI_ISR_START_DEF` */ + +/* `#END` */ + + +/******************************************************************************* +* Function Name: NOR_SPI_TX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for TX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_txBufferWrite - used for the account of the bytes which +* have been written down in the TX software buffer. +* NOR_SPI_txBufferRead - used for the account of the bytes which +* have been read from the TX software buffer, modified when exist data to +* sending and FIFO Not Full. +* NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE] - used to store +* data to sending. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(NOR_SPI_TX_ISR) +{ + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + #ifdef NOR_SPI_TX_ISR_ENTRY_CALLBACK + NOR_SPI_TX_ISR_EntryCallback(); + #endif /* NOR_SPI_TX_ISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START NOR_SPI_TX_ISR_START` */ + + /* `#END` */ + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + /* Check if TX data buffer is not empty and there is space in TX FIFO */ + while(NOR_SPI_txBufferRead != NOR_SPI_txBufferWrite) + { + tmpStatus = NOR_SPI_GET_STATUS_TX(NOR_SPI_swStatusTx); + NOR_SPI_swStatusTx = tmpStatus; + + if(0u != (NOR_SPI_swStatusTx & NOR_SPI_STS_TX_FIFO_NOT_FULL)) + { + if(0u == NOR_SPI_txBufferFull) + { + NOR_SPI_txBufferRead++; + + if(NOR_SPI_txBufferRead >= NOR_SPI_TX_BUFFER_SIZE) + { + NOR_SPI_txBufferRead = 0u; + } + } + else + { + NOR_SPI_txBufferFull = 0u; + } + + /* Put data element into the TX FIFO */ + CY_SET_REG8(NOR_SPI_TXDATA_PTR, + NOR_SPI_txBuffer[NOR_SPI_txBufferRead]); + } + else + { + break; + } + } + + if(NOR_SPI_txBufferRead == NOR_SPI_txBufferWrite) + { + /* TX Buffer is EMPTY: disable interrupt on TX NOT FULL */ + NOR_SPI_TX_STATUS_MASK_REG &= ((uint8) ~NOR_SPI_STS_TX_FIFO_NOT_FULL); + } + + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START NOR_SPI_TX_ISR_END` */ + + /* `#END` */ + + #ifdef NOR_SPI_TX_ISR_EXIT_CALLBACK + NOR_SPI_TX_ISR_ExitCallback(); + #endif /* NOR_SPI_TX_ISR_EXIT_CALLBACK */ +} + + +/******************************************************************************* +* Function Name: NOR_SPI_RX_ISR +******************************************************************************** +* +* Summary: +* Interrupt Service Routine for RX portion of the SPI Master. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global variables: +* NOR_SPI_rxBufferWrite - used for the account of the bytes which +* have been written down in the RX software buffer modified when FIFO contains +* new data. +* NOR_SPI_rxBufferRead - used for the account of the bytes which +* have been read from the RX software buffer, modified when overflow occurred. +* NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE] - used to store +* received data, modified when FIFO contains new data. +* All described above Global variables are used when Software Buffer is used. +* +*******************************************************************************/ +CY_ISR(NOR_SPI_RX_ISR) +{ + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + uint8 tmpStatus; + uint8 rxData; + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + #ifdef NOR_SPI_RX_ISR_ENTRY_CALLBACK + NOR_SPI_RX_ISR_EntryCallback(); + #endif /* NOR_SPI_RX_ISR_ENTRY_CALLBACK */ + + /* User code required at start of ISR */ + /* `#START NOR_SPI_RX_ISR_START` */ + + /* `#END` */ + + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + + tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx); + NOR_SPI_swStatusRx = tmpStatus; + + /* Check if RX data FIFO has some data to be moved into the RX Buffer */ + while(0u != (NOR_SPI_swStatusRx & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) + { + rxData = CY_GET_REG8(NOR_SPI_RXDATA_PTR); + + /* Set next pointer. */ + NOR_SPI_rxBufferWrite++; + if(NOR_SPI_rxBufferWrite >= NOR_SPI_RX_BUFFER_SIZE) + { + NOR_SPI_rxBufferWrite = 0u; + } + + if(NOR_SPI_rxBufferWrite == NOR_SPI_rxBufferRead) + { + NOR_SPI_rxBufferRead++; + if(NOR_SPI_rxBufferRead >= NOR_SPI_RX_BUFFER_SIZE) + { + NOR_SPI_rxBufferRead = 0u; + } + + NOR_SPI_rxBufferFull = 1u; + } + + /* Move data from the FIFO to the Buffer */ + NOR_SPI_rxBuffer[NOR_SPI_rxBufferWrite] = rxData; + + tmpStatus = NOR_SPI_GET_STATUS_RX(NOR_SPI_swStatusRx); + NOR_SPI_swStatusRx = tmpStatus; + } + + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + /* User code required at end of ISR (Optional) */ + /* `#START NOR_SPI_RX_ISR_END` */ + + /* `#END` */ + + #ifdef NOR_SPI_RX_ISR_EXIT_CALLBACK + NOR_SPI_RX_ISR_ExitCallback(); + #endif /* NOR_SPI_RX_ISR_EXIT_CALLBACK */ +} + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PM.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PM.c new file mode 100644 index 0000000..c8e5ca1 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PM.c @@ -0,0 +1,149 @@ +/******************************************************************************* +* File Name: NOR_SPI_PM.c +* Version 2.50 +* +* Description: +* This file contains the setup, control and status commands to support +* component operations in low power mode. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "NOR_SPI_PVT.h" + +static NOR_SPI_BACKUP_STRUCT NOR_SPI_backup = +{ + NOR_SPI_DISABLED, + NOR_SPI_BITCTR_INIT, +}; + + +/******************************************************************************* +* Function Name: NOR_SPI_SaveConfig +******************************************************************************** +* +* Summary: +* Empty function. Included for consistency with other components. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void NOR_SPI_SaveConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: NOR_SPI_RestoreConfig +******************************************************************************** +* +* Summary: +* Empty function. Included for consistency with other components. +* +* Parameters: +* None. +* +* Return: +* None. +* +*******************************************************************************/ +void NOR_SPI_RestoreConfig(void) +{ + +} + + +/******************************************************************************* +* Function Name: NOR_SPI_Sleep +******************************************************************************** +* +* Summary: +* Prepare SPIM Component goes to sleep. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* NOR_SPI_backup - modified when non-retention registers are saved. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_Sleep(void) +{ + /* Save components enable state */ + NOR_SPI_backup.enableState = ((uint8) NOR_SPI_IS_ENABLED); + + NOR_SPI_Stop(); +} + + +/******************************************************************************* +* Function Name: NOR_SPI_Wakeup +******************************************************************************** +* +* Summary: +* Prepare SPIM Component to wake up. +* +* Parameters: +* None. +* +* Return: +* None. +* +* Global Variables: +* NOR_SPI_backup - used when non-retention registers are restored. +* NOR_SPI_txBufferWrite - modified every function call - resets to +* zero. +* NOR_SPI_txBufferRead - modified every function call - resets to +* zero. +* NOR_SPI_rxBufferWrite - modified every function call - resets to +* zero. +* NOR_SPI_rxBufferRead - modified every function call - resets to +* zero. +* +* Reentrant: +* No. +* +*******************************************************************************/ +void NOR_SPI_Wakeup(void) +{ + #if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + NOR_SPI_rxBufferFull = 0u; + NOR_SPI_rxBufferRead = 0u; + NOR_SPI_rxBufferWrite = 0u; + #endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + + #if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + NOR_SPI_txBufferFull = 0u; + NOR_SPI_txBufferRead = 0u; + NOR_SPI_txBufferWrite = 0u; + #endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + + /* Clear any data from the RX and TX FIFO */ + NOR_SPI_ClearFIFO(); + + /* Restore components block enable state */ + if(0u != NOR_SPI_backup.enableState) + { + NOR_SPI_Enable(); + } +} + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PVT.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PVT.h new file mode 100644 index 0000000..392c7ad --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/NOR_SPI_PVT.h @@ -0,0 +1,53 @@ +/******************************************************************************* +* File Name: .h +* Version 2.50 +* +* Description: +* This private header file contains internal definitions for the SPIM +* component. Do not use these definitions directly in your application. +* +* Note: +* +******************************************************************************** +* Copyright 2012-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_SPIM_PVT_NOR_SPI_H) +#define CY_SPIM_PVT_NOR_SPI_H + +#include "NOR_SPI.h" + + +/********************************** +* Functions with external linkage +**********************************/ + + +/********************************** +* Variables with external linkage +**********************************/ + +extern volatile uint8 NOR_SPI_swStatusTx; +extern volatile uint8 NOR_SPI_swStatusRx; + +#if(NOR_SPI_TX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 NOR_SPI_txBuffer[NOR_SPI_TX_BUFFER_SIZE]; + extern volatile uint8 NOR_SPI_txBufferRead; + extern volatile uint8 NOR_SPI_txBufferWrite; + extern volatile uint8 NOR_SPI_txBufferFull; +#endif /* (NOR_SPI_TX_SOFTWARE_BUF_ENABLED) */ + +#if(NOR_SPI_RX_SOFTWARE_BUF_ENABLED) + extern volatile uint8 NOR_SPI_rxBuffer[NOR_SPI_RX_BUFFER_SIZE]; + extern volatile uint8 NOR_SPI_rxBufferRead; + extern volatile uint8 NOR_SPI_rxBufferWrite; + extern volatile uint8 NOR_SPI_rxBufferFull; +#endif /* (NOR_SPI_RX_SOFTWARE_BUF_ENABLED) */ + +#endif /* CY_SPIM_PVT_NOR_SPI_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h index c917e54..6704c4a 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h @@ -355,33 +355,101 @@ #define USBFS_USB__USBIO_CR0 CYREG_USB_USBIO_CR0 #define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1 +/* NOR_SI */ +#define NOR_SI__0__INTTYPE CYREG_PICU3_INTTYPE6 +#define NOR_SI__0__MASK 0x40u +#define NOR_SI__0__PC CYREG_PRT3_PC6 +#define NOR_SI__0__PORT 3u +#define NOR_SI__0__SHIFT 6u +#define NOR_SI__AG CYREG_PRT3_AG +#define NOR_SI__AMUX CYREG_PRT3_AMUX +#define NOR_SI__BIE CYREG_PRT3_BIE +#define NOR_SI__BIT_MASK CYREG_PRT3_BIT_MASK +#define NOR_SI__BYP CYREG_PRT3_BYP +#define NOR_SI__CTL CYREG_PRT3_CTL +#define NOR_SI__DM0 CYREG_PRT3_DM0 +#define NOR_SI__DM1 CYREG_PRT3_DM1 +#define NOR_SI__DM2 CYREG_PRT3_DM2 +#define NOR_SI__DR CYREG_PRT3_DR +#define NOR_SI__INP_DIS CYREG_PRT3_INP_DIS +#define NOR_SI__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define NOR_SI__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define NOR_SI__LCD_EN CYREG_PRT3_LCD_EN +#define NOR_SI__MASK 0x40u +#define NOR_SI__PORT 3u +#define NOR_SI__PRT CYREG_PRT3_PRT +#define NOR_SI__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define NOR_SI__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define NOR_SI__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define NOR_SI__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define NOR_SI__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define NOR_SI__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define NOR_SI__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define NOR_SI__PS CYREG_PRT3_PS +#define NOR_SI__SHIFT 6u +#define NOR_SI__SLW CYREG_PRT3_SLW + +/* NOR_SO */ +#define NOR_SO__0__INTTYPE CYREG_PICU15_INTTYPE2 +#define NOR_SO__0__MASK 0x04u +#define NOR_SO__0__PC CYREG_IO_PC_PRT15_PC2 +#define NOR_SO__0__PORT 15u +#define NOR_SO__0__SHIFT 2u +#define NOR_SO__AG CYREG_PRT15_AG +#define NOR_SO__AMUX CYREG_PRT15_AMUX +#define NOR_SO__BIE CYREG_PRT15_BIE +#define NOR_SO__BIT_MASK CYREG_PRT15_BIT_MASK +#define NOR_SO__BYP CYREG_PRT15_BYP +#define NOR_SO__CTL CYREG_PRT15_CTL +#define NOR_SO__DM0 CYREG_PRT15_DM0 +#define NOR_SO__DM1 CYREG_PRT15_DM1 +#define NOR_SO__DM2 CYREG_PRT15_DM2 +#define NOR_SO__DR CYREG_PRT15_DR +#define NOR_SO__INP_DIS CYREG_PRT15_INP_DIS +#define NOR_SO__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU15_BASE +#define NOR_SO__LCD_COM_SEG CYREG_PRT15_LCD_COM_SEG +#define NOR_SO__LCD_EN CYREG_PRT15_LCD_EN +#define NOR_SO__MASK 0x04u +#define NOR_SO__PORT 15u +#define NOR_SO__PRT CYREG_PRT15_PRT +#define NOR_SO__PRTDSI__CAPS_SEL CYREG_PRT15_CAPS_SEL +#define NOR_SO__PRTDSI__DBL_SYNC_IN CYREG_PRT15_DBL_SYNC_IN +#define NOR_SO__PRTDSI__OE_SEL0 CYREG_PRT15_OE_SEL0 +#define NOR_SO__PRTDSI__OE_SEL1 CYREG_PRT15_OE_SEL1 +#define NOR_SO__PRTDSI__OUT_SEL0 CYREG_PRT15_OUT_SEL0 +#define NOR_SO__PRTDSI__OUT_SEL1 CYREG_PRT15_OUT_SEL1 +#define NOR_SO__PRTDSI__SYNC_OUT CYREG_PRT15_SYNC_OUT +#define NOR_SO__PS CYREG_PRT15_PS +#define NOR_SO__SHIFT 2u +#define NOR_SO__SLW CYREG_PRT15_SLW + /* SDCard */ -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL -#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK -#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL -#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL -#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST -#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK -#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL -#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL +#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK +#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB05_CTL +#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL +#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB05_06_ST +#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB05_MSK +#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB05_ACTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB05_ST_CTL +#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB05_ST #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL #define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST #define SDCard_BSPIM_RxStsReg__4__MASK 0x10u @@ -392,7 +460,11 @@ #define SDCard_BSPIM_RxStsReg__6__POS 6 #define SDCard_BSPIM_RxStsReg__MASK 0x70u #define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK +#define SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL #define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define SDCard_BSPIM_RxStsReg__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL +#define SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL #define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0 #define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1 @@ -411,14 +483,12 @@ #define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1 #define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0 #define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1 -#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL -#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL #define SDCard_BSPIM_TxStsReg__0__MASK 0x01u #define SDCard_BSPIM_TxStsReg__0__POS 0 #define SDCard_BSPIM_TxStsReg__1__MASK 0x02u #define SDCard_BSPIM_TxStsReg__1__POS 1 -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL -#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL +#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST #define SDCard_BSPIM_TxStsReg__2__MASK 0x04u #define SDCard_BSPIM_TxStsReg__2__POS 2 #define SDCard_BSPIM_TxStsReg__3__MASK 0x08u @@ -426,9 +496,9 @@ #define SDCard_BSPIM_TxStsReg__4__MASK 0x10u #define SDCard_BSPIM_TxStsReg__4__POS 4 #define SDCard_BSPIM_TxStsReg__MASK 0x1Fu -#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK -#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL -#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST +#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB06_MSK +#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL +#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB06_ST /* SD_SCK */ #define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE1 @@ -464,6 +534,137 @@ #define SD_SCK__SHIFT 1u #define SD_SCK__SLW CYREG_PRT3_SLW +/* NOR_CTL */ +#define NOR_CTL_Sync_ctrl_reg__0__MASK 0x01u +#define NOR_CTL_Sync_ctrl_reg__0__POS 0 +#define NOR_CTL_Sync_ctrl_reg__1__MASK 0x02u +#define NOR_CTL_Sync_ctrl_reg__1__POS 1 +#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL +#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL +#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL +#define NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL +#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK +#define NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK +#define NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK +#define NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL +#define NOR_CTL_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB06_CTL +#define NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL +#define NOR_CTL_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB06_CTL +#define NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL +#define NOR_CTL_Sync_ctrl_reg__MASK 0x03u +#define NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL +#define NOR_CTL_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB06_MSK + +/* NOR_SCK */ +#define NOR_SCK__0__INTTYPE CYREG_PICU3_INTTYPE7 +#define NOR_SCK__0__MASK 0x80u +#define NOR_SCK__0__PC CYREG_PRT3_PC7 +#define NOR_SCK__0__PORT 3u +#define NOR_SCK__0__SHIFT 7u +#define NOR_SCK__AG CYREG_PRT3_AG +#define NOR_SCK__AMUX CYREG_PRT3_AMUX +#define NOR_SCK__BIE CYREG_PRT3_BIE +#define NOR_SCK__BIT_MASK CYREG_PRT3_BIT_MASK +#define NOR_SCK__BYP CYREG_PRT3_BYP +#define NOR_SCK__CTL CYREG_PRT3_CTL +#define NOR_SCK__DM0 CYREG_PRT3_DM0 +#define NOR_SCK__DM1 CYREG_PRT3_DM1 +#define NOR_SCK__DM2 CYREG_PRT3_DM2 +#define NOR_SCK__DR CYREG_PRT3_DR +#define NOR_SCK__INP_DIS CYREG_PRT3_INP_DIS +#define NOR_SCK__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define NOR_SCK__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define NOR_SCK__LCD_EN CYREG_PRT3_LCD_EN +#define NOR_SCK__MASK 0x80u +#define NOR_SCK__PORT 3u +#define NOR_SCK__PRT CYREG_PRT3_PRT +#define NOR_SCK__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define NOR_SCK__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define NOR_SCK__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define NOR_SCK__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define NOR_SCK__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define NOR_SCK__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define NOR_SCK__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define NOR_SCK__PS CYREG_PRT3_PS +#define NOR_SCK__SHIFT 7u +#define NOR_SCK__SLW CYREG_PRT3_SLW + +/* NOR_SPI */ +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB08_09_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB08_09_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB08_09_CTL +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB08_09_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB08_09_MSK +#define NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB08_09_MSK +#define NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB08_CTL +#define NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB08_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB08_CTL +#define NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB08_ST_CTL +#define NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB08_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB08_MSK +#define NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB08_MSK_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB08_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB08_ST_CTL +#define NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB08_ST +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL +#define NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST +#define NOR_SPI_BSPIM_RxStsReg__4__MASK 0x10u +#define NOR_SPI_BSPIM_RxStsReg__4__POS 4 +#define NOR_SPI_BSPIM_RxStsReg__5__MASK 0x20u +#define NOR_SPI_BSPIM_RxStsReg__5__POS 5 +#define NOR_SPI_BSPIM_RxStsReg__6__MASK 0x40u +#define NOR_SPI_BSPIM_RxStsReg__6__POS 6 +#define NOR_SPI_BSPIM_RxStsReg__MASK 0x70u +#define NOR_SPI_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK +#define NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL +#define NOR_SPI_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB04_05_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB04_05_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB04_05_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB04_05_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB04_05_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB04_05_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB04_A0_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB04_A0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB04_A1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB04_D0_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB04_D0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB04_D1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB04_ACTL +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB04_F0_F1 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB04_F0 +#define NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB04_F1 +#define NOR_SPI_BSPIM_TxStsReg__0__MASK 0x01u +#define NOR_SPI_BSPIM_TxStsReg__0__POS 0 +#define NOR_SPI_BSPIM_TxStsReg__1__MASK 0x02u +#define NOR_SPI_BSPIM_TxStsReg__1__POS 1 +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL +#define NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST +#define NOR_SPI_BSPIM_TxStsReg__2__MASK 0x04u +#define NOR_SPI_BSPIM_TxStsReg__2__POS 2 +#define NOR_SPI_BSPIM_TxStsReg__3__MASK 0x08u +#define NOR_SPI_BSPIM_TxStsReg__3__POS 3 +#define NOR_SPI_BSPIM_TxStsReg__4__MASK 0x10u +#define NOR_SPI_BSPIM_TxStsReg__4__POS 4 +#define NOR_SPI_BSPIM_TxStsReg__MASK 0x1Fu +#define NOR_SPI_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK +#define NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL +#define NOR_SPI_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST + /* SCSI_In */ #define SCSI_In__0__INTTYPE CYREG_PICU6_INTTYPE1 #define SCSI_In__0__MASK 0x02u @@ -1051,16 +1252,84 @@ #define TERM_EN__SHIFT 3u #define TERM_EN__SLW CYREG_PRT15_SLW +/* nNOR_CS */ +#define nNOR_CS__0__INTTYPE CYREG_PICU3_INTTYPE4 +#define nNOR_CS__0__MASK 0x10u +#define nNOR_CS__0__PC CYREG_PRT3_PC4 +#define nNOR_CS__0__PORT 3u +#define nNOR_CS__0__SHIFT 4u +#define nNOR_CS__AG CYREG_PRT3_AG +#define nNOR_CS__AMUX CYREG_PRT3_AMUX +#define nNOR_CS__BIE CYREG_PRT3_BIE +#define nNOR_CS__BIT_MASK CYREG_PRT3_BIT_MASK +#define nNOR_CS__BYP CYREG_PRT3_BYP +#define nNOR_CS__CTL CYREG_PRT3_CTL +#define nNOR_CS__DM0 CYREG_PRT3_DM0 +#define nNOR_CS__DM1 CYREG_PRT3_DM1 +#define nNOR_CS__DM2 CYREG_PRT3_DM2 +#define nNOR_CS__DR CYREG_PRT3_DR +#define nNOR_CS__INP_DIS CYREG_PRT3_INP_DIS +#define nNOR_CS__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define nNOR_CS__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define nNOR_CS__LCD_EN CYREG_PRT3_LCD_EN +#define nNOR_CS__MASK 0x10u +#define nNOR_CS__PORT 3u +#define nNOR_CS__PRT CYREG_PRT3_PRT +#define nNOR_CS__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define nNOR_CS__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define nNOR_CS__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define nNOR_CS__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define nNOR_CS__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define nNOR_CS__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define nNOR_CS__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define nNOR_CS__PS CYREG_PRT3_PS +#define nNOR_CS__SHIFT 4u +#define nNOR_CS__SLW CYREG_PRT3_SLW + +/* nNOR_WP */ +#define nNOR_WP__0__INTTYPE CYREG_PICU3_INTTYPE5 +#define nNOR_WP__0__MASK 0x20u +#define nNOR_WP__0__PC CYREG_PRT3_PC5 +#define nNOR_WP__0__PORT 3u +#define nNOR_WP__0__SHIFT 5u +#define nNOR_WP__AG CYREG_PRT3_AG +#define nNOR_WP__AMUX CYREG_PRT3_AMUX +#define nNOR_WP__BIE CYREG_PRT3_BIE +#define nNOR_WP__BIT_MASK CYREG_PRT3_BIT_MASK +#define nNOR_WP__BYP CYREG_PRT3_BYP +#define nNOR_WP__CTL CYREG_PRT3_CTL +#define nNOR_WP__DM0 CYREG_PRT3_DM0 +#define nNOR_WP__DM1 CYREG_PRT3_DM1 +#define nNOR_WP__DM2 CYREG_PRT3_DM2 +#define nNOR_WP__DR CYREG_PRT3_DR +#define nNOR_WP__INP_DIS CYREG_PRT3_INP_DIS +#define nNOR_WP__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE +#define nNOR_WP__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG +#define nNOR_WP__LCD_EN CYREG_PRT3_LCD_EN +#define nNOR_WP__MASK 0x20u +#define nNOR_WP__PORT 3u +#define nNOR_WP__PRT CYREG_PRT3_PRT +#define nNOR_WP__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL +#define nNOR_WP__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN +#define nNOR_WP__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 +#define nNOR_WP__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 +#define nNOR_WP__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 +#define nNOR_WP__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 +#define nNOR_WP__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT +#define nNOR_WP__PS CYREG_PRT3_PS +#define nNOR_WP__SHIFT 5u +#define nNOR_WP__SLW CYREG_PRT3_SLW + /* SCSI_CLK */ -#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG1_CFG0 -#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG1_CFG1 -#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG1_CFG2 +#define SCSI_CLK__CFG0 CYREG_CLKDIST_DCFG2_CFG0 +#define SCSI_CLK__CFG1 CYREG_CLKDIST_DCFG2_CFG1 +#define SCSI_CLK__CFG2 CYREG_CLKDIST_DCFG2_CFG2 #define SCSI_CLK__CFG2_SRC_SEL_MASK 0x07u -#define SCSI_CLK__INDEX 0x01u +#define SCSI_CLK__INDEX 0x02u #define SCSI_CLK__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SCSI_CLK__PM_ACT_MSK 0x02u +#define SCSI_CLK__PM_ACT_MSK 0x04u #define SCSI_CLK__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SCSI_CLK__PM_STBY_MSK 0x02u +#define SCSI_CLK__PM_STBY_MSK 0x04u /* SCSI_Out */ #define SCSI_Out__0__AG CYREG_PRT6_AG @@ -1515,15 +1784,15 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0 #define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1 -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK -#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB09_10_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB09_10_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB09_10_MSK #define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2 #define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u @@ -1536,35 +1805,35 @@ #define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6 #define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u #define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7 -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL -#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB09_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB09_ST_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB09_CTL +#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB09_ST_CTL #define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu -#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL -#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK +#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB09_MSK_ACTL +#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB09_MSK #define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL #define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL -#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK +#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK #define SCSI_Out_DBx__0__AG CYREG_PRT6_AG #define SCSI_Out_DBx__0__AMUX CYREG_PRT6_AMUX #define SCSI_Out_DBx__0__BIE CYREG_PRT6_BIE @@ -2012,6 +2281,17 @@ #define SCSI_Out_DBx__DB7__SHIFT 5u #define SCSI_Out_DBx__DB7__SLW CYREG_PRT15_SLW +/* NOR_Clock */ +#define NOR_Clock__CFG0 CYREG_CLKDIST_DCFG0_CFG0 +#define NOR_Clock__CFG1 CYREG_CLKDIST_DCFG0_CFG1 +#define NOR_Clock__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define NOR_Clock__CFG2_SRC_SEL_MASK 0x07u +#define NOR_Clock__INDEX 0x00u +#define NOR_Clock__PM_ACT_CFG CYREG_PM_ACT_CFG2 +#define NOR_Clock__PM_ACT_MSK 0x01u +#define NOR_Clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 +#define NOR_Clock__PM_STBY_MSK 0x01u + /* SD_RX_DMA */ #define SD_RX_DMA__DRQ_CTL CYREG_IDMUX_DRQ_CTL0 #define SD_RX_DMA__DRQ_NUMBER 2u @@ -2052,6 +2332,39 @@ #define SD_TX_DMA_COMPLETE__INTC_SET_EN_REG CYREG_NVIC_SETENA0 #define SD_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 +/* nNOR_HOLD */ +#define nNOR_HOLD__0__INTTYPE CYREG_PICU12_INTTYPE1 +#define nNOR_HOLD__0__MASK 0x02u +#define nNOR_HOLD__0__PC CYREG_PRT12_PC1 +#define nNOR_HOLD__0__PORT 12u +#define nNOR_HOLD__0__SHIFT 1u +#define nNOR_HOLD__AG CYREG_PRT12_AG +#define nNOR_HOLD__BIE CYREG_PRT12_BIE +#define nNOR_HOLD__BIT_MASK CYREG_PRT12_BIT_MASK +#define nNOR_HOLD__BYP CYREG_PRT12_BYP +#define nNOR_HOLD__DM0 CYREG_PRT12_DM0 +#define nNOR_HOLD__DM1 CYREG_PRT12_DM1 +#define nNOR_HOLD__DM2 CYREG_PRT12_DM2 +#define nNOR_HOLD__DR CYREG_PRT12_DR +#define nNOR_HOLD__INP_DIS CYREG_PRT12_INP_DIS +#define nNOR_HOLD__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE +#define nNOR_HOLD__MASK 0x02u +#define nNOR_HOLD__PORT 12u +#define nNOR_HOLD__PRT CYREG_PRT12_PRT +#define nNOR_HOLD__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN +#define nNOR_HOLD__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 +#define nNOR_HOLD__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 +#define nNOR_HOLD__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 +#define nNOR_HOLD__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 +#define nNOR_HOLD__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT +#define nNOR_HOLD__PS CYREG_PRT12_PS +#define nNOR_HOLD__SHIFT 1u +#define nNOR_HOLD__SIO_CFG CYREG_PRT12_SIO_CFG +#define nNOR_HOLD__SIO_DIFF CYREG_PRT12_SIO_DIFF +#define nNOR_HOLD__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN +#define nNOR_HOLD__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ +#define nNOR_HOLD__SLW CYREG_PRT12_SLW + /* SCSI_Noise */ #define SCSI_Noise__0__AG CYREG_PRT4_AG #define SCSI_Noise__0__AMUX CYREG_PRT4_AMUX @@ -2384,6 +2697,8 @@ #define scsiTarget_StatusReg__0__POS 0 #define scsiTarget_StatusReg__1__MASK 0x02u #define scsiTarget_StatusReg__1__POS 1 +#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL +#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST #define scsiTarget_StatusReg__2__MASK 0x04u #define scsiTarget_StatusReg__2__POS 2 #define scsiTarget_StatusReg__3__MASK 0x08u @@ -2391,13 +2706,13 @@ #define scsiTarget_StatusReg__4__MASK 0x10u #define scsiTarget_StatusReg__4__POS 4 #define scsiTarget_StatusReg__MASK 0x1Fu -#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB15_MSK -#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB15_ST_CTL -#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB15_ST_CTL -#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB15_ST +#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK +#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL +#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL +#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB03_ST_CTL +#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST /* Debug_Timer */ #define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2466,111 +2781,26 @@ #define SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG CYREG_NVIC_SETPEND0 /* SD_Data_Clk */ -#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG0_CFG0 -#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG0_CFG1 -#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG0_CFG2 +#define SD_Data_Clk__CFG0 CYREG_CLKDIST_DCFG1_CFG0 +#define SD_Data_Clk__CFG1 CYREG_CLKDIST_DCFG1_CFG1 +#define SD_Data_Clk__CFG2 CYREG_CLKDIST_DCFG1_CFG2 #define SD_Data_Clk__CFG2_SRC_SEL_MASK 0x07u -#define SD_Data_Clk__INDEX 0x00u +#define SD_Data_Clk__INDEX 0x01u #define SD_Data_Clk__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define SD_Data_Clk__PM_ACT_MSK 0x01u +#define SD_Data_Clk__PM_ACT_MSK 0x02u #define SD_Data_Clk__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define SD_Data_Clk__PM_STBY_MSK 0x01u - -/* SPI_Pullups */ -#define SPI_Pullups__0__INTTYPE CYREG_PICU3_INTTYPE4 -#define SPI_Pullups__0__MASK 0x10u -#define SPI_Pullups__0__PC CYREG_PRT3_PC4 -#define SPI_Pullups__0__PORT 3u -#define SPI_Pullups__0__SHIFT 4u -#define SPI_Pullups__1__INTTYPE CYREG_PICU3_INTTYPE5 -#define SPI_Pullups__1__MASK 0x20u -#define SPI_Pullups__1__PC CYREG_PRT3_PC5 -#define SPI_Pullups__1__PORT 3u -#define SPI_Pullups__1__SHIFT 5u -#define SPI_Pullups__2__INTTYPE CYREG_PICU3_INTTYPE6 -#define SPI_Pullups__2__MASK 0x40u -#define SPI_Pullups__2__PC CYREG_PRT3_PC6 -#define SPI_Pullups__2__PORT 3u -#define SPI_Pullups__2__SHIFT 6u -#define SPI_Pullups__3__INTTYPE CYREG_PICU3_INTTYPE7 -#define SPI_Pullups__3__MASK 0x80u -#define SPI_Pullups__3__PC CYREG_PRT3_PC7 -#define SPI_Pullups__3__PORT 3u -#define SPI_Pullups__3__SHIFT 7u -#define SPI_Pullups__AG CYREG_PRT3_AG -#define SPI_Pullups__AMUX CYREG_PRT3_AMUX -#define SPI_Pullups__BIE CYREG_PRT3_BIE -#define SPI_Pullups__BIT_MASK CYREG_PRT3_BIT_MASK -#define SPI_Pullups__BYP CYREG_PRT3_BYP -#define SPI_Pullups__CTL CYREG_PRT3_CTL -#define SPI_Pullups__DM0 CYREG_PRT3_DM0 -#define SPI_Pullups__DM1 CYREG_PRT3_DM1 -#define SPI_Pullups__DM2 CYREG_PRT3_DM2 -#define SPI_Pullups__DR CYREG_PRT3_DR -#define SPI_Pullups__INP_DIS CYREG_PRT3_INP_DIS -#define SPI_Pullups__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU3_BASE -#define SPI_Pullups__LCD_COM_SEG CYREG_PRT3_LCD_COM_SEG -#define SPI_Pullups__LCD_EN CYREG_PRT3_LCD_EN -#define SPI_Pullups__MASK 0xF0u -#define SPI_Pullups__PORT 3u -#define SPI_Pullups__PRT CYREG_PRT3_PRT -#define SPI_Pullups__PRTDSI__CAPS_SEL CYREG_PRT3_CAPS_SEL -#define SPI_Pullups__PRTDSI__DBL_SYNC_IN CYREG_PRT3_DBL_SYNC_IN -#define SPI_Pullups__PRTDSI__OE_SEL0 CYREG_PRT3_OE_SEL0 -#define SPI_Pullups__PRTDSI__OE_SEL1 CYREG_PRT3_OE_SEL1 -#define SPI_Pullups__PRTDSI__OUT_SEL0 CYREG_PRT3_OUT_SEL0 -#define SPI_Pullups__PRTDSI__OUT_SEL1 CYREG_PRT3_OUT_SEL1 -#define SPI_Pullups__PRTDSI__SYNC_OUT CYREG_PRT3_SYNC_OUT -#define SPI_Pullups__PS CYREG_PRT3_PS -#define SPI_Pullups__SHIFT 4u -#define SPI_Pullups__SLW CYREG_PRT3_SLW -#define SPI_Pullups_1__0__INTTYPE CYREG_PICU12_INTTYPE0 -#define SPI_Pullups_1__0__MASK 0x01u -#define SPI_Pullups_1__0__PC CYREG_PRT12_PC0 -#define SPI_Pullups_1__0__PORT 12u -#define SPI_Pullups_1__0__SHIFT 0u -#define SPI_Pullups_1__1__INTTYPE CYREG_PICU12_INTTYPE1 -#define SPI_Pullups_1__1__MASK 0x02u -#define SPI_Pullups_1__1__PC CYREG_PRT12_PC1 -#define SPI_Pullups_1__1__PORT 12u -#define SPI_Pullups_1__1__SHIFT 1u -#define SPI_Pullups_1__AG CYREG_PRT12_AG -#define SPI_Pullups_1__BIE CYREG_PRT12_BIE -#define SPI_Pullups_1__BIT_MASK CYREG_PRT12_BIT_MASK -#define SPI_Pullups_1__BYP CYREG_PRT12_BYP -#define SPI_Pullups_1__DM0 CYREG_PRT12_DM0 -#define SPI_Pullups_1__DM1 CYREG_PRT12_DM1 -#define SPI_Pullups_1__DM2 CYREG_PRT12_DM2 -#define SPI_Pullups_1__DR CYREG_PRT12_DR -#define SPI_Pullups_1__INP_DIS CYREG_PRT12_INP_DIS -#define SPI_Pullups_1__INTTYPE_BASE CYDEV_PICU_INTTYPE_PICU12_BASE -#define SPI_Pullups_1__MASK 0x03u -#define SPI_Pullups_1__PORT 12u -#define SPI_Pullups_1__PRT CYREG_PRT12_PRT -#define SPI_Pullups_1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN -#define SPI_Pullups_1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0 -#define SPI_Pullups_1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1 -#define SPI_Pullups_1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0 -#define SPI_Pullups_1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1 -#define SPI_Pullups_1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT -#define SPI_Pullups_1__PS CYREG_PRT12_PS -#define SPI_Pullups_1__SHIFT 0u -#define SPI_Pullups_1__SIO_CFG CYREG_PRT12_SIO_CFG -#define SPI_Pullups_1__SIO_DIFF CYREG_PRT12_SIO_DIFF -#define SPI_Pullups_1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN -#define SPI_Pullups_1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ -#define SPI_Pullups_1__SLW CYREG_PRT12_SLW +#define SD_Data_Clk__PM_STBY_MSK 0x02u /* timer_clock */ -#define timer_clock__CFG0 CYREG_CLKDIST_DCFG2_CFG0 -#define timer_clock__CFG1 CYREG_CLKDIST_DCFG2_CFG1 -#define timer_clock__CFG2 CYREG_CLKDIST_DCFG2_CFG2 +#define timer_clock__CFG0 CYREG_CLKDIST_DCFG3_CFG0 +#define timer_clock__CFG1 CYREG_CLKDIST_DCFG3_CFG1 +#define timer_clock__CFG2 CYREG_CLKDIST_DCFG3_CFG2 #define timer_clock__CFG2_SRC_SEL_MASK 0x07u -#define timer_clock__INDEX 0x02u +#define timer_clock__INDEX 0x03u #define timer_clock__PM_ACT_CFG CYREG_PM_ACT_CFG2 -#define timer_clock__PM_ACT_MSK 0x04u +#define timer_clock__PM_ACT_MSK 0x08u #define timer_clock__PM_STBY_CFG CYREG_PM_STBY_CFG2 -#define timer_clock__PM_STBY_MSK 0x04u +#define timer_clock__PM_STBY_MSK 0x08u /* SCSI_RST_ISR */ #define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0 @@ -2597,8 +2827,6 @@ #define SCSI_Filtered_sts_sts_reg__0__POS 0 #define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u #define SCSI_Filtered_sts_sts_reg__1__POS 1 -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL -#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST #define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u #define SCSI_Filtered_sts_sts_reg__2__POS 2 #define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u @@ -2606,58 +2834,67 @@ #define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u #define SCSI_Filtered_sts_sts_reg__4__POS 4 #define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu -#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB07_MSK -#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL -#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB07_ST +#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB15_MSK +#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB15_ACTL +#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB15_ST /* SCSI_CTL_PHASE */ #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0 #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u #define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1 +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB12_13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB12_13_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB12_13_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB12_13_MSK #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u #define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2 -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB15_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB15_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB15_ST_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB15_CTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB15_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB12_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB12_ST_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB12_CTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB12_ST_CTL #define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u -#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB15_MSK_ACTL -#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB15_MSK +#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB12_MSK_ACTL +#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB12_MSK /* SCSI_Glitch_Ctl */ #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u #define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0 -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB13_14_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB13_14_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB13_14_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB13_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB13_ST_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB13_CTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB13_ST_CTL #define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL -#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB13_MSK_ACTL +#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB13_MSK /* SCSI_Parity_Error */ #define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u #define SCSI_Parity_Error_sts_sts_reg__0__POS 0 -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL -#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB14_15_ST +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL +#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST #define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u -#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB14_MSK -#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB14_ACTL -#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB14_ST +#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK +#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL +#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST /* Miscellaneous */ #define BCLK__BUS_CLK__HZ 50000000U diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c index d04b6a7..b9cd1c4 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c @@ -149,7 +149,7 @@ static void CyClockStartupError(uint8 errorCode) } #endif -#define CY_CFG_BASE_ADDR_COUNT 39u +#define CY_CFG_BASE_ADDR_COUNT 42u CYPACKED typedef struct { uint8 offset; @@ -217,10 +217,12 @@ static void ClockSetup(void) /* Configure Digital Clocks based on settings from Clock DWR */ CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0), 0x0000u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG0_CFG0 + 0x2u), 0x58u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0001u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x18u); - CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0031u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0), 0x0000u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG1_CFG0 + 0x2u), 0x58u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0), 0x0001u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG2_CFG0 + 0x2u), 0x18u); + CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0), 0x0031u); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_DCFG3_CFG0 + 0x2u), 0x18u); /* Configure ILO based on settings from Clock DWR */ CY_SET_XTND_REG8((void CYFAR *)(CYREG_SLOWCLK_ILO_CR0), 0x06u); @@ -256,7 +258,7 @@ static void ClockSetup(void) CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_UCFG), 0x00u); CY_SET_XTND_REG8((void CYFAR *)(CYREG_CLKDIST_LD), 0x02u); - CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x07u))); + CY_SET_XTND_REG8((void CYFAR *)(CYREG_PM_ACT_CFG2), ((CY_GET_XTND_REG8((void CYFAR *)CYREG_PM_ACT_CFG2) | 0x0Fu))); } @@ -347,7 +349,7 @@ void cyfitter_cfg(void) /* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_7_VAL[] = { - 0x05u, 0x00u, 0x13u, 0x20u, 0x2Cu, 0x0Cu, 0x20u, 0x00u, 0x00u, 0x0Cu}; + 0x04u, 0x00u, 0x10u, 0x22u, 0x2Eu, 0x0Cu, 0x22u, 0x00u, 0x00u, 0x0Cu}; /* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */ static const uint8 CYCODE BS_IOPINS1_7_VAL[] = { @@ -355,7 +357,7 @@ void cyfitter_cfg(void) /* IOPINS0_8 Address: CYREG_PRT15_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_8_VAL[] = { - 0x40u, 0x00u, 0x00u, 0x28u, 0x28u, 0x08u, 0x20u, 0x00u, 0xC0u, 0x00u}; + 0x40u, 0x00u, 0x04u, 0x28u, 0x28u, 0x08u, 0x20u, 0x00u, 0xC0u, 0x00u}; /* IOPINS0_1 Address: CYREG_PRT1_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_1_VAL[] = { @@ -367,7 +369,7 @@ void cyfitter_cfg(void) /* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */ static const uint8 CYCODE BS_IOPINS0_3_VAL[] = { - 0x18u, 0x00u, 0xF1u, 0x0Eu, 0x0Eu, 0x02u, 0x06u, 0x00u, 0x00u, 0x01u}; + 0x08u, 0x00u, 0x01u, 0xFEu, 0xFEu, 0x02u, 0xF6u, 0x00u, 0x00u, 0x01u}; /* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */ static const uint8 CYCODE BS_IOPINS0_4_VAL[] = { @@ -408,102 +410,93 @@ void cyfitter_cfg(void) static const uint32 CYCODE cy_cfg_addr_table[] = { 0x40004501u, /* Base address: 0x40004500 Count: 1 */ 0x40004F02u, /* Base address: 0x40004F00 Count: 2 */ - 0x4000520Cu, /* Base address: 0x40005200 Count: 12 */ - 0x40006401u, /* Base address: 0x40006400 Count: 1 */ - 0x40006501u, /* Base address: 0x40006500 Count: 1 */ - 0x40010042u, /* Base address: 0x40010000 Count: 66 */ - 0x4001013Eu, /* Base address: 0x40010100 Count: 62 */ - 0x4001025Fu, /* Base address: 0x40010200 Count: 95 */ - 0x40010356u, /* Base address: 0x40010300 Count: 86 */ - 0x40010450u, /* Base address: 0x40010400 Count: 80 */ - 0x40010557u, /* Base address: 0x40010500 Count: 87 */ - 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */ - 0x40010756u, /* Base address: 0x40010700 Count: 86 */ - 0x40010915u, /* Base address: 0x40010900 Count: 21 */ - 0x40010A54u, /* Base address: 0x40010A00 Count: 84 */ - 0x40010B52u, /* Base address: 0x40010B00 Count: 82 */ - 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */ - 0x40010D53u, /* Base address: 0x40010D00 Count: 83 */ - 0x40010E4Bu, /* Base address: 0x40010E00 Count: 75 */ - 0x40010F38u, /* Base address: 0x40010F00 Count: 56 */ - 0x40011416u, /* Base address: 0x40011400 Count: 22 */ - 0x4001154Eu, /* Base address: 0x40011500 Count: 78 */ - 0x40011653u, /* Base address: 0x40011600 Count: 83 */ - 0x40011744u, /* Base address: 0x40011700 Count: 68 */ - 0x40011908u, /* Base address: 0x40011900 Count: 8 */ - 0x40011B08u, /* Base address: 0x40011B00 Count: 8 */ - 0x4001401Fu, /* Base address: 0x40014000 Count: 31 */ - 0x4001411Eu, /* Base address: 0x40014100 Count: 30 */ - 0x40014211u, /* Base address: 0x40014200 Count: 17 */ - 0x40014310u, /* Base address: 0x40014300 Count: 16 */ + 0x4000520Eu, /* Base address: 0x40005200 Count: 14 */ + 0x40006402u, /* Base address: 0x40006400 Count: 2 */ + 0x40006502u, /* Base address: 0x40006500 Count: 2 */ + 0x40010045u, /* Base address: 0x40010000 Count: 69 */ + 0x4001013Au, /* Base address: 0x40010100 Count: 58 */ + 0x4001024Eu, /* Base address: 0x40010200 Count: 78 */ + 0x4001035Bu, /* Base address: 0x40010300 Count: 91 */ + 0x4001041Bu, /* Base address: 0x40010400 Count: 27 */ + 0x40010545u, /* Base address: 0x40010500 Count: 69 */ + 0x40010651u, /* Base address: 0x40010600 Count: 81 */ + 0x40010751u, /* Base address: 0x40010700 Count: 81 */ + 0x4001084Eu, /* Base address: 0x40010800 Count: 78 */ + 0x4001095Fu, /* Base address: 0x40010900 Count: 95 */ + 0x40010A5Cu, /* Base address: 0x40010A00 Count: 92 */ + 0x40010B60u, /* Base address: 0x40010B00 Count: 96 */ + 0x40010C49u, /* Base address: 0x40010C00 Count: 73 */ + 0x40010D54u, /* Base address: 0x40010D00 Count: 84 */ + 0x40010E51u, /* Base address: 0x40010E00 Count: 81 */ + 0x40010F43u, /* Base address: 0x40010F00 Count: 67 */ + 0x40011462u, /* Base address: 0x40011400 Count: 98 */ + 0x40011540u, /* Base address: 0x40011500 Count: 64 */ + 0x40011651u, /* Base address: 0x40011600 Count: 81 */ + 0x4001174Cu, /* Base address: 0x40011700 Count: 76 */ + 0x40011855u, /* Base address: 0x40011800 Count: 85 */ + 0x40011948u, /* Base address: 0x40011900 Count: 72 */ + 0x40011B06u, /* Base address: 0x40011B00 Count: 6 */ + 0x4001401Du, /* Base address: 0x40014000 Count: 29 */ + 0x40014120u, /* Base address: 0x40014100 Count: 32 */ + 0x4001420Fu, /* Base address: 0x40014200 Count: 15 */ + 0x4001430Au, /* Base address: 0x40014300 Count: 10 */ 0x40014411u, /* Base address: 0x40014400 Count: 17 */ - 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */ - 0x40014613u, /* Base address: 0x40014600 Count: 19 */ - 0x4001470Au, /* Base address: 0x40014700 Count: 10 */ - 0x40014807u, /* Base address: 0x40014800 Count: 7 */ - 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */ - 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */ - 0x40015002u, /* Base address: 0x40015000 Count: 2 */ + 0x40014517u, /* Base address: 0x40014500 Count: 23 */ + 0x4001460Fu, /* Base address: 0x40014600 Count: 15 */ + 0x4001470Cu, /* Base address: 0x40014700 Count: 12 */ + 0x4001480Du, /* Base address: 0x40014800 Count: 13 */ + 0x4001491Au, /* Base address: 0x40014900 Count: 26 */ + 0x40014C0Cu, /* Base address: 0x40014C00 Count: 12 */ + 0x40014D07u, /* Base address: 0x40014D00 Count: 7 */ + 0x40015005u, /* Base address: 0x40015000 Count: 5 */ 0x40015104u, /* Base address: 0x40015100 Count: 4 */ }; static const cy_cfg_addrvalue_t CYCODE cy_cfg_data_table[] = { {0x7Eu, 0x02u}, + {0x01u, 0x30u}, + {0x0Au, 0x4Bu}, + {0x00u, 0x02u}, {0x01u, 0x20u}, - {0x0Au, 0x27u}, - {0x01u, 0x22u}, - {0x10u, 0xAAu}, - {0x11u, 0x88u}, - {0x18u, 0x02u}, - {0x19u, 0x08u}, + {0x10u, 0xA8u}, + {0x11u, 0x2Au}, + {0x18u, 0x62u}, + {0x19u, 0x38u}, {0x1Cu, 0x08u}, - {0x20u, 0x02u}, - {0x21u, 0x02u}, - {0x30u, 0x80u}, - {0x31u, 0x04u}, + {0x20u, 0x01u}, + {0x30u, 0x84u}, + {0x31u, 0x20u}, + {0x61u, 0x20u}, {0x78u, 0x20u}, + {0x79u, 0x20u}, {0x7Cu, 0x40u}, {0x20u, 0x01u}, - {0x84u, 0x0Fu}, - {0x04u, 0xE0u}, - {0x05u, 0xFFu}, - {0x08u, 0x11u}, - {0x0Au, 0xECu}, - {0x0Bu, 0xFFu}, - {0x0Cu, 0x40u}, - {0x0Du, 0x69u}, - {0x0Eu, 0x80u}, - {0x0Fu, 0x96u}, - {0x10u, 0x0Bu}, - {0x11u, 0x0Fu}, - {0x12u, 0xF4u}, - {0x13u, 0xF0u}, - {0x16u, 0xFFu}, - {0x17u, 0xFFu}, - {0x18u, 0xCAu}, - {0x19u, 0x33u}, - {0x1Au, 0x15u}, - {0x1Bu, 0xCCu}, - {0x1Eu, 0x10u}, - {0x20u, 0x06u}, - {0x25u, 0xFFu}, - {0x28u, 0x40u}, - {0x29u, 0x55u}, - {0x2Au, 0x80u}, - {0x2Bu, 0xAAu}, - {0x2Cu, 0x01u}, - {0x2Fu, 0xFFu}, - {0x30u, 0xC0u}, - {0x31u, 0xFFu}, - {0x34u, 0x3Fu}, - {0x3Au, 0x02u}, - {0x3Bu, 0x02u}, - {0x40u, 0x52u}, + {0x88u, 0x0Fu}, + {0x76u, 0x01u}, + {0x85u, 0x0Fu}, + {0x00u, 0x0Au}, + {0x02u, 0x55u}, + {0x06u, 0x7Fu}, + {0x0Cu, 0x8Bu}, + {0x0Eu, 0x74u}, + {0x14u, 0x91u}, + {0x16u, 0x6Cu}, + {0x18u, 0x01u}, + {0x1Cu, 0x40u}, + {0x1Eu, 0x80u}, + {0x22u, 0x10u}, + {0x24u, 0x06u}, + {0x28u, 0x20u}, + {0x2Au, 0x40u}, + {0x30u, 0x3Fu}, + {0x36u, 0xC0u}, + {0x3Au, 0x80u}, + {0x40u, 0x62u}, {0x41u, 0x04u}, - {0x42u, 0x30u}, - {0x45u, 0xC2u}, - {0x46u, 0xFDu}, - {0x47u, 0x0Eu}, + {0x42u, 0x10u}, + {0x45u, 0xECu}, + {0x46u, 0x2Du}, + {0x47u, 0x0Fu}, {0x48u, 0x1Fu}, {0x49u, 0xFFu}, {0x4Au, 0xFFu}, @@ -511,11 +504,10 @@ void cyfitter_cfg(void) {0x4Fu, 0x2Cu}, {0x56u, 0x01u}, {0x58u, 0x04u}, - {0x59u, 0x04u}, {0x5Au, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Du, 0x01u}, + {0x5Cu, 0x02u}, + {0x5Du, 0x02u}, {0x5Fu, 0x01u}, {0x60u, 0x08u}, {0x62u, 0xC8u}, @@ -523,1519 +515,1883 @@ void cyfitter_cfg(void) {0x68u, 0x40u}, {0x69u, 0x40u}, {0x6Eu, 0x08u}, - {0x9Du, 0x01u}, - {0xB1u, 0x01u}, - {0xBFu, 0x01u}, - {0xD6u, 0x08u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDDu, 0x90u}, - {0xDFu, 0x01u}, - {0x00u, 0x20u}, - {0x03u, 0x26u}, - {0x09u, 0x80u}, - {0x0Au, 0x44u}, - {0x0Bu, 0x20u}, - {0x10u, 0x81u}, - {0x12u, 0x04u}, - {0x19u, 0x20u}, - {0x1Au, 0x84u}, - {0x1Bu, 0x02u}, - {0x20u, 0x40u}, - {0x21u, 0x02u}, - {0x24u, 0x80u}, - {0x2Au, 0xA0u}, - {0x2Bu, 0x20u}, - {0x30u, 0x10u}, - {0x31u, 0x02u}, - {0x33u, 0x04u}, - {0x35u, 0x40u}, - {0x3Au, 0x48u}, - {0x3Bu, 0x20u}, - {0x41u, 0x08u}, - {0x42u, 0xCCu}, - {0x48u, 0x80u}, - {0x4Au, 0x10u}, - {0x4Bu, 0x80u}, - {0x50u, 0x20u}, - {0x51u, 0xC0u}, - {0x52u, 0x08u}, - {0x59u, 0x10u}, - {0x5Au, 0x88u}, - {0x5Bu, 0x01u}, - {0x5Cu, 0x80u}, - {0x5Fu, 0x28u}, - {0x61u, 0x24u}, - {0x63u, 0x82u}, - {0x64u, 0x12u}, - {0x66u, 0x24u}, - {0x69u, 0x51u}, - {0x6Bu, 0x10u}, - {0x70u, 0x18u}, - {0x73u, 0x42u}, - {0x80u, 0x20u}, - {0x81u, 0x80u}, - {0x82u, 0x40u}, - {0x84u, 0x80u}, - {0x87u, 0x40u}, - {0x8Bu, 0x22u}, - {0x8Cu, 0xC0u}, - {0xC0u, 0x07u}, - {0xC2u, 0x0Fu}, - {0xC4u, 0x0Bu}, - {0xCAu, 0x0Eu}, - {0xCCu, 0x17u}, - {0xCEu, 0x0Eu}, - {0xD0u, 0x07u}, - {0xD2u, 0x08u}, - {0xD6u, 0x7Fu}, - {0xD8u, 0x7Fu}, - {0xE0u, 0x1Du}, - {0xE4u, 0x03u}, - {0xE6u, 0x10u}, - {0x00u, 0x88u}, - {0x01u, 0x04u}, - {0x02u, 0x77u}, - {0x03u, 0x08u}, - {0x04u, 0x34u}, - {0x05u, 0x40u}, - {0x06u, 0x40u}, - {0x08u, 0x10u}, - {0x0Au, 0x20u}, - {0x0Bu, 0x3Fu}, - {0x0Cu, 0x03u}, - {0x0Du, 0x01u}, - {0x0Eu, 0x0Cu}, - {0x0Fu, 0x02u}, - {0x10u, 0x8Bu}, - {0x11u, 0x01u}, - {0x12u, 0x74u}, - {0x13u, 0x02u}, - {0x14u, 0x40u}, - {0x15u, 0x10u}, - {0x16u, 0x80u}, - {0x17u, 0x20u}, - {0x18u, 0x3Du}, - {0x19u, 0x10u}, - {0x1Au, 0x42u}, - {0x1Bu, 0x20u}, - {0x1Cu, 0x02u}, - {0x1Du, 0x3Fu}, - {0x23u, 0x3Fu}, - {0x24u, 0x10u}, - {0x26u, 0x20u}, - {0x27u, 0x3Fu}, - {0x29u, 0x3Fu}, - {0x2Au, 0x77u}, - {0x2Du, 0x04u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x08u}, - {0x31u, 0x0Cu}, - {0x32u, 0xC0u}, - {0x33u, 0x40u}, - {0x34u, 0x30u}, - {0x35u, 0x30u}, - {0x36u, 0x0Fu}, - {0x37u, 0x03u}, - {0x3Au, 0xA8u}, - {0x3Bu, 0xA2u}, - {0x3Fu, 0x04u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x11u}, - {0x5Fu, 0x01u}, - {0x80u, 0x50u}, - {0x82u, 0x8Cu}, - {0x84u, 0x0Cu}, - {0x86u, 0x80u}, - {0x87u, 0x18u}, - {0x88u, 0x04u}, - {0x8Au, 0x08u}, - {0x8Bu, 0x20u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x24u}, - {0x92u, 0x02u}, - {0x94u, 0x20u}, - {0x96u, 0x0Cu}, - {0x97u, 0x04u}, - {0x98u, 0x4Cu}, - {0x9Au, 0x80u}, - {0x9Fu, 0x03u}, - {0xA0u, 0x01u}, - {0xA1u, 0x24u}, - {0xA2u, 0x02u}, - {0xA3u, 0x09u}, - {0xA4u, 0x10u}, - {0xA6u, 0x8Cu}, - {0xA8u, 0x04u}, - {0xA9u, 0x24u}, - {0xAAu, 0x08u}, - {0xABu, 0x12u}, - {0xAEu, 0x10u}, - {0xB0u, 0xF0u}, - {0xB2u, 0x0Cu}, - {0xB3u, 0x38u}, - {0xB4u, 0x03u}, + {0x81u, 0x04u}, + {0x84u, 0x02u}, + {0x86u, 0x01u}, + {0x89u, 0x02u}, + {0x8Du, 0x01u}, + {0x94u, 0x02u}, + {0x96u, 0x01u}, + {0x98u, 0x02u}, + {0x9Au, 0x05u}, + {0x9Cu, 0x01u}, + {0x9Eu, 0x02u}, + {0xA0u, 0x02u}, + {0xA2u, 0x09u}, + {0xB1u, 0x04u}, + {0xB2u, 0x08u}, + {0xB4u, 0x04u}, + {0xB5u, 0x02u}, {0xB6u, 0x03u}, - {0xB7u, 0x07u}, - {0xB8u, 0x02u}, - {0xBAu, 0x08u}, - {0xBEu, 0x50u}, + {0xB7u, 0x01u}, + {0xBAu, 0x80u}, + {0xBFu, 0x50u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x92u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, {0x01u, 0x02u}, - {0x02u, 0x01u}, - {0x03u, 0x28u}, - {0x04u, 0x08u}, - {0x05u, 0x52u}, - {0x08u, 0x0Au}, - {0x0Au, 0x04u}, - {0x0Bu, 0x20u}, - {0x0Cu, 0x02u}, - {0x0Du, 0x48u}, - {0x0Eu, 0x04u}, - {0x10u, 0x05u}, - {0x13u, 0x0Au}, - {0x14u, 0x08u}, - {0x16u, 0x22u}, - {0x18u, 0x08u}, - {0x19u, 0x86u}, - {0x1Au, 0x40u}, - {0x1Bu, 0x28u}, - {0x1Du, 0x58u}, - {0x21u, 0x84u}, - {0x25u, 0x20u}, - {0x26u, 0x26u}, - {0x27u, 0x01u}, - {0x29u, 0x22u}, - {0x2Du, 0x22u}, - {0x2Fu, 0x11u}, - {0x30u, 0x08u}, - {0x31u, 0x80u}, - {0x35u, 0x80u}, - {0x36u, 0x28u}, - {0x37u, 0x01u}, - {0x38u, 0x20u}, - {0x39u, 0x08u}, - {0x3Bu, 0x80u}, - {0x3Cu, 0x20u}, - {0x3Du, 0x08u}, - {0x3Eu, 0x80u}, + {0x03u, 0x12u}, + {0x04u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Bu, 0x28u}, + {0x0Eu, 0x2Au}, + {0x10u, 0xA4u}, + {0x16u, 0x80u}, + {0x19u, 0x02u}, + {0x1Au, 0x01u}, + {0x1Cu, 0x04u}, + {0x1Eu, 0x22u}, + {0x1Fu, 0x80u}, + {0x24u, 0x02u}, + {0x25u, 0x02u}, + {0x27u, 0x04u}, + {0x3Du, 0xA2u}, {0x3Fu, 0x02u}, - {0x58u, 0x40u}, - {0x62u, 0x40u}, - {0x6Bu, 0x02u}, - {0x7Au, 0x02u}, - {0x7Bu, 0x01u}, - {0x81u, 0x04u}, - {0x84u, 0x12u}, - {0x86u, 0x12u}, - {0x87u, 0x48u}, - {0x89u, 0x80u}, - {0x90u, 0x20u}, - {0x91u, 0xD1u}, - {0x92u, 0x04u}, - {0x96u, 0x48u}, - {0x97u, 0xA0u}, - {0x98u, 0x43u}, - {0x99u, 0x20u}, - {0x9Au, 0x31u}, - {0x9Bu, 0x10u}, - {0x9Du, 0x54u}, - {0x9Eu, 0x40u}, - {0x9Fu, 0x01u}, - {0xA0u, 0x08u}, - {0xA2u, 0x10u}, - {0xA3u, 0x04u}, - {0xA4u, 0x10u}, - {0xA5u, 0x28u}, - {0xA7u, 0x61u}, - {0xAAu, 0x01u}, - {0xABu, 0x04u}, - {0xAFu, 0x08u}, - {0xB0u, 0x43u}, - {0xB2u, 0x18u}, - {0xB4u, 0x40u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xFEu}, - {0xC4u, 0xEFu}, - {0xCAu, 0xF5u}, - {0xCCu, 0xFAu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x08u}, - {0xD8u, 0x08u}, - {0xE2u, 0x8Cu}, - {0xE4u, 0x08u}, - {0xE8u, 0x02u}, - {0xEAu, 0x0Du}, - {0xEEu, 0x84u}, - {0x00u, 0x04u}, - {0x02u, 0x79u}, - {0x04u, 0x78u}, - {0x05u, 0x44u}, - {0x07u, 0x88u}, - {0x0Bu, 0xFFu}, - {0x0Eu, 0x03u}, - {0x10u, 0x20u}, - {0x11u, 0x33u}, - {0x12u, 0x40u}, - {0x13u, 0xCCu}, - {0x15u, 0x21u}, - {0x16u, 0x78u}, - {0x17u, 0x12u}, - {0x18u, 0x7Cu}, - {0x1Au, 0x02u}, - {0x1Cu, 0x20u}, - {0x1Du, 0x0Fu}, - {0x1Eu, 0x40u}, - {0x1Fu, 0xF0u}, - {0x20u, 0x08u}, - {0x21u, 0x84u}, - {0x22u, 0x10u}, - {0x23u, 0x48u}, - {0x25u, 0xFFu}, - {0x26u, 0x7Cu}, - {0x28u, 0x08u}, - {0x2Au, 0x10u}, - {0x2Bu, 0xFFu}, - {0x2Du, 0x11u}, - {0x2Eu, 0x04u}, - {0x2Fu, 0x22u}, - {0x30u, 0x07u}, - {0x31u, 0xFFu}, - {0x34u, 0x18u}, - {0x36u, 0x60u}, - {0x3Au, 0xA0u}, - {0x3Fu, 0x01u}, + {0x40u, 0x08u}, + {0x42u, 0x01u}, + {0x43u, 0x02u}, + {0x48u, 0x20u}, + {0x49u, 0x14u}, + {0x4Bu, 0x22u}, + {0x50u, 0x80u}, + {0x51u, 0x60u}, + {0x52u, 0x10u}, + {0x53u, 0x08u}, + {0x59u, 0xA0u}, + {0x5Bu, 0x0Au}, + {0x5Cu, 0x80u}, + {0x60u, 0x60u}, + {0x62u, 0xA0u}, + {0x66u, 0x80u}, + {0x68u, 0x04u}, + {0x69u, 0x44u}, + {0x6Bu, 0x40u}, + {0x70u, 0x50u}, + {0x72u, 0x40u}, + {0x73u, 0x10u}, + {0x81u, 0x60u}, + {0x83u, 0x01u}, + {0x84u, 0x08u}, + {0x85u, 0x46u}, + {0x87u, 0x10u}, + {0x88u, 0xA0u}, + {0x8Cu, 0x41u}, + {0xC0u, 0x2Du}, + {0xC2u, 0xE7u}, + {0xC4u, 0x1Eu}, + {0xCEu, 0xB0u}, + {0xD0u, 0x0Du}, + {0xD2u, 0x04u}, + {0xD6u, 0x1Fu}, + {0xD8u, 0x1Fu}, + {0xE0u, 0x2Du}, + {0xE2u, 0x42u}, + {0xE4u, 0x0Au}, + {0x01u, 0x02u}, + {0x03u, 0x11u}, + {0x05u, 0x02u}, + {0x07u, 0x05u}, + {0x0Cu, 0x02u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x01u}, + {0x11u, 0x01u}, + {0x13u, 0x02u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x11u}, + {0x17u, 0x09u}, + {0x18u, 0x02u}, + {0x1Au, 0x05u}, + {0x1Cu, 0x01u}, + {0x1Eu, 0x02u}, + {0x24u, 0x02u}, + {0x26u, 0x09u}, + {0x30u, 0x04u}, + {0x31u, 0x03u}, + {0x32u, 0x08u}, + {0x33u, 0x08u}, + {0x34u, 0x10u}, + {0x35u, 0x10u}, + {0x36u, 0x03u}, + {0x37u, 0x04u}, + {0x3Au, 0x80u}, + {0x3Bu, 0x02u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, + {0x5Cu, 0x22u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x10u}, - {0x82u, 0x08u}, - {0x83u, 0x40u}, - {0x85u, 0x48u}, - {0x87u, 0x24u}, - {0x88u, 0x10u}, - {0x8Au, 0x0Au}, - {0x8Bu, 0x08u}, - {0x93u, 0x30u}, - {0x94u, 0x10u}, - {0x96u, 0x09u}, - {0x97u, 0x48u}, - {0x98u, 0x10u}, - {0x9Au, 0x0Cu}, - {0x9Bu, 0x06u}, - {0x9Cu, 0x08u}, - {0x9Eu, 0x10u}, - {0xABu, 0x01u}, - {0xADu, 0x48u}, + {0x80u, 0x78u}, + {0x82u, 0x03u}, + {0x86u, 0x7Fu}, + {0x87u, 0x06u}, + {0x8Cu, 0x20u}, + {0x8Eu, 0x40u}, + {0x8Fu, 0x08u}, + {0x90u, 0x01u}, + {0x92u, 0x6Eu}, + {0x94u, 0x20u}, + {0x96u, 0x40u}, + {0x97u, 0x30u}, + {0x98u, 0x80u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x01u}, + {0x9Cu, 0x03u}, + {0x9Eu, 0x74u}, + {0x9Fu, 0x40u}, + {0xA0u, 0x02u}, + {0xA1u, 0x49u}, + {0xA3u, 0x24u}, + {0xA6u, 0x08u}, + {0xA8u, 0x64u}, + {0xA9u, 0x01u}, + {0xABu, 0x48u}, + {0xADu, 0x49u}, {0xAFu, 0x12u}, - {0xB0u, 0x02u}, - {0xB2u, 0x04u}, - {0xB3u, 0x0Eu}, - {0xB4u, 0x01u}, - {0xB5u, 0x01u}, - {0xB6u, 0x18u}, - {0xB7u, 0x70u}, + {0xB2u, 0x80u}, + {0xB3u, 0x70u}, + {0xB4u, 0x1Fu}, + {0xB5u, 0x0Eu}, + {0xB6u, 0x60u}, + {0xB7u, 0x01u}, {0xBAu, 0x80u}, + {0xBEu, 0x04u}, + {0xBFu, 0x40u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDFu, 0x01u}, + {0x01u, 0x82u}, + {0x03u, 0x10u}, + {0x04u, 0x40u}, + {0x08u, 0x89u}, + {0x0Bu, 0x08u}, + {0x0Du, 0x20u}, + {0x0Eu, 0x12u}, + {0x10u, 0x84u}, + {0x12u, 0x10u}, + {0x13u, 0x02u}, + {0x16u, 0x20u}, + {0x18u, 0x28u}, + {0x19u, 0x90u}, + {0x1Cu, 0x42u}, + {0x1Du, 0x20u}, + {0x1Eu, 0x12u}, + {0x20u, 0x24u}, + {0x21u, 0x88u}, + {0x25u, 0x45u}, + {0x26u, 0x02u}, + {0x27u, 0x04u}, + {0x28u, 0x01u}, + {0x29u, 0x12u}, + {0x2Bu, 0x02u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x01u}, + {0x30u, 0x20u}, + {0x31u, 0x08u}, + {0x33u, 0x40u}, + {0x36u, 0x02u}, + {0x37u, 0x04u}, + {0x38u, 0x04u}, + {0x39u, 0x40u}, + {0x3Du, 0x88u}, + {0x3Fu, 0x01u}, + {0x40u, 0x20u}, + {0x43u, 0x08u}, + {0x58u, 0x20u}, + {0x59u, 0x04u}, + {0x5Au, 0x40u}, + {0x5Bu, 0x02u}, + {0x5Fu, 0x50u}, + {0x61u, 0x80u}, + {0x66u, 0x20u}, + {0x67u, 0x01u}, + {0x6Bu, 0x01u}, + {0x80u, 0x10u}, + {0x81u, 0x10u}, + {0x84u, 0x54u}, + {0x87u, 0x04u}, + {0x8Bu, 0x50u}, + {0x91u, 0x40u}, + {0x93u, 0x02u}, + {0x97u, 0x08u}, + {0x99u, 0x06u}, + {0x9Au, 0x10u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0x04u}, + {0x9Du, 0x90u}, + {0x9Fu, 0x18u}, + {0xA0u, 0xA4u}, + {0xA2u, 0x10u}, + {0xA3u, 0x08u}, + {0xA4u, 0x01u}, + {0xA5u, 0x11u}, + {0xA6u, 0xA4u}, + {0xA7u, 0x02u}, + {0xA8u, 0x10u}, + {0xABu, 0x82u}, + {0xACu, 0x01u}, + {0xADu, 0x22u}, + {0xB3u, 0x01u}, + {0xB4u, 0x40u}, + {0xB6u, 0x40u}, + {0xB7u, 0x0Cu}, + {0xC0u, 0x8Du}, + {0xC2u, 0xEFu}, + {0xC4u, 0x2Eu}, + {0xCAu, 0x0Du}, + {0xCCu, 0xCEu}, + {0xCEu, 0xDAu}, + {0xD6u, 0x3Fu}, + {0xD8u, 0x38u}, + {0xE0u, 0x28u}, + {0xE2u, 0x01u}, + {0xE4u, 0x82u}, + {0xE6u, 0x08u}, + {0xE8u, 0x04u}, + {0xEAu, 0x10u}, + {0xECu, 0x0Cu}, + {0xEEu, 0x13u}, + {0x88u, 0x02u}, + {0x8Du, 0x02u}, + {0x8Fu, 0x01u}, + {0x91u, 0x02u}, + {0x93u, 0x05u}, + {0x95u, 0x02u}, + {0x96u, 0x01u}, + {0x97u, 0x09u}, + {0x99u, 0x01u}, + {0x9Bu, 0x02u}, + {0xADu, 0x02u}, + {0xAFu, 0x11u}, + {0xB0u, 0x02u}, + {0xB1u, 0x04u}, + {0xB3u, 0x03u}, + {0xB4u, 0x01u}, + {0xB5u, 0x10u}, + {0xB7u, 0x08u}, + {0xBBu, 0x08u}, + {0xBEu, 0x01u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x22u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x40u}, - {0x01u, 0x02u}, - {0x03u, 0x20u}, - {0x05u, 0x11u}, - {0x08u, 0x02u}, - {0x0Au, 0x06u}, - {0x0Bu, 0x20u}, - {0x0Eu, 0x22u}, - {0x0Fu, 0x04u}, - {0x10u, 0x08u}, - {0x11u, 0x40u}, - {0x12u, 0x40u}, - {0x13u, 0x08u}, - {0x18u, 0x40u}, - {0x1Au, 0x0Au}, - {0x1Bu, 0x40u}, - {0x1Du, 0x11u}, - {0x1Eu, 0x22u}, - {0x1Fu, 0x40u}, - {0x20u, 0x80u}, - {0x25u, 0x08u}, - {0x27u, 0x26u}, - {0x29u, 0x40u}, - {0x2Au, 0x04u}, - {0x2Bu, 0x88u}, - {0x2Cu, 0x02u}, - {0x2Eu, 0x40u}, - {0x2Fu, 0x04u}, - {0x31u, 0x08u}, - {0x32u, 0x80u}, - {0x33u, 0x02u}, - {0x37u, 0x2Au}, - {0x3Au, 0x18u}, - {0x3Du, 0x11u}, - {0x3Eu, 0x04u}, - {0x4Cu, 0x08u}, - {0x4Eu, 0x04u}, - {0x58u, 0x10u}, - {0x59u, 0x08u}, - {0x5Bu, 0x40u}, - {0x5Du, 0x20u}, - {0x5Fu, 0x80u}, - {0x60u, 0x0Au}, - {0x62u, 0x08u}, - {0x63u, 0x20u}, - {0x65u, 0x80u}, - {0x66u, 0x80u}, - {0x67u, 0x04u}, - {0x78u, 0x0Cu}, - {0x80u, 0xC0u}, - {0x83u, 0x40u}, - {0x87u, 0xC0u}, - {0x89u, 0x40u}, - {0x8Bu, 0x03u}, - {0x8Du, 0x20u}, - {0x91u, 0x51u}, - {0x92u, 0x44u}, - {0x96u, 0x08u}, - {0x97u, 0x22u}, - {0x98u, 0x10u}, - {0x99u, 0x0Au}, - {0x9Au, 0x51u}, - {0x9Bu, 0x18u}, - {0x9Cu, 0x04u}, - {0x9Eu, 0x80u}, - {0xA3u, 0x24u}, - {0xA6u, 0x08u}, - {0xA7u, 0x40u}, - {0xAAu, 0x04u}, - {0xACu, 0x10u}, - {0xB1u, 0x04u}, - {0xB2u, 0x04u}, - {0xB4u, 0x04u}, - {0xB5u, 0x08u}, - {0xC0u, 0x5Du}, - {0xC2u, 0xEFu}, - {0xC4u, 0x0Fu}, - {0xCAu, 0x3Fu}, - {0xCCu, 0xEBu}, - {0xCEu, 0xE6u}, - {0xD6u, 0x3Eu}, - {0xD8u, 0x3Eu}, - {0xE0u, 0x10u}, - {0xE2u, 0x06u}, - {0xE4u, 0x16u}, - {0xE6u, 0x01u}, - {0xEEu, 0x02u}, - {0x04u, 0x20u}, - {0x06u, 0x50u}, - {0x0Au, 0x04u}, - {0x0Eu, 0x03u}, - {0x10u, 0x20u}, - {0x12u, 0x18u}, - {0x14u, 0x20u}, - {0x16u, 0x10u}, - {0x18u, 0x04u}, - {0x19u, 0x02u}, + {0x00u, 0x18u}, + {0x01u, 0x80u}, + {0x05u, 0x10u}, + {0x08u, 0xA0u}, + {0x09u, 0x88u}, + {0x0Bu, 0x80u}, + {0x0Eu, 0x20u}, + {0x11u, 0xAAu}, + {0x19u, 0x01u}, {0x1Au, 0x02u}, + {0x1Cu, 0x80u}, + {0x1Eu, 0x08u}, + {0x20u, 0x08u}, + {0x21u, 0x24u}, + {0x23u, 0x01u}, + {0x24u, 0x40u}, + {0x27u, 0x36u}, + {0x28u, 0x20u}, + {0x29u, 0x21u}, + {0x2Au, 0x40u}, + {0x2Eu, 0x80u}, + {0x30u, 0x02u}, + {0x31u, 0xA8u}, + {0x37u, 0x26u}, + {0x38u, 0x90u}, + {0x39u, 0x08u}, + {0x3Au, 0x01u}, + {0x3Cu, 0x40u}, + {0x40u, 0x81u}, + {0x41u, 0x08u}, + {0x48u, 0x80u}, + {0x49u, 0x08u}, + {0x4Au, 0x0Au}, + {0x4Bu, 0x02u}, + {0x52u, 0x50u}, + {0x53u, 0x48u}, + {0x5Du, 0x40u}, + {0x66u, 0x80u}, + {0x82u, 0x20u}, + {0x86u, 0x90u}, + {0x87u, 0x08u}, + {0x8Du, 0x40u}, + {0x8Fu, 0x20u}, + {0x90u, 0x04u}, + {0x9Bu, 0x01u}, + {0x9Fu, 0x18u}, + {0xA2u, 0x10u}, + {0xA4u, 0x40u}, + {0xA6u, 0xA4u}, + {0xA7u, 0x02u}, + {0xA8u, 0x08u}, + {0xACu, 0x04u}, + {0xB4u, 0x84u}, + {0xC0u, 0x47u}, + {0xC2u, 0x2Fu}, + {0xC4u, 0x0Fu}, + {0xCAu, 0x1Fu}, + {0xCCu, 0xEFu}, + {0xCEu, 0x1Fu}, + {0xD0u, 0x0Bu}, + {0xD2u, 0x0Cu}, + {0xD6u, 0x10u}, + {0xD8u, 0x10u}, + {0xE0u, 0x42u}, + {0xE4u, 0x02u}, + {0xE6u, 0x89u}, + {0xE8u, 0x40u}, + {0xEAu, 0x08u}, + {0xEEu, 0x04u}, + {0x01u, 0x01u}, + {0x02u, 0x9Fu}, + {0x04u, 0x80u}, + {0x05u, 0x01u}, + {0x08u, 0x1Fu}, + {0x09u, 0x88u}, + {0x0Au, 0x20u}, + {0x0Bu, 0x21u}, + {0x0Cu, 0xC0u}, + {0x0Du, 0xA2u}, + {0x0Eu, 0x01u}, + {0x0Fu, 0x08u}, + {0x10u, 0x7Fu}, + {0x11u, 0x01u}, + {0x12u, 0x80u}, + {0x15u, 0x01u}, + {0x16u, 0xFFu}, + {0x18u, 0xC0u}, + {0x19u, 0x40u}, + {0x1Au, 0x04u}, + {0x1Cu, 0xC0u}, {0x1Du, 0x04u}, - {0x20u, 0x10u}, - {0x21u, 0x01u}, - {0x22u, 0x20u}, + {0x1Eu, 0x02u}, + {0x21u, 0x10u}, + {0x22u, 0x60u}, + {0x25u, 0x87u}, + {0x27u, 0x18u}, + {0x28u, 0xC0u}, + {0x2Au, 0x08u}, + {0x2Cu, 0x90u}, + {0x2Du, 0x01u}, + {0x2Eu, 0x40u}, + {0x31u, 0x80u}, + {0x32u, 0xFFu}, + {0x33u, 0x40u}, + {0x35u, 0x3Fu}, + {0x37u, 0x08u}, + {0x39u, 0x20u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x51u}, + {0x54u, 0x09u}, + {0x56u, 0x04u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x90u}, + {0x5Du, 0x10u}, + {0x5Fu, 0x01u}, + {0x81u, 0x9Cu}, + {0x84u, 0x01u}, + {0x89u, 0x61u}, + {0x8Bu, 0x1Eu}, + {0x8Cu, 0x01u}, + {0x8Du, 0xA4u}, + {0x8Eu, 0x02u}, + {0x8Fu, 0x10u}, + {0x91u, 0x8Cu}, + {0x93u, 0x10u}, + {0x95u, 0x30u}, + {0x97u, 0x8Fu}, + {0x98u, 0x02u}, + {0x99u, 0xD1u}, + {0x9Bu, 0x22u}, + {0x9Du, 0x08u}, + {0x9Fu, 0x40u}, + {0xA1u, 0x9Cu}, + {0xA5u, 0x94u}, + {0xA7u, 0x08u}, + {0xADu, 0x10u}, + {0xAFu, 0x8Cu}, + {0xB0u, 0x03u}, + {0xB1u, 0x30u}, + {0xB3u, 0xC1u}, + {0xB7u, 0x0Fu}, + {0xBBu, 0x0Eu}, + {0xBEu, 0x01u}, + {0xD4u, 0x09u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDFu, 0x01u}, + {0x00u, 0x04u}, + {0x03u, 0x01u}, + {0x05u, 0x16u}, + {0x06u, 0x02u}, + {0x0Au, 0x08u}, + {0x0Eu, 0x56u}, + {0x14u, 0x40u}, + {0x15u, 0x50u}, + {0x19u, 0x01u}, + {0x1Fu, 0x04u}, + {0x20u, 0x40u}, + {0x21u, 0x88u}, + {0x26u, 0x44u}, + {0x27u, 0x48u}, + {0x28u, 0xA0u}, + {0x2Au, 0x80u}, + {0x2Du, 0x42u}, + {0x2Fu, 0x20u}, + {0x30u, 0x82u}, + {0x31u, 0x08u}, + {0x32u, 0x20u}, + {0x34u, 0x40u}, + {0x35u, 0x04u}, + {0x36u, 0x81u}, + {0x37u, 0x20u}, + {0x38u, 0xD0u}, + {0x3Au, 0x01u}, + {0x3Cu, 0x80u}, + {0x3Eu, 0x16u}, + {0x44u, 0x01u}, + {0x47u, 0x40u}, + {0x59u, 0x08u}, + {0x5Bu, 0x92u}, + {0x5Cu, 0x02u}, + {0x5Eu, 0x80u}, + {0x5Fu, 0x14u}, + {0x63u, 0x01u}, + {0x64u, 0x01u}, + {0x67u, 0x40u}, + {0x7Cu, 0x40u}, + {0x7Du, 0x80u}, + {0x80u, 0xB0u}, + {0x81u, 0x35u}, + {0x82u, 0x81u}, + {0x84u, 0x02u}, + {0x85u, 0x80u}, + {0x8Au, 0x04u}, + {0x8Bu, 0x40u}, + {0x8Du, 0x81u}, + {0x8Eu, 0x22u}, + {0x90u, 0x04u}, + {0x93u, 0x83u}, + {0x94u, 0x91u}, + {0x99u, 0x08u}, + {0x9Bu, 0x21u}, + {0x9Cu, 0x20u}, + {0x9Du, 0xA0u}, + {0x9Eu, 0x01u}, + {0xA0u, 0x80u}, + {0xA4u, 0x02u}, + {0xA5u, 0xDDu}, + {0xA6u, 0x0Au}, + {0xABu, 0x08u}, + {0xAFu, 0x01u}, + {0xB2u, 0x01u}, + {0xB4u, 0x10u}, + {0xB5u, 0x10u}, + {0xB7u, 0x02u}, + {0xC0u, 0xF5u}, + {0xC2u, 0xF2u}, + {0xC4u, 0xD0u}, + {0xCAu, 0xDBu}, + {0xCCu, 0xFFu}, + {0xCEu, 0xFDu}, + {0xD6u, 0xFFu}, + {0xD8u, 0x98u}, + {0xE2u, 0x2Du}, + {0xE4u, 0x10u}, + {0xE6u, 0x05u}, + {0xE8u, 0x02u}, + {0xEAu, 0x25u}, + {0x00u, 0x11u}, + {0x01u, 0x40u}, + {0x02u, 0x22u}, + {0x03u, 0x03u}, + {0x04u, 0xFFu}, + {0x05u, 0x80u}, + {0x0Au, 0xFFu}, + {0x0Bu, 0x20u}, + {0x0Cu, 0x0Fu}, + {0x0Du, 0x40u}, + {0x0Eu, 0xF0u}, + {0x0Fu, 0x80u}, + {0x10u, 0x33u}, + {0x12u, 0xCCu}, + {0x13u, 0x24u}, + {0x14u, 0x48u}, + {0x16u, 0x84u}, + {0x17u, 0x18u}, + {0x18u, 0x12u}, + {0x19u, 0x24u}, + {0x1Au, 0x21u}, + {0x1Bu, 0x09u}, + {0x1Cu, 0xFFu}, + {0x24u, 0x44u}, + {0x26u, 0x88u}, + {0x27u, 0x04u}, + {0x29u, 0x24u}, + {0x2Bu, 0x12u}, + {0x30u, 0xFFu}, + {0x31u, 0x07u}, + {0x33u, 0x38u}, + {0x37u, 0xC0u}, + {0x3Eu, 0x01u}, + {0x3Fu, 0x40u}, + {0x56u, 0x02u}, + {0x57u, 0x2Cu}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x20u}, + {0x5Fu, 0x01u}, + {0x80u, 0x0Fu}, + {0x82u, 0xF0u}, + {0x84u, 0xFFu}, + {0x85u, 0x44u}, + {0x87u, 0x88u}, + {0x89u, 0x84u}, + {0x8Bu, 0x48u}, + {0x8Fu, 0xFFu}, + {0x91u, 0x11u}, + {0x92u, 0xFFu}, + {0x93u, 0x22u}, + {0x94u, 0x33u}, + {0x96u, 0xCCu}, + {0x98u, 0xFFu}, + {0x9Bu, 0xFFu}, + {0x9Cu, 0x96u}, + {0x9Eu, 0x69u}, + {0xA0u, 0x55u}, + {0xA1u, 0x33u}, + {0xA2u, 0xAAu}, + {0xA3u, 0xCCu}, + {0xA5u, 0xFFu}, + {0xA6u, 0xFFu}, + {0xA9u, 0x21u}, + {0xABu, 0x12u}, + {0xADu, 0x0Fu}, + {0xAEu, 0xFFu}, + {0xAFu, 0xF0u}, + {0xB0u, 0xFFu}, + {0xB3u, 0xFFu}, + {0xBAu, 0x02u}, + {0xBFu, 0x04u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x02u}, + {0xDFu, 0x01u}, + {0x01u, 0x02u}, + {0x02u, 0x20u}, + {0x05u, 0x95u}, + {0x07u, 0xA2u}, + {0x08u, 0x0Au}, + {0x0Bu, 0x09u}, + {0x0Cu, 0x01u}, + {0x0Du, 0x40u}, + {0x0Eu, 0x12u}, + {0x0Fu, 0x98u}, + {0x10u, 0x10u}, + {0x11u, 0x08u}, + {0x12u, 0x42u}, + {0x15u, 0x04u}, + {0x19u, 0x02u}, + {0x1Fu, 0x01u}, + {0x22u, 0x08u}, {0x24u, 0x20u}, - {0x25u, 0x08u}, - {0x26u, 0x10u}, - {0x2Au, 0x04u}, - {0x2Cu, 0x04u}, - {0x2Du, 0x02u}, - {0x2Eu, 0x01u}, - {0x2Fu, 0x04u}, + {0x25u, 0x01u}, + {0x26u, 0x84u}, + {0x27u, 0x80u}, + {0x29u, 0x84u}, + {0x2Bu, 0x48u}, + {0x2Fu, 0x14u}, + {0x31u, 0x11u}, + {0x34u, 0x12u}, + {0x36u, 0x04u}, + {0x39u, 0x84u}, + {0x3Bu, 0x10u}, + {0x3Cu, 0x20u}, + {0x3Du, 0x86u}, + {0x48u, 0x02u}, + {0x4Au, 0x01u}, + {0x67u, 0x80u}, + {0x68u, 0x05u}, + {0x69u, 0x05u}, + {0x6Au, 0x12u}, + {0x6Cu, 0x01u}, + {0x6Eu, 0x04u}, + {0x6Fu, 0x66u}, + {0x70u, 0x04u}, + {0x71u, 0xA0u}, + {0x72u, 0x01u}, + {0x73u, 0x40u}, + {0x74u, 0x80u}, + {0x76u, 0x01u}, + {0x7Bu, 0x0Cu}, + {0x80u, 0x80u}, + {0x83u, 0x64u}, + {0x87u, 0x02u}, + {0x88u, 0x01u}, + {0x8Cu, 0x82u}, + {0x8Eu, 0x08u}, + {0x91u, 0x20u}, + {0x92u, 0x28u}, + {0x93u, 0xA8u}, + {0x94u, 0x68u}, + {0x95u, 0x01u}, + {0x96u, 0x01u}, + {0x97u, 0x42u}, + {0x98u, 0x0Fu}, + {0x99u, 0x38u}, + {0x9Au, 0x40u}, + {0x9Bu, 0x02u}, + {0x9Du, 0x02u}, + {0x9Eu, 0x0Cu}, + {0x9Fu, 0x08u}, + {0xA0u, 0x10u}, + {0xA1u, 0x44u}, + {0xA2u, 0x22u}, + {0xA3u, 0x08u}, + {0xA4u, 0x04u}, + {0xA5u, 0x20u}, + {0xA6u, 0x08u}, + {0xA8u, 0x04u}, + {0xA9u, 0x10u}, + {0xABu, 0x60u}, + {0xACu, 0x11u}, + {0xADu, 0x40u}, + {0xB4u, 0x80u}, + {0xB5u, 0x44u}, + {0xB7u, 0x40u}, + {0xC0u, 0xFCu}, + {0xC2u, 0xFFu}, + {0xC4u, 0x2Du}, + {0xCAu, 0x6Fu}, + {0xCCu, 0xE5u}, + {0xCEu, 0xFEu}, + {0xD8u, 0x80u}, + {0xE0u, 0x10u}, + {0xE2u, 0x80u}, + {0xE4u, 0x40u}, + {0xE8u, 0x10u}, + {0xEAu, 0x41u}, + {0xEEu, 0x43u}, + {0x05u, 0x50u}, + {0x06u, 0x04u}, + {0x07u, 0xA0u}, + {0x09u, 0x05u}, + {0x0Au, 0x03u}, + {0x0Bu, 0x0Au}, + {0x0Cu, 0x40u}, + {0x0Du, 0x30u}, + {0x0Fu, 0xC0u}, + {0x11u, 0x06u}, + {0x12u, 0x24u}, + {0x13u, 0x09u}, + {0x14u, 0x24u}, + {0x15u, 0x03u}, + {0x16u, 0x09u}, + {0x17u, 0x0Cu}, + {0x18u, 0x24u}, + {0x19u, 0x60u}, + {0x1Au, 0x12u}, + {0x1Bu, 0x90u}, + {0x1Cu, 0x40u}, + {0x22u, 0x18u}, + {0x24u, 0x40u}, + {0x28u, 0x40u}, + {0x2Du, 0x0Fu}, + {0x2Eu, 0x20u}, + {0x2Fu, 0xF0u}, {0x30u, 0x40u}, - {0x32u, 0x08u}, - {0x33u, 0x08u}, - {0x34u, 0x30u}, - {0x35u, 0x01u}, - {0x36u, 0x07u}, - {0x37u, 0x06u}, - {0x3Au, 0x20u}, + {0x32u, 0x07u}, + {0x34u, 0x38u}, + {0x37u, 0xFFu}, + {0x3Eu, 0x01u}, {0x3Fu, 0x40u}, {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x91u}, + {0x5Cu, 0x02u}, {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x82u, 0xFFu}, - {0x84u, 0xFFu}, - {0x87u, 0xFFu}, - {0x8Bu, 0xFFu}, - {0x90u, 0x55u}, - {0x91u, 0x33u}, - {0x92u, 0xAAu}, - {0x93u, 0xCCu}, - {0x94u, 0x33u}, - {0x95u, 0x21u}, - {0x96u, 0xCCu}, - {0x97u, 0x12u}, - {0x98u, 0xFFu}, - {0x9Du, 0x0Fu}, - {0x9Fu, 0xF0u}, - {0xA0u, 0x96u}, - {0xA1u, 0x84u}, - {0xA2u, 0x69u}, - {0xA3u, 0x48u}, - {0xA5u, 0x44u}, - {0xA6u, 0xFFu}, - {0xA7u, 0x88u}, - {0xA8u, 0x0Fu}, - {0xA9u, 0xFFu}, - {0xAAu, 0xF0u}, - {0xADu, 0x11u}, - {0xAEu, 0xFFu}, - {0xAFu, 0x22u}, - {0xB1u, 0xFFu}, - {0xB2u, 0xFFu}, - {0xB8u, 0x02u}, - {0xBAu, 0x08u}, - {0xBEu, 0x01u}, - {0xBFu, 0x01u}, + {0x81u, 0x01u}, + {0x83u, 0x02u}, + {0x84u, 0x04u}, + {0x85u, 0x04u}, + {0x86u, 0x08u}, + {0x87u, 0x08u}, + {0x89u, 0x01u}, + {0x8Au, 0x3Fu}, + {0x8Bu, 0x02u}, + {0x8Cu, 0x3Fu}, + {0x8Du, 0x50u}, + {0x8Fu, 0x8Fu}, + {0x91u, 0x10u}, + {0x92u, 0x3Fu}, + {0x93u, 0x8Fu}, + {0x94u, 0x3Fu}, + {0x95u, 0x20u}, + {0x97u, 0x0Fu}, + {0x98u, 0x01u}, + {0x99u, 0x0Fu}, + {0x9Au, 0x02u}, + {0x9Bu, 0x80u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x04u}, + {0x9Eu, 0x20u}, + {0x9Fu, 0x08u}, + {0xA0u, 0x10u}, + {0xA1u, 0x4Fu}, + {0xA2u, 0x20u}, + {0xA3u, 0x80u}, + {0xA4u, 0x04u}, + {0xA6u, 0x08u}, + {0xA7u, 0x10u}, + {0xA8u, 0x01u}, + {0xAAu, 0x02u}, + {0xAEu, 0x3Fu}, + {0xB1u, 0x03u}, + {0xB2u, 0x0Cu}, + {0xB3u, 0xF0u}, + {0xB4u, 0x03u}, + {0xB6u, 0x30u}, + {0xB7u, 0x0Cu}, + {0xB9u, 0x08u}, + {0xBAu, 0xA8u}, + {0xBBu, 0x82u}, + {0xD4u, 0x01u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x01u}, + {0xDCu, 0x22u}, + {0xDDu, 0x20u}, {0xDFu, 0x01u}, - {0x01u, 0x01u}, - {0x03u, 0x20u}, - {0x05u, 0x40u}, - {0x06u, 0x20u}, - {0x07u, 0x08u}, - {0x08u, 0x0Au}, - {0x0Au, 0x04u}, - {0x0Du, 0x02u}, - {0x0Eu, 0x24u}, - {0x10u, 0x86u}, - {0x11u, 0xC0u}, + {0x00u, 0x40u}, + {0x01u, 0x04u}, + {0x03u, 0x08u}, + {0x05u, 0x04u}, + {0x06u, 0x02u}, + {0x07u, 0x04u}, + {0x08u, 0x02u}, + {0x09u, 0x04u}, + {0x0Bu, 0x0Au}, + {0x0Eu, 0x28u}, + {0x0Fu, 0x82u}, + {0x10u, 0x42u}, + {0x12u, 0x08u}, {0x13u, 0x08u}, - {0x15u, 0x41u}, - {0x17u, 0x16u}, - {0x19u, 0x08u}, - {0x1Au, 0x80u}, - {0x1Du, 0x42u}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x14u}, - {0x23u, 0x40u}, - {0x24u, 0x08u}, - {0x26u, 0x08u}, - {0x27u, 0x01u}, - {0x28u, 0x40u}, + {0x14u, 0x02u}, + {0x15u, 0x02u}, + {0x16u, 0x20u}, + {0x17u, 0x10u}, + {0x1Au, 0x48u}, + {0x1Bu, 0x08u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x04u}, + {0x1Eu, 0x08u}, + {0x1Fu, 0x80u}, + {0x23u, 0x02u}, + {0x25u, 0x05u}, + {0x26u, 0x80u}, + {0x28u, 0x01u}, {0x29u, 0x40u}, - {0x2Au, 0x08u}, - {0x2Bu, 0x88u}, - {0x2Fu, 0x52u}, - {0x31u, 0x08u}, - {0x32u, 0x80u}, - {0x33u, 0x02u}, - {0x34u, 0x44u}, - {0x35u, 0x08u}, - {0x37u, 0x20u}, - {0x39u, 0x08u}, - {0x3Au, 0x14u}, - {0x45u, 0x80u}, - {0x46u, 0x01u}, - {0x59u, 0x04u}, - {0x5Au, 0x10u}, - {0x5Bu, 0x82u}, - {0x5Cu, 0x40u}, - {0x5Fu, 0x10u}, - {0x61u, 0x80u}, - {0x66u, 0x20u}, - {0x67u, 0x02u}, - {0x6Fu, 0x02u}, - {0x82u, 0x40u}, - {0x86u, 0x08u}, - {0x8Au, 0x8Au}, - {0x8Du, 0x04u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x80u}, - {0x92u, 0x04u}, - {0x93u, 0x80u}, - {0x97u, 0x6Au}, - {0x98u, 0x0Au}, + {0x2Du, 0x08u}, + {0x2Eu, 0x02u}, + {0x2Fu, 0x20u}, + {0x31u, 0x20u}, + {0x32u, 0x05u}, + {0x34u, 0x02u}, + {0x36u, 0xA0u}, + {0x37u, 0x04u}, + {0x38u, 0x28u}, + {0x3Bu, 0x40u}, + {0x3Du, 0x02u}, + {0x3Fu, 0xA8u}, + {0x58u, 0x10u}, + {0x5Bu, 0x40u}, + {0x5Du, 0x80u}, + {0x60u, 0x08u}, + {0x62u, 0x40u}, + {0x63u, 0x08u}, + {0x79u, 0x02u}, + {0x7Bu, 0x80u}, + {0x81u, 0x01u}, + {0x85u, 0x30u}, + {0x87u, 0x80u}, + {0x88u, 0x40u}, + {0x8Au, 0x04u}, + {0x8Cu, 0x20u}, + {0x8Du, 0x08u}, + {0x8Eu, 0x42u}, + {0x8Fu, 0x04u}, + {0x91u, 0x44u}, + {0x92u, 0x22u}, + {0x93u, 0xA8u}, + {0x95u, 0x01u}, + {0x96u, 0x01u}, + {0x98u, 0x06u}, {0x99u, 0x80u}, - {0x9Au, 0x11u}, - {0x9Bu, 0x3Cu}, - {0x9Du, 0x40u}, - {0x9Eu, 0x0Cu}, - {0x9Fu, 0x01u}, - {0xA0u, 0x82u}, - {0xA1u, 0x08u}, - {0xA2u, 0x01u}, - {0xA3u, 0xBCu}, + {0x9Au, 0x22u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x80u}, + {0x9Du, 0x46u}, + {0x9Eu, 0x4Cu}, + {0xA0u, 0x12u}, + {0xA2u, 0x30u}, + {0xA3u, 0x31u}, + {0xA4u, 0x24u}, + {0xA5u, 0x2Cu}, {0xA6u, 0x80u}, - {0xA7u, 0x02u}, - {0xABu, 0x20u}, - {0xACu, 0x40u}, - {0xAFu, 0x80u}, - {0xB3u, 0x02u}, - {0xB7u, 0x08u}, - {0xC0u, 0xECu}, - {0xC2u, 0x7Eu}, - {0xC4u, 0xFFu}, - {0xCAu, 0xDFu}, - {0xCCu, 0x3Bu}, - {0xCEu, 0x06u}, - {0xD6u, 0x3Fu}, - {0xD8u, 0x38u}, - {0xE2u, 0x09u}, - {0xE6u, 0xA2u}, - {0xE8u, 0x03u}, - {0xEEu, 0x08u}, - {0x85u, 0x04u}, - {0x88u, 0x01u}, - {0x8Du, 0x02u}, - {0x91u, 0x04u}, - {0x9Bu, 0x20u}, - {0x9Cu, 0xD1u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x01u}, - {0xA1u, 0x22u}, - {0xA5u, 0x08u}, - {0xAAu, 0x02u}, + {0xA7u, 0x48u}, + {0xA8u, 0x40u}, {0xABu, 0x04u}, - {0xADu, 0x10u}, - {0xAEu, 0x10u}, - {0xB0u, 0x02u}, - {0xB1u, 0x04u}, - {0xB5u, 0x41u}, - {0xE2u, 0x89u}, - {0xE6u, 0x10u}, - {0xEAu, 0x10u}, - {0xECu, 0x80u}, - {0x00u, 0x0Fu}, - {0x02u, 0xF0u}, - {0x04u, 0x11u}, - {0x05u, 0x44u}, - {0x06u, 0x22u}, - {0x07u, 0x88u}, - {0x08u, 0x12u}, - {0x09u, 0x48u}, - {0x0Au, 0x21u}, - {0x0Bu, 0x84u}, - {0x0Du, 0x0Fu}, - {0x0Fu, 0xF0u}, - {0x11u, 0x12u}, - {0x12u, 0xFFu}, - {0x13u, 0x21u}, - {0x16u, 0xFFu}, - {0x19u, 0xFFu}, - {0x1Au, 0xFFu}, - {0x1Du, 0xFFu}, - {0x21u, 0x33u}, - {0x23u, 0xCCu}, - {0x24u, 0x44u}, - {0x25u, 0x11u}, - {0x26u, 0x88u}, - {0x27u, 0x22u}, - {0x28u, 0x48u}, - {0x2Au, 0x84u}, - {0x2Bu, 0xFFu}, - {0x2Cu, 0x33u}, - {0x2Eu, 0xCCu}, - {0x35u, 0xFFu}, - {0x36u, 0xFFu}, - {0x3Eu, 0x40u}, + {0xADu, 0x20u}, + {0xAFu, 0x88u}, + {0xB2u, 0x04u}, + {0xB4u, 0x42u}, + {0xC0u, 0xE7u}, + {0xC2u, 0xFFu}, + {0xC4u, 0xFFu}, + {0xCAu, 0xC8u}, + {0xCCu, 0xF7u}, + {0xCEu, 0xFEu}, + {0xD6u, 0x1Cu}, + {0xD8u, 0x0Cu}, + {0xE4u, 0x10u}, + {0xE6u, 0x80u}, + {0xE8u, 0x51u}, + {0xECu, 0x08u}, + {0xEEu, 0x02u}, + {0x01u, 0x02u}, + {0x03u, 0x01u}, + {0x08u, 0x01u}, + {0x0Au, 0x06u}, + {0x0Du, 0x02u}, + {0x0Fu, 0x01u}, + {0x11u, 0x10u}, + {0x13u, 0x20u}, + {0x15u, 0x01u}, + {0x17u, 0x12u}, + {0x1Cu, 0x04u}, + {0x1Eu, 0x03u}, + {0x20u, 0x03u}, + {0x22u, 0x04u}, + {0x25u, 0x02u}, + {0x27u, 0x09u}, + {0x28u, 0x05u}, + {0x2Au, 0x02u}, + {0x2Du, 0x02u}, + {0x2Fu, 0x25u}, + {0x31u, 0x08u}, + {0x33u, 0x03u}, + {0x35u, 0x30u}, + {0x36u, 0x07u}, + {0x37u, 0x04u}, + {0x3Au, 0x80u}, + {0x3Bu, 0x08u}, {0x3Fu, 0x10u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Cu, 0x20u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x80u, 0x01u}, - {0x81u, 0x02u}, - {0x82u, 0x02u}, - {0x83u, 0x05u}, - {0x84u, 0x04u}, - {0x85u, 0x02u}, - {0x87u, 0x21u}, - {0x88u, 0x04u}, - {0x89u, 0x02u}, - {0x8Bu, 0x01u}, - {0x8Cu, 0x02u}, - {0x8Du, 0x02u}, - {0x8Eu, 0x01u}, - {0x8Fu, 0x01u}, - {0x91u, 0x10u}, - {0x94u, 0x02u}, - {0x96u, 0x09u}, - {0x99u, 0x01u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0x04u}, + {0x81u, 0x24u}, + {0x83u, 0x12u}, + {0x84u, 0x40u}, + {0x88u, 0x20u}, + {0x8Bu, 0x18u}, + {0x8Fu, 0x20u}, + {0x90u, 0x29u}, + {0x91u, 0x40u}, + {0x92u, 0x52u}, + {0x93u, 0x03u}, + {0x94u, 0x08u}, + {0x97u, 0x04u}, + {0x99u, 0x80u}, + {0x9Cu, 0x10u}, + {0x9Du, 0x40u}, + {0x9Fu, 0x80u}, {0xA0u, 0x02u}, - {0xA2u, 0x01u}, - {0xA4u, 0x02u}, - {0xA5u, 0x08u}, - {0xA6u, 0x11u}, - {0xA8u, 0x04u}, - {0xADu, 0x08u}, - {0xAFu, 0x10u}, + {0xA1u, 0x24u}, + {0xA3u, 0x09u}, + {0xA8u, 0x01u}, + {0xAEu, 0x04u}, + {0xAFu, 0x24u}, {0xB0u, 0x03u}, - {0xB1u, 0x18u}, - {0xB2u, 0x10u}, - {0xB3u, 0x03u}, - {0xB4u, 0x04u}, - {0xB5u, 0x04u}, - {0xB6u, 0x08u}, - {0xB7u, 0x20u}, - {0xBAu, 0x02u}, - {0xBBu, 0x08u}, - {0xBEu, 0x10u}, - {0xBFu, 0x01u}, + {0xB1u, 0x07u}, + {0xB2u, 0x04u}, + {0xB3u, 0xC0u}, + {0xB4u, 0x60u}, + {0xB5u, 0x38u}, + {0xB6u, 0x18u}, + {0xBEu, 0x51u}, + {0xBFu, 0x04u}, {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, - {0xDCu, 0x11u}, + {0xDCu, 0x22u}, {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x00u, 0x02u}, - {0x02u, 0x40u}, - {0x03u, 0x24u}, - {0x04u, 0x80u}, - {0x05u, 0x21u}, - {0x06u, 0x10u}, - {0x08u, 0x04u}, - {0x09u, 0x25u}, - {0x0Au, 0x80u}, - {0x0Eu, 0x21u}, - {0x10u, 0x02u}, - {0x11u, 0x14u}, - {0x12u, 0x01u}, - {0x15u, 0x21u}, - {0x16u, 0x20u}, - {0x1Au, 0x01u}, - {0x1Du, 0x13u}, - {0x1Eu, 0x20u}, + {0x00u, 0x08u}, + {0x03u, 0x08u}, + {0x06u, 0x08u}, + {0x0Au, 0xA1u}, + {0x0Eu, 0x02u}, + {0x10u, 0x04u}, + {0x11u, 0x81u}, + {0x14u, 0x80u}, + {0x16u, 0x04u}, + {0x18u, 0x80u}, + {0x19u, 0x18u}, + {0x1Bu, 0x80u}, + {0x1Eu, 0x02u}, {0x1Fu, 0x40u}, {0x21u, 0x10u}, - {0x24u, 0x01u}, - {0x25u, 0x11u}, - {0x27u, 0x20u}, - {0x28u, 0x04u}, - {0x2Au, 0x01u}, - {0x2Bu, 0x20u}, - {0x2Cu, 0x02u}, - {0x2Du, 0x09u}, - {0x2Fu, 0x40u}, - {0x31u, 0x20u}, - {0x32u, 0x42u}, - {0x37u, 0x22u}, - {0x39u, 0x14u}, - {0x3Au, 0x40u}, - {0x3Cu, 0x01u}, - {0x3Du, 0xA0u}, - {0x3Eu, 0x08u}, - {0x5Du, 0x40u}, - {0x5Eu, 0x10u}, - {0x5Fu, 0x04u}, - {0x65u, 0x80u}, - {0x66u, 0x28u}, - {0x81u, 0x88u}, - {0x85u, 0x20u}, - {0x88u, 0x08u}, - {0x8Au, 0x01u}, - {0x8Bu, 0x20u}, - {0x8Du, 0x10u}, - {0x8Eu, 0x10u}, - {0x90u, 0x80u}, - {0x91u, 0x14u}, - {0x93u, 0x04u}, - {0x95u, 0x08u}, - {0x96u, 0x02u}, - {0x97u, 0x80u}, - {0x9Bu, 0x02u}, - {0x9Cu, 0xD9u}, - {0x9Eu, 0x04u}, - {0xA0u, 0x01u}, - {0xA1u, 0x64u}, - {0xA5u, 0x19u}, - {0xAAu, 0x40u}, - {0xB0u, 0x04u}, - {0xB2u, 0x02u}, - {0xB4u, 0x04u}, - {0xB7u, 0x08u}, - {0xC0u, 0xFEu}, - {0xC2u, 0xAEu}, - {0xC4u, 0x77u}, - {0xCAu, 0x57u}, - {0xCCu, 0xADu}, - {0xCEu, 0xFEu}, - {0xD6u, 0x70u}, - {0xD8u, 0x70u}, - {0xE0u, 0xA0u}, - {0xE2u, 0x02u}, - {0xE4u, 0x30u}, - {0xE6u, 0x01u}, - {0xE8u, 0x10u}, - {0xEAu, 0x40u}, - {0xECu, 0xA1u}, - {0xEEu, 0x02u}, - {0x00u, 0x30u}, - {0x02u, 0xC0u}, - {0x03u, 0x08u}, - {0x04u, 0x50u}, - {0x05u, 0x40u}, - {0x06u, 0xA0u}, - {0x07u, 0x01u}, - {0x08u, 0x0Fu}, - {0x0Au, 0xF0u}, - {0x0Bu, 0x20u}, - {0x0Du, 0x01u}, - {0x0Fu, 0x0Eu}, - {0x11u, 0x18u}, - {0x13u, 0x03u}, - {0x14u, 0x06u}, - {0x15u, 0x03u}, - {0x16u, 0x09u}, - {0x17u, 0x14u}, - {0x18u, 0x60u}, - {0x19u, 0x02u}, - {0x1Au, 0x90u}, - {0x1Cu, 0x03u}, - {0x1Eu, 0x0Cu}, - {0x20u, 0x05u}, - {0x22u, 0x0Au}, - {0x23u, 0x80u}, - {0x27u, 0x1Fu}, - {0x29u, 0x04u}, - {0x31u, 0x80u}, - {0x33u, 0x1Fu}, - {0x35u, 0x40u}, - {0x36u, 0xFFu}, - {0x37u, 0x20u}, - {0x3Eu, 0x40u}, - {0x3Fu, 0x10u}, - {0x58u, 0x04u}, - {0x59u, 0x04u}, - {0x5Cu, 0x10u}, - {0x5Fu, 0x01u}, - {0x80u, 0x04u}, - {0x81u, 0x80u}, - {0x84u, 0x10u}, - {0x85u, 0x53u}, - {0x87u, 0xACu}, - {0x89u, 0x01u}, - {0x8Bu, 0x02u}, - {0x8Du, 0x40u}, - {0x91u, 0x12u}, - {0x93u, 0x01u}, - {0x94u, 0x01u}, - {0x98u, 0x15u}, - {0x9Au, 0x2Au}, - {0x9Cu, 0x20u}, - {0x9Du, 0x28u}, - {0x9Fu, 0x04u}, - {0xA1u, 0x04u}, - {0xA3u, 0x08u}, - {0xA4u, 0x02u}, - {0xA8u, 0x08u}, - {0xB0u, 0x0Cu}, - {0xB1u, 0xC0u}, - {0xB2u, 0x03u}, - {0xB3u, 0x30u}, - {0xB4u, 0x30u}, - {0xB5u, 0x0Fu}, - {0xBEu, 0x15u}, - {0xBFu, 0x15u}, - {0xD8u, 0x04u}, - {0xD9u, 0x04u}, - {0xDBu, 0x04u}, - {0xDFu, 0x01u}, - {0x02u, 0x50u}, - {0x04u, 0x02u}, - {0x05u, 0x04u}, - {0x06u, 0x08u}, - {0x08u, 0x04u}, - {0x09u, 0x80u}, - {0x0Bu, 0x08u}, - {0x0Cu, 0x24u}, - {0x0Du, 0x40u}, - {0x0Fu, 0x01u}, - {0x10u, 0x20u}, - {0x13u, 0x20u}, - {0x15u, 0x02u}, - {0x16u, 0x40u}, - {0x18u, 0x04u}, - {0x1Au, 0x90u}, - {0x1Cu, 0x02u}, - {0x20u, 0x90u}, - {0x21u, 0x20u}, - {0x24u, 0xA0u}, - {0x25u, 0x40u}, - {0x26u, 0x18u}, - {0x2Au, 0x02u}, - {0x2Cu, 0x10u}, - {0x2Fu, 0x48u}, - {0x32u, 0x01u}, - {0x33u, 0x40u}, - {0x35u, 0x20u}, - {0x36u, 0x0Au}, - {0x38u, 0x02u}, - {0x39u, 0x88u}, - {0x3Au, 0x18u}, - {0x3Bu, 0x08u}, - {0x3Du, 0x28u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x82u}, - {0x69u, 0x14u}, - {0x6Bu, 0x52u}, - {0x70u, 0x21u}, - {0x71u, 0x84u}, - {0x72u, 0x02u}, - {0x73u, 0x20u}, + {0x22u, 0x15u}, + {0x25u, 0x41u}, + {0x26u, 0x34u}, + {0x27u, 0x0Cu}, + {0x28u, 0x02u}, + {0x2Bu, 0x40u}, + {0x2Du, 0x08u}, + {0x2Fu, 0x01u}, + {0x31u, 0x60u}, + {0x32u, 0x49u}, + {0x36u, 0x04u}, + {0x37u, 0x01u}, + {0x39u, 0xA0u}, + {0x3Au, 0x02u}, + {0x3Du, 0x82u}, + {0x59u, 0x20u}, + {0x5Au, 0x44u}, + {0x5Cu, 0x50u}, + {0x63u, 0x2Au}, + {0x66u, 0x20u}, + {0x67u, 0x02u}, + {0x6Bu, 0x01u}, + {0x6Du, 0x40u}, + {0x6Eu, 0x10u}, + {0x6Fu, 0x20u}, {0x80u, 0x10u}, + {0x81u, 0x10u}, {0x82u, 0x50u}, - {0x86u, 0x08u}, - {0x87u, 0x01u}, - {0x88u, 0x40u}, - {0x89u, 0x01u}, - {0x8Au, 0x10u}, - {0x8Du, 0x01u}, - {0x92u, 0x44u}, - {0x93u, 0x05u}, - {0x94u, 0x20u}, - {0x95u, 0x08u}, - {0x99u, 0x20u}, - {0x9Au, 0x10u}, - {0x9Cu, 0xC9u}, - {0x9Eu, 0x04u}, - {0x9Fu, 0x10u}, - {0xA3u, 0x40u}, - {0xA5u, 0x08u}, - {0xA6u, 0x0Au}, - {0xA8u, 0x04u}, - {0xAAu, 0xA0u}, - {0xABu, 0x04u}, - {0xAFu, 0x04u}, - {0xB0u, 0x04u}, - {0xB1u, 0x80u}, - {0xB2u, 0x04u}, - {0xB6u, 0x02u}, - {0xC0u, 0x7Cu}, - {0xC2u, 0xE7u}, - {0xC4u, 0x16u}, - {0xCAu, 0xE1u}, - {0xCCu, 0xE9u}, - {0xCEu, 0xFFu}, - {0xE0u, 0x21u}, - {0xE2u, 0x80u}, - {0xE4u, 0x01u}, - {0xE8u, 0x60u}, - {0xEAu, 0x88u}, - {0xECu, 0x81u}, - {0xEEu, 0x20u}, - {0x00u, 0x02u}, + {0x84u, 0x04u}, + {0x85u, 0x04u}, + {0x87u, 0x20u}, + {0x8Au, 0x04u}, + {0x91u, 0x80u}, + {0x93u, 0x28u}, + {0x99u, 0x80u}, + {0x9Au, 0x02u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x06u}, + {0x9Eu, 0x60u}, + {0x9Fu, 0x04u}, + {0xA0u, 0x12u}, + {0xA2u, 0x08u}, + {0xA4u, 0x20u}, + {0xA5u, 0x0Cu}, + {0xA6u, 0xA4u}, + {0xA7u, 0x75u}, + {0xA8u, 0x61u}, + {0xA9u, 0x04u}, + {0xAAu, 0x08u}, + {0xADu, 0x10u}, + {0xAFu, 0x08u}, + {0xB1u, 0x08u}, + {0xB4u, 0x02u}, + {0xB7u, 0x80u}, + {0xC0u, 0x46u}, + {0xC2u, 0x8Du}, + {0xC4u, 0x5Bu}, + {0xCAu, 0x59u}, + {0xCCu, 0xCFu}, + {0xCEu, 0x9Du}, + {0xD6u, 0x3Eu}, + {0xD8u, 0x3Eu}, + {0xE2u, 0x04u}, + {0xE4u, 0x04u}, + {0xE6u, 0x01u}, + {0xE8u, 0x80u}, + {0xEAu, 0x40u}, + {0xECu, 0x40u}, + {0x00u, 0x06u}, + {0x01u, 0x55u}, {0x02u, 0x09u}, - {0x04u, 0x02u}, - {0x05u, 0x08u}, - {0x06u, 0x11u}, - {0x07u, 0x10u}, - {0x0Du, 0x04u}, - {0x0Fu, 0x03u}, - {0x11u, 0x01u}, - {0x13u, 0x06u}, - {0x14u, 0x02u}, - {0x15u, 0x03u}, - {0x16u, 0x01u}, - {0x17u, 0x04u}, - {0x18u, 0x01u}, - {0x19u, 0x10u}, - {0x1Au, 0x02u}, - {0x1Cu, 0x02u}, - {0x1Eu, 0x05u}, - {0x21u, 0x05u}, - {0x23u, 0x02u}, - {0x29u, 0x08u}, - {0x30u, 0x10u}, - {0x32u, 0x04u}, - {0x34u, 0x03u}, - {0x35u, 0x18u}, - {0x36u, 0x08u}, - {0x37u, 0x07u}, - {0x3Au, 0x20u}, - {0x3Bu, 0x80u}, - {0x3Fu, 0x10u}, - {0x54u, 0x01u}, + {0x03u, 0xAAu}, + {0x04u, 0x0Fu}, + {0x05u, 0xFFu}, + {0x09u, 0x69u}, + {0x0Bu, 0x96u}, + {0x10u, 0x40u}, + {0x11u, 0x0Fu}, + {0x12u, 0x1Fu}, + {0x13u, 0xF0u}, + {0x14u, 0x10u}, + {0x16u, 0x2Fu}, + {0x17u, 0xFFu}, + {0x19u, 0xFFu}, + {0x1Eu, 0x70u}, + {0x23u, 0xFFu}, + {0x24u, 0x05u}, + {0x26u, 0x0Au}, + {0x28u, 0x20u}, + {0x29u, 0x33u}, + {0x2Au, 0x4Fu}, + {0x2Bu, 0xCCu}, + {0x2Cu, 0x03u}, + {0x2Eu, 0x0Cu}, + {0x2Fu, 0xFFu}, + {0x31u, 0xFFu}, + {0x36u, 0x7Fu}, + {0x3Bu, 0x02u}, + {0x56u, 0x08u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x01u}, - {0x5Du, 0x10u}, + {0x5Cu, 0x22u}, + {0x5Du, 0x90u}, {0x5Fu, 0x01u}, - {0x83u, 0x18u}, - {0x84u, 0x90u}, - {0x86u, 0x2Fu}, - {0x87u, 0x20u}, - {0x88u, 0xC0u}, - {0x89u, 0x40u}, - {0x8Au, 0x1Fu}, - {0x8Cu, 0x03u}, - {0x8Eu, 0x0Cu}, - {0x8Fu, 0x04u}, - {0x91u, 0x24u}, - {0x93u, 0x12u}, - {0x96u, 0x70u}, - {0x97u, 0x24u}, - {0x98u, 0x0Fu}, - {0x9Eu, 0x80u}, - {0xA0u, 0x06u}, - {0xA2u, 0x09u}, - {0xA7u, 0x03u}, - {0xA8u, 0x05u}, - {0xA9u, 0x24u}, - {0xAAu, 0x0Au}, - {0xABu, 0x09u}, - {0xACu, 0xA0u}, - {0xAEu, 0x4Fu}, - {0xB0u, 0x80u}, - {0xB2u, 0x7Fu}, - {0xB3u, 0x07u}, - {0xB5u, 0x40u}, - {0xB7u, 0x38u}, - {0xBEu, 0x01u}, - {0xBFu, 0x10u}, + {0x80u, 0x0Bu}, + {0x81u, 0x55u}, + {0x82u, 0xF4u}, + {0x83u, 0xAAu}, + {0x84u, 0x02u}, + {0x88u, 0x10u}, + {0x89u, 0x69u}, + {0x8Au, 0x20u}, + {0x8Bu, 0x96u}, + {0x8Cu, 0x40u}, + {0x8Eu, 0x80u}, + {0x8Fu, 0xFFu}, + {0x90u, 0x08u}, + {0x92u, 0xF7u}, + {0x93u, 0xFFu}, + {0x95u, 0x0Fu}, + {0x96u, 0xF7u}, + {0x97u, 0xF0u}, + {0x98u, 0x03u}, + {0x99u, 0xFFu}, + {0x9Au, 0x0Cu}, + {0x9Cu, 0x10u}, + {0x9Eu, 0x20u}, + {0xA0u, 0x40u}, + {0xA1u, 0xFFu}, + {0xA2u, 0x80u}, + {0xA4u, 0xF4u}, + {0xA7u, 0xFFu}, + {0xA8u, 0xFDu}, + {0xA9u, 0x33u}, + {0xAAu, 0x02u}, + {0xABu, 0xCCu}, + {0xAEu, 0x01u}, + {0xB2u, 0x30u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0xFFu}, + {0xB6u, 0xC0u}, + {0xBAu, 0xA8u}, + {0xBBu, 0x20u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDBu, 0x04u}, + {0xDCu, 0x22u}, + {0xDFu, 0x01u}, + {0x01u, 0x02u}, + {0x03u, 0x20u}, + {0x04u, 0x10u}, + {0x05u, 0x41u}, + {0x07u, 0x20u}, + {0x08u, 0x02u}, + {0x09u, 0x04u}, + {0x0Au, 0x01u}, + {0x0Du, 0x08u}, + {0x0Eu, 0x04u}, + {0x0Fu, 0x81u}, + {0x12u, 0x06u}, + {0x13u, 0x08u}, + {0x16u, 0x45u}, + {0x17u, 0x04u}, + {0x19u, 0x80u}, + {0x1Au, 0x01u}, + {0x1Cu, 0x10u}, + {0x1Du, 0x40u}, + {0x1Eu, 0x04u}, + {0x1Fu, 0x88u}, + {0x22u, 0x02u}, + {0x27u, 0x08u}, + {0x28u, 0x02u}, + {0x2Bu, 0x44u}, + {0x2Cu, 0x20u}, + {0x2Eu, 0x22u}, + {0x31u, 0x08u}, + {0x32u, 0x22u}, + {0x34u, 0x02u}, + {0x35u, 0x01u}, + {0x36u, 0x20u}, + {0x37u, 0x08u}, + {0x3Au, 0x14u}, + {0x3Bu, 0x09u}, + {0x3Fu, 0xA2u}, + {0x41u, 0x20u}, + {0x43u, 0x10u}, + {0x58u, 0x10u}, + {0x5Au, 0x80u}, + {0x5Cu, 0x41u}, + {0x5Du, 0x18u}, + {0x61u, 0x20u}, + {0x62u, 0x10u}, + {0x63u, 0x01u}, + {0x67u, 0x02u}, + {0x82u, 0x41u}, + {0x83u, 0x20u}, + {0x84u, 0x10u}, + {0x86u, 0x06u}, + {0x87u, 0x14u}, + {0x88u, 0x10u}, + {0x8Au, 0x80u}, + {0x8Du, 0x40u}, + {0x8Eu, 0x04u}, + {0x8Fu, 0x01u}, + {0xC0u, 0xFCu}, + {0xC2u, 0xFDu}, + {0xC4u, 0xF7u}, + {0xCAu, 0xEDu}, + {0xCCu, 0xE7u}, + {0xCEu, 0xB7u}, + {0xD6u, 0xFCu}, + {0xD8u, 0x1Cu}, + {0xE2u, 0x80u}, + {0xE4u, 0x10u}, + {0xE6u, 0x01u}, + {0x01u, 0x88u}, + {0x03u, 0x03u}, + {0x09u, 0x04u}, + {0x0Bu, 0x43u}, + {0x11u, 0xE0u}, + {0x17u, 0xECu}, + {0x19u, 0x21u}, + {0x1Bu, 0x02u}, + {0x1Fu, 0x01u}, + {0x23u, 0x12u}, + {0x33u, 0x0Fu}, + {0x35u, 0xE0u}, + {0x37u, 0x10u}, + {0x3Fu, 0x10u}, + {0x40u, 0x34u}, + {0x41u, 0x06u}, + {0x42u, 0x10u}, + {0x44u, 0x05u}, + {0x45u, 0xBEu}, + {0x46u, 0xFCu}, + {0x47u, 0x0Du}, + {0x48u, 0x1Fu}, + {0x49u, 0xFFu}, + {0x4Au, 0xFFu}, + {0x4Bu, 0xFFu}, + {0x4Cu, 0x22u}, + {0x4Eu, 0xF0u}, + {0x4Fu, 0x08u}, + {0x50u, 0x04u}, + {0x59u, 0x04u}, + {0x5Au, 0x04u}, + {0x5Cu, 0x10u}, + {0x5Du, 0x01u}, + {0x5Fu, 0x01u}, + {0x62u, 0xC0u}, + {0x64u, 0x40u}, + {0x65u, 0x01u}, + {0x66u, 0x10u}, + {0x67u, 0x11u}, + {0x68u, 0xC0u}, + {0x69u, 0x01u}, + {0x6Bu, 0x11u}, + {0x6Cu, 0x40u}, + {0x6Du, 0x01u}, + {0x6Eu, 0x40u}, + {0x6Fu, 0x01u}, + {0x80u, 0xC0u}, + {0x84u, 0x24u}, + {0x85u, 0x40u}, + {0x86u, 0x10u}, + {0x87u, 0x30u}, + {0x88u, 0x11u}, + {0x89u, 0x32u}, + {0x8Au, 0x62u}, + {0x8Bu, 0x44u}, + {0x8Cu, 0x1Cu}, + {0x8Du, 0x0Du}, + {0x8Fu, 0x80u}, + {0x90u, 0x70u}, + {0x91u, 0x8Du}, + {0x92u, 0x0Fu}, + {0x94u, 0x21u}, + {0x95u, 0x8Du}, + {0x96u, 0x9Eu}, + {0x98u, 0x14u}, + {0x99u, 0x02u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x0Du}, + {0x9Cu, 0x1Cu}, + {0xA0u, 0x08u}, + {0xA1u, 0x8Du}, + {0xA5u, 0x11u}, + {0xA7u, 0x62u}, + {0xA8u, 0x10u}, + {0xA9u, 0x8Du}, + {0xAAu, 0x0Cu}, + {0xACu, 0x0Cu}, + {0xADu, 0x52u}, + {0xAEu, 0x10u}, + {0xAFu, 0x28u}, + {0xB0u, 0xC1u}, + {0xB2u, 0x30u}, + {0xB3u, 0x70u}, + {0xB4u, 0x0Fu}, + {0xB5u, 0x0Fu}, + {0xB7u, 0x80u}, + {0xB8u, 0x02u}, + {0xBAu, 0x08u}, + {0xBBu, 0x28u}, + {0xBFu, 0x40u}, + {0xD6u, 0x02u}, + {0xD7u, 0x28u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, {0xDCu, 0x11u}, + {0xDDu, 0x10u}, {0xDFu, 0x01u}, - {0x00u, 0x08u}, - {0x01u, 0x02u}, - {0x04u, 0x20u}, - {0x06u, 0x22u}, - {0x0Au, 0x2Au}, - {0x0Eu, 0x25u}, - {0x11u, 0x0Cu}, - {0x12u, 0x10u}, - {0x14u, 0x42u}, - {0x16u, 0x04u}, - {0x18u, 0x04u}, - {0x19u, 0x02u}, - {0x1Au, 0x2Au}, - {0x1Eu, 0x20u}, - {0x1Fu, 0x01u}, - {0x21u, 0x40u}, - {0x22u, 0xA0u}, + {0x05u, 0x15u}, + {0x06u, 0x02u}, + {0x0Eu, 0x5Au}, + {0x15u, 0x50u}, + {0x16u, 0x40u}, + {0x1Du, 0x15u}, + {0x1Fu, 0x20u}, + {0x21u, 0x88u}, + {0x23u, 0x08u}, {0x24u, 0x01u}, - {0x25u, 0x04u}, - {0x27u, 0x04u}, - {0x28u, 0x88u}, - {0x2Du, 0x04u}, - {0x2Eu, 0x20u}, - {0x30u, 0x01u}, - {0x31u, 0x08u}, - {0x33u, 0x10u}, - {0x34u, 0x02u}, - {0x36u, 0x0Au}, - {0x39u, 0x88u}, - {0x3Cu, 0x01u}, - {0x3Du, 0x10u}, - {0x3Eu, 0x08u}, - {0x3Fu, 0x41u}, - {0x59u, 0x40u}, - {0x5Du, 0x80u}, - {0x5Fu, 0x2Au}, - {0x67u, 0x02u}, - {0x6Du, 0x10u}, - {0x6Eu, 0x44u}, - {0x81u, 0x20u}, - {0x82u, 0x20u}, - {0x83u, 0x62u}, - {0x85u, 0x40u}, - {0x86u, 0x19u}, - {0x87u, 0x08u}, - {0x8Bu, 0x40u}, - {0xC0u, 0xECu}, - {0xC2u, 0xE7u}, - {0xC4u, 0xD0u}, - {0xCAu, 0x65u}, - {0xCCu, 0xC7u}, - {0xCEu, 0xFAu}, - {0xD6u, 0xF8u}, - {0xD8u, 0x10u}, - {0xE0u, 0x20u}, - {0xE6u, 0x20u}, - {0x80u, 0x02u}, - {0x82u, 0x64u}, - {0x84u, 0x11u}, - {0x88u, 0xC4u}, - {0x8Au, 0x02u}, - {0x8Eu, 0x11u}, - {0x92u, 0x20u}, - {0x96u, 0x01u}, - {0x98u, 0x0Cu}, - {0x9Cu, 0x11u}, - {0xA0u, 0x11u}, - {0xA4u, 0x11u}, - {0xA8u, 0x02u}, - {0xAAu, 0xA8u}, - {0xB0u, 0xE0u}, - {0xB2u, 0x01u}, - {0xB4u, 0x0Eu}, - {0xB6u, 0x10u}, - {0xB8u, 0x20u}, - {0xBEu, 0x44u}, - {0xD8u, 0x04u}, - {0xDFu, 0x01u}, - {0x01u, 0x20u}, - {0x03u, 0x52u}, - {0x04u, 0x10u}, - {0x07u, 0x92u}, - {0x09u, 0x80u}, - {0x0Au, 0x80u}, - {0x0Bu, 0x14u}, - {0x0Cu, 0x90u}, - {0x0Du, 0x08u}, - {0x0Eu, 0x48u}, - {0x10u, 0x08u}, - {0x12u, 0x40u}, - {0x13u, 0x40u}, - {0x15u, 0x02u}, - {0x17u, 0x28u}, - {0x18u, 0x80u}, - {0x19u, 0x20u}, - {0x1Bu, 0x03u}, - {0x1Du, 0x04u}, - {0x1Eu, 0x49u}, - {0x20u, 0x90u}, - {0x22u, 0x16u}, - {0x23u, 0xD4u}, - {0x2Bu, 0x81u}, - {0x32u, 0x16u}, - {0x33u, 0x40u}, - {0x39u, 0x54u}, - {0x3Au, 0x02u}, - {0x42u, 0x01u}, - {0x43u, 0x22u}, - {0x49u, 0x09u}, - {0x4Au, 0x80u}, - {0x4Bu, 0x50u}, - {0x51u, 0x08u}, + {0x26u, 0x20u}, + {0x27u, 0x10u}, + {0x29u, 0x02u}, + {0x2Du, 0x10u}, + {0x2Eu, 0x42u}, + {0x2Fu, 0x20u}, + {0x31u, 0x99u}, + {0x36u, 0x25u}, + {0x38u, 0x10u}, + {0x39u, 0x02u}, + {0x3Du, 0x40u}, + {0x3Eu, 0x18u}, + {0x40u, 0x13u}, + {0x41u, 0x01u}, + {0x42u, 0x50u}, + {0x46u, 0x08u}, + {0x47u, 0x10u}, + {0x48u, 0x01u}, + {0x49u, 0x12u}, + {0x4Bu, 0x04u}, + {0x51u, 0x04u}, {0x52u, 0x50u}, - {0x53u, 0x80u}, - {0x63u, 0x08u}, - {0x68u, 0x08u}, - {0x69u, 0x56u}, - {0x6Au, 0x82u}, - {0x6Bu, 0x5Au}, - {0x70u, 0x80u}, - {0x71u, 0x80u}, - {0x72u, 0x02u}, - {0x80u, 0x40u}, - {0x83u, 0x20u}, - {0x84u, 0x60u}, - {0x87u, 0x80u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x40u}, - {0x8Fu, 0x20u}, - {0x95u, 0x40u}, - {0x96u, 0x83u}, - {0x97u, 0x54u}, - {0x9Cu, 0x30u}, - {0x9Du, 0x0Du}, - {0x9Eu, 0x12u}, - {0x9Fu, 0x10u}, - {0xA3u, 0x04u}, - {0xA4u, 0x88u}, - {0xA5u, 0x08u}, - {0xA6u, 0x80u}, - {0xA7u, 0x03u}, - {0xAFu, 0xC0u}, - {0xB0u, 0x01u}, - {0xB1u, 0x08u}, - {0xB7u, 0x04u}, - {0xC0u, 0xFFu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x7Bu}, - {0xCAu, 0x09u}, - {0xCCu, 0x0Fu}, - {0xCEu, 0x0Fu}, - {0xD0u, 0x0Du}, + {0x66u, 0x08u}, + {0x6Du, 0x50u}, + {0x6Eu, 0x0Eu}, + {0x76u, 0x02u}, + {0x84u, 0x01u}, + {0x87u, 0x08u}, + {0x89u, 0x40u}, + {0x92u, 0x50u}, + {0x95u, 0x58u}, + {0x96u, 0x04u}, + {0x97u, 0x04u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x16u}, + {0x9Eu, 0x52u}, + {0xA1u, 0x40u}, + {0xA6u, 0x01u}, + {0xA7u, 0x20u}, + {0xABu, 0x20u}, + {0xADu, 0x84u}, + {0xB4u, 0x10u}, + {0xB5u, 0x01u}, + {0xC0u, 0xF0u}, + {0xC2u, 0xF0u}, + {0xC4u, 0xD0u}, + {0xCAu, 0xF1u}, + {0xCCu, 0xEFu}, + {0xCEu, 0x75u}, + {0xD0u, 0x0Bu}, {0xD2u, 0x0Cu}, - {0xD8u, 0x04u}, - {0xE0u, 0x43u}, - {0xE6u, 0x40u}, - {0x02u, 0x12u}, - {0x05u, 0xFFu}, - {0x09u, 0x69u}, - {0x0Au, 0x01u}, - {0x0Bu, 0x96u}, - {0x0Fu, 0xFFu}, - {0x10u, 0x21u}, - {0x12u, 0x02u}, - {0x13u, 0xFFu}, - {0x14u, 0x88u}, - {0x16u, 0x03u}, - {0x17u, 0xFFu}, - {0x19u, 0x0Fu}, - {0x1Au, 0xECu}, - {0x1Bu, 0xF0u}, - {0x1Cu, 0x04u}, - {0x1Du, 0x33u}, - {0x1Eu, 0x43u}, - {0x1Fu, 0xCCu}, - {0x24u, 0xE0u}, - {0x25u, 0xFFu}, - {0x2Du, 0x55u}, - {0x2Fu, 0xAAu}, - {0x32u, 0x10u}, - {0x34u, 0x0Fu}, - {0x35u, 0xFFu}, - {0x36u, 0xE0u}, - {0x3Bu, 0x20u}, - {0x3Eu, 0x40u}, + {0xD8u, 0x40u}, + {0xE6u, 0x20u}, + {0xEEu, 0x40u}, + {0x04u, 0x42u}, + {0x08u, 0x77u}, + {0x0Au, 0x08u}, + {0x0Bu, 0x05u}, + {0x0Cu, 0xC6u}, + {0x10u, 0x01u}, + {0x12u, 0x5Eu}, + {0x14u, 0x39u}, + {0x15u, 0x08u}, + {0x16u, 0x06u}, + {0x18u, 0xC2u}, + {0x1Au, 0x04u}, + {0x1Bu, 0x01u}, + {0x1Cu, 0xC6u}, + {0x20u, 0x04u}, + {0x22u, 0x20u}, + {0x26u, 0x80u}, + {0x27u, 0x03u}, + {0x28u, 0x80u}, + {0x29u, 0x08u}, + {0x2Au, 0x46u}, + {0x2Cu, 0x46u}, + {0x2Du, 0x06u}, + {0x2Eu, 0x80u}, + {0x30u, 0x70u}, + {0x32u, 0x0Fu}, + {0x33u, 0x07u}, + {0x34u, 0x80u}, + {0x37u, 0x08u}, + {0x38u, 0x08u}, + {0x39u, 0x80u}, + {0x3Au, 0x03u}, + {0x3Eu, 0x10u}, {0x54u, 0x40u}, {0x56u, 0x04u}, {0x58u, 0x04u}, {0x59u, 0x04u}, {0x5Bu, 0x04u}, - {0x5Cu, 0x10u}, + {0x5Cu, 0x11u}, + {0x5Du, 0x10u}, {0x5Fu, 0x01u}, - {0x80u, 0x10u}, - {0x81u, 0xC0u}, - {0x83u, 0x01u}, - {0x84u, 0x01u}, - {0x85u, 0x80u}, - {0x88u, 0x04u}, - {0x89u, 0x7Fu}, - {0x8Bu, 0x80u}, - {0x8Cu, 0x88u}, - {0x8Du, 0x1Fu}, - {0x8Eu, 0x21u}, - {0x8Fu, 0x20u}, - {0x90u, 0x87u}, - {0x91u, 0xC0u}, - {0x92u, 0x18u}, - {0x93u, 0x02u}, - {0x94u, 0x40u}, - {0x95u, 0xC0u}, - {0x97u, 0x08u}, - {0x98u, 0x40u}, - {0x99u, 0xC0u}, - {0x9Bu, 0x04u}, - {0x9Cu, 0x01u}, - {0x9Du, 0x90u}, - {0x9Fu, 0x40u}, - {0xA0u, 0x01u}, - {0xA3u, 0x9Fu}, - {0xA4u, 0x01u}, - {0xA8u, 0xA2u}, - {0xAAu, 0x08u}, - {0xABu, 0x60u}, - {0xACu, 0x01u}, - {0xAFu, 0xFFu}, - {0xB0u, 0x08u}, - {0xB2u, 0x3Fu}, - {0xB4u, 0x40u}, - {0xB5u, 0xFFu}, - {0xB6u, 0x80u}, - {0xB8u, 0x28u}, - {0xBEu, 0x45u}, - {0xBFu, 0x10u}, - {0xD4u, 0x09u}, - {0xD6u, 0x04u}, + {0x81u, 0x04u}, + {0x86u, 0xECu}, + {0x89u, 0x86u}, + {0x8Au, 0x01u}, + {0x8Du, 0x02u}, + {0x91u, 0x06u}, + {0x92u, 0x12u}, + {0x93u, 0x80u}, + {0x94u, 0x88u}, + {0x95u, 0x61u}, + {0x96u, 0x03u}, + {0x97u, 0x0Eu}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x21u}, + {0x9Du, 0x07u}, + {0x9Eu, 0x02u}, + {0x9Fu, 0x38u}, + {0xA0u, 0xE0u}, + {0xA1u, 0x86u}, + {0xA5u, 0x82u}, + {0xA7u, 0x04u}, + {0xA8u, 0x04u}, + {0xA9u, 0x09u}, + {0xAAu, 0x43u}, + {0xABu, 0x56u}, + {0xADu, 0x80u}, + {0xAFu, 0x06u}, + {0xB0u, 0xE0u}, + {0xB1u, 0x08u}, + {0xB2u, 0x0Fu}, + {0xB3u, 0x0Fu}, + {0xB4u, 0x10u}, + {0xB5u, 0x70u}, + {0xB7u, 0x80u}, + {0xB9u, 0x08u}, + {0xBEu, 0x01u}, + {0xBFu, 0x41u}, + {0xD8u, 0x04u}, + {0xD9u, 0x04u}, + {0xDFu, 0x01u}, + {0x01u, 0x28u}, + {0x05u, 0x14u}, + {0x06u, 0x02u}, + {0x09u, 0x88u}, + {0x0Bu, 0x80u}, + {0x0Eu, 0x56u}, + {0x10u, 0x04u}, + {0x11u, 0x02u}, + {0x12u, 0x08u}, + {0x15u, 0x58u}, + {0x16u, 0x40u}, + {0x19u, 0x29u}, + {0x1Cu, 0x80u}, + {0x1Eu, 0x50u}, + {0x1Fu, 0x10u}, + {0x20u, 0x11u}, + {0x22u, 0x18u}, + {0x23u, 0x82u}, + {0x26u, 0x80u}, + {0x27u, 0x20u}, + {0x28u, 0xA4u}, + {0x2Au, 0x80u}, + {0x2Eu, 0x40u}, + {0x2Fu, 0x24u}, + {0x30u, 0x02u}, + {0x31u, 0x88u}, + {0x32u, 0x10u}, + {0x37u, 0x28u}, + {0x38u, 0x60u}, + {0x3Bu, 0x02u}, + {0x3Eu, 0x10u}, + {0x64u, 0x40u}, + {0x65u, 0x80u}, + {0x66u, 0x10u}, + {0x67u, 0x20u}, + {0x6Du, 0x80u}, + {0x6Eu, 0x20u}, + {0x84u, 0x40u}, + {0x8Au, 0x10u}, + {0x8Du, 0x01u}, + {0x8Eu, 0x10u}, + {0x90u, 0x60u}, + {0x93u, 0x8Au}, + {0x94u, 0x11u}, + {0x95u, 0x50u}, + {0x96u, 0x54u}, + {0x97u, 0x04u}, + {0x98u, 0xA0u}, + {0x9Au, 0x80u}, + {0x9Bu, 0x08u}, + {0x9Cu, 0x02u}, + {0x9Du, 0x16u}, + {0x9Eu, 0x42u}, + {0x9Fu, 0x82u}, + {0xA0u, 0x02u}, + {0xA1u, 0x88u}, + {0xA4u, 0x40u}, + {0xA6u, 0x89u}, + {0xA7u, 0x20u}, + {0xA8u, 0x80u}, + {0xA9u, 0x08u}, + {0xAAu, 0x04u}, + {0xABu, 0x10u}, + {0xAEu, 0x40u}, + {0xAFu, 0x10u}, + {0xC0u, 0xE6u}, + {0xC2u, 0xFDu}, + {0xC4u, 0xFAu}, + {0xCAu, 0x7Fu}, + {0xCCu, 0x6Fu}, + {0xCEu, 0x2Du}, + {0xD8u, 0xF0u}, + {0xE2u, 0xD0u}, + {0xE8u, 0x01u}, + {0xEAu, 0x10u}, + {0xEEu, 0x08u}, + {0x00u, 0x0Du}, + {0x01u, 0x11u}, + {0x02u, 0x10u}, + {0x03u, 0x22u}, + {0x04u, 0x02u}, + {0x05u, 0x44u}, + {0x06u, 0x0Du}, + {0x07u, 0x88u}, + {0x08u, 0x1Du}, + {0x09u, 0x48u}, + {0x0Bu, 0x84u}, + {0x0Cu, 0x1Du}, + {0x0Du, 0x33u}, + {0x0Fu, 0xCCu}, + {0x10u, 0x42u}, + {0x11u, 0x0Fu}, + {0x12u, 0x28u}, + {0x13u, 0xF0u}, + {0x14u, 0x22u}, + {0x16u, 0x84u}, + {0x18u, 0x1Du}, + {0x1Bu, 0xFFu}, + {0x1Cu, 0xC0u}, + {0x20u, 0x21u}, + {0x22u, 0x42u}, + {0x27u, 0xFFu}, + {0x29u, 0x12u}, + {0x2Au, 0x10u}, + {0x2Bu, 0x21u}, + {0x2Cu, 0x1Du}, + {0x2Fu, 0xFFu}, + {0x32u, 0x10u}, + {0x34u, 0x0Fu}, + {0x35u, 0xFFu}, + {0x36u, 0xE0u}, + {0x38u, 0x80u}, + {0x3Au, 0x20u}, + {0x3Eu, 0x04u}, + {0x3Fu, 0x10u}, + {0x54u, 0x40u}, + {0x58u, 0x04u}, + {0x59u, 0x04u}, + {0x5Bu, 0x04u}, + {0x5Fu, 0x01u}, + {0x80u, 0x0Fu}, + {0x82u, 0xF0u}, + {0x84u, 0x84u}, + {0x85u, 0x20u}, + {0x86u, 0x48u}, + {0x88u, 0x21u}, + {0x89u, 0x10u}, + {0x8Au, 0x12u}, + {0x8Du, 0x80u}, + {0x90u, 0x11u}, + {0x91u, 0x08u}, + {0x92u, 0x22u}, + {0x93u, 0x04u}, + {0x95u, 0x40u}, + {0x96u, 0xFFu}, + {0x99u, 0x01u}, + {0x9Bu, 0x02u}, + {0x9Cu, 0x33u}, + {0x9Du, 0x04u}, + {0x9Eu, 0xCCu}, + {0x9Fu, 0x08u}, + {0xA1u, 0x53u}, + {0xA3u, 0xACu}, + {0xA4u, 0x44u}, + {0xA6u, 0x88u}, + {0xA9u, 0x02u}, + {0xAAu, 0xFFu}, + {0xABu, 0x01u}, + {0xACu, 0xFFu}, + {0xB0u, 0xFFu}, + {0xB1u, 0xC0u}, + {0xB3u, 0x0Fu}, + {0xB7u, 0x30u}, + {0xBEu, 0x01u}, + {0xBFu, 0x45u}, + {0xD6u, 0x08u}, {0xD8u, 0x04u}, {0xD9u, 0x04u}, {0xDBu, 0x04u}, + {0xDDu, 0x90u}, {0xDFu, 0x01u}, - {0x01u, 0x20u}, - {0x02u, 0x80u}, - {0x03u, 0x12u}, - {0x04u, 0x10u}, - {0x05u, 0x01u}, - {0x09u, 0x20u}, - {0x0Au, 0x22u}, - {0x0Bu, 0x40u}, - {0x0Eu, 0x08u}, - {0x0Fu, 0x52u}, - {0x10u, 0x80u}, - {0x11u, 0x40u}, - {0x13u, 0x14u}, - {0x14u, 0x10u}, - {0x19u, 0x70u}, - {0x1Au, 0x60u}, - {0x1Cu, 0x10u}, - {0x1Eu, 0x08u}, - {0x1Fu, 0x80u}, - {0x21u, 0x20u}, - {0x26u, 0x20u}, - {0x27u, 0x04u}, - {0x29u, 0x11u}, - {0x2Bu, 0x02u}, - {0x2Fu, 0x21u}, - {0x30u, 0x08u}, - {0x32u, 0x41u}, - {0x33u, 0x10u}, - {0x35u, 0x80u}, - {0x36u, 0x20u}, - {0x37u, 0x0Au}, - {0x3Au, 0x02u}, - {0x3Bu, 0x54u}, - {0x3Du, 0x80u}, - {0x3Eu, 0x04u}, - {0x3Fu, 0x20u}, - {0x58u, 0x20u}, - {0x59u, 0x08u}, - {0x5Au, 0x41u}, - {0x61u, 0x40u}, - {0x62u, 0x02u}, - {0x64u, 0x01u}, - {0x65u, 0x04u}, - {0x66u, 0x10u}, - {0x67u, 0x80u}, - {0x92u, 0x04u}, - {0x93u, 0x02u}, - {0x99u, 0x80u}, - {0x9Bu, 0x0Au}, - {0xA1u, 0x40u}, - {0xA3u, 0x34u}, - {0xA6u, 0x02u}, - {0xA8u, 0x40u}, - {0xAAu, 0x10u}, - {0xAFu, 0x10u}, - {0xB1u, 0x0Cu}, - {0xB3u, 0x12u}, - {0xB4u, 0x04u}, - {0xC0u, 0x5Fu}, - {0xC2u, 0xFFu}, - {0xC4u, 0x2Fu}, - {0xCAu, 0x5Du}, - {0xCCu, 0xFFu}, - {0xCEu, 0x7Fu}, - {0xD6u, 0x0Fu}, - {0xD8u, 0xF9u}, - {0xEAu, 0x11u}, - {0xEEu, 0x1Cu}, - {0x9Cu, 0x81u}, - {0x9Eu, 0x04u}, - {0xA5u, 0x08u}, - {0xABu, 0x20u}, - {0xB0u, 0x50u}, - {0xB1u, 0x20u}, - {0xE8u, 0xA0u}, - {0xEEu, 0x9Cu}, - {0x81u, 0x08u}, - {0x84u, 0x01u}, - {0x8Cu, 0x80u}, - {0x9Cu, 0x81u}, - {0xA5u, 0x08u}, - {0xB6u, 0x04u}, - {0xE0u, 0x10u}, - {0xECu, 0x10u}, - {0x04u, 0x10u}, - {0x0Cu, 0x20u}, - {0x0Du, 0x08u}, - {0x11u, 0x08u}, - {0x12u, 0x08u}, + {0x00u, 0x08u}, + {0x01u, 0x02u}, + {0x03u, 0x08u}, + {0x04u, 0x06u}, + {0x06u, 0x01u}, + {0x07u, 0x04u}, + {0x09u, 0x41u}, + {0x0Bu, 0x20u}, + {0x0Du, 0x02u}, + {0x0Eu, 0x06u}, + {0x0Fu, 0x20u}, + {0x10u, 0x02u}, + {0x11u, 0x04u}, + {0x13u, 0x20u}, + {0x14u, 0x80u}, + {0x15u, 0x20u}, + {0x17u, 0x40u}, + {0x18u, 0x40u}, + {0x1Cu, 0x04u}, + {0x1Du, 0x04u}, + {0x1Eu, 0x02u}, + {0x20u, 0x02u}, + {0x23u, 0xA0u}, + {0x27u, 0x08u}, + {0x28u, 0x04u}, + {0x2Bu, 0x40u}, + {0x2Cu, 0x02u}, + {0x2Du, 0x08u}, + {0x2Fu, 0x18u}, + {0x31u, 0x80u}, + {0x32u, 0x15u}, + {0x35u, 0x02u}, + {0x37u, 0x22u}, + {0x38u, 0x28u}, + {0x3Bu, 0x40u}, + {0x3Du, 0x86u}, + {0x3Eu, 0x10u}, + {0x3Fu, 0x80u}, + {0x59u, 0x80u}, + {0x63u, 0x01u}, + {0x65u, 0x24u}, + {0x66u, 0x80u}, + {0x8Bu, 0x80u}, + {0x8Eu, 0x01u}, + {0x90u, 0x2Au}, + {0x91u, 0x24u}, + {0x92u, 0x3Eu}, + {0x93u, 0x40u}, + {0x94u, 0x40u}, + {0x97u, 0x01u}, + {0x98u, 0x84u}, + {0x99u, 0x28u}, + {0x9Au, 0x01u}, + {0x9Bu, 0x46u}, + {0x9Fu, 0x28u}, + {0xA0u, 0x06u}, + {0xA1u, 0xC3u}, + {0xA3u, 0x08u}, + {0xA9u, 0x02u}, + {0xAAu, 0x04u}, + {0xB6u, 0x80u}, + {0xC0u, 0xFEu}, + {0xC2u, 0xFDu}, + {0xC4u, 0xD7u}, + {0xCAu, 0x75u}, + {0xCCu, 0xAFu}, + {0xCEu, 0xFEu}, + {0xD6u, 0x08u}, + {0xD8u, 0x78u}, + {0xE2u, 0x10u}, + {0xEAu, 0x10u}, + {0xEEu, 0x08u}, + {0xB0u, 0x01u}, + {0xB1u, 0x10u}, + {0xB2u, 0x80u}, + {0xB5u, 0x80u}, + {0xB7u, 0x10u}, + {0xE8u, 0x10u}, + {0x04u, 0x40u}, + {0x0Cu, 0x10u}, + {0x0Du, 0x04u}, + {0x12u, 0x01u}, + {0x13u, 0x02u}, {0x16u, 0x80u}, - {0x17u, 0x80u}, - {0x30u, 0x10u}, - {0x33u, 0x02u}, - {0x35u, 0x80u}, - {0x36u, 0x01u}, - {0x39u, 0x08u}, - {0x3Au, 0x80u}, - {0x3Du, 0x21u}, - {0x42u, 0x04u}, - {0x53u, 0x04u}, - {0x5Eu, 0x10u}, - {0x6Du, 0x08u}, - {0x6Fu, 0x02u}, - {0x81u, 0x10u}, - {0x8Cu, 0x10u}, - {0x8Eu, 0x10u}, + {0x17u, 0x40u}, + {0x30u, 0x40u}, + {0x33u, 0x01u}, + {0x34u, 0x20u}, + {0x36u, 0x02u}, + {0x3Au, 0x82u}, + {0x3Cu, 0x02u}, + {0x3Fu, 0x20u}, + {0x42u, 0x08u}, + {0x53u, 0x20u}, + {0x54u, 0x80u}, + {0x6Bu, 0x03u}, + {0x82u, 0x02u}, + {0x88u, 0x10u}, + {0x8Fu, 0x20u}, {0xC0u, 0x80u}, {0xC2u, 0xA0u}, {0xC4u, 0xF0u}, {0xCCu, 0xF0u}, {0xCEu, 0xF0u}, {0xD0u, 0x10u}, - {0xD4u, 0x20u}, - {0xD6u, 0x20u}, - {0xE2u, 0x80u}, - {0x03u, 0x08u}, - {0x0Au, 0x01u}, - {0x30u, 0x04u}, - {0x33u, 0x10u}, - {0x37u, 0x84u}, + {0xD4u, 0x60u}, + {0xE6u, 0x20u}, + {0x01u, 0x20u}, + {0x0Bu, 0x02u}, + {0x30u, 0x10u}, + {0x32u, 0x08u}, + {0x36u, 0x01u}, + {0x37u, 0x40u}, {0x39u, 0x80u}, - {0x52u, 0x02u}, - {0x63u, 0x08u}, - {0x8Bu, 0x04u}, - {0x95u, 0x01u}, - {0x96u, 0x04u}, - {0x97u, 0x08u}, - {0x9Bu, 0x90u}, - {0x9Cu, 0x10u}, - {0x9Du, 0x80u}, - {0xA0u, 0x20u}, - {0xA2u, 0x02u}, - {0xA6u, 0x01u}, - {0xAAu, 0x0Au}, - {0xABu, 0x10u}, - {0xADu, 0x08u}, - {0xB1u, 0x04u}, + {0x56u, 0x04u}, + {0x62u, 0x02u}, + {0x64u, 0x10u}, + {0x66u, 0x01u}, + {0x80u, 0x80u}, + {0x86u, 0x02u}, + {0x89u, 0x24u}, + {0x90u, 0x40u}, + {0x91u, 0x08u}, + {0x9Au, 0x05u}, + {0x9Bu, 0x40u}, + {0x9Cu, 0x60u}, + {0x9Eu, 0x08u}, + {0xA4u, 0x81u}, + {0xAEu, 0x02u}, + {0xB6u, 0x04u}, + {0xB7u, 0x10u}, {0xC0u, 0x40u}, {0xC2u, 0x40u}, {0xCCu, 0xF0u}, {0xCEu, 0x10u}, - {0xD4u, 0x80u}, + {0xD4u, 0x40u}, {0xD8u, 0x40u}, - {0xE8u, 0x40u}, - {0xEAu, 0x80u}, - {0x10u, 0x10u}, + {0xE2u, 0x60u}, + {0xEAu, 0x40u}, + {0x10u, 0x40u}, {0x33u, 0x80u}, - {0x8Cu, 0x20u}, - {0x8Fu, 0x08u}, - {0x92u, 0x01u}, - {0x95u, 0x81u}, - {0x96u, 0x04u}, - {0x9Cu, 0x14u}, - {0x9Du, 0x80u}, - {0x9Fu, 0x04u}, - {0xA0u, 0x20u}, - {0xA3u, 0x08u}, - {0xA6u, 0x01u}, - {0xABu, 0x04u}, + {0x5Bu, 0x02u}, + {0x8Au, 0x08u}, + {0x8Fu, 0x01u}, + {0x93u, 0x02u}, + {0x95u, 0x80u}, + {0x9Cu, 0x60u}, + {0x9Eu, 0x08u}, + {0xA4u, 0x01u}, + {0xA6u, 0x09u}, + {0xB4u, 0x40u}, {0xC4u, 0x10u}, {0xCCu, 0x10u}, - {0xEEu, 0x20u}, - {0x6Bu, 0x40u}, - {0x83u, 0x44u}, - {0x84u, 0x04u}, - {0x89u, 0x80u}, - {0x8Au, 0x04u}, - {0x92u, 0x01u}, - {0x95u, 0x81u}, - {0x96u, 0x04u}, - {0x9Cu, 0x04u}, - {0x9Du, 0x80u}, - {0x9Fu, 0x04u}, + {0xD6u, 0x40u}, + {0x8Au, 0x08u}, + {0x8Eu, 0x04u}, + {0x9Cu, 0x20u}, + {0x9Eu, 0x08u}, + {0xA4u, 0x01u}, {0xA6u, 0x01u}, {0xA7u, 0x80u}, - {0xDCu, 0x20u}, - {0xE2u, 0x90u}, - {0xE6u, 0x80u}, - {0x04u, 0x10u}, - {0x05u, 0x02u}, - {0x09u, 0x02u}, - {0x0Au, 0x01u}, - {0x10u, 0x40u}, - {0x5Au, 0x20u}, - {0x5Bu, 0x01u}, - {0x5Eu, 0x02u}, - {0x78u, 0x80u}, - {0x89u, 0x02u}, + {0xA9u, 0x40u}, + {0xB3u, 0x02u}, + {0xEAu, 0x80u}, + {0x06u, 0x08u}, + {0x07u, 0x10u}, + {0x08u, 0x02u}, + {0x0Au, 0x02u}, + {0x13u, 0x02u}, + {0x56u, 0x20u}, + {0x5Cu, 0x04u}, + {0x60u, 0x20u}, + {0x80u, 0x02u}, + {0x8Bu, 0x02u}, {0xC0u, 0x05u}, {0xC2u, 0x0Au}, {0xC4u, 0x08u}, - {0xD4u, 0x01u}, - {0xD6u, 0x03u}, - {0xDCu, 0x01u}, - {0xE6u, 0x04u}, - {0x01u, 0x44u}, - {0x08u, 0x08u}, - {0x09u, 0x40u}, - {0x57u, 0x08u}, - {0x5Fu, 0x20u}, - {0x65u, 0x80u}, - {0x66u, 0x08u}, - {0x82u, 0x08u}, - {0x83u, 0x20u}, - {0x89u, 0x08u}, - {0x8Eu, 0x01u}, - {0x90u, 0x10u}, - {0x96u, 0x20u}, - {0x99u, 0x02u}, - {0x9Fu, 0x01u}, - {0xA6u, 0x01u}, - {0xA8u, 0x80u}, - {0xAEu, 0x01u}, - {0xB0u, 0x40u}, + {0xD4u, 0x02u}, + {0xD6u, 0x01u}, + {0xD8u, 0x02u}, + {0xE2u, 0x04u}, + {0x00u, 0x08u}, + {0x02u, 0x02u}, + {0x08u, 0x80u}, + {0x09u, 0x04u}, + {0x56u, 0x02u}, + {0x58u, 0x40u}, + {0x5Cu, 0x01u}, + {0x64u, 0x08u}, + {0x80u, 0xA0u}, + {0x81u, 0x04u}, + {0x8Au, 0x02u}, + {0x92u, 0x02u}, + {0x94u, 0x04u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x20u}, + {0x9Eu, 0x20u}, {0xC0u, 0x0Au}, {0xC2u, 0x0Au}, - {0xD4u, 0x02u}, + {0xD4u, 0x01u}, {0xD6u, 0x05u}, {0xD8u, 0x01u}, - {0xE0u, 0x08u}, - {0xE4u, 0x04u}, - {0xEAu, 0x01u}, + {0xE6u, 0x04u}, + {0x8Bu, 0x40u}, + {0x8Eu, 0x20u}, + {0x94u, 0x04u}, + {0x9Au, 0x08u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x40u}, + {0x9Eu, 0x20u}, + {0xA0u, 0x04u}, + {0xA8u, 0x01u}, + {0xACu, 0x08u}, + {0xAEu, 0x01u}, + {0xB2u, 0x02u}, + {0xE4u, 0x02u}, + {0xE6u, 0x01u}, + {0xE8u, 0x01u}, + {0x0Bu, 0x81u}, + {0x0Fu, 0x22u}, + {0x8Cu, 0x04u}, + {0x94u, 0x04u}, + {0x97u, 0x81u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x40u}, + {0xAAu, 0x08u}, + {0xABu, 0x01u}, + {0xACu, 0x04u}, + {0xC2u, 0x0Fu}, + {0xE4u, 0x02u}, + {0x02u, 0x04u}, + {0x84u, 0x01u}, + {0x89u, 0x02u}, + {0x8Cu, 0x08u}, + {0x8Eu, 0x01u}, + {0x9Eu, 0x04u}, + {0xA4u, 0x01u}, + {0xA8u, 0x20u}, + {0xAFu, 0x80u}, + {0xB6u, 0x01u}, + {0xC0u, 0x40u}, + {0xE6u, 0x10u}, + {0xEEu, 0x30u}, + {0x03u, 0x20u}, + {0x51u, 0x20u}, {0x55u, 0x08u}, - {0x80u, 0x10u}, - {0x85u, 0x40u}, - {0x8Bu, 0x01u}, - {0x8Eu, 0x10u}, - {0x90u, 0x10u}, - {0x96u, 0x20u}, + {0x58u, 0x08u}, + {0x5Fu, 0x08u}, + {0x61u, 0x02u}, + {0x65u, 0x02u}, + {0x7Au, 0x01u}, + {0x85u, 0x20u}, + {0x87u, 0x20u}, + {0x89u, 0x02u}, {0x98u, 0x08u}, {0x99u, 0x02u}, - {0x9Fu, 0x01u}, - {0xA1u, 0x48u}, - {0xABu, 0x08u}, - {0xADu, 0x04u}, - {0xB5u, 0xC0u}, - {0xD4u, 0x02u}, - {0xE0u, 0x02u}, - {0xE4u, 0x04u}, - {0xEAu, 0x02u}, - {0xECu, 0x02u}, - {0x09u, 0x10u}, - {0x0Bu, 0x80u}, - {0x0Du, 0x02u}, - {0x0Fu, 0x02u}, - {0x81u, 0x02u}, - {0x87u, 0x40u}, - {0x98u, 0x08u}, - {0xB5u, 0x02u}, - {0xC2u, 0x0Fu}, - {0xEAu, 0x02u}, - {0x95u, 0x01u}, - {0xAEu, 0x01u}, - {0xAFu, 0x80u}, - {0xB5u, 0x40u}, - {0xB6u, 0x01u}, - {0xE8u, 0x10u}, - {0xEEu, 0x10u}, - {0x03u, 0x80u}, - {0x52u, 0x80u}, - {0x56u, 0x20u}, - {0x8Eu, 0x20u}, - {0x8Fu, 0x80u}, - {0xA2u, 0x80u}, - {0xADu, 0x01u}, - {0xAEu, 0x80u}, + {0x9Bu, 0x08u}, + {0xA1u, 0x08u}, + {0xA2u, 0x01u}, + {0xA9u, 0x08u}, + {0xB7u, 0x08u}, {0xC0u, 0x10u}, {0xD4u, 0x60u}, - {0xEAu, 0x10u}, - {0xEEu, 0x10u}, - {0xA8u, 0x08u}, + {0xD6u, 0xC0u}, + {0xD8u, 0xC0u}, + {0xDCu, 0x80u}, + {0xE2u, 0x10u}, + {0xE4u, 0x10u}, + {0xEAu, 0x80u}, + {0x74u, 0x08u}, + {0x88u, 0x08u}, + {0x90u, 0x02u}, + {0x9Bu, 0x10u}, + {0x9Cu, 0x40u}, {0xAFu, 0x01u}, - {0xB5u, 0x10u}, - {0xEEu, 0x08u}, + {0xB4u, 0x01u}, + {0xB7u, 0x10u}, + {0xDEu, 0x04u}, + {0xE4u, 0x04u}, + {0xE8u, 0x02u}, + {0xEAu, 0x08u}, + {0x70u, 0x01u}, + {0x90u, 0x02u}, + {0xB0u, 0x40u}, + {0xB7u, 0x10u}, + {0xDCu, 0x01u}, + {0xE8u, 0x01u}, + {0xEEu, 0x02u}, {0x10u, 0x03u}, + {0x11u, 0x01u}, {0x1Au, 0x03u}, + {0x1Cu, 0x01u}, + {0x1Du, 0x01u}, {0x00u, 0xFFu}, {0x01u, 0xBFu}, {0x02u, 0x2Au}, @@ -2060,31 +2416,32 @@ void cyfitter_cfg(void) /* address, size */ {(void CYFAR *)(CYREG_TMR0_CFG0), 12u}, {(void CYFAR *)(CYREG_PRT5_DR), 16u}, - {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u}, - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U1_BASE), 1920u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1024u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U1_BASE), 2944u}, + {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u}, {(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u}, {(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u}, {(void CYFAR *)(CYREG_BCTL1_MDCLK_EN), 16u}, }; - /* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */ - static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = { - 0xD6u, 0x6Cu, 0x00u, 0x00u, 0xD2u, 0x64u, 0x04u, 0x08u, 0x20u, 0x40u, 0xD0u, 0x2Cu, 0x29u, 0x2Cu, 0x46u, 0x40u, - 0xD6u, 0x71u, 0x00u, 0x82u, 0x21u, 0xC0u, 0x8Eu, 0x2Fu, 0x02u, 0xA4u, 0x00u, 0x40u, 0xD6u, 0x6Cu, 0x00u, 0x00u, - 0x04u, 0x08u, 0x00u, 0x10u, 0x00u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x00u, 0x06u, 0x00u, 0x17u, 0x91u, 0x28u, 0x4Eu, - 0x0Fu, 0x0Fu, 0x00u, 0x31u, 0xF0u, 0xC0u, 0x00u, 0x00u, 0x02u, 0x00u, 0x20u, 0x2Cu, 0x00u, 0x00u, 0x00u, 0x00u, - 0x46u, 0x05u, 0x10u, 0x00u, 0x02u, 0xBEu, 0xFCu, 0x0Du, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, - 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u, + /* UDB_1_3_0_CONFIG Address: CYDEV_UCFG_B0_P2_U0_BASE Size (bytes): 128 */ + static const uint8 CYCODE BS_UDB_1_3_0_CONFIG_VAL[] = { + 0x00u, 0x01u, 0x00u, 0x00u, 0x00u, 0x40u, 0x60u, 0x00u, 0x00u, 0x88u, 0xFFu, 0x21u, 0x90u, 0x01u, 0x40u, 0x00u, + 0x00u, 0x01u, 0x9Fu, 0x00u, 0x7Fu, 0xA2u, 0x80u, 0x08u, 0xC0u, 0x04u, 0x04u, 0x00u, 0x1Fu, 0x87u, 0x20u, 0x18u, + 0xC0u, 0x40u, 0x02u, 0x00u, 0xC0u, 0x01u, 0x01u, 0x00u, 0xC0u, 0x01u, 0x08u, 0x00u, 0x80u, 0x10u, 0x00u, 0x00u, + 0xFFu, 0x00u, 0x00u, 0x3Fu, 0x00u, 0x40u, 0x00u, 0x80u, 0x80u, 0x28u, 0x00u, 0x00u, 0x00u, 0x00u, 0x41u, 0x44u, + 0x63u, 0x04u, 0x10u, 0x00u, 0x05u, 0xCEu, 0xDBu, 0x0Fu, 0x1Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u, + 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u, 0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u}; /* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */ static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = { - 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u, 0x03u, 0x00u}; + 0x07u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x01u, 0x07u, 0x01u, 0x05u, 0x01u, 0x05u, 0x01u}; static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = { /* dest, src, size */ - {(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), BS_UDB_1_0_0_CONFIG_VAL, 128u}, + {(void CYFAR *)(CYDEV_UCFG_B0_P2_U0_BASE), BS_UDB_1_3_0_CONFIG_VAL, 128u}, {(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), BS_UCFG_BCTL0_VAL, 16u}, }; diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc index d6a1b5c..043d4f7 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc @@ -355,33 +355,101 @@ .set USBFS_USB__USBIO_CR0, CYREG_USB_USBIO_CR0 .set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1 +/* NOR_SI */ +.set NOR_SI__0__INTTYPE, CYREG_PICU3_INTTYPE6 +.set NOR_SI__0__MASK, 0x40 +.set NOR_SI__0__PC, CYREG_PRT3_PC6 +.set NOR_SI__0__PORT, 3 +.set NOR_SI__0__SHIFT, 6 +.set NOR_SI__AG, CYREG_PRT3_AG +.set NOR_SI__AMUX, CYREG_PRT3_AMUX +.set NOR_SI__BIE, CYREG_PRT3_BIE +.set NOR_SI__BIT_MASK, CYREG_PRT3_BIT_MASK +.set NOR_SI__BYP, CYREG_PRT3_BYP +.set NOR_SI__CTL, CYREG_PRT3_CTL +.set NOR_SI__DM0, CYREG_PRT3_DM0 +.set NOR_SI__DM1, CYREG_PRT3_DM1 +.set NOR_SI__DM2, CYREG_PRT3_DM2 +.set NOR_SI__DR, CYREG_PRT3_DR +.set NOR_SI__INP_DIS, CYREG_PRT3_INP_DIS +.set NOR_SI__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set NOR_SI__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set NOR_SI__LCD_EN, CYREG_PRT3_LCD_EN +.set NOR_SI__MASK, 0x40 +.set NOR_SI__PORT, 3 +.set NOR_SI__PRT, CYREG_PRT3_PRT +.set NOR_SI__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set NOR_SI__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set NOR_SI__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set NOR_SI__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set NOR_SI__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set NOR_SI__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set NOR_SI__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set NOR_SI__PS, CYREG_PRT3_PS +.set NOR_SI__SHIFT, 6 +.set NOR_SI__SLW, CYREG_PRT3_SLW + +/* NOR_SO */ +.set NOR_SO__0__INTTYPE, CYREG_PICU15_INTTYPE2 +.set NOR_SO__0__MASK, 0x04 +.set NOR_SO__0__PC, CYREG_IO_PC_PRT15_PC2 +.set NOR_SO__0__PORT, 15 +.set NOR_SO__0__SHIFT, 2 +.set NOR_SO__AG, CYREG_PRT15_AG +.set NOR_SO__AMUX, CYREG_PRT15_AMUX +.set NOR_SO__BIE, CYREG_PRT15_BIE +.set NOR_SO__BIT_MASK, CYREG_PRT15_BIT_MASK +.set NOR_SO__BYP, CYREG_PRT15_BYP +.set NOR_SO__CTL, CYREG_PRT15_CTL +.set NOR_SO__DM0, CYREG_PRT15_DM0 +.set NOR_SO__DM1, CYREG_PRT15_DM1 +.set NOR_SO__DM2, CYREG_PRT15_DM2 +.set NOR_SO__DR, CYREG_PRT15_DR +.set NOR_SO__INP_DIS, CYREG_PRT15_INP_DIS +.set NOR_SO__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU15_BASE +.set NOR_SO__LCD_COM_SEG, CYREG_PRT15_LCD_COM_SEG +.set NOR_SO__LCD_EN, CYREG_PRT15_LCD_EN +.set NOR_SO__MASK, 0x04 +.set NOR_SO__PORT, 15 +.set NOR_SO__PRT, CYREG_PRT15_PRT +.set NOR_SO__PRTDSI__CAPS_SEL, CYREG_PRT15_CAPS_SEL +.set NOR_SO__PRTDSI__DBL_SYNC_IN, CYREG_PRT15_DBL_SYNC_IN +.set NOR_SO__PRTDSI__OE_SEL0, CYREG_PRT15_OE_SEL0 +.set NOR_SO__PRTDSI__OE_SEL1, CYREG_PRT15_OE_SEL1 +.set NOR_SO__PRTDSI__OUT_SEL0, CYREG_PRT15_OUT_SEL0 +.set NOR_SO__PRTDSI__OUT_SEL1, CYREG_PRT15_OUT_SEL1 +.set NOR_SO__PRTDSI__SYNC_OUT, CYREG_PRT15_SYNC_OUT +.set NOR_SO__PS, CYREG_PRT15_PS +.set NOR_SO__SHIFT, 2 +.set NOR_SO__SLW, CYREG_PRT15_SLW + /* SDCard */ -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL -.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK -.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL -.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL -.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST -.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK -.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL -.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL +.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK +.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB05_CTL +.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL +.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB05_06_ST +.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB05_MSK +.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB05_ACTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB05_ST_CTL +.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB05_ST .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL .set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST .set SDCard_BSPIM_RxStsReg__4__MASK, 0x10 @@ -392,7 +460,11 @@ .set SDCard_BSPIM_RxStsReg__6__POS, 6 .set SDCard_BSPIM_RxStsReg__MASK, 0x70 .set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK +.set SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL .set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set SDCard_BSPIM_RxStsReg__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL +.set SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL .set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0 .set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1 @@ -411,14 +483,12 @@ .set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1 .set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0 .set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1 -.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL -.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL .set SDCard_BSPIM_TxStsReg__0__MASK, 0x01 .set SDCard_BSPIM_TxStsReg__0__POS, 0 .set SDCard_BSPIM_TxStsReg__1__MASK, 0x02 .set SDCard_BSPIM_TxStsReg__1__POS, 1 -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL -.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL +.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST .set SDCard_BSPIM_TxStsReg__2__MASK, 0x04 .set SDCard_BSPIM_TxStsReg__2__POS, 2 .set SDCard_BSPIM_TxStsReg__3__MASK, 0x08 @@ -426,9 +496,9 @@ .set SDCard_BSPIM_TxStsReg__4__MASK, 0x10 .set SDCard_BSPIM_TxStsReg__4__POS, 4 .set SDCard_BSPIM_TxStsReg__MASK, 0x1F -.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK -.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL -.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST +.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB06_MSK +.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL +.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB06_ST /* SD_SCK */ .set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE1 @@ -464,6 +534,137 @@ .set SD_SCK__SHIFT, 1 .set SD_SCK__SLW, CYREG_PRT3_SLW +/* NOR_CTL */ +.set NOR_CTL_Sync_ctrl_reg__0__MASK, 0x01 +.set NOR_CTL_Sync_ctrl_reg__0__POS, 0 +.set NOR_CTL_Sync_ctrl_reg__1__MASK, 0x02 +.set NOR_CTL_Sync_ctrl_reg__1__POS, 1 +.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL +.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL +.set NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL +.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK +.set NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK +.set NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK +.set NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL +.set NOR_CTL_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB06_CTL +.set NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL +.set NOR_CTL_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB06_CTL +.set NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL +.set NOR_CTL_Sync_ctrl_reg__MASK, 0x03 +.set NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL +.set NOR_CTL_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB06_MSK + +/* NOR_SCK */ +.set NOR_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE7 +.set NOR_SCK__0__MASK, 0x80 +.set NOR_SCK__0__PC, CYREG_PRT3_PC7 +.set NOR_SCK__0__PORT, 3 +.set NOR_SCK__0__SHIFT, 7 +.set NOR_SCK__AG, CYREG_PRT3_AG +.set NOR_SCK__AMUX, CYREG_PRT3_AMUX +.set NOR_SCK__BIE, CYREG_PRT3_BIE +.set NOR_SCK__BIT_MASK, CYREG_PRT3_BIT_MASK +.set NOR_SCK__BYP, CYREG_PRT3_BYP +.set NOR_SCK__CTL, CYREG_PRT3_CTL +.set NOR_SCK__DM0, CYREG_PRT3_DM0 +.set NOR_SCK__DM1, CYREG_PRT3_DM1 +.set NOR_SCK__DM2, CYREG_PRT3_DM2 +.set NOR_SCK__DR, CYREG_PRT3_DR +.set NOR_SCK__INP_DIS, CYREG_PRT3_INP_DIS +.set NOR_SCK__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set NOR_SCK__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set NOR_SCK__LCD_EN, CYREG_PRT3_LCD_EN +.set NOR_SCK__MASK, 0x80 +.set NOR_SCK__PORT, 3 +.set NOR_SCK__PRT, CYREG_PRT3_PRT +.set NOR_SCK__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set NOR_SCK__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set NOR_SCK__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set NOR_SCK__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set NOR_SCK__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set NOR_SCK__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set NOR_SCK__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set NOR_SCK__PS, CYREG_PRT3_PS +.set NOR_SCK__SHIFT, 7 +.set NOR_SCK__SLW, CYREG_PRT3_SLW + +/* NOR_SPI */ +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB08_09_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB08_09_CTL +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB08_09_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB08_09_MSK +.set NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB08_09_MSK +.set NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB08_CTL +.set NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB08_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB08_CTL +.set NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB08_ST_CTL +.set NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB08_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB08_MSK +.set NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB08_MSK_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB08_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB08_ST_CTL +.set NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB08_ST +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL +.set NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST +.set NOR_SPI_BSPIM_RxStsReg__4__MASK, 0x10 +.set NOR_SPI_BSPIM_RxStsReg__4__POS, 4 +.set NOR_SPI_BSPIM_RxStsReg__5__MASK, 0x20 +.set NOR_SPI_BSPIM_RxStsReg__5__POS, 5 +.set NOR_SPI_BSPIM_RxStsReg__6__MASK, 0x40 +.set NOR_SPI_BSPIM_RxStsReg__6__POS, 6 +.set NOR_SPI_BSPIM_RxStsReg__MASK, 0x70 +.set NOR_SPI_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK +.set NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL +.set NOR_SPI_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB04_05_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB04_05_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB04_05_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB04_05_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB04_05_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB04_05_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB04_A0_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB04_A0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB04_A1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB04_D0_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB04_D0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB04_D1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB04_ACTL +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB04_F0_F1 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB04_F0 +.set NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB04_F1 +.set NOR_SPI_BSPIM_TxStsReg__0__MASK, 0x01 +.set NOR_SPI_BSPIM_TxStsReg__0__POS, 0 +.set NOR_SPI_BSPIM_TxStsReg__1__MASK, 0x02 +.set NOR_SPI_BSPIM_TxStsReg__1__POS, 1 +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL +.set NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST +.set NOR_SPI_BSPIM_TxStsReg__2__MASK, 0x04 +.set NOR_SPI_BSPIM_TxStsReg__2__POS, 2 +.set NOR_SPI_BSPIM_TxStsReg__3__MASK, 0x08 +.set NOR_SPI_BSPIM_TxStsReg__3__POS, 3 +.set NOR_SPI_BSPIM_TxStsReg__4__MASK, 0x10 +.set NOR_SPI_BSPIM_TxStsReg__4__POS, 4 +.set NOR_SPI_BSPIM_TxStsReg__MASK, 0x1F +.set NOR_SPI_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK +.set NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL +.set NOR_SPI_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST + /* SCSI_In */ .set SCSI_In__0__INTTYPE, CYREG_PICU6_INTTYPE1 .set SCSI_In__0__MASK, 0x02 @@ -1051,16 +1252,84 @@ .set TERM_EN__SHIFT, 3 .set TERM_EN__SLW, CYREG_PRT15_SLW +/* nNOR_CS */ +.set nNOR_CS__0__INTTYPE, CYREG_PICU3_INTTYPE4 +.set nNOR_CS__0__MASK, 0x10 +.set nNOR_CS__0__PC, CYREG_PRT3_PC4 +.set nNOR_CS__0__PORT, 3 +.set nNOR_CS__0__SHIFT, 4 +.set nNOR_CS__AG, CYREG_PRT3_AG +.set nNOR_CS__AMUX, CYREG_PRT3_AMUX +.set nNOR_CS__BIE, CYREG_PRT3_BIE +.set nNOR_CS__BIT_MASK, CYREG_PRT3_BIT_MASK +.set nNOR_CS__BYP, CYREG_PRT3_BYP +.set nNOR_CS__CTL, CYREG_PRT3_CTL +.set nNOR_CS__DM0, CYREG_PRT3_DM0 +.set nNOR_CS__DM1, CYREG_PRT3_DM1 +.set nNOR_CS__DM2, CYREG_PRT3_DM2 +.set nNOR_CS__DR, CYREG_PRT3_DR +.set nNOR_CS__INP_DIS, CYREG_PRT3_INP_DIS +.set nNOR_CS__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set nNOR_CS__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set nNOR_CS__LCD_EN, CYREG_PRT3_LCD_EN +.set nNOR_CS__MASK, 0x10 +.set nNOR_CS__PORT, 3 +.set nNOR_CS__PRT, CYREG_PRT3_PRT +.set nNOR_CS__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set nNOR_CS__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set nNOR_CS__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set nNOR_CS__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set nNOR_CS__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set nNOR_CS__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set nNOR_CS__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set nNOR_CS__PS, CYREG_PRT3_PS +.set nNOR_CS__SHIFT, 4 +.set nNOR_CS__SLW, CYREG_PRT3_SLW + +/* nNOR_WP */ +.set nNOR_WP__0__INTTYPE, CYREG_PICU3_INTTYPE5 +.set nNOR_WP__0__MASK, 0x20 +.set nNOR_WP__0__PC, CYREG_PRT3_PC5 +.set nNOR_WP__0__PORT, 3 +.set nNOR_WP__0__SHIFT, 5 +.set nNOR_WP__AG, CYREG_PRT3_AG +.set nNOR_WP__AMUX, CYREG_PRT3_AMUX +.set nNOR_WP__BIE, CYREG_PRT3_BIE +.set nNOR_WP__BIT_MASK, CYREG_PRT3_BIT_MASK +.set nNOR_WP__BYP, CYREG_PRT3_BYP +.set nNOR_WP__CTL, CYREG_PRT3_CTL +.set nNOR_WP__DM0, CYREG_PRT3_DM0 +.set nNOR_WP__DM1, CYREG_PRT3_DM1 +.set nNOR_WP__DM2, CYREG_PRT3_DM2 +.set nNOR_WP__DR, CYREG_PRT3_DR +.set nNOR_WP__INP_DIS, CYREG_PRT3_INP_DIS +.set nNOR_WP__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE +.set nNOR_WP__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG +.set nNOR_WP__LCD_EN, CYREG_PRT3_LCD_EN +.set nNOR_WP__MASK, 0x20 +.set nNOR_WP__PORT, 3 +.set nNOR_WP__PRT, CYREG_PRT3_PRT +.set nNOR_WP__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL +.set nNOR_WP__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN +.set nNOR_WP__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 +.set nNOR_WP__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 +.set nNOR_WP__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 +.set nNOR_WP__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 +.set nNOR_WP__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT +.set nNOR_WP__PS, CYREG_PRT3_PS +.set nNOR_WP__SHIFT, 5 +.set nNOR_WP__SLW, CYREG_PRT3_SLW + /* SCSI_CLK */ -.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG1_CFG0 -.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG1_CFG1 -.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG1_CFG2 +.set SCSI_CLK__CFG0, CYREG_CLKDIST_DCFG2_CFG0 +.set SCSI_CLK__CFG1, CYREG_CLKDIST_DCFG2_CFG1 +.set SCSI_CLK__CFG2, CYREG_CLKDIST_DCFG2_CFG2 .set SCSI_CLK__CFG2_SRC_SEL_MASK, 0x07 -.set SCSI_CLK__INDEX, 0x01 +.set SCSI_CLK__INDEX, 0x02 .set SCSI_CLK__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SCSI_CLK__PM_ACT_MSK, 0x02 +.set SCSI_CLK__PM_ACT_MSK, 0x04 .set SCSI_CLK__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SCSI_CLK__PM_STBY_MSK, 0x02 +.set SCSI_CLK__PM_STBY_MSK, 0x04 /* SCSI_Out */ .set SCSI_Out__0__AG, CYREG_PRT6_AG @@ -1515,15 +1784,15 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0 .set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1 -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK -.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB09_10_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB09_10_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB09_10_MSK .set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2 .set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08 @@ -1536,35 +1805,35 @@ .set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6 .set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80 .set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7 -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL -.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB09_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB09_ST_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB09_CTL +.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB09_ST_CTL .set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF -.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL -.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK +.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB09_MSK_ACTL +.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB09_MSK .set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL .set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL -.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK +.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK .set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG .set SCSI_Out_DBx__0__AMUX, CYREG_PRT6_AMUX .set SCSI_Out_DBx__0__BIE, CYREG_PRT6_BIE @@ -2012,6 +2281,17 @@ .set SCSI_Out_DBx__DB7__SHIFT, 5 .set SCSI_Out_DBx__DB7__SLW, CYREG_PRT15_SLW +/* NOR_Clock */ +.set NOR_Clock__CFG0, CYREG_CLKDIST_DCFG0_CFG0 +.set NOR_Clock__CFG1, CYREG_CLKDIST_DCFG0_CFG1 +.set NOR_Clock__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set NOR_Clock__CFG2_SRC_SEL_MASK, 0x07 +.set NOR_Clock__INDEX, 0x00 +.set NOR_Clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2 +.set NOR_Clock__PM_ACT_MSK, 0x01 +.set NOR_Clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 +.set NOR_Clock__PM_STBY_MSK, 0x01 + /* SD_RX_DMA */ .set SD_RX_DMA__DRQ_CTL, CYREG_IDMUX_DRQ_CTL0 .set SD_RX_DMA__DRQ_NUMBER, 2 @@ -2052,6 +2332,39 @@ .set SD_TX_DMA_COMPLETE__INTC_SET_EN_REG, CYREG_NVIC_SETENA0 .set SD_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 +/* nNOR_HOLD */ +.set nNOR_HOLD__0__INTTYPE, CYREG_PICU12_INTTYPE1 +.set nNOR_HOLD__0__MASK, 0x02 +.set nNOR_HOLD__0__PC, CYREG_PRT12_PC1 +.set nNOR_HOLD__0__PORT, 12 +.set nNOR_HOLD__0__SHIFT, 1 +.set nNOR_HOLD__AG, CYREG_PRT12_AG +.set nNOR_HOLD__BIE, CYREG_PRT12_BIE +.set nNOR_HOLD__BIT_MASK, CYREG_PRT12_BIT_MASK +.set nNOR_HOLD__BYP, CYREG_PRT12_BYP +.set nNOR_HOLD__DM0, CYREG_PRT12_DM0 +.set nNOR_HOLD__DM1, CYREG_PRT12_DM1 +.set nNOR_HOLD__DM2, CYREG_PRT12_DM2 +.set nNOR_HOLD__DR, CYREG_PRT12_DR +.set nNOR_HOLD__INP_DIS, CYREG_PRT12_INP_DIS +.set nNOR_HOLD__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE +.set nNOR_HOLD__MASK, 0x02 +.set nNOR_HOLD__PORT, 12 +.set nNOR_HOLD__PRT, CYREG_PRT12_PRT +.set nNOR_HOLD__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN +.set nNOR_HOLD__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 +.set nNOR_HOLD__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 +.set nNOR_HOLD__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 +.set nNOR_HOLD__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 +.set nNOR_HOLD__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT +.set nNOR_HOLD__PS, CYREG_PRT12_PS +.set nNOR_HOLD__SHIFT, 1 +.set nNOR_HOLD__SIO_CFG, CYREG_PRT12_SIO_CFG +.set nNOR_HOLD__SIO_DIFF, CYREG_PRT12_SIO_DIFF +.set nNOR_HOLD__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN +.set nNOR_HOLD__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ +.set nNOR_HOLD__SLW, CYREG_PRT12_SLW + /* SCSI_Noise */ .set SCSI_Noise__0__AG, CYREG_PRT4_AG .set SCSI_Noise__0__AMUX, CYREG_PRT4_AMUX @@ -2384,6 +2697,8 @@ .set scsiTarget_StatusReg__0__POS, 0 .set scsiTarget_StatusReg__1__MASK, 0x02 .set scsiTarget_StatusReg__1__POS, 1 +.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL +.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST .set scsiTarget_StatusReg__2__MASK, 0x04 .set scsiTarget_StatusReg__2__POS, 2 .set scsiTarget_StatusReg__3__MASK, 0x08 @@ -2391,13 +2706,13 @@ .set scsiTarget_StatusReg__4__MASK, 0x10 .set scsiTarget_StatusReg__4__POS, 4 .set scsiTarget_StatusReg__MASK, 0x1F -.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB15_MSK -.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB15_ST_CTL -.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB15_ST_CTL -.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB15_ST +.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK +.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL +.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL +.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB03_ST_CTL +.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST /* Debug_Timer */ .set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2466,111 +2781,26 @@ .set SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0 /* SD_Data_Clk */ -.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG0_CFG0 -.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG0_CFG1 -.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG0_CFG2 +.set SD_Data_Clk__CFG0, CYREG_CLKDIST_DCFG1_CFG0 +.set SD_Data_Clk__CFG1, CYREG_CLKDIST_DCFG1_CFG1 +.set SD_Data_Clk__CFG2, CYREG_CLKDIST_DCFG1_CFG2 .set SD_Data_Clk__CFG2_SRC_SEL_MASK, 0x07 -.set SD_Data_Clk__INDEX, 0x00 +.set SD_Data_Clk__INDEX, 0x01 .set SD_Data_Clk__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set SD_Data_Clk__PM_ACT_MSK, 0x01 +.set SD_Data_Clk__PM_ACT_MSK, 0x02 .set SD_Data_Clk__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set SD_Data_Clk__PM_STBY_MSK, 0x01 - -/* SPI_Pullups */ -.set SPI_Pullups__0__INTTYPE, CYREG_PICU3_INTTYPE4 -.set SPI_Pullups__0__MASK, 0x10 -.set SPI_Pullups__0__PC, CYREG_PRT3_PC4 -.set SPI_Pullups__0__PORT, 3 -.set SPI_Pullups__0__SHIFT, 4 -.set SPI_Pullups__1__INTTYPE, CYREG_PICU3_INTTYPE5 -.set SPI_Pullups__1__MASK, 0x20 -.set SPI_Pullups__1__PC, CYREG_PRT3_PC5 -.set SPI_Pullups__1__PORT, 3 -.set SPI_Pullups__1__SHIFT, 5 -.set SPI_Pullups__2__INTTYPE, CYREG_PICU3_INTTYPE6 -.set SPI_Pullups__2__MASK, 0x40 -.set SPI_Pullups__2__PC, CYREG_PRT3_PC6 -.set SPI_Pullups__2__PORT, 3 -.set SPI_Pullups__2__SHIFT, 6 -.set SPI_Pullups__3__INTTYPE, CYREG_PICU3_INTTYPE7 -.set SPI_Pullups__3__MASK, 0x80 -.set SPI_Pullups__3__PC, CYREG_PRT3_PC7 -.set SPI_Pullups__3__PORT, 3 -.set SPI_Pullups__3__SHIFT, 7 -.set SPI_Pullups__AG, CYREG_PRT3_AG -.set SPI_Pullups__AMUX, CYREG_PRT3_AMUX -.set SPI_Pullups__BIE, CYREG_PRT3_BIE -.set SPI_Pullups__BIT_MASK, CYREG_PRT3_BIT_MASK -.set SPI_Pullups__BYP, CYREG_PRT3_BYP -.set SPI_Pullups__CTL, CYREG_PRT3_CTL -.set SPI_Pullups__DM0, CYREG_PRT3_DM0 -.set SPI_Pullups__DM1, CYREG_PRT3_DM1 -.set SPI_Pullups__DM2, CYREG_PRT3_DM2 -.set SPI_Pullups__DR, CYREG_PRT3_DR -.set SPI_Pullups__INP_DIS, CYREG_PRT3_INP_DIS -.set SPI_Pullups__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU3_BASE -.set SPI_Pullups__LCD_COM_SEG, CYREG_PRT3_LCD_COM_SEG -.set SPI_Pullups__LCD_EN, CYREG_PRT3_LCD_EN -.set SPI_Pullups__MASK, 0xF0 -.set SPI_Pullups__PORT, 3 -.set SPI_Pullups__PRT, CYREG_PRT3_PRT -.set SPI_Pullups__PRTDSI__CAPS_SEL, CYREG_PRT3_CAPS_SEL -.set SPI_Pullups__PRTDSI__DBL_SYNC_IN, CYREG_PRT3_DBL_SYNC_IN -.set SPI_Pullups__PRTDSI__OE_SEL0, CYREG_PRT3_OE_SEL0 -.set SPI_Pullups__PRTDSI__OE_SEL1, CYREG_PRT3_OE_SEL1 -.set SPI_Pullups__PRTDSI__OUT_SEL0, CYREG_PRT3_OUT_SEL0 -.set SPI_Pullups__PRTDSI__OUT_SEL1, CYREG_PRT3_OUT_SEL1 -.set SPI_Pullups__PRTDSI__SYNC_OUT, CYREG_PRT3_SYNC_OUT -.set SPI_Pullups__PS, CYREG_PRT3_PS -.set SPI_Pullups__SHIFT, 4 -.set SPI_Pullups__SLW, CYREG_PRT3_SLW -.set SPI_Pullups_1__0__INTTYPE, CYREG_PICU12_INTTYPE0 -.set SPI_Pullups_1__0__MASK, 0x01 -.set SPI_Pullups_1__0__PC, CYREG_PRT12_PC0 -.set SPI_Pullups_1__0__PORT, 12 -.set SPI_Pullups_1__0__SHIFT, 0 -.set SPI_Pullups_1__1__INTTYPE, CYREG_PICU12_INTTYPE1 -.set SPI_Pullups_1__1__MASK, 0x02 -.set SPI_Pullups_1__1__PC, CYREG_PRT12_PC1 -.set SPI_Pullups_1__1__PORT, 12 -.set SPI_Pullups_1__1__SHIFT, 1 -.set SPI_Pullups_1__AG, CYREG_PRT12_AG -.set SPI_Pullups_1__BIE, CYREG_PRT12_BIE -.set SPI_Pullups_1__BIT_MASK, CYREG_PRT12_BIT_MASK -.set SPI_Pullups_1__BYP, CYREG_PRT12_BYP -.set SPI_Pullups_1__DM0, CYREG_PRT12_DM0 -.set SPI_Pullups_1__DM1, CYREG_PRT12_DM1 -.set SPI_Pullups_1__DM2, CYREG_PRT12_DM2 -.set SPI_Pullups_1__DR, CYREG_PRT12_DR -.set SPI_Pullups_1__INP_DIS, CYREG_PRT12_INP_DIS -.set SPI_Pullups_1__INTTYPE_BASE, CYDEV_PICU_INTTYPE_PICU12_BASE -.set SPI_Pullups_1__MASK, 0x03 -.set SPI_Pullups_1__PORT, 12 -.set SPI_Pullups_1__PRT, CYREG_PRT12_PRT -.set SPI_Pullups_1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN -.set SPI_Pullups_1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0 -.set SPI_Pullups_1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1 -.set SPI_Pullups_1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0 -.set SPI_Pullups_1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1 -.set SPI_Pullups_1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT -.set SPI_Pullups_1__PS, CYREG_PRT12_PS -.set SPI_Pullups_1__SHIFT, 0 -.set SPI_Pullups_1__SIO_CFG, CYREG_PRT12_SIO_CFG -.set SPI_Pullups_1__SIO_DIFF, CYREG_PRT12_SIO_DIFF -.set SPI_Pullups_1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN -.set SPI_Pullups_1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ -.set SPI_Pullups_1__SLW, CYREG_PRT12_SLW +.set SD_Data_Clk__PM_STBY_MSK, 0x02 /* timer_clock */ -.set timer_clock__CFG0, CYREG_CLKDIST_DCFG2_CFG0 -.set timer_clock__CFG1, CYREG_CLKDIST_DCFG2_CFG1 -.set timer_clock__CFG2, CYREG_CLKDIST_DCFG2_CFG2 +.set timer_clock__CFG0, CYREG_CLKDIST_DCFG3_CFG0 +.set timer_clock__CFG1, CYREG_CLKDIST_DCFG3_CFG1 +.set timer_clock__CFG2, CYREG_CLKDIST_DCFG3_CFG2 .set timer_clock__CFG2_SRC_SEL_MASK, 0x07 -.set timer_clock__INDEX, 0x02 +.set timer_clock__INDEX, 0x03 .set timer_clock__PM_ACT_CFG, CYREG_PM_ACT_CFG2 -.set timer_clock__PM_ACT_MSK, 0x04 +.set timer_clock__PM_ACT_MSK, 0x08 .set timer_clock__PM_STBY_CFG, CYREG_PM_STBY_CFG2 -.set timer_clock__PM_STBY_MSK, 0x04 +.set timer_clock__PM_STBY_MSK, 0x08 /* SCSI_RST_ISR */ .set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0 @@ -2597,8 +2827,6 @@ .set SCSI_Filtered_sts_sts_reg__0__POS, 0 .set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02 .set SCSI_Filtered_sts_sts_reg__1__POS, 1 -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL -.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST .set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04 .set SCSI_Filtered_sts_sts_reg__2__POS, 2 .set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08 @@ -2606,58 +2834,67 @@ .set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10 .set SCSI_Filtered_sts_sts_reg__4__POS, 4 .set SCSI_Filtered_sts_sts_reg__MASK, 0x1F -.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB07_MSK -.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL -.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB07_ST +.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB15_MSK +.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB15_ACTL +.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB15_ST /* SCSI_CTL_PHASE */ .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02 .set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1 +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB12_13_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB12_13_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB12_13_MSK .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04 .set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB15_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB15_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB15_ST_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB15_CTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB15_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB12_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB12_ST_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB12_CTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB12_ST_CTL .set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07 -.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB15_MSK_ACTL -.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB15_MSK +.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB12_MSK_ACTL +.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB12_MSK /* SCSI_Glitch_Ctl */ .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01 .set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_14_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB13_14_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB13_14_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB13_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB13_ST_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB13_CTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB13_ST_CTL .set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01 -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL -.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB13_MSK_ACTL +.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB13_MSK /* SCSI_Parity_Error */ .set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01 .set SCSI_Parity_Error_sts_sts_reg__0__POS, 0 -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL -.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB14_15_ST +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL +.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST .set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01 -.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB14_MSK -.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB14_ACTL -.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB14_ST +.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK +.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL +.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST /* Miscellaneous */ .set BCLK__BUS_CLK__HZ, 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc index 1fab3ec..5442ef3 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc @@ -354,33 +354,101 @@ USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +/* NOR_SI */ +NOR_SI__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +NOR_SI__0__MASK EQU 0x40 +NOR_SI__0__PC EQU CYREG_PRT3_PC6 +NOR_SI__0__PORT EQU 3 +NOR_SI__0__SHIFT EQU 6 +NOR_SI__AG EQU CYREG_PRT3_AG +NOR_SI__AMUX EQU CYREG_PRT3_AMUX +NOR_SI__BIE EQU CYREG_PRT3_BIE +NOR_SI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +NOR_SI__BYP EQU CYREG_PRT3_BYP +NOR_SI__CTL EQU CYREG_PRT3_CTL +NOR_SI__DM0 EQU CYREG_PRT3_DM0 +NOR_SI__DM1 EQU CYREG_PRT3_DM1 +NOR_SI__DM2 EQU CYREG_PRT3_DM2 +NOR_SI__DR EQU CYREG_PRT3_DR +NOR_SI__INP_DIS EQU CYREG_PRT3_INP_DIS +NOR_SI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +NOR_SI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +NOR_SI__LCD_EN EQU CYREG_PRT3_LCD_EN +NOR_SI__MASK EQU 0x40 +NOR_SI__PORT EQU 3 +NOR_SI__PRT EQU CYREG_PRT3_PRT +NOR_SI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +NOR_SI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +NOR_SI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +NOR_SI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +NOR_SI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +NOR_SI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +NOR_SI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +NOR_SI__PS EQU CYREG_PRT3_PS +NOR_SI__SHIFT EQU 6 +NOR_SI__SLW EQU CYREG_PRT3_SLW + +/* NOR_SO */ +NOR_SO__0__INTTYPE EQU CYREG_PICU15_INTTYPE2 +NOR_SO__0__MASK EQU 0x04 +NOR_SO__0__PC EQU CYREG_IO_PC_PRT15_PC2 +NOR_SO__0__PORT EQU 15 +NOR_SO__0__SHIFT EQU 2 +NOR_SO__AG EQU CYREG_PRT15_AG +NOR_SO__AMUX EQU CYREG_PRT15_AMUX +NOR_SO__BIE EQU CYREG_PRT15_BIE +NOR_SO__BIT_MASK EQU CYREG_PRT15_BIT_MASK +NOR_SO__BYP EQU CYREG_PRT15_BYP +NOR_SO__CTL EQU CYREG_PRT15_CTL +NOR_SO__DM0 EQU CYREG_PRT15_DM0 +NOR_SO__DM1 EQU CYREG_PRT15_DM1 +NOR_SO__DM2 EQU CYREG_PRT15_DM2 +NOR_SO__DR EQU CYREG_PRT15_DR +NOR_SO__INP_DIS EQU CYREG_PRT15_INP_DIS +NOR_SO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +NOR_SO__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +NOR_SO__LCD_EN EQU CYREG_PRT15_LCD_EN +NOR_SO__MASK EQU 0x04 +NOR_SO__PORT EQU 15 +NOR_SO__PRT EQU CYREG_PRT15_PRT +NOR_SO__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +NOR_SO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +NOR_SO__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +NOR_SO__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +NOR_SO__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +NOR_SO__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +NOR_SO__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +NOR_SO__PS EQU CYREG_PRT15_PS +NOR_SO__SHIFT EQU 2 +NOR_SO__SLW EQU CYREG_PRT15_SLW + /* SDCard */ -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -391,7 +459,11 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 @@ -410,14 +482,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -425,9 +495,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST /* SD_SCK */ SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -463,6 +533,137 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW +/* NOR_CTL */ +NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 +NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 +NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 +NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL +NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL +NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 +NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK + +/* NOR_SCK */ +NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 +NOR_SCK__0__MASK EQU 0x80 +NOR_SCK__0__PC EQU CYREG_PRT3_PC7 +NOR_SCK__0__PORT EQU 3 +NOR_SCK__0__SHIFT EQU 7 +NOR_SCK__AG EQU CYREG_PRT3_AG +NOR_SCK__AMUX EQU CYREG_PRT3_AMUX +NOR_SCK__BIE EQU CYREG_PRT3_BIE +NOR_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +NOR_SCK__BYP EQU CYREG_PRT3_BYP +NOR_SCK__CTL EQU CYREG_PRT3_CTL +NOR_SCK__DM0 EQU CYREG_PRT3_DM0 +NOR_SCK__DM1 EQU CYREG_PRT3_DM1 +NOR_SCK__DM2 EQU CYREG_PRT3_DM2 +NOR_SCK__DR EQU CYREG_PRT3_DR +NOR_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +NOR_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +NOR_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +NOR_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +NOR_SCK__MASK EQU 0x80 +NOR_SCK__PORT EQU 3 +NOR_SCK__PRT EQU CYREG_PRT3_PRT +NOR_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +NOR_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +NOR_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +NOR_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +NOR_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +NOR_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +NOR_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +NOR_SCK__PS EQU CYREG_PRT3_PS +NOR_SCK__SHIFT EQU 7 +NOR_SCK__SLW EQU CYREG_PRT3_SLW + +/* NOR_SPI */ +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 +NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 +NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 +NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 +NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 +NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 +NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 +NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 +NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 +NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 +NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 +NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 +NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 +NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 +NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 +NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST + /* SCSI_In */ SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 SCSI_In__0__MASK EQU 0x02 @@ -1050,16 +1251,84 @@ TERM_EN__PS EQU CYREG_PRT15_PS TERM_EN__SHIFT EQU 3 TERM_EN__SLW EQU CYREG_PRT15_SLW +/* nNOR_CS */ +nNOR_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +nNOR_CS__0__MASK EQU 0x10 +nNOR_CS__0__PC EQU CYREG_PRT3_PC4 +nNOR_CS__0__PORT EQU 3 +nNOR_CS__0__SHIFT EQU 4 +nNOR_CS__AG EQU CYREG_PRT3_AG +nNOR_CS__AMUX EQU CYREG_PRT3_AMUX +nNOR_CS__BIE EQU CYREG_PRT3_BIE +nNOR_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +nNOR_CS__BYP EQU CYREG_PRT3_BYP +nNOR_CS__CTL EQU CYREG_PRT3_CTL +nNOR_CS__DM0 EQU CYREG_PRT3_DM0 +nNOR_CS__DM1 EQU CYREG_PRT3_DM1 +nNOR_CS__DM2 EQU CYREG_PRT3_DM2 +nNOR_CS__DR EQU CYREG_PRT3_DR +nNOR_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +nNOR_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +nNOR_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +nNOR_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +nNOR_CS__MASK EQU 0x10 +nNOR_CS__PORT EQU 3 +nNOR_CS__PRT EQU CYREG_PRT3_PRT +nNOR_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +nNOR_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +nNOR_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +nNOR_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +nNOR_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +nNOR_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +nNOR_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +nNOR_CS__PS EQU CYREG_PRT3_PS +nNOR_CS__SHIFT EQU 4 +nNOR_CS__SLW EQU CYREG_PRT3_SLW + +/* nNOR_WP */ +nNOR_WP__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +nNOR_WP__0__MASK EQU 0x20 +nNOR_WP__0__PC EQU CYREG_PRT3_PC5 +nNOR_WP__0__PORT EQU 3 +nNOR_WP__0__SHIFT EQU 5 +nNOR_WP__AG EQU CYREG_PRT3_AG +nNOR_WP__AMUX EQU CYREG_PRT3_AMUX +nNOR_WP__BIE EQU CYREG_PRT3_BIE +nNOR_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +nNOR_WP__BYP EQU CYREG_PRT3_BYP +nNOR_WP__CTL EQU CYREG_PRT3_CTL +nNOR_WP__DM0 EQU CYREG_PRT3_DM0 +nNOR_WP__DM1 EQU CYREG_PRT3_DM1 +nNOR_WP__DM2 EQU CYREG_PRT3_DM2 +nNOR_WP__DR EQU CYREG_PRT3_DR +nNOR_WP__INP_DIS EQU CYREG_PRT3_INP_DIS +nNOR_WP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +nNOR_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +nNOR_WP__LCD_EN EQU CYREG_PRT3_LCD_EN +nNOR_WP__MASK EQU 0x20 +nNOR_WP__PORT EQU 3 +nNOR_WP__PRT EQU CYREG_PRT3_PRT +nNOR_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +nNOR_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +nNOR_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +nNOR_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +nNOR_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +nNOR_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +nNOR_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +nNOR_WP__PS EQU CYREG_PRT3_PS +nNOR_WP__SHIFT EQU 5 +nNOR_WP__SLW EQU CYREG_PRT3_SLW + /* SCSI_CLK */ -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__INDEX EQU 0x02 SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_ACT_MSK EQU 0x04 SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +SCSI_CLK__PM_STBY_MSK EQU 0x04 /* SCSI_Out */ SCSI_Out__0__AG EQU CYREG_PRT6_AG @@ -1514,15 +1783,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1535,35 +1804,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2011,6 +2280,17 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS SCSI_Out_DBx__DB7__SHIFT EQU 5 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW +/* NOR_Clock */ +NOR_Clock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +NOR_Clock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +NOR_Clock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +NOR_Clock__CFG2_SRC_SEL_MASK EQU 0x07 +NOR_Clock__INDEX EQU 0x00 +NOR_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +NOR_Clock__PM_ACT_MSK EQU 0x01 +NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +NOR_Clock__PM_STBY_MSK EQU 0x01 + /* SD_RX_DMA */ SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2051,6 +2331,39 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +/* nNOR_HOLD */ +nNOR_HOLD__0__INTTYPE EQU CYREG_PICU12_INTTYPE1 +nNOR_HOLD__0__MASK EQU 0x02 +nNOR_HOLD__0__PC EQU CYREG_PRT12_PC1 +nNOR_HOLD__0__PORT EQU 12 +nNOR_HOLD__0__SHIFT EQU 1 +nNOR_HOLD__AG EQU CYREG_PRT12_AG +nNOR_HOLD__BIE EQU CYREG_PRT12_BIE +nNOR_HOLD__BIT_MASK EQU CYREG_PRT12_BIT_MASK +nNOR_HOLD__BYP EQU CYREG_PRT12_BYP +nNOR_HOLD__DM0 EQU CYREG_PRT12_DM0 +nNOR_HOLD__DM1 EQU CYREG_PRT12_DM1 +nNOR_HOLD__DM2 EQU CYREG_PRT12_DM2 +nNOR_HOLD__DR EQU CYREG_PRT12_DR +nNOR_HOLD__INP_DIS EQU CYREG_PRT12_INP_DIS +nNOR_HOLD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +nNOR_HOLD__MASK EQU 0x02 +nNOR_HOLD__PORT EQU 12 +nNOR_HOLD__PRT EQU CYREG_PRT12_PRT +nNOR_HOLD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +nNOR_HOLD__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +nNOR_HOLD__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +nNOR_HOLD__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +nNOR_HOLD__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +nNOR_HOLD__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +nNOR_HOLD__PS EQU CYREG_PRT12_PS +nNOR_HOLD__SHIFT EQU 1 +nNOR_HOLD__SIO_CFG EQU CYREG_PRT12_SIO_CFG +nNOR_HOLD__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +nNOR_HOLD__SLW EQU CYREG_PRT12_SLW + /* SCSI_Noise */ SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2383,6 +2696,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2390,13 +2705,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST /* Debug_Timer */ Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2465,111 +2780,26 @@ SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 /* SD_Data_Clk */ -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__INDEX EQU 0x01 SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_ACT_MSK EQU 0x02 SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -/* SPI_Pullups */ -SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SPI_Pullups__0__MASK EQU 0x10 -SPI_Pullups__0__PC EQU CYREG_PRT3_PC4 -SPI_Pullups__0__PORT EQU 3 -SPI_Pullups__0__SHIFT EQU 4 -SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SPI_Pullups__1__MASK EQU 0x20 -SPI_Pullups__1__PC EQU CYREG_PRT3_PC5 -SPI_Pullups__1__PORT EQU 3 -SPI_Pullups__1__SHIFT EQU 5 -SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SPI_Pullups__2__MASK EQU 0x40 -SPI_Pullups__2__PC EQU CYREG_PRT3_PC6 -SPI_Pullups__2__PORT EQU 3 -SPI_Pullups__2__SHIFT EQU 6 -SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 -SPI_Pullups__3__MASK EQU 0x80 -SPI_Pullups__3__PC EQU CYREG_PRT3_PC7 -SPI_Pullups__3__PORT EQU 3 -SPI_Pullups__3__SHIFT EQU 7 -SPI_Pullups__AG EQU CYREG_PRT3_AG -SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX -SPI_Pullups__BIE EQU CYREG_PRT3_BIE -SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SPI_Pullups__BYP EQU CYREG_PRT3_BYP -SPI_Pullups__CTL EQU CYREG_PRT3_CTL -SPI_Pullups__DM0 EQU CYREG_PRT3_DM0 -SPI_Pullups__DM1 EQU CYREG_PRT3_DM1 -SPI_Pullups__DM2 EQU CYREG_PRT3_DM2 -SPI_Pullups__DR EQU CYREG_PRT3_DR -SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS -SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN -SPI_Pullups__MASK EQU 0xF0 -SPI_Pullups__PORT EQU 3 -SPI_Pullups__PRT EQU CYREG_PRT3_PRT -SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SPI_Pullups__PS EQU CYREG_PRT3_PS -SPI_Pullups__SHIFT EQU 4 -SPI_Pullups__SLW EQU CYREG_PRT3_SLW -SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 -SPI_Pullups_1__0__MASK EQU 0x01 -SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0 -SPI_Pullups_1__0__PORT EQU 12 -SPI_Pullups_1__0__SHIFT EQU 0 -SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 -SPI_Pullups_1__1__MASK EQU 0x02 -SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1 -SPI_Pullups_1__1__PORT EQU 12 -SPI_Pullups_1__1__SHIFT EQU 1 -SPI_Pullups_1__AG EQU CYREG_PRT12_AG -SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE -SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP -SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0 -SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1 -SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2 -SPI_Pullups_1__DR EQU CYREG_PRT12_DR -SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS -SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE -SPI_Pullups_1__MASK EQU 0x03 -SPI_Pullups_1__PORT EQU 12 -SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT -SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SPI_Pullups_1__PS EQU CYREG_PRT12_PS -SPI_Pullups_1__SHIFT EQU 0 -SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW +SD_Data_Clk__PM_STBY_MSK EQU 0x02 /* timer_clock */ -timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 -timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 -timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 -timer_clock__INDEX EQU 0x02 +timer_clock__INDEX EQU 0x03 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -timer_clock__PM_ACT_MSK EQU 0x04 +timer_clock__PM_ACT_MSK EQU 0x08 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -timer_clock__PM_STBY_MSK EQU 0x04 +timer_clock__PM_STBY_MSK EQU 0x08 /* SCSI_RST_ISR */ SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2596,8 +2826,6 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2605,58 +2833,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST /* SCSI_CTL_PHASE */ SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK /* SCSI_Glitch_Ctl */ SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK /* SCSI_Parity_Error */ SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST /* Miscellaneous */ BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc index cd3a5eb..5ddb795 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc @@ -354,33 +354,101 @@ USBFS_USB__USB_CLK_EN EQU CYREG_USB_USB_CLK_EN USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0 USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1 +; NOR_SI +NOR_SI__0__INTTYPE EQU CYREG_PICU3_INTTYPE6 +NOR_SI__0__MASK EQU 0x40 +NOR_SI__0__PC EQU CYREG_PRT3_PC6 +NOR_SI__0__PORT EQU 3 +NOR_SI__0__SHIFT EQU 6 +NOR_SI__AG EQU CYREG_PRT3_AG +NOR_SI__AMUX EQU CYREG_PRT3_AMUX +NOR_SI__BIE EQU CYREG_PRT3_BIE +NOR_SI__BIT_MASK EQU CYREG_PRT3_BIT_MASK +NOR_SI__BYP EQU CYREG_PRT3_BYP +NOR_SI__CTL EQU CYREG_PRT3_CTL +NOR_SI__DM0 EQU CYREG_PRT3_DM0 +NOR_SI__DM1 EQU CYREG_PRT3_DM1 +NOR_SI__DM2 EQU CYREG_PRT3_DM2 +NOR_SI__DR EQU CYREG_PRT3_DR +NOR_SI__INP_DIS EQU CYREG_PRT3_INP_DIS +NOR_SI__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +NOR_SI__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +NOR_SI__LCD_EN EQU CYREG_PRT3_LCD_EN +NOR_SI__MASK EQU 0x40 +NOR_SI__PORT EQU 3 +NOR_SI__PRT EQU CYREG_PRT3_PRT +NOR_SI__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +NOR_SI__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +NOR_SI__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +NOR_SI__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +NOR_SI__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +NOR_SI__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +NOR_SI__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +NOR_SI__PS EQU CYREG_PRT3_PS +NOR_SI__SHIFT EQU 6 +NOR_SI__SLW EQU CYREG_PRT3_SLW + +; NOR_SO +NOR_SO__0__INTTYPE EQU CYREG_PICU15_INTTYPE2 +NOR_SO__0__MASK EQU 0x04 +NOR_SO__0__PC EQU CYREG_IO_PC_PRT15_PC2 +NOR_SO__0__PORT EQU 15 +NOR_SO__0__SHIFT EQU 2 +NOR_SO__AG EQU CYREG_PRT15_AG +NOR_SO__AMUX EQU CYREG_PRT15_AMUX +NOR_SO__BIE EQU CYREG_PRT15_BIE +NOR_SO__BIT_MASK EQU CYREG_PRT15_BIT_MASK +NOR_SO__BYP EQU CYREG_PRT15_BYP +NOR_SO__CTL EQU CYREG_PRT15_CTL +NOR_SO__DM0 EQU CYREG_PRT15_DM0 +NOR_SO__DM1 EQU CYREG_PRT15_DM1 +NOR_SO__DM2 EQU CYREG_PRT15_DM2 +NOR_SO__DR EQU CYREG_PRT15_DR +NOR_SO__INP_DIS EQU CYREG_PRT15_INP_DIS +NOR_SO__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU15_BASE +NOR_SO__LCD_COM_SEG EQU CYREG_PRT15_LCD_COM_SEG +NOR_SO__LCD_EN EQU CYREG_PRT15_LCD_EN +NOR_SO__MASK EQU 0x04 +NOR_SO__PORT EQU 15 +NOR_SO__PRT EQU CYREG_PRT15_PRT +NOR_SO__PRTDSI__CAPS_SEL EQU CYREG_PRT15_CAPS_SEL +NOR_SO__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT15_DBL_SYNC_IN +NOR_SO__PRTDSI__OE_SEL0 EQU CYREG_PRT15_OE_SEL0 +NOR_SO__PRTDSI__OE_SEL1 EQU CYREG_PRT15_OE_SEL1 +NOR_SO__PRTDSI__OUT_SEL0 EQU CYREG_PRT15_OUT_SEL0 +NOR_SO__PRTDSI__OUT_SEL1 EQU CYREG_PRT15_OUT_SEL1 +NOR_SO__PRTDSI__SYNC_OUT EQU CYREG_PRT15_SYNC_OUT +NOR_SO__PS EQU CYREG_PRT15_PS +NOR_SO__SHIFT EQU 2 +NOR_SO__SLW EQU CYREG_PRT15_SLW + ; SDCard -SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL -SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK -SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL -SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL -SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST -SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK -SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL -SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL -SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST +SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL +SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK +SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB05_CTL +SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL +SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB05_06_ST +SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB05_MSK +SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL +SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB05_ST_CTL +SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB05_ST SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10 @@ -391,7 +459,11 @@ SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40 SDCard_BSPIM_RxStsReg__6__POS EQU 6 SDCard_BSPIM_RxStsReg__MASK EQU 0x70 SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK +SDCard_BSPIM_RxStsReg__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +SDCard_BSPIM_RxStsReg__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +SDCard_BSPIM_RxStsReg__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL +SDCard_BSPIM_RxStsReg__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0 SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1 @@ -410,14 +482,12 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1 SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0 SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1 -SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL -SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01 SDCard_BSPIM_TxStsReg__0__POS EQU 0 SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02 SDCard_BSPIM_TxStsReg__1__POS EQU 1 -SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL -SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST +SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL +SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04 SDCard_BSPIM_TxStsReg__2__POS EQU 2 SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08 @@ -425,9 +495,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3 SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10 SDCard_BSPIM_TxStsReg__4__POS EQU 4 SDCard_BSPIM_TxStsReg__MASK EQU 0x1F -SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK -SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL -SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST +SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB06_MSK +SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL +SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB06_ST ; SD_SCK SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE1 @@ -463,6 +533,137 @@ SD_SCK__PS EQU CYREG_PRT3_PS SD_SCK__SHIFT EQU 1 SD_SCK__SLW EQU CYREG_PRT3_SLW +; NOR_CTL +NOR_CTL_Sync_ctrl_reg__0__MASK EQU 0x01 +NOR_CTL_Sync_ctrl_reg__0__POS EQU 0 +NOR_CTL_Sync_ctrl_reg__1__MASK EQU 0x02 +NOR_CTL_Sync_ctrl_reg__1__POS EQU 1 +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL +NOR_CTL_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK +NOR_CTL_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL +NOR_CTL_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB06_CTL +NOR_CTL_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL +NOR_CTL_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB06_CTL +NOR_CTL_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL +NOR_CTL_Sync_ctrl_reg__MASK EQU 0x03 +NOR_CTL_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +NOR_CTL_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL +NOR_CTL_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB06_MSK + +; NOR_SCK +NOR_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE7 +NOR_SCK__0__MASK EQU 0x80 +NOR_SCK__0__PC EQU CYREG_PRT3_PC7 +NOR_SCK__0__PORT EQU 3 +NOR_SCK__0__SHIFT EQU 7 +NOR_SCK__AG EQU CYREG_PRT3_AG +NOR_SCK__AMUX EQU CYREG_PRT3_AMUX +NOR_SCK__BIE EQU CYREG_PRT3_BIE +NOR_SCK__BIT_MASK EQU CYREG_PRT3_BIT_MASK +NOR_SCK__BYP EQU CYREG_PRT3_BYP +NOR_SCK__CTL EQU CYREG_PRT3_CTL +NOR_SCK__DM0 EQU CYREG_PRT3_DM0 +NOR_SCK__DM1 EQU CYREG_PRT3_DM1 +NOR_SCK__DM2 EQU CYREG_PRT3_DM2 +NOR_SCK__DR EQU CYREG_PRT3_DR +NOR_SCK__INP_DIS EQU CYREG_PRT3_INP_DIS +NOR_SCK__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +NOR_SCK__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +NOR_SCK__LCD_EN EQU CYREG_PRT3_LCD_EN +NOR_SCK__MASK EQU 0x80 +NOR_SCK__PORT EQU 3 +NOR_SCK__PRT EQU CYREG_PRT3_PRT +NOR_SCK__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +NOR_SCK__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +NOR_SCK__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +NOR_SCK__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +NOR_SCK__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +NOR_SCK__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +NOR_SCK__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +NOR_SCK__PS EQU CYREG_PRT3_PS +NOR_SCK__SHIFT EQU 7 +NOR_SCK__SLW EQU CYREG_PRT3_SLW + +; NOR_SPI +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB08_09_CTL +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB08_09_MSK +NOR_SPI_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +NOR_SPI_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB08_CTL +NOR_SPI_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB08_CTL +NOR_SPI_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB08_MSK +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL +NOR_SPI_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST +NOR_SPI_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB08_MSK +NOR_SPI_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB08_MSK_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB08_ST_CTL +NOR_SPI_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB08_ST +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL +NOR_SPI_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST +NOR_SPI_BSPIM_RxStsReg__4__MASK EQU 0x10 +NOR_SPI_BSPIM_RxStsReg__4__POS EQU 4 +NOR_SPI_BSPIM_RxStsReg__5__MASK EQU 0x20 +NOR_SPI_BSPIM_RxStsReg__5__POS EQU 5 +NOR_SPI_BSPIM_RxStsReg__6__MASK EQU 0x40 +NOR_SPI_BSPIM_RxStsReg__6__POS EQU 6 +NOR_SPI_BSPIM_RxStsReg__MASK EQU 0x70 +NOR_SPI_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK +NOR_SPI_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL +NOR_SPI_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB04_05_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB04_05_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB04_05_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB04_05_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB04_05_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB04_05_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB04_A0_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB04_A0 +NOR_SPI_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB04_A1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB04_D0_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB04_D0 +NOR_SPI_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB04_D1 +NOR_SPI_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL +NOR_SPI_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB04_F0_F1 +NOR_SPI_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB04_F0 +NOR_SPI_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB04_F1 +NOR_SPI_BSPIM_TxStsReg__0__MASK EQU 0x01 +NOR_SPI_BSPIM_TxStsReg__0__POS EQU 0 +NOR_SPI_BSPIM_TxStsReg__1__MASK EQU 0x02 +NOR_SPI_BSPIM_TxStsReg__1__POS EQU 1 +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL +NOR_SPI_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST +NOR_SPI_BSPIM_TxStsReg__2__MASK EQU 0x04 +NOR_SPI_BSPIM_TxStsReg__2__POS EQU 2 +NOR_SPI_BSPIM_TxStsReg__3__MASK EQU 0x08 +NOR_SPI_BSPIM_TxStsReg__3__POS EQU 3 +NOR_SPI_BSPIM_TxStsReg__4__MASK EQU 0x10 +NOR_SPI_BSPIM_TxStsReg__4__POS EQU 4 +NOR_SPI_BSPIM_TxStsReg__MASK EQU 0x1F +NOR_SPI_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK +NOR_SPI_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL +NOR_SPI_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST + ; SCSI_In SCSI_In__0__INTTYPE EQU CYREG_PICU6_INTTYPE1 SCSI_In__0__MASK EQU 0x02 @@ -1050,16 +1251,84 @@ TERM_EN__PS EQU CYREG_PRT15_PS TERM_EN__SHIFT EQU 3 TERM_EN__SLW EQU CYREG_PRT15_SLW +; nNOR_CS +nNOR_CS__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 +nNOR_CS__0__MASK EQU 0x10 +nNOR_CS__0__PC EQU CYREG_PRT3_PC4 +nNOR_CS__0__PORT EQU 3 +nNOR_CS__0__SHIFT EQU 4 +nNOR_CS__AG EQU CYREG_PRT3_AG +nNOR_CS__AMUX EQU CYREG_PRT3_AMUX +nNOR_CS__BIE EQU CYREG_PRT3_BIE +nNOR_CS__BIT_MASK EQU CYREG_PRT3_BIT_MASK +nNOR_CS__BYP EQU CYREG_PRT3_BYP +nNOR_CS__CTL EQU CYREG_PRT3_CTL +nNOR_CS__DM0 EQU CYREG_PRT3_DM0 +nNOR_CS__DM1 EQU CYREG_PRT3_DM1 +nNOR_CS__DM2 EQU CYREG_PRT3_DM2 +nNOR_CS__DR EQU CYREG_PRT3_DR +nNOR_CS__INP_DIS EQU CYREG_PRT3_INP_DIS +nNOR_CS__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +nNOR_CS__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +nNOR_CS__LCD_EN EQU CYREG_PRT3_LCD_EN +nNOR_CS__MASK EQU 0x10 +nNOR_CS__PORT EQU 3 +nNOR_CS__PRT EQU CYREG_PRT3_PRT +nNOR_CS__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +nNOR_CS__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +nNOR_CS__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +nNOR_CS__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +nNOR_CS__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +nNOR_CS__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +nNOR_CS__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +nNOR_CS__PS EQU CYREG_PRT3_PS +nNOR_CS__SHIFT EQU 4 +nNOR_CS__SLW EQU CYREG_PRT3_SLW + +; nNOR_WP +nNOR_WP__0__INTTYPE EQU CYREG_PICU3_INTTYPE5 +nNOR_WP__0__MASK EQU 0x20 +nNOR_WP__0__PC EQU CYREG_PRT3_PC5 +nNOR_WP__0__PORT EQU 3 +nNOR_WP__0__SHIFT EQU 5 +nNOR_WP__AG EQU CYREG_PRT3_AG +nNOR_WP__AMUX EQU CYREG_PRT3_AMUX +nNOR_WP__BIE EQU CYREG_PRT3_BIE +nNOR_WP__BIT_MASK EQU CYREG_PRT3_BIT_MASK +nNOR_WP__BYP EQU CYREG_PRT3_BYP +nNOR_WP__CTL EQU CYREG_PRT3_CTL +nNOR_WP__DM0 EQU CYREG_PRT3_DM0 +nNOR_WP__DM1 EQU CYREG_PRT3_DM1 +nNOR_WP__DM2 EQU CYREG_PRT3_DM2 +nNOR_WP__DR EQU CYREG_PRT3_DR +nNOR_WP__INP_DIS EQU CYREG_PRT3_INP_DIS +nNOR_WP__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE +nNOR_WP__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG +nNOR_WP__LCD_EN EQU CYREG_PRT3_LCD_EN +nNOR_WP__MASK EQU 0x20 +nNOR_WP__PORT EQU 3 +nNOR_WP__PRT EQU CYREG_PRT3_PRT +nNOR_WP__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL +nNOR_WP__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN +nNOR_WP__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 +nNOR_WP__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 +nNOR_WP__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 +nNOR_WP__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 +nNOR_WP__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT +nNOR_WP__PS EQU CYREG_PRT3_PS +nNOR_WP__SHIFT EQU 5 +nNOR_WP__SLW EQU CYREG_PRT3_SLW + ; SCSI_CLK -SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 -SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 -SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 +SCSI_CLK__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 +SCSI_CLK__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 +SCSI_CLK__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 SCSI_CLK__CFG2_SRC_SEL_MASK EQU 0x07 -SCSI_CLK__INDEX EQU 0x01 +SCSI_CLK__INDEX EQU 0x02 SCSI_CLK__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SCSI_CLK__PM_ACT_MSK EQU 0x02 +SCSI_CLK__PM_ACT_MSK EQU 0x04 SCSI_CLK__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SCSI_CLK__PM_STBY_MSK EQU 0x02 +SCSI_CLK__PM_STBY_MSK EQU 0x04 ; SCSI_Out SCSI_Out__0__AG EQU CYREG_PRT6_AG @@ -1514,15 +1783,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0 SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1 -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK -SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB09_10_CTL +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB09_10_MSK +SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB09_10_MSK SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2 SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08 @@ -1535,35 +1804,35 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40 SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6 SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80 SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7 -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL -SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB09_ST_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB09_CTL +SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB09_ST_CTL SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF -SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL -SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK +SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB09_MSK_ACTL +SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB09_MSK SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL -SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL +SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL -SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK +SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG SCSI_Out_DBx__0__AMUX EQU CYREG_PRT6_AMUX SCSI_Out_DBx__0__BIE EQU CYREG_PRT6_BIE @@ -2011,6 +2280,17 @@ SCSI_Out_DBx__DB7__PS EQU CYREG_PRT15_PS SCSI_Out_DBx__DB7__SHIFT EQU 5 SCSI_Out_DBx__DB7__SLW EQU CYREG_PRT15_SLW +; NOR_Clock +NOR_Clock__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 +NOR_Clock__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 +NOR_Clock__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +NOR_Clock__CFG2_SRC_SEL_MASK EQU 0x07 +NOR_Clock__INDEX EQU 0x00 +NOR_Clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 +NOR_Clock__PM_ACT_MSK EQU 0x01 +NOR_Clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 +NOR_Clock__PM_STBY_MSK EQU 0x01 + ; SD_RX_DMA SD_RX_DMA__DRQ_CTL EQU CYREG_IDMUX_DRQ_CTL0 SD_RX_DMA__DRQ_NUMBER EQU 2 @@ -2051,6 +2331,39 @@ SD_TX_DMA_COMPLETE__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_6 SD_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SD_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 +; nNOR_HOLD +nNOR_HOLD__0__INTTYPE EQU CYREG_PICU12_INTTYPE1 +nNOR_HOLD__0__MASK EQU 0x02 +nNOR_HOLD__0__PC EQU CYREG_PRT12_PC1 +nNOR_HOLD__0__PORT EQU 12 +nNOR_HOLD__0__SHIFT EQU 1 +nNOR_HOLD__AG EQU CYREG_PRT12_AG +nNOR_HOLD__BIE EQU CYREG_PRT12_BIE +nNOR_HOLD__BIT_MASK EQU CYREG_PRT12_BIT_MASK +nNOR_HOLD__BYP EQU CYREG_PRT12_BYP +nNOR_HOLD__DM0 EQU CYREG_PRT12_DM0 +nNOR_HOLD__DM1 EQU CYREG_PRT12_DM1 +nNOR_HOLD__DM2 EQU CYREG_PRT12_DM2 +nNOR_HOLD__DR EQU CYREG_PRT12_DR +nNOR_HOLD__INP_DIS EQU CYREG_PRT12_INP_DIS +nNOR_HOLD__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE +nNOR_HOLD__MASK EQU 0x02 +nNOR_HOLD__PORT EQU 12 +nNOR_HOLD__PRT EQU CYREG_PRT12_PRT +nNOR_HOLD__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN +nNOR_HOLD__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 +nNOR_HOLD__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 +nNOR_HOLD__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 +nNOR_HOLD__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 +nNOR_HOLD__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT +nNOR_HOLD__PS EQU CYREG_PRT12_PS +nNOR_HOLD__SHIFT EQU 1 +nNOR_HOLD__SIO_CFG EQU CYREG_PRT12_SIO_CFG +nNOR_HOLD__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF +nNOR_HOLD__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN +nNOR_HOLD__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ +nNOR_HOLD__SLW EQU CYREG_PRT12_SLW + ; SCSI_Noise SCSI_Noise__0__AG EQU CYREG_PRT4_AG SCSI_Noise__0__AMUX EQU CYREG_PRT4_AMUX @@ -2383,6 +2696,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01 scsiTarget_StatusReg__0__POS EQU 0 scsiTarget_StatusReg__1__MASK EQU 0x02 scsiTarget_StatusReg__1__POS EQU 1 +scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL +scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST scsiTarget_StatusReg__2__MASK EQU 0x04 scsiTarget_StatusReg__2__POS EQU 2 scsiTarget_StatusReg__3__MASK EQU 0x08 @@ -2390,13 +2705,13 @@ scsiTarget_StatusReg__3__POS EQU 3 scsiTarget_StatusReg__4__MASK EQU 0x10 scsiTarget_StatusReg__4__POS EQU 4 scsiTarget_StatusReg__MASK EQU 0x1F -scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB15_MSK -scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB15_ST_CTL -scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB15_ST +scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK +scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL +scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL +scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB03_ST_CTL +scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST ; Debug_Timer Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2465,111 +2780,26 @@ SCSI_TX_DMA_COMPLETE__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0 SCSI_TX_DMA_COMPLETE__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0 ; SD_Data_Clk -SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG0_CFG0 -SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG0_CFG1 -SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG0_CFG2 +SD_Data_Clk__CFG0 EQU CYREG_CLKDIST_DCFG1_CFG0 +SD_Data_Clk__CFG1 EQU CYREG_CLKDIST_DCFG1_CFG1 +SD_Data_Clk__CFG2 EQU CYREG_CLKDIST_DCFG1_CFG2 SD_Data_Clk__CFG2_SRC_SEL_MASK EQU 0x07 -SD_Data_Clk__INDEX EQU 0x00 +SD_Data_Clk__INDEX EQU 0x01 SD_Data_Clk__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -SD_Data_Clk__PM_ACT_MSK EQU 0x01 +SD_Data_Clk__PM_ACT_MSK EQU 0x02 SD_Data_Clk__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -SD_Data_Clk__PM_STBY_MSK EQU 0x01 - -; SPI_Pullups -SPI_Pullups__0__INTTYPE EQU CYREG_PICU3_INTTYPE4 -SPI_Pullups__0__MASK EQU 0x10 -SPI_Pullups__0__PC EQU CYREG_PRT3_PC4 -SPI_Pullups__0__PORT EQU 3 -SPI_Pullups__0__SHIFT EQU 4 -SPI_Pullups__1__INTTYPE EQU CYREG_PICU3_INTTYPE5 -SPI_Pullups__1__MASK EQU 0x20 -SPI_Pullups__1__PC EQU CYREG_PRT3_PC5 -SPI_Pullups__1__PORT EQU 3 -SPI_Pullups__1__SHIFT EQU 5 -SPI_Pullups__2__INTTYPE EQU CYREG_PICU3_INTTYPE6 -SPI_Pullups__2__MASK EQU 0x40 -SPI_Pullups__2__PC EQU CYREG_PRT3_PC6 -SPI_Pullups__2__PORT EQU 3 -SPI_Pullups__2__SHIFT EQU 6 -SPI_Pullups__3__INTTYPE EQU CYREG_PICU3_INTTYPE7 -SPI_Pullups__3__MASK EQU 0x80 -SPI_Pullups__3__PC EQU CYREG_PRT3_PC7 -SPI_Pullups__3__PORT EQU 3 -SPI_Pullups__3__SHIFT EQU 7 -SPI_Pullups__AG EQU CYREG_PRT3_AG -SPI_Pullups__AMUX EQU CYREG_PRT3_AMUX -SPI_Pullups__BIE EQU CYREG_PRT3_BIE -SPI_Pullups__BIT_MASK EQU CYREG_PRT3_BIT_MASK -SPI_Pullups__BYP EQU CYREG_PRT3_BYP -SPI_Pullups__CTL EQU CYREG_PRT3_CTL -SPI_Pullups__DM0 EQU CYREG_PRT3_DM0 -SPI_Pullups__DM1 EQU CYREG_PRT3_DM1 -SPI_Pullups__DM2 EQU CYREG_PRT3_DM2 -SPI_Pullups__DR EQU CYREG_PRT3_DR -SPI_Pullups__INP_DIS EQU CYREG_PRT3_INP_DIS -SPI_Pullups__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU3_BASE -SPI_Pullups__LCD_COM_SEG EQU CYREG_PRT3_LCD_COM_SEG -SPI_Pullups__LCD_EN EQU CYREG_PRT3_LCD_EN -SPI_Pullups__MASK EQU 0xF0 -SPI_Pullups__PORT EQU 3 -SPI_Pullups__PRT EQU CYREG_PRT3_PRT -SPI_Pullups__PRTDSI__CAPS_SEL EQU CYREG_PRT3_CAPS_SEL -SPI_Pullups__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT3_DBL_SYNC_IN -SPI_Pullups__PRTDSI__OE_SEL0 EQU CYREG_PRT3_OE_SEL0 -SPI_Pullups__PRTDSI__OE_SEL1 EQU CYREG_PRT3_OE_SEL1 -SPI_Pullups__PRTDSI__OUT_SEL0 EQU CYREG_PRT3_OUT_SEL0 -SPI_Pullups__PRTDSI__OUT_SEL1 EQU CYREG_PRT3_OUT_SEL1 -SPI_Pullups__PRTDSI__SYNC_OUT EQU CYREG_PRT3_SYNC_OUT -SPI_Pullups__PS EQU CYREG_PRT3_PS -SPI_Pullups__SHIFT EQU 4 -SPI_Pullups__SLW EQU CYREG_PRT3_SLW -SPI_Pullups_1__0__INTTYPE EQU CYREG_PICU12_INTTYPE0 -SPI_Pullups_1__0__MASK EQU 0x01 -SPI_Pullups_1__0__PC EQU CYREG_PRT12_PC0 -SPI_Pullups_1__0__PORT EQU 12 -SPI_Pullups_1__0__SHIFT EQU 0 -SPI_Pullups_1__1__INTTYPE EQU CYREG_PICU12_INTTYPE1 -SPI_Pullups_1__1__MASK EQU 0x02 -SPI_Pullups_1__1__PC EQU CYREG_PRT12_PC1 -SPI_Pullups_1__1__PORT EQU 12 -SPI_Pullups_1__1__SHIFT EQU 1 -SPI_Pullups_1__AG EQU CYREG_PRT12_AG -SPI_Pullups_1__BIE EQU CYREG_PRT12_BIE -SPI_Pullups_1__BIT_MASK EQU CYREG_PRT12_BIT_MASK -SPI_Pullups_1__BYP EQU CYREG_PRT12_BYP -SPI_Pullups_1__DM0 EQU CYREG_PRT12_DM0 -SPI_Pullups_1__DM1 EQU CYREG_PRT12_DM1 -SPI_Pullups_1__DM2 EQU CYREG_PRT12_DM2 -SPI_Pullups_1__DR EQU CYREG_PRT12_DR -SPI_Pullups_1__INP_DIS EQU CYREG_PRT12_INP_DIS -SPI_Pullups_1__INTTYPE_BASE EQU CYDEV_PICU_INTTYPE_PICU12_BASE -SPI_Pullups_1__MASK EQU 0x03 -SPI_Pullups_1__PORT EQU 12 -SPI_Pullups_1__PRT EQU CYREG_PRT12_PRT -SPI_Pullups_1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN -SPI_Pullups_1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0 -SPI_Pullups_1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1 -SPI_Pullups_1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0 -SPI_Pullups_1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1 -SPI_Pullups_1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT -SPI_Pullups_1__PS EQU CYREG_PRT12_PS -SPI_Pullups_1__SHIFT EQU 0 -SPI_Pullups_1__SIO_CFG EQU CYREG_PRT12_SIO_CFG -SPI_Pullups_1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF -SPI_Pullups_1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN -SPI_Pullups_1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ -SPI_Pullups_1__SLW EQU CYREG_PRT12_SLW +SD_Data_Clk__PM_STBY_MSK EQU 0x02 ; timer_clock -timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG2_CFG0 -timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG2_CFG1 -timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG2_CFG2 +timer_clock__CFG0 EQU CYREG_CLKDIST_DCFG3_CFG0 +timer_clock__CFG1 EQU CYREG_CLKDIST_DCFG3_CFG1 +timer_clock__CFG2 EQU CYREG_CLKDIST_DCFG3_CFG2 timer_clock__CFG2_SRC_SEL_MASK EQU 0x07 -timer_clock__INDEX EQU 0x02 +timer_clock__INDEX EQU 0x03 timer_clock__PM_ACT_CFG EQU CYREG_PM_ACT_CFG2 -timer_clock__PM_ACT_MSK EQU 0x04 +timer_clock__PM_ACT_MSK EQU 0x08 timer_clock__PM_STBY_CFG EQU CYREG_PM_STBY_CFG2 -timer_clock__PM_STBY_MSK EQU 0x04 +timer_clock__PM_STBY_MSK EQU 0x08 ; SCSI_RST_ISR SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0 @@ -2596,8 +2826,6 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01 SCSI_Filtered_sts_sts_reg__0__POS EQU 0 SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02 SCSI_Filtered_sts_sts_reg__1__POS EQU 1 -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL -SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04 SCSI_Filtered_sts_sts_reg__2__POS EQU 2 SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08 @@ -2605,58 +2833,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3 SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10 SCSI_Filtered_sts_sts_reg__4__POS EQU 4 SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F -SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB07_MSK -SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL -SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB07_ST +SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB15_MSK +SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL +SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB15_ST ; SCSI_CTL_PHASE SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0 SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02 SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1 +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB12_13_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB12_13_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB12_13_MSK SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04 SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2 -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB15_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB15_ST_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB15_CTL -SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB15_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB12_ST_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB12_CTL +SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB12_ST_CTL SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07 -SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB15_MSK_ACTL -SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB15_MSK +SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB12_MSK_ACTL +SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB12_MSK ; SCSI_Glitch_Ctl SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01 SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0 -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_14_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB13_14_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB13_14_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB13_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB13_ST_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB13_CTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB13_ST_CTL SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01 -SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL -SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK +SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB13_MSK_ACTL +SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK ; SCSI_Parity_Error SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01 SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0 -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL -SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB14_15_ST +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL +SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01 -SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB14_MSK -SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL -SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB14_ST +SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK +SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL +SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST ; Miscellaneous BCLK__BUS_CLK__HZ EQU 50000000 diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.c new file mode 100644 index 0000000..2daa12c --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: nNOR_CS.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "nNOR_CS.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + nNOR_CS__PORT == 15 && ((nNOR_CS__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: nNOR_CS_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet nNOR_CS_SUT.c usage_nNOR_CS_Write +*******************************************************************************/ +void nNOR_CS_Write(uint8 value) +{ + uint8 staticBits = (nNOR_CS_DR & (uint8)(~nNOR_CS_MASK)); + nNOR_CS_DR = staticBits | ((uint8)(value << nNOR_CS_SHIFT) & nNOR_CS_MASK); +} + + +/******************************************************************************* +* Function Name: nNOR_CS_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet nNOR_CS_SUT.c usage_nNOR_CS_SetDriveMode +*******************************************************************************/ +void nNOR_CS_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(nNOR_CS_0, mode); +} + + +/******************************************************************************* +* Function Name: nNOR_CS_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet nNOR_CS_SUT.c usage_nNOR_CS_Read +*******************************************************************************/ +uint8 nNOR_CS_Read(void) +{ + return (nNOR_CS_PS & nNOR_CS_MASK) >> nNOR_CS_SHIFT; +} + + +/******************************************************************************* +* Function Name: nNOR_CS_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred nNOR_CS_Read() API because the +* nNOR_CS_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet nNOR_CS_SUT.c usage_nNOR_CS_ReadDataReg +*******************************************************************************/ +uint8 nNOR_CS_ReadDataReg(void) +{ + return (nNOR_CS_DR & nNOR_CS_MASK) >> nNOR_CS_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(nNOR_CS_INTSTAT) + + /******************************************************************************* + * Function Name: nNOR_CS_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use nNOR_CS_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - nNOR_CS_0_INTR (First pin in the list) + * - nNOR_CS_1_INTR (Second pin in the list) + * - ... + * - nNOR_CS_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet nNOR_CS_SUT.c usage_nNOR_CS_SetInterruptMode + *******************************************************************************/ + void nNOR_CS_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & nNOR_CS_0_INTR) != 0u) + { + nNOR_CS_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: nNOR_CS_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet nNOR_CS_SUT.c usage_nNOR_CS_ClearInterrupt + *******************************************************************************/ + uint8 nNOR_CS_ClearInterrupt(void) + { + return (nNOR_CS_INTSTAT & nNOR_CS_MASK) >> nNOR_CS_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.h new file mode 100644 index 0000000..f5662d0 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: nNOR_CS.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_CS_H) /* Pins nNOR_CS_H */ +#define CY_PINS_nNOR_CS_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "nNOR_CS_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + nNOR_CS__PORT == 15 && ((nNOR_CS__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void nNOR_CS_Write(uint8 value); +void nNOR_CS_SetDriveMode(uint8 mode); +uint8 nNOR_CS_ReadDataReg(void); +uint8 nNOR_CS_Read(void); +void nNOR_CS_SetInterruptMode(uint16 position, uint16 mode); +uint8 nNOR_CS_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the nNOR_CS_SetDriveMode() function. + * @{ + */ + #define nNOR_CS_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define nNOR_CS_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define nNOR_CS_DM_RES_UP PIN_DM_RES_UP + #define nNOR_CS_DM_RES_DWN PIN_DM_RES_DWN + #define nNOR_CS_DM_OD_LO PIN_DM_OD_LO + #define nNOR_CS_DM_OD_HI PIN_DM_OD_HI + #define nNOR_CS_DM_STRONG PIN_DM_STRONG + #define nNOR_CS_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define nNOR_CS_MASK nNOR_CS__MASK +#define nNOR_CS_SHIFT nNOR_CS__SHIFT +#define nNOR_CS_WIDTH 1u + +/* Interrupt constants */ +#if defined(nNOR_CS__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in nNOR_CS_SetInterruptMode() function. + * @{ + */ + #define nNOR_CS_INTR_NONE (uint16)(0x0000u) + #define nNOR_CS_INTR_RISING (uint16)(0x0001u) + #define nNOR_CS_INTR_FALLING (uint16)(0x0002u) + #define nNOR_CS_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define nNOR_CS_INTR_MASK (0x01u) +#endif /* (nNOR_CS__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define nNOR_CS_PS (* (reg8 *) nNOR_CS__PS) +/* Data Register */ +#define nNOR_CS_DR (* (reg8 *) nNOR_CS__DR) +/* Port Number */ +#define nNOR_CS_PRT_NUM (* (reg8 *) nNOR_CS__PRT) +/* Connect to Analog Globals */ +#define nNOR_CS_AG (* (reg8 *) nNOR_CS__AG) +/* Analog MUX bux enable */ +#define nNOR_CS_AMUX (* (reg8 *) nNOR_CS__AMUX) +/* Bidirectional Enable */ +#define nNOR_CS_BIE (* (reg8 *) nNOR_CS__BIE) +/* Bit-mask for Aliased Register Access */ +#define nNOR_CS_BIT_MASK (* (reg8 *) nNOR_CS__BIT_MASK) +/* Bypass Enable */ +#define nNOR_CS_BYP (* (reg8 *) nNOR_CS__BYP) +/* Port wide control signals */ +#define nNOR_CS_CTL (* (reg8 *) nNOR_CS__CTL) +/* Drive Modes */ +#define nNOR_CS_DM0 (* (reg8 *) nNOR_CS__DM0) +#define nNOR_CS_DM1 (* (reg8 *) nNOR_CS__DM1) +#define nNOR_CS_DM2 (* (reg8 *) nNOR_CS__DM2) +/* Input Buffer Disable Override */ +#define nNOR_CS_INP_DIS (* (reg8 *) nNOR_CS__INP_DIS) +/* LCD Common or Segment Drive */ +#define nNOR_CS_LCD_COM_SEG (* (reg8 *) nNOR_CS__LCD_COM_SEG) +/* Enable Segment LCD */ +#define nNOR_CS_LCD_EN (* (reg8 *) nNOR_CS__LCD_EN) +/* Slew Rate Control */ +#define nNOR_CS_SLW (* (reg8 *) nNOR_CS__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define nNOR_CS_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_CS__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define nNOR_CS_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_CS__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define nNOR_CS_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_CS__PRTDSI__OE_SEL0) +#define nNOR_CS_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_CS__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define nNOR_CS_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_CS__PRTDSI__OUT_SEL0) +#define nNOR_CS_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_CS__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define nNOR_CS_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_CS__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(nNOR_CS__SIO_CFG) + #define nNOR_CS_SIO_HYST_EN (* (reg8 *) nNOR_CS__SIO_HYST_EN) + #define nNOR_CS_SIO_REG_HIFREQ (* (reg8 *) nNOR_CS__SIO_REG_HIFREQ) + #define nNOR_CS_SIO_CFG (* (reg8 *) nNOR_CS__SIO_CFG) + #define nNOR_CS_SIO_DIFF (* (reg8 *) nNOR_CS__SIO_DIFF) +#endif /* (nNOR_CS__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(nNOR_CS__INTSTAT) + #define nNOR_CS_INTSTAT (* (reg8 *) nNOR_CS__INTSTAT) + #define nNOR_CS_SNAP (* (reg8 *) nNOR_CS__SNAP) + + #define nNOR_CS_0_INTTYPE_REG (* (reg8 *) nNOR_CS__0__INTTYPE) +#endif /* (nNOR_CS__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_nNOR_CS_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS_aliases.h new file mode 100644 index 0000000..d5cf164 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_CS_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: nNOR_CS.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_CS_ALIASES_H) /* Pins nNOR_CS_ALIASES_H */ +#define CY_PINS_nNOR_CS_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define nNOR_CS_0 (nNOR_CS__0__PC) +#define nNOR_CS_0_INTR ((uint16)((uint16)0x0001u << nNOR_CS__0__SHIFT)) + +#define nNOR_CS_INTR_ALL ((uint16)(nNOR_CS_0_INTR)) + +#endif /* End Pins nNOR_CS_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.c new file mode 100644 index 0000000..e78dbdd --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: nNOR_HOLD.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "nNOR_HOLD.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + nNOR_HOLD__PORT == 15 && ((nNOR_HOLD__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: nNOR_HOLD_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_Write +*******************************************************************************/ +void nNOR_HOLD_Write(uint8 value) +{ + uint8 staticBits = (nNOR_HOLD_DR & (uint8)(~nNOR_HOLD_MASK)); + nNOR_HOLD_DR = staticBits | ((uint8)(value << nNOR_HOLD_SHIFT) & nNOR_HOLD_MASK); +} + + +/******************************************************************************* +* Function Name: nNOR_HOLD_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_SetDriveMode +*******************************************************************************/ +void nNOR_HOLD_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(nNOR_HOLD_0, mode); +} + + +/******************************************************************************* +* Function Name: nNOR_HOLD_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_Read +*******************************************************************************/ +uint8 nNOR_HOLD_Read(void) +{ + return (nNOR_HOLD_PS & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT; +} + + +/******************************************************************************* +* Function Name: nNOR_HOLD_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred nNOR_HOLD_Read() API because the +* nNOR_HOLD_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_ReadDataReg +*******************************************************************************/ +uint8 nNOR_HOLD_ReadDataReg(void) +{ + return (nNOR_HOLD_DR & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(nNOR_HOLD_INTSTAT) + + /******************************************************************************* + * Function Name: nNOR_HOLD_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use nNOR_HOLD_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - nNOR_HOLD_0_INTR (First pin in the list) + * - nNOR_HOLD_1_INTR (Second pin in the list) + * - ... + * - nNOR_HOLD_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_SetInterruptMode + *******************************************************************************/ + void nNOR_HOLD_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & nNOR_HOLD_0_INTR) != 0u) + { + nNOR_HOLD_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: nNOR_HOLD_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet nNOR_HOLD_SUT.c usage_nNOR_HOLD_ClearInterrupt + *******************************************************************************/ + uint8 nNOR_HOLD_ClearInterrupt(void) + { + return (nNOR_HOLD_INTSTAT & nNOR_HOLD_MASK) >> nNOR_HOLD_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.h new file mode 100644 index 0000000..c75b8ee --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: nNOR_HOLD.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_HOLD_H) /* Pins nNOR_HOLD_H */ +#define CY_PINS_nNOR_HOLD_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "nNOR_HOLD_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + nNOR_HOLD__PORT == 15 && ((nNOR_HOLD__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void nNOR_HOLD_Write(uint8 value); +void nNOR_HOLD_SetDriveMode(uint8 mode); +uint8 nNOR_HOLD_ReadDataReg(void); +uint8 nNOR_HOLD_Read(void); +void nNOR_HOLD_SetInterruptMode(uint16 position, uint16 mode); +uint8 nNOR_HOLD_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the nNOR_HOLD_SetDriveMode() function. + * @{ + */ + #define nNOR_HOLD_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define nNOR_HOLD_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define nNOR_HOLD_DM_RES_UP PIN_DM_RES_UP + #define nNOR_HOLD_DM_RES_DWN PIN_DM_RES_DWN + #define nNOR_HOLD_DM_OD_LO PIN_DM_OD_LO + #define nNOR_HOLD_DM_OD_HI PIN_DM_OD_HI + #define nNOR_HOLD_DM_STRONG PIN_DM_STRONG + #define nNOR_HOLD_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define nNOR_HOLD_MASK nNOR_HOLD__MASK +#define nNOR_HOLD_SHIFT nNOR_HOLD__SHIFT +#define nNOR_HOLD_WIDTH 1u + +/* Interrupt constants */ +#if defined(nNOR_HOLD__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in nNOR_HOLD_SetInterruptMode() function. + * @{ + */ + #define nNOR_HOLD_INTR_NONE (uint16)(0x0000u) + #define nNOR_HOLD_INTR_RISING (uint16)(0x0001u) + #define nNOR_HOLD_INTR_FALLING (uint16)(0x0002u) + #define nNOR_HOLD_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define nNOR_HOLD_INTR_MASK (0x01u) +#endif /* (nNOR_HOLD__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define nNOR_HOLD_PS (* (reg8 *) nNOR_HOLD__PS) +/* Data Register */ +#define nNOR_HOLD_DR (* (reg8 *) nNOR_HOLD__DR) +/* Port Number */ +#define nNOR_HOLD_PRT_NUM (* (reg8 *) nNOR_HOLD__PRT) +/* Connect to Analog Globals */ +#define nNOR_HOLD_AG (* (reg8 *) nNOR_HOLD__AG) +/* Analog MUX bux enable */ +#define nNOR_HOLD_AMUX (* (reg8 *) nNOR_HOLD__AMUX) +/* Bidirectional Enable */ +#define nNOR_HOLD_BIE (* (reg8 *) nNOR_HOLD__BIE) +/* Bit-mask for Aliased Register Access */ +#define nNOR_HOLD_BIT_MASK (* (reg8 *) nNOR_HOLD__BIT_MASK) +/* Bypass Enable */ +#define nNOR_HOLD_BYP (* (reg8 *) nNOR_HOLD__BYP) +/* Port wide control signals */ +#define nNOR_HOLD_CTL (* (reg8 *) nNOR_HOLD__CTL) +/* Drive Modes */ +#define nNOR_HOLD_DM0 (* (reg8 *) nNOR_HOLD__DM0) +#define nNOR_HOLD_DM1 (* (reg8 *) nNOR_HOLD__DM1) +#define nNOR_HOLD_DM2 (* (reg8 *) nNOR_HOLD__DM2) +/* Input Buffer Disable Override */ +#define nNOR_HOLD_INP_DIS (* (reg8 *) nNOR_HOLD__INP_DIS) +/* LCD Common or Segment Drive */ +#define nNOR_HOLD_LCD_COM_SEG (* (reg8 *) nNOR_HOLD__LCD_COM_SEG) +/* Enable Segment LCD */ +#define nNOR_HOLD_LCD_EN (* (reg8 *) nNOR_HOLD__LCD_EN) +/* Slew Rate Control */ +#define nNOR_HOLD_SLW (* (reg8 *) nNOR_HOLD__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define nNOR_HOLD_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_HOLD__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define nNOR_HOLD_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_HOLD__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define nNOR_HOLD_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_HOLD__PRTDSI__OE_SEL0) +#define nNOR_HOLD_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_HOLD__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define nNOR_HOLD_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_HOLD__PRTDSI__OUT_SEL0) +#define nNOR_HOLD_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_HOLD__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define nNOR_HOLD_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_HOLD__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(nNOR_HOLD__SIO_CFG) + #define nNOR_HOLD_SIO_HYST_EN (* (reg8 *) nNOR_HOLD__SIO_HYST_EN) + #define nNOR_HOLD_SIO_REG_HIFREQ (* (reg8 *) nNOR_HOLD__SIO_REG_HIFREQ) + #define nNOR_HOLD_SIO_CFG (* (reg8 *) nNOR_HOLD__SIO_CFG) + #define nNOR_HOLD_SIO_DIFF (* (reg8 *) nNOR_HOLD__SIO_DIFF) +#endif /* (nNOR_HOLD__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(nNOR_HOLD__INTSTAT) + #define nNOR_HOLD_INTSTAT (* (reg8 *) nNOR_HOLD__INTSTAT) + #define nNOR_HOLD_SNAP (* (reg8 *) nNOR_HOLD__SNAP) + + #define nNOR_HOLD_0_INTTYPE_REG (* (reg8 *) nNOR_HOLD__0__INTTYPE) +#endif /* (nNOR_HOLD__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_nNOR_HOLD_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD_aliases.h new file mode 100644 index 0000000..ecd6798 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_HOLD_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: nNOR_HOLD.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_HOLD_ALIASES_H) /* Pins nNOR_HOLD_ALIASES_H */ +#define CY_PINS_nNOR_HOLD_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define nNOR_HOLD_0 (nNOR_HOLD__0__PC) +#define nNOR_HOLD_0_INTR ((uint16)((uint16)0x0001u << nNOR_HOLD__0__SHIFT)) + +#define nNOR_HOLD_INTR_ALL ((uint16)(nNOR_HOLD_0_INTR)) + +#endif /* End Pins nNOR_HOLD_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.c b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.c new file mode 100644 index 0000000..a5c18bc --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.c @@ -0,0 +1,226 @@ +/******************************************************************************* +* File Name: nNOR_WP.c +* Version 2.20 +* +* Description: +* This file contains API to enable firmware control of a Pins component. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#include "cytypes.h" +#include "nNOR_WP.h" + +/* APIs are not generated for P15[7:6] on PSoC 5 */ +#if !(CY_PSOC5A &&\ + nNOR_WP__PORT == 15 && ((nNOR_WP__MASK & 0xC0) != 0)) + + +/******************************************************************************* +* Function Name: nNOR_WP_Write +****************************************************************************//** +* +* \brief Writes the value to the physical port (data output register), masking +* and shifting the bits appropriately. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This function avoids changing +* other bits in the port by using the appropriate method (read-modify-write or +* bit banding). +* +* Note This function should not be used on a hardware digital output pin +* as it is driven by the hardware signal attached to it. +* +* \param value +* Value to write to the component instance. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic; the Interrupt +* Service Routines (ISR) can cause corruption of this function. An ISR that +* interrupts this function and performs writes to the Pins component data +* register can cause corrupted port data. To avoid this issue, you should +* either use the Per-Pin APIs (primary method) or disable interrupts around +* this function. +* +* \funcusage +* \snippet nNOR_WP_SUT.c usage_nNOR_WP_Write +*******************************************************************************/ +void nNOR_WP_Write(uint8 value) +{ + uint8 staticBits = (nNOR_WP_DR & (uint8)(~nNOR_WP_MASK)); + nNOR_WP_DR = staticBits | ((uint8)(value << nNOR_WP_SHIFT) & nNOR_WP_MASK); +} + + +/******************************************************************************* +* Function Name: nNOR_WP_SetDriveMode +****************************************************************************//** +* +* \brief Sets the drive mode for each of the Pins component's pins. +* +* Note This affects all pins in the Pins component instance. Use the +* Per-Pin APIs if you wish to control individual pin's drive modes. +* +* \param mode +* Mode for the selected signals. Valid options are documented in +* \ref driveMode. +* +* \return +* None +* +* \sideeffect +* If you use read-modify-write operations that are not atomic, the ISR can +* cause corruption of this function. An ISR that interrupts this function +* and performs writes to the Pins component Drive Mode registers can cause +* corrupted port data. To avoid this issue, you should either use the Per-Pin +* APIs (primary method) or disable interrupts around this function. +* +* \funcusage +* \snippet nNOR_WP_SUT.c usage_nNOR_WP_SetDriveMode +*******************************************************************************/ +void nNOR_WP_SetDriveMode(uint8 mode) +{ + CyPins_SetPinDriveMode(nNOR_WP_0, mode); +} + + +/******************************************************************************* +* Function Name: nNOR_WP_Read +****************************************************************************//** +* +* \brief Reads the associated physical port (pin status register) and masks +* the required bits according to the width and bit position of the component +* instance. +* +* The pin's status register returns the current logic level present on the +* physical pin. +* +* \return +* The current value for the pins in the component as a right justified number. +* +* \funcusage +* \snippet nNOR_WP_SUT.c usage_nNOR_WP_Read +*******************************************************************************/ +uint8 nNOR_WP_Read(void) +{ + return (nNOR_WP_PS & nNOR_WP_MASK) >> nNOR_WP_SHIFT; +} + + +/******************************************************************************* +* Function Name: nNOR_WP_ReadDataReg +****************************************************************************//** +* +* \brief Reads the associated physical port's data output register and masks +* the correct bits according to the width and bit position of the component +* instance. +* +* The data output register controls the signal applied to the physical pin in +* conjunction with the drive mode parameter. This is not the same as the +* preferred nNOR_WP_Read() API because the +* nNOR_WP_ReadDataReg() reads the data register instead of the status +* register. For output pins this is a useful function to determine the value +* just written to the pin. +* +* \return +* The current value of the data register masked and shifted into a right +* justified number for the component instance. +* +* \funcusage +* \snippet nNOR_WP_SUT.c usage_nNOR_WP_ReadDataReg +*******************************************************************************/ +uint8 nNOR_WP_ReadDataReg(void) +{ + return (nNOR_WP_DR & nNOR_WP_MASK) >> nNOR_WP_SHIFT; +} + + +/* If interrupt is connected for this Pins component */ +#if defined(nNOR_WP_INTSTAT) + + /******************************************************************************* + * Function Name: nNOR_WP_SetInterruptMode + ****************************************************************************//** + * + * \brief Configures the interrupt mode for each of the Pins component's + * pins. Alternatively you may set the interrupt mode for all the pins + * specified in the Pins component. + * + * Note The interrupt is port-wide and therefore any enabled pin + * interrupt may trigger it. + * + * \param position + * The pin position as listed in the Pins component. You may OR these to be + * able to configure the interrupt mode of multiple pins within a Pins + * component. Or you may use nNOR_WP_INTR_ALL to configure the + * interrupt mode of all the pins in the Pins component. + * - nNOR_WP_0_INTR (First pin in the list) + * - nNOR_WP_1_INTR (Second pin in the list) + * - ... + * - nNOR_WP_INTR_ALL (All pins in Pins component) + * + * \param mode + * Interrupt mode for the selected pins. Valid options are documented in + * \ref intrMode. + * + * \return + * None + * + * \sideeffect + * It is recommended that the interrupt be disabled before calling this + * function to avoid unintended interrupt requests. Note that the interrupt + * type is port wide, and therefore will trigger for any enabled pin on the + * port. + * + * \funcusage + * \snippet nNOR_WP_SUT.c usage_nNOR_WP_SetInterruptMode + *******************************************************************************/ + void nNOR_WP_SetInterruptMode(uint16 position, uint16 mode) + { + if((position & nNOR_WP_0_INTR) != 0u) + { + nNOR_WP_0_INTTYPE_REG = (uint8)mode; + } + } + + + /******************************************************************************* + * Function Name: nNOR_WP_ClearInterrupt + ****************************************************************************//** + * + * \brief Clears any active interrupts attached with the component and returns + * the value of the interrupt status register allowing determination of which + * pins generated an interrupt event. + * + * \return + * The right-shifted current value of the interrupt status register. Each pin + * has one bit set if it generated an interrupt event. For example, bit 0 is + * for pin 0 and bit 1 is for pin 1 of the Pins component. + * + * \sideeffect + * Clears all bits of the physical port's interrupt status register, not just + * those associated with the Pins component. + * + * \funcusage + * \snippet nNOR_WP_SUT.c usage_nNOR_WP_ClearInterrupt + *******************************************************************************/ + uint8 nNOR_WP_ClearInterrupt(void) + { + return (nNOR_WP_INTSTAT & nNOR_WP_MASK) >> nNOR_WP_SHIFT; + } + +#endif /* If Interrupts Are Enabled for this Pins component */ + +#endif /* CY_PSOC5A... */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.h new file mode 100644 index 0000000..1baacb3 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP.h @@ -0,0 +1,165 @@ +/******************************************************************************* +* File Name: nNOR_WP.h +* Version 2.20 +* +* Description: +* This file contains Pin function prototypes and register defines +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_WP_H) /* Pins nNOR_WP_H */ +#define CY_PINS_nNOR_WP_H + +#include "cytypes.h" +#include "cyfitter.h" +#include "cypins.h" +#include "nNOR_WP_aliases.h" + +/* APIs are not generated for P15[7:6] */ +#if !(CY_PSOC5A &&\ + nNOR_WP__PORT == 15 && ((nNOR_WP__MASK & 0xC0) != 0)) + + +/*************************************** +* Function Prototypes +***************************************/ + +/** +* \addtogroup group_general +* @{ +*/ +void nNOR_WP_Write(uint8 value); +void nNOR_WP_SetDriveMode(uint8 mode); +uint8 nNOR_WP_ReadDataReg(void); +uint8 nNOR_WP_Read(void); +void nNOR_WP_SetInterruptMode(uint16 position, uint16 mode); +uint8 nNOR_WP_ClearInterrupt(void); +/** @} general */ + +/*************************************** +* API Constants +***************************************/ +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup driveMode Drive mode constants + * \brief Constants to be passed as "mode" parameter in the nNOR_WP_SetDriveMode() function. + * @{ + */ + #define nNOR_WP_DM_ALG_HIZ PIN_DM_ALG_HIZ + #define nNOR_WP_DM_DIG_HIZ PIN_DM_DIG_HIZ + #define nNOR_WP_DM_RES_UP PIN_DM_RES_UP + #define nNOR_WP_DM_RES_DWN PIN_DM_RES_DWN + #define nNOR_WP_DM_OD_LO PIN_DM_OD_LO + #define nNOR_WP_DM_OD_HI PIN_DM_OD_HI + #define nNOR_WP_DM_STRONG PIN_DM_STRONG + #define nNOR_WP_DM_RES_UPDWN PIN_DM_RES_UPDWN + /** @} driveMode */ +/** @} group_constants */ + +/* Digital Port Constants */ +#define nNOR_WP_MASK nNOR_WP__MASK +#define nNOR_WP_SHIFT nNOR_WP__SHIFT +#define nNOR_WP_WIDTH 1u + +/* Interrupt constants */ +#if defined(nNOR_WP__INTSTAT) +/** +* \addtogroup group_constants +* @{ +*/ + /** \addtogroup intrMode Interrupt constants + * \brief Constants to be passed as "mode" parameter in nNOR_WP_SetInterruptMode() function. + * @{ + */ + #define nNOR_WP_INTR_NONE (uint16)(0x0000u) + #define nNOR_WP_INTR_RISING (uint16)(0x0001u) + #define nNOR_WP_INTR_FALLING (uint16)(0x0002u) + #define nNOR_WP_INTR_BOTH (uint16)(0x0003u) + /** @} intrMode */ +/** @} group_constants */ + + #define nNOR_WP_INTR_MASK (0x01u) +#endif /* (nNOR_WP__INTSTAT) */ + + +/*************************************** +* Registers +***************************************/ + +/* Main Port Registers */ +/* Pin State */ +#define nNOR_WP_PS (* (reg8 *) nNOR_WP__PS) +/* Data Register */ +#define nNOR_WP_DR (* (reg8 *) nNOR_WP__DR) +/* Port Number */ +#define nNOR_WP_PRT_NUM (* (reg8 *) nNOR_WP__PRT) +/* Connect to Analog Globals */ +#define nNOR_WP_AG (* (reg8 *) nNOR_WP__AG) +/* Analog MUX bux enable */ +#define nNOR_WP_AMUX (* (reg8 *) nNOR_WP__AMUX) +/* Bidirectional Enable */ +#define nNOR_WP_BIE (* (reg8 *) nNOR_WP__BIE) +/* Bit-mask for Aliased Register Access */ +#define nNOR_WP_BIT_MASK (* (reg8 *) nNOR_WP__BIT_MASK) +/* Bypass Enable */ +#define nNOR_WP_BYP (* (reg8 *) nNOR_WP__BYP) +/* Port wide control signals */ +#define nNOR_WP_CTL (* (reg8 *) nNOR_WP__CTL) +/* Drive Modes */ +#define nNOR_WP_DM0 (* (reg8 *) nNOR_WP__DM0) +#define nNOR_WP_DM1 (* (reg8 *) nNOR_WP__DM1) +#define nNOR_WP_DM2 (* (reg8 *) nNOR_WP__DM2) +/* Input Buffer Disable Override */ +#define nNOR_WP_INP_DIS (* (reg8 *) nNOR_WP__INP_DIS) +/* LCD Common or Segment Drive */ +#define nNOR_WP_LCD_COM_SEG (* (reg8 *) nNOR_WP__LCD_COM_SEG) +/* Enable Segment LCD */ +#define nNOR_WP_LCD_EN (* (reg8 *) nNOR_WP__LCD_EN) +/* Slew Rate Control */ +#define nNOR_WP_SLW (* (reg8 *) nNOR_WP__SLW) + +/* DSI Port Registers */ +/* Global DSI Select Register */ +#define nNOR_WP_PRTDSI__CAPS_SEL (* (reg8 *) nNOR_WP__PRTDSI__CAPS_SEL) +/* Double Sync Enable */ +#define nNOR_WP_PRTDSI__DBL_SYNC_IN (* (reg8 *) nNOR_WP__PRTDSI__DBL_SYNC_IN) +/* Output Enable Select Drive Strength */ +#define nNOR_WP_PRTDSI__OE_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL0) +#define nNOR_WP_PRTDSI__OE_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OE_SEL1) +/* Port Pin Output Select Registers */ +#define nNOR_WP_PRTDSI__OUT_SEL0 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL0) +#define nNOR_WP_PRTDSI__OUT_SEL1 (* (reg8 *) nNOR_WP__PRTDSI__OUT_SEL1) +/* Sync Output Enable Registers */ +#define nNOR_WP_PRTDSI__SYNC_OUT (* (reg8 *) nNOR_WP__PRTDSI__SYNC_OUT) + +/* SIO registers */ +#if defined(nNOR_WP__SIO_CFG) + #define nNOR_WP_SIO_HYST_EN (* (reg8 *) nNOR_WP__SIO_HYST_EN) + #define nNOR_WP_SIO_REG_HIFREQ (* (reg8 *) nNOR_WP__SIO_REG_HIFREQ) + #define nNOR_WP_SIO_CFG (* (reg8 *) nNOR_WP__SIO_CFG) + #define nNOR_WP_SIO_DIFF (* (reg8 *) nNOR_WP__SIO_DIFF) +#endif /* (nNOR_WP__SIO_CFG) */ + +/* Interrupt Registers */ +#if defined(nNOR_WP__INTSTAT) + #define nNOR_WP_INTSTAT (* (reg8 *) nNOR_WP__INTSTAT) + #define nNOR_WP_SNAP (* (reg8 *) nNOR_WP__SNAP) + + #define nNOR_WP_0_INTTYPE_REG (* (reg8 *) nNOR_WP__0__INTTYPE) +#endif /* (nNOR_WP__INTSTAT) */ + +#endif /* CY_PSOC5A... */ + +#endif /* CY_PINS_nNOR_WP_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP_aliases.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP_aliases.h new file mode 100644 index 0000000..d9c2f02 --- /dev/null +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/nNOR_WP_aliases.h @@ -0,0 +1,36 @@ +/******************************************************************************* +* File Name: nNOR_WP.h +* Version 2.20 +* +* Description: +* This file contains the Alias definitions for Per-Pin APIs in cypins.h. +* Information on using these APIs can be found in the System Reference Guide. +* +* Note: +* +******************************************************************************** +* Copyright 2008-2015, Cypress Semiconductor Corporation. All rights reserved. +* You may use this file only in accordance with the license, terms, conditions, +* disclaimers, and limitations in the end user license agreement accompanying +* the software package with which this file was provided. +*******************************************************************************/ + +#if !defined(CY_PINS_nNOR_WP_ALIASES_H) /* Pins nNOR_WP_ALIASES_H */ +#define CY_PINS_nNOR_WP_ALIASES_H + +#include "cytypes.h" +#include "cyfitter.h" + + +/*************************************** +* Constants +***************************************/ +#define nNOR_WP_0 (nNOR_WP__0__PC) +#define nNOR_WP_0_INTR ((uint16)((uint16)0x0001u << nNOR_WP__0__SHIFT)) + +#define nNOR_WP_INTR_ALL ((uint16)(nNOR_WP_0_INTR)) + +#endif /* End Pins nNOR_WP_ALIASES_H */ + + +/* [] END OF FILE */ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h index e00c8c0..fde38ec 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h @@ -70,10 +70,22 @@ #include "SCSI_Glitch_Ctl.h" #include "TERM_EN_aliases.h" #include "TERM_EN.h" -#include "SPI_Pullups_aliases.h" -#include "SPI_Pullups.h" -#include "SPI_Pullups_1_aliases.h" -#include "SPI_Pullups_1.h" +#include "NOR_Clock.h" +#include "NOR_SO_aliases.h" +#include "NOR_SO.h" +#include "NOR_SPI.h" +#include "NOR_SPI_PVT.h" +#include "NOR_SCK_aliases.h" +#include "NOR_SCK.h" +#include "nNOR_HOLD_aliases.h" +#include "nNOR_HOLD.h" +#include "NOR_SI_aliases.h" +#include "NOR_SI.h" +#include "NOR_CTL.h" +#include "nNOR_CS_aliases.h" +#include "nNOR_CS.h" +#include "nNOR_WP_aliases.h" +#include "nNOR_WP.h" #include "USBFS_Dm_aliases.h" #include "USBFS_Dm.h" #include "USBFS_Dp_aliases.h" diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx index 0fb7619..d68d1f5 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cycdx @@ -1,49 +1,20 @@ - \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr index 47e0e7f..19736fe 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cydwr @@ -529,26 +529,31 @@ - + + + + + + @@ -3688,7 +3693,7 @@ - + @@ -3793,6 +3798,11 @@ + + + + + @@ -3816,6 +3826,11 @@ + + + + + @@ -3837,6 +3852,11 @@ + + + + + @@ -3879,6 +3899,11 @@ + + + + + @@ -3889,6 +3914,11 @@ + + + + + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit index c125153..c3ea79e 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyfit differ diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj index 2a622b3..b52eef2 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.cyprj @@ -2232,27 +2232,27 @@ - + - + - + - + @@ -2265,26 +2265,330 @@ - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd index 510c132..9c0eed5 100644 --- a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd +++ b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/SCSI2SD.svd @@ -7,7 +7,7 @@ 32 - SCSI_Filtered + SCSI_Glitch_Ctl No description available 0x0 @@ -17,148 +17,14 @@ - SCSI_Filtered_STATUS_REG + SCSI_Glitch_Ctl_CONTROL_REG No description available - 0x40006467 + 0x4000647D 8 read-write 0 0 - - SCSI_Filtered_MASK_REG - No description available - 0x40006487 - 8 - read-write - 0 - 0 - - - SCSI_Filtered_STATUS_AUX_CTL_REG - No description available - 0x40006497 - 8 - read-write - 0 - 0 - - - FIFO0 - FIFO0 clear - 5 - 5 - read-write - - - ENABLED - Enable counter - 1 - - - DISABLED - Disable counter - 0 - - - - - INTRENBL - Enables or disables the Interrupt - 4 - 4 - read-write - - - ENABLED - Interrupt enabled - 1 - - - DISABLED - Interrupt disabled - 0 - - - - - FIFO1LEVEL - FIFO level - 3 - 3 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO0LEVEL - FIFO level - 2 - 2 - read-write - - - ENABLED - FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full - 1 - - - DISABLED - FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty - 0 - - - - - FIFO1CLEAR - FIFO clear - 1 - 1 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - FIFO0CLEAR - FIFO clear - 0 - 0 - read-write - - - ENABLED - Clear FIFO state - 1 - - - DISABLED - Normal FIFO operation - 0 - - - - - @@ -174,7 +40,7 @@ SCSI_Parity_Error_STATUS_REG No description available - 0x4000646E + 0x4000646B 8 read-write 0 @@ -183,7 +49,7 @@ SCSI_Parity_Error_MASK_REG No description available - 0x4000648E + 0x4000648B 8 read-write 0 @@ -192,7 +58,7 @@ SCSI_Parity_Error_STATUS_AUX_CTL_REG No description available - 0x4000649E + 0x4000649B 8 read-write 0 @@ -317,7 +183,7 @@ - SCSI_Glitch_Ctl + SCSI_Filtered No description available 0x0 @@ -327,9 +193,164 @@ - SCSI_Glitch_Ctl_CONTROL_REG + SCSI_Filtered_STATUS_REG No description available - 0x40006473 + 0x4000646F + 8 + read-write + 0 + 0 + + + SCSI_Filtered_MASK_REG + No description available + 0x4000648F + 8 + read-write + 0 + 0 + + + SCSI_Filtered_STATUS_AUX_CTL_REG + No description available + 0x4000649F + 8 + read-write + 0 + 0 + + + FIFO0 + FIFO0 clear + 5 + 5 + read-write + + + ENABLED + Enable counter + 1 + + + DISABLED + Disable counter + 0 + + + + + INTRENBL + Enables or disables the Interrupt + 4 + 4 + read-write + + + ENABLED + Interrupt enabled + 1 + + + DISABLED + Interrupt disabled + 0 + + + + + FIFO1LEVEL + FIFO level + 3 + 3 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO0LEVEL + FIFO level + 2 + 2 + read-write + + + ENABLED + FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full + 1 + + + DISABLED + FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty + 0 + + + + + FIFO1CLEAR + FIFO clear + 1 + 1 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + FIFO0CLEAR + FIFO clear + 0 + 0 + read-write + + + ENABLED + Clear FIFO state + 1 + + + DISABLED + Normal FIFO operation + 0 + + + + + + + + + NOR_CTL + No description available + 0x0 + + 0 + 0x0 + registers + + + + NOR_CTL_CONTROL_REG + No description available + 0x40006576 8 read-write 0 @@ -350,341 +371,7 @@ SCSI_CTL_PHASE_CONTROL_REG No description available - 0x4000647F - 8 - read-write - 0 - 0 - - - - - Debug_Timer - No description available - 0x0 - - 0 - 0x0 - registers - - - - Debug_Timer_GLOBAL_ENABLE - PM.ACT.CFG - 0x400043A3 - 8 - read-write - 0 - 0 - - - en_timer - Enable timer/counters. - 0 - 3 - read-write - - - - - Debug_Timer_CONTROL - TMRx.CFG0 - 0x40004F00 - 8 - read-write - 0 - 0 - - - EN - Enables timer/comparator. - 0 - 0 - read-write - - - MODE - Mode. (0 = Timer; 1 = Comparator) - 1 - 1 - read-write - - - Timer - Timer mode. CNT/CMP register holds timer count value. - 0 - - - Comparator - Comparator mode. CNT/CMP register holds comparator threshold value. - 1 - - - - - ONESHOT - Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. - 2 - 2 - read-write - - - CMP_BUFF - Buffer compare register. Compare register updates only on timer terminal count. - 3 - 3 - read-write - - - INV - Invert sense of TIMEREN signal - 4 - 4 - read-write - - - DB - Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. - 5 - 5 - read-write - - - Timer - CMP and TC are output. - 0 - - - Deadband - PHI1 (instead of CMP) and PHI2 (instead of TC) are output. - 1 - - - - - DEADBAND_PERIOD - Deadband Period - 6 - 7 - read-write - - - - - Debug_Timer_CONTROL2 - TMRx.CFG1 - 0x40004F01 - 8 - read-write - 0 - 0 - - - IRQ_SEL - Irq selection. (0 = raw interrupts; 1 = status register interrupts) - 0 - 0 - read-write - - - FTC - First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. - 1 - 1 - read-write - - - Disable_FTC - Disable the single cycle pulse, which signifies the timer is starting. - 0 - - - Enable_FTC - Enable the single cycle pulse, which signifies the timer is starting. - 1 - - - - - DCOR - Disable Clear on Read (DCOR) of Status Register SR0. - 2 - 2 - read-write - - - DBMODE - Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). - 3 - 3 - read-write - - - CLK_BUS_EN_SEL - Digital Global Clock selection. - 4 - 6 - read-write - - - BUS_CLK_SEL - Bus Clock selection. - 7 - 7 - read-write - - - - - Debug_Timer_CONTROL3_ - TMRx.CFG2 - 0x40004F02 - 8 - read-write - 0 - 0 - - - TMR_CFG - Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ - 0 - 1 - read-write - - - Continuous - Timer runs while EN bit of CFG0 register is set to '1'. - 0 - - - Pulsewidth - Timer runs from positive to negative edge of TIMEREN. - 1 - - - Period - Timer runs from positive to positive edge of TIMEREN. - 2 - - - Irq - Timer runs until IRQ. - 3 - - - - - COD - Clear On Disable (COD). Clears or gates outputs to zero. - 2 - 2 - read-write - - - ROD - Reset On Disable (ROD). Resets internal state of output logic - 3 - 3 - read-write - - - CMP_CFG - Comparator configurations - 4 - 6 - read-write - - - Equal - Compare Equal - 0 - - - Less_than - Compare Less Than - 1 - - - Less_than_or_equal - Compare Less Than or Equal . - 2 - - - Greater - Compare Greater Than . - 3 - - - Greater_than_or_equal - Compare Greater Than or Equal - 4 - - - - - HW_EN - When set Timer Enable controls counting. - 7 - 7 - read-write - - - - - Debug_Timer_PERIOD - TMRx.PER0 - Assigned Period - 0x40004F04 - 16 - read-write - 0 - 0 - - - Debug_Timer_COUNTER - TMRx.CNT_CMP0 - Current Down Counter Value - 0x40004F06 - 16 - read-write - 0 - 0 - - - - - SCSI_Out_Ctl - No description available - 0x0 - - 0 - 0x0 - registers - - - - SCSI_Out_Ctl_CONTROL_REG - No description available - 0x40006476 - 8 - read-write - 0 - 0 - - - - - SCSI_Out_Bits - No description available - 0x0 - - 0 - 0x0 - registers - - - - SCSI_Out_Bits_CONTROL_REG - No description available - 0x4000647D + 0x4000647C 8 read-write 0 @@ -2930,5 +2617,339 @@ + + SCSI_Out_Ctl + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Ctl_CONTROL_REG + No description available + 0x40006473 + 8 + read-write + 0 + 0 + + + + + Debug_Timer + No description available + 0x0 + + 0 + 0x0 + registers + + + + Debug_Timer_GLOBAL_ENABLE + PM.ACT.CFG + 0x400043A3 + 8 + read-write + 0 + 0 + + + en_timer + Enable timer/counters. + 0 + 3 + read-write + + + + + Debug_Timer_CONTROL + TMRx.CFG0 + 0x40004F00 + 8 + read-write + 0 + 0 + + + EN + Enables timer/comparator. + 0 + 0 + read-write + + + MODE + Mode. (0 = Timer; 1 = Comparator) + 1 + 1 + read-write + + + Timer + Timer mode. CNT/CMP register holds timer count value. + 0 + + + Comparator + Comparator mode. CNT/CMP register holds comparator threshold value. + 1 + + + + + ONESHOT + Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block. + 2 + 2 + read-write + + + CMP_BUFF + Buffer compare register. Compare register updates only on timer terminal count. + 3 + 3 + read-write + + + INV + Invert sense of TIMEREN signal + 4 + 4 + read-write + + + DB + Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively. + 5 + 5 + read-write + + + Timer + CMP and TC are output. + 0 + + + Deadband + PHI1 (instead of CMP) and PHI2 (instead of TC) are output. + 1 + + + + + DEADBAND_PERIOD + Deadband Period + 6 + 7 + read-write + + + + + Debug_Timer_CONTROL2 + TMRx.CFG1 + 0x40004F01 + 8 + read-write + 0 + 0 + + + IRQ_SEL + Irq selection. (0 = raw interrupts; 1 = status register interrupts) + 0 + 0 + read-write + + + FTC + First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled. + 1 + 1 + read-write + + + Disable_FTC + Disable the single cycle pulse, which signifies the timer is starting. + 0 + + + Enable_FTC + Enable the single cycle pulse, which signifies the timer is starting. + 1 + + + + + DCOR + Disable Clear on Read (DCOR) of Status Register SR0. + 2 + 2 + read-write + + + DBMODE + Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND). + 3 + 3 + read-write + + + CLK_BUS_EN_SEL + Digital Global Clock selection. + 4 + 6 + read-write + + + BUS_CLK_SEL + Bus Clock selection. + 7 + 7 + read-write + + + + + Debug_Timer_CONTROL3_ + TMRx.CFG2 + 0x40004F02 + 8 + read-write + 0 + 0 + + + TMR_CFG + Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ + 0 + 1 + read-write + + + Continuous + Timer runs while EN bit of CFG0 register is set to '1'. + 0 + + + Pulsewidth + Timer runs from positive to negative edge of TIMEREN. + 1 + + + Period + Timer runs from positive to positive edge of TIMEREN. + 2 + + + Irq + Timer runs until IRQ. + 3 + + + + + COD + Clear On Disable (COD). Clears or gates outputs to zero. + 2 + 2 + read-write + + + ROD + Reset On Disable (ROD). Resets internal state of output logic + 3 + 3 + read-write + + + CMP_CFG + Comparator configurations + 4 + 6 + read-write + + + Equal + Compare Equal + 0 + + + Less_than + Compare Less Than + 1 + + + Less_than_or_equal + Compare Less Than or Equal . + 2 + + + Greater + Compare Greater Than . + 3 + + + Greater_than_or_equal + Compare Greater Than or Equal + 4 + + + + + HW_EN + When set Timer Enable controls counting. + 7 + 7 + read-write + + + + + Debug_Timer_PERIOD + TMRx.PER0 - Assigned Period + 0x40004F04 + 16 + read-write + 0 + 0 + + + Debug_Timer_COUNTER + TMRx.CNT_CMP0 - Current Down Counter Value + 0x40004F06 + 16 + read-write + 0 + 0 + + + + + SCSI_Out_Bits + No description available + 0x0 + + 0 + 0x0 + registers + + + + SCSI_Out_Bits_CONTROL_REG + No description available + 0x40006479 + 8 + read-write + 0 + 0 + + + \ No newline at end of file diff --git a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch index fbbca47..e4871d0 100644 Binary files a/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v5.2/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ