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Write performance improvements.

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- Multi-sector SD card writes supported.
- Updated to PSoC Creator 3.0
This commit is contained in:
Michael McMaster 2013-10-14 22:24:04 +10:00
parent 27e482ea8c
commit cc6921e4ce
80 changed files with 20919 additions and 5217 deletions
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4
STATUS
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@ -9,7 +9,5 @@ assignments are incorrect.
- Partity checking is on
- Unit Attention Condition is off
- Write performance is not adequate
- Multi-sector SD commands are not yet supported.
- DMA is not used for SPI transfers
- DMA is not used for SPI transfers

14
readme.txt
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@ -42,10 +42,18 @@ Dimensions
Performance
As currently implemented:
Sequential read: 250kb/sec Sequential write: 50kb/sec
These numbers are dreadful. I am working on updating the slow polling SD card
communication to use DMA. I expect the performance to reach 1.8Mb/sec.
Sequential read: 250kb/sec Sequential write: 240kb/sec
Tested with a 16GB class 10 SD card, via the commands:
# WRITE TEST
sudo dd bs=8192 count=100 if=/dev/zero of=/dev/sdX oflag=dsync
# READ TEST
sudo dd bs=8192 count=100 if=/dev/sdX of=/dev/null
I am working on updating the slow polling SD card communication to use DMA. I expect the performance to reach 1Mb/sec.
Compatibility

113
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Iar.icf Normal file
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@ -0,0 +1,113 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 262144 - 1;
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000 - (65536 / 2);
define symbol __ICFEDIT_region_RAM_end__ = 0x20000000 + (65536 / 2) - 1;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x4000;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
/******** Definitions ********/
define symbol CY_APPL_LOADABLE = 0;
define symbol CY_APPL_LOADER = 0;
define symbol CY_APPL_NUM = 1;
define symbol CY_APPL_MAX = 1;
define symbol CY_METADATA_SIZE = 64;
define symbol CY_EE_IN_BTLDR = 0x0;
define symbol CY_EE_SIZE = 2048;
if (!CY_APPL_LOADABLE) {
define symbol CYDEV_BTLDR_SIZE = 0;
}
define symbol CY_FLASH_SIZE = 262144;
define symbol CY_APPL_ORIGIN = 0;
define symbol CY_FLASH_ROW_SIZE = 256;
define symbol CY_ECC_ROW_SIZE = 32;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
define block HSTACK {block HEAP, last block CSTACK};
define block LOADER { readonly section .cybootloader };
define block APPL with fixed order {readonly section .romvectors, readonly};
/* The address of Flash row next after Bootloader image */
define symbol CY_BTLDR_END = CYDEV_BTLDR_SIZE +
((CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE) ?
(CY_FLASH_ROW_SIZE - (CYDEV_BTLDR_SIZE % CY_FLASH_ROW_SIZE)) : 0);
/* The start address of Standard/Loader/Loadable#1 image */
define symbol CY_APPL1_START = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : CY_BTLDR_END;
/* The number of metadata records located at the end of Flash */
define symbol CY_METADATA_CNT = (CY_APPL_NUM == 2) ? 2 : ((CY_APPL_LOADER || CY_APPL_LOADABLE) ? 1 : 0);
/* The application area size measured in rows */
define symbol CY_APPL_ROW_CNT = ((CY_FLASH_SIZE - CY_APPL1_START) / CY_FLASH_ROW_SIZE) - CY_METADATA_CNT;
/* The start address of Loadable#2 image if any */
define symbol CY_APPL2_START = CY_APPL1_START + (CY_APPL_ROW_CNT / 2 + CY_APPL_ROW_CNT % 2) * CY_FLASH_ROW_SIZE;
/* The current image (Standard/Loader/Loadable) start address */
define symbol CY_APPL_START = (CY_APPL_NUM == 1) ? CY_APPL1_START : CY_APPL2_START;
/* The ECC data placement address */
define exported symbol CY_ECC_OFFSET = (CY_APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
/* The EEPROM offset and size that can be used by current application (Standard/Loader/Loadable) */
define symbol CY_EE_OFFSET = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
define symbol CY_EE_IN_USE = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
/* Define EEPROM region */
define region EEPROM_region = mem:[from (0x90200000 + CY_EE_OFFSET) size CY_EE_IN_USE];
/* Define APPL region that will limit application size */
define region APPL_region = mem:[from CY_APPL_START size CY_APPL_ROW_CNT * CY_FLASH_ROW_SIZE];
/****** Initializations ******/
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { readwrite section .ramvectors };
/******** Placements *********/
".cybootloader" : place at start of ROM_region {block LOADER};
"APPL" : place at start of APPL_region {block APPL};
"RAMVEC" : place at start of RAM_region { readwrite section .ramvectors };
"readwrite" : place in RAM_region { readwrite };
"HSTACK" : place at end of RAM_region { block HSTACK};
keep { section .cybootloader,
section .cyloadermeta,
section .cyloadablemeta,
section .cyconfigecc,
section .cycustnvl,
section .cywolatch,
section .cyeeprom,
section .cyflashprotect,
section .cymeta };
".cyloadermeta" : place at address mem : (CY_APPL_LOADER ? (CY_FLASH_SIZE - CY_METADATA_SIZE) : 0xF0000000) { readonly section .cyloadermeta };
".cyloadablemeta" : place at address mem : (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) { readonly section .cyloadablemeta };
".cyconfigecc" : place at address mem : (0x80000000 + CY_ECC_OFFSET) { readonly section .cyconfigecc };
".cycustnvl" : place at address mem : 0x90000000 { readonly section .cycustnvl };
".cywolatch" : place at address mem : 0x90100000 { readonly section .cywolatch };
".cyeeprom" : place in EEPROM_region { readonly section .cyeeprom };
".cyflashprotect" : place at address mem : 0x90400000 { readonly section .cyflashprotect };
".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
/* EOF */

132
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3RealView.scat
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@ -1,6 +1,10 @@
#! armcc -E
; The first line specifies a preprocessor command that the linker invokes
; to pass a scatter file through a C preprocessor.
;********************************************************************************
;* File Name: Cm3RealView.scat
;* Version 3.40
;* Version 4.0
;*
;* Description:
;* This Linker Descriptor file describes the memory layout of the PSoC5
@ -26,8 +30,62 @@
;* disclaimers, and limitations in the end user license agreement accompanying
;* the software package with which this file was provided.
;********************************************************************************/
#include "cyfitter.h"
LOAD_ROM 0 (262144 - 0)
#define CY_FLASH_SIZE 262144
#define CY_APPL_ORIGIN 0
#define CY_FLASH_ROW_SIZE 256
#define CY_ECC_ROW_SIZE 32
#define CY_EE_SIZE 2048
#define CY_METADATA_SIZE 64
; Define application base address
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
#define CY_APPL_NUM 1
#define CY_APPL_MAX 1
#define CY_EE_IN_BTLDR
#if CY_APPL_ORIGIN
#define APPL1_START CY_APPL_ORIGIN
#else
#define APPL1_START AlignExpr(ImageLimit(CYBOOTLOADER), CY_FLASH_ROW_SIZE)
#endif
#define APPL_START (APPL1_START + AlignExpr(((CY_FLASH_SIZE - APPL1_START - 2 * CY_FLASH_ROW_SIZE) / 2 ) * (CY_APPL_NUM - 1), CY_FLASH_ROW_SIZE))
#define ECC_OFFSET ((APPL_START / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE)
#define EE_OFFSET (CY_EE_IN_BTLDR ? 0 : (CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1))
#define EE_SIZE (CY_EE_IN_BTLDR ? CY_EE_SIZE : (CY_EE_SIZE / CY_APPL_MAX))
#else
#define APPL_START 0
#define ECC_OFFSET 0
#define EE_OFFSET 0
#define EE_SIZE CY_EE_SIZE
#endif
; Place Bootloader at the beginning of Flash
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
CYBOOTLOADER 0
{
.cybootloader +0
{
* (.cybootloader)
}
}
#if CY_APPL_ORIGIN
ScatterAssert(APPL_START > LoadLimit(CYBOOTLOADER))
#endif
#endif
APPLICATION APPL_START (CY_FLASH_SIZE - APPL_START)
{
VECTORS +0
{
@ -51,7 +109,7 @@ LOAD_ROM 0 (262144 - 0)
DATA +0
{
* (+RW, +ZI)
.ANY (+RW, +ZI)
}
ARM_LIB_HEAP (0x20000000 + (65536 / 2) - 0x1000 - 0x4000) EMPTY 0x1000
@ -62,3 +120,71 @@ LOAD_ROM 0 (262144 - 0)
{
}
}
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_BOOTLOADER || CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER)
CYLOADERMETA (CY_FLASH_SIZE - CY_METADATA_SIZE)
{
.cyloadermeta +0 { * (.cyloadermeta) }
}
#else
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
CYLOADABLEMETA (CY_FLASH_SIZE - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE)
{
.cyloadablemeta +0 { * (.cyloadablemeta) }
}
#endif
#endif
#if (CYDEV_ECC_ENABLE == 0)
CYCONFIGECC (0x80000000 + ECC_OFFSET)
{
.cyconfigecc +0 { * (.cyconfigecc) }
}
#endif
CYCUSTNVL 0x90000000
{
.cycustnvl +0 { * (.cycustnvl) }
}
CYWOLATCH 0x90100000
{
.cywolatch +0 { * (.cywolatch) }
}
#if defined(CYDEV_ALLOCATE_EEPROM)
CYEEPROM 0x90200000 + EE_OFFSET (EE_SIZE)
{
.cyeeprom +0 { * (.cyeeprom) }
}
#endif
CYFLASHPROTECT 0x90400000
{
.cyflashprotect +0 { * (.cyflashprotect) }
}
CYMETA 0x90500000
{
.cymeta +0 { * (.cymeta) }
}
#if (CYDEV_PROJ_TYPE == CYDEV_PROJ_TYPE_LOADABLE)
CYLOADERMETA +0
{
.cyloadermeta +0 { * (.cyloadermeta) }
}
#endif

322
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/Cm3Start.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: Cm3Start.c
* Version 3.40
* Version 4.0
*
* Description:
* Startup code for the ARM CM3.
@ -12,6 +12,7 @@
* the software package with which this file was provided.
*******************************************************************************/
#include <limits.h>
#include "cydevice_trm.h"
#include "cytypes.h"
#include "cyfitter_cfg.h"
@ -19,14 +20,15 @@
#include "CyDmac.h"
#include "cyfitter.h"
#define NUM_INTERRUPTS 32u
#define NUM_VECTORS (CYINT_IRQ_BASE+NUM_INTERRUPTS)
#define NUM_ROM_VECTORS 4u
#define NVIC_APINT ((reg32 *) CYREG_NVIC_APPLN_INTR)
#define NVIC_CFG_CTRL ((reg32 *) CYREG_NVIC_CFG_CONTROL)
#define NVIC_APINT_PRIGROUP_3_5 0x00000400u /* Priority group 3.5 split */
#define NVIC_APINT_VECTKEY 0x05FA0000u /* This key is required in order to write the NVIC_APINT register */
#define NVIC_CFG_STACKALIGN 0x00000200u /* This specifies that the exception stack must be 8 byte aligned */
#define CY_NUM_INTERRUPTS (32u)
#define CY_NUM_VECTORS (CYINT_IRQ_BASE + CY_NUM_INTERRUPTS)
#define CY_NUM_ROM_VECTORS (4u)
#define CY_NVIC_APINT_PTR ((reg32 *) CYREG_NVIC_APPLN_INTR)
#define CY_NVIC_CFG_CTRL_PTR ((reg32 *) CYREG_NVIC_CFG_CONTROL)
#define CY_NVIC_APINT_PRIGROUP_3_5 (0x00000400u) /* Priority group 3.5 split */
#define CY_NVIC_APINT_VECTKEY (0x05FA0000u) /* This key is required in order to write the NVIC_APINT register */
#define CY_NVIC_CFG_STACKALIGN (0x00000200u) /* This specifies that the exception stack must be 8 byte aligned */
/* Extern functions */
extern void CyBtldr_CheckLaunch(void);
@ -38,26 +40,35 @@ void Reset(void);
CY_ISR(IntDefaultHandler);
#if defined(__ARMCC_VERSION)
#define INITIAL_STACK_POINTER (cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit
#define INITIAL_STACK_POINTER ((cyisraddress)(uint32)&Image$$ARM_LIB_STACK$$ZI$$Limit)
#elif defined (__GNUC__)
#define INITIAL_STACK_POINTER __cs3_stack
#define INITIAL_STACK_POINTER (&__cy_stack)
#elif defined (__ICCARM__)
#pragma language=extended
#pragma segment="CSTACK"
#define INITIAL_STACK_POINTER { .__ptr = __sfe( "CSTACK" ) }
extern void __iar_program_start( void );
extern void __iar_data_init3 (void);
#endif /* (__ARMCC_VERSION) */
/* Global variables */
CY_NOINIT static uint32 cySysNoInitDataValid;
#if !defined (__ICCARM__)
CY_NOINIT static uint32 cySysNoInitDataValid;
#endif /* !defined (__ICCARM__) */
/*******************************************************************************
* Default Ram Interrupt Vector table storage area. Must be 256-byte aligned.
*******************************************************************************/
__attribute__ ((section(".ramvectors")))
#if defined(__ARMCC_VERSION)
__align(256)
#elif defined (__GNUC__)
__attribute__ ((aligned(256)))
#endif
cyisraddress CyRamVectors[NUM_VECTORS];
#if defined (__ICCARM__)
#pragma location=".ramvectors"
#pragma data_alignment=256
#else
CY_SECTION(".ramvectors")
CY_ALIGN(256)
#endif /* defined (__ICCARM__) */
cyisraddress CyRamVectors[CY_NUM_VECTORS];
/*******************************************************************************
@ -121,42 +132,27 @@ extern int __main(void);
* None
*
*******************************************************************************/
__asm void Reset(void)
void Reset(void)
{
PRESERVE8
EXTERN __main
EXTERN CyResetStatus
#if(CYDEV_BOOTLOADER_ENABLE)
EXTERN CyBtldr_CheckLaunch
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
#if(CYDEV_DEBUGGING_ENABLE)
ldr r3, =0x400046e8 /* CYDEV_DEBUG_ENABLE_REGISTER */
ldrb r4, [r3, #0]
orr r4, r4, #01
strb r4, [r3, #0]
debugEnabled
#endif /* (CYDEV_DEBUGGING_ENABLE) */
ldr r3, =0x400046fa /* CYREG_RESET_SR0 */
ldrb r2, [r3, #0]
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
ldr r3, =0x400076BC /* CYREG_PHUB_CFGMEM23_CFG1 */
strb r2, [r3, #0]
#if(CYDEV_BOOTLOADER_ENABLE)
bl CyBtldr_CheckLaunch
CyBtldr_CheckLaunch();
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
/* Let RealView setup the libraries. */
bl __main
ALIGN
__main();
}
@ -181,14 +177,38 @@ void $Sub$$main(void)
/* Call original main */
$Super$$main();
/* If main returns it is undefined what we should do. */
while (1);
while (1)
{
/* If main returns it is undefined what we should do. */
}
}
#elif defined(__GNUC__)
extern void __cs3_stack(void);
extern void __cs3_start_c(void);
void Start_c(void);
/* Stack Base address */
extern void __cy_stack(void);
/* Application entry point. */
extern int main(void);
/* The static objects constructors initializer */
extern void __libc_init_array(void);
typedef unsigned char __cy_byte_align8 __attribute ((aligned (8)));
struct __cy_region
{
__cy_byte_align8 *init; /* Initial contents of this region. */
__cy_byte_align8 *data; /* Start address of region. */
size_t init_size; /* Size of initial data. */
size_t zero_size; /* Additional size to be zeroed. */
};
extern const struct __cy_region __cy_regions[];
extern const char __cy_region_num __attribute__((weak));
#define __cy_region_num ((size_t)&__cy_region_num)
/*******************************************************************************
@ -196,7 +216,7 @@ extern void __cs3_start_c(void);
********************************************************************************
*
* Summary:
* This function handles the reset interrupt for the GCC toolchain. This is the
* This function handles the reset interrupt for the GCC toolchain. This is the
* first bit of code that is executed at startup.
*
* Parameters:
@ -206,34 +226,140 @@ extern void __cs3_start_c(void);
* None
*
*******************************************************************************/
__attribute__ ((naked))
void Reset(void)
{
__asm volatile(
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
#if(CYDEV_DEBUGGING_ENABLE)
" ldr r3, =%0\n"
" ldrb r4, [r3, #0]\n"
" orr r4, r4, #01\n"
" strb r4, [r3, #0]\n"
"debugEnabled:\n"
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
" ldr r3, =%1\n"
" ldrb r2, [r3, #0]\n"
" uxtb r2, r2\n"
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
" ldr r3, =%2\n"
" strb r2, [r3, #0]\n"
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
#if(CYDEV_BOOTLOADER_ENABLE)
" bl CyBtldr_CheckLaunch\n"
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
#if(CYDEV_BOOTLOADER_ENABLE)
CyBtldr_CheckLaunch();
#endif /* (CYDEV_BOOTLOADER_ENABLE) */
/* Switch to C initialization phase */
" bl __cs3_start_c\n" : : "i" (CYDEV_DEBUG_ENABLE_REGISTER), "i" (CYREG_RESET_SR0), "i" (CYREG_PHUB_CFGMEM23_CFG1));
Start_c();
}
__attribute__((weak))
void _exit(int status)
{
/* Cause a divide by 0 exception */
int x = status / INT_MAX;
x = 4 / x;
while(1)
{
}
}
/*******************************************************************************
* Function Name: Start_c
********************************************************************************
*
* Summary:
* This function handles initializing the .data and .bss sections in
* preperation for running standard C code. Once initialization is complete
* it will call main(). This function will never return.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void Start_c(void) __attribute__ ((noreturn));
void Start_c(void)
{
unsigned regions = __cy_region_num;
const struct __cy_region *rptr = __cy_regions;
/* Initialize memory */
for (regions = __cy_region_num, rptr = __cy_regions; regions--; rptr++)
{
uint32 *src = (uint32 *)rptr->init;
uint32 *dst = (uint32 *)rptr->data;
unsigned limit = rptr->init_size;
unsigned count;
for (count = 0u; count != limit; count += sizeof (uint32))
{
*dst++ = *src++;
}
limit = rptr->zero_size;
for (count = 0u; count != limit; count += sizeof (uint32))
{
*dst++ = 0u;
}
}
/* Invoke static objects constructors */
__libc_init_array();
(void) main();
while (1)
{
/* If main returns, make sure we don't return. */
}
}
#elif defined (__ICCARM__)
/*******************************************************************************
* Function Name: __low_level_init
********************************************************************************
*
* Summary:
* This function perform early initializations for the IAR Embedded
* Workbench IDE. It is executed in the context of reset interrupt handler
* before the data sections are initialized.
*
* Parameters:
* None
*
* Return:
* The value that determines whether or not data sections should be initialized
* by the system startup code:
* 0 - skip data sections initialization;
* 1 - initialize data sections;
*
*******************************************************************************/
int __low_level_init(void)
{
#if(CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE)
/* For PSoC 5LP, debugging is enabled by default */
#if(CYDEV_DEBUGGING_ENABLE == 0)
*(reg32 *)(CYDEV_DEBUG_ENABLE_REGISTER) |= CYDEV_DEBUG_ENABLE_MASK;
#endif /* (CYDEV_DEBUGGING_ENABLE) */
/* Reset Status Register has Read-to-clear SW access mode.
* Preserve current RESET_SR0 state to make it available for next reading.
*/
*(reg32 *)(CYREG_PHUB_CFGMEM23_CFG1) = *(reg32 *)(CYREG_RESET_SR0);
#endif /* (CYDEV_PROJ_TYPE != CYDEV_PROJ_TYPE_LOADABLE) */
#if (CYDEV_BOOTLOADER_ENABLE)
CyBtldr_CheckLaunch();
#endif /* CYDEV_BOOTLOADER_ENABLE */
/* Initialize data sections */
__iar_data_init3();
initialize_psoc();
return 0;
}
#endif /* __GNUC__ */
@ -245,21 +371,32 @@ void Reset(void)
*
*******************************************************************************/
#if defined(__ARMCC_VERSION)
/* Suppress diagnostic message 1296-D: extended constant initialiser used */
#pragma diag_suppress 1296
#endif
__attribute__ ((section(".romvectors")))
const cyisraddress RomVectors[NUM_ROM_VECTORS] =
#endif /* defined(__ARMCC_VERSION) */
#if defined (__ICCARM__)
#pragma location=".romvectors"
const intvec_elem __vector_table[CY_NUM_ROM_VECTORS] =
#else
CY_SECTION(".romvectors")
const cyisraddress RomVectors[CY_NUM_ROM_VECTORS] =
#endif /* defined (__ICCARM__) */
{
#if defined(__ARMCC_VERSION)
INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
#elif defined (__GNUC__)
&INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
#endif /* (__ARMCC_VERSION) */
(cyisraddress)&Reset, /* The reset handler 1 */
INITIAL_STACK_POINTER, /* The initial stack pointer 0 */
#if defined (__ICCARM__) /* The reset handler 1 */
__iar_program_start,
#else
(cyisraddress)&Reset,
#endif /* defined (__ICCARM__) */
&IntDefaultHandler, /* The NMI handler 2 */
&IntDefaultHandler, /* The hard fault handler 3 */
};
#if defined(__ARMCC_VERSION)
#pragma diag_default 1296
#endif /* defined(__ARMCC_VERSION) */
/*******************************************************************************
* Function Name: initialize_psoc
@ -278,7 +415,6 @@ const cyisraddress RomVectors[NUM_ROM_VECTORS] =
#if (defined(__GNUC__) && !defined(__ARMCC_VERSION))
__attribute__ ((constructor(101)))
#endif
void initialize_psoc(void)
{
uint32 i;
@ -286,13 +422,17 @@ void initialize_psoc(void)
/* Set Priority group 5. */
/* Writes to NVIC_APINT register require the VECTKEY in the upper half */
*NVIC_APINT = NVIC_APINT_VECTKEY | NVIC_APINT_PRIGROUP_3_5;
*NVIC_CFG_CTRL |= NVIC_CFG_STACKALIGN;
*CY_NVIC_APINT_PTR = CY_NVIC_APINT_VECTKEY | CY_NVIC_APINT_PRIGROUP_3_5;
*CY_NVIC_CFG_CTRL_PTR |= CY_NVIC_CFG_STACKALIGN;
/* Set Ram interrupt vectors to default functions. */
for(i = 0u; i < NUM_VECTORS; i++)
for (i = 0u; i < CY_NUM_VECTORS; i++)
{
CyRamVectors[i] = (i < NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
#if defined (__ICCARM__)
CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? __vector_table[i].__fun : &IntDefaultHandler;
#else
CyRamVectors[i] = (i < CY_NUM_ROM_VECTORS) ? RomVectors[i] : &IntDefaultHandler;
#endif /* defined (__ICCARM__) */
}
/* Was stored in CFGMEM to avoid being cleared while SRAM gets cleared */
@ -310,9 +450,11 @@ void initialize_psoc(void)
CyDmacConfigure();
#endif /* (0u != DMA_CHANNELS_USED__MASK0) */
/* Actually, no need to clean this variable, just to make compiler happy. */
cySysNoInitDataValid = 0u;
#if !defined (__ICCARM__)
/* Actually, no need to clean this variable, just to make compiler happy. */
cySysNoInitDataValid = 0u;
#endif /* !defined (__ICCARM__) */
}

82
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmGnu.s
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyBootAsmGnu.s
* Version 3.40
* Version 4.0
*
* Description:
* Assembly routines for GNU as.
@ -12,6 +12,8 @@
* the software package with which this file was provided.
*******************************************************************************/
.include "cyfittergnu.inc"
.syntax unified
.text
.thumb
@ -38,16 +40,68 @@
.type CyDelayCycles, %function
.thumb_func
CyDelayCycles: /* cycles bytes */
ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */
LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */
BEQ CyDelayCycles_done /* 2 2 Skip if 0 */
NOP /* 1 2 Loop alignment padding */
/* If ICache is enabled */
.ifeq CYDEV_INSTRUCT_CACHE_ENABLED - 1
ADDS r0, r0, #2 /* 1 2 Round to nearest multiple of 4 */
LSRS r0, r0, #2 /* 1 2 Divide by 4 and set flags */
BEQ CyDelayCycles_done /* 2 2 Skip if 0 */
NOP /* 1 2 Loop alignment padding */
CyDelayCycles_loop:
SUBS r0, r0, #1 /* 1 2 */
MOV r0, r0 /* 1 2 Pad loop to power of two cycles */
BNE CyDelayCycles_loop /* 2 2 */
SUBS r0, r0, #1 /* 1 2 */
MOV r0, r0 /* 1 2 Pad loop to power of two cycles */
BNE CyDelayCycles_loop /* 2 2 */
CyDelayCycles_done:
BX lr /* 3 2 */
BX lr /* 3 2 */
.else
CMP r0, #20 /* 1 2 If delay is short - jump to cycle */
BLS CyDelayCycles_short /* 1 2 */
PUSH {r1} /* 2 2 PUSH r1 to stack */
MOVS r1, #1 /* 1 2 */
SUBS r0, r0, #20 /* 1 2 Subtract overhead */
LDR r1,=CYREG_CACHE_CC_CTL/* 2 2 Load flash wait cycles value */
LDRB r1, [r1, #0] /* 2 2 */
ANDS r1, #0xC0 /* 1 2 */
LSRS r1, r1, #6 /* 1 2 */
PUSH {r2} /* 1 2 PUSH r2 to stack */
LDR r2, =cy_flash_cycles /* 2 2 */
LDRB r1, [r2, r1] /* 2 2 */
POP {r2} /* 2 2 POP r2 from stack */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
CyDelayCycles_loop:
SBCS r0, r0, r1 /* 1 2 */
BPL CyDelayCycles_loop /* 3 2 */
NOP /* 1 2 Loop alignment padding */
NOP /* 1 2 Loop alignment padding */
POP {r1} /* 2 2 POP r1 from stack */
CyDelayCycles_done:
BX lr /* 3 2 */
NOP /* 1 2 Alignment padding */
NOP /* 1 2 Alignment padding */
CyDelayCycles_short:
SBCS r0, r0, #4 /* 1 2 */
BPL CyDelayCycles_short /* 3 2 */
BX lr /* 3 2 */
cy_flash_cycles:
.byte 0x0B
.byte 0x05
.byte 0x07
.byte 0x09
.endif
.endfunc
@ -81,9 +135,9 @@ CyDelayCycles_done:
.type CyEnterCriticalSection, %function
.thumb_func
CyEnterCriticalSection:
MRS r0, PRIMASK /* Save and return interrupt state */
CPSID I /* Disable interrupts */
BX lr
MRS r0, PRIMASK /* Save and return interrupt state */
CPSID I /* Disable interrupts */
BX lr
.endfunc
@ -110,8 +164,8 @@ CyEnterCriticalSection:
.type CyExitCriticalSection, %function
.thumb_func
CyExitCriticalSection:
MSR PRIMASK, r0 /* Restore interrupt state */
BX lr
MSR PRIMASK, r0 /* Restore interrupt state */
BX lr
.endfunc
.end

156
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmIar.s Normal file
View File

@ -0,0 +1,156 @@
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmIar.s
; Version 4.0
;
; DESCRIPTION:
; Assembly routines for IAR Embedded Workbench IDE.
;
;-------------------------------------------------------------------------------
; Copyright 2013, Cypress Semiconductor Corporation. All rights reserved.
; You may use this file only in accordance with the license, terms, conditions,
; disclaimers, and limitations in the end user license agreement accompanying
; the software package with which this file was provided.
;-------------------------------------------------------------------------------
SECTION .text:CODE:ROOT(4)
PUBLIC CyDelayCycles
PUBLIC CyEnterCriticalSection
PUBLIC CyExitCriticalSection
INCLUDE cyfitteriar.inc
THUMB
;-------------------------------------------------------------------------------
; Function Name: CyEnterCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyEnterCriticalSection disables interrupts and returns a value indicating
; whether interrupts were previously enabled.
;
; Note Implementation of CyEnterCriticalSection manipulates the IRQ enable bit
; with interrupts still enabled. The test and set of the interrupt bits is not
; atomic. Therefore, to avoid corrupting processor state, it must be the policy
; that all interrupt routines restore the interrupt enable bits as they were
; found on entry.
;
; Parameters:
; None
;
; Return:
; uint8
; Returns 0 if interrupts were previously enabled or 1 if interrupts
; were previously disabled.
;
;-------------------------------------------------------------------------------
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection:
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
;-------------------------------------------------------------------------------
; Function Name: CyExitCriticalSection
;-------------------------------------------------------------------------------
;
; Summary:
; CyExitCriticalSection re-enables interrupts if they were enabled before
; CyEnterCriticalSection was called. The argument should be the value returned
; from CyEnterCriticalSection.
;
; Parameters:
; uint8 savedIntrStatus:
; Saved interrupt status returned by the CyEnterCriticalSection function.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyExitCriticalSection(uint8 savedIntrStatus)
CyExitCriticalSection:
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
;-------------------------------------------------------------------------------
; Function Name: CyDelayCycles
;-------------------------------------------------------------------------------
;
; Summary:
; Delays for the specified number of cycles.
;
; Parameters:
; uint32 cycles: number of cycles to delay.
;
; Return:
; None
;
;-------------------------------------------------------------------------------
; void CyDelayCycles(uint32 cycles)
CyDelayCycles:
IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
CyDelayCycles_loop:
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
CyDelayCycles_done:
BX lr ; 3 2
ELSE
CMP r0, #20 ; 1 2 If delay is short - jump to cycle
BLS CyDelayCycles_short ; 1 2
PUSH {r1} ; 2 2 PUSH r1 to stack
MOVS r1, #1 ; 1 2
SUBS r0, r0, #20 ; 1 2 Subtract overhead
LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value
LDRB r1, [r1, #0] ; 2 2
ANDS r1, r1, #0xC0 ; 1 2
LSRS r1, r1, #6 ; 1 2
PUSH {r2} ; 1 2 PUSH r2 to stack
LDR r2, =cy_flash_cycles ; 2 2
LDRB r1, [r2, r1] ; 2 2
POP {r2} ; 2 2 POP r2 from stack
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_loop:
SBCS r0, r0, r1 ; 1 2
BPL CyDelayCycles_loop ; 3 2
NOP ; 1 2 Loop alignment padding
NOP ; 1 2 Loop alignment padding
POP {r1} ; 2 2 POP r1 from stack
CyDelayCycles_done:
BX lr ; 3 2
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_short:
SBCS r0, r0, #4 ; 1 2
BPL CyDelayCycles_short ; 3 2
BX lr ; 3 2
NOP ; 1 2 Loop alignment padding
DATA
cy_flash_cycles:
byte_1 DCB 0x0B
byte_2 DCB 0x05
byte_3 DCB 0x07
byte_4 DCB 0x09
ENDIF
END

103
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyBootAsmRv.s
View File

@ -1,6 +1,6 @@
;-------------------------------------------------------------------------------
; FILENAME: CyBootAsmRv.s
; Version 3.40
; Version 4.0
;
; DESCRIPTION:
; Assembly routines for RealView.
@ -12,9 +12,11 @@
; the software package with which this file was provided.
;-------------------------------------------------------------------------------
AREA |.text|,CODE,ALIGN=3
THUMB
EXTERN Reset
AREA |.text|,CODE,ALIGN=3
THUMB
EXTERN Reset
GET cyfitterrv.inc
;-------------------------------------------------------------------------------
; Function Name: CyDelayCycles
@ -31,21 +33,70 @@
;
;-------------------------------------------------------------------------------
; void CyDelayCycles(uint32 cycles)
ALIGN 8
ALIGN 8
CyDelayCycles FUNCTION
EXPORT CyDelayCycles
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
EXPORT CyDelayCycles
IF CYDEV_INSTRUCT_CACHE_ENABLED == 1
; cycles bytes
ADDS r0, r0, #2 ; 1 2 Round to nearest multiple of 4
LSRS r0, r0, #2 ; 1 2 Divide by 4 and set flags
BEQ CyDelayCycles_done ; 2 2 Skip if 0
NOP ; 1 2 Loop alignment padding
CyDelayCycles_loop
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
SUBS r0, r0, #1 ; 1 2
MOV r0, r0 ; 1 2 Pad loop to power of two cycles
BNE CyDelayCycles_loop ; 2 2
NOP ; 1 2 Loop alignment padding
CyDelayCycles_done
BX lr ; 3 2
ENDFUNC
BX lr ; 3 2
ELSE
CMP r0, #20 ; 1 2 If delay is short - jump to cycle
BLS CyDelayCycles_short ; 1 2
PUSH {r1} ; 2 2 PUSH r1 to stack
MOVS r1, #1 ; 1 2
SUBS r0, r0, #20 ; 1 2 Subtract overhead
LDR r1,=CYREG_CACHE_CC_CTL; 2 2 Load flash wait cycles value
LDRB r1, [r1, #0] ; 2 2
ANDS r1, #0xC0 ; 1 2
LSRS r1, r1, #6 ; 1 2
PUSH {r2} ; 1 2 PUSH r2 to stack
LDR r2, =cy_flash_cycles ; 2 2
LDRB r1, [r2, r1] ; 2 2
POP {r2} ; 2 2 POP r2 from stack
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_loop
SBCS r0, r0, r1 ; 1 2
BPL CyDelayCycles_loop ; 3 2
NOP ; 1 2 Loop alignment padding
NOP ; 1 2 Loop alignment padding
POP {r1} ; 2 2 POP r1 from stack
CyDelayCycles_done
BX lr ; 3 2
NOP ; 1 2 Alignment padding
NOP ; 1 2 Alignment padding
CyDelayCycles_short
SBCS r0, r0, #4 ; 1 2
BPL CyDelayCycles_short ; 3 2
BX lr ; 3 2
cy_flash_cycles
byte_1 DCB 0x0B
byte_2 DCB 0x05
byte_3 DCB 0x07
byte_4 DCB 0x09
ENDIF
ENDFUNC
;-------------------------------------------------------------------------------
@ -74,11 +125,11 @@ CyDelayCycles_done
;-------------------------------------------------------------------------------
; uint8 CyEnterCriticalSection(void)
CyEnterCriticalSection FUNCTION
EXPORT CyEnterCriticalSection
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
ENDFUNC
EXPORT CyEnterCriticalSection
MRS r0, PRIMASK ; Save and return interrupt state
CPSID I ; Disable interrupts
BX lr
ENDFUNC
;-------------------------------------------------------------------------------
@ -100,11 +151,11 @@ CyEnterCriticalSection FUNCTION
;-------------------------------------------------------------------------------
; void CyExitCriticalSection(uint8 savedIntrStatus)
CyExitCriticalSection FUNCTION
EXPORT CyExitCriticalSection
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
ENDFUNC
EXPORT CyExitCriticalSection
MSR PRIMASK, r0 ; Restore interrupt state
BX lr
ENDFUNC
END
END
; [] END OF FILE

82
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyDmac.c
* Version 3.40
* Version 4.0
*
* Description:
* Provides an API for the DMAC component. The API includes functions for the
@ -29,9 +29,17 @@
#include "CyDmac.h"
static uint8 CyDmaTdCurrentNumber; /* Current Number of free elements in the list */
static uint8 CyDmaTdFreeIndex; /* Index of the first available TD */
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */
/*******************************************************************************
* The following variables are initialized from CyDmacConfigure() function that
* is executed from initialize_psoc() at the early initialization stage.
* In case of IAR EW IDE, initialize_psoc() is executed before the data sections
* are initialized. To avoid zeroing, these variables should be initialized
* properly during segments initialization as well.
*******************************************************************************/
static uint8 CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS; /* Current Number of free elements in the list */
static uint8 CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); /* Index of the first available TD */
static uint32 CyDmaChannels = DMA_CHANNELS_USED__MASK0; /* Bit map of DMA channel ownership */
/*******************************************************************************
@ -55,13 +63,13 @@ void CyDmacConfigure(void)
uint8 dmaIndex;
/* Set TD list variables. */
CyDmaTdFreeIndex = ((uint8) (CY_DMA_NUMBEROF_TDS - 1u));
CyDmaTdFreeIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u);
CyDmaTdCurrentNumber = CY_DMA_NUMBEROF_TDS;
/* Make TD free list. */
for(dmaIndex = ((uint8)(CY_DMA_NUMBEROF_TDS - 1u)); dmaIndex != 0u; dmaIndex--)
for(dmaIndex = (uint8)(CY_DMA_NUMBEROF_TDS - 1u); dmaIndex != 0u; dmaIndex--)
{
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = ((uint8)(dmaIndex - 1u));
CY_DMA_TDMEM_STRUCT_PTR[dmaIndex].TD0[0u] = (uint8)(dmaIndex - 1u);
}
/* Make the last one point to zero. */
@ -299,8 +307,22 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds)
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
{
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =
(CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~0x20u))) | ((0u != preserveTds) ? 0x21u : 0x01u);
if (0u != preserveTds)
{
/* Store the intermediate TD states separately in CHn_SEP_TD0/1 to
* preserve the original TD chain
*/
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_WORK_SEP;
}
else
{
/* Store the intermediate and final TD states on top of the original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_CH_BASIC_CFG_WORK_SEP);
}
/* Enable channel */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= CY_DMA_CH_BASIC_CFG_EN;
status = CYRET_SUCCESS;
}
@ -335,7 +357,16 @@ cystatus CyDmaChDisable(uint8 chHandle)
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
{
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~0x21u));
/***********************************************************************
* Should not change configuration information of a DMA channel when it
* is active (or vulnerable to becoming active).
***********************************************************************/
/* Disable channel */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_EN));
/* Store the intermediate and final TD states on top of the original TD chain */
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0] &= ((uint8) (~CY_DMA_CH_BASIC_CFG_WORK_SEP));
status = CYRET_SUCCESS;
}
@ -440,6 +471,7 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
{
cystatus status = CYRET_BAD_PARAM;
reg16 *convert;
#if(CY_PSOC5)
@ -460,11 +492,12 @@ cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destina
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
{
/* Set source address */
reg16 *convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[0];
CY_SET_REG16(convert, source);
/* Set destination address */
CY_SET_REG16((reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2], destination);
convert = (reg16 *) &CY_DMA_CFGMEM_STRUCT_PTR[chHandle].CFG1[2u];
CY_SET_REG16(convert, destination);
status = CYRET_SUCCESS;
}
@ -570,7 +603,7 @@ cystatus CyDmaChGetRequest(uint8 chHandle)
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
{
status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
status = (cystatus) ((uint32)CY_DMA_CH_STRUCT_PTR[chHandle].action[0u] &
(uint32)(CY_DMA_CPU_REQ | CY_DMA_CPU_TERM_TD | CY_DMA_CPU_TERM_CHAIN));
}
@ -977,15 +1010,17 @@ cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 *
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination)
{
cystatus status = CYRET_BAD_PARAM;
reg16 *convert;
if(tdHandle < CY_DMA_NUMBEROF_TDS)
{
/* Set source address */
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
CY_SET_REG16(convert, source);
/* Set destination address */
CY_SET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2], destination);
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
CY_SET_REG16(convert, destination);
status = CYRET_SUCCESS;
}
@ -1023,6 +1058,7 @@ cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination)
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination)
{
cystatus status = CYRET_BAD_PARAM;
reg16 *convert;
if(tdHandle < CY_DMA_NUMBEROF_TDS)
{
@ -1030,7 +1066,7 @@ cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination
if(NULL != source)
{
/* Get source address */
reg16 *convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0];
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[0u];
*source = CY_GET_REG16(convert);
}
@ -1038,7 +1074,8 @@ cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination
if(NULL != destination)
{
/* Get Destination address. */
*destination = CY_GET_REG16((reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2]);
convert = (reg16 *) &CY_DMA_TDMEM_STRUCT_PTR[tdHandle].TD1[2u];
*destination = CY_GET_REG16(convert);
}
status = CYRET_SUCCESS;
@ -1075,9 +1112,14 @@ cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR)
if(chHandle < CY_DMA_NUMBEROF_CHANNELS)
{
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] =
(CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] & ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE))) |
((0u != enableRR) ? CY_DMA_ROUND_ROBIN_ENABLE : ((uint8)(~CY_DMA_ROUND_ROBIN_ENABLE)));
if (0u != enableRR)
{
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] |= (uint8)CY_DMA_ROUND_ROBIN_ENABLE;
}
else
{
CY_DMA_CH_STRUCT_PTR[chHandle].basic_cfg[0u] &= (uint8)(~CY_DMA_ROUND_ROBIN_ENABLE);
}
status = CYRET_SUCCESS;
}

30
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyDmac.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyDmac.h
* Version 3.40
* Version 4.0
*
* Description:
* Provides the function definitions for the DMA Controller.
@ -43,20 +43,24 @@ cystatus CyDmaChEnable(uint8 chHandle, uint8 preserveTds) ;
cystatus CyDmaChDisable(uint8 chHandle) ;
cystatus CyDmaClearPendingDrq(uint8 chHandle) ;
cystatus CyDmaChPriority(uint8 chHandle, uint8 priority) ;
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination);
cystatus CyDmaChSetExtendedAddress(uint8 chHandle, uint16 source, uint16 destination)\
;
cystatus CyDmaChSetInitialTd(uint8 chHandle, uint8 startTd) ;
cystatus CyDmaChSetRequest(uint8 chHandle, uint8 request) ;
cystatus CyDmaChGetRequest(uint8 chHandle) ;
cystatus CyDmaChStatus(uint8 chHandle, uint8 * currentTd, uint8 * state) ;
cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0, uint8 tdDone1, uint8 tdStop) ;
cystatus CyDmaChSetConfiguration(uint8 chHandle, uint8 burstCount, uint8 requestPerBurst, uint8 tdDone0,
uint8 tdDone1, uint8 tdStop) ;
cystatus CyDmaChRoundRobin(uint8 chHandle, uint8 enableRR) ;
/* Transfer Descriptor functions. */
uint8 CyDmaTdAllocate(void) ;
void CyDmaTdFree(uint8 tdHandle) ;
uint8 CyDmaTdFreeCount(void) ;
cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration) ;
cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration) ;
cystatus CyDmaTdSetConfiguration(uint8 tdHandle, uint16 transferCount, uint8 nextTd, uint8 configuration)\
;
cystatus CyDmaTdGetConfiguration(uint8 tdHandle, uint16 * transferCount, uint8 * nextTd, uint8 * configuration)\
;
cystatus CyDmaTdSetAddress(uint8 tdHandle, uint16 source, uint16 destination) ;
cystatus CyDmaTdGetAddress(uint8 tdHandle, uint16 * source, uint16 * destination) ;
@ -108,10 +112,7 @@ typedef struct dmac_tdmem2_struct
#define CY_DMA_INVALID_CHANNEL 0xFFu /* Invalid Channel ID */
#define CY_DMA_INVALID_TD 0xFFu /* Invalid TD */
#define CY_DMA_END_CHAIN_TD 0xFFu /* End of chain TD */
#if(CY_PSOC3 || CY_PSOC5LP)
#define CY_DMA_DISABLE_TD 0xFEu
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define CY_DMA_DISABLE_TD 0xFEu
#define CY_DMA_TD_SIZE 0x08u
@ -146,6 +147,13 @@ typedef struct dmac_tdmem2_struct
#define CY_DMA_ROUND_ROBIN_ENABLE ((uint8)(1u << 4u))
/*******************************************************************************
* CyDmaChEnable() / CyDmaChDisable() API constants
*******************************************************************************/
#define CY_DMA_CH_BASIC_CFG_EN (0x01u)
#define CY_DMA_CH_BASIC_CFG_WORK_SEP (0x20u)
/***************************************
* Registers
***************************************/
@ -195,9 +203,7 @@ typedef struct dmac_tdmem2_struct
#define DMAC_UNPOP_ACC (CY_DMA_UNPOP_ACC)
#define DMAC_PERIPH_ERR (CY_DMA_PERIPH_ERR)
#define ROUND_ROBIN_ENABLE (CY_DMA_ROUND_ROBIN_ENABLE)
#if(CY_PSOC3 || CY_PSOC5LP)
#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define DMA_DISABLE_TD (CY_DMA_DISABLE_TD)
#define DMAC_CFG (CY_DMA_CFG_PTR)
#define DMAC_ERR (CY_DMA_ERR_PTR)

352
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyFlash.c
* Version 3.40
* Version 4.0
*
* Description:
* Provides an API for the FLASH/EEPROM.
@ -42,10 +42,7 @@ static cystatus CySetTempInt(void);
********************************************************************************
*
* Summary:
* Enable the EEPROM/Flash.
*
* Note: For PSoC 5, this will enable both Flash and EEPROM. For PSoC 3 and
* PSOC 5LP this will enable only Flash.
* Enable the Flash.
*
* Parameters:
* None
@ -56,25 +53,11 @@ static cystatus CySetTempInt(void);
*******************************************************************************/
void CyFlash_Start(void)
{
#if(CY_PSOC5A)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_EE_MASK;
#endif /* (CY_PSOC5A) */
#if(CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_FLASH_MASK;
CyDelayUs(CY_FLASH_EE_STARTUP_DELAY);
}
@ -85,11 +68,7 @@ void CyFlash_Start(void)
********************************************************************************
*
* Summary:
* Disable the EEPROM/Flash.
*
* Note:
* PSoC 5: disable both Flash and EEPROM.
* PSoC 3 and PSOC 5LP: disable only Flash. Use CyEEPROM_Stop() to stop EEPROM.
* Disable the Flash.
*
* Parameters:
* None
@ -104,25 +83,11 @@ void CyFlash_Start(void)
*******************************************************************************/
void CyFlash_Stop(void)
{
#if (CY_PSOC5A)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_EE_MASK));
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_FLASH_MASK));
}
@ -158,30 +123,26 @@ static cystatus CySetTempInt(void)
if(CySpcLock() == CYRET_SUCCESS)
{
/* Write the command. */
#if(CY_PSOC5A)
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES, CY_TEMP_TIMER_PERIOD, CY_TEMP_CLK_DIV_SELECT))
#else
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
#endif /* (CY_PSOC5A) */
if(CYRET_STARTED == CySpcGetTemp(CY_TEMP_NUMBER_OF_SAMPLES))
{
do
{
do
if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
{
if(CySpcReadData(dieTemperature, CY_FLASH_DIE_TEMP_DATA_SIZE) == CY_FLASH_DIE_TEMP_DATA_SIZE)
status = CYRET_SUCCESS;
while(CY_SPC_BUSY)
{
status = CYRET_SUCCESS;
while(CY_SPC_BUSY)
{
/* Spin until idle. */
CyDelayUs(1u);
}
break;
/* Spin until idle. */
CyDelayUs(1u);
}
break;
}
} while(CY_SPC_BUSY);
}
} while(CY_SPC_BUSY);
}
CySpcUnlock();
CySpcUnlock();
}
else
{
@ -288,15 +249,17 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
********************************************************************************
*
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
* Sends a command to the SPC to load and program a row of data in
* Flash or EEPROM.
*
* Parameters:
* arrayID:
* ID of the array to write.
* rowAddress:
* rowAddress of flash row to program.
* rowData:
* Array of bytes to write.
* arrayID: ID of the array to write.
* The type of write, Flash or EEPROM, is determined from the array ID.
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts from 0x00 to
* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
* rowAddress: rowAddress of flash row to program.
* rowData: Array of bytes to write.
*
* Return:
* status:
@ -324,10 +287,15 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
********************************************************************************
*
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
* Sends a command to the SPC to load and program a row of data in
* Flash or EEPROM.
*
* Parameters:
* arrayID : ID of the array to write.
* The type of write, Flash or EEPROM, is determined from the array ID.
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts from 0x00 to
* 0x3F and for the EEPROM memory it lasts from 0x40 to 0x7F.
* rowAddress : rowAddress of flash row to program.
* rowData : Array of bytes to write.
*
@ -346,30 +314,41 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
uint16 rowSize;
cystatus status;
rowSize = (arrayId > CY_SPC_LAST_FLASH_ARRAYID) ? \
CYDEV_EEPROM_ROW_SIZE : \
(CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
if(rowSize != CYDEV_EEPROM_ROW_SIZE)
/* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
if(NULL != rowBuffer)
{
/* Save the ECC area. */
offset = CYDEV_ECC_BASE + ((uint32) arrayId * CYDEV_ECC_SECTOR_SIZE) +
((uint32) rowAddress * CYDEV_ECC_ROW_SIZE);
for (i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
if(arrayId > CY_SPC_LAST_FLASH_ARRAYID)
{
*(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
rowSize = CYDEV_EEPROM_ROW_SIZE;
}
}
else
{
rowSize = CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE;
/* Copy the rowdata to the temporary buffer. */
/* Save the ECC area. */
offset = CYDEV_ECC_BASE +
((uint32)arrayId * CYDEV_ECC_SECTOR_SIZE) +
((uint32)rowAddress * CYDEV_ECC_ROW_SIZE);
for(i = 0u; i < CYDEV_ECC_ROW_SIZE; i++)
{
*(rowBuffer + CYDEV_FLS_ROW_SIZE + i) = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
}
/* Copy the rowdata to the temporary buffer. */
#if(CY_PSOC3)
(void) memcpy((void *) rowBuffer, (void *)((uint32) rowData), (int16) CYDEV_FLS_ROW_SIZE);
#else
(void) memcpy((void *) rowBuffer, (const void *) rowData, CYDEV_FLS_ROW_SIZE);
#endif /* (CY_PSOC3) */
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, rowSize);
}
else
{
status = CYRET_UNKNOWN;
}
return(status);
}
@ -388,12 +367,12 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
* This function is only valid for Flash array IDs (not for EEPROM).
*
* Parameters:
* arrayId:
* ID of the array to write
* rowAddress:
* Address of the sector to erase.
* rowECC:
* Array of bytes to write.
* arrayId: ID of the array to write
* The arrays in the part are sequential starting at the first ID for the
* specific memory type. The array ID for the Flash memory lasts
* from 0x00 to 0x3F.
* rowAddress: Address of the sector to erase.
* rowECC: Array of bytes to write.
*
* Return:
* status:
@ -403,32 +382,45 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)
cystatus CyWriteRowConfig(uint8 arrayId, uint16 rowAddress, const uint8 * rowECC)\
{
uint32 offset;
uint16 i;
cystatus status;
/* Read the existing flash data. */
offset = ((uint32) arrayId * CYDEV_FLS_SECTOR_SIZE) +
((uint32) rowAddress * CYDEV_FLS_ROW_SIZE);
#if (CYDEV_FLS_BASE != 0u)
offset += CYDEV_FLS_BASE;
#endif
for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
/* Check whether rowBuffer pointer has been initialized by CySetFlashEEBuffer() */
if(NULL != rowBuffer)
{
rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
/* Read the existing flash data. */
offset = ((uint32)arrayId * CYDEV_FLS_SECTOR_SIZE) +
((uint32)rowAddress * CYDEV_FLS_ROW_SIZE);
#if (CYDEV_FLS_BASE != 0u)
offset += CYDEV_FLS_BASE;
#endif /* (CYDEV_FLS_BASE != 0u) */
for (i = 0u; i < CYDEV_FLS_ROW_SIZE; i++)
{
rowBuffer[i] = CY_GET_XTND_REG8((void CYFAR *)(offset + i));
}
#if(CY_PSOC3)
(void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
(void *)(uint32)rowECC,
(int16)CYDEV_ECC_ROW_SIZE);
#else
(void) memcpy((void *)&rowBuffer[CYDEV_FLS_ROW_SIZE],
(const void *)rowECC,
CYDEV_ECC_ROW_SIZE);
#endif /* (CY_PSOC3) */
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
}
else
{
status = CYRET_UNKNOWN;
}
#if(CY_PSOC3)
(void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (void *)((uint32)rowECC), (int16) CYDEV_ECC_ROW_SIZE);
#else
(void) memcpy((void *) &rowBuffer[CYDEV_FLS_ROW_SIZE], (const void *) rowECC, CYDEV_ECC_ROW_SIZE);
#endif /* (CY_PSOC3) */
status = CyWriteRowFull(arrayId, rowAddress, rowBuffer, CYDEV_FLS_ROW_SIZE + CYDEV_ECC_ROW_SIZE);
return (status);
}
@ -441,20 +433,20 @@ cystatus CySetFlashEEBuffer(uint8 * buffer)
* Function Name: CyWriteRowFull
********************************************************************************
* Summary:
* Sends a command to the SPC to load and program a row of data in flash.
* rowData array is expected to contain Flash and ECC data if needed.
* Sends a command to the SPC to load and program a row of data in flash.
* rowData array is expected to contain Flash and ECC data if needed.
*
* Parameters:
* arrayId: FLASH or EEPROM array id.
* rowData: pointer to a row of data to write.
* rowNumber: Zero based number of the row.
* rowSize: Size of the row.
* arrayId: FLASH or EEPROM array id.
* rowData: Pointer to a row of data to write.
* rowNumber: Zero based number of the row.
* rowSize: Size of the row.
*
* Return:
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
* CYRET_SUCCESS if successful.
* CYRET_LOCKED if the SPC is already in use.
* CYRET_CANCELED if command not accepted
* CYRET_UNKNOWN if there was an SPC error.
*
*******************************************************************************/
cystatus CyWriteRowFull(uint8 arrayId, uint16 rowNumber, const uint8* rowData, uint16 rowSize) \
@ -575,7 +567,7 @@ void CyFlash_SetWaitCycles(uint8 freq)
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
#if (CY_PSOC5)
if (freq <= 16u)
{
@ -598,89 +590,59 @@ void CyFlash_SetWaitCycles(uint8 freq)
((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
if (freq <= 16u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_16MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 33u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_33MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else if (freq <= 50u)
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_LESSER_OR_EQUAL_50MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
else
{
*CY_FLASH_CONTROL_PTR = ((*CY_FLASH_CONTROL_PTR & ((uint8)(~CY_FLASH_CYCLES_MASK))) |
((uint8)(CY_FLASH_GREATER_51MHz << CY_FLASH_CYCLES_MASK_SHIFT)));
}
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/* Restore global interrupt enable state */
CyExitCriticalSection(interruptState);
}
#if (CY_PSOC3 || CY_PSOC5LP)
/*******************************************************************************
* Function Name: CyEEPROM_Start
********************************************************************************
*
* Summary:
* Enable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Start(void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
/*******************************************************************************
* Function Name: CyEEPROM_Start
********************************************************************************
*
* Summary:
* Enable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Start(void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
}
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR |= CY_FLASH_PM_EE_MASK;
}
/*******************************************************************************
* Function Name: CyEEPROM_Stop
********************************************************************************
*
* Summary:
* Disable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Stop (void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
/*******************************************************************************
* Function Name: CyEEPROM_Stop
********************************************************************************
*
* Summary:
* Disable the EEPROM.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void CyEEPROM_Stop (void)
{
/* Active Power Mode */
*CY_FLASH_PM_ACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
}
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Standby Power Mode */
*CY_FLASH_PM_ALTACT_EEFLASH_PTR &= ((uint8)(~CY_FLASH_PM_EE_MASK));
}
/*******************************************************************************

114
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyFlash.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyFlash.h
* Version 3.40
* Version 4.0
*
* Description:
* Provides the function definitions for the FLASH/EEPROM.
@ -75,10 +75,8 @@ cystatus CyWriteRowData(uint8 arrayId, uint16 rowAddress, const uint8 * rowData)
void CyFlash_SetWaitCycles(uint8 freq) ;
/* EEPROM Functions */
#if (CY_PSOC3 || CY_PSOC5LP)
void CyEEPROM_Start(void) ;
void CyEEPROM_Stop(void) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void CyEEPROM_Start(void) ;
void CyEEPROM_Stop(void) ;
void CyEEPROM_ReadReserve(void) ;
void CyEEPROM_ReadRelease(void) ;
@ -87,31 +85,13 @@ void CyEEPROM_ReadRelease(void) ;
/***************************************
* Registers
***************************************/
/* Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
#if (CY_PSOC5A)
/* Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG0)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
/* Alternate Active Power Mode Configuration Register 0 */
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG0)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
/* Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ACT_EEFLASH_REG (* (reg8 *) CYREG_PM_ACT_CFG12)
#define CY_FLASH_PM_ACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_ACT_CFG12)
/* Alternate Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Alternate Active Power Mode Configuration Register 12 */
#define CY_FLASH_PM_ALTACT_EEFLASH_REG (* (reg8 *) CYREG_PM_STBY_CFG12)
#define CY_FLASH_PM_ALTACT_EEFLASH_PTR ( (reg8 *) CYREG_PM_STBY_CFG12)
/* Cache Control Register */
@ -139,19 +119,8 @@ void CyEEPROM_ReadRelease(void) ;
***************************************/
/* Power Mode Masks */
#if(CY_PSOC5A)
#define CY_FLASH_PM_FLASH_EE_MASK (0x80u)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define CY_FLASH_PM_EE_MASK (0x10u)
#define CY_FLASH_PM_FLASH_MASK (0x01u)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define CY_FLASH_PM_EE_MASK (0x10u)
#define CY_FLASH_PM_FLASH_MASK (0x01u)
/* Frequency Constants */
#if (CY_PSOC3)
@ -162,23 +131,14 @@ void CyEEPROM_ReadRelease(void) ;
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
#if (CY_PSOC5)
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
#define CY_FLASH_GREATER_51MHz (0x00u)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
#define CY_FLASH_LESSER_OR_EQUAL_16MHz (0x01u)
#define CY_FLASH_LESSER_OR_EQUAL_33MHz (0x02u)
#define CY_FLASH_LESSER_OR_EQUAL_50MHz (0x03u)
#define CY_FLASH_GREATER_51MHz (0x00u)
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
#define CY_FLASH_CYCLES_MASK_SHIFT (0x06u)
#define CY_FLASH_CYCLES_MASK ((uint8)(0x03u << (CY_FLASH_CYCLES_MASK_SHIFT)))
@ -238,37 +198,14 @@ void CyEEPROM_ReadRelease(void) ;
#define ECC_ADDR (0x80u)
#if (CY_PSOC5A)
#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_ACT_EEFLASH (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_STBY_EEFLASH (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define PM_ACT_EE_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_ACT_FLASH_PTR (CY_FLASH_PM_ACT_EEFLASH_PTR)
#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#if(CY_PSOC5A)
#define PM_FLASH_EE_MASK (CY_FLASH_PM_FLASH_EE_MASK)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC3 || CY_PSOC5LP)
#define PM_EE_MASK (CY_FLASH_PM_EE_MASK)
#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define PM_STBY_EE_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_STBY_FLASH_PTR (CY_FLASH_PM_ALTACT_EEFLASH_PTR)
#define PM_EE_MASK (CY_FLASH_PM_EE_MASK)
#define PM_FLASH_MASK (CY_FLASH_PM_FLASH_MASK)
#define FLASH_CYCLES_MASK_SHIFT (CY_FLASH_CYCLES_MASK_SHIFT)
#define FLASH_CYCLES_MASK (CY_FLASH_CYCLES_MASK)
@ -282,16 +219,7 @@ void CyEEPROM_ReadRelease(void) ;
#endif /* (CY_PSOC3) */
#if (CY_PSOC5A)
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)
#define LESSER_OR_EQUAL_50MHz (CY_FLASH_LESSER_OR_EQUAL_50MHz)
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)
#endif /* (CY_PSOC5A) */
#if (CY_PSOC5LP)
#if (CY_PSOC5)
#define LESSER_OR_EQUAL_16MHz (CY_FLASH_LESSER_OR_EQUAL_16MHz)
#define LESSER_OR_EQUAL_33MHz (CY_FLASH_LESSER_OR_EQUAL_33MHz)
@ -300,7 +228,7 @@ void CyEEPROM_ReadRelease(void) ;
#define GREATER_67MHz (CY_FLASH_GREATER_67MHz)
#define GREATER_51MHz (CY_FLASH_GREATER_51MHz)
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
#define AHUB_EE_REQ_ACK_PTR (CY_FLASH_EE_SCR_PTR)

932
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.c
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File diff suppressed because it is too large Load Diff

532
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CyLib.h
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@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CyLib.h
* Version 3.40
* Version 4.0
*
* Description:
* Provides the function definitions for the system, clocking, interrupts and
@ -34,31 +34,23 @@
#endif /* (CY_PSOC3) */
#if(!CY_PSOC5A)
#if(CYDEV_VARIABLE_VDDA == 1)
#if(CYDEV_VARIABLE_VDDA == 1)
#include "CyScBoostClk.h"
#include "CyScBoostClk.h"
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
#endif /* (!CY_PSOC5A) */
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
/* Global variable with preserved reset status */
extern uint8 CYXDATA CyResetStatus;
#if(!CY_PSOC5A)
/* Variable Vdda */
#if(CYDEV_VARIABLE_VDDA == 1)
/* Variable Vdda */
#if(CYDEV_VARIABLE_VDDA == 1)
extern uint8 CyScPumpEnabled;
extern uint8 CyScPumpEnabled;
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
#endif /* (!CY_PSOC5A) */
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
/* Do not use these definitions directly in your application */
@ -110,18 +102,15 @@ void CyXTAL_32KHZ_Stop(void) ;
cystatus CyXTAL_Start(uint8 wait) ;
void CyXTAL_Stop(void) ;
void CyXTAL_SetStartup(uint8 setting) ;
#if(!CY_PSOC5A)
void CyXTAL_EnableErrStatus(void) ;
void CyXTAL_DisableErrStatus(void) ;
uint8 CyXTAL_ReadStatus(void) ;
void CyXTAL_EnableFaultRecovery(void) ;
void CyXTAL_DisableFaultRecovery(void) ;
#endif /* (!CY_PSOC5A) */
#if(CY_PSOC3 || CY_PSOC5LP)
void CyXTAL_SetFbVoltage(uint8 setting) ;
void CyXTAL_SetWdVoltage(uint8 setting) ;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
void CyXTAL_EnableErrStatus(void) ;
void CyXTAL_DisableErrStatus(void) ;
uint8 CyXTAL_ReadStatus(void) ;
void CyXTAL_EnableFaultRecovery(void) ;
void CyXTAL_DisableFaultRecovery(void) ;
void CyXTAL_SetFbVoltage(uint8 setting) ;
void CyXTAL_SetWdVoltage(uint8 setting) ;
void CyWdtStart(uint8 ticks, uint8 lpMode) ;
void CyWdtClear(void) ;
@ -172,11 +161,7 @@ void CyVdHvAnalogDisable(void) ;
uint8 CyVdStickyStatus(uint8 mask) ;
uint8 CyVdRealTimeStatus(void) ;
#if(!CY_PSOC5A)
void CySetScPumps(uint8 enable) ;
#endif /* (!CY_PSOC5A) */
void CySetScPumps(uint8 enable) ;
/***************************************
@ -207,7 +192,6 @@ uint8 CyVdRealTimeStatus(void) ;
*******************************************************************************/
#define CY_XTAL32K_ANA_STAT (0x20u)
#define CY_CLK_XTAL32_CR_LPM (0x02u)
#define CY_CLK_XTAL32_CR_EN (0x01u)
#if(CY_PSOC3)
@ -285,49 +269,48 @@ uint8 CyVdRealTimeStatus(void) ;
/*******************************************************************************
* Variable VDDA
* Variable VDDA API Constants
*******************************************************************************/
#if(!CY_PSOC5A)
#if(CYDEV_VARIABLE_VDDA == 1)
#if(CYDEV_VARIABLE_VDDA == 1)
/* Active Power Mode Configuration Register 9 */
#define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u)
#define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u)
#define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u)
#define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u)
#define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu)
/* Active Power Mode Configuration Register 9 */
#define CY_LIB_ACT_CFG9_SWCAP0_EN (0x01u)
#define CY_LIB_ACT_CFG9_SWCAP1_EN (0x02u)
#define CY_LIB_ACT_CFG9_SWCAP2_EN (0x04u)
#define CY_LIB_ACT_CFG9_SWCAP3_EN (0x08u)
#define CY_LIB_ACT_CFG9_SWCAPS_MASK (0x0Fu)
/* Switched Cap Miscellaneous Control Register */
#define CY_LIB_SC_MISC_PUMP_FORCE (0x20u)
/* Switched Cap Miscellaneous Control Register */
#define CY_LIB_SC_MISC_PUMP_FORCE (0x20u)
/* Switched Capacitor 0 Boost Clock Selection Register */
#define CY_LIB_SC_BST_CLK_EN (0x08u)
#define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u)
/* Switched Capacitor 0 Boost Clock Selection Register */
#define CY_LIB_SC_BST_CLK_EN (0x08u)
#define CY_LIB_SC_BST_CLK_INDEX_MASK (0xF8u)
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
#endif /* (!CY_PSOC5A) */
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
/*******************************************************************************
* Clock Distribution Constants
* Clock Distribution API Constants
*******************************************************************************/
#define CY_LIB_CLKDIST_AMASK_MASK (0xF0u)
#define CY_LIB_CLKDIST_DMASK_MASK (0x00u)
#define CY_LIB_CLKDIST_LD_LOAD (0x01u)
#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u) /* Enable shadow loads */
#define CY_LIB_CLKDIST_BCFG2_MASK (0x80u)
#define CY_LIB_CLKDIST_MASTERCLK_DIV (7u)
#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u) /* Sync source is same frequency */
#define CY_LIB_CLKDIST_BCFG2_SSS (0x40u)
#define CY_LIB_CLKDIST_MSTR1_SRC_MASK (0xFCu)
#define CY_LIB_FASTCLK_IMO_DOUBLER (0x10u)
#define CY_LIB_FASTCLK_IMO_IMO (0x20u)
#define CY_LIB_CLKDIST_CR_IMO2X (0x40u)
#define CY_LIB_FASTCLK_IMO_CR_RANGE_MASK (0xF8u)
#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu)
#define CY_LIB_CLKDIST_CR_PLL_SCR_MASK (0xFCu)
#define ILO_CONTROL_PD_MODE (0x10u)
/* CyILO_SetPowerMode() */
#define CY_ILO_CONTROL_PD_MODE (0x10u)
#define CY_ILO_CONTROL_PD_POSITION (4u)
#define CY_ILO_SOURCE_100K (0u)
#define CY_ILO_SOURCE_33K (1u)
@ -341,7 +324,6 @@ uint8 CyVdRealTimeStatus(void) ;
#define CY_ILO_SOURCE_33K_SET (0x04u)
#define CY_ILO_SOURCE_100K_SET (0x00u)
#define CY_MASTER_SOURCE_IMO (0u)
#define CY_MASTER_SOURCE_PLL (1u)
#define CY_MASTER_SOURCE_XTAL (2u)
@ -350,16 +332,21 @@ uint8 CyVdRealTimeStatus(void) ;
#define CY_IMO_SOURCE_IMO (0u)
#define CY_IMO_SOURCE_XTAL (1u)
#define CY_IMO_SOURCE_DSI (2u)
#define IMO_PM_ENABLE (0x10u) /* Enable IMO clock source. */
#define FASTCLK_IMO_USBCLK_ON_SET (0x40u)
#define CLOCK_IMO_3MHZ_VALUE (0x03u)
#define CLOCK_IMO_6MHZ_VALUE (0x01u)
#define CLOCK_IMO_12MHZ_VALUE (0x00u)
#define CLOCK_IMO_24MHZ_VALUE (0x02u)
#define CLOCK_IMO_48MHZ_VALUE (0x04u)
#define CLOCK_IMO_62MHZ_VALUE (0x05u)
#define CLOCK_IMO_74MHZ_VALUE (0x06u)
/* CyIMO_Start() */
#define CY_LIB_PM_ACT_CFG0_IMO_EN (0x10u)
#define CY_LIB_PM_STBY_CFG0_IMO_EN (0x10u)
#define CY_LIB_CLK_IMO_FTW_TIMEOUT (0x00u)
#define CY_LIB_IMO_3MHZ_VALUE (0x03u)
#define CY_LIB_IMO_6MHZ_VALUE (0x01u)
#define CY_LIB_IMO_12MHZ_VALUE (0x00u)
#define CY_LIB_IMO_24MHZ_VALUE (0x02u)
#define CY_LIB_IMO_48MHZ_VALUE (0x04u)
#define CY_LIB_IMO_62MHZ_VALUE (0x05u)
#define CY_LIB_IMO_74MHZ_VALUE (0x06u)
/* CyIMO_SetFreq() */
#define CY_IMO_FREQ_3MHZ (0u)
@ -367,42 +354,48 @@ uint8 CyVdRealTimeStatus(void) ;
#define CY_IMO_FREQ_12MHZ (2u)
#define CY_IMO_FREQ_24MHZ (3u)
#define CY_IMO_FREQ_48MHZ (4u)
#if(!CY_PSOC5A)
#define CY_IMO_FREQ_62MHZ (5u)
#endif /* (!CY_PSOC5A) */
#define CY_IMO_FREQ_62MHZ (5u)
#if(CY_PSOC5)
#define CY_IMO_FREQ_74MHZ (6u)
#endif /* (CY_PSOC5) */
#define CY_IMO_FREQ_USB (8u)
#define CY_LIB_IMO_USBCLK_ON_SET (0x40u)
#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu)
#define CLKDIST_DIV_POSITION (4u)
#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu)
#define CLOCK_USB_ENABLE (0x02u)
#define CLOCK_IMO_OUT_X2 (0x10u)
#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2))
/* CyCpuClk_SetDivider() */
#define CY_LIB_CLKDIST_DIV_POSITION (4u)
#define CY_LIB_CLKDIST_MSTR1_DIV_MASK (0x0Fu)
/* CyIMO_SetTrimValue() */
#define CY_LIB_USB_CLK_EN (0x02u)
/* CyPLL_OUT_SetSource() - parameters */
#define CY_PLL_SOURCE_IMO (0u)
#define CY_PLL_SOURCE_XTAL (1u)
#define CY_PLL_SOURCE_DSI (2u)
#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI))
#define ILO_CONTROL_PD_POSITION (4u)
#define ILO_CONTROL_1KHZ_ON (0x02u)
#define ILO_CONTROL_100KHZ_ON (0x04u)
#define ILO_CONTROL_33KHZ_ON (0x20u)
/* CyILO_[Start|Stop][1|100K](), CyILO_[Enable|Disable]33K() */
#define CY_LIB_SLOWCLK_ILO_CR0_EN_1KHZ (0x02u)
#define CY_LIB_SLOWCLK_ILO_CR0_EN_33KHZ (0x20u)
#define CY_LIB_SLOWCLK_ILO_CR0_EN_100KHZ (0x04u)
#define USB_CLKDIST_CONFIG_MASK (0x03u)
#define USB_CLK_IMO2X (0x00u)
#define USB_CLK_IMO (0x01u)
#define USB_CLK_PLL (0x02u)
#define USB_CLK_DSI (0x03u)
#define USB_CLK_DIV2_ON (0x04u)
#define USB_CLK_STOP_FLAG (0x00u)
#define USB_CLK_START_FLAG (0x01u)
#define FTW_CLEAR_ALL_BITS (0x00u) /* To clear all bits of PM_TW_CFG2 */
#define FTW_CLEAR_FTW_BITS (0xFCu) /* To clear FTW bits of PM_TW_CFG2 */
#define FTW_ENABLE (0x01u) /* To enable FTW, no interrupt */
/* CyUsbClk_SetSource() */
#define CY_LIB_CLKDIST_UCFG_SRC_SEL_MASK (0x03u)
/* CyUsbClk_SetSource() - parameters */
#define CY_LIB_USB_CLK_IMO2X (0x00u)
#define CY_LIB_USB_CLK_IMO (0x01u)
#define CY_LIB_USB_CLK_PLL (0x02u)
#define CY_LIB_USB_CLK_DSI (0x03u)
/* CyUSB_PowerOnCheck() */
#define CY_ACT_USB_ENABLED (0x01u)
#define CY_ALT_ACT_USB_ENABLED (0x01u)
@ -412,6 +405,72 @@ uint8 CyVdRealTimeStatus(void) ;
***************************************/
/*******************************************************************************
* System Registers
*******************************************************************************/
/* Software Reset Control Register */
#define CY_LIB_RESET_CR2_REG (* (reg8 *) CYREG_RESET_CR2)
#define CY_LIB_RESET_CR2_PTR ( (reg8 *) CYREG_RESET_CR2)
/* Timewheel Configuration Register 0 */
#define CY_LIB_PM_TW_CFG0_REG (*(reg8 *) CYREG_PM_TW_CFG0)
#define CY_LIB_PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)
/* Timewheel Configuration Register 2 */
#define CY_LIB_PM_TW_CFG2_REG (*(reg8 *) CYREG_PM_TW_CFG2)
#define CY_LIB_PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)
/* USB Configuration Register */
#define CY_LIB_CLKDIST_UCFG_REG (*(reg8 *) CYREG_CLKDIST_UCFG)
#define CY_LIB_CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)
/* Internal Main Oscillator Trim Register 1 */
#define CY_LIB_IMO_TR1_REG (*(reg8 *) CYREG_IMO_TR1)
#define CY_LIB_IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)
/* USB control 1 Register */
#define CY_LIB_USB_CR1_REG (*(reg8 *) CYREG_USB_CR1 )
#define CY_LIB_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )
/* Active Power Mode Configuration Register 0 */
#define CY_LIB_PM_ACT_CFG0_REG (*(reg8 *) CYREG_PM_ACT_CFG0)
#define CY_LIB_PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
/* Standby Power Mode Configuration Register 0 */
#define CY_LIB_PM_STBY_CFG0_REG (*(reg8 *) CYREG_PM_STBY_CFG0)
#define CY_LIB_PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
/* Active Power Mode Configuration Register 5 */
#define CY_LIB_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )
#define CY_LIB_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )
/* Standby Power Mode Configuration Register 5 */
#define CY_LIB_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )
#define CY_LIB_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )
/* CyIMO_SetTrimValue() */
#if(CY_PSOC3)
#define CY_LIB_TRIM_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define CY_LIB_TRIM_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define CY_LIB_TRIM_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define CY_LIB_TRIM_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define CY_LIB_TRIM_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define CY_LIB_TRIM_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define CY_LIB_TRIM_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#define CY_LIB_TRIM_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#else
#define CY_LIB_TRIM_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define CY_LIB_TRIM_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define CY_LIB_TRIM_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define CY_LIB_TRIM_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define CY_LIB_TRIM_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define CY_LIB_TRIM_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define CY_LIB_TRIM_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#define CY_LIB_TRIM_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#endif /* (CY_PSOC3) */
/*******************************************************************************
* PLL Registers
*******************************************************************************/
@ -442,16 +501,16 @@ uint8 CyVdRealTimeStatus(void) ;
*******************************************************************************/
/* External MHz Crystal Oscillator Status and Control Register */
#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
#define CY_CLK_XMHZ_CSR_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CSR)
#define CY_CLK_XMHZ_CSR_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CSR)
/* External MHz Crystal Oscillator Configuration Register 0 */
#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
#define CY_CLK_XMHZ_CFG0_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
#define CY_CLK_XMHZ_CFG0_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG0)
/* External MHz Crystal Oscillator Configuration Register 1 */
#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
#define CY_CLK_XMHZ_CFG1_REG (*(reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
#define CY_CLK_XMHZ_CFG1_PTR ( (reg8 *) CYREG_FASTCLK_XMHZ_CFG1)
/*******************************************************************************
@ -459,20 +518,20 @@ uint8 CyVdRealTimeStatus(void) ;
*******************************************************************************/
/* 32 kHz Watch Crystal Oscillator Trim Register */
#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR)
#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR)
#define CY_CLK_XTAL32_TR_REG (*(reg8 *) CYREG_X32_TR)
#define CY_CLK_XTAL32_TR_PTR ( (reg8 *) CYREG_X32_TR)
/* External 32kHz Crystal Oscillator Test Register */
#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST)
#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST)
#define CY_CLK_XTAL32_TST_REG (*(reg8 *) CYREG_SLOWCLK_X32_TST)
#define CY_CLK_XTAL32_TST_PTR ( (reg8 *) CYREG_SLOWCLK_X32_TST)
/* External 32kHz Crystal Oscillator Control Register */
#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR)
#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR)
#define CY_CLK_XTAL32_CR_REG (*(reg8 *) CYREG_SLOWCLK_X32_CR)
#define CY_CLK_XTAL32_CR_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CR)
/* External 32kHz Crystal Oscillator Configuration Register */
#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
#define CY_CLK_XTAL32_CFG_REG (*(reg8 *) CYREG_SLOWCLK_X32_CFG)
#define CY_CLK_XTAL32_CFG_PTR ( (reg8 *) CYREG_SLOWCLK_X32_CFG)
/*******************************************************************************
@ -492,56 +551,52 @@ uint8 CyVdRealTimeStatus(void) ;
* LVI/HVI Registers
*******************************************************************************/
#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYDEV_RESET_CR0)
#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYDEV_RESET_CR0)
#define CY_VD_LVI_TRIP_REG (* (reg8 *) CYREG_RESET_CR0)
#define CY_VD_LVI_TRIP_PTR ( (reg8 *) CYREG_RESET_CR0)
#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR1)
#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR1)
#define CY_VD_LVI_HVI_CONTROL_REG (* (reg8 *) CYREG_RESET_CR1)
#define CY_VD_LVI_HVI_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR1)
#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYDEV_RESET_CR3)
#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYDEV_RESET_CR3)
#define CY_VD_PRES_CONTROL_REG (* (reg8 *) CYREG_RESET_CR3)
#define CY_VD_PRES_CONTROL_PTR ( (reg8 *) CYREG_RESET_CR3)
#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR0)
#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR0)
#define CY_VD_PERSISTENT_STATUS_REG (* (reg8 *) CYREG_RESET_SR0)
#define CY_VD_PERSISTENT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR0)
#define CY_VD_RT_STATUS_REG (* (reg8 *) CYDEV_RESET_SR2)
#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYDEV_RESET_SR2)
#define CY_VD_RT_STATUS_REG (* (reg8 *) CYREG_RESET_SR2)
#define CY_VD_RT_STATUS_PTR ( (reg8 *) CYREG_RESET_SR2)
/*******************************************************************************
* Variable VDDA
*******************************************************************************/
#if(!CY_PSOC5A)
#if(CYDEV_VARIABLE_VDDA == 1)
#if(CYDEV_VARIABLE_VDDA == 1)
/* Active Power Mode Configuration Register 9 */
#define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 )
#define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 )
/* Active Power Mode Configuration Register 9 */
#define CY_LIB_ACT_CFG9_REG (* (reg8 *) CYREG_PM_ACT_CFG9 )
#define CY_LIB_ACT_CFG9_PTR ( (reg8 *) CYREG_PM_ACT_CFG9 )
/* Switched Capacitor 0 Boost Clock Selection Register */
#define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST )
#define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST )
/* Switched Capacitor 0 Boost Clock Selection Register */
#define CY_LIB_SC0_BST_REG (* (reg8 *) CYREG_SC0_BST )
#define CY_LIB_SC0_BST_PTR ( (reg8 *) CYREG_SC0_BST )
/* Switched Capacitor 1 Boost Clock Selection Register */
#define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST )
#define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST )
/* Switched Capacitor 1 Boost Clock Selection Register */
#define CY_LIB_SC1_BST_REG (* (reg8 *) CYREG_SC1_BST )
#define CY_LIB_SC1_BST_PTR ( (reg8 *) CYREG_SC1_BST )
/* Switched Capacitor 2 Boost Clock Selection Register */
#define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST )
#define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST )
/* Switched Capacitor 2 Boost Clock Selection Register */
#define CY_LIB_SC2_BST_REG (* (reg8 *) CYREG_SC2_BST )
#define CY_LIB_SC2_BST_PTR ( (reg8 *) CYREG_SC2_BST )
/* Switched Capacitor 3 Boost Clock Selection Register */
#define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST )
#define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST )
/* Switched Capacitor 3 Boost Clock Selection Register */
#define CY_LIB_SC3_BST_REG (* (reg8 *) CYREG_SC3_BST )
#define CY_LIB_SC3_BST_PTR ( (reg8 *) CYREG_SC3_BST )
/* Switched Cap Miscellaneous Control Register */
#define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC )
#define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC )
/* Switched Cap Miscellaneous Control Register */
#define CY_LIB_SC_MISC_REG (* (reg8 *) CYREG_SC_MISC )
#define CY_LIB_SC_MISC_PTR ( (reg8 *) CYREG_SC_MISC )
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
#endif /* (!CY_PSOC5A) */
#endif /* (CYDEV_VARIABLE_VDDA == 1) */
/*******************************************************************************
@ -596,71 +651,9 @@ uint8 CyVdRealTimeStatus(void) ;
#define CY_LIB_CLKDIST_CR_REG (*(reg8 *) CYREG_CLKDIST_CR)
#define CY_LIB_CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)
#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)
#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG)
#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)
#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0)
#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)
#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2)
#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)
#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1)
#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR)
#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)
#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1)
#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )
#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 )
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)
#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0)
#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2)
#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2)
/* Active Power Mode Configuration Register 5 */
#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )
#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )
/* Standby Power Mode Configuration Register 5 */
#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )
#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )
#if(CY_PSOC3)
#define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#else
#define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#endif /* (CY_PSOC3) */
#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)
#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG)
/* Internal Low-speed Oscillator Control Register 0 */
#define CY_LIB_SLOWCLK_ILO_CR0_REG (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
#define CY_LIB_SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
/*******************************************************************************
@ -709,33 +702,33 @@ uint8 CyVdRealTimeStatus(void) ;
#define CY_INT_ENABLE_REG (* (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_ENABLE_PTR ( (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN0_REG (* (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN0_PTR ( (reg8 *) CYREG_INTC_SET_EN0)
#define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1)
#define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1)
#define CY_INT_SET_EN1_REG (* (reg8 *) CYREG_INTC_SET_EN1)
#define CY_INT_SET_EN1_PTR ( (reg8 *) CYREG_INTC_SET_EN1)
#define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2)
#define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2)
#define CY_INT_SET_EN2_REG (* (reg8 *) CYREG_INTC_SET_EN2)
#define CY_INT_SET_EN2_PTR ( (reg8 *) CYREG_INTC_SET_EN2)
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)
#define CY_INT_SET_EN3_REG (* (reg8 *) CYREG_INTC_SET_EN3)
#define CY_INT_SET_EN3_PTR ( (reg8 *) CYREG_INTC_SET_EN3)
/* Interrrupt Controller Clear Enable Registers */
#define CY_INT_CLEAR_REG (* (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLEAR_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN0_REG (* (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN0_PTR ( (reg8 *) CYREG_INTC_CLR_EN0)
#define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1)
#define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1)
#define CY_INT_CLR_EN1_REG (* (reg8 *) CYREG_INTC_CLR_EN1)
#define CY_INT_CLR_EN1_PTR ( (reg8 *) CYREG_INTC_CLR_EN1)
#define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2)
#define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2)
#define CY_INT_CLR_EN2_REG (* (reg8 *) CYREG_INTC_CLR_EN2)
#define CY_INT_CLR_EN2_PTR ( (reg8 *) CYREG_INTC_CLR_EN2)
#define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3)
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)
#define CY_INT_CLR_EN3_REG (* (reg8 *) CYREG_INTC_CLR_EN3)
#define CY_INT_CLR_EN3_PTR ( (reg8 *) CYREG_INTC_CLR_EN3)
/* Interrrupt Controller Set Pend Registers */
@ -810,7 +803,7 @@ uint8 CyVdRealTimeStatus(void) ;
#if defined(__ARMCC_VERSION)
#define CyGlobalIntEnable {__enable_irq();}
#define CyGlobalIntDisable {__disable_irq();}
#elif defined(__GNUC__)
#elif defined(__GNUC__) || defined (__ICCARM__)
#define CyGlobalIntEnable {__asm("CPSIE i");}
#define CyGlobalIntDisable {__asm("CPSID i");}
#elif defined(__C51__)
@ -824,6 +817,10 @@ uint8 CyVdRealTimeStatus(void) ;
CY_NOP; \
EA = 0u;\
}
#else
#error No compiler toolchain defined
#define CyGlobalIntEnable
#define CyGlobalIntDisable
#endif /* (__ARMCC_VERSION) */
@ -840,13 +837,12 @@ uint8 CyVdRealTimeStatus(void) ;
#define CYDEV_CHIP_REV_ACTUAL (CY_GET_REG8(CYREG_MLOGIC_REV_ID))
#endif /* (CYREG_MLOGIC_REV_ID_REV_ID) */
#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2)
/*******************************************************************************
* System API constants
*******************************************************************************/
#define CY_CACHE_CONTROL_FLUSH (0x0004u)
#define CY_LIB_RESET_CR2_RESET (0x01u)
/*******************************************************************************
@ -1057,9 +1053,7 @@ uint8 CyVdRealTimeStatus(void) ;
#define X32_CONTROL_LPM (CY_CLK_XTAL32_CR_LPM)
#define X32_CONTROL_LPM_POSITION (1u)
#define X32_CONTROL_X32EN (CY_CLK_XTAL32_CR_EN)
#if(CY_PSOC3 || CY_PSOC5LP)
#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define X32_CONTROL_PDBEN (CY_CLK_XTAL32_CR_PDBEN)
#define X32_TR_DPMODE (CY_CLK_XTAL32_TR_STARTUP)
#define X32_TR_CLEAR (CY_CLK_XTAL32_TR_POWERDOWN)
#define X32_TR_HPMODE (CY_CLK_XTAL32_TR_HIGH_POWER)
@ -1195,6 +1189,92 @@ uint8 CyVdRealTimeStatus(void) ;
#define CLKDIST_CR_PTR ( (reg8 *) CYREG_CLKDIST_CR)
#define CLKDIST_CR (*(reg8 *) CYREG_CLKDIST_CR)
/*******************************************************************************
* Following code are OBSOLETE and must not be used starting from cy_boot 3.50
*******************************************************************************/
#define IMO_PM_ENABLE (0x10u)
#define PM_ACT_CFG0_PTR ( (reg8 *) CYREG_PM_ACT_CFG0)
#define PM_ACT_CFG0 (*(reg8 *) CYREG_PM_ACT_CFG0)
#define SLOWCLK_ILO_CR0_PTR ( (reg8 *) CYREG_SLOWCLK_ILO_CR0)
#define SLOWCLK_ILO_CR0 (*(reg8 *) CYREG_SLOWCLK_ILO_CR0)
#define ILO_CONTROL_PD_MODE (0x10u)
#define ILO_CONTROL_PD_POSITION (4u)
#define ILO_CONTROL_1KHZ_ON (0x02u)
#define ILO_CONTROL_100KHZ_ON (0x04u)
#define ILO_CONTROL_33KHZ_ON (0x20u)
#define PM_TW_CFG0_PTR ( (reg8 *) CYREG_PM_TW_CFG0)
#define PM_TW_CFG0 (*(reg8 *) CYREG_PM_TW_CFG0)
#define PM_TW_CFG2_PTR ( (reg8 *) CYREG_PM_TW_CFG2)
#define PM_TW_CFG2 (*(reg8 *) CYREG_PM_TW_CFG2)
#define RESET_CR2 ((reg8 *) CYREG_RESET_CR2)
#define FASTCLK_IMO_USBCLK_ON_SET (0x40u)
#define CLOCK_IMO_3MHZ_VALUE (0x03u)
#define CLOCK_IMO_6MHZ_VALUE (0x01u)
#define CLOCK_IMO_12MHZ_VALUE (0x00u)
#define CLOCK_IMO_24MHZ_VALUE (0x02u)
#define CLOCK_IMO_48MHZ_VALUE (0x04u)
#define CLOCK_IMO_62MHZ_VALUE (0x05u)
#define CLOCK_IMO_74MHZ_VALUE (0x06u)
#define CLKDIST_DIV_POSITION (4u)
#define CLKDIST_MSTR1_DIV_CLEAR (0x0Fu)
#define SFR_USER_CPUCLK_DIV_MASK (0x0Fu)
#define CLOCK_USB_ENABLE (0x02u)
#define CLOCK_IMO_OUT_X2 (0x10u)
#define CLOCK_IMO_OUT_X1 ((uint8)(~CLOCK_IMO_OUT_X2))
#define CLOCK_IMO2X_ECO ((uint8)(~CLOCK_IMO2X_DSI))
#define USB_CLKDIST_CONFIG_MASK (0x03u)
#define USB_CLK_IMO2X (0x00u)
#define USB_CLK_IMO (0x01u)
#define USB_CLK_PLL (0x02u)
#define USB_CLK_DSI (0x03u)
#define USB_CLK_DIV2_ON (0x04u)
#define USB_CLK_STOP_FLAG (0x00u)
#define USB_CLK_START_FLAG (0x01u)
#define FTW_CLEAR_ALL_BITS (0x00u)
#define FTW_CLEAR_FTW_BITS (0xFCu)
#define FTW_ENABLE (0x01u)
#define PM_STBY_CFG0_PTR ( (reg8 *) CYREG_PM_STBY_CFG0)
#define PM_STBY_CFG0 (*(reg8 *) CYREG_PM_STBY_CFG0)
#define PM_AVAIL_CR2_PTR ( (reg8 *) CYREG_PM_AVAIL_CR2)
#define PM_AVAIL_CR2 (*(reg8 *) CYREG_PM_AVAIL_CR2)
#define CLKDIST_UCFG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)
#define CLKDIST_UCFG (*(reg8 *) CYREG_CLKDIST_UCFG)
#define CLKDIST_MSTR1_PTR ( (reg8 *) CYREG_CLKDIST_MSTR1)
#define CLKDIST_MSTR1 (*(reg8 *) CYREG_CLKDIST_MSTR1)
#define SFR_USER_CPUCLK_DIV_PTR ((void far *) CYREG_SFR_USER_CPUCLK_DIV)
#define IMO_TR1_PTR ( (reg8 *) CYREG_IMO_TR1)
#define IMO_TR1 (*(reg8 *) CYREG_IMO_TR1)
#define CLOCK_CONTROL ( (reg8 *) CYREG_CLKDIST_CR)
#define CY_USB_CR1_PTR ( (reg8 *) CYREG_USB_CR1 )
#define CY_USB_CR1 (*(reg8 *) CYREG_USB_CR1 )
#define USB_CLKDIST_CONFIG_PTR ( (reg8 *) CYREG_CLKDIST_UCFG)
#define USB_CLKDIST_CONFIG (*(reg8 *) CYREG_CLKDIST_UCFG)
#define CY_PM_ACT_CFG5_REG (* (reg8 *) CYREG_PM_ACT_CFG5 )
#define CY_PM_ACT_CFG5_PTR ( (reg8 *) CYREG_PM_ACT_CFG5 )
#define CY_PM_STBY_CFG5_REG (* (reg8 *) CYREG_PM_STBY_CFG5 )
#define CY_PM_STBY_CFG5_PTR ( (reg8 *) CYREG_PM_STBY_CFG5 )
#if(CY_PSOC3)
#define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define FLSHID_CUST_TABLES_IMO_USB_PTR ((void far *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#define FLSHID_MFG_CFG_IMO_TR1_PTR ((void far *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#else
#define FLSHID_CUST_TABLES_IMO_3MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_3MHZ)
#define FLSHID_CUST_TABLES_IMO_6MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_6MHZ)
#define FLSHID_CUST_TABLES_IMO_12MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_12MHZ)
#define FLSHID_CUST_TABLES_IMO_24MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_24MHZ)
#define FLSHID_CUST_TABLES_IMO_67MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_67MHZ)
#define FLSHID_CUST_TABLES_IMO_80MHZ_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_80MHZ)
#define FLSHID_CUST_TABLES_IMO_USB_PTR ((reg8 *) CYREG_FLSHID_CUST_TABLES_IMO_USB)
#define FLSHID_MFG_CFG_IMO_TR1_PTR ((reg8 *) (CYREG_FLSHID_MFG_CFG_IMO_TR1 + 1u))
#endif /* (CY_PSOC3) */
#endif /* (CY_BOOT_CYLIB_H) */

32
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CySpc.c
* Version 3.40
* Version 4.0
*
* Description:
* Provides an API for the System Performance Component.
@ -48,7 +48,7 @@
uint8 SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5LP)
#if(CY_PSOC5)
/***************************************************************************
* The wait-state pipeline must be enabled prior to accessing the SPC
@ -57,9 +57,9 @@ uint8 SpcLockState = CY_SPC_UNLOCKED;
* function, which must be called after SPC transaction, restores original
* state.
***************************************************************************/
static uint8 spcWaitPipeBypass = 0u;
static uint32 spcWaitPipeBypass = 0u;
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/*******************************************************************************
@ -175,7 +175,8 @@ uint8 CySpcReadData(uint8 buffer[], uint8 size)
* CYRET_BAD_PARAM
*
*******************************************************************************/
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
{
cystatus status = CYRET_STARTED;
uint8 i;
@ -312,7 +313,8 @@ cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size)
* CYRET_LOCKED
*
*******************************************************************************/
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
{
cystatus status = CYRET_STARTED;
@ -420,11 +422,7 @@ cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber)
* CYRET_LOCKED
*
*******************************************************************************/
#if(CY_PSOC5A)
cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect)
#else
cystatus CySpcGetTemp(uint8 numSamples)
#endif /* (CY_PSOC5A) */
{
cystatus status = CYRET_STARTED;
@ -439,12 +437,6 @@ cystatus CySpcGetTemp(uint8 numSamples)
if(CY_SPC_BUSY)
{
CY_SPC_CPU_DATA_REG = numSamples;
#if(CY_PSOC5A)
CY_SPC_CPU_DATA_REG = HI8(timerPeriod);
CY_SPC_CPU_DATA_REG = LO8(timerPeriod);
CY_SPC_CPU_DATA_REG = clkDivSelect;
#endif /* (CY_PSOC5A) */
}
else
{
@ -488,7 +480,7 @@ cystatus CySpcLock(void)
SpcLockState = CY_SPC_LOCKED;
status = CYRET_SUCCESS;
#if(CY_PSOC5LP)
#if(CY_PSOC5)
if(0u != (CY_SPC_CPU_WAITPIPE_REG & CY_SPC_CPU_WAITPIPE_BYPASS))
{
@ -503,7 +495,7 @@ cystatus CySpcLock(void)
spcWaitPipeBypass = CY_SPC_CPU_WAITPIPE_BYPASS;
}
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
}
/* Exit critical section */
@ -537,7 +529,7 @@ void CySpcUnlock(void)
/* Release the SPC object */
SpcLockState = CY_SPC_UNLOCKED;
#if(CY_PSOC5LP)
#if(CY_PSOC5)
if(CY_SPC_CPU_WAITPIPE_BYPASS == spcWaitPipeBypass)
{
@ -552,7 +544,7 @@ void CySpcUnlock(void)
spcWaitPipeBypass = 0u;
}
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/* Exit critical section */
CyExitCriticalSection(interruptState);

25
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/CySpc.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: CySpc.c
* Version 3.40
* Version 4.0
*
* Description:
* Provides definitions for the System Performance Component API.
@ -34,18 +34,13 @@ extern uint8 SpcLockState;
void CySpcStart(void);
void CySpcStop(void);
uint8 CySpcReadData(uint8 buffer[], uint8 size);
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size) ;
cystatus CySpcLoadMultiByte(uint8 array, uint16 address, const uint8 buffer[], uint8 size)\
;
cystatus CySpcLoadRow(uint8 array, const uint8 buffer[], uint16 size);
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude) ;
cystatus CySpcWriteRow(uint8 array, uint16 address, uint8 tempPolarity, uint8 tempMagnitude)\
;
cystatus CySpcEraseSector(uint8 array, uint8 sectorNumber);
#if(CY_PSOC5A)
cystatus CySpcGetTemp(uint8 numSamples, uint16 timerPeriod, uint8 clkDivSelect);
#else
cystatus CySpcGetTemp(uint8 numSamples);
#endif /* (CY_PSOC5A) */
cystatus CySpcGetTemp(uint8 numSamples);
cystatus CySpcLock(void);
void CySpcUnlock(void);
@ -91,12 +86,12 @@ void CySpcUnlock(void);
#define CY_SPC_STATUS_TADC_INPUT (0x0Du) /* Invalid input value for Get Temp & Get ADC commands */
#define CY_SPC_STATUS_BUSY (0xFFu) /* SPC is busy */
#if(CY_PSOC5LP)
#if(CY_PSOC5)
/* Wait-state pipeline */
#define CY_SPC_CPU_WAITPIPE_BYPASS ((uint32)0x01u)
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/***************************************
@ -119,13 +114,13 @@ void CySpcUnlock(void);
#define CY_SPC_PM_STBY_REG (* (reg8 *) CYREG_PM_STBY_CFG0 )
#define CY_SPC_PM_STBY_PTR ( (reg8 *) CYREG_PM_STBY_CFG0 )
#if(CY_PSOC5LP)
#if(CY_PSOC5)
/* Wait State Pipeline */
#define CY_SPC_CPU_WAITPIPE_REG (* (reg32 *) CYREG_PANTHER_WAITPIPE )
#define CY_SPC_CPU_WAITPIPE_PTR ( (reg32 *) CYREG_PANTHER_WAITPIPE )
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/***************************************

137
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN.c Normal file
View File

@ -0,0 +1,137 @@
/*******************************************************************************
* File Name: SCSI_ATN.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_ATN.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_ATN_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_Write(uint8 value)
{
uint8 staticBits = (SCSI_ATN_DR & (uint8)(~SCSI_ATN_MASK));
SCSI_ATN_DR = staticBits | ((uint8)(value << SCSI_ATN_SHIFT) & SCSI_ATN_MASK);
}
/*******************************************************************************
* Function Name: SCSI_ATN_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_ATN_0, mode);
}
/*******************************************************************************
* Function Name: SCSI_ATN_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_ATN_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_ATN_Read(void)
{
return (SCSI_ATN_PS & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_ATN_ReadDataReg(void)
{
return (SCSI_ATN_DR & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_ATN_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_ATN_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_ATN_ClearInterrupt(void)
{
return (SCSI_ATN_INTSTAT & SCSI_ATN_MASK) >> SCSI_ATN_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_ATN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_ATN_H) /* Pins SCSI_ATN_H */
#define CY_PINS_SCSI_ATN_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_ATN_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_ATN__PORT == 15 && ((SCSI_ATN__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_ATN_Write(uint8 value) ;
void SCSI_ATN_SetDriveMode(uint8 mode) ;
uint8 SCSI_ATN_ReadDataReg(void) ;
uint8 SCSI_ATN_Read(void) ;
uint8 SCSI_ATN_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_ATN_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_ATN_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_ATN_DM_RES_UP PIN_DM_RES_UP
#define SCSI_ATN_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_ATN_DM_OD_LO PIN_DM_OD_LO
#define SCSI_ATN_DM_OD_HI PIN_DM_OD_HI
#define SCSI_ATN_DM_STRONG PIN_DM_STRONG
#define SCSI_ATN_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_ATN_MASK SCSI_ATN__MASK
#define SCSI_ATN_SHIFT SCSI_ATN__SHIFT
#define SCSI_ATN_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_ATN_PS (* (reg8 *) SCSI_ATN__PS)
/* Data Register */
#define SCSI_ATN_DR (* (reg8 *) SCSI_ATN__DR)
/* Port Number */
#define SCSI_ATN_PRT_NUM (* (reg8 *) SCSI_ATN__PRT)
/* Connect to Analog Globals */
#define SCSI_ATN_AG (* (reg8 *) SCSI_ATN__AG)
/* Analog MUX bux enable */
#define SCSI_ATN_AMUX (* (reg8 *) SCSI_ATN__AMUX)
/* Bidirectional Enable */
#define SCSI_ATN_BIE (* (reg8 *) SCSI_ATN__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_ATN_BIT_MASK (* (reg8 *) SCSI_ATN__BIT_MASK)
/* Bypass Enable */
#define SCSI_ATN_BYP (* (reg8 *) SCSI_ATN__BYP)
/* Port wide control signals */
#define SCSI_ATN_CTL (* (reg8 *) SCSI_ATN__CTL)
/* Drive Modes */
#define SCSI_ATN_DM0 (* (reg8 *) SCSI_ATN__DM0)
#define SCSI_ATN_DM1 (* (reg8 *) SCSI_ATN__DM1)
#define SCSI_ATN_DM2 (* (reg8 *) SCSI_ATN__DM2)
/* Input Buffer Disable Override */
#define SCSI_ATN_INP_DIS (* (reg8 *) SCSI_ATN__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_ATN_LCD_COM_SEG (* (reg8 *) SCSI_ATN__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_ATN_LCD_EN (* (reg8 *) SCSI_ATN__LCD_EN)
/* Slew Rate Control */
#define SCSI_ATN_SLW (* (reg8 *) SCSI_ATN__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_ATN_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_ATN__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_ATN_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_ATN__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_ATN_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL0)
#define SCSI_ATN_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_ATN_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL0)
#define SCSI_ATN_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_ATN__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_ATN_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_ATN__PRTDSI__SYNC_OUT)
#if defined(SCSI_ATN__INTSTAT) /* Interrupt Registers */
#define SCSI_ATN_INTSTAT (* (reg8 *) SCSI_ATN__INTSTAT)
#define SCSI_ATN_SNAP (* (reg8 *) SCSI_ATN__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_ATN_H */
/* [] END OF FILE */

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/*******************************************************************************
* File Name: SCSI_ATN_ISR.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SCSI_ATN_ISR.h>
#if !defined(SCSI_ATN_ISR__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SCSI_ATN_ISR_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_Start(void)
{
/* For all we know the interrupt is active. */
SCSI_ATN_ISR_Disable();
/* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */
SCSI_ATN_ISR_SetVector(&SCSI_ATN_ISR_Interrupt);
/* Set the priority. */
SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_ATN_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SCSI_ATN_ISR_Disable();
/* Set the ISR to point to the SCSI_ATN_ISR Interrupt. */
SCSI_ATN_ISR_SetVector(address);
/* Set the priority. */
SCSI_ATN_ISR_SetPriority((uint8)SCSI_ATN_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_ATN_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_Stop(void)
{
/* Disable this interrupt. */
SCSI_ATN_ISR_Disable();
/* Set the ISR to point to the passive one. */
SCSI_ATN_ISR_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SCSI_ATN_ISR.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SCSI_ATN_ISR_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SCSI_ATN_ISR_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SCSI_ATN_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_ATN_ISR_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SCSI_ATN_ISR_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_ATN_ISR__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SCSI_ATN_ISR_Start
* or SCSI_ATN_ISR_StartEx will override any effect this method
* would have had. This method should only be called after
* SCSI_ATN_ISR_Start or SCSI_ATN_ISR_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_SetPriority(uint8 priority)
{
*SCSI_ATN_ISR_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SCSI_ATN_ISR_GetPriority(void)
{
uint8 priority;
priority = *SCSI_ATN_ISR_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_Enable(void)
{
/* Enable the general interrupt. */
*SCSI_ATN_ISR_INTC_SET_EN = SCSI_ATN_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SCSI_ATN_ISR_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SCSI_ATN_ISR_INTC_SET_EN & (uint32)SCSI_ATN_ISR__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_Disable(void)
{
/* Disable the general interrupt. */
*SCSI_ATN_ISR_INTC_CLR_EN = SCSI_ATN_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_SetPending(void)
{
*SCSI_ATN_ISR_INTC_SET_PD = SCSI_ATN_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_ATN_ISR_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_ATN_ISR_ClearPending(void)
{
*SCSI_ATN_ISR_INTC_CLR_PD = SCSI_ATN_ISR__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
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/*******************************************************************************
* File Name: SCSI_ATN_ISR.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SCSI_ATN_ISR_H)
#define CY_ISR_SCSI_ATN_ISR_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SCSI_ATN_ISR_Start(void);
void SCSI_ATN_ISR_StartEx(cyisraddress address);
void SCSI_ATN_ISR_Stop(void);
CY_ISR_PROTO(SCSI_ATN_ISR_Interrupt);
void SCSI_ATN_ISR_SetVector(cyisraddress address);
cyisraddress SCSI_ATN_ISR_GetVector(void);
void SCSI_ATN_ISR_SetPriority(uint8 priority);
uint8 SCSI_ATN_ISR_GetPriority(void);
void SCSI_ATN_ISR_Enable(void);
uint8 SCSI_ATN_ISR_GetState(void);
void SCSI_ATN_ISR_Disable(void);
void SCSI_ATN_ISR_SetPending(void);
void SCSI_ATN_ISR_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_ATN_ISR ISR. */
#define SCSI_ATN_ISR_INTC_VECTOR ((reg32 *) SCSI_ATN_ISR__INTC_VECT)
/* Address of the SCSI_ATN_ISR ISR priority. */
#define SCSI_ATN_ISR_INTC_PRIOR ((reg8 *) SCSI_ATN_ISR__INTC_PRIOR_REG)
/* Priority of the SCSI_ATN_ISR interrupt. */
#define SCSI_ATN_ISR_INTC_PRIOR_NUMBER SCSI_ATN_ISR__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_ATN_ISR interrupt. */
#define SCSI_ATN_ISR_INTC_SET_EN ((reg32 *) SCSI_ATN_ISR__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_ATN_ISR interrupt. */
#define SCSI_ATN_ISR_INTC_CLR_EN ((reg32 *) SCSI_ATN_ISR__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SCSI_ATN_ISR interrupt state to pending. */
#define SCSI_ATN_ISR_INTC_SET_PD ((reg32 *) SCSI_ATN_ISR__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SCSI_ATN_ISR interrupt. */
#define SCSI_ATN_ISR_INTC_CLR_PD ((reg32 *) SCSI_ATN_ISR__INTC_CLR_PD_REG)
#endif /* CY_ISR_SCSI_ATN_ISR_H */
/* [] END OF FILE */

34
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_ATN_aliases.h Normal file
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/*******************************************************************************
* File Name: SCSI_ATN.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_ATN_ALIASES_H) /* Pins SCSI_ATN_ALIASES_H */
#define CY_PINS_SCSI_ATN_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_ATN_0 SCSI_ATN__0__PC
#define SCSI_ATN_INT SCSI_ATN__INT__PC
#endif /* End Pins SCSI_ATN_ALIASES_H */
/* [] END OF FILE */

16
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_DBx_aliases.h
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@ -34,14 +34,14 @@
#define SCSI_In_DBx_6 SCSI_In_DBx__6__PC
#define SCSI_In_DBx_7 SCSI_In_DBx__7__PC
#define SCSI_In_DBx_SCSI_Out_DB0 SCSI_In_DBx__SCSI_Out_DB0__PC
#define SCSI_In_DBx_SCSI_Out_DB1 SCSI_In_DBx__SCSI_Out_DB1__PC
#define SCSI_In_DBx_SCSI_Out_DB2 SCSI_In_DBx__SCSI_Out_DB2__PC
#define SCSI_In_DBx_SCSI_Out_DB3 SCSI_In_DBx__SCSI_Out_DB3__PC
#define SCSI_In_DBx_SCSI_Out_DB4 SCSI_In_DBx__SCSI_Out_DB4__PC
#define SCSI_In_DBx_SCSI_Out_DB5 SCSI_In_DBx__SCSI_Out_DB5__PC
#define SCSI_In_DBx_SCSI_Out_DB6 SCSI_In_DBx__SCSI_Out_DB6__PC
#define SCSI_In_DBx_SCSI_Out_DB7 SCSI_In_DBx__SCSI_Out_DB7__PC
#define SCSI_In_DBx_DB0 SCSI_In_DBx__DB0__PC
#define SCSI_In_DBx_DB1 SCSI_In_DBx__DB1__PC
#define SCSI_In_DBx_DB2 SCSI_In_DBx__DB2__PC
#define SCSI_In_DBx_DB3 SCSI_In_DBx__DB3__PC
#define SCSI_In_DBx_DB4 SCSI_In_DBx__DB4__PC
#define SCSI_In_DBx_DB5 SCSI_In_DBx__DB5__PC
#define SCSI_In_DBx_DB6 SCSI_In_DBx__DB6__PC
#define SCSI_In_DBx_DB7 SCSI_In_DBx__DB7__PC
#endif /* End Pins SCSI_In_DBx_ALIASES_H */

4
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_In_aliases.h
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@ -33,14 +33,10 @@
#define SCSI_In_5 SCSI_In__5__PC
#define SCSI_In_6 SCSI_In__6__PC
#define SCSI_In_7 SCSI_In__7__PC
#define SCSI_In_8 SCSI_In__8__PC
#define SCSI_In_9 SCSI_In__9__PC
#define SCSI_In_DBP SCSI_In__DBP__PC
#define SCSI_In_ATN SCSI_In__ATN__PC
#define SCSI_In_BSY SCSI_In__BSY__PC
#define SCSI_In_ACK SCSI_In__ACK__PC
#define SCSI_In_RST SCSI_In__RST__PC
#define SCSI_In_MSG SCSI_In__MSG__PC
#define SCSI_In_SEL SCSI_In__SEL__PC
#define SCSI_In_CD SCSI_In__CD__PC

16
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_Out_DBx_aliases.h
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@ -34,14 +34,14 @@
#define SCSI_Out_DBx_6 SCSI_Out_DBx__6__PC
#define SCSI_Out_DBx_7 SCSI_Out_DBx__7__PC
#define SCSI_Out_DBx_SCSI_Out_DB0 SCSI_Out_DBx__SCSI_Out_DB0__PC
#define SCSI_Out_DBx_SCSI_Out_DB1 SCSI_Out_DBx__SCSI_Out_DB1__PC
#define SCSI_Out_DBx_SCSI_Out_DB2 SCSI_Out_DBx__SCSI_Out_DB2__PC
#define SCSI_Out_DBx_SCSI_Out_DB3 SCSI_Out_DBx__SCSI_Out_DB3__PC
#define SCSI_Out_DBx_SCSI_Out_DB4 SCSI_Out_DBx__SCSI_Out_DB4__PC
#define SCSI_Out_DBx_SCSI_Out_DB5 SCSI_Out_DBx__SCSI_Out_DB5__PC
#define SCSI_Out_DBx_SCSI_Out_DB6 SCSI_Out_DBx__SCSI_Out_DB6__PC
#define SCSI_Out_DBx_SCSI_Out_DB7 SCSI_Out_DBx__SCSI_Out_DB7__PC
#define SCSI_Out_DBx_DB0 SCSI_Out_DBx__DB0__PC
#define SCSI_Out_DBx_DB1 SCSI_Out_DBx__DB1__PC
#define SCSI_Out_DBx_DB2 SCSI_Out_DBx__DB2__PC
#define SCSI_Out_DBx_DB3 SCSI_Out_DBx__DB3__PC
#define SCSI_Out_DBx_DB4 SCSI_Out_DBx__DB4__PC
#define SCSI_Out_DBx_DB5 SCSI_Out_DBx__DB5__PC
#define SCSI_Out_DBx_DB6 SCSI_Out_DBx__DB6__PC
#define SCSI_Out_DBx_DB7 SCSI_Out_DBx__DB7__PC
#endif /* End Pins SCSI_Out_DBx_ALIASES_H */

137
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/*******************************************************************************
* File Name: SCSI_RST.c
* Version 1.90
*
* Description:
* This file contains API to enable firmware control of a Pins component.
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include "cytypes.h"
#include "SCSI_RST.h"
/* APIs are not generated for P15[7:6] on PSoC 5 */
#if !(CY_PSOC5A &&\
SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
/*******************************************************************************
* Function Name: SCSI_RST_Write
********************************************************************************
*
* Summary:
* Assign a new value to the digital port's data output register.
*
* Parameters:
* prtValue: The value to be assigned to the Digital Port.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_Write(uint8 value)
{
uint8 staticBits = (SCSI_RST_DR & (uint8)(~SCSI_RST_MASK));
SCSI_RST_DR = staticBits | ((uint8)(value << SCSI_RST_SHIFT) & SCSI_RST_MASK);
}
/*******************************************************************************
* Function Name: SCSI_RST_SetDriveMode
********************************************************************************
*
* Summary:
* Change the drive mode on the pins of the port.
*
* Parameters:
* mode: Change the pins to this drive mode.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_SetDriveMode(uint8 mode)
{
CyPins_SetPinDriveMode(SCSI_RST_0, mode);
}
/*******************************************************************************
* Function Name: SCSI_RST_Read
********************************************************************************
*
* Summary:
* Read the current value on the pins of the Digital Port in right justified
* form.
*
* Parameters:
* None
*
* Return:
* Returns the current value of the Digital Port as a right justified number
*
* Note:
* Macro SCSI_RST_ReadPS calls this function.
*
*******************************************************************************/
uint8 SCSI_RST_Read(void)
{
return (SCSI_RST_PS & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
/*******************************************************************************
* Function Name: SCSI_RST_ReadDataReg
********************************************************************************
*
* Summary:
* Read the current value assigned to a Digital Port's data output register
*
* Parameters:
* None
*
* Return:
* Returns the current value assigned to the Digital Port's data output register
*
*******************************************************************************/
uint8 SCSI_RST_ReadDataReg(void)
{
return (SCSI_RST_DR & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
/* If Interrupts Are Enabled for this Pins component */
#if defined(SCSI_RST_INTSTAT)
/*******************************************************************************
* Function Name: SCSI_RST_ClearInterrupt
********************************************************************************
* Summary:
* Clears any active interrupts attached to port and returns the value of the
* interrupt status register.
*
* Parameters:
* None
*
* Return:
* Returns the value of the interrupt status register
*
*******************************************************************************/
uint8 SCSI_RST_ClearInterrupt(void)
{
return (SCSI_RST_INTSTAT & SCSI_RST_MASK) >> SCSI_RST_SHIFT;
}
#endif /* If Interrupts Are Enabled for this Pins component */
#endif /* CY_PSOC5A... */
/* [] END OF FILE */

130
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@ -0,0 +1,130 @@
/*******************************************************************************
* File Name: SCSI_RST.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_RST_H) /* Pins SCSI_RST_H */
#define CY_PINS_SCSI_RST_H
#include "cytypes.h"
#include "cyfitter.h"
#include "cypins.h"
#include "SCSI_RST_aliases.h"
/* Check to see if required defines such as CY_PSOC5A are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5A)
#error Component cy_pins_v1_90 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5A) */
/* APIs are not generated for P15[7:6] */
#if !(CY_PSOC5A &&\
SCSI_RST__PORT == 15 && ((SCSI_RST__MASK & 0xC0) != 0))
/***************************************
* Function Prototypes
***************************************/
void SCSI_RST_Write(uint8 value) ;
void SCSI_RST_SetDriveMode(uint8 mode) ;
uint8 SCSI_RST_ReadDataReg(void) ;
uint8 SCSI_RST_Read(void) ;
uint8 SCSI_RST_ClearInterrupt(void) ;
/***************************************
* API Constants
***************************************/
/* Drive Modes */
#define SCSI_RST_DM_ALG_HIZ PIN_DM_ALG_HIZ
#define SCSI_RST_DM_DIG_HIZ PIN_DM_DIG_HIZ
#define SCSI_RST_DM_RES_UP PIN_DM_RES_UP
#define SCSI_RST_DM_RES_DWN PIN_DM_RES_DWN
#define SCSI_RST_DM_OD_LO PIN_DM_OD_LO
#define SCSI_RST_DM_OD_HI PIN_DM_OD_HI
#define SCSI_RST_DM_STRONG PIN_DM_STRONG
#define SCSI_RST_DM_RES_UPDWN PIN_DM_RES_UPDWN
/* Digital Port Constants */
#define SCSI_RST_MASK SCSI_RST__MASK
#define SCSI_RST_SHIFT SCSI_RST__SHIFT
#define SCSI_RST_WIDTH 1u
/***************************************
* Registers
***************************************/
/* Main Port Registers */
/* Pin State */
#define SCSI_RST_PS (* (reg8 *) SCSI_RST__PS)
/* Data Register */
#define SCSI_RST_DR (* (reg8 *) SCSI_RST__DR)
/* Port Number */
#define SCSI_RST_PRT_NUM (* (reg8 *) SCSI_RST__PRT)
/* Connect to Analog Globals */
#define SCSI_RST_AG (* (reg8 *) SCSI_RST__AG)
/* Analog MUX bux enable */
#define SCSI_RST_AMUX (* (reg8 *) SCSI_RST__AMUX)
/* Bidirectional Enable */
#define SCSI_RST_BIE (* (reg8 *) SCSI_RST__BIE)
/* Bit-mask for Aliased Register Access */
#define SCSI_RST_BIT_MASK (* (reg8 *) SCSI_RST__BIT_MASK)
/* Bypass Enable */
#define SCSI_RST_BYP (* (reg8 *) SCSI_RST__BYP)
/* Port wide control signals */
#define SCSI_RST_CTL (* (reg8 *) SCSI_RST__CTL)
/* Drive Modes */
#define SCSI_RST_DM0 (* (reg8 *) SCSI_RST__DM0)
#define SCSI_RST_DM1 (* (reg8 *) SCSI_RST__DM1)
#define SCSI_RST_DM2 (* (reg8 *) SCSI_RST__DM2)
/* Input Buffer Disable Override */
#define SCSI_RST_INP_DIS (* (reg8 *) SCSI_RST__INP_DIS)
/* LCD Common or Segment Drive */
#define SCSI_RST_LCD_COM_SEG (* (reg8 *) SCSI_RST__LCD_COM_SEG)
/* Enable Segment LCD */
#define SCSI_RST_LCD_EN (* (reg8 *) SCSI_RST__LCD_EN)
/* Slew Rate Control */
#define SCSI_RST_SLW (* (reg8 *) SCSI_RST__SLW)
/* DSI Port Registers */
/* Global DSI Select Register */
#define SCSI_RST_PRTDSI__CAPS_SEL (* (reg8 *) SCSI_RST__PRTDSI__CAPS_SEL)
/* Double Sync Enable */
#define SCSI_RST_PRTDSI__DBL_SYNC_IN (* (reg8 *) SCSI_RST__PRTDSI__DBL_SYNC_IN)
/* Output Enable Select Drive Strength */
#define SCSI_RST_PRTDSI__OE_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL0)
#define SCSI_RST_PRTDSI__OE_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OE_SEL1)
/* Port Pin Output Select Registers */
#define SCSI_RST_PRTDSI__OUT_SEL0 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL0)
#define SCSI_RST_PRTDSI__OUT_SEL1 (* (reg8 *) SCSI_RST__PRTDSI__OUT_SEL1)
/* Sync Output Enable Registers */
#define SCSI_RST_PRTDSI__SYNC_OUT (* (reg8 *) SCSI_RST__PRTDSI__SYNC_OUT)
#if defined(SCSI_RST__INTSTAT) /* Interrupt Registers */
#define SCSI_RST_INTSTAT (* (reg8 *) SCSI_RST__INTSTAT)
#define SCSI_RST_SNAP (* (reg8 *) SCSI_RST__SNAP)
#endif /* Interrupt Registers */
#endif /* CY_PSOC5A... */
#endif /* CY_PINS_SCSI_RST_H */
/* [] END OF FILE */

356
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.c Normal file
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@ -0,0 +1,356 @@
/*******************************************************************************
* File Name: SCSI_RST_ISR.c
* Version 1.70
*
* Description:
* API for controlling the state of an interrupt.
*
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#include <cydevice_trm.h>
#include <CyLib.h>
#include <SCSI_RST_ISR.h>
#if !defined(SCSI_RST_ISR__REMOVED) /* Check for removal by optimization */
/*******************************************************************************
* Place your includes, defines and code here
********************************************************************************/
/* `#START SCSI_RST_ISR_intc` */
/* `#END` */
#ifndef CYINT_IRQ_BASE
#define CYINT_IRQ_BASE 16
#endif /* CYINT_IRQ_BASE */
#ifndef CYINT_VECT_TABLE
#define CYINT_VECT_TABLE ((cyisraddress **) CYREG_NVIC_VECT_OFFSET)
#endif /* CYINT_VECT_TABLE */
/* Declared in startup, used to set unused interrupts to. */
CY_ISR_PROTO(IntDefaultHandler);
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Start
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Start(void)
{
/* For all we know the interrupt is active. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
SCSI_RST_ISR_SetVector(&SCSI_RST_ISR_Interrupt);
/* Set the priority. */
SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RST_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_StartEx
********************************************************************************
*
* Summary:
* Set up the interrupt and enable it.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_StartEx(cyisraddress address)
{
/* For all we know the interrupt is active. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the SCSI_RST_ISR Interrupt. */
SCSI_RST_ISR_SetVector(address);
/* Set the priority. */
SCSI_RST_ISR_SetPriority((uint8)SCSI_RST_ISR_INTC_PRIOR_NUMBER);
/* Enable it. */
SCSI_RST_ISR_Enable();
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Stop
********************************************************************************
*
* Summary:
* Disables and removes the interrupt.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Stop(void)
{
/* Disable this interrupt. */
SCSI_RST_ISR_Disable();
/* Set the ISR to point to the passive one. */
SCSI_RST_ISR_SetVector(&IntDefaultHandler);
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Interrupt
********************************************************************************
*
* Summary:
* The default Interrupt Service Routine for SCSI_RST_ISR.
*
* Add custom code between the coments to keep the next version of this file
* from over writting your code.
*
* Parameters:
*
* Return:
* None
*
*******************************************************************************/
CY_ISR(SCSI_RST_ISR_Interrupt)
{
/* Place your Interrupt code here. */
/* `#START SCSI_RST_ISR_Interrupt` */
/* `#END` */
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetVector
********************************************************************************
*
* Summary:
* Change the ISR vector for the Interrupt. Note calling SCSI_RST_ISR_Start
* will override any effect this method would have had. To set the vector
* before the component has been started use SCSI_RST_ISR_StartEx instead.
*
* Parameters:
* address: Address of the ISR to set in the interrupt vector table.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_SetVector(cyisraddress address)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER] = address;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetVector
********************************************************************************
*
* Summary:
* Gets the "address" of the current ISR vector for the Interrupt.
*
* Parameters:
* None
*
* Return:
* Address of the ISR in the interrupt vector table.
*
*******************************************************************************/
cyisraddress SCSI_RST_ISR_GetVector(void)
{
cyisraddress * ramVectorTable;
ramVectorTable = (cyisraddress *) *CYINT_VECT_TABLE;
return ramVectorTable[CYINT_IRQ_BASE + (uint32)SCSI_RST_ISR__INTC_NUMBER];
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetPriority
********************************************************************************
*
* Summary:
* Sets the Priority of the Interrupt. Note calling SCSI_RST_ISR_Start
* or SCSI_RST_ISR_StartEx will override any effect this method
* would have had. This method should only be called after
* SCSI_RST_ISR_Start or SCSI_RST_ISR_StartEx has been called. To set
* the initial priority for the component use the cydwr file in the tool.
*
* Parameters:
* priority: Priority of the interrupt. 0 - 7, 0 being the highest.
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_SetPriority(uint8 priority)
{
*SCSI_RST_ISR_INTC_PRIOR = priority << 5;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetPriority
********************************************************************************
*
* Summary:
* Gets the Priority of the Interrupt.
*
* Parameters:
* None
*
* Return:
* Priority of the interrupt. 0 - 7, 0 being the highest.
*
*******************************************************************************/
uint8 SCSI_RST_ISR_GetPriority(void)
{
uint8 priority;
priority = *SCSI_RST_ISR_INTC_PRIOR >> 5;
return priority;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Enable
********************************************************************************
*
* Summary:
* Enables the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Enable(void)
{
/* Enable the general interrupt. */
*SCSI_RST_ISR_INTC_SET_EN = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_GetState
********************************************************************************
*
* Summary:
* Gets the state (enabled, disabled) of the Interrupt.
*
* Parameters:
* None
*
* Return:
* 1 if enabled, 0 if disabled.
*
*******************************************************************************/
uint8 SCSI_RST_ISR_GetState(void)
{
/* Get the state of the general interrupt. */
return ((*SCSI_RST_ISR_INTC_SET_EN & (uint32)SCSI_RST_ISR__INTC_MASK) != 0u) ? 1u:0u;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_Disable
********************************************************************************
*
* Summary:
* Disables the Interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_Disable(void)
{
/* Disable the general interrupt. */
*SCSI_RST_ISR_INTC_CLR_EN = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_SetPending
********************************************************************************
*
* Summary:
* Causes the Interrupt to enter the pending state, a software method of
* generating the interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_SetPending(void)
{
*SCSI_RST_ISR_INTC_SET_PD = SCSI_RST_ISR__INTC_MASK;
}
/*******************************************************************************
* Function Name: SCSI_RST_ISR_ClearPending
********************************************************************************
*
* Summary:
* Clears a pending interrupt.
*
* Parameters:
* None
*
* Return:
* None
*
*******************************************************************************/
void SCSI_RST_ISR_ClearPending(void)
{
*SCSI_RST_ISR_INTC_CLR_PD = SCSI_RST_ISR__INTC_MASK;
}
#endif /* End check for removal by optimization */
/* [] END OF FILE */

70
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_ISR.h Normal file
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@ -0,0 +1,70 @@
/*******************************************************************************
* File Name: SCSI_RST_ISR.h
* Version 1.70
*
* Description:
* Provides the function definitions for the Interrupt Controller.
*
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_ISR_SCSI_RST_ISR_H)
#define CY_ISR_SCSI_RST_ISR_H
#include <cytypes.h>
#include <cyfitter.h>
/* Interrupt Controller API. */
void SCSI_RST_ISR_Start(void);
void SCSI_RST_ISR_StartEx(cyisraddress address);
void SCSI_RST_ISR_Stop(void);
CY_ISR_PROTO(SCSI_RST_ISR_Interrupt);
void SCSI_RST_ISR_SetVector(cyisraddress address);
cyisraddress SCSI_RST_ISR_GetVector(void);
void SCSI_RST_ISR_SetPriority(uint8 priority);
uint8 SCSI_RST_ISR_GetPriority(void);
void SCSI_RST_ISR_Enable(void);
uint8 SCSI_RST_ISR_GetState(void);
void SCSI_RST_ISR_Disable(void);
void SCSI_RST_ISR_SetPending(void);
void SCSI_RST_ISR_ClearPending(void);
/* Interrupt Controller Constants */
/* Address of the INTC.VECT[x] register that contains the Address of the SCSI_RST_ISR ISR. */
#define SCSI_RST_ISR_INTC_VECTOR ((reg32 *) SCSI_RST_ISR__INTC_VECT)
/* Address of the SCSI_RST_ISR ISR priority. */
#define SCSI_RST_ISR_INTC_PRIOR ((reg8 *) SCSI_RST_ISR__INTC_PRIOR_REG)
/* Priority of the SCSI_RST_ISR interrupt. */
#define SCSI_RST_ISR_INTC_PRIOR_NUMBER SCSI_RST_ISR__INTC_PRIOR_NUM
/* Address of the INTC.SET_EN[x] byte to bit enable SCSI_RST_ISR interrupt. */
#define SCSI_RST_ISR_INTC_SET_EN ((reg32 *) SCSI_RST_ISR__INTC_SET_EN_REG)
/* Address of the INTC.CLR_EN[x] register to bit clear the SCSI_RST_ISR interrupt. */
#define SCSI_RST_ISR_INTC_CLR_EN ((reg32 *) SCSI_RST_ISR__INTC_CLR_EN_REG)
/* Address of the INTC.SET_PD[x] register to set the SCSI_RST_ISR interrupt state to pending. */
#define SCSI_RST_ISR_INTC_SET_PD ((reg32 *) SCSI_RST_ISR__INTC_SET_PD_REG)
/* Address of the INTC.CLR_PD[x] register to clear the SCSI_RST_ISR interrupt. */
#define SCSI_RST_ISR_INTC_CLR_PD ((reg32 *) SCSI_RST_ISR__INTC_CLR_PD_REG)
#endif /* CY_ISR_SCSI_RST_ISR_H */
/* [] END OF FILE */

34
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SCSI_RST_aliases.h Normal file
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@ -0,0 +1,34 @@
/*******************************************************************************
* File Name: SCSI_RST.h
* Version 1.90
*
* Description:
* This file containts Control Register function prototypes and register defines
*
* Note:
*
********************************************************************************
* Copyright 2008-2012, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
*******************************************************************************/
#if !defined(CY_PINS_SCSI_RST_ALIASES_H) /* Pins SCSI_RST_ALIASES_H */
#define CY_PINS_SCSI_RST_ALIASES_H
#include "cytypes.h"
#include "cyfitter.h"
/***************************************
* Constants
***************************************/
#define SCSI_RST_0 SCSI_RST__0__PC
#define SCSI_RST_INT SCSI_RST__INT__PC
#endif /* End Pins SCSI_RST_ALIASES_H */
/* [] END OF FILE */

4
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SDCard.h
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@ -48,8 +48,8 @@
/* Internal interrupt handling */
#define SDCard_TX_BUFFER_SIZE (4u)
#define SDCard_RX_BUFFER_SIZE (4u)
#define SDCard_INTERNAL_TX_INT_ENABLED (1u)
#define SDCard_INTERNAL_RX_INT_ENABLED (1u)
#define SDCard_INTERNAL_TX_INT_ENABLED (0u)
#define SDCard_INTERNAL_RX_INT_ENABLED (0u)
#define SDCard_SINGLE_REG_SIZE (8u)
#define SDCard_USE_SECOND_DATAPATH (SDCard_DATA_WIDTH > SDCard_SINGLE_REG_SIZE)

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: SD_Data_Clk.c
* Version 2.0
* Version 2.10
*
* Description:
* This file provides the source code to the API for the clock component.

10
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Data_Clk.h
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@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: SD_Data_Clk.h
* Version 2.0
* Version 2.10
*
* Description:
* Provides the function and constant definitions for the clock component.
@ -28,7 +28,7 @@
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_0 requires cy_boot v3.0 or later
#error Component cy_clock_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
@ -59,13 +59,13 @@ uint8 SD_Data_Clk_GetPhaseRegister(void) ;
#define SD_Data_Clk_Enable() SD_Data_Clk_Start()
#define SD_Data_Clk_Disable() SD_Data_Clk_Stop()
#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1)
#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1, 1)
#define SD_Data_Clk_SetDivider(clkDivider) SD_Data_Clk_SetDividerRegister(clkDivider, 1u)
#define SD_Data_Clk_SetDividerValue(clkDivider) SD_Data_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
#define SD_Data_Clk_SetMode(clkMode) SD_Data_Clk_SetModeRegister(clkMode)
#define SD_Data_Clk_SetSource(clkSource) SD_Data_Clk_SetSourceRegister(clkSource)
#if defined(SD_Data_Clk__CFG3)
#define SD_Data_Clk_SetPhase(clkPhase) SD_Data_Clk_SetPhaseRegister(clkPhase)
#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1)
#define SD_Data_Clk_SetPhaseValue(clkPhase) SD_Data_Clk_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(SD_Data_Clk__CFG3) */

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: SD_Init_Clk.c
* Version 2.0
* Version 2.10
*
* Description:
* This file provides the source code to the API for the clock component.

10
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/SD_Init_Clk.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: SD_Init_Clk.h
* Version 2.0
* Version 2.10
*
* Description:
* Provides the function and constant definitions for the clock component.
@ -28,7 +28,7 @@
/* Check to see if required defines such as CY_PSOC5LP are available */
/* They are defined starting with cy_boot v3.0 */
#if !defined (CY_PSOC5LP)
#error Component cy_clock_v2_0 requires cy_boot v3.0 or later
#error Component cy_clock_v2_10 requires cy_boot v3.0 or later
#endif /* (CY_PSOC5LP) */
@ -59,13 +59,13 @@ uint8 SD_Init_Clk_GetPhaseRegister(void) ;
#define SD_Init_Clk_Enable() SD_Init_Clk_Start()
#define SD_Init_Clk_Disable() SD_Init_Clk_Stop()
#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1)
#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1, 1)
#define SD_Init_Clk_SetDivider(clkDivider) SD_Init_Clk_SetDividerRegister(clkDivider, 1u)
#define SD_Init_Clk_SetDividerValue(clkDivider) SD_Init_Clk_SetDividerRegister((clkDivider) - 1u, 1u)
#define SD_Init_Clk_SetMode(clkMode) SD_Init_Clk_SetModeRegister(clkMode)
#define SD_Init_Clk_SetSource(clkSource) SD_Init_Clk_SetSourceRegister(clkSource)
#if defined(SD_Init_Clk__CFG3)
#define SD_Init_Clk_SetPhase(clkPhase) SD_Init_Clk_SetPhaseRegister(clkPhase)
#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1)
#define SD_Init_Clk_SetPhaseValue(clkPhase) SD_Init_Clk_SetPhaseRegister((clkPhase) + 1u)
#endif /* defined(SD_Init_Clk__CFG3) */

150
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cm3gcc.ld
View File

@ -16,55 +16,84 @@
* they apply.
*/
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
ENTRY(__cs3_reset)
ENTRY(__cy_reset)
SEARCH_DIR(.)
GROUP(-lgcc -lc -lcs3 -lcs3unhosted -lcs3micro)
GROUP(-lgcc -lc -lnosys)
MEMORY
{
rom (rx) : ORIGIN = 0, LENGTH = (262144 - 0)
ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = (65536 - 0x4000 - 0x1000)
rom (rx) : ORIGIN = 0x0, LENGTH = 262144
ram (rwx) : ORIGIN = 0x20000000 - (65536 / 2), LENGTH = 65536
}
CY_APPL_ORIGIN = 0;
CY_FLASH_ROW_SIZE = 256;
CY_ECC_ROW_SIZE = 32;
CY_EE_IN_BTLDR = 0x0;
CY_APPL_LOADABLE = 0;
CY_EE_SIZE = 2048;
CY_APPL_NUM = 1;
CY_APPL_MAX = 1;
CY_METADATA_SIZE = 64;
/* These force the linker to search for particular symbols from
* the start of the link process and thus ensure the user's
* overrides are picked up
*/
EXTERN(__cs3_reset Reset)
EXTERN(__cs3_start_asm __cs3_start_asm_generic_m)
EXTERN(Reset)
/* Bring in the interrupt routines & vector */
INCLUDE micro-names.inc
EXTERN(__cs3_start_c main __cs3_stack __cs3_heap_end)
EXTERN(main)
/* Bring in the meta data */
EXTERN(cy_meta_loader cy_bootloader cy_meta_loadable cy_meta_bootloader)
EXTERN(cy_meta_custnvl cy_meta_wolatch cy_meta_flashprotect cy_metadata)
/* Provide fall-back values */
PROVIDE(__cs3_heap_start = _end);
PROVIDE(__cs3_region_num = (__cs3_regions_end - __cs3_regions) / 20);
PROVIDE(__cs3_stack = 0x20000000 + (65536 / 2));
PROVIDE(__cs3_heap_end = __cs3_stack - 0x4000);
PROVIDE(__cy_heap_start = _end);
PROVIDE(__cy_region_num = (__cy_regions_end - __cy_regions) / 16);
PROVIDE(__cy_stack = ORIGIN(ram) + LENGTH(ram));
PROVIDE(__cy_heap_end = __cy_stack - 0x4000);
SECTIONS
{
/* The bootloader location */
.cybootloader 0x0 : { KEEP(*(.cybootloader)) } >rom
.text :
/* Calculate where the loadables should start */
appl1_start = CY_APPL_ORIGIN ? CY_APPL_ORIGIN : ALIGN(CY_FLASH_ROW_SIZE);
appl2_start = appl1_start + ALIGN((LENGTH(rom) - appl1_start - 2 * CY_FLASH_ROW_SIZE) / 2, CY_FLASH_ROW_SIZE);
appl_start = (CY_APPL_NUM == 1) ? appl1_start : appl2_start;
ecc_offset = (appl_start / CY_FLASH_ROW_SIZE) * CY_ECC_ROW_SIZE;
ee_offset = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? ((CY_EE_SIZE / CY_APPL_MAX) * (CY_APPL_NUM - 1)) : 0;
ee_size = (CY_APPL_LOADABLE && !CY_EE_IN_BTLDR) ? (CY_EE_SIZE / CY_APPL_MAX) : CY_EE_SIZE;
PROVIDE(CY_ECC_OFFSET = ecc_offset);
.text appl_start :
{
CREATE_OBJECT_SYMBOLS
PROVIDE(__cs3_interrupt_vector = RomVectors);
*(.romvectors)
*(.cs3.interrupt_vector)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cs3_interrupt_vector, "No interrupt vector");
PROVIDE(__cy_interrupt_vector = RomVectors);
PROVIDE(__cs3_reset = Reset);
*(.cs3.reset)
*(.romvectors)
/* Make sure we pulled in an interrupt vector. */
ASSERT (. != __cy_interrupt_vector, "No interrupt vector");
ASSERT (CY_APPL_ORIGIN ? (SIZEOF(.cybootloader) <= CY_APPL_ORIGIN) : 1, "Wrong image location");
PROVIDE(__cy_reset = Reset);
*(.text.Reset)
/* Make sure we pulled in some reset code. */
ASSERT (. != __cs3_reset, "No reset code");
ASSERT (. != __cy_reset, "No reset code");
/* Place the DMA initialization before text to ensure it gets placed in first 64K of flash */
*(.dma_init)
ASSERT(0 + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
ASSERT(appl_start + . <= 0x10000 || !0, "DMA Init must be within the first 64k of flash");
*(.text.cs3.init)
*(.text .text.* .gnu.linkonce.t.*)
*(.plt)
*(.gnu.warning)
@ -130,13 +159,12 @@ SECTIONS
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
__cs3_regions = .;
LONG (0)
LONG (__cs3_region_init_ram)
LONG (__cs3_region_start_data)
LONG (__cs3_region_init_size_ram)
LONG (__cs3_region_zero_size_ram)
__cs3_regions_end = .;
__cy_regions = .;
LONG (__cy_region_init_ram)
LONG (__cy_region_start_data)
LONG (__cy_region_init_size_ram)
LONG (__cy_region_zero_size_ram)
__cy_regions_end = .;
. = ALIGN (8);
_etext = .;
@ -144,9 +172,7 @@ SECTIONS
.ramvectors (NOLOAD) : ALIGN(8)
{
__cs3_region_start_ram = .;
*(.cs3.region-head.ram)
ASSERT (. == __cs3_region_start_ram, ".cs3.region-head.ram not permitted");
__cy_region_start_ram = .;
KEEP(*(.ramvectors))
}
@ -157,7 +183,7 @@ SECTIONS
.data : ALIGN(8)
{
__cs3_region_start_data = .;
__cy_region_start_data = .;
KEEP(*(.jcr))
*(.got.plt) *(.got)
@ -169,6 +195,7 @@ SECTIONS
} >ram AT>rom
.bss : ALIGN(8)
{
PROVIDE(__bss_start__ = .);
*(.shbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
@ -177,13 +204,58 @@ SECTIONS
_end = .;
__end = .;
} >ram AT>rom
PROVIDE(end = .);
PROVIDE(__bss_end__ = .);
__cs3_region_end_ram = __cs3_region_start_ram + LENGTH(ram);
__cs3_region_size_ram = LENGTH(ram);
__cs3_region_init_ram = LOADADDR (.data);
__cs3_region_init_size_ram = _edata - ADDR (.data);
__cs3_region_zero_size_ram = _end - _edata;
__cy_region_init_ram = LOADADDR (.data);
__cy_region_init_size_ram = _edata - ADDR (.data);
__cy_region_zero_size_ram = _end - _edata;
/* The .stack and .heap sections don't contain any symbols.
* They are only used for linker to calculate RAM utilization.
*/
.heap (NOLOAD) :
{
. = _end;
. += 0x1000;
__cy_heap_limit = .;
} >ram
.stack (__cy_stack - 0x4000) (NOLOAD) :
{
__cy_stack_limit = .;
. += 0x4000;
} >ram
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__cy_stack_limit >= __cy_heap_limit, "region RAM overflowed with stack")
.cyloadermeta ((appl_start == 0) ? (LENGTH(rom) - CY_METADATA_SIZE) : 0xF0000000) :
{
KEEP(*(.cyloadermeta))
} :NONE
.cyloadablemeta (LENGTH(rom) - CY_FLASH_ROW_SIZE * (CY_APPL_NUM - 1) - CY_METADATA_SIZE) :
{
KEEP(*(.cyloadablemeta))
} >rom
.cyconfigecc (0x80000000 + ecc_offset) :
{
KEEP(*(.cyconfigecc))
} :NONE
.cycustnvl 0x90000000 : { KEEP(*(.cycustnvl)) } :NONE
.cywolatch 0x90100000 : { KEEP(*(.cywolatch)) } :NONE
.cyeeprom (0x90200000 + ee_offset) :
{
KEEP(*(.cyeeprom))
ASSERT(. <= (0x90200000 + ee_offset + ee_size), ".cyeeprom data will not fit in EEPROM");
} :NONE
.cyflashprotect 0x90400000 : { KEEP(*(.cyflashprotect)) } :NONE
.cymeta 0x90500000 : { KEEP(*(.cymeta)) } :NONE
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }

61
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/config.hex
View File

@ -1,30 +1,33 @@
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:2000200003400140024101400242014002430140064801401049014004500140015101405C
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:200060008A408BAE8C888D698E618F0690019186924094479698978698E299E79A089B0810
:200080009C419D86A110A404A504A740A840A982AC41AD10B10FB3E0B4C0B510B63FB7087A
:2000A000B880B922BA20BB0CBE40BF40D409D604D80BD90BDB0BDC99DD90DF010040012602
:2000C0000A6910081220138019A02054226C2310281029A12A04300831403210330138500B
:2000E0003905581059085A82628063406D407801C00FC20FC407CA0FCC0FCE0FD60FD809B0
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:2001400037083B083E503F5054405604580B590B5B0B5C995D905F01820885018610870274
:2001600089028B018D018E058F0494069A019D06AA03AC08AE10B018B107B407B902BE0108
:20018000D808D908DC99DF010040010A02080448068008200A610E080F101028124013803D
:2001A0001560190A1A021B901E88210822A027402902310832103340374038403B103C4019
:2001C0003F1460806250632078017F018004848086808A028E2490409160926193169602FD
:2001E00098219A509B80A028A208A508A6C2A780A821C0BFC26FC4CFCA01CC1ECE7CD80FA1
:20020000DE11E250E42056085B045D90004401210A69102A190120102110221023042840C0
:2002200029602A0430083210334138503904404041104380490A4A0A500352545E806108D9
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:2003000000DC9F00FF0000F0000F000000000008000001004602100005BEFDBC3FFFFFFF4B
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:200200001B101C032003260128032E4830403201343C3538360237073B203E445440580BDF
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:2002E000EE801440C404B040EA01201026808E80C86008025B205F4084028B209340A810AD
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2443
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3.h
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File diff suppressed because it is too large Load Diff

13
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cm3_psoc5.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: core_cm3_psoc5.h
* Version 3.40
* Version 4.0
*
* Description:
* Provides important type information for the PSoC5. This includes types
@ -38,6 +38,17 @@ typedef enum IRQn
/* Not relevant. All peripheral interrupts are defined by the user */
} IRQn_Type;
#include <cytypes.h>
#define __CHECK_DEVICE_DEFINES
#define __CM3_REV 0x0201
#define __MPU_PRESENT 0
#define __NVIC_PRIO_BITS 3
#define __Vendor_SysTickConfig 0
#include <core_cm3.h>
#endif /* __CORE_CM3_PSOC5_H__ */

636
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/core_cmFunc.h Normal file
View File

@ -0,0 +1,636 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.20
* @date 25. February 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i" : : : "memory");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f" : : : "memory");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f" : : : "memory");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
__ASM volatile ("");
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
/* Empty asm statement works as a scheduling barrier */
__ASM volatile ("");
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
__ASM volatile ("");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.20
* @date 05. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return __builtin_bswap32(value);
#else
uint32_t result;
__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return (short)__builtin_bswap16(value);
#else
uint32_t result;
__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
return(result);
#endif
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << (32 - op2));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint32_t result;
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
#endif
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex" ::: "memory");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint32_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

1212
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.c
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File diff suppressed because it is too large Load Diff

272
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyPm.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: cyPm.h
* Version 3.40
* Version 4.0
*
* Description:
* Provides the function definitions for the power management API.
@ -91,37 +91,33 @@ void CyPmOppsSet(void) ;
#endif /* (CY_PSOC3) */
#if(CY_PSOC3 || CY_PSOC5LP)
/* Wake up sources for the Sleep mode */
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)
#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u)
#define PM_SLEEP_SRC_PICU (0x0040u)
#define PM_SLEEP_SRC_I2C (0x0080u)
#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u)
#define PM_SLEEP_SRC_VD (0x0400u)
#define PM_SLEEP_SRC_CTW (0x0800u)
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)
#define PM_SLEEP_SRC_LCD (0x1000u)
/* Wake up sources for the Sleep mode */
#define PM_SLEEP_SRC_COMPARATOR0 (0x0001u)
#define PM_SLEEP_SRC_COMPARATOR1 (0x0002u)
#define PM_SLEEP_SRC_COMPARATOR2 (0x0004u)
#define PM_SLEEP_SRC_COMPARATOR3 (0x0008u)
#define PM_SLEEP_SRC_PICU (0x0040u)
#define PM_SLEEP_SRC_I2C (0x0080u)
#define PM_SLEEP_SRC_BOOSTCONVERTER (0x0200u)
#define PM_SLEEP_SRC_VD (0x0400u)
#define PM_SLEEP_SRC_CTW (0x0800u)
#define PM_SLEEP_SRC_ONE_PPS (0x0800u)
#define PM_SLEEP_SRC_LCD (0x1000u)
/* Wake up sources for the Alternate Active mode */
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)
#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u)
#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u)
#define PM_ALT_ACT_SRC_PICU (0x0040u)
#define PM_ALT_ACT_SRC_I2C (0x0080u)
#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u)
#define PM_ALT_ACT_SRC_FTW (0x0400u)
#define PM_ALT_ACT_SRC_VD (0x0400u)
#define PM_ALT_ACT_SRC_CTW (0x0800u)
#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u)
#define PM_ALT_ACT_SRC_LCD (0x1000u)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
/* Wake up sources for the Alternate Active mode */
#define PM_ALT_ACT_SRC_COMPARATOR0 (0x0001u)
#define PM_ALT_ACT_SRC_COMPARATOR1 (0x0002u)
#define PM_ALT_ACT_SRC_COMPARATOR2 (0x0004u)
#define PM_ALT_ACT_SRC_COMPARATOR3 (0x0008u)
#define PM_ALT_ACT_SRC_INTERRUPT (0x0010u)
#define PM_ALT_ACT_SRC_PICU (0x0040u)
#define PM_ALT_ACT_SRC_I2C (0x0080u)
#define PM_ALT_ACT_SRC_BOOSTCONVERTER (0x0200u)
#define PM_ALT_ACT_SRC_FTW (0x0400u)
#define PM_ALT_ACT_SRC_VD (0x0400u)
#define PM_ALT_ACT_SRC_CTW (0x0800u)
#define PM_ALT_ACT_SRC_ONE_PPS (0x0800u)
#define PM_ALT_ACT_SRC_LCD (0x1000u)
#define CY_PM_WAKEUP_PICU (0x04u)
@ -146,11 +142,7 @@ void CyPmOppsSet(void) ;
#define CY_PM_FREQ_48MHZ (48u)
#if(CY_PSOC5A)
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (650u)
#else
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)
#endif /* (CY_PSOC5A) */
#define CY_PM_MHZ_XTAL_WAIT_NUM_OF_200_US (5u)
/* Delay line bandgap current settling time starting from a wakeup event */
@ -165,13 +157,9 @@ void CyPmOppsSet(void) ;
#define CY_PM_MAX_FLASH_WAIT_CYCLES (45u)
#endif /* (CY_PSOC3) */
#if(CY_PSOC5A)
#if(CY_PSOC5)
#define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)
#endif /* (CY_PSOC5A) */
#if(CY_PSOC5LP)
#define CY_PM_MAX_FLASH_WAIT_CYCLES (55u)
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/*******************************************************************************
@ -182,8 +170,9 @@ void CyPmOppsSet(void) ;
* bitfield.
*******************************************************************************/
#if(CY_PSOC3)
#define CY_PM_GET_CPU_FREQ_MHZ ((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \
((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))
#define CY_PM_GET_CPU_FREQ_MHZ \
((uint32)(cyPmImoFreqReg2Mhz[CY_PM_FASTCLK_IMO_CR_REG & CY_PM_FASTCLK_IMO_CR_FREQ_MASK]) / \
((uint8)(((CY_PM_CLKDIST_MSTR1_REG & CY_PM_CLKDIST_CPU_DIV_MASK) >> 4u) + 1u)))
#endif /* (CY_PSOC3) */
#if(CY_PSOC5)
@ -205,7 +194,7 @@ void CyPmOppsSet(void) ;
#if defined(__ARMCC_VERSION) /* Instristic for Keil compilers */
#define CY_PM_WFI __wfi()
#else /* ASM for GCC */
#else /* ASM for GCC & IAR */
#define CY_PM_WFI asm volatile ("WFI \n")
#endif /* (__ARMCC_VERSION) */
@ -273,75 +262,28 @@ typedef struct cyPmClockBackupStruct
typedef struct cyPmBackupStruct
{
#if(!CY_PSOC5A)
uint8 iloPowerMode; /* ILO power mode */
uint8 ilo1kEnable; /* ILO 1K enable state */
uint8 ilo100kEnable; /* ILO 100K enable state */
uint8 slpTrBypass; /* Sleep Trim Bypass */
#endif /* (!CY_PSOC5A) */
#if(CY_PSOC5A)
/* State of the I2C regulator backup */
uint8 i2cRegBackup;
#endif /* (CY_PSOC5A) */
#if(CY_PSOC5A)
uint8 buzzSleepTrim;
#endif /* (CY_PSOC5A) */
uint8 iloPowerMode; /* ILO power mode */
uint8 ilo1kEnable; /* ILO 1K enable state */
uint8 ilo100kEnable; /* ILO 100K enable state */
uint8 slpTrBypass; /* Sleep Trim Bypass */
#if(CY_PSOC3)
uint8 swvClkEnabled; /* SWV clock enable state */
uint8 prt1Dm; /* Ports drive mode configuration */
uint8 hardwareBuzz;
#endif /* (CY_PSOC3) */
#if(CY_PSOC3 || CY_PSOC5LP)
uint8 wakeupCfg0; /* Wake up configuration 0 */
uint8 wakeupCfg1; /* Wake up configuration 1 */
uint8 wakeupCfg2; /* Wake up configuration 2 */
uint8 wakeupCfg0; /* Wake up configuration 0 */
uint8 wakeupCfg1; /* Wake up configuration 1 */
uint8 wakeupCfg2; /* Wake up configuration 2 */
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#if(CY_PSOC3 || CY_PSOC5LP)
uint8 wakeupTrim0;
uint8 wakeupTrim1;
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#if(CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP)
uint8 scctData[28u]; /* SC/CT routing registers */
#endif /* (CY_PSOC3 || CY_PSOC5A || CY_PSOC5LP) */
#if(CY_PSOC5A)
uint8 cmpData[20u];
uint8 dacData[16u];
uint8 dsmData[5u];
uint8 sarData[10u];
uint8 pmTwCfg2;
uint8 picuIntType[72u];
uint8 pres1;
uint8 pres2;
#endif /* (CY_PSOC5A) */
uint8 wakeupTrim0;
uint8 wakeupTrim1;
uint8 scctData[28u]; /* SC/CT routing registers */
/* CyPmHviLviSaveDisable()/CyPmHviLviRestore() */
uint8 lvidEn;
@ -425,26 +367,15 @@ typedef struct cyPmBackupStruct
#endif /* (CY_PSOC3) */
#if(!CY_PSOC5A)
/* Sleep Regulator Trim Register */
#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR )
#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR )
/* Sleep Regulator Trim Register */
#define CY_PM_PWRSYS_SLP_TR_REG (* (reg8 *) CYREG_PWRSYS_SLP_TR )
#define CY_PM_PWRSYS_SLP_TR_PTR ( (reg8 *) CYREG_PWRSYS_SLP_TR )
#endif /* (CY_PSOC3) */
/* Reset System Control Register */
#define CY_PM_RESET_CR1_REG (* (reg8 *) CYREG_RESET_CR1 )
#define CY_PM_RESET_CR1_PTR ( (reg8 *) CYREG_RESET_CR1 )
#if(CY_PSOC5A)
/* LVD/POR Test Mode Control Register */
#define CY_PM_RESET_CR3_REG (* (reg8 *) CYREG_RESET_CR3 )
#define CY_PM_RESET_CR3_PTR ( (reg8 *) CYREG_RESET_CR3 )
#endif /* (CY_PSOC5A) */
/* Power Mode Wakeup Trim Register 0 */
#define CY_PM_PWRSYS_WAKE_TR0_REG (* (reg8 *) CYREG_PWRSYS_WAKE_TR0 )
#define CY_PM_PWRSYS_WAKE_TR0_PTR ( (reg8 *) CYREG_PWRSYS_WAKE_TR0 )
@ -457,14 +388,6 @@ typedef struct cyPmBackupStruct
#endif /* (CY_PSOC3) */
#if(CY_PSOC5A)
/* Power Mode Buzz Trim Register */
#define CY_PM_PWRSYS_BUZZ_TR_REG (* (reg8 *) CYREG_PWRSYS_BUZZ_TR )
#define CY_PM_PWRSYS_BUZZ_TR_PTR ( (reg8 *) CYREG_PWRSYS_BUZZ_TR )
#endif /* (CY_PSOC5A) */
/* Power Manager Interrupt Status Register */
#define CY_PM_INT_SR_REG (* (reg8 *) CYREG_PM_INT_SR )
#define CY_PM_INT_SR_PTR ( (reg8 *) CYREG_PM_INT_SR )
@ -533,31 +456,17 @@ typedef struct cyPmBackupStruct
#endif /* (CY_PSOC3) */
#if(CY_PSOC3 || CY_PSOC5LP)
/* Power Mode Wakeup Mask Configuration Register 0 */
#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )
#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 )
/* Power Mode Wakeup Mask Configuration Register 0 */
#define CY_PM_WAKEUP_CFG0_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG0 )
#define CY_PM_WAKEUP_CFG0_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG0 )
/* Power Mode Wakeup Mask Configuration Register 1 */
#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )
#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 )
/* Power Mode Wakeup Mask Configuration Register 2 */
#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )
#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 )
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#if(CY_PSOC5A)
/* Watchdog Timer Configuration Register */
#define CY_PM_WDT_CFG_REG (* (reg8 *) CYREG_PM_WDT_CFG )
#define CY_PM_WDT_CFG_PTR ( (reg8 *) CYREG_PM_WDT_CFG )
#endif /* (CY_PSOC5A) */
/* Power Mode Wakeup Mask Configuration Register 1 */
#define CY_PM_WAKEUP_CFG1_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG1 )
#define CY_PM_WAKEUP_CFG1_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG1 )
/* Power Mode Wakeup Mask Configuration Register 2 */
#define CY_PM_WAKEUP_CFG2_REG (* (reg8 *) CYREG_PM_WAKEUP_CFG2 )
#define CY_PM_WAKEUP_CFG2_PTR ( (reg8 *) CYREG_PM_WAKEUP_CFG2 )
/* Boost Control 2 */
#define CY_PM_BOOST_CR2_REG (* (reg8 *) CYREG_BOOST_CR2 )
@ -657,29 +566,14 @@ typedef struct cyPmBackupStruct
/* The low-voltage-interrupt feature on the external digital supply */
#define CY_PM_RESET_CR1_LVID_EN (0x01u)
#if(CY_PSOC5A)
/* Partly disables PRES-A and PRES-D circuits */
#define CY_PM_RESET_CR1_DIS_PRES1 (0x10u)
/* Partly disables PRES-A and PRES-D circuits */
#define CY_PM_RESET_CR3_DIS_PRES2 (0x08u)
#endif /* (CY_PSOC5A) */
/* Allows the system to program delays on clk_sync_d */
#define CY_PM_CLKDIST_DELAY_EN (0x04u)
#if(CY_PSOC3 || CY_PSOC5LP)
#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu)
/* Holdoff mask sleep trim */
#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu)
#endif /* (CY_PSOC3 || CY_PSOC5LP) */
#define CY_PM_WAKEUP_SRC_CMPS_MASK (0x000Fu)
/* Holdoff mask sleep trim */
#define CY_PM_PWRSYS_SLP_TR_HIBSLP_HOLDOFF_MASK (0x1Fu)
#if(CY_PSOC3)
@ -701,49 +595,12 @@ typedef struct cyPmBackupStruct
#endif /* (CY_PSOC3) */
#if(!CY_PSOC5A)
/* Disable the sleep regulator and shorts vccd to vpwrsleep */
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)
#endif /* (!CY_PSOC5A) */
#if(CY_PSOC5A)
#define CY_PM_PWRSYS_BUZZ_TR_512_TICKS (0x08u)
#define CY_PM_PWRSYS_BUZZ_TR_MASK (0xF0u)
#endif /* (CY_PSOC5A) */
#if(CY_PSOC5A)
/* Watchdog Timer Configuration Register */
#define CY_PM_WDT_CFG_CTW_RESET (0x80u)
/***************************************************************************
* The PICU interrupt type registers are divided into three sections where
* the registers addresses are consecutive.
***************************************************************************/
#define CY_PM_PICU_0_6_INT_BASE (CYDEV_PICU_INTTYPE_PICU0_BASE )
#define CY_PM_PICU_12_INT_BASE (CYDEV_PICU_INTTYPE_PICU12_BASE)
#define CY_PM_PICU_15_INT_BASE (CYDEV_PICU_INTTYPE_PICU15_BASE)
#define CY_PM_PICU_0_6_INT_SIZE (CYDEV_PICU_INTTYPE_PICU0_SIZE + CYDEV_PICU_INTTYPE_PICU1_SIZE + \
CYDEV_PICU_INTTYPE_PICU2_SIZE + CYDEV_PICU_INTTYPE_PICU3_SIZE + \
CYDEV_PICU_INTTYPE_PICU4_SIZE + CYDEV_PICU_INTTYPE_PICU5_SIZE + \
CYDEV_PICU_INTTYPE_PICU6_SIZE)
#define CY_PM_PICU_12_INT_SIZE (CYDEV_PICU_INTTYPE_PICU12_SIZE)
#define CY_PM_PICU_15_INT_SIZE (CYDEV_PICU_INTTYPE_PICU15_SIZE)
#endif /* (CY_PSOC5A) */
/* Disable the sleep regulator and shorts vccd to vpwrsleep */
#define CY_PM_PWRSYS_SLP_TR_BYPASS (0x10u)
/* Boost Control 2: Select external precision reference */
#define CY_PM_BOOST_CR2_EREFSEL_EXT (0x08u)
#if(CY_PSOC3)
#define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)
@ -751,13 +608,12 @@ typedef struct cyPmBackupStruct
#endif /* (CY_PSOC3) */
#if(CY_PSOC5LP)
#if(CY_PSOC5)
#define CY_PM_PWRSYS_WAKE_TR0 (0xFFu)
#define CY_PM_PWRSYS_WAKE_TR1 (0xB0u)
#endif /* (CY_PSOC5LP) */
#endif /* (CY_PSOC5) */
/*******************************************************************************

3
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice.h
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@ -1,10 +1,11 @@
/*******************************************************************************
* FILENAME: cydevice.h
* OBSOLETE: Do not use this file. Use the _trm version instead.
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.

3
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevice_trm.h
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@ -1,10 +1,11 @@
/*******************************************************************************
* FILENAME: cydevice_trm.h
*
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.

3
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu.inc
View File

@ -1,10 +1,11 @@
/*******************************************************************************
* FILENAME: cydevicegnu.inc
* OBSOLETE: Do not use this file. Use the _trm version instead.
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.

3
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicegnu_trm.inc
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@ -1,10 +1,11 @@
/*******************************************************************************
* FILENAME: cydevicegnu_trm.inc
*
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* DESCRIPTION:
* This file provides all of the address values for the entire PSoC device.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.

5356
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar.inc Normal file
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File diff suppressed because it is too large Load Diff

5356
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydeviceiar_trm.inc Normal file
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File diff suppressed because it is too large Load Diff

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv.inc
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@ -1,7 +1,7 @@
;
; FILENAME: cydevicerv.inc
; OBSOLETE: Do not use this file. Use the _trm version instead.
; PSoC Creator 2.2 Component Pack 6
; PSoC Creator 3.0
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydevicerv_trm.inc
View File

@ -1,7 +1,7 @@
;
; FILENAME: cydevicerv_trm.inc
;
; PSoC Creator 2.2 Component Pack 6
; PSoC Creator 3.0
;
; DESCRIPTION:
; This file provides all of the address values for the entire PSoC device.

5
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cydisabledsheets.h Normal file
View File

@ -0,0 +1,5 @@
#ifndef INCLUDED_CYDISABLEDSHEETS_H
#define INCLUDED_CYDISABLEDSHEETS_H
#endif /* INCLUDED_CYDISABLEDSHEETS_H */

678
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
View File

@ -3,25 +3,15 @@
#include <cydevice.h>
#include <cydevice_trm.h>
/* SDCard_RxInternalInterrupt */
#define SDCard_RxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SDCard_RxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SDCard_RxInternalInterrupt__INTC_MASK 0x01u
#define SDCard_RxInternalInterrupt__INTC_NUMBER 0u
#define SDCard_RxInternalInterrupt__INTC_PRIOR_NUM 7u
#define SDCard_RxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define SDCard_RxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SDCard_RxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_TxInternalInterrupt */
#define SDCard_TxInternalInterrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SDCard_TxInternalInterrupt__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SDCard_TxInternalInterrupt__INTC_MASK 0x02u
#define SDCard_TxInternalInterrupt__INTC_NUMBER 1u
#define SDCard_TxInternalInterrupt__INTC_PRIOR_NUM 7u
#define SDCard_TxInternalInterrupt__INTC_PRIOR_REG CYREG_NVIC_PRI_1
#define SDCard_TxInternalInterrupt__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SDCard_TxInternalInterrupt__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_ATN_ISR */
#define SCSI_ATN_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_ATN_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SCSI_ATN_ISR__INTC_MASK 0x01u
#define SCSI_ATN_ISR__INTC_NUMBER 0u
#define SCSI_ATN_ISR__INTC_PRIOR_NUM 7u
#define SCSI_ATN_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_0
#define SCSI_ATN_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_ATN_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__MASK 0x01u
@ -62,6 +52,38 @@
#define SCSI_Out_DBx__BIT_MASK CYREG_PRT0_BIT_MASK
#define SCSI_Out_DBx__BYP CYREG_PRT0_BYP
#define SCSI_Out_DBx__CTL CYREG_PRT0_CTL
#define SCSI_Out_DBx__DB0__MASK 0x01u
#define SCSI_Out_DBx__DB0__PC CYREG_PRT0_PC0
#define SCSI_Out_DBx__DB0__PORT 0u
#define SCSI_Out_DBx__DB0__SHIFT 0
#define SCSI_Out_DBx__DB1__MASK 0x02u
#define SCSI_Out_DBx__DB1__PC CYREG_PRT0_PC1
#define SCSI_Out_DBx__DB1__PORT 0u
#define SCSI_Out_DBx__DB1__SHIFT 1
#define SCSI_Out_DBx__DB2__MASK 0x04u
#define SCSI_Out_DBx__DB2__PC CYREG_PRT0_PC2
#define SCSI_Out_DBx__DB2__PORT 0u
#define SCSI_Out_DBx__DB2__SHIFT 2
#define SCSI_Out_DBx__DB3__MASK 0x08u
#define SCSI_Out_DBx__DB3__PC CYREG_PRT0_PC3
#define SCSI_Out_DBx__DB3__PORT 0u
#define SCSI_Out_DBx__DB3__SHIFT 3
#define SCSI_Out_DBx__DB4__MASK 0x10u
#define SCSI_Out_DBx__DB4__PC CYREG_PRT0_PC4
#define SCSI_Out_DBx__DB4__PORT 0u
#define SCSI_Out_DBx__DB4__SHIFT 4
#define SCSI_Out_DBx__DB5__MASK 0x20u
#define SCSI_Out_DBx__DB5__PC CYREG_PRT0_PC5
#define SCSI_Out_DBx__DB5__PORT 0u
#define SCSI_Out_DBx__DB5__SHIFT 5
#define SCSI_Out_DBx__DB6__MASK 0x40u
#define SCSI_Out_DBx__DB6__PC CYREG_PRT0_PC6
#define SCSI_Out_DBx__DB6__PORT 0u
#define SCSI_Out_DBx__DB6__SHIFT 6
#define SCSI_Out_DBx__DB7__MASK 0x80u
#define SCSI_Out_DBx__DB7__PC CYREG_PRT0_PC7
#define SCSI_Out_DBx__DB7__PORT 0u
#define SCSI_Out_DBx__DB7__SHIFT 7
#define SCSI_Out_DBx__DM0 CYREG_PRT0_DM0
#define SCSI_Out_DBx__DM1 CYREG_PRT0_DM1
#define SCSI_Out_DBx__DM2 CYREG_PRT0_DM2
@ -80,70 +102,48 @@
#define SCSI_Out_DBx__PRTDSI__OUT_SEL1 CYREG_PRT0_OUT_SEL1
#define SCSI_Out_DBx__PRTDSI__SYNC_OUT CYREG_PRT0_SYNC_OUT
#define SCSI_Out_DBx__PS CYREG_PRT0_PS
#define SCSI_Out_DBx__SCSI_Out_DB0__MASK 0x01u
#define SCSI_Out_DBx__SCSI_Out_DB0__PC CYREG_PRT0_PC0
#define SCSI_Out_DBx__SCSI_Out_DB0__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB0__SHIFT 0
#define SCSI_Out_DBx__SCSI_Out_DB1__MASK 0x02u
#define SCSI_Out_DBx__SCSI_Out_DB1__PC CYREG_PRT0_PC1
#define SCSI_Out_DBx__SCSI_Out_DB1__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB1__SHIFT 1
#define SCSI_Out_DBx__SCSI_Out_DB2__MASK 0x04u
#define SCSI_Out_DBx__SCSI_Out_DB2__PC CYREG_PRT0_PC2
#define SCSI_Out_DBx__SCSI_Out_DB2__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB2__SHIFT 2
#define SCSI_Out_DBx__SCSI_Out_DB3__MASK 0x08u
#define SCSI_Out_DBx__SCSI_Out_DB3__PC CYREG_PRT0_PC3
#define SCSI_Out_DBx__SCSI_Out_DB3__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB3__SHIFT 3
#define SCSI_Out_DBx__SCSI_Out_DB4__MASK 0x10u
#define SCSI_Out_DBx__SCSI_Out_DB4__PC CYREG_PRT0_PC4
#define SCSI_Out_DBx__SCSI_Out_DB4__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB4__SHIFT 4
#define SCSI_Out_DBx__SCSI_Out_DB5__MASK 0x20u
#define SCSI_Out_DBx__SCSI_Out_DB5__PC CYREG_PRT0_PC5
#define SCSI_Out_DBx__SCSI_Out_DB5__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB5__SHIFT 5
#define SCSI_Out_DBx__SCSI_Out_DB6__MASK 0x40u
#define SCSI_Out_DBx__SCSI_Out_DB6__PC CYREG_PRT0_PC6
#define SCSI_Out_DBx__SCSI_Out_DB6__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB6__SHIFT 6
#define SCSI_Out_DBx__SCSI_Out_DB7__MASK 0x80u
#define SCSI_Out_DBx__SCSI_Out_DB7__PC CYREG_PRT0_PC7
#define SCSI_Out_DBx__SCSI_Out_DB7__PORT 0u
#define SCSI_Out_DBx__SCSI_Out_DB7__SHIFT 7
#define SCSI_Out_DBx__SHIFT 0
#define SCSI_Out_DBx__SLW CYREG_PRT0_SLW
/* SCSI_RST_ISR */
#define SCSI_RST_ISR__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
#define SCSI_RST_ISR__INTC_CLR_PD_REG CYREG_NVIC_CLRPEND0
#define SCSI_RST_ISR__INTC_MASK 0x400u
#define SCSI_RST_ISR__INTC_NUMBER 10u
#define SCSI_RST_ISR__INTC_PRIOR_NUM 7u
#define SCSI_RST_ISR__INTC_PRIOR_REG CYREG_NVIC_PRI_10
#define SCSI_RST_ISR__INTC_SET_EN_REG CYREG_NVIC_SETENA0
#define SCSI_RST_ISR__INTC_SET_PD_REG CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB06_07_ST
#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB06_ST
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB06_CTL
#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB06_CTL
#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB06_MSK
#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@ -151,13 +151,13 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB06_MSK
#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB06_ST
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
@ -167,28 +167,28 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB07_08_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB07_08_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB07_08_D0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B1_UDB07_08_D1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B1_UDB07_08_F0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B1_UDB07_08_F1
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B1_UDB07_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B1_UDB07_A0
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B1_UDB07_A1
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B1_UDB07_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B1_UDB07_D0
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B1_UDB07_D1
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB07_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB07_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB07_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB05_MSK
#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB05_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B0_UDB06_07_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B0_UDB06_07_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B0_UDB06_07_D0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG CYREG_B0_UDB06_07_D1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG CYREG_B0_UDB06_07_F0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG CYREG_B0_UDB06_07_F1
#define SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG CYREG_B0_UDB06_A0_A1
#define SDCard_BSPIM_sR8_Dp_u0__A0_REG CYREG_B0_UDB06_A0
#define SDCard_BSPIM_sR8_Dp_u0__A1_REG CYREG_B0_UDB06_A1
#define SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG CYREG_B0_UDB06_D0_D1
#define SDCard_BSPIM_sR8_Dp_u0__D0_REG CYREG_B0_UDB06_D0
#define SDCard_BSPIM_sR8_Dp_u0__D1_REG CYREG_B0_UDB06_D1
#define SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B0_UDB06_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B0_UDB06_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B0_UDB06_F1
#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
/* SCSI_In_DBx */
#define SCSI_In_DBx__0__MASK 0x01u
@ -229,6 +229,38 @@
#define SCSI_In_DBx__BIT_MASK CYREG_PRT2_BIT_MASK
#define SCSI_In_DBx__BYP CYREG_PRT2_BYP
#define SCSI_In_DBx__CTL CYREG_PRT2_CTL
#define SCSI_In_DBx__DB0__MASK 0x01u
#define SCSI_In_DBx__DB0__PC CYREG_PRT2_PC0
#define SCSI_In_DBx__DB0__PORT 2u
#define SCSI_In_DBx__DB0__SHIFT 0
#define SCSI_In_DBx__DB1__MASK 0x02u
#define SCSI_In_DBx__DB1__PC CYREG_PRT2_PC1
#define SCSI_In_DBx__DB1__PORT 2u
#define SCSI_In_DBx__DB1__SHIFT 1
#define SCSI_In_DBx__DB2__MASK 0x04u
#define SCSI_In_DBx__DB2__PC CYREG_PRT2_PC2
#define SCSI_In_DBx__DB2__PORT 2u
#define SCSI_In_DBx__DB2__SHIFT 2
#define SCSI_In_DBx__DB3__MASK 0x08u
#define SCSI_In_DBx__DB3__PC CYREG_PRT2_PC3
#define SCSI_In_DBx__DB3__PORT 2u
#define SCSI_In_DBx__DB3__SHIFT 3
#define SCSI_In_DBx__DB4__MASK 0x10u
#define SCSI_In_DBx__DB4__PC CYREG_PRT2_PC4
#define SCSI_In_DBx__DB4__PORT 2u
#define SCSI_In_DBx__DB4__SHIFT 4
#define SCSI_In_DBx__DB5__MASK 0x20u
#define SCSI_In_DBx__DB5__PC CYREG_PRT2_PC5
#define SCSI_In_DBx__DB5__PORT 2u
#define SCSI_In_DBx__DB5__SHIFT 5
#define SCSI_In_DBx__DB6__MASK 0x40u
#define SCSI_In_DBx__DB6__PC CYREG_PRT2_PC6
#define SCSI_In_DBx__DB6__PORT 2u
#define SCSI_In_DBx__DB6__SHIFT 6
#define SCSI_In_DBx__DB7__MASK 0x80u
#define SCSI_In_DBx__DB7__PC CYREG_PRT2_PC7
#define SCSI_In_DBx__DB7__PORT 2u
#define SCSI_In_DBx__DB7__SHIFT 7
#define SCSI_In_DBx__DM0 CYREG_PRT2_DM0
#define SCSI_In_DBx__DM1 CYREG_PRT2_DM1
#define SCSI_In_DBx__DM2 CYREG_PRT2_DM2
@ -247,38 +279,6 @@
#define SCSI_In_DBx__PRTDSI__OUT_SEL1 CYREG_PRT2_OUT_SEL1
#define SCSI_In_DBx__PRTDSI__SYNC_OUT CYREG_PRT2_SYNC_OUT
#define SCSI_In_DBx__PS CYREG_PRT2_PS
#define SCSI_In_DBx__SCSI_Out_DB0__MASK 0x01u
#define SCSI_In_DBx__SCSI_Out_DB0__PC CYREG_PRT2_PC0
#define SCSI_In_DBx__SCSI_Out_DB0__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB0__SHIFT 0
#define SCSI_In_DBx__SCSI_Out_DB1__MASK 0x02u
#define SCSI_In_DBx__SCSI_Out_DB1__PC CYREG_PRT2_PC1
#define SCSI_In_DBx__SCSI_Out_DB1__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB1__SHIFT 1
#define SCSI_In_DBx__SCSI_Out_DB2__MASK 0x04u
#define SCSI_In_DBx__SCSI_Out_DB2__PC CYREG_PRT2_PC2
#define SCSI_In_DBx__SCSI_Out_DB2__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB2__SHIFT 2
#define SCSI_In_DBx__SCSI_Out_DB3__MASK 0x08u
#define SCSI_In_DBx__SCSI_Out_DB3__PC CYREG_PRT2_PC3
#define SCSI_In_DBx__SCSI_Out_DB3__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB3__SHIFT 3
#define SCSI_In_DBx__SCSI_Out_DB4__MASK 0x10u
#define SCSI_In_DBx__SCSI_Out_DB4__PC CYREG_PRT2_PC4
#define SCSI_In_DBx__SCSI_Out_DB4__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB4__SHIFT 4
#define SCSI_In_DBx__SCSI_Out_DB5__MASK 0x20u
#define SCSI_In_DBx__SCSI_Out_DB5__PC CYREG_PRT2_PC5
#define SCSI_In_DBx__SCSI_Out_DB5__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB5__SHIFT 5
#define SCSI_In_DBx__SCSI_Out_DB6__MASK 0x40u
#define SCSI_In_DBx__SCSI_Out_DB6__PC CYREG_PRT2_PC6
#define SCSI_In_DBx__SCSI_Out_DB6__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB6__SHIFT 6
#define SCSI_In_DBx__SCSI_Out_DB7__MASK 0x80u
#define SCSI_In_DBx__SCSI_Out_DB7__PC CYREG_PRT2_PC7
#define SCSI_In_DBx__SCSI_Out_DB7__PORT 2u
#define SCSI_In_DBx__SCSI_Out_DB7__SHIFT 7
#define SCSI_In_DBx__SHIFT 0
#define SCSI_In_DBx__SLW CYREG_PRT2_SLW
@ -307,24 +307,24 @@
/* SD_Clk_Ctl */
#define SD_Clk_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SD_Clk_Ctl_Sync_ctrl_reg__0__POS 0
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB06_07_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB06_07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB06_07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB06_07_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB06_07_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB06_07_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB06_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB06_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB06_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB06_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB06_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB07_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK 0x01u
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB06_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB06_MSK_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
#define SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB07_MSK
#define SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
/* PARITY_EN */
#define PARITY_EN__0__MASK 0x10u
@ -358,6 +358,41 @@
#define PARITY_EN__SHIFT 4
#define PARITY_EN__SLW CYREG_PRT5_SLW
/* SCSI_ATN */
#define SCSI_ATN__0__MASK 0x20u
#define SCSI_ATN__0__PC CYREG_PRT12_PC5
#define SCSI_ATN__0__PORT 12u
#define SCSI_ATN__0__SHIFT 5
#define SCSI_ATN__AG CYREG_PRT12_AG
#define SCSI_ATN__BIE CYREG_PRT12_BIE
#define SCSI_ATN__BIT_MASK CYREG_PRT12_BIT_MASK
#define SCSI_ATN__BYP CYREG_PRT12_BYP
#define SCSI_ATN__DM0 CYREG_PRT12_DM0
#define SCSI_ATN__DM1 CYREG_PRT12_DM1
#define SCSI_ATN__DM2 CYREG_PRT12_DM2
#define SCSI_ATN__DR CYREG_PRT12_DR
#define SCSI_ATN__INP_DIS CYREG_PRT12_INP_DIS
#define SCSI_ATN__INT__MASK 0x20u
#define SCSI_ATN__INT__PC CYREG_PRT12_PC5
#define SCSI_ATN__INT__PORT 12u
#define SCSI_ATN__INT__SHIFT 5
#define SCSI_ATN__MASK 0x20u
#define SCSI_ATN__PORT 12u
#define SCSI_ATN__PRT CYREG_PRT12_PRT
#define SCSI_ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SCSI_ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SCSI_ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SCSI_ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SCSI_ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SCSI_ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SCSI_ATN__PS CYREG_PRT12_PS
#define SCSI_ATN__SHIFT 5
#define SCSI_ATN__SIO_CFG CYREG_PRT12_SIO_CFG
#define SCSI_ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SCSI_ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SCSI_ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SCSI_ATN__SLW CYREG_PRT12_SLW
/* SCSI_Out */
#define SCSI_Out__0__AG CYREG_PRT4_AG
#define SCSI_Out__0__AMUX CYREG_PRT4_AMUX
@ -900,6 +935,44 @@
#define SCSI_Out__SEL__SHIFT 0
#define SCSI_Out__SEL__SLW CYREG_PRT6_SLW
/* SCSI_RST */
#define SCSI_RST__0__MASK 0x40u
#define SCSI_RST__0__PC CYREG_PRT6_PC6
#define SCSI_RST__0__PORT 6u
#define SCSI_RST__0__SHIFT 6
#define SCSI_RST__AG CYREG_PRT6_AG
#define SCSI_RST__AMUX CYREG_PRT6_AMUX
#define SCSI_RST__BIE CYREG_PRT6_BIE
#define SCSI_RST__BIT_MASK CYREG_PRT6_BIT_MASK
#define SCSI_RST__BYP CYREG_PRT6_BYP
#define SCSI_RST__CTL CYREG_PRT6_CTL
#define SCSI_RST__DM0 CYREG_PRT6_DM0
#define SCSI_RST__DM1 CYREG_PRT6_DM1
#define SCSI_RST__DM2 CYREG_PRT6_DM2
#define SCSI_RST__DR CYREG_PRT6_DR
#define SCSI_RST__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_RST__INTSTAT CYREG_PICU6_INTSTAT
#define SCSI_RST__INT__MASK 0x40u
#define SCSI_RST__INT__PC CYREG_PRT6_PC6
#define SCSI_RST__INT__PORT 6u
#define SCSI_RST__INT__SHIFT 6
#define SCSI_RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_RST__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_RST__MASK 0x40u
#define SCSI_RST__PORT 6u
#define SCSI_RST__PRT CYREG_PRT6_PRT
#define SCSI_RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define SCSI_RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define SCSI_RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define SCSI_RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define SCSI_RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define SCSI_RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_RST__PS CYREG_PRT6_PS
#define SCSI_RST__SHIFT 6
#define SCSI_RST__SLW CYREG_PRT6_SLW
#define SCSI_RST__SNAP CYREG_PICU6_SNAP
/* SCSI_ID */
#define SCSI_ID__0__MASK 0x80u
#define SCSI_ID__0__PC CYREG_PRT5_PC7
@ -965,32 +1038,33 @@
#define SCSI_In__0__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SCSI_In__0__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SCSI_In__0__SLW CYREG_PRT12_SLW
#define SCSI_In__1__AG CYREG_PRT12_AG
#define SCSI_In__1__BIE CYREG_PRT12_BIE
#define SCSI_In__1__BIT_MASK CYREG_PRT12_BIT_MASK
#define SCSI_In__1__BYP CYREG_PRT12_BYP
#define SCSI_In__1__DM0 CYREG_PRT12_DM0
#define SCSI_In__1__DM1 CYREG_PRT12_DM1
#define SCSI_In__1__DM2 CYREG_PRT12_DM2
#define SCSI_In__1__DR CYREG_PRT12_DR
#define SCSI_In__1__INP_DIS CYREG_PRT12_INP_DIS
#define SCSI_In__1__MASK 0x20u
#define SCSI_In__1__PC CYREG_PRT12_PC5
#define SCSI_In__1__PORT 12u
#define SCSI_In__1__PRT CYREG_PRT12_PRT
#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SCSI_In__1__PS CYREG_PRT12_PS
#define SCSI_In__1__SHIFT 5
#define SCSI_In__1__SIO_CFG CYREG_PRT12_SIO_CFG
#define SCSI_In__1__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SCSI_In__1__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SCSI_In__1__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SCSI_In__1__SLW CYREG_PRT12_SLW
#define SCSI_In__1__AG CYREG_PRT6_AG
#define SCSI_In__1__AMUX CYREG_PRT6_AMUX
#define SCSI_In__1__BIE CYREG_PRT6_BIE
#define SCSI_In__1__BIT_MASK CYREG_PRT6_BIT_MASK
#define SCSI_In__1__BYP CYREG_PRT6_BYP
#define SCSI_In__1__CTL CYREG_PRT6_CTL
#define SCSI_In__1__DM0 CYREG_PRT6_DM0
#define SCSI_In__1__DM1 CYREG_PRT6_DM1
#define SCSI_In__1__DM2 CYREG_PRT6_DM2
#define SCSI_In__1__DR CYREG_PRT6_DR
#define SCSI_In__1__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__1__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__1__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__1__MASK 0x10u
#define SCSI_In__1__PC CYREG_PRT6_PC4
#define SCSI_In__1__PORT 6u
#define SCSI_In__1__PRT CYREG_PRT6_PRT
#define SCSI_In__1__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define SCSI_In__1__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define SCSI_In__1__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define SCSI_In__1__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define SCSI_In__1__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define SCSI_In__1__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__1__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__1__PS CYREG_PRT6_PS
#define SCSI_In__1__SHIFT 4
#define SCSI_In__1__SLW CYREG_PRT6_SLW
#define SCSI_In__2__AG CYREG_PRT6_AG
#define SCSI_In__2__AMUX CYREG_PRT6_AMUX
#define SCSI_In__2__BIE CYREG_PRT6_BIE
@ -1004,8 +1078,8 @@
#define SCSI_In__2__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__2__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__2__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__2__MASK 0x10u
#define SCSI_In__2__PC CYREG_PRT6_PC4
#define SCSI_In__2__MASK 0x20u
#define SCSI_In__2__PC CYREG_PRT6_PC5
#define SCSI_In__2__PORT 6u
#define SCSI_In__2__PRT CYREG_PRT6_PRT
#define SCSI_In__2__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
@ -1016,7 +1090,7 @@
#define SCSI_In__2__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__2__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__2__PS CYREG_PRT6_PS
#define SCSI_In__2__SHIFT 4
#define SCSI_In__2__SHIFT 5
#define SCSI_In__2__SLW CYREG_PRT6_SLW
#define SCSI_In__3__AG CYREG_PRT6_AG
#define SCSI_In__3__AMUX CYREG_PRT6_AMUX
@ -1031,8 +1105,8 @@
#define SCSI_In__3__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__3__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__3__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__3__MASK 0x20u
#define SCSI_In__3__PC CYREG_PRT6_PC5
#define SCSI_In__3__MASK 0x80u
#define SCSI_In__3__PC CYREG_PRT6_PC7
#define SCSI_In__3__PORT 6u
#define SCSI_In__3__PRT CYREG_PRT6_PRT
#define SCSI_In__3__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
@ -1043,62 +1117,62 @@
#define SCSI_In__3__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__3__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__3__PS CYREG_PRT6_PS
#define SCSI_In__3__SHIFT 5
#define SCSI_In__3__SHIFT 7
#define SCSI_In__3__SLW CYREG_PRT6_SLW
#define SCSI_In__4__AG CYREG_PRT6_AG
#define SCSI_In__4__AMUX CYREG_PRT6_AMUX
#define SCSI_In__4__BIE CYREG_PRT6_BIE
#define SCSI_In__4__BIT_MASK CYREG_PRT6_BIT_MASK
#define SCSI_In__4__BYP CYREG_PRT6_BYP
#define SCSI_In__4__CTL CYREG_PRT6_CTL
#define SCSI_In__4__DM0 CYREG_PRT6_DM0
#define SCSI_In__4__DM1 CYREG_PRT6_DM1
#define SCSI_In__4__DM2 CYREG_PRT6_DM2
#define SCSI_In__4__DR CYREG_PRT6_DR
#define SCSI_In__4__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__4__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__4__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__4__MASK 0x40u
#define SCSI_In__4__PC CYREG_PRT6_PC6
#define SCSI_In__4__PORT 6u
#define SCSI_In__4__PRT CYREG_PRT6_PRT
#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__4__PS CYREG_PRT6_PS
#define SCSI_In__4__SHIFT 6
#define SCSI_In__4__SLW CYREG_PRT6_SLW
#define SCSI_In__5__AG CYREG_PRT6_AG
#define SCSI_In__5__AMUX CYREG_PRT6_AMUX
#define SCSI_In__5__BIE CYREG_PRT6_BIE
#define SCSI_In__5__BIT_MASK CYREG_PRT6_BIT_MASK
#define SCSI_In__5__BYP CYREG_PRT6_BYP
#define SCSI_In__5__CTL CYREG_PRT6_CTL
#define SCSI_In__5__DM0 CYREG_PRT6_DM0
#define SCSI_In__5__DM1 CYREG_PRT6_DM1
#define SCSI_In__5__DM2 CYREG_PRT6_DM2
#define SCSI_In__5__DR CYREG_PRT6_DR
#define SCSI_In__5__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__5__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__5__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__5__MASK 0x80u
#define SCSI_In__5__PC CYREG_PRT6_PC7
#define SCSI_In__5__PORT 6u
#define SCSI_In__5__PRT CYREG_PRT6_PRT
#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__5__PS CYREG_PRT6_PS
#define SCSI_In__5__SHIFT 7
#define SCSI_In__5__SLW CYREG_PRT6_SLW
#define SCSI_In__4__AG CYREG_PRT5_AG
#define SCSI_In__4__AMUX CYREG_PRT5_AMUX
#define SCSI_In__4__BIE CYREG_PRT5_BIE
#define SCSI_In__4__BIT_MASK CYREG_PRT5_BIT_MASK
#define SCSI_In__4__BYP CYREG_PRT5_BYP
#define SCSI_In__4__CTL CYREG_PRT5_CTL
#define SCSI_In__4__DM0 CYREG_PRT5_DM0
#define SCSI_In__4__DM1 CYREG_PRT5_DM1
#define SCSI_In__4__DM2 CYREG_PRT5_DM2
#define SCSI_In__4__DR CYREG_PRT5_DR
#define SCSI_In__4__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__4__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__4__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__4__MASK 0x01u
#define SCSI_In__4__PC CYREG_PRT5_PC0
#define SCSI_In__4__PORT 5u
#define SCSI_In__4__PRT CYREG_PRT5_PRT
#define SCSI_In__4__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define SCSI_In__4__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define SCSI_In__4__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define SCSI_In__4__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define SCSI_In__4__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define SCSI_In__4__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__4__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__4__PS CYREG_PRT5_PS
#define SCSI_In__4__SHIFT 0
#define SCSI_In__4__SLW CYREG_PRT5_SLW
#define SCSI_In__5__AG CYREG_PRT5_AG
#define SCSI_In__5__AMUX CYREG_PRT5_AMUX
#define SCSI_In__5__BIE CYREG_PRT5_BIE
#define SCSI_In__5__BIT_MASK CYREG_PRT5_BIT_MASK
#define SCSI_In__5__BYP CYREG_PRT5_BYP
#define SCSI_In__5__CTL CYREG_PRT5_CTL
#define SCSI_In__5__DM0 CYREG_PRT5_DM0
#define SCSI_In__5__DM1 CYREG_PRT5_DM1
#define SCSI_In__5__DM2 CYREG_PRT5_DM2
#define SCSI_In__5__DR CYREG_PRT5_DR
#define SCSI_In__5__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__5__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__5__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__5__MASK 0x02u
#define SCSI_In__5__PC CYREG_PRT5_PC1
#define SCSI_In__5__PORT 5u
#define SCSI_In__5__PRT CYREG_PRT5_PRT
#define SCSI_In__5__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define SCSI_In__5__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define SCSI_In__5__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define SCSI_In__5__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define SCSI_In__5__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define SCSI_In__5__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__5__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__5__PS CYREG_PRT5_PS
#define SCSI_In__5__SHIFT 1
#define SCSI_In__5__SLW CYREG_PRT5_SLW
#define SCSI_In__6__AG CYREG_PRT5_AG
#define SCSI_In__6__AMUX CYREG_PRT5_AMUX
#define SCSI_In__6__BIE CYREG_PRT5_BIE
@ -1112,8 +1186,8 @@
#define SCSI_In__6__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__6__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__6__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__6__MASK 0x01u
#define SCSI_In__6__PC CYREG_PRT5_PC0
#define SCSI_In__6__MASK 0x04u
#define SCSI_In__6__PC CYREG_PRT5_PC2
#define SCSI_In__6__PORT 5u
#define SCSI_In__6__PRT CYREG_PRT5_PRT
#define SCSI_In__6__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
@ -1124,7 +1198,7 @@
#define SCSI_In__6__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__6__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__6__PS CYREG_PRT5_PS
#define SCSI_In__6__SHIFT 0
#define SCSI_In__6__SHIFT 2
#define SCSI_In__6__SLW CYREG_PRT5_SLW
#define SCSI_In__7__AG CYREG_PRT5_AG
#define SCSI_In__7__AMUX CYREG_PRT5_AMUX
@ -1139,8 +1213,8 @@
#define SCSI_In__7__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__7__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__7__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__7__MASK 0x02u
#define SCSI_In__7__PC CYREG_PRT5_PC1
#define SCSI_In__7__MASK 0x08u
#define SCSI_In__7__PC CYREG_PRT5_PC3
#define SCSI_In__7__PORT 5u
#define SCSI_In__7__PRT CYREG_PRT5_PRT
#define SCSI_In__7__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
@ -1151,62 +1225,8 @@
#define SCSI_In__7__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__7__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__7__PS CYREG_PRT5_PS
#define SCSI_In__7__SHIFT 1
#define SCSI_In__7__SHIFT 3
#define SCSI_In__7__SLW CYREG_PRT5_SLW
#define SCSI_In__8__AG CYREG_PRT5_AG
#define SCSI_In__8__AMUX CYREG_PRT5_AMUX
#define SCSI_In__8__BIE CYREG_PRT5_BIE
#define SCSI_In__8__BIT_MASK CYREG_PRT5_BIT_MASK
#define SCSI_In__8__BYP CYREG_PRT5_BYP
#define SCSI_In__8__CTL CYREG_PRT5_CTL
#define SCSI_In__8__DM0 CYREG_PRT5_DM0
#define SCSI_In__8__DM1 CYREG_PRT5_DM1
#define SCSI_In__8__DM2 CYREG_PRT5_DM2
#define SCSI_In__8__DR CYREG_PRT5_DR
#define SCSI_In__8__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__8__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__8__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__8__MASK 0x04u
#define SCSI_In__8__PC CYREG_PRT5_PC2
#define SCSI_In__8__PORT 5u
#define SCSI_In__8__PRT CYREG_PRT5_PRT
#define SCSI_In__8__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define SCSI_In__8__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define SCSI_In__8__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define SCSI_In__8__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define SCSI_In__8__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define SCSI_In__8__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__8__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__8__PS CYREG_PRT5_PS
#define SCSI_In__8__SHIFT 2
#define SCSI_In__8__SLW CYREG_PRT5_SLW
#define SCSI_In__9__AG CYREG_PRT5_AG
#define SCSI_In__9__AMUX CYREG_PRT5_AMUX
#define SCSI_In__9__BIE CYREG_PRT5_BIE
#define SCSI_In__9__BIT_MASK CYREG_PRT5_BIT_MASK
#define SCSI_In__9__BYP CYREG_PRT5_BYP
#define SCSI_In__9__CTL CYREG_PRT5_CTL
#define SCSI_In__9__DM0 CYREG_PRT5_DM0
#define SCSI_In__9__DM1 CYREG_PRT5_DM1
#define SCSI_In__9__DM2 CYREG_PRT5_DM2
#define SCSI_In__9__DR CYREG_PRT5_DR
#define SCSI_In__9__INP_DIS CYREG_PRT5_INP_DIS
#define SCSI_In__9__LCD_COM_SEG CYREG_PRT5_LCD_COM_SEG
#define SCSI_In__9__LCD_EN CYREG_PRT5_LCD_EN
#define SCSI_In__9__MASK 0x08u
#define SCSI_In__9__PC CYREG_PRT5_PC3
#define SCSI_In__9__PORT 5u
#define SCSI_In__9__PRT CYREG_PRT5_PRT
#define SCSI_In__9__PRTDSI__CAPS_SEL CYREG_PRT5_CAPS_SEL
#define SCSI_In__9__PRTDSI__DBL_SYNC_IN CYREG_PRT5_DBL_SYNC_IN
#define SCSI_In__9__PRTDSI__OE_SEL0 CYREG_PRT5_OE_SEL0
#define SCSI_In__9__PRTDSI__OE_SEL1 CYREG_PRT5_OE_SEL1
#define SCSI_In__9__PRTDSI__OUT_SEL0 CYREG_PRT5_OUT_SEL0
#define SCSI_In__9__PRTDSI__OUT_SEL1 CYREG_PRT5_OUT_SEL1
#define SCSI_In__9__PRTDSI__SYNC_OUT CYREG_PRT5_SYNC_OUT
#define SCSI_In__9__PS CYREG_PRT5_PS
#define SCSI_In__9__SHIFT 3
#define SCSI_In__9__SLW CYREG_PRT5_SLW
#define SCSI_In__ACK__AG CYREG_PRT6_AG
#define SCSI_In__ACK__AMUX CYREG_PRT6_AMUX
#define SCSI_In__ACK__BIE CYREG_PRT6_BIE
@ -1234,32 +1254,6 @@
#define SCSI_In__ACK__PS CYREG_PRT6_PS
#define SCSI_In__ACK__SHIFT 5
#define SCSI_In__ACK__SLW CYREG_PRT6_SLW
#define SCSI_In__ATN__AG CYREG_PRT12_AG
#define SCSI_In__ATN__BIE CYREG_PRT12_BIE
#define SCSI_In__ATN__BIT_MASK CYREG_PRT12_BIT_MASK
#define SCSI_In__ATN__BYP CYREG_PRT12_BYP
#define SCSI_In__ATN__DM0 CYREG_PRT12_DM0
#define SCSI_In__ATN__DM1 CYREG_PRT12_DM1
#define SCSI_In__ATN__DM2 CYREG_PRT12_DM2
#define SCSI_In__ATN__DR CYREG_PRT12_DR
#define SCSI_In__ATN__INP_DIS CYREG_PRT12_INP_DIS
#define SCSI_In__ATN__MASK 0x20u
#define SCSI_In__ATN__PC CYREG_PRT12_PC5
#define SCSI_In__ATN__PORT 12u
#define SCSI_In__ATN__PRT CYREG_PRT12_PRT
#define SCSI_In__ATN__PRTDSI__DBL_SYNC_IN CYREG_PRT12_DBL_SYNC_IN
#define SCSI_In__ATN__PRTDSI__OE_SEL0 CYREG_PRT12_OE_SEL0
#define SCSI_In__ATN__PRTDSI__OE_SEL1 CYREG_PRT12_OE_SEL1
#define SCSI_In__ATN__PRTDSI__OUT_SEL0 CYREG_PRT12_OUT_SEL0
#define SCSI_In__ATN__PRTDSI__OUT_SEL1 CYREG_PRT12_OUT_SEL1
#define SCSI_In__ATN__PRTDSI__SYNC_OUT CYREG_PRT12_SYNC_OUT
#define SCSI_In__ATN__PS CYREG_PRT12_PS
#define SCSI_In__ATN__SHIFT 5
#define SCSI_In__ATN__SIO_CFG CYREG_PRT12_SIO_CFG
#define SCSI_In__ATN__SIO_DIFF CYREG_PRT12_SIO_DIFF
#define SCSI_In__ATN__SIO_HYST_EN CYREG_PRT12_SIO_HYST_EN
#define SCSI_In__ATN__SIO_REG_HIFREQ CYREG_PRT12_SIO_REG_HIFREQ
#define SCSI_In__ATN__SLW CYREG_PRT12_SLW
#define SCSI_In__BSY__AG CYREG_PRT6_AG
#define SCSI_In__BSY__AMUX CYREG_PRT6_AMUX
#define SCSI_In__BSY__BIE CYREG_PRT6_BIE
@ -1421,33 +1415,6 @@
#define SCSI_In__REQ__PS CYREG_PRT5_PS
#define SCSI_In__REQ__SHIFT 2
#define SCSI_In__REQ__SLW CYREG_PRT5_SLW
#define SCSI_In__RST__AG CYREG_PRT6_AG
#define SCSI_In__RST__AMUX CYREG_PRT6_AMUX
#define SCSI_In__RST__BIE CYREG_PRT6_BIE
#define SCSI_In__RST__BIT_MASK CYREG_PRT6_BIT_MASK
#define SCSI_In__RST__BYP CYREG_PRT6_BYP
#define SCSI_In__RST__CTL CYREG_PRT6_CTL
#define SCSI_In__RST__DM0 CYREG_PRT6_DM0
#define SCSI_In__RST__DM1 CYREG_PRT6_DM1
#define SCSI_In__RST__DM2 CYREG_PRT6_DM2
#define SCSI_In__RST__DR CYREG_PRT6_DR
#define SCSI_In__RST__INP_DIS CYREG_PRT6_INP_DIS
#define SCSI_In__RST__LCD_COM_SEG CYREG_PRT6_LCD_COM_SEG
#define SCSI_In__RST__LCD_EN CYREG_PRT6_LCD_EN
#define SCSI_In__RST__MASK 0x40u
#define SCSI_In__RST__PC CYREG_PRT6_PC6
#define SCSI_In__RST__PORT 6u
#define SCSI_In__RST__PRT CYREG_PRT6_PRT
#define SCSI_In__RST__PRTDSI__CAPS_SEL CYREG_PRT6_CAPS_SEL
#define SCSI_In__RST__PRTDSI__DBL_SYNC_IN CYREG_PRT6_DBL_SYNC_IN
#define SCSI_In__RST__PRTDSI__OE_SEL0 CYREG_PRT6_OE_SEL0
#define SCSI_In__RST__PRTDSI__OE_SEL1 CYREG_PRT6_OE_SEL1
#define SCSI_In__RST__PRTDSI__OUT_SEL0 CYREG_PRT6_OUT_SEL0
#define SCSI_In__RST__PRTDSI__OUT_SEL1 CYREG_PRT6_OUT_SEL1
#define SCSI_In__RST__PRTDSI__SYNC_OUT CYREG_PRT6_SYNC_OUT
#define SCSI_In__RST__PS CYREG_PRT6_PS
#define SCSI_In__RST__SHIFT 6
#define SCSI_In__RST__SLW CYREG_PRT6_SLW
#define SCSI_In__SEL__AG CYREG_PRT5_AG
#define SCSI_In__SEL__AMUX CYREG_PRT5_AMUX
#define SCSI_In__SEL__BIE CYREG_PRT5_BIE
@ -1831,7 +1798,6 @@
#define CYDEV_DEBUGGING_DPS_JTAG_5 0
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_ENABLE 1
#define CYDEV_DEBUGGING_REQXRES 1
#define CYDEV_DEBUGGING_XRES 0
#define CYDEV_DEBUG_ENABLE_MASK 0x20u
#define CYDEV_DEBUG_ENABLE_REGISTER CYREG_MLOGIC_DEBUG
@ -1839,7 +1805,7 @@
#define CYDEV_ECC_ENABLE 0
#define CYDEV_HEAP_SIZE 0x1000
#define CYDEV_INSTRUCT_CACHE_ENABLED 1
#define CYDEV_INTR_RISING 0x00000003u
#define CYDEV_INTR_RISING 0x00000001u
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LOADABLE 2

163
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* FILENAME: cyfitter_cfg.c
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* Description:
* This file is automatically generated by PSoC Creator with device
@ -21,6 +21,62 @@
#include <CyLib.h>
#include <cyfitter_cfg.h>
#define CY_NEED_CYCLOCKSTARTUPERROR 1
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#define CYPACKED
#define CYPACKED_ATTR __attribute__ ((packed))
#define CYALIGNED __attribute__ ((aligned))
#define CY_CFG_UNUSED __attribute__ ((unused))
#define CY_CFG_SECTION __attribute__ ((section(".psocinit")))
#if defined(__ARMCC_VERSION)
#define CY_CFG_MEMORY_BARRIER() __memory_changed()
#else
#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
#endif
#elif defined(__ICCARM__)
#include <intrinsics.h>
#define CYPACKED __packed
#define CYPACKED_ATTR
#define CYALIGNED _Pragma("data_alignment=4")
#define CY_CFG_UNUSED _Pragma("diag_suppress=Pe177")
#define CY_CFG_SECTION _Pragma("location=\".psocinit\"")
#define CY_CFG_MEMORY_BARRIER() __DMB()
#else
#error Unsupported toolchain
#endif
CY_CFG_UNUSED
static void CYMEMZERO(void *s, size_t n);
CY_CFG_UNUSED
static void CYMEMZERO(void *s, size_t n)
{
(void)memset(s, 0, n);
}
CY_CFG_UNUSED
static void CYCONFIGCPY(void *dest, const void *src, size_t n);
CY_CFG_UNUSED
static void CYCONFIGCPY(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
CY_CFG_UNUSED
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
CY_CFG_UNUSED
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
/* Clock startup error codes */
#define CYCLOCKSTART_NO_ERROR 0u
#define CYCLOCKSTART_XTAL_ERROR 1u
@ -43,13 +99,9 @@
* void
*
*******************************************************************************/
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((unused))
#endif
CY_CFG_UNUSED
static void CyClockStartupError(uint8 errorCode);
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((unused))
#endif
CY_CFG_UNUSED
static void CyClockStartupError(uint8 errorCode)
{
/* To remove the compiler warning if errorCode not used. */
@ -69,79 +121,42 @@ static void CyClockStartupError(uint8 errorCode)
}
#endif
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
#define CYPACKED __attribute__ ((packed))
#define CYALIGNED __attribute__ ((aligned))
#if defined(__ARMCC_VERSION)
#define CY_CFG_MEMORY_BARRIER() __memory_changed()
#else
#define CY_CFG_MEMORY_BARRIER() __sync_synchronize()
#endif
__attribute__ ((unused))
static void CYMEMZERO(void *s, size_t n);
__attribute__ ((unused))
static void CYMEMZERO(void *s, size_t n)
{
(void)memset(s, 0, n);
}
__attribute__ ((unused))
static void CYCONFIGCPY(void *dest, const void *src, size_t n);
__attribute__ ((unused))
static void CYCONFIGCPY(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
__attribute__ ((unused))
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n);
__attribute__ ((unused))
static void CYCONFIGCPYCODE(void *dest, const void *src, size_t n)
{
(void)memcpy(dest, src, n);
}
#else
#error Unsupported toolchain
#endif
#define CY_CFG_BASE_ADDR_COUNT 16u
typedef struct
#define CY_CFG_BASE_ADDR_COUNT 22u
CYPACKED typedef struct
{
uint8 offset;
uint8 value;
} CYPACKED cy_cfg_addrvalue_t;
} CYPACKED_ATTR cy_cfg_addrvalue_t;
#define cy_cfg_addr_table ((const uint32 CYFAR *)0x48000000u)
#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000040u)
#define cy_cfg_data_table ((const cy_cfg_addrvalue_t CYFAR *)0x48000058u)
/* UDB_1_1_0_CONFIG Address: CYDEV_UCFG_B1_P3_U1_BASE Size (bytes): 128 */
#define BS_UDB_1_1_0_CONFIG_VAL ((const uint8 CYFAR *)0x480002D4u)
/* UDB_1_2_1_CONFIG Address: CYDEV_UCFG_B0_P3_U0_BASE Size (bytes): 128 */
#define BS_UDB_1_2_1_CONFIG_VAL ((const uint8 CYFAR *)0x48000318u)
/* IOPINS0_0 Address: CYREG_PRT0_DM0 Size (bytes): 8 */
#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000354u)
#define BS_IOPINS0_0_VAL ((const uint8 CYFAR *)0x48000398u)
/* IOPINS0_7 Address: CYREG_PRT12_DR Size (bytes): 10 */
#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x4800035Cu)
#define BS_IOPINS0_7_VAL ((const uint8 CYFAR *)0x480003A0u)
/* IOPINS1_7 Address: CYREG_PRT12_DR + 0x0000000Bu Size (bytes): 5 */
#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x48000368u)
#define BS_IOPINS1_7_VAL ((const uint8 CYFAR *)0x480003ACu)
/* IOPINS0_2 Address: CYREG_PRT2_DM0 Size (bytes): 8 */
#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x48000370u)
#define BS_IOPINS0_2_VAL ((const uint8 CYFAR *)0x480003B4u)
/* IOPINS0_3 Address: CYREG_PRT3_DR Size (bytes): 10 */
#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x48000378u)
#define BS_IOPINS0_3_VAL ((const uint8 CYFAR *)0x480003BCu)
/* IOPINS0_4 Address: CYREG_PRT4_DM0 Size (bytes): 8 */
#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x48000384u)
#define BS_IOPINS0_4_VAL ((const uint8 CYFAR *)0x480003C8u)
/* IOPINS0_5 Address: CYREG_PRT5_DR Size (bytes): 10 */
#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x4800038Cu)
#define BS_IOPINS0_5_VAL ((const uint8 CYFAR *)0x480003D0u)
/* IOPINS0_6 Address: CYREG_PRT6_DM0 Size (bytes): 8 */
#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x48000398u)
#define BS_IOPINS0_6_VAL ((const uint8 CYFAR *)0x480003DCu)
/*******************************************************************************
@ -216,13 +231,19 @@ static void ClockSetup(void)
/* Configure PLL based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_P), 0x0F15u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1051u);
CY_SET_XTND_REG16((void CYFAR *)(CYREG_FASTCLK_PLL_CFG0), 0x1251u);
/* Wait up to 250us for the PLL to lock */
pllLock = 0u;
for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--) {
for (timeout = 250u / 10u; (timeout > 0u) && (pllLock != 0x03u); timeout--)
{
pllLock = 0x03u & ((uint8)((uint8)pllLock << 1) | ((CY_GET_XTND_REG8((void CYFAR *)CYREG_FASTCLK_PLL_SR) & 0x01u) >> 0));
CyDelayCycles(10u * 48u); /* Delay 10us based on 48MHz clock */
}
/* If we ran out of time the PLL didn't lock so go to the error function */
if (timeout == 0u)
{
CyClockStartupError(CYCLOCKSTART_PLL_ERROR);
}
/* Configure Bus/Master Clock based on settings from Clock DWR */
CY_SET_XTND_REG16((void CYFAR *)(CYREG_CLKDIST_MSTR0), 0x0100u);
@ -258,8 +279,8 @@ static void AnalogSetDefault(void);
static void AnalogSetDefault(void)
{
uint8 bg_xover_inl_trim = CY_GET_XTND_REG8((void CYFAR *)(CYREG_FLSHID_MFG_CFG_BG_XOVER_INL_TRIM + 1u));
CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT0, bg_xover_inl_trim & 0x07u);
CY_SET_XTND_REG8((void CYFAR *)CYREG_BG_DFT1, ((uint8)((uint8)bg_xover_inl_trim >> 4)) & 0x0Fu);
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT0), (bg_xover_inl_trim & 0x07u));
CY_SET_XTND_REG8((void CYFAR *)(CYREG_BG_DFT1), ((bg_xover_inl_trim >> 4) & 0x0Fu));
CY_SET_XTND_REG8((void CYFAR *)CYREG_PUMP_CR0, 0x44u);
}
@ -332,25 +353,25 @@ void cyfitter_cfg(void)
{
typedef struct {
CYPACKED typedef struct {
void CYFAR *address;
uint16 size;
} CYPACKED cfg_memset_t;
} CYPACKED_ATTR cfg_memset_t;
typedef struct {
CYPACKED typedef struct {
void CYFAR *dest;
const void CYFAR *src;
uint16 size;
} CYPACKED cfg_memcpy_t;
} CYPACKED_ATTR cfg_memcpy_t;
static const cfg_memset_t CYCODE cfg_memset_list [] = {
/* address, size */
{(void CYFAR *)(CYREG_PRT1_DR), 16u},
{(void CYFAR *)(CYREG_PRT15_DR), 16u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 4096u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 640u},
{(void CYFAR *)(CYDEV_UCFG_B1_P3_ROUTE_BASE), 1280u},
{(void CYFAR *)(CYDEV_UCFG_B0_P0_U0_BASE), 1536u},
{(void CYFAR *)(CYDEV_UCFG_B0_P3_U1_BASE), 2432u},
{(void CYFAR *)(CYDEV_UCFG_B1_P2_U0_BASE), 2048u},
{(void CYFAR *)(CYDEV_UCFG_DSI0_BASE), 2560u},
{(void CYFAR *)(CYDEV_UCFG_DSI12_BASE), 512u},
{(void CYFAR *)(CYREG_BCTL0_MDCLK_EN), 32u},
@ -358,7 +379,7 @@ void cyfitter_cfg(void)
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
{(void CYFAR *)(CYDEV_UCFG_B1_P3_U1_BASE), BS_UDB_1_1_0_CONFIG_VAL, 128u},
{(void CYFAR *)(CYDEV_UCFG_B0_P3_U0_BASE), BS_UDB_1_2_1_CONFIG_VAL, 128u},
};
uint8 CYDATA i;
@ -402,7 +423,7 @@ void cyfitter_cfg(void)
CYCONFIGCPY((void CYFAR *)(CYREG_PRT6_DM0), (const void CYFAR *)(BS_IOPINS0_6_VAL), 8u);
/* Switch Boost to the precision bandgap reference from its internal reference */
CY_SET_REG8((void CYXDATA *)CYDEV_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYDEV_BOOST_CR2) | 0x08u));
CY_SET_REG8((void CYXDATA *)CYREG_BOOST_CR2, (CY_GET_REG8((void CYXDATA *)CYREG_BOOST_CR2) | 0x08u));
/* Perform basic analog initialization to defaults */
AnalogSetDefault();

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* FILENAME: cyfitter_cfg.h
* PSoC Creator 2.2 Component Pack 6
* PSoC Creator 3.0
*
* Description:
* This file is automatically generated by PSoC Creator.

678
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
View File

@ -3,25 +3,15 @@
.include "cydevicegnu.inc"
.include "cydevicegnu_trm.inc"
/* SDCard_RxInternalInterrupt */
.set SDCard_RxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SDCard_RxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SDCard_RxInternalInterrupt__INTC_MASK, 0x01
.set SDCard_RxInternalInterrupt__INTC_NUMBER, 0
.set SDCard_RxInternalInterrupt__INTC_PRIOR_NUM, 7
.set SDCard_RxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
.set SDCard_RxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SDCard_RxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_TxInternalInterrupt */
.set SDCard_TxInternalInterrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SDCard_TxInternalInterrupt__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SDCard_TxInternalInterrupt__INTC_MASK, 0x02
.set SDCard_TxInternalInterrupt__INTC_NUMBER, 1
.set SDCard_TxInternalInterrupt__INTC_PRIOR_NUM, 7
.set SDCard_TxInternalInterrupt__INTC_PRIOR_REG, CYREG_NVIC_PRI_1
.set SDCard_TxInternalInterrupt__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SDCard_TxInternalInterrupt__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_ATN_ISR */
.set SCSI_ATN_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_ATN_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SCSI_ATN_ISR__INTC_MASK, 0x01
.set SCSI_ATN_ISR__INTC_NUMBER, 0
.set SCSI_ATN_ISR__INTC_PRIOR_NUM, 7
.set SCSI_ATN_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_0
.set SCSI_ATN_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_ATN_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__MASK, 0x01
@ -62,6 +52,38 @@
.set SCSI_Out_DBx__BIT_MASK, CYREG_PRT0_BIT_MASK
.set SCSI_Out_DBx__BYP, CYREG_PRT0_BYP
.set SCSI_Out_DBx__CTL, CYREG_PRT0_CTL
.set SCSI_Out_DBx__DB0__MASK, 0x01
.set SCSI_Out_DBx__DB0__PC, CYREG_PRT0_PC0
.set SCSI_Out_DBx__DB0__PORT, 0
.set SCSI_Out_DBx__DB0__SHIFT, 0
.set SCSI_Out_DBx__DB1__MASK, 0x02
.set SCSI_Out_DBx__DB1__PC, CYREG_PRT0_PC1
.set SCSI_Out_DBx__DB1__PORT, 0
.set SCSI_Out_DBx__DB1__SHIFT, 1
.set SCSI_Out_DBx__DB2__MASK, 0x04
.set SCSI_Out_DBx__DB2__PC, CYREG_PRT0_PC2
.set SCSI_Out_DBx__DB2__PORT, 0
.set SCSI_Out_DBx__DB2__SHIFT, 2
.set SCSI_Out_DBx__DB3__MASK, 0x08
.set SCSI_Out_DBx__DB3__PC, CYREG_PRT0_PC3
.set SCSI_Out_DBx__DB3__PORT, 0
.set SCSI_Out_DBx__DB3__SHIFT, 3
.set SCSI_Out_DBx__DB4__MASK, 0x10
.set SCSI_Out_DBx__DB4__PC, CYREG_PRT0_PC4
.set SCSI_Out_DBx__DB4__PORT, 0
.set SCSI_Out_DBx__DB4__SHIFT, 4
.set SCSI_Out_DBx__DB5__MASK, 0x20
.set SCSI_Out_DBx__DB5__PC, CYREG_PRT0_PC5
.set SCSI_Out_DBx__DB5__PORT, 0
.set SCSI_Out_DBx__DB5__SHIFT, 5
.set SCSI_Out_DBx__DB6__MASK, 0x40
.set SCSI_Out_DBx__DB6__PC, CYREG_PRT0_PC6
.set SCSI_Out_DBx__DB6__PORT, 0
.set SCSI_Out_DBx__DB6__SHIFT, 6
.set SCSI_Out_DBx__DB7__MASK, 0x80
.set SCSI_Out_DBx__DB7__PC, CYREG_PRT0_PC7
.set SCSI_Out_DBx__DB7__PORT, 0
.set SCSI_Out_DBx__DB7__SHIFT, 7
.set SCSI_Out_DBx__DM0, CYREG_PRT0_DM0
.set SCSI_Out_DBx__DM1, CYREG_PRT0_DM1
.set SCSI_Out_DBx__DM2, CYREG_PRT0_DM2
@ -80,70 +102,48 @@
.set SCSI_Out_DBx__PRTDSI__OUT_SEL1, CYREG_PRT0_OUT_SEL1
.set SCSI_Out_DBx__PRTDSI__SYNC_OUT, CYREG_PRT0_SYNC_OUT
.set SCSI_Out_DBx__PS, CYREG_PRT0_PS
.set SCSI_Out_DBx__SCSI_Out_DB0__MASK, 0x01
.set SCSI_Out_DBx__SCSI_Out_DB0__PC, CYREG_PRT0_PC0
.set SCSI_Out_DBx__SCSI_Out_DB0__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB0__SHIFT, 0
.set SCSI_Out_DBx__SCSI_Out_DB1__MASK, 0x02
.set SCSI_Out_DBx__SCSI_Out_DB1__PC, CYREG_PRT0_PC1
.set SCSI_Out_DBx__SCSI_Out_DB1__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB1__SHIFT, 1
.set SCSI_Out_DBx__SCSI_Out_DB2__MASK, 0x04
.set SCSI_Out_DBx__SCSI_Out_DB2__PC, CYREG_PRT0_PC2
.set SCSI_Out_DBx__SCSI_Out_DB2__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB2__SHIFT, 2
.set SCSI_Out_DBx__SCSI_Out_DB3__MASK, 0x08
.set SCSI_Out_DBx__SCSI_Out_DB3__PC, CYREG_PRT0_PC3
.set SCSI_Out_DBx__SCSI_Out_DB3__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB3__SHIFT, 3
.set SCSI_Out_DBx__SCSI_Out_DB4__MASK, 0x10
.set SCSI_Out_DBx__SCSI_Out_DB4__PC, CYREG_PRT0_PC4
.set SCSI_Out_DBx__SCSI_Out_DB4__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB4__SHIFT, 4
.set SCSI_Out_DBx__SCSI_Out_DB5__MASK, 0x20
.set SCSI_Out_DBx__SCSI_Out_DB5__PC, CYREG_PRT0_PC5
.set SCSI_Out_DBx__SCSI_Out_DB5__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB5__SHIFT, 5
.set SCSI_Out_DBx__SCSI_Out_DB6__MASK, 0x40
.set SCSI_Out_DBx__SCSI_Out_DB6__PC, CYREG_PRT0_PC6
.set SCSI_Out_DBx__SCSI_Out_DB6__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB6__SHIFT, 6
.set SCSI_Out_DBx__SCSI_Out_DB7__MASK, 0x80
.set SCSI_Out_DBx__SCSI_Out_DB7__PC, CYREG_PRT0_PC7
.set SCSI_Out_DBx__SCSI_Out_DB7__PORT, 0
.set SCSI_Out_DBx__SCSI_Out_DB7__SHIFT, 7
.set SCSI_Out_DBx__SHIFT, 0
.set SCSI_Out_DBx__SLW, CYREG_PRT0_SLW
/* SCSI_RST_ISR */
.set SCSI_RST_ISR__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
.set SCSI_RST_ISR__INTC_CLR_PD_REG, CYREG_NVIC_CLRPEND0
.set SCSI_RST_ISR__INTC_MASK, 0x400
.set SCSI_RST_ISR__INTC_NUMBER, 10
.set SCSI_RST_ISR__INTC_PRIOR_NUM, 7
.set SCSI_RST_ISR__INTC_PRIOR_REG, CYREG_NVIC_PRI_10
.set SCSI_RST_ISR__INTC_SET_EN_REG, CYREG_NVIC_SETENA0
.set SCSI_RST_ISR__INTC_SET_PD_REG, CYREG_NVIC_SETPEND0
/* SDCard_BSPIM */
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB06_07_ST
.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB06_ST
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB06_CTL
.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB06_CTL
.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB06_MSK
.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@ -151,13 +151,13 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB06_MSK
.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB06_ST
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
@ -167,28 +167,28 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB07_08_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB07_08_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB07_08_D0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B1_UDB07_08_D1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B1_UDB07_08_F0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B1_UDB07_08_F1
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B1_UDB07_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B1_UDB07_A0
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B1_UDB07_A1
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B1_UDB07_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B1_UDB07_D0
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B1_UDB07_D1
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB07_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB07_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB07_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB05_MSK
.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB05_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B0_UDB06_07_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B0_UDB06_07_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B0_UDB06_07_D0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG, CYREG_B0_UDB06_07_D1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG, CYREG_B0_UDB06_07_F0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG, CYREG_B0_UDB06_07_F1
.set SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG, CYREG_B0_UDB06_A0_A1
.set SDCard_BSPIM_sR8_Dp_u0__A0_REG, CYREG_B0_UDB06_A0
.set SDCard_BSPIM_sR8_Dp_u0__A1_REG, CYREG_B0_UDB06_A1
.set SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG, CYREG_B0_UDB06_D0_D1
.set SDCard_BSPIM_sR8_Dp_u0__D0_REG, CYREG_B0_UDB06_D0
.set SDCard_BSPIM_sR8_Dp_u0__D1_REG, CYREG_B0_UDB06_D1
.set SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B0_UDB06_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B0_UDB06_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B0_UDB06_F1
.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
/* SCSI_In_DBx */
.set SCSI_In_DBx__0__MASK, 0x01
@ -229,6 +229,38 @@
.set SCSI_In_DBx__BIT_MASK, CYREG_PRT2_BIT_MASK
.set SCSI_In_DBx__BYP, CYREG_PRT2_BYP
.set SCSI_In_DBx__CTL, CYREG_PRT2_CTL
.set SCSI_In_DBx__DB0__MASK, 0x01
.set SCSI_In_DBx__DB0__PC, CYREG_PRT2_PC0
.set SCSI_In_DBx__DB0__PORT, 2
.set SCSI_In_DBx__DB0__SHIFT, 0
.set SCSI_In_DBx__DB1__MASK, 0x02
.set SCSI_In_DBx__DB1__PC, CYREG_PRT2_PC1
.set SCSI_In_DBx__DB1__PORT, 2
.set SCSI_In_DBx__DB1__SHIFT, 1
.set SCSI_In_DBx__DB2__MASK, 0x04
.set SCSI_In_DBx__DB2__PC, CYREG_PRT2_PC2
.set SCSI_In_DBx__DB2__PORT, 2
.set SCSI_In_DBx__DB2__SHIFT, 2
.set SCSI_In_DBx__DB3__MASK, 0x08
.set SCSI_In_DBx__DB3__PC, CYREG_PRT2_PC3
.set SCSI_In_DBx__DB3__PORT, 2
.set SCSI_In_DBx__DB3__SHIFT, 3
.set SCSI_In_DBx__DB4__MASK, 0x10
.set SCSI_In_DBx__DB4__PC, CYREG_PRT2_PC4
.set SCSI_In_DBx__DB4__PORT, 2
.set SCSI_In_DBx__DB4__SHIFT, 4
.set SCSI_In_DBx__DB5__MASK, 0x20
.set SCSI_In_DBx__DB5__PC, CYREG_PRT2_PC5
.set SCSI_In_DBx__DB5__PORT, 2
.set SCSI_In_DBx__DB5__SHIFT, 5
.set SCSI_In_DBx__DB6__MASK, 0x40
.set SCSI_In_DBx__DB6__PC, CYREG_PRT2_PC6
.set SCSI_In_DBx__DB6__PORT, 2
.set SCSI_In_DBx__DB6__SHIFT, 6
.set SCSI_In_DBx__DB7__MASK, 0x80
.set SCSI_In_DBx__DB7__PC, CYREG_PRT2_PC7
.set SCSI_In_DBx__DB7__PORT, 2
.set SCSI_In_DBx__DB7__SHIFT, 7
.set SCSI_In_DBx__DM0, CYREG_PRT2_DM0
.set SCSI_In_DBx__DM1, CYREG_PRT2_DM1
.set SCSI_In_DBx__DM2, CYREG_PRT2_DM2
@ -247,38 +279,6 @@
.set SCSI_In_DBx__PRTDSI__OUT_SEL1, CYREG_PRT2_OUT_SEL1
.set SCSI_In_DBx__PRTDSI__SYNC_OUT, CYREG_PRT2_SYNC_OUT
.set SCSI_In_DBx__PS, CYREG_PRT2_PS
.set SCSI_In_DBx__SCSI_Out_DB0__MASK, 0x01
.set SCSI_In_DBx__SCSI_Out_DB0__PC, CYREG_PRT2_PC0
.set SCSI_In_DBx__SCSI_Out_DB0__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB0__SHIFT, 0
.set SCSI_In_DBx__SCSI_Out_DB1__MASK, 0x02
.set SCSI_In_DBx__SCSI_Out_DB1__PC, CYREG_PRT2_PC1
.set SCSI_In_DBx__SCSI_Out_DB1__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB1__SHIFT, 1
.set SCSI_In_DBx__SCSI_Out_DB2__MASK, 0x04
.set SCSI_In_DBx__SCSI_Out_DB2__PC, CYREG_PRT2_PC2
.set SCSI_In_DBx__SCSI_Out_DB2__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB2__SHIFT, 2
.set SCSI_In_DBx__SCSI_Out_DB3__MASK, 0x08
.set SCSI_In_DBx__SCSI_Out_DB3__PC, CYREG_PRT2_PC3
.set SCSI_In_DBx__SCSI_Out_DB3__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB3__SHIFT, 3
.set SCSI_In_DBx__SCSI_Out_DB4__MASK, 0x10
.set SCSI_In_DBx__SCSI_Out_DB4__PC, CYREG_PRT2_PC4
.set SCSI_In_DBx__SCSI_Out_DB4__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB4__SHIFT, 4
.set SCSI_In_DBx__SCSI_Out_DB5__MASK, 0x20
.set SCSI_In_DBx__SCSI_Out_DB5__PC, CYREG_PRT2_PC5
.set SCSI_In_DBx__SCSI_Out_DB5__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB5__SHIFT, 5
.set SCSI_In_DBx__SCSI_Out_DB6__MASK, 0x40
.set SCSI_In_DBx__SCSI_Out_DB6__PC, CYREG_PRT2_PC6
.set SCSI_In_DBx__SCSI_Out_DB6__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB6__SHIFT, 6
.set SCSI_In_DBx__SCSI_Out_DB7__MASK, 0x80
.set SCSI_In_DBx__SCSI_Out_DB7__PC, CYREG_PRT2_PC7
.set SCSI_In_DBx__SCSI_Out_DB7__PORT, 2
.set SCSI_In_DBx__SCSI_Out_DB7__SHIFT, 7
.set SCSI_In_DBx__SHIFT, 0
.set SCSI_In_DBx__SLW, CYREG_PRT2_SLW
@ -307,24 +307,24 @@
/* SD_Clk_Ctl */
.set SD_Clk_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SD_Clk_Ctl_Sync_ctrl_reg__0__POS, 0
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_07_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB06_07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB06_07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB06_07_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB06_07_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB06_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB06_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB06_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB06_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB07_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK, 0x01
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB06_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB06_MSK_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
.set SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB07_MSK
.set SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
/* PARITY_EN */
.set PARITY_EN__0__MASK, 0x10
@ -358,6 +358,41 @@
.set PARITY_EN__SHIFT, 4
.set PARITY_EN__SLW, CYREG_PRT5_SLW
/* SCSI_ATN */
.set SCSI_ATN__0__MASK, 0x20
.set SCSI_ATN__0__PC, CYREG_PRT12_PC5
.set SCSI_ATN__0__PORT, 12
.set SCSI_ATN__0__SHIFT, 5
.set SCSI_ATN__AG, CYREG_PRT12_AG
.set SCSI_ATN__BIE, CYREG_PRT12_BIE
.set SCSI_ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
.set SCSI_ATN__BYP, CYREG_PRT12_BYP
.set SCSI_ATN__DM0, CYREG_PRT12_DM0
.set SCSI_ATN__DM1, CYREG_PRT12_DM1
.set SCSI_ATN__DM2, CYREG_PRT12_DM2
.set SCSI_ATN__DR, CYREG_PRT12_DR
.set SCSI_ATN__INP_DIS, CYREG_PRT12_INP_DIS
.set SCSI_ATN__INT__MASK, 0x20
.set SCSI_ATN__INT__PC, CYREG_PRT12_PC5
.set SCSI_ATN__INT__PORT, 12
.set SCSI_ATN__INT__SHIFT, 5
.set SCSI_ATN__MASK, 0x20
.set SCSI_ATN__PORT, 12
.set SCSI_ATN__PRT, CYREG_PRT12_PRT
.set SCSI_ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
.set SCSI_ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
.set SCSI_ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
.set SCSI_ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
.set SCSI_ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
.set SCSI_ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
.set SCSI_ATN__PS, CYREG_PRT12_PS
.set SCSI_ATN__SHIFT, 5
.set SCSI_ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
.set SCSI_ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
.set SCSI_ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set SCSI_ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set SCSI_ATN__SLW, CYREG_PRT12_SLW
/* SCSI_Out */
.set SCSI_Out__0__AG, CYREG_PRT4_AG
.set SCSI_Out__0__AMUX, CYREG_PRT4_AMUX
@ -900,6 +935,44 @@
.set SCSI_Out__SEL__SHIFT, 0
.set SCSI_Out__SEL__SLW, CYREG_PRT6_SLW
/* SCSI_RST */
.set SCSI_RST__0__MASK, 0x40
.set SCSI_RST__0__PC, CYREG_PRT6_PC6
.set SCSI_RST__0__PORT, 6
.set SCSI_RST__0__SHIFT, 6
.set SCSI_RST__AG, CYREG_PRT6_AG
.set SCSI_RST__AMUX, CYREG_PRT6_AMUX
.set SCSI_RST__BIE, CYREG_PRT6_BIE
.set SCSI_RST__BIT_MASK, CYREG_PRT6_BIT_MASK
.set SCSI_RST__BYP, CYREG_PRT6_BYP
.set SCSI_RST__CTL, CYREG_PRT6_CTL
.set SCSI_RST__DM0, CYREG_PRT6_DM0
.set SCSI_RST__DM1, CYREG_PRT6_DM1
.set SCSI_RST__DM2, CYREG_PRT6_DM2
.set SCSI_RST__DR, CYREG_PRT6_DR
.set SCSI_RST__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_RST__INTSTAT, CYREG_PICU6_INTSTAT
.set SCSI_RST__INT__MASK, 0x40
.set SCSI_RST__INT__PC, CYREG_PRT6_PC6
.set SCSI_RST__INT__PORT, 6
.set SCSI_RST__INT__SHIFT, 6
.set SCSI_RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_RST__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_RST__MASK, 0x40
.set SCSI_RST__PORT, 6
.set SCSI_RST__PRT, CYREG_PRT6_PRT
.set SCSI_RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set SCSI_RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set SCSI_RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set SCSI_RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set SCSI_RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set SCSI_RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_RST__PS, CYREG_PRT6_PS
.set SCSI_RST__SHIFT, 6
.set SCSI_RST__SLW, CYREG_PRT6_SLW
.set SCSI_RST__SNAP, CYREG_PICU6_SNAP
/* SCSI_ID */
.set SCSI_ID__0__MASK, 0x80
.set SCSI_ID__0__PC, CYREG_PRT5_PC7
@ -965,32 +1038,33 @@
.set SCSI_In__0__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set SCSI_In__0__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set SCSI_In__0__SLW, CYREG_PRT12_SLW
.set SCSI_In__1__AG, CYREG_PRT12_AG
.set SCSI_In__1__BIE, CYREG_PRT12_BIE
.set SCSI_In__1__BIT_MASK, CYREG_PRT12_BIT_MASK
.set SCSI_In__1__BYP, CYREG_PRT12_BYP
.set SCSI_In__1__DM0, CYREG_PRT12_DM0
.set SCSI_In__1__DM1, CYREG_PRT12_DM1
.set SCSI_In__1__DM2, CYREG_PRT12_DM2
.set SCSI_In__1__DR, CYREG_PRT12_DR
.set SCSI_In__1__INP_DIS, CYREG_PRT12_INP_DIS
.set SCSI_In__1__MASK, 0x20
.set SCSI_In__1__PC, CYREG_PRT12_PC5
.set SCSI_In__1__PORT, 12
.set SCSI_In__1__PRT, CYREG_PRT12_PRT
.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
.set SCSI_In__1__PS, CYREG_PRT12_PS
.set SCSI_In__1__SHIFT, 5
.set SCSI_In__1__SIO_CFG, CYREG_PRT12_SIO_CFG
.set SCSI_In__1__SIO_DIFF, CYREG_PRT12_SIO_DIFF
.set SCSI_In__1__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set SCSI_In__1__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set SCSI_In__1__SLW, CYREG_PRT12_SLW
.set SCSI_In__1__AG, CYREG_PRT6_AG
.set SCSI_In__1__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__1__BIE, CYREG_PRT6_BIE
.set SCSI_In__1__BIT_MASK, CYREG_PRT6_BIT_MASK
.set SCSI_In__1__BYP, CYREG_PRT6_BYP
.set SCSI_In__1__CTL, CYREG_PRT6_CTL
.set SCSI_In__1__DM0, CYREG_PRT6_DM0
.set SCSI_In__1__DM1, CYREG_PRT6_DM1
.set SCSI_In__1__DM2, CYREG_PRT6_DM2
.set SCSI_In__1__DR, CYREG_PRT6_DR
.set SCSI_In__1__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__1__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__1__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__1__MASK, 0x10
.set SCSI_In__1__PC, CYREG_PRT6_PC4
.set SCSI_In__1__PORT, 6
.set SCSI_In__1__PRT, CYREG_PRT6_PRT
.set SCSI_In__1__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set SCSI_In__1__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set SCSI_In__1__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set SCSI_In__1__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set SCSI_In__1__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set SCSI_In__1__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__1__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__1__PS, CYREG_PRT6_PS
.set SCSI_In__1__SHIFT, 4
.set SCSI_In__1__SLW, CYREG_PRT6_SLW
.set SCSI_In__2__AG, CYREG_PRT6_AG
.set SCSI_In__2__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__2__BIE, CYREG_PRT6_BIE
@ -1004,8 +1078,8 @@
.set SCSI_In__2__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__2__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__2__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__2__MASK, 0x10
.set SCSI_In__2__PC, CYREG_PRT6_PC4
.set SCSI_In__2__MASK, 0x20
.set SCSI_In__2__PC, CYREG_PRT6_PC5
.set SCSI_In__2__PORT, 6
.set SCSI_In__2__PRT, CYREG_PRT6_PRT
.set SCSI_In__2__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
@ -1016,7 +1090,7 @@
.set SCSI_In__2__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__2__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__2__PS, CYREG_PRT6_PS
.set SCSI_In__2__SHIFT, 4
.set SCSI_In__2__SHIFT, 5
.set SCSI_In__2__SLW, CYREG_PRT6_SLW
.set SCSI_In__3__AG, CYREG_PRT6_AG
.set SCSI_In__3__AMUX, CYREG_PRT6_AMUX
@ -1031,8 +1105,8 @@
.set SCSI_In__3__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__3__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__3__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__3__MASK, 0x20
.set SCSI_In__3__PC, CYREG_PRT6_PC5
.set SCSI_In__3__MASK, 0x80
.set SCSI_In__3__PC, CYREG_PRT6_PC7
.set SCSI_In__3__PORT, 6
.set SCSI_In__3__PRT, CYREG_PRT6_PRT
.set SCSI_In__3__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
@ -1043,62 +1117,62 @@
.set SCSI_In__3__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__3__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__3__PS, CYREG_PRT6_PS
.set SCSI_In__3__SHIFT, 5
.set SCSI_In__3__SHIFT, 7
.set SCSI_In__3__SLW, CYREG_PRT6_SLW
.set SCSI_In__4__AG, CYREG_PRT6_AG
.set SCSI_In__4__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__4__BIE, CYREG_PRT6_BIE
.set SCSI_In__4__BIT_MASK, CYREG_PRT6_BIT_MASK
.set SCSI_In__4__BYP, CYREG_PRT6_BYP
.set SCSI_In__4__CTL, CYREG_PRT6_CTL
.set SCSI_In__4__DM0, CYREG_PRT6_DM0
.set SCSI_In__4__DM1, CYREG_PRT6_DM1
.set SCSI_In__4__DM2, CYREG_PRT6_DM2
.set SCSI_In__4__DR, CYREG_PRT6_DR
.set SCSI_In__4__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__4__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__4__MASK, 0x40
.set SCSI_In__4__PC, CYREG_PRT6_PC6
.set SCSI_In__4__PORT, 6
.set SCSI_In__4__PRT, CYREG_PRT6_PRT
.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__4__PS, CYREG_PRT6_PS
.set SCSI_In__4__SHIFT, 6
.set SCSI_In__4__SLW, CYREG_PRT6_SLW
.set SCSI_In__5__AG, CYREG_PRT6_AG
.set SCSI_In__5__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__5__BIE, CYREG_PRT6_BIE
.set SCSI_In__5__BIT_MASK, CYREG_PRT6_BIT_MASK
.set SCSI_In__5__BYP, CYREG_PRT6_BYP
.set SCSI_In__5__CTL, CYREG_PRT6_CTL
.set SCSI_In__5__DM0, CYREG_PRT6_DM0
.set SCSI_In__5__DM1, CYREG_PRT6_DM1
.set SCSI_In__5__DM2, CYREG_PRT6_DM2
.set SCSI_In__5__DR, CYREG_PRT6_DR
.set SCSI_In__5__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__5__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__5__MASK, 0x80
.set SCSI_In__5__PC, CYREG_PRT6_PC7
.set SCSI_In__5__PORT, 6
.set SCSI_In__5__PRT, CYREG_PRT6_PRT
.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__5__PS, CYREG_PRT6_PS
.set SCSI_In__5__SHIFT, 7
.set SCSI_In__5__SLW, CYREG_PRT6_SLW
.set SCSI_In__4__AG, CYREG_PRT5_AG
.set SCSI_In__4__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__4__BIE, CYREG_PRT5_BIE
.set SCSI_In__4__BIT_MASK, CYREG_PRT5_BIT_MASK
.set SCSI_In__4__BYP, CYREG_PRT5_BYP
.set SCSI_In__4__CTL, CYREG_PRT5_CTL
.set SCSI_In__4__DM0, CYREG_PRT5_DM0
.set SCSI_In__4__DM1, CYREG_PRT5_DM1
.set SCSI_In__4__DM2, CYREG_PRT5_DM2
.set SCSI_In__4__DR, CYREG_PRT5_DR
.set SCSI_In__4__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__4__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__4__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__4__MASK, 0x01
.set SCSI_In__4__PC, CYREG_PRT5_PC0
.set SCSI_In__4__PORT, 5
.set SCSI_In__4__PRT, CYREG_PRT5_PRT
.set SCSI_In__4__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
.set SCSI_In__4__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
.set SCSI_In__4__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
.set SCSI_In__4__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
.set SCSI_In__4__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
.set SCSI_In__4__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__4__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__4__PS, CYREG_PRT5_PS
.set SCSI_In__4__SHIFT, 0
.set SCSI_In__4__SLW, CYREG_PRT5_SLW
.set SCSI_In__5__AG, CYREG_PRT5_AG
.set SCSI_In__5__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__5__BIE, CYREG_PRT5_BIE
.set SCSI_In__5__BIT_MASK, CYREG_PRT5_BIT_MASK
.set SCSI_In__5__BYP, CYREG_PRT5_BYP
.set SCSI_In__5__CTL, CYREG_PRT5_CTL
.set SCSI_In__5__DM0, CYREG_PRT5_DM0
.set SCSI_In__5__DM1, CYREG_PRT5_DM1
.set SCSI_In__5__DM2, CYREG_PRT5_DM2
.set SCSI_In__5__DR, CYREG_PRT5_DR
.set SCSI_In__5__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__5__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__5__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__5__MASK, 0x02
.set SCSI_In__5__PC, CYREG_PRT5_PC1
.set SCSI_In__5__PORT, 5
.set SCSI_In__5__PRT, CYREG_PRT5_PRT
.set SCSI_In__5__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
.set SCSI_In__5__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
.set SCSI_In__5__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
.set SCSI_In__5__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
.set SCSI_In__5__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
.set SCSI_In__5__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__5__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__5__PS, CYREG_PRT5_PS
.set SCSI_In__5__SHIFT, 1
.set SCSI_In__5__SLW, CYREG_PRT5_SLW
.set SCSI_In__6__AG, CYREG_PRT5_AG
.set SCSI_In__6__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__6__BIE, CYREG_PRT5_BIE
@ -1112,8 +1186,8 @@
.set SCSI_In__6__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__6__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__6__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__6__MASK, 0x01
.set SCSI_In__6__PC, CYREG_PRT5_PC0
.set SCSI_In__6__MASK, 0x04
.set SCSI_In__6__PC, CYREG_PRT5_PC2
.set SCSI_In__6__PORT, 5
.set SCSI_In__6__PRT, CYREG_PRT5_PRT
.set SCSI_In__6__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
@ -1124,7 +1198,7 @@
.set SCSI_In__6__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__6__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__6__PS, CYREG_PRT5_PS
.set SCSI_In__6__SHIFT, 0
.set SCSI_In__6__SHIFT, 2
.set SCSI_In__6__SLW, CYREG_PRT5_SLW
.set SCSI_In__7__AG, CYREG_PRT5_AG
.set SCSI_In__7__AMUX, CYREG_PRT5_AMUX
@ -1139,8 +1213,8 @@
.set SCSI_In__7__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__7__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__7__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__7__MASK, 0x02
.set SCSI_In__7__PC, CYREG_PRT5_PC1
.set SCSI_In__7__MASK, 0x08
.set SCSI_In__7__PC, CYREG_PRT5_PC3
.set SCSI_In__7__PORT, 5
.set SCSI_In__7__PRT, CYREG_PRT5_PRT
.set SCSI_In__7__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
@ -1151,62 +1225,8 @@
.set SCSI_In__7__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__7__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__7__PS, CYREG_PRT5_PS
.set SCSI_In__7__SHIFT, 1
.set SCSI_In__7__SHIFT, 3
.set SCSI_In__7__SLW, CYREG_PRT5_SLW
.set SCSI_In__8__AG, CYREG_PRT5_AG
.set SCSI_In__8__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__8__BIE, CYREG_PRT5_BIE
.set SCSI_In__8__BIT_MASK, CYREG_PRT5_BIT_MASK
.set SCSI_In__8__BYP, CYREG_PRT5_BYP
.set SCSI_In__8__CTL, CYREG_PRT5_CTL
.set SCSI_In__8__DM0, CYREG_PRT5_DM0
.set SCSI_In__8__DM1, CYREG_PRT5_DM1
.set SCSI_In__8__DM2, CYREG_PRT5_DM2
.set SCSI_In__8__DR, CYREG_PRT5_DR
.set SCSI_In__8__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__8__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__8__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__8__MASK, 0x04
.set SCSI_In__8__PC, CYREG_PRT5_PC2
.set SCSI_In__8__PORT, 5
.set SCSI_In__8__PRT, CYREG_PRT5_PRT
.set SCSI_In__8__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
.set SCSI_In__8__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
.set SCSI_In__8__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
.set SCSI_In__8__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
.set SCSI_In__8__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
.set SCSI_In__8__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__8__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__8__PS, CYREG_PRT5_PS
.set SCSI_In__8__SHIFT, 2
.set SCSI_In__8__SLW, CYREG_PRT5_SLW
.set SCSI_In__9__AG, CYREG_PRT5_AG
.set SCSI_In__9__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__9__BIE, CYREG_PRT5_BIE
.set SCSI_In__9__BIT_MASK, CYREG_PRT5_BIT_MASK
.set SCSI_In__9__BYP, CYREG_PRT5_BYP
.set SCSI_In__9__CTL, CYREG_PRT5_CTL
.set SCSI_In__9__DM0, CYREG_PRT5_DM0
.set SCSI_In__9__DM1, CYREG_PRT5_DM1
.set SCSI_In__9__DM2, CYREG_PRT5_DM2
.set SCSI_In__9__DR, CYREG_PRT5_DR
.set SCSI_In__9__INP_DIS, CYREG_PRT5_INP_DIS
.set SCSI_In__9__LCD_COM_SEG, CYREG_PRT5_LCD_COM_SEG
.set SCSI_In__9__LCD_EN, CYREG_PRT5_LCD_EN
.set SCSI_In__9__MASK, 0x08
.set SCSI_In__9__PC, CYREG_PRT5_PC3
.set SCSI_In__9__PORT, 5
.set SCSI_In__9__PRT, CYREG_PRT5_PRT
.set SCSI_In__9__PRTDSI__CAPS_SEL, CYREG_PRT5_CAPS_SEL
.set SCSI_In__9__PRTDSI__DBL_SYNC_IN, CYREG_PRT5_DBL_SYNC_IN
.set SCSI_In__9__PRTDSI__OE_SEL0, CYREG_PRT5_OE_SEL0
.set SCSI_In__9__PRTDSI__OE_SEL1, CYREG_PRT5_OE_SEL1
.set SCSI_In__9__PRTDSI__OUT_SEL0, CYREG_PRT5_OUT_SEL0
.set SCSI_In__9__PRTDSI__OUT_SEL1, CYREG_PRT5_OUT_SEL1
.set SCSI_In__9__PRTDSI__SYNC_OUT, CYREG_PRT5_SYNC_OUT
.set SCSI_In__9__PS, CYREG_PRT5_PS
.set SCSI_In__9__SHIFT, 3
.set SCSI_In__9__SLW, CYREG_PRT5_SLW
.set SCSI_In__ACK__AG, CYREG_PRT6_AG
.set SCSI_In__ACK__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__ACK__BIE, CYREG_PRT6_BIE
@ -1234,32 +1254,6 @@
.set SCSI_In__ACK__PS, CYREG_PRT6_PS
.set SCSI_In__ACK__SHIFT, 5
.set SCSI_In__ACK__SLW, CYREG_PRT6_SLW
.set SCSI_In__ATN__AG, CYREG_PRT12_AG
.set SCSI_In__ATN__BIE, CYREG_PRT12_BIE
.set SCSI_In__ATN__BIT_MASK, CYREG_PRT12_BIT_MASK
.set SCSI_In__ATN__BYP, CYREG_PRT12_BYP
.set SCSI_In__ATN__DM0, CYREG_PRT12_DM0
.set SCSI_In__ATN__DM1, CYREG_PRT12_DM1
.set SCSI_In__ATN__DM2, CYREG_PRT12_DM2
.set SCSI_In__ATN__DR, CYREG_PRT12_DR
.set SCSI_In__ATN__INP_DIS, CYREG_PRT12_INP_DIS
.set SCSI_In__ATN__MASK, 0x20
.set SCSI_In__ATN__PC, CYREG_PRT12_PC5
.set SCSI_In__ATN__PORT, 12
.set SCSI_In__ATN__PRT, CYREG_PRT12_PRT
.set SCSI_In__ATN__PRTDSI__DBL_SYNC_IN, CYREG_PRT12_DBL_SYNC_IN
.set SCSI_In__ATN__PRTDSI__OE_SEL0, CYREG_PRT12_OE_SEL0
.set SCSI_In__ATN__PRTDSI__OE_SEL1, CYREG_PRT12_OE_SEL1
.set SCSI_In__ATN__PRTDSI__OUT_SEL0, CYREG_PRT12_OUT_SEL0
.set SCSI_In__ATN__PRTDSI__OUT_SEL1, CYREG_PRT12_OUT_SEL1
.set SCSI_In__ATN__PRTDSI__SYNC_OUT, CYREG_PRT12_SYNC_OUT
.set SCSI_In__ATN__PS, CYREG_PRT12_PS
.set SCSI_In__ATN__SHIFT, 5
.set SCSI_In__ATN__SIO_CFG, CYREG_PRT12_SIO_CFG
.set SCSI_In__ATN__SIO_DIFF, CYREG_PRT12_SIO_DIFF
.set SCSI_In__ATN__SIO_HYST_EN, CYREG_PRT12_SIO_HYST_EN
.set SCSI_In__ATN__SIO_REG_HIFREQ, CYREG_PRT12_SIO_REG_HIFREQ
.set SCSI_In__ATN__SLW, CYREG_PRT12_SLW
.set SCSI_In__BSY__AG, CYREG_PRT6_AG
.set SCSI_In__BSY__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__BSY__BIE, CYREG_PRT6_BIE
@ -1421,33 +1415,6 @@
.set SCSI_In__REQ__PS, CYREG_PRT5_PS
.set SCSI_In__REQ__SHIFT, 2
.set SCSI_In__REQ__SLW, CYREG_PRT5_SLW
.set SCSI_In__RST__AG, CYREG_PRT6_AG
.set SCSI_In__RST__AMUX, CYREG_PRT6_AMUX
.set SCSI_In__RST__BIE, CYREG_PRT6_BIE
.set SCSI_In__RST__BIT_MASK, CYREG_PRT6_BIT_MASK
.set SCSI_In__RST__BYP, CYREG_PRT6_BYP
.set SCSI_In__RST__CTL, CYREG_PRT6_CTL
.set SCSI_In__RST__DM0, CYREG_PRT6_DM0
.set SCSI_In__RST__DM1, CYREG_PRT6_DM1
.set SCSI_In__RST__DM2, CYREG_PRT6_DM2
.set SCSI_In__RST__DR, CYREG_PRT6_DR
.set SCSI_In__RST__INP_DIS, CYREG_PRT6_INP_DIS
.set SCSI_In__RST__LCD_COM_SEG, CYREG_PRT6_LCD_COM_SEG
.set SCSI_In__RST__LCD_EN, CYREG_PRT6_LCD_EN
.set SCSI_In__RST__MASK, 0x40
.set SCSI_In__RST__PC, CYREG_PRT6_PC6
.set SCSI_In__RST__PORT, 6
.set SCSI_In__RST__PRT, CYREG_PRT6_PRT
.set SCSI_In__RST__PRTDSI__CAPS_SEL, CYREG_PRT6_CAPS_SEL
.set SCSI_In__RST__PRTDSI__DBL_SYNC_IN, CYREG_PRT6_DBL_SYNC_IN
.set SCSI_In__RST__PRTDSI__OE_SEL0, CYREG_PRT6_OE_SEL0
.set SCSI_In__RST__PRTDSI__OE_SEL1, CYREG_PRT6_OE_SEL1
.set SCSI_In__RST__PRTDSI__OUT_SEL0, CYREG_PRT6_OUT_SEL0
.set SCSI_In__RST__PRTDSI__OUT_SEL1, CYREG_PRT6_OUT_SEL1
.set SCSI_In__RST__PRTDSI__SYNC_OUT, CYREG_PRT6_SYNC_OUT
.set SCSI_In__RST__PS, CYREG_PRT6_PS
.set SCSI_In__RST__SHIFT, 6
.set SCSI_In__RST__SLW, CYREG_PRT6_SLW
.set SCSI_In__SEL__AG, CYREG_PRT5_AG
.set SCSI_In__SEL__AMUX, CYREG_PRT5_AMUX
.set SCSI_In__SEL__BIE, CYREG_PRT5_BIE
@ -1831,7 +1798,6 @@
.set CYDEV_DEBUGGING_DPS_JTAG_5, 0
.set CYDEV_DEBUGGING_DPS_SWD, 2
.set CYDEV_DEBUGGING_ENABLE, 1
.set CYDEV_DEBUGGING_REQXRES, 1
.set CYDEV_DEBUGGING_XRES, 0
.set CYDEV_DEBUG_ENABLE_MASK, 0x20
.set CYDEV_DEBUG_ENABLE_REGISTER, CYREG_MLOGIC_DEBUG
@ -1839,7 +1805,7 @@
.set CYDEV_ECC_ENABLE, 0
.set CYDEV_HEAP_SIZE, 0x1000
.set CYDEV_INSTRUCT_CACHE_ENABLED, 1
.set CYDEV_INTR_RISING, 0x00000003
.set CYDEV_INTR_RISING, 0x00000001
.set CYDEV_PROJ_TYPE, 0
.set CYDEV_PROJ_TYPE_BOOTLOADER, 1
.set CYDEV_PROJ_TYPE_LOADABLE, 2

1834
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc Normal file
View File

File diff suppressed because it is too large Load Diff

678
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
View File

@ -3,25 +3,15 @@ INCLUDED_CYFITTERRV_INC EQU 1
GET cydevicerv.inc
GET cydevicerv_trm.inc
; SDCard_RxInternalInterrupt
SDCard_RxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SDCard_RxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SDCard_RxInternalInterrupt__INTC_MASK EQU 0x01
SDCard_RxInternalInterrupt__INTC_NUMBER EQU 0
SDCard_RxInternalInterrupt__INTC_PRIOR_NUM EQU 7
SDCard_RxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
SDCard_RxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SDCard_RxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_TxInternalInterrupt
SDCard_TxInternalInterrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SDCard_TxInternalInterrupt__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SDCard_TxInternalInterrupt__INTC_MASK EQU 0x02
SDCard_TxInternalInterrupt__INTC_NUMBER EQU 1
SDCard_TxInternalInterrupt__INTC_PRIOR_NUM EQU 7
SDCard_TxInternalInterrupt__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_1
SDCard_TxInternalInterrupt__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SDCard_TxInternalInterrupt__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_ATN_ISR
SCSI_ATN_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_ATN_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_ATN_ISR__INTC_MASK EQU 0x01
SCSI_ATN_ISR__INTC_NUMBER EQU 0
SCSI_ATN_ISR__INTC_PRIOR_NUM EQU 7
SCSI_ATN_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_0
SCSI_ATN_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_ATN_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SCSI_Out_DBx
SCSI_Out_DBx__0__MASK EQU 0x01
@ -62,6 +52,38 @@ SCSI_Out_DBx__BIE EQU CYREG_PRT0_BIE
SCSI_Out_DBx__BIT_MASK EQU CYREG_PRT0_BIT_MASK
SCSI_Out_DBx__BYP EQU CYREG_PRT0_BYP
SCSI_Out_DBx__CTL EQU CYREG_PRT0_CTL
SCSI_Out_DBx__DB0__MASK EQU 0x01
SCSI_Out_DBx__DB0__PC EQU CYREG_PRT0_PC0
SCSI_Out_DBx__DB0__PORT EQU 0
SCSI_Out_DBx__DB0__SHIFT EQU 0
SCSI_Out_DBx__DB1__MASK EQU 0x02
SCSI_Out_DBx__DB1__PC EQU CYREG_PRT0_PC1
SCSI_Out_DBx__DB1__PORT EQU 0
SCSI_Out_DBx__DB1__SHIFT EQU 1
SCSI_Out_DBx__DB2__MASK EQU 0x04
SCSI_Out_DBx__DB2__PC EQU CYREG_PRT0_PC2
SCSI_Out_DBx__DB2__PORT EQU 0
SCSI_Out_DBx__DB2__SHIFT EQU 2
SCSI_Out_DBx__DB3__MASK EQU 0x08
SCSI_Out_DBx__DB3__PC EQU CYREG_PRT0_PC3
SCSI_Out_DBx__DB3__PORT EQU 0
SCSI_Out_DBx__DB3__SHIFT EQU 3
SCSI_Out_DBx__DB4__MASK EQU 0x10
SCSI_Out_DBx__DB4__PC EQU CYREG_PRT0_PC4
SCSI_Out_DBx__DB4__PORT EQU 0
SCSI_Out_DBx__DB4__SHIFT EQU 4
SCSI_Out_DBx__DB5__MASK EQU 0x20
SCSI_Out_DBx__DB5__PC EQU CYREG_PRT0_PC5
SCSI_Out_DBx__DB5__PORT EQU 0
SCSI_Out_DBx__DB5__SHIFT EQU 5
SCSI_Out_DBx__DB6__MASK EQU 0x40
SCSI_Out_DBx__DB6__PC EQU CYREG_PRT0_PC6
SCSI_Out_DBx__DB6__PORT EQU 0
SCSI_Out_DBx__DB6__SHIFT EQU 6
SCSI_Out_DBx__DB7__MASK EQU 0x80
SCSI_Out_DBx__DB7__PC EQU CYREG_PRT0_PC7
SCSI_Out_DBx__DB7__PORT EQU 0
SCSI_Out_DBx__DB7__SHIFT EQU 7
SCSI_Out_DBx__DM0 EQU CYREG_PRT0_DM0
SCSI_Out_DBx__DM1 EQU CYREG_PRT0_DM1
SCSI_Out_DBx__DM2 EQU CYREG_PRT0_DM2
@ -80,70 +102,48 @@ SCSI_Out_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT0_OUT_SEL0
SCSI_Out_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT0_OUT_SEL1
SCSI_Out_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT0_SYNC_OUT
SCSI_Out_DBx__PS EQU CYREG_PRT0_PS
SCSI_Out_DBx__SCSI_Out_DB0__MASK EQU 0x01
SCSI_Out_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT0_PC0
SCSI_Out_DBx__SCSI_Out_DB0__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB0__SHIFT EQU 0
SCSI_Out_DBx__SCSI_Out_DB1__MASK EQU 0x02
SCSI_Out_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT0_PC1
SCSI_Out_DBx__SCSI_Out_DB1__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB1__SHIFT EQU 1
SCSI_Out_DBx__SCSI_Out_DB2__MASK EQU 0x04
SCSI_Out_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT0_PC2
SCSI_Out_DBx__SCSI_Out_DB2__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB2__SHIFT EQU 2
SCSI_Out_DBx__SCSI_Out_DB3__MASK EQU 0x08
SCSI_Out_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT0_PC3
SCSI_Out_DBx__SCSI_Out_DB3__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB3__SHIFT EQU 3
SCSI_Out_DBx__SCSI_Out_DB4__MASK EQU 0x10
SCSI_Out_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT0_PC4
SCSI_Out_DBx__SCSI_Out_DB4__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB4__SHIFT EQU 4
SCSI_Out_DBx__SCSI_Out_DB5__MASK EQU 0x20
SCSI_Out_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT0_PC5
SCSI_Out_DBx__SCSI_Out_DB5__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB5__SHIFT EQU 5
SCSI_Out_DBx__SCSI_Out_DB6__MASK EQU 0x40
SCSI_Out_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT0_PC6
SCSI_Out_DBx__SCSI_Out_DB6__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB6__SHIFT EQU 6
SCSI_Out_DBx__SCSI_Out_DB7__MASK EQU 0x80
SCSI_Out_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT0_PC7
SCSI_Out_DBx__SCSI_Out_DB7__PORT EQU 0
SCSI_Out_DBx__SCSI_Out_DB7__SHIFT EQU 7
SCSI_Out_DBx__SHIFT EQU 0
SCSI_Out_DBx__SLW EQU CYREG_PRT0_SLW
; SCSI_RST_ISR
SCSI_RST_ISR__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
SCSI_RST_ISR__INTC_CLR_PD_REG EQU CYREG_NVIC_CLRPEND0
SCSI_RST_ISR__INTC_MASK EQU 0x400
SCSI_RST_ISR__INTC_NUMBER EQU 10
SCSI_RST_ISR__INTC_PRIOR_NUM EQU 7
SCSI_RST_ISR__INTC_PRIOR_REG EQU CYREG_NVIC_PRI_10
SCSI_RST_ISR__INTC_SET_EN_REG EQU CYREG_NVIC_SETENA0
SCSI_RST_ISR__INTC_SET_PD_REG EQU CYREG_NVIC_SETPEND0
; SDCard_BSPIM
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB06_07_ST
SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB06_ST
SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB06_CTL
SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@ -151,13 +151,13 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB06_MSK
SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB06_ST
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
@ -167,28 +167,28 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB07_08_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB07_08_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB07_08_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B1_UDB07_08_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B1_UDB07_08_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B1_UDB07_08_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B1_UDB07_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B1_UDB07_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B1_UDB07_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B1_UDB07_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B1_UDB07_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B1_UDB07_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB07_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB07_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB07_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB05_MSK
SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB05_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B0_UDB06_07_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B0_UDB06_07_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B0_UDB06_07_D0
SDCard_BSPIM_sR8_Dp_u0__16BIT_D1_REG EQU CYREG_B0_UDB06_07_D1
SDCard_BSPIM_sR8_Dp_u0__16BIT_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SDCard_BSPIM_sR8_Dp_u0__16BIT_F0_REG EQU CYREG_B0_UDB06_07_F0
SDCard_BSPIM_sR8_Dp_u0__16BIT_F1_REG EQU CYREG_B0_UDB06_07_F1
SDCard_BSPIM_sR8_Dp_u0__A0_A1_REG EQU CYREG_B0_UDB06_A0_A1
SDCard_BSPIM_sR8_Dp_u0__A0_REG EQU CYREG_B0_UDB06_A0
SDCard_BSPIM_sR8_Dp_u0__A1_REG EQU CYREG_B0_UDB06_A1
SDCard_BSPIM_sR8_Dp_u0__D0_D1_REG EQU CYREG_B0_UDB06_D0_D1
SDCard_BSPIM_sR8_Dp_u0__D0_REG EQU CYREG_B0_UDB06_D0
SDCard_BSPIM_sR8_Dp_u0__D1_REG EQU CYREG_B0_UDB06_D1
SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B0_UDB06_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B0_UDB06_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B0_UDB06_F1
SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
; SCSI_In_DBx
SCSI_In_DBx__0__MASK EQU 0x01
@ -229,6 +229,38 @@ SCSI_In_DBx__BIE EQU CYREG_PRT2_BIE
SCSI_In_DBx__BIT_MASK EQU CYREG_PRT2_BIT_MASK
SCSI_In_DBx__BYP EQU CYREG_PRT2_BYP
SCSI_In_DBx__CTL EQU CYREG_PRT2_CTL
SCSI_In_DBx__DB0__MASK EQU 0x01
SCSI_In_DBx__DB0__PC EQU CYREG_PRT2_PC0
SCSI_In_DBx__DB0__PORT EQU 2
SCSI_In_DBx__DB0__SHIFT EQU 0
SCSI_In_DBx__DB1__MASK EQU 0x02
SCSI_In_DBx__DB1__PC EQU CYREG_PRT2_PC1
SCSI_In_DBx__DB1__PORT EQU 2
SCSI_In_DBx__DB1__SHIFT EQU 1
SCSI_In_DBx__DB2__MASK EQU 0x04
SCSI_In_DBx__DB2__PC EQU CYREG_PRT2_PC2
SCSI_In_DBx__DB2__PORT EQU 2
SCSI_In_DBx__DB2__SHIFT EQU 2
SCSI_In_DBx__DB3__MASK EQU 0x08
SCSI_In_DBx__DB3__PC EQU CYREG_PRT2_PC3
SCSI_In_DBx__DB3__PORT EQU 2
SCSI_In_DBx__DB3__SHIFT EQU 3
SCSI_In_DBx__DB4__MASK EQU 0x10
SCSI_In_DBx__DB4__PC EQU CYREG_PRT2_PC4
SCSI_In_DBx__DB4__PORT EQU 2
SCSI_In_DBx__DB4__SHIFT EQU 4
SCSI_In_DBx__DB5__MASK EQU 0x20
SCSI_In_DBx__DB5__PC EQU CYREG_PRT2_PC5
SCSI_In_DBx__DB5__PORT EQU 2
SCSI_In_DBx__DB5__SHIFT EQU 5
SCSI_In_DBx__DB6__MASK EQU 0x40
SCSI_In_DBx__DB6__PC EQU CYREG_PRT2_PC6
SCSI_In_DBx__DB6__PORT EQU 2
SCSI_In_DBx__DB6__SHIFT EQU 6
SCSI_In_DBx__DB7__MASK EQU 0x80
SCSI_In_DBx__DB7__PC EQU CYREG_PRT2_PC7
SCSI_In_DBx__DB7__PORT EQU 2
SCSI_In_DBx__DB7__SHIFT EQU 7
SCSI_In_DBx__DM0 EQU CYREG_PRT2_DM0
SCSI_In_DBx__DM1 EQU CYREG_PRT2_DM1
SCSI_In_DBx__DM2 EQU CYREG_PRT2_DM2
@ -247,38 +279,6 @@ SCSI_In_DBx__PRTDSI__OUT_SEL0 EQU CYREG_PRT2_OUT_SEL0
SCSI_In_DBx__PRTDSI__OUT_SEL1 EQU CYREG_PRT2_OUT_SEL1
SCSI_In_DBx__PRTDSI__SYNC_OUT EQU CYREG_PRT2_SYNC_OUT
SCSI_In_DBx__PS EQU CYREG_PRT2_PS
SCSI_In_DBx__SCSI_Out_DB0__MASK EQU 0x01
SCSI_In_DBx__SCSI_Out_DB0__PC EQU CYREG_PRT2_PC0
SCSI_In_DBx__SCSI_Out_DB0__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB0__SHIFT EQU 0
SCSI_In_DBx__SCSI_Out_DB1__MASK EQU 0x02
SCSI_In_DBx__SCSI_Out_DB1__PC EQU CYREG_PRT2_PC1
SCSI_In_DBx__SCSI_Out_DB1__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB1__SHIFT EQU 1
SCSI_In_DBx__SCSI_Out_DB2__MASK EQU 0x04
SCSI_In_DBx__SCSI_Out_DB2__PC EQU CYREG_PRT2_PC2
SCSI_In_DBx__SCSI_Out_DB2__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB2__SHIFT EQU 2
SCSI_In_DBx__SCSI_Out_DB3__MASK EQU 0x08
SCSI_In_DBx__SCSI_Out_DB3__PC EQU CYREG_PRT2_PC3
SCSI_In_DBx__SCSI_Out_DB3__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB3__SHIFT EQU 3
SCSI_In_DBx__SCSI_Out_DB4__MASK EQU 0x10
SCSI_In_DBx__SCSI_Out_DB4__PC EQU CYREG_PRT2_PC4
SCSI_In_DBx__SCSI_Out_DB4__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB4__SHIFT EQU 4
SCSI_In_DBx__SCSI_Out_DB5__MASK EQU 0x20
SCSI_In_DBx__SCSI_Out_DB5__PC EQU CYREG_PRT2_PC5
SCSI_In_DBx__SCSI_Out_DB5__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB5__SHIFT EQU 5
SCSI_In_DBx__SCSI_Out_DB6__MASK EQU 0x40
SCSI_In_DBx__SCSI_Out_DB6__PC EQU CYREG_PRT2_PC6
SCSI_In_DBx__SCSI_Out_DB6__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB6__SHIFT EQU 6
SCSI_In_DBx__SCSI_Out_DB7__MASK EQU 0x80
SCSI_In_DBx__SCSI_Out_DB7__PC EQU CYREG_PRT2_PC7
SCSI_In_DBx__SCSI_Out_DB7__PORT EQU 2
SCSI_In_DBx__SCSI_Out_DB7__SHIFT EQU 7
SCSI_In_DBx__SHIFT EQU 0
SCSI_In_DBx__SLW EQU CYREG_PRT2_SLW
@ -307,24 +307,24 @@ SD_Init_Clk__PM_STBY_MSK EQU 0x02
; SD_Clk_Ctl
SD_Clk_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__0__POS EQU 0
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_07_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB06_07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB06_07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB06_07_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB06_07_MSK
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB06_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB06_CTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB06_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB06_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
SD_Clk_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB07_CTL
SD_Clk_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
SD_Clk_Ctl_Sync_ctrl_reg__MASK EQU 0x01
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB06_MSK
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB06_MSK_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
SD_Clk_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB07_MSK
SD_Clk_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
; PARITY_EN
PARITY_EN__0__MASK EQU 0x10
@ -358,6 +358,41 @@ PARITY_EN__PS EQU CYREG_PRT5_PS
PARITY_EN__SHIFT EQU 4
PARITY_EN__SLW EQU CYREG_PRT5_SLW
; SCSI_ATN
SCSI_ATN__0__MASK EQU 0x20
SCSI_ATN__0__PC EQU CYREG_PRT12_PC5
SCSI_ATN__0__PORT EQU 12
SCSI_ATN__0__SHIFT EQU 5
SCSI_ATN__AG EQU CYREG_PRT12_AG
SCSI_ATN__BIE EQU CYREG_PRT12_BIE
SCSI_ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
SCSI_ATN__BYP EQU CYREG_PRT12_BYP
SCSI_ATN__DM0 EQU CYREG_PRT12_DM0
SCSI_ATN__DM1 EQU CYREG_PRT12_DM1
SCSI_ATN__DM2 EQU CYREG_PRT12_DM2
SCSI_ATN__DR EQU CYREG_PRT12_DR
SCSI_ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
SCSI_ATN__INT__MASK EQU 0x20
SCSI_ATN__INT__PC EQU CYREG_PRT12_PC5
SCSI_ATN__INT__PORT EQU 12
SCSI_ATN__INT__SHIFT EQU 5
SCSI_ATN__MASK EQU 0x20
SCSI_ATN__PORT EQU 12
SCSI_ATN__PRT EQU CYREG_PRT12_PRT
SCSI_ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
SCSI_ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
SCSI_ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
SCSI_ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
SCSI_ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
SCSI_ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
SCSI_ATN__PS EQU CYREG_PRT12_PS
SCSI_ATN__SHIFT EQU 5
SCSI_ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
SCSI_ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SCSI_ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SCSI_ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SCSI_ATN__SLW EQU CYREG_PRT12_SLW
; SCSI_Out
SCSI_Out__0__AG EQU CYREG_PRT4_AG
SCSI_Out__0__AMUX EQU CYREG_PRT4_AMUX
@ -900,6 +935,44 @@ SCSI_Out__SEL__PS EQU CYREG_PRT6_PS
SCSI_Out__SEL__SHIFT EQU 0
SCSI_Out__SEL__SLW EQU CYREG_PRT6_SLW
; SCSI_RST
SCSI_RST__0__MASK EQU 0x40
SCSI_RST__0__PC EQU CYREG_PRT6_PC6
SCSI_RST__0__PORT EQU 6
SCSI_RST__0__SHIFT EQU 6
SCSI_RST__AG EQU CYREG_PRT6_AG
SCSI_RST__AMUX EQU CYREG_PRT6_AMUX
SCSI_RST__BIE EQU CYREG_PRT6_BIE
SCSI_RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
SCSI_RST__BYP EQU CYREG_PRT6_BYP
SCSI_RST__CTL EQU CYREG_PRT6_CTL
SCSI_RST__DM0 EQU CYREG_PRT6_DM0
SCSI_RST__DM1 EQU CYREG_PRT6_DM1
SCSI_RST__DM2 EQU CYREG_PRT6_DM2
SCSI_RST__DR EQU CYREG_PRT6_DR
SCSI_RST__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_RST__INTSTAT EQU CYREG_PICU6_INTSTAT
SCSI_RST__INT__MASK EQU 0x40
SCSI_RST__INT__PC EQU CYREG_PRT6_PC6
SCSI_RST__INT__PORT EQU 6
SCSI_RST__INT__SHIFT EQU 6
SCSI_RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_RST__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_RST__MASK EQU 0x40
SCSI_RST__PORT EQU 6
SCSI_RST__PRT EQU CYREG_PRT6_PRT
SCSI_RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
SCSI_RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
SCSI_RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
SCSI_RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
SCSI_RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_RST__PS EQU CYREG_PRT6_PS
SCSI_RST__SHIFT EQU 6
SCSI_RST__SLW EQU CYREG_PRT6_SLW
SCSI_RST__SNAP EQU CYREG_PICU6_SNAP
; SCSI_ID
SCSI_ID__0__MASK EQU 0x80
SCSI_ID__0__PC EQU CYREG_PRT5_PC7
@ -965,32 +1038,33 @@ SCSI_In__0__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SCSI_In__0__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SCSI_In__0__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SCSI_In__0__SLW EQU CYREG_PRT12_SLW
SCSI_In__1__AG EQU CYREG_PRT12_AG
SCSI_In__1__BIE EQU CYREG_PRT12_BIE
SCSI_In__1__BIT_MASK EQU CYREG_PRT12_BIT_MASK
SCSI_In__1__BYP EQU CYREG_PRT12_BYP
SCSI_In__1__DM0 EQU CYREG_PRT12_DM0
SCSI_In__1__DM1 EQU CYREG_PRT12_DM1
SCSI_In__1__DM2 EQU CYREG_PRT12_DM2
SCSI_In__1__DR EQU CYREG_PRT12_DR
SCSI_In__1__INP_DIS EQU CYREG_PRT12_INP_DIS
SCSI_In__1__MASK EQU 0x20
SCSI_In__1__PC EQU CYREG_PRT12_PC5
SCSI_In__1__PORT EQU 12
SCSI_In__1__PRT EQU CYREG_PRT12_PRT
SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
SCSI_In__1__PS EQU CYREG_PRT12_PS
SCSI_In__1__SHIFT EQU 5
SCSI_In__1__SIO_CFG EQU CYREG_PRT12_SIO_CFG
SCSI_In__1__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SCSI_In__1__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SCSI_In__1__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SCSI_In__1__SLW EQU CYREG_PRT12_SLW
SCSI_In__1__AG EQU CYREG_PRT6_AG
SCSI_In__1__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__1__BIE EQU CYREG_PRT6_BIE
SCSI_In__1__BIT_MASK EQU CYREG_PRT6_BIT_MASK
SCSI_In__1__BYP EQU CYREG_PRT6_BYP
SCSI_In__1__CTL EQU CYREG_PRT6_CTL
SCSI_In__1__DM0 EQU CYREG_PRT6_DM0
SCSI_In__1__DM1 EQU CYREG_PRT6_DM1
SCSI_In__1__DM2 EQU CYREG_PRT6_DM2
SCSI_In__1__DR EQU CYREG_PRT6_DR
SCSI_In__1__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__1__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__1__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__1__MASK EQU 0x10
SCSI_In__1__PC EQU CYREG_PRT6_PC4
SCSI_In__1__PORT EQU 6
SCSI_In__1__PRT EQU CYREG_PRT6_PRT
SCSI_In__1__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
SCSI_In__1__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
SCSI_In__1__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
SCSI_In__1__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
SCSI_In__1__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__1__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__1__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__1__PS EQU CYREG_PRT6_PS
SCSI_In__1__SHIFT EQU 4
SCSI_In__1__SLW EQU CYREG_PRT6_SLW
SCSI_In__2__AG EQU CYREG_PRT6_AG
SCSI_In__2__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__2__BIE EQU CYREG_PRT6_BIE
@ -1004,8 +1078,8 @@ SCSI_In__2__DR EQU CYREG_PRT6_DR
SCSI_In__2__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__2__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__2__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__2__MASK EQU 0x10
SCSI_In__2__PC EQU CYREG_PRT6_PC4
SCSI_In__2__MASK EQU 0x20
SCSI_In__2__PC EQU CYREG_PRT6_PC5
SCSI_In__2__PORT EQU 6
SCSI_In__2__PRT EQU CYREG_PRT6_PRT
SCSI_In__2__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
@ -1016,7 +1090,7 @@ SCSI_In__2__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__2__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__2__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__2__PS EQU CYREG_PRT6_PS
SCSI_In__2__SHIFT EQU 4
SCSI_In__2__SHIFT EQU 5
SCSI_In__2__SLW EQU CYREG_PRT6_SLW
SCSI_In__3__AG EQU CYREG_PRT6_AG
SCSI_In__3__AMUX EQU CYREG_PRT6_AMUX
@ -1031,8 +1105,8 @@ SCSI_In__3__DR EQU CYREG_PRT6_DR
SCSI_In__3__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__3__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__3__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__3__MASK EQU 0x20
SCSI_In__3__PC EQU CYREG_PRT6_PC5
SCSI_In__3__MASK EQU 0x80
SCSI_In__3__PC EQU CYREG_PRT6_PC7
SCSI_In__3__PORT EQU 6
SCSI_In__3__PRT EQU CYREG_PRT6_PRT
SCSI_In__3__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
@ -1043,62 +1117,62 @@ SCSI_In__3__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__3__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__3__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__3__PS EQU CYREG_PRT6_PS
SCSI_In__3__SHIFT EQU 5
SCSI_In__3__SHIFT EQU 7
SCSI_In__3__SLW EQU CYREG_PRT6_SLW
SCSI_In__4__AG EQU CYREG_PRT6_AG
SCSI_In__4__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__4__BIE EQU CYREG_PRT6_BIE
SCSI_In__4__BIT_MASK EQU CYREG_PRT6_BIT_MASK
SCSI_In__4__BYP EQU CYREG_PRT6_BYP
SCSI_In__4__CTL EQU CYREG_PRT6_CTL
SCSI_In__4__DM0 EQU CYREG_PRT6_DM0
SCSI_In__4__DM1 EQU CYREG_PRT6_DM1
SCSI_In__4__DM2 EQU CYREG_PRT6_DM2
SCSI_In__4__DR EQU CYREG_PRT6_DR
SCSI_In__4__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__4__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__4__MASK EQU 0x40
SCSI_In__4__PC EQU CYREG_PRT6_PC6
SCSI_In__4__PORT EQU 6
SCSI_In__4__PRT EQU CYREG_PRT6_PRT
SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__4__PS EQU CYREG_PRT6_PS
SCSI_In__4__SHIFT EQU 6
SCSI_In__4__SLW EQU CYREG_PRT6_SLW
SCSI_In__5__AG EQU CYREG_PRT6_AG
SCSI_In__5__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__5__BIE EQU CYREG_PRT6_BIE
SCSI_In__5__BIT_MASK EQU CYREG_PRT6_BIT_MASK
SCSI_In__5__BYP EQU CYREG_PRT6_BYP
SCSI_In__5__CTL EQU CYREG_PRT6_CTL
SCSI_In__5__DM0 EQU CYREG_PRT6_DM0
SCSI_In__5__DM1 EQU CYREG_PRT6_DM1
SCSI_In__5__DM2 EQU CYREG_PRT6_DM2
SCSI_In__5__DR EQU CYREG_PRT6_DR
SCSI_In__5__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__5__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__5__MASK EQU 0x80
SCSI_In__5__PC EQU CYREG_PRT6_PC7
SCSI_In__5__PORT EQU 6
SCSI_In__5__PRT EQU CYREG_PRT6_PRT
SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__5__PS EQU CYREG_PRT6_PS
SCSI_In__5__SHIFT EQU 7
SCSI_In__5__SLW EQU CYREG_PRT6_SLW
SCSI_In__4__AG EQU CYREG_PRT5_AG
SCSI_In__4__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__4__BIE EQU CYREG_PRT5_BIE
SCSI_In__4__BIT_MASK EQU CYREG_PRT5_BIT_MASK
SCSI_In__4__BYP EQU CYREG_PRT5_BYP
SCSI_In__4__CTL EQU CYREG_PRT5_CTL
SCSI_In__4__DM0 EQU CYREG_PRT5_DM0
SCSI_In__4__DM1 EQU CYREG_PRT5_DM1
SCSI_In__4__DM2 EQU CYREG_PRT5_DM2
SCSI_In__4__DR EQU CYREG_PRT5_DR
SCSI_In__4__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__4__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__4__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__4__MASK EQU 0x01
SCSI_In__4__PC EQU CYREG_PRT5_PC0
SCSI_In__4__PORT EQU 5
SCSI_In__4__PRT EQU CYREG_PRT5_PRT
SCSI_In__4__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
SCSI_In__4__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
SCSI_In__4__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
SCSI_In__4__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
SCSI_In__4__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__4__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__4__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__4__PS EQU CYREG_PRT5_PS
SCSI_In__4__SHIFT EQU 0
SCSI_In__4__SLW EQU CYREG_PRT5_SLW
SCSI_In__5__AG EQU CYREG_PRT5_AG
SCSI_In__5__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__5__BIE EQU CYREG_PRT5_BIE
SCSI_In__5__BIT_MASK EQU CYREG_PRT5_BIT_MASK
SCSI_In__5__BYP EQU CYREG_PRT5_BYP
SCSI_In__5__CTL EQU CYREG_PRT5_CTL
SCSI_In__5__DM0 EQU CYREG_PRT5_DM0
SCSI_In__5__DM1 EQU CYREG_PRT5_DM1
SCSI_In__5__DM2 EQU CYREG_PRT5_DM2
SCSI_In__5__DR EQU CYREG_PRT5_DR
SCSI_In__5__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__5__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__5__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__5__MASK EQU 0x02
SCSI_In__5__PC EQU CYREG_PRT5_PC1
SCSI_In__5__PORT EQU 5
SCSI_In__5__PRT EQU CYREG_PRT5_PRT
SCSI_In__5__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
SCSI_In__5__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
SCSI_In__5__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
SCSI_In__5__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
SCSI_In__5__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__5__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__5__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__5__PS EQU CYREG_PRT5_PS
SCSI_In__5__SHIFT EQU 1
SCSI_In__5__SLW EQU CYREG_PRT5_SLW
SCSI_In__6__AG EQU CYREG_PRT5_AG
SCSI_In__6__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__6__BIE EQU CYREG_PRT5_BIE
@ -1112,8 +1186,8 @@ SCSI_In__6__DR EQU CYREG_PRT5_DR
SCSI_In__6__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__6__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__6__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__6__MASK EQU 0x01
SCSI_In__6__PC EQU CYREG_PRT5_PC0
SCSI_In__6__MASK EQU 0x04
SCSI_In__6__PC EQU CYREG_PRT5_PC2
SCSI_In__6__PORT EQU 5
SCSI_In__6__PRT EQU CYREG_PRT5_PRT
SCSI_In__6__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
@ -1124,7 +1198,7 @@ SCSI_In__6__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__6__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__6__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__6__PS EQU CYREG_PRT5_PS
SCSI_In__6__SHIFT EQU 0
SCSI_In__6__SHIFT EQU 2
SCSI_In__6__SLW EQU CYREG_PRT5_SLW
SCSI_In__7__AG EQU CYREG_PRT5_AG
SCSI_In__7__AMUX EQU CYREG_PRT5_AMUX
@ -1139,8 +1213,8 @@ SCSI_In__7__DR EQU CYREG_PRT5_DR
SCSI_In__7__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__7__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__7__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__7__MASK EQU 0x02
SCSI_In__7__PC EQU CYREG_PRT5_PC1
SCSI_In__7__MASK EQU 0x08
SCSI_In__7__PC EQU CYREG_PRT5_PC3
SCSI_In__7__PORT EQU 5
SCSI_In__7__PRT EQU CYREG_PRT5_PRT
SCSI_In__7__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
@ -1151,62 +1225,8 @@ SCSI_In__7__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__7__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__7__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__7__PS EQU CYREG_PRT5_PS
SCSI_In__7__SHIFT EQU 1
SCSI_In__7__SHIFT EQU 3
SCSI_In__7__SLW EQU CYREG_PRT5_SLW
SCSI_In__8__AG EQU CYREG_PRT5_AG
SCSI_In__8__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__8__BIE EQU CYREG_PRT5_BIE
SCSI_In__8__BIT_MASK EQU CYREG_PRT5_BIT_MASK
SCSI_In__8__BYP EQU CYREG_PRT5_BYP
SCSI_In__8__CTL EQU CYREG_PRT5_CTL
SCSI_In__8__DM0 EQU CYREG_PRT5_DM0
SCSI_In__8__DM1 EQU CYREG_PRT5_DM1
SCSI_In__8__DM2 EQU CYREG_PRT5_DM2
SCSI_In__8__DR EQU CYREG_PRT5_DR
SCSI_In__8__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__8__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__8__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__8__MASK EQU 0x04
SCSI_In__8__PC EQU CYREG_PRT5_PC2
SCSI_In__8__PORT EQU 5
SCSI_In__8__PRT EQU CYREG_PRT5_PRT
SCSI_In__8__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
SCSI_In__8__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
SCSI_In__8__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
SCSI_In__8__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
SCSI_In__8__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__8__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__8__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__8__PS EQU CYREG_PRT5_PS
SCSI_In__8__SHIFT EQU 2
SCSI_In__8__SLW EQU CYREG_PRT5_SLW
SCSI_In__9__AG EQU CYREG_PRT5_AG
SCSI_In__9__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__9__BIE EQU CYREG_PRT5_BIE
SCSI_In__9__BIT_MASK EQU CYREG_PRT5_BIT_MASK
SCSI_In__9__BYP EQU CYREG_PRT5_BYP
SCSI_In__9__CTL EQU CYREG_PRT5_CTL
SCSI_In__9__DM0 EQU CYREG_PRT5_DM0
SCSI_In__9__DM1 EQU CYREG_PRT5_DM1
SCSI_In__9__DM2 EQU CYREG_PRT5_DM2
SCSI_In__9__DR EQU CYREG_PRT5_DR
SCSI_In__9__INP_DIS EQU CYREG_PRT5_INP_DIS
SCSI_In__9__LCD_COM_SEG EQU CYREG_PRT5_LCD_COM_SEG
SCSI_In__9__LCD_EN EQU CYREG_PRT5_LCD_EN
SCSI_In__9__MASK EQU 0x08
SCSI_In__9__PC EQU CYREG_PRT5_PC3
SCSI_In__9__PORT EQU 5
SCSI_In__9__PRT EQU CYREG_PRT5_PRT
SCSI_In__9__PRTDSI__CAPS_SEL EQU CYREG_PRT5_CAPS_SEL
SCSI_In__9__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT5_DBL_SYNC_IN
SCSI_In__9__PRTDSI__OE_SEL0 EQU CYREG_PRT5_OE_SEL0
SCSI_In__9__PRTDSI__OE_SEL1 EQU CYREG_PRT5_OE_SEL1
SCSI_In__9__PRTDSI__OUT_SEL0 EQU CYREG_PRT5_OUT_SEL0
SCSI_In__9__PRTDSI__OUT_SEL1 EQU CYREG_PRT5_OUT_SEL1
SCSI_In__9__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__9__PS EQU CYREG_PRT5_PS
SCSI_In__9__SHIFT EQU 3
SCSI_In__9__SLW EQU CYREG_PRT5_SLW
SCSI_In__ACK__AG EQU CYREG_PRT6_AG
SCSI_In__ACK__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__ACK__BIE EQU CYREG_PRT6_BIE
@ -1234,32 +1254,6 @@ SCSI_In__ACK__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__ACK__PS EQU CYREG_PRT6_PS
SCSI_In__ACK__SHIFT EQU 5
SCSI_In__ACK__SLW EQU CYREG_PRT6_SLW
SCSI_In__ATN__AG EQU CYREG_PRT12_AG
SCSI_In__ATN__BIE EQU CYREG_PRT12_BIE
SCSI_In__ATN__BIT_MASK EQU CYREG_PRT12_BIT_MASK
SCSI_In__ATN__BYP EQU CYREG_PRT12_BYP
SCSI_In__ATN__DM0 EQU CYREG_PRT12_DM0
SCSI_In__ATN__DM1 EQU CYREG_PRT12_DM1
SCSI_In__ATN__DM2 EQU CYREG_PRT12_DM2
SCSI_In__ATN__DR EQU CYREG_PRT12_DR
SCSI_In__ATN__INP_DIS EQU CYREG_PRT12_INP_DIS
SCSI_In__ATN__MASK EQU 0x20
SCSI_In__ATN__PC EQU CYREG_PRT12_PC5
SCSI_In__ATN__PORT EQU 12
SCSI_In__ATN__PRT EQU CYREG_PRT12_PRT
SCSI_In__ATN__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT12_DBL_SYNC_IN
SCSI_In__ATN__PRTDSI__OE_SEL0 EQU CYREG_PRT12_OE_SEL0
SCSI_In__ATN__PRTDSI__OE_SEL1 EQU CYREG_PRT12_OE_SEL1
SCSI_In__ATN__PRTDSI__OUT_SEL0 EQU CYREG_PRT12_OUT_SEL0
SCSI_In__ATN__PRTDSI__OUT_SEL1 EQU CYREG_PRT12_OUT_SEL1
SCSI_In__ATN__PRTDSI__SYNC_OUT EQU CYREG_PRT12_SYNC_OUT
SCSI_In__ATN__PS EQU CYREG_PRT12_PS
SCSI_In__ATN__SHIFT EQU 5
SCSI_In__ATN__SIO_CFG EQU CYREG_PRT12_SIO_CFG
SCSI_In__ATN__SIO_DIFF EQU CYREG_PRT12_SIO_DIFF
SCSI_In__ATN__SIO_HYST_EN EQU CYREG_PRT12_SIO_HYST_EN
SCSI_In__ATN__SIO_REG_HIFREQ EQU CYREG_PRT12_SIO_REG_HIFREQ
SCSI_In__ATN__SLW EQU CYREG_PRT12_SLW
SCSI_In__BSY__AG EQU CYREG_PRT6_AG
SCSI_In__BSY__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__BSY__BIE EQU CYREG_PRT6_BIE
@ -1421,33 +1415,6 @@ SCSI_In__REQ__PRTDSI__SYNC_OUT EQU CYREG_PRT5_SYNC_OUT
SCSI_In__REQ__PS EQU CYREG_PRT5_PS
SCSI_In__REQ__SHIFT EQU 2
SCSI_In__REQ__SLW EQU CYREG_PRT5_SLW
SCSI_In__RST__AG EQU CYREG_PRT6_AG
SCSI_In__RST__AMUX EQU CYREG_PRT6_AMUX
SCSI_In__RST__BIE EQU CYREG_PRT6_BIE
SCSI_In__RST__BIT_MASK EQU CYREG_PRT6_BIT_MASK
SCSI_In__RST__BYP EQU CYREG_PRT6_BYP
SCSI_In__RST__CTL EQU CYREG_PRT6_CTL
SCSI_In__RST__DM0 EQU CYREG_PRT6_DM0
SCSI_In__RST__DM1 EQU CYREG_PRT6_DM1
SCSI_In__RST__DM2 EQU CYREG_PRT6_DM2
SCSI_In__RST__DR EQU CYREG_PRT6_DR
SCSI_In__RST__INP_DIS EQU CYREG_PRT6_INP_DIS
SCSI_In__RST__LCD_COM_SEG EQU CYREG_PRT6_LCD_COM_SEG
SCSI_In__RST__LCD_EN EQU CYREG_PRT6_LCD_EN
SCSI_In__RST__MASK EQU 0x40
SCSI_In__RST__PC EQU CYREG_PRT6_PC6
SCSI_In__RST__PORT EQU 6
SCSI_In__RST__PRT EQU CYREG_PRT6_PRT
SCSI_In__RST__PRTDSI__CAPS_SEL EQU CYREG_PRT6_CAPS_SEL
SCSI_In__RST__PRTDSI__DBL_SYNC_IN EQU CYREG_PRT6_DBL_SYNC_IN
SCSI_In__RST__PRTDSI__OE_SEL0 EQU CYREG_PRT6_OE_SEL0
SCSI_In__RST__PRTDSI__OE_SEL1 EQU CYREG_PRT6_OE_SEL1
SCSI_In__RST__PRTDSI__OUT_SEL0 EQU CYREG_PRT6_OUT_SEL0
SCSI_In__RST__PRTDSI__OUT_SEL1 EQU CYREG_PRT6_OUT_SEL1
SCSI_In__RST__PRTDSI__SYNC_OUT EQU CYREG_PRT6_SYNC_OUT
SCSI_In__RST__PS EQU CYREG_PRT6_PS
SCSI_In__RST__SHIFT EQU 6
SCSI_In__RST__SLW EQU CYREG_PRT6_SLW
SCSI_In__SEL__AG EQU CYREG_PRT5_AG
SCSI_In__SEL__AMUX EQU CYREG_PRT5_AMUX
SCSI_In__SEL__BIE EQU CYREG_PRT5_BIE
@ -1831,7 +1798,6 @@ CYDEV_DEBUGGING_DPS_JTAG_4 EQU 1
CYDEV_DEBUGGING_DPS_JTAG_5 EQU 0
CYDEV_DEBUGGING_DPS_SWD EQU 2
CYDEV_DEBUGGING_ENABLE EQU 1
CYDEV_DEBUGGING_REQXRES EQU 1
CYDEV_DEBUGGING_XRES EQU 0
CYDEV_DEBUG_ENABLE_MASK EQU 0x20
CYDEV_DEBUG_ENABLE_REGISTER EQU CYREG_MLOGIC_DEBUG
@ -1839,7 +1805,7 @@ CYDEV_DMA_CHANNELS_AVAILABLE EQU 24
CYDEV_ECC_ENABLE EQU 0
CYDEV_HEAP_SIZE EQU 0x1000
CYDEV_INSTRUCT_CACHE_ENABLED EQU 1
CYDEV_INTR_RISING EQU 0x00000003
CYDEV_INTR_RISING EQU 0x00000001
CYDEV_PROJ_TYPE EQU 0
CYDEV_PROJ_TYPE_BOOTLOADER EQU 1
CYDEV_PROJ_TYPE_LOADABLE EQU 2

230
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cymetadata.c Normal file
View File

@ -0,0 +1,230 @@
/*******************************************************************************
* FILENAME: cymetadata.c
*
* PSoC Creator 3.0
*
* DESCRIPTION:
* This file defines all extra memory spaces that need to be included.
* This file is automatically generated by PSoC Creator.
*
********************************************************************************
* Copyright 2008-2013, Cypress Semiconductor Corporation. All rights reserved.
* You may use this file only in accordance with the license, terms, conditions,
* disclaimers, and limitations in the end user license agreement accompanying
* the software package with which this file was provided.
********************************************************************************/
#include "cytypes.h"
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cyconfigecc"), used))
#elif defined(__ICCARM__)
#pragma location=".cyconfigecc"
#else
#error "Unsupported toolchain"
#endif
const uint8 cy_meta_configecc[] = {
0x01u, 0x45u, 0x00u, 0x40u, 0x07u, 0x52u, 0x00u, 0x40u,
0x01u, 0x64u, 0x00u, 0x40u, 0x02u, 0x03u, 0x01u, 0x40u,
0x3Fu, 0x04u, 0x01u, 0x40u, 0x2Au, 0x05u, 0x01u, 0x40u,
0x03u, 0x06u, 0x01u, 0x40u, 0x41u, 0x07u, 0x01u, 0x40u,
0x01u, 0x0Du, 0x01u, 0x40u, 0x09u, 0x15u, 0x01u, 0x40u,
0x43u, 0x16u, 0x01u, 0x40u, 0x3Au, 0x17u, 0x01u, 0x40u,
0x02u, 0x40u, 0x01u, 0x40u, 0x01u, 0x41u, 0x01u, 0x40u,
0x01u, 0x42u, 0x01u, 0x40u, 0x02u, 0x43u, 0x01u, 0x40u,
0x02u, 0x44u, 0x01u, 0x40u, 0x02u, 0x45u, 0x01u, 0x40u,
0x04u, 0x48u, 0x01u, 0x40u, 0x0Eu, 0x49u, 0x01u, 0x40u,
0x04u, 0x50u, 0x01u, 0x40u, 0x01u, 0x51u, 0x01u, 0x40u,
0x36u, 0x02u, 0x14u, 0xFFu, 0x18u, 0x04u, 0x19u, 0x0Cu,
0x1Cu, 0xE1u, 0x2Cu, 0xFFu, 0x34u, 0xF0u, 0x64u, 0x10u,
0x86u, 0x0Fu, 0x98u, 0x40u, 0xB0u, 0x40u, 0x00u, 0x01u,
0x1Du, 0x01u, 0x2Du, 0x01u, 0x30u, 0x01u, 0x31u, 0x01u,
0x39u, 0x02u, 0x3Eu, 0x01u, 0x56u, 0x08u, 0x58u, 0x04u,
0x59u, 0x0Bu, 0x5Bu, 0x04u, 0x5Cu, 0x90u, 0x5Du, 0x90u,
0x5Fu, 0x01u, 0x80u, 0x6Cu, 0x81u, 0x41u, 0x84u, 0x68u,
0x86u, 0x04u, 0x88u, 0x6Cu, 0x89u, 0x81u, 0x8Bu, 0x40u,
0x8Du, 0x41u, 0x91u, 0x04u, 0x92u, 0x02u, 0x94u, 0x10u,
0x95u, 0xE2u, 0x96u, 0x68u, 0x97u, 0x08u, 0x98u, 0x10u,
0x99u, 0x88u, 0x9Au, 0xC5u, 0x9Bu, 0x61u, 0x9Cu, 0x6Cu,
0x9Du, 0x47u, 0x9Fu, 0x98u, 0xA0u, 0x6Cu, 0xA1u, 0x10u,
0xA4u, 0x04u, 0xA5u, 0x41u, 0xA8u, 0x93u, 0xA9u, 0x40u,
0xAAu, 0x20u, 0xACu, 0x0Fu, 0xADu, 0x01u, 0xAEu, 0x90u,
0xAFu, 0x40u, 0xB2u, 0x78u, 0xB4u, 0x07u, 0xB5u, 0xC0u,
0xB6u, 0x80u, 0xB7u, 0x3Fu, 0xB9u, 0x80u, 0xBAu, 0x38u,
0xBBu, 0x20u, 0xBEu, 0x40u, 0xBFu, 0x40u, 0xD4u, 0x09u,
0xD8u, 0x0Bu, 0xD9u, 0x0Bu, 0xDBu, 0x0Bu, 0xDCu, 0x99u,
0xDDu, 0x90u, 0xDFu, 0x01u, 0x00u, 0x01u, 0x04u, 0x28u,
0x06u, 0x80u, 0x0Cu, 0x02u, 0x0Du, 0x01u, 0x0Eu, 0x29u,
0x17u, 0x69u, 0x1Au, 0x80u, 0x1Du, 0x30u, 0x1Eu, 0x28u,
0x1Fu, 0x40u, 0x21u, 0x02u, 0x22u, 0x02u, 0x25u, 0x90u,
0x27u, 0x08u, 0x29u, 0x40u, 0x2Fu, 0xAAu, 0x31u, 0x80u,
0x36u, 0x06u, 0x37u, 0x60u, 0x3Cu, 0x80u, 0x3Du, 0x20u,
0x3Eu, 0x81u, 0x4Bu, 0xC0u, 0x58u, 0x40u, 0x5Du, 0x24u,
0x5Eu, 0x02u, 0x5Fu, 0x40u, 0x60u, 0x01u, 0x66u, 0x40u,
0x78u, 0x02u, 0x7Cu, 0x02u, 0x98u, 0x40u, 0xC0u, 0x78u,
0xC2u, 0xF0u, 0xC4u, 0xF0u, 0xCAu, 0xF8u, 0xCCu, 0xF8u,
0xCEu, 0xB0u, 0xD6u, 0xF8u, 0xD8u, 0x18u, 0xDEu, 0x81u,
0xD6u, 0x08u, 0xDBu, 0x04u, 0xDDu, 0x90u, 0x00u, 0x01u,
0x02u, 0x40u, 0x05u, 0x10u, 0x07u, 0x61u, 0x0Du, 0x02u,
0x0Eu, 0x21u, 0x0Fu, 0x08u, 0x17u, 0x1Au, 0x1Du, 0x40u,
0x24u, 0x01u, 0x25u, 0x0Cu, 0x26u, 0x02u, 0x27u, 0x60u,
0x2Au, 0x02u, 0x2Bu, 0x80u, 0x2Cu, 0x02u, 0x2Eu, 0x01u,
0x2Fu, 0x28u, 0x36u, 0x46u, 0x3Cu, 0x80u, 0x3Du, 0x28u,
0x44u, 0x80u, 0x45u, 0xA8u, 0x4Cu, 0x80u, 0x4Du, 0x04u,
0x4Eu, 0x02u, 0x54u, 0x02u, 0x56u, 0x10u, 0x57u, 0x84u,
0x59u, 0x80u, 0x60u, 0x02u, 0x66u, 0x20u, 0x6Cu, 0x14u,
0x6Eu, 0xA1u, 0x6Fu, 0x3Bu, 0x74u, 0x40u, 0x77u, 0x02u,
0x7Cu, 0x02u, 0x94u, 0x28u, 0x95u, 0x04u, 0x96u, 0x01u,
0x99u, 0x10u, 0x9Bu, 0x08u, 0x9Cu, 0x02u, 0x9Du, 0x40u,
0x9Eu, 0x40u, 0x9Fu, 0x61u, 0xA1u, 0x32u, 0xA2u, 0x04u,
0xA4u, 0x42u, 0xA6u, 0x01u, 0xA7u, 0xAAu, 0xAAu, 0x40u,
0xADu, 0x21u, 0xC0u, 0xF0u, 0xC2u, 0xF0u, 0xC4u, 0x70u,
0xCAu, 0xF0u, 0xCCu, 0xD0u, 0xCEu, 0x70u, 0xD0u, 0xF0u,
0xD2u, 0x10u, 0xD6u, 0x08u, 0xD8u, 0x28u, 0xDEu, 0x80u,
0xEAu, 0x80u, 0x84u, 0x80u, 0x89u, 0x40u, 0x9Cu, 0x80u,
0xA1u, 0x40u, 0xAAu, 0x40u, 0xADu, 0x01u, 0xB0u, 0x85u,
0xB2u, 0x10u, 0xE6u, 0x20u, 0x00u, 0x04u, 0x02u, 0x08u,
0x04u, 0x10u, 0x05u, 0x18u, 0x06u, 0x0Cu, 0x07u, 0x25u,
0x08u, 0x20u, 0x09u, 0x20u, 0x0Au, 0x0Cu, 0x0Bu, 0x18u,
0x0Eu, 0x03u, 0x0Fu, 0x01u, 0x11u, 0x08u, 0x12u, 0x04u,
0x13u, 0x33u, 0x14u, 0x03u, 0x19u, 0x2Eu, 0x1Au, 0x30u,
0x1Bu, 0x10u, 0x1Cu, 0x03u, 0x20u, 0x03u, 0x26u, 0x01u,
0x28u, 0x03u, 0x2Eu, 0x48u, 0x30u, 0x40u, 0x32u, 0x01u,
0x34u, 0x3Cu, 0x35u, 0x38u, 0x36u, 0x02u, 0x37u, 0x07u,
0x3Bu, 0x20u, 0x3Eu, 0x44u, 0x54u, 0x40u, 0x58u, 0x0Bu,
0x59u, 0x0Bu, 0x5Bu, 0x0Bu, 0x5Cu, 0x99u, 0x5Du, 0x90u,
0x5Fu, 0x01u, 0x80u, 0x01u, 0x82u, 0x02u, 0x88u, 0x06u,
0x8Bu, 0x07u, 0x8Eu, 0x10u, 0x91u, 0x01u, 0x92u, 0x08u,
0x97u, 0x02u, 0x98u, 0x02u, 0x9Au, 0x01u, 0xA1u, 0x07u,
0xA8u, 0x01u, 0xA9u, 0x04u, 0xAAu, 0x04u, 0xACu, 0x08u,
0xAEu, 0x10u, 0xB0u, 0x07u, 0xB1u, 0x07u, 0xB2u, 0x07u,
0xB6u, 0x18u, 0xB8u, 0x0Au, 0xBEu, 0x40u, 0xBFu, 0x01u,
0xD8u, 0x0Bu, 0xD9u, 0x04u, 0xDBu, 0x04u, 0xDCu, 0x09u,
0xDFu, 0x01u, 0x00u, 0x10u, 0x01u, 0x40u, 0x03u, 0x40u,
0x05u, 0x10u, 0x07u, 0x61u, 0x09u, 0x20u, 0x0Au, 0x80u,
0x0Eu, 0x69u, 0x10u, 0x02u, 0x12u, 0x08u, 0x13u, 0x20u,
0x16u, 0x12u, 0x17u, 0x12u, 0x18u, 0x10u, 0x19u, 0x81u,
0x1Du, 0x84u, 0x1Eu, 0x4Au, 0x1Fu, 0x10u, 0x21u, 0x01u,
0x25u, 0x40u, 0x27u, 0x08u, 0x29u, 0x11u, 0x32u, 0x0Au,
0x35u, 0x10u, 0x36u, 0x02u, 0x3Bu, 0x20u, 0x3Du, 0x88u,
0x3Eu, 0x20u, 0x46u, 0x20u, 0x47u, 0x08u, 0x64u, 0x05u,
0x65u, 0x04u, 0x68u, 0x02u, 0x78u, 0x02u, 0x7Cu, 0x02u,
0x8Du, 0x40u, 0x92u, 0x01u, 0x98u, 0x02u, 0x99u, 0x10u,
0x9Au, 0x12u, 0x9Bu, 0x73u, 0x9Cu, 0x80u, 0x9Du, 0x80u,
0x9Eu, 0x20u, 0xA0u, 0x80u, 0xA1u, 0x24u, 0xA2u, 0x12u,
0xA5u, 0x80u, 0xA6u, 0x01u, 0xC0u, 0xFBu, 0xC2u, 0xFAu,
0xC4u, 0xF3u, 0xCAu, 0x05u, 0xCCu, 0xA3u, 0xCEu, 0x74u,
0xD8u, 0x70u, 0xDEu, 0x81u, 0xE0u, 0x40u, 0x33u, 0x40u,
0xCCu, 0x10u, 0x9Fu, 0x40u, 0x9Fu, 0x40u, 0xABu, 0x40u,
0xEEu, 0x80u, 0x14u, 0x40u, 0xC4u, 0x04u, 0xB0u, 0x40u,
0xEAu, 0x01u, 0x20u, 0x10u, 0x26u, 0x80u, 0x8Eu, 0x80u,
0xC8u, 0x60u, 0x08u, 0x02u, 0x5Bu, 0x20u, 0x5Fu, 0x40u,
0x84u, 0x02u, 0x8Bu, 0x20u, 0x93u, 0x40u, 0xA8u, 0x10u,
0xAFu, 0x40u, 0xC2u, 0x10u, 0xD4u, 0x80u, 0xD6u, 0x20u,
0xE4u, 0x40u, 0xECu, 0x80u, 0xEEu, 0x40u, 0x01u, 0x01u,
0x0Bu, 0x01u, 0x11u, 0x01u, 0x1Bu, 0x01u, 0x00u, 0x03u,
0x1Fu, 0x00u, 0x20u, 0x00u, 0x00u, 0x91u, 0xFFu, 0x6Eu,
0x7Fu, 0x24u, 0x80u, 0x00u, 0x90u, 0x6Cu, 0x40u, 0x00u,
0x00u, 0x71u, 0x60u, 0x82u, 0xC0u, 0x10u, 0x08u, 0xEFu,
0x00u, 0x00u, 0x9Fu, 0x00u, 0xC0u, 0x6Cu, 0x02u, 0x00u,
0xC0u, 0x6Cu, 0x01u, 0x00u, 0x80u, 0x24u, 0x00u, 0x48u,
0xC0u, 0x00u, 0x04u, 0x6Cu, 0x00u, 0x48u, 0x00u, 0x00u,
0x00u, 0x0Fu, 0x00u, 0xF0u, 0x00u, 0x00u, 0xFFu, 0x10u,
0x00u, 0x08u, 0x00u, 0x00u, 0x00u, 0x00u, 0x40u, 0x40u,
0x32u, 0x05u, 0x10u, 0x00u, 0x04u, 0xFEu, 0xDBu, 0xCBu,
0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u,
0x04u, 0x0Bu, 0x0Bu, 0x0Bu, 0x90u, 0x99u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u,
0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0xFFu, 0xFFu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x08u, 0x00u, 0x30u, 0x00u, 0x08u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x10u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x01u, 0x02u, 0x00u, 0xF1u, 0x0Eu,
0x0Eu, 0x00u, 0x0Cu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0xFCu, 0xFCu, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0xF0u, 0x00u, 0x0Fu, 0xF0u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x01u, 0x00u, 0x00u, 0xF0u, 0x0Fu, 0x0Fu, 0x00u,
0x00u, 0x00u, 0x00u, 0x01u
};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cycustnvl"), used))
#elif defined(__ICCARM__)
#pragma location=".cycustnvl"
#else
#error "Unsupported toolchain"
#endif
const uint8 cy_meta_custnvl[] = {
0x00u, 0x00u, 0x40u, 0x05u
};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cywolatch"), used))
#elif defined(__ICCARM__)
#pragma location=".cywolatch"
#else
#error "Unsupported toolchain"
#endif
const uint8 cy_meta_wonvl[] = {
0xBCu, 0x90u, 0xACu, 0xAFu
};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cyflashprotect"), used))
#elif defined(__ICCARM__)
#pragma location=".cyflashprotect"
#else
#error "Unsupported toolchain"
#endif
const uint8 cy_meta_flashprotect[] = {
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u
};
#if defined(__GNUC__) || defined(__ARMCC_VERSION)
__attribute__ ((__section__(".cymeta"), used))
#elif defined(__ICCARM__)
#pragma location=".cymeta"
#else
#error "Unsupported toolchain"
#endif
const uint8 cy_metadata[] = {
0x00u, 0x01u, 0x2Eu, 0x12u, 0xF0u, 0x69u, 0x00u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u
};

2
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cypins.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: cypins.h
* Version 3.40
* Version 4.0
*
* Description:
* This file contains the function prototypes and constants used for port/pin

99
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cytypes.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* FILENAME: cytypes.h
* Version 3.40
* Version 4.0
*
* Description:
* CyTypes provides register access macros and approved types for use in
@ -38,6 +38,12 @@
#include "cyfitter.h"
#if defined( __ICCARM__ )
/* Suppress warning for multiple volatile variables in an expression. */
/* This is common in component code and the usage is not order dependent. */
#pragma diag_suppress=Pa082
#endif /* defined( __ICCARM__ ) */
/***************************************
* Conditional Compilation Parameters
@ -55,12 +61,21 @@
/*******************************************************************************
* MEMBER encodes both the family and the detailed architecture
*******************************************************************************/
#define CY_PSOC4A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4A)
#ifdef CYDEV_CHIP_MEMBER_4D
#define CY_PSOC4D (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_4D)
#define CY_PSOC4SF (CY_PSOC4D)
#else
#define CY_PSOC4D (0u != 0u)
#define CY_PSOC4SF (CY_PSOC4D)
#endif /* CYDEV_CHIP_MEMBER_4D */
#define CY_PSOC5A (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5A)
#ifdef CYDEV_CHIP_MEMBER_5B
#define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
#define CY_PSOC5LP (CYDEV_CHIP_MEMBER_USED == CYDEV_CHIP_MEMBER_5B)
#else
#define CY_PSOC5LP 0
#endif
#define CY_PSOC5LP (0u != 0u)
#endif /* CYDEV_CHIP_MEMBER_5B */
/*******************************************************************************
@ -103,23 +118,23 @@ typedef char char8;
* endian conversion. These functions should be called through the
* CY_GET_XTND_REGxx and CY_SET_XTND_REGxx macros.
***************************************************************************/
extern uint8 cyread8 (volatile void far *addr);
extern uint8 cyread8 (const volatile void far *addr);
extern void cywrite8 (volatile void far *addr, uint8 value);
extern uint16 cyread16 (volatile void far *addr);
extern uint16 cyread16_nodpx(volatile void far *addr);
extern uint16 cyread16 (const volatile void far *addr);
extern uint16 cyread16_nodpx(const volatile void far *addr);
extern void cywrite16 (volatile void far *addr, uint16 value);
extern void cywrite16_nodpx(volatile void far *addr, uint16 value);
extern uint32 cyread24 (volatile void far *addr);
extern uint32 cyread24_nodpx(volatile void far *addr);
extern uint32 cyread24 (const volatile void far *addr);
extern uint32 cyread24_nodpx(const volatile void far *addr);
extern void cywrite24 (volatile void far *addr, uint32 value);
extern void cywrite24_nodpx(volatile void far *addr, uint32 value);
extern uint32 cyread32 (volatile void far *addr);
extern uint32 cyread32_nodpx(volatile void far *addr);
extern uint32 cyread32 (const volatile void far *addr);
extern uint32 cyread32_nodpx(const volatile void far *addr);
extern void cywrite32 (volatile void far *addr, uint32 value);
extern void cywrite32_nodpx(volatile void far *addr, uint32 value);
@ -144,9 +159,9 @@ typedef char char8;
#if(CY_PSOC4)
extern uint32 CyGetReg24(uint32 volatile * addr);
extern uint32 CyGetReg24(uint32 const volatile * addr);
#endif /*(CY_PSOC4)*/
#endif /* (CY_PSOC4) */
#endif /* (CY_PSOC3) */
@ -169,7 +184,7 @@ typedef char char8;
#define CYSMALL small
#define CYXDATA xdata
#define XDATA xdata
#define CY_NOINIT
#else
@ -187,13 +202,21 @@ typedef char char8;
#define CYSMALL
#define CYXDATA
#define XDATA
#if defined(__ARMCC_VERSION)
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
#elif defined (__GNUC__)
#define CY_NOINIT __attribute__ ((section(".noinit")))
#endif /* (__ARMCC_VERSION) */
#if defined(__ARMCC_VERSION)
#define CY_NOINIT __attribute__ ((section(".noinit"), zero_init))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
#define CY_ALIGN(align) __align(align)
#elif defined (__GNUC__)
#define CY_NOINIT __attribute__ ((section(".noinit")))
#define CY_NORETURN __attribute__ ((noreturn))
#define CY_SECTION(name) __attribute__ ((section(name)))
#define CY_ALIGN(align) __attribute__ ((aligned(align)))
#elif defined (__ICCARM__)
#define CY_NOINIT __no_init
#define CY_NORETURN __noreturn
#endif /* (__ARMCC_VERSION) */
#endif /* (CY_PSOC3) */
@ -234,6 +257,10 @@ typedef volatile uint32 CYXDATA reg32;
#define CY_ISR_PROTO(FuncName) void FuncName (void)
typedef void (* cyisraddress)(void);
#if defined (__ICCARM__)
typedef union { cyisraddress __fun; void * __ptr; } intvec_elem;
#endif /* defined (__ICCARM__) */
#endif /* (CY_PSOC3) */
@ -252,50 +279,50 @@ typedef volatile uint32 CYXDATA reg32;
/* Access macros for 8, 16, 24 and 32-bit registers, IN THE FIRST 64K OF XDATA */
#define CY_GET_REG8(addr) (*((reg8 *)(addr)))
#define CY_GET_REG8(addr) (*((const reg8 *)(addr)))
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))
#define CY_GET_REG16(addr) cyread16_nodpx ((volatile void far *)(reg16 *)(addr))
#define CY_GET_REG16(addr) cyread16_nodpx ((const volatile void far *)(const reg16 *)(addr))
#define CY_SET_REG16(addr, value) cywrite16_nodpx((volatile void far *)(reg16 *)(addr), value)
#define CY_GET_REG24(addr) cyread24_nodpx ((volatile void far *)(reg32 *)(addr))
#define CY_GET_REG24(addr) cyread24_nodpx ((const volatile void far *)(const reg32 *)(addr))
#define CY_SET_REG24(addr, value) cywrite24_nodpx((volatile void far *)(reg32 *)(addr),value)
#define CY_GET_REG32(addr) cyread32_nodpx ((volatile void far *)(reg32 *)(addr))
#define CY_GET_REG32(addr) cyread32_nodpx ((const volatile void far *)(const reg32 *)(addr))
#define CY_SET_REG32(addr, value) cywrite32_nodpx((volatile void far *)(reg32 *)(addr), value)
/* Access 8, 16, 24 and 32-bit registers, ABOVE THE FIRST 64K OF XDATA */
#define CY_GET_XTND_REG8(addr) cyread8((volatile void far *)(addr))
#define CY_GET_XTND_REG8(addr) cyread8((const volatile void far *)(addr))
#define CY_SET_XTND_REG8(addr, value) cywrite8((volatile void far *)(addr), value)
#define CY_GET_XTND_REG16(addr) cyread16((volatile void far *)(addr))
#define CY_GET_XTND_REG16(addr) cyread16((const volatile void far *)(addr))
#define CY_SET_XTND_REG16(addr, value) cywrite16((volatile void far *)(addr), value)
#define CY_GET_XTND_REG24(addr) cyread24((volatile void far *)(addr))
#define CY_GET_XTND_REG24(addr) cyread24((const volatile void far *)(addr))
#define CY_SET_XTND_REG24(addr, value) cywrite24((volatile void far *)(addr), value)
#define CY_GET_XTND_REG32(addr) cyread32((volatile void far *)(addr))
#define CY_GET_XTND_REG32(addr) cyread32((const volatile void far *)(addr))
#define CY_SET_XTND_REG32(addr, value) cywrite32((volatile void far *)(addr), value)
#else
/* 8, 16, 24 and 32-bit register access macros */
#define CY_GET_REG8(addr) (*((reg8 *)(addr)))
#define CY_GET_REG8(addr) (*((const reg8 *)(addr)))
#define CY_SET_REG8(addr, value) (*((reg8 *)(addr)) = (uint8)(value))
#define CY_GET_REG16(addr) (*((reg16 *)(addr)))
#define CY_GET_REG16(addr) (*((const reg16 *)(addr)))
#define CY_SET_REG16(addr, value) (*((reg16 *)(addr)) = (uint16)(value))
#define CY_SET_REG24(addr, value) CySetReg24((reg32 *) (addr), (value))
#if(CY_PSOC4)
#define CY_GET_REG24(addr) CyGetReg24((reg32 *) (addr))
#define CY_GET_REG24(addr) CyGetReg24((const reg32 *) (addr))
#else
#define CY_GET_REG24(addr) (*((reg32 *)(addr)) & 0x00FFFFFFu)
#define CY_GET_REG24(addr) (*((const reg32 *)(addr)) & 0x00FFFFFFu)
#endif /* (CY_PSOC4) */
#define CY_GET_REG32(addr) (*((reg32 *)(addr)))
#define CY_GET_REG32(addr) (*((const reg32 *)(addr)))
#define CY_SET_REG32(addr, value) (*((reg32 *)(addr)) = (uint32)(value))
@ -321,11 +348,11 @@ typedef volatile uint32 CYXDATA reg32;
*******************************************************************************/
/* Get 8 bits of a 16 bit value. */
#define LO8(x) ((uint8) (x))
#define HI8(x) ((uint8) ((x) >> 8))
#define LO8(x) ((uint8) ((x) & 0xFFu))
#define HI8(x) ((uint8) ((uint16)(x) >> 8))
/* Get 16 bits of a 32 bit value. */
#define LO16(x) ((uint16) (x))
#define LO16(x) ((uint16) ((x) & 0xFFFFu))
#define HI16(x) ((uint16) ((uint32)(x) >> 16))
/* Swap the byte ordering of a 32 bit value */

8
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/cyutils.c
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* FILENAME: cyutils.c
* Version 3.40
* Version 4.0
*
* Description:
* CyUtils provides function to handle 24-bit value writes.
@ -65,12 +65,12 @@
* No
*
***************************************************************************/
uint32 CyGetReg24(uint32 volatile * addr)
uint32 CyGetReg24(uint32 const volatile * addr)
{
uint8 volatile *tmpAddr;
uint8 const volatile *tmpAddr;
uint32 value;
tmpAddr = (uint8 volatile *) addr;
tmpAddr = (uint8 const volatile *) addr;
value = (uint32) tmpAddr[0u];
value |= ((uint32) tmpAddr[1u] << 8u );

0
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/eeprom.hex Normal file
View File

13
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoC5/project.h
View File

@ -1,6 +1,6 @@
/*******************************************************************************
* File Name: project.h
* PSoC Creator 2.2 Component Pack 6
* File Name: project.h
* PSoC Creator 3.0
*
* Description:
* This file is automatically generated by PSoC Creator and should not
@ -18,6 +18,7 @@
#include <cydevice.h>
#include <cydevice_trm.h>
#include <cyfitter.h>
#include <cydisabledsheets.h>
#include <SCSI_In_DBx_aliases.h>
#include <SCSI_In_DBx.h>
#include <SCSI_Out_DBx_aliases.h>
@ -50,6 +51,12 @@
#include <SD_Init_Clk.h>
#include <SD_Data_Clk.h>
#include <SD_Clk_Ctl.h>
#include <SCSI_RST_aliases.h>
#include <SCSI_RST.h>
#include <SCSI_ATN_aliases.h>
#include <SCSI_ATN.h>
#include <SCSI_RST_ISR.h>
#include <SCSI_ATN_ISR.h>
#include <core_cm3_psoc5.h>
#include <core_cm3.h>
#include <CyDmac.h>
@ -59,6 +66,8 @@
#include <cyPm.h>
#include <CySpc.h>
#include <cytypes.h>
#include <core_cmFunc.h>
#include <core_cmInstr.h>
/*[]*/

208
software/SCSI2SD/SCSI2SD.cydsn/Generated_Source/PSoCCreatorExportIDE.xml Executable file
View File

@ -0,0 +1,208 @@
<?xml version="1.0" encoding="utf-8"?>
<!--DO NOT EDIT. This document is generated by PSoC Creator design builds.-->
<PSoCCreatorIdeExport Version="1">
<Device Part="CY8C5268AXI-LP047" Processor="CortexM3" DeviceID="2E12F069" />
<Toolchains>
<Toolchain Name="ARM GCC" Selected="True">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="arm-none-eabi-as.exe" Options="-I. -I./Generated_Source/PSoC5 -mcpu=cortex-m3 -mthumb -g -alh=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="arm-none-eabi-gcc.exe" Options="-I. -I./Generated_Source/PSoC5 -Wno-main -mcpu=cortex-m3 -mthumb -Wall -g -D NDEBUG -Wa,-alh=${OutputDir}\${CompileFile}.lst -Os -ffunction-sections " />
<Tool Name="linker" Command="arm-none-eabi-gcc.exe" Options="-mthumb -march=armv7-m -mfix-cortex-m3-ldrd -T .\Generated_Source\PSoC5\cm3gcc.ld -g -Wl,-Map,${OutputDir}\${ProjectShortName}.map -specs=nano.specs -Wl,--gc-sections " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
<Toolchain Name="ARM Keil MDK" Selected="False">
<Tool Name="prebuild" Command="" Options="" />
<Tool Name="assembler" Command="armasm.exe" Options="-i. -iGenerated_Source/PSoC5 --diag_style=gnu --thumb --cpu=Cortex-M3 -g --list=${OutputDir}/${CompileFile}.lst " />
<Tool Name="compiler" Command="armcc.exe" Options="-I. -I./Generated_Source/PSoC5 --diag_suppress=951 --diag_style=gnu --cpu=Cortex-M3 -g -D NDEBUG --signed_chars --list -Ospace --split_sections " />
<Tool Name="linker" Command="armlink.exe" Options="--diag_style=gnu --no_startup --cpu=Cortex-M3 --scatter .\Generated_Source\PSoC5\Cm3RealView.scat --map --list ${OutputDir}\${ProjectShortName}.map " />
<Tool Name="postbuild" Command="" Options="" />
</Toolchain>
</Toolchains>
<Project Name="SCSI2SD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn" Version="4.0" Type="Normal">
<CMSIS_SVD_File>SCSI2SD.svd</CMSIS_SVD_File>
<Datasheet>SCSI2SD_datasheet.pdf</Datasheet>
<LinkerFiles>
<LinkerFile Toolchain="ARM GCC">.\Generated_Source\PSoC5\cm3gcc.ld</LinkerFile>
<LinkerFile Toolchain="ARM Keil MDK">.\Generated_Source\PSoC5\Cm3RealView.scat</LinkerFile>
<LinkerFile Toolchain="IAR EWARM">.\Generated_Source\PSoC5\Cm3Iar.icf</LinkerFile>
</LinkerFiles>
<Folders>
<Folder BuildType="BUILD" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
<Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\main.c</File>
<File BuildType="BUILD" Toolchain="">.\loopback.c</File>
<File BuildType="BUILD" Toolchain="">.\blinky.c</File>
<File BuildType="BUILD" Toolchain="">.\bits.c</File>
<File BuildType="BUILD" Toolchain="">.\device.h</File>
<File BuildType="BUILD" Toolchain="">.\blinky.h</File>
<File BuildType="BUILD" Toolchain="">.\loopback.h</File>
<File BuildType="BUILD" Toolchain="">.\bits.h</File>
</Files>
</Folder>
<Folder BuildType="BUILD" Path="\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
<Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.c</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\diagnostic.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\disk.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\geometry.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\inquiry.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\led.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\mode.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsi.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\scsiPhy.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sense.h</File>
<File BuildType="BUILD" Toolchain="">\\xengarden\michael\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\sd.h</File>
</Files>
</Folder>
<Folder BuildType="STRICT" Path="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn\Generated_Source\PSoC5">
<Files Root="Z:\projects\SCSI2SD\git\software\SCSI2SD\SCSI2SD.cydsn">
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter_cfg.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevice_trm.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicegnu_trm.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cydevicerv_trm.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfittergnu.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitterrv.inc</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\cyfitter.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_In_DBx.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_Out_DBx.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MISO.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_MOSI.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_SCK.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CS.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT1.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_DAT2.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_WP.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SD_CD.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\SCSI_ID_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN_aliases.h</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.c</File>
<File BuildType="BUILD" Toolchain="">.\Generated_Source\PSoC5\PARITY_EN.h</File>
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<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@General@Warnings as Errors" v="False" />
@ -1495,7 +1659,6 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Difference Tables" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Assembly@General@Create Listing File" v="True" />
@ -1506,6 +1669,7 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM0@Linker@Command Line@Command Line" v="" />
@ -1527,7 +1691,6 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Difference Tables" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Join Data and Text Sections" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Assembly@General@Create Listing File" v="True" />
@ -1538,10 +1701,75 @@
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM0@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Warnings as Errors" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Warning Level" v="High" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Pedantic Compilation" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Preprocessor Definitions" v="DEBUG" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@General@Create Listing File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Optimization Level" v="None" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@General@Create Listing File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Debug@CortexM3@Library Generation@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@General@Output Directory" v="${ProjectDir}\${ProcessorType}\${Platform}\${Config}" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warnings as Errors" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Warning Level" v="High" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Pedantic Compilation" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Preprocessor Definitions" v="NDEBUG" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Default Char Unsigned" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@General@Create Listing File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Optimization Level" v="Size" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Inline Functions" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Optimization@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Struct Return Method" v="System Default" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Code Generation@Verbose Asm" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@C/C++@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Additional Include Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Suppress Warnings" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Generate Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Join Data and Text Sections" v="False" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@General@Create Listing File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Assembly@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Link Files" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Libraries" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Additional Library Directories" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Debugging Information" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Generate Map File" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Default Libs" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Use Nano Lib" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Remove Unused Functions" v="True" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@General@Custom Linker Script" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Linker@Command Line@Command Line" v="" />
<name_val_pair name="c9323d49-d323-40b8-9b59-cc008d68a989@Release@CortexM3@Library Generation@Command Line@Command Line" v="" />
</name>
</platform>
</platforms>
@ -1549,9 +1777,9 @@
<project_current_processor v="CortexM3" />
<component_generation v="PSoC Creator 2.2 Component Pack 6" />
<last_selected_tab v="Cypress" />
<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , CP6) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 2.2SP1) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
<WriteAppVersionLastSavedWith v="2.2.0.572" />
<WriteAppMarketingVersionLastSavedWith v=" 2.2 Component Pack 6" />
<component_dependent_projects_generation v="(69eeda1b-ded5-4da3-a74d-3a98f2d5d4ab , 2.1PR) | (b1a3f413-e018-46a5-a51c-20818b2f118e , 3.0) | (cd381074-8dad-4f43-bb88-7719b3e16126 , 2.1) | (29420278-6fcc-46a7-a651-999ec5c253d2 , 2.1) | (e95576e7-780d-474a-b944-018db0492cc9 , 2.1)" />
<WriteAppVersionLastSavedWith v="3.0.0.1539" />
<WriteAppMarketingVersionLastSavedWith v=" 3.0" />
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<custom_data>
<CyGuid_7a7929f8-5e3b-4f86-a093-2d4ee6513111 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtProjectCustomData" version="1">
@ -1573,7 +1801,8 @@
<CyGuid_b0d670ad-d48f-47cb-9d0b-b1642bab195c type_name="CyDesigner.Common.Base.CyExprTypeMgr" version="1" />
<ignored_deps />
</CyGuid_495451fe-d201-4d01-b22d-5d3f5609ac37>
<boot_component v="cy_boot_v3_40" />
<boot_component v="cy_boot_v4_0" />
<BootloaderTag hexFile="" elfFile="" />
<current_generation v="0" />
</CyGuid_fec8f9e8-2365-4bdb-96d3-a4380222e01b>
</CyXmlSerializer>

31
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD.svd
View File

@ -1,31 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<device schemaVersion="1.0" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD_Schema_1_0.xsd">
<name>CY8C5268AXI_LP047</name>
<version>0.1</version>
<description>CY8C52LP</description>
<addressUnitBits>8</addressUnitBits>
<width>32</width>
<peripherals>
<peripheral>
<name>SD_Clk_Ctl</name>
<description>No description available</description>
<baseAddress>0x40006476</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1</size>
<usage>registers</usage>
</addressBlock>
<registers>
<register>
<name>SD_Clk_Ctl_CONTROL_REG</name>
<description>No description available</description>
<addressOffset>0x0</addressOffset>
<size>8</size>
<access>read-write</access>
<resetValue>0</resetValue>
<resetMask>0</resetMask>
</register>
</registers>
</peripheral>
</peripherals>
</device>

100
software/SCSI2SD/SCSI2SD.cydsn/SCSI2SD_PSoC5lib.uvproj
View File

@ -697,6 +697,56 @@
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
</File>
<File>
<FileName>SCSI_RST_aliases.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
</File>
<File>
<FileName>SCSI_RST.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
</File>
<File>
<FileName>SCSI_RST.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
</File>
<File>
<FileName>SCSI_ATN_aliases.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
</File>
<File>
<FileName>SCSI_ATN.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
</File>
<File>
<FileName>SCSI_ATN.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
</File>
<File>
<FileName>SCSI_RST_ISR.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
</File>
<File>
<FileName>SCSI_RST_ISR.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
</File>
<File>
<FileName>SCSI_ATN_ISR.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
</File>
<File>
<FileName>SCSI_ATN_ISR.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
</File>
</Files>
</Group>
</Groups>
@ -1396,6 +1446,56 @@
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SDCard_PVT.h</FilePath>
</File>
<File>
<FileName>SCSI_RST_aliases.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_aliases.h</FilePath>
</File>
<File>
<FileName>SCSI_RST.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST.c</FilePath>
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<File>
<FileName>SCSI_RST.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST.h</FilePath>
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<FileName>SCSI_ATN_aliases.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_aliases.h</FilePath>
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<File>
<FileName>SCSI_ATN.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN.c</FilePath>
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<File>
<FileName>SCSI_ATN.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN.h</FilePath>
</File>
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<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.c</FilePath>
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<File>
<FileName>SCSI_RST_ISR.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_RST_ISR.h</FilePath>
</File>
<File>
<FileName>SCSI_ATN_ISR.c</FileName>
<FileType>1</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.c</FilePath>
</File>
<File>
<FileName>SCSI_ATN_ISR.h</FileName>
<FileType>5</FileType>
<FilePath>.\Generated_Source\PSoC5\SCSI_ATN_ISR.h</FilePath>
</File>
</Files>
</Group>
</Groups>

BIN
software/SCSI2SD/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
View File

Binary file not shown.

5
software/SCSI2SD/SCSI2SD.cydsn/inquiry.c
View File

@ -30,9 +30,14 @@ static const uint8 StandardResponse[] =
31, // standard length
0, 0, //Reserved
0, // We don't support anything at all
/* TODO testing Apple Drive Setup. Make configurable!
'c','o','d','e','s','r','c',' ',
'S','C','S','I','2','S','D',' ',' ',' ',' ',' ',' ',' ',' ',' ',
'2','.','0','a'
*/
' ','S','E','A','G','A','T','E',
' ',' ',' ',' ',' ',' ',' ',' ',' ',' ','S','T','2','2','5','N',
'1','.','0',' '
};
static const uint8 SupportedVitalPages[] =

29
software/SCSI2SD/SCSI2SD.cydsn/loopback.c
View File

@ -16,6 +16,7 @@
// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
#include "loopback.h"
#include "scsi.h"
#include "device.h"
// Return true if all inputs are un-asserted (1)
@ -27,10 +28,10 @@ static int test_initial_inputs(void)
int result =
(dbx == 0xFF) &&
CyPins_ReadPin(SCSI_In_DBP) &&
CyPins_ReadPin(SCSI_In_ATN) &&
CyPins_ReadPin(SCSI_ATN_INT) &&
CyPins_ReadPin(SCSI_In_BSY) &&
CyPins_ReadPin(SCSI_In_ACK) &&
CyPins_ReadPin(SCSI_In_RST) &&
CyPins_ReadPin(SCSI_RST_INT) &&
CyPins_ReadPin(SCSI_In_MSG) &&
CyPins_ReadPin(SCSI_In_SEL) &&
CyPins_ReadPin(SCSI_In_CD) &&
@ -86,6 +87,25 @@ static int test_data_10MHz(void)
return result;
}
static int test_ATN_interrupt(void)
{
int result = 1;
int i;
scsiDev.atnFlag = 0;
for (i = 0; i < 100 && result; ++i)
{
// We write using Active High
CyPins_SetPin(SCSI_Out_ATN);
CyDelayCycles(2);
result &= scsiDev.atnFlag == 1;
scsiDev.atnFlag = 0;
CyPins_ClearPin(SCSI_Out_ATN);
result &= scsiDev.atnFlag == 0;
}
return result;
}
static void test_error(void)
{
// Toggle LED.
@ -111,7 +131,10 @@ static void test_success(void)
}
void scsi2sd_test_loopback(void)
{
if (!test_initial_inputs() || !test_data_lines() || !test_data_10MHz())
if (!test_initial_inputs() ||
!test_data_lines() ||
!test_data_10MHz() ||
!test_ATN_interrupt())
{
test_error();
}

24
software/SCSI2SD/SCSI2SD.cydsn/main.c
View File

@ -17,25 +17,30 @@
#include "device.h"
// #include "blinky.h"
// #include "loopback.h"
#include "loopback.h"
#include "scsi.h"
#include "scsiPhy.h"
#include "disk.h"
#include "led.h"
const char* Notice = "Copyright (C) 2013 Michael McMaster <michael@codesrc.com>";
void main()
int main()
{
// scsi2sd_test_blinky(); // Initial test. Will not return.
// scsi2sd_test_loopback(); // Second test. Will not return.
ledOff();
/* Uncomment this line to enable global interrupts. */
// MM: Try to avoid interrupts completely, as it will screw with our
// timing.
CyGlobalIntEnable;
// TODO insert any initialisation code here.
// Enable global interrupts.
// Needed for RST and ATN interrupt handlers.
CyGlobalIntEnable;
// Set interrupt handlers.
scsiPhyInit();
// Loopback test requires the interrupt handers.
// Will not return if uncommented.
// scsi2sd_test_loopback();
scsiInit(0, 1); // ID 0 is mac boot disk
scsiDiskInit();
@ -49,5 +54,6 @@ void main()
scsiPoll();
scsiDiskPoll();
}
return 0;
}

16
software/SCSI2SD/SCSI2SD.cydsn/mode.c
View File

@ -93,6 +93,17 @@ static const uint8 ControlModePage[] =
0x00, 0x00 // AEN holdoff period.
};
// Allow Apple 68k Drive Setup to format this drive.
// Code
// TODO make this string configurable.
static const uint8 AppleVendorPage[] =
{
0x30, // Page code
28, // Page length
0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
'A','P','P','L','E',' ','C','O','M','P','U','T','E','R',',',' ','I','N','C','.'
};
static void pageIn(int pc, int dataIdx, const uint8* pageData, int pageLen)
{
memcpy(&scsiDev.data[dataIdx], pageData, pageLen);
@ -235,6 +246,11 @@ static void doModeSense(
idx += sizeof(ControlModePage);
break;
case 0x30:
pageIn(pc, idx, AppleVendorPage, sizeof(AppleVendorPage));
idx += sizeof(AppleVendorPage);
break;
default:
// Unknown Page Code
pageFound = 0;

65
software/SCSI2SD/SCSI2SD.cydsn/scsi.c
View File

@ -66,9 +66,6 @@ static void process_MessageIn()
scsiEnterPhase(MESSAGE_IN);
scsiWrite(scsiDev.msgIn);
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
if (scsiDev.atnFlag)
{
// If there was a parity error, we go
@ -122,9 +119,6 @@ static void process_DataIn()
{
scsiWrite(scsiDev.data[scsiDev.dataPtr]);
++scsiDev.dataPtr;
// scsiWrite will update resetFlag.
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
}
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
@ -157,9 +151,6 @@ static void process_DataOut()
break;
}
++scsiDev.dataPtr;
// scsiRead will update resetFlag.
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
}
if ((scsiDev.dataPtr >= scsiDev.dataLen) &&
@ -268,8 +259,6 @@ static void process_Command()
{
enter_Status(GOOD);
}
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
}
static void doReserveRelease()
@ -342,8 +331,6 @@ static void scsiReset()
SCSI_ClearPin(SCSI_Out_CD);
SCSI_ClearPin(SCSI_Out_IO);
scsiDev.resetFlag = 0;
scsiDev.atnFlag = 0;
scsiDev.parityError = 0;
scsiDev.phase = BUS_FREE;
@ -365,14 +352,18 @@ static void scsiReset()
do
{
CyDelay(10); // 10ms.
reset = SCSI_ReadPin(SCSI_In_RST);
reset = SCSI_ReadPin(SCSI_RST_INT);
} while (reset);
scsiDev.resetFlag = 0;
scsiDev.atnFlag = 0;
}
static void enter_SelectionPhase()
{
scsiDev.atnFlag = 0;
// Ignore stale versions of this flag, but ensure we know the
// current value if the flag is still set.
scsiDev.atnFlag = SCSI_ReadPin(SCSI_ATN_INT);
scsiDev.parityError = 0;
scsiDev.dataPtr = 0;
scsiDev.savedDataPtr = 0;
@ -385,7 +376,6 @@ static void process_SelectionPhase()
uint8 mask = ~SCSI_In_DBx_Read();
int goodParity = (Lookup_OddParity[mask] == SCSI_ReadPin(SCSI_In_DBP));
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
int sel = SCSI_ReadPin(SCSI_In_SEL);
int bsy = SCSI_ReadPin(SCSI_In_BSY);
if (!bsy && sel &&
@ -402,16 +392,12 @@ static void process_SelectionPhase()
ledOn();
// Wait until the end of the selection phase.
// Keep checking the ATN flag, as the initiator may assert it at any
// time before releasing SEL.
while (!scsiDev.resetFlag)
{
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
if (!SCSI_ReadPin(SCSI_In_SEL))
{
break;
}
scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
}
// Save our initiator now that we're no longer in a time-critical
@ -434,15 +420,13 @@ static void process_SelectionPhase()
{
scsiDev.phase = BUS_BUSY;
}
scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);
}
static void process_MessageOut()
{
scsiDev.atnFlag = 0;
scsiEnterPhase(MESSAGE_OUT);
scsiDev.atnFlag = 0;
scsiDev.parityError = 0;
scsiDev.msgOut = scsiRead();
@ -451,10 +435,9 @@ static void process_MessageOut()
// Skip the remaining message bytes, and then start the MESSAGE_OUT
// phase again from the start. The initiator will re-send the
// same set of messages.
while (SCSI_ReadPin(SCSI_In_ATN) && !scsiDev.resetFlag)
while (SCSI_ReadPin(SCSI_ATN_INT) && !scsiDev.resetFlag)
{
scsiRead();
scsiDev.resetFlag = scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST);
}
// Go-back and try the message again.
@ -559,15 +542,30 @@ static void process_MessageOut()
{
enter_MessageIn(MSG_REJECT);
}
// atnFlag will be forced to 1 if there was a parity error.
scsiDev.atnFlag = scsiDev.atnFlag || SCSI_ReadPin(SCSI_In_ATN);
// Re-check the ATN flag. We won't get another interrupt if
// it stays asserted.
scsiDev.atnFlag |= SCSI_ReadPin(SCSI_ATN_INT);
}
// TODO remove.
// This is a hack until I work out why the ATN ISR isn't
// running when it should.
static int atnErrCount = 0;
static void checkATN()
{
int atn = SCSI_ReadPin(SCSI_ATN_INT);
if (atn && !scsiDev.atnFlag)
{
atnErrCount++;
scsiDev.atnFlag = 1;
}
}
void scsiPoll(void)
{
if (scsiDev.resetFlag || SCSI_ReadPin(SCSI_In_RST))
if (scsiDev.resetFlag)
{
scsiReset();
}
@ -607,6 +605,7 @@ void scsiPoll(void)
break;
case COMMAND:
checkATN();
if (scsiDev.atnFlag)
{
process_MessageOut();
@ -618,6 +617,7 @@ void scsiPoll(void)
break;
case DATA_IN:
checkATN();
if (scsiDev.atnFlag)
{
process_MessageOut();
@ -629,6 +629,7 @@ void scsiPoll(void)
break;
case DATA_OUT:
checkATN();
if (scsiDev.atnFlag)
{
process_MessageOut();
@ -636,10 +637,11 @@ void scsiPoll(void)
else
{
process_DataOut();
}
}
break;
case STATUS:
checkATN();
if (scsiDev.atnFlag)
{
process_MessageOut();
@ -651,6 +653,7 @@ void scsiPoll(void)
break;
case MESSAGE_IN:
checkATN();
if (scsiDev.atnFlag)
{
process_MessageOut();

4
software/SCSI2SD/SCSI2SD.cydsn/scsi.h
View File

@ -70,10 +70,10 @@ typedef struct
// Set to true (1) if the ATN flag was set, and we need to
// enter the MESSAGE_OUT phase.
int atnFlag;
volatile int atnFlag;
// Set to true (1) if the RST flag was set.
int resetFlag;
volatile int resetFlag;
// Set to true (1) if a parity error was observed.
int parityError;

60
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.c
View File

@ -20,43 +20,41 @@
#include "scsiPhy.h"
#include "bits.h"
// Spins until the SCSI pin is true, or the reset flag is set.
static void waitForPinTrue(int pin)
CY_ISR_PROTO(scsiResetISR);
CY_ISR(scsiResetISR)
{
while (!scsiDev.resetFlag)
{
// TODO put some hardware gates in front of the RST pin, and store
// the state in a register. The minimum "Reset hold time" is 25us, which
// we can easily satisfy within this loop, but perhaps hard to satisfy
// if we don't call this function often.
scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
scsiDev.resetFlag = 1;
SCSI_RST_ClearInterrupt();
}
if (SCSI_ReadPin(pin))
{
break;
}
CY_ISR_PROTO(scsiAttentionISR);
CY_ISR(scsiAttentionISR)
{
scsiDev.atnFlag = 1;
// Not needed when using pin value for interrupt SCSI_ATN_ClearInterrupt();
}
// Spins until the SCSI pin is true, or the reset flag is set.
static inline void waitForPinTrue(int pin)
{
int finished = SCSI_ReadPin(pin);
while (!finished && !scsiDev.resetFlag)
{
finished = SCSI_ReadPin(pin);
}
}
// Spins until the SCSI pin is true, or the reset flag is set.
static void waitForPinFalse(int pin)
static inline void waitForPinFalse(int pin)
{
while (!scsiDev.resetFlag)
int finished = !SCSI_ReadPin(pin);
while (!finished && !scsiDev.resetFlag)
{
// TODO put some hardware gates in front of the RST pin, and store
// the state in a register. The minimum "Reset hold time" is 25us, which
// we can easily satisfy within this loop, but perhaps hard to satisfy
// if we don't call this function often.
scsiDev.resetFlag = SCSI_ReadPin(SCSI_In_RST);
if (!SCSI_ReadPin(pin))
{
break;
}
finished = !SCSI_ReadPin(pin);
}
}
static void deskewDelay(void)
static inline void deskewDelay(void)
{
// Delay for deskew + cable skew. total 55 nanoseconds.
// Assumes 66MHz.
@ -148,3 +146,13 @@ void scsiEnterPhase(int phase)
busSettleDelay();
}
void scsiPhyInit()
{
SCSI_RST_ISR_StartEx(scsiResetISR);
SCSI_ATN_ISR_StartEx(scsiAttentionISR);
// Interrupts may have already been directed to the (empty)
// standard ISR generated by PSoC Creator.
SCSI_RST_ClearInterrupt();
// Not needed for pin level interrupt SCSI_ATN_ClearInterrupt();
}

1
software/SCSI2SD/SCSI2SD.cydsn/scsiPhy.h
View File

@ -30,6 +30,7 @@
// Contains the odd-parity flag for a given 8-bit value.
extern const uint8 Lookup_OddParity[256];
void scsiPhyInit();
uint8 scsiRead(void);
void scsiWrite(uint8 value);

53
software/SCSI2SD/SCSI2SD.cydsn/sd.c
View File

@ -52,7 +52,7 @@ static uint8 sdSpiByte(uint8 value)
return SDCard_ReadRxData();
}
static void sdSendCommand(uint8 cmd, uint32 param)
static void sdSendCRCCommand(uint8 cmd, uint32 param)
{
uint8 send[6];
@ -69,6 +69,23 @@ static void sdSendCommand(uint8 cmd, uint32 param)
}
}
static void sdSendCommand(uint8 cmd, uint32 param)
{
uint8 send[6];
send[0] = cmd | 0x40;
send[1] = param >> 24;
send[2] = param >> 16;
send[3] = param >> 8;
send[4] = param;
send[5] = 0;
for(cmd = 0; cmd < sizeof(send); cmd++)
{
sdSpiByte(send[cmd]);
}
}
static uint8 sdReadResp()
{
uint8 v;
@ -100,6 +117,14 @@ static uint8 sdCommandAndResponse(uint8 cmd, uint32 param)
return sdReadResp();
}
static uint8 sdCRCCommandAndResponse(uint8 cmd, uint32 param)
{
SDCard_ClearRxBuffer();
sdSpiByte(0xFF);
sdSendCRCCommand(cmd, param);
return sdReadResp();
}
void sdPrepareRead(int nextBlockOffset)
{
@ -197,12 +222,12 @@ int sdWriteSector()
while(!(SDCard_ReadTxStatus() & SDCard_STS_SPI_DONE))
{}
SDCard_ReadRxData();
SDCard_ReadRxData();
SDCard_ReadRxData();
SDCard_ReadRxData();
}
SDCard_ReadRxData();
SDCard_ReadRxData();
SDCard_ReadRxData();
SDCard_ReadRxData();
sdSpiByte(0x00); // CRC
sdSpiByte(0x00); // CRC
@ -260,7 +285,7 @@ static int sendIfCond()
do
{
uint8 status = sdCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
uint8 status = sdCRCCommandAndResponse(SD_SEND_IF_COND, 0x000001AA);
if (status == SD_R1_IDLE)
{
@ -294,9 +319,9 @@ static int sdOpCond()
{
CyDelay(33); // Spec says to retry for 1 second.
sdCommandAndResponse(SD_APP_CMD, 0);
sdCRCCommandAndResponse(SD_APP_CMD, 0);
// Host Capacity Support = 1 (SDHC/SDXC supported)
status = sdCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
status = sdCRCCommandAndResponse(SD_APP_SEND_OP_COND, 0x40000000);
} while ((status != 0) && (--retries > 0));
return retries > 0;
@ -304,7 +329,7 @@ static int sdOpCond()
static int sdReadOCR()
{
uint8 status = sdCommandAndResponse(SD_READ_OCR, 0);
uint8 status = sdCRCCommandAndResponse(SD_READ_OCR, 0);
if(status){goto bad;}
uint8 buf[4];
@ -323,7 +348,7 @@ bad:
static int sdReadCSD()
{
uint8 status = sdCommandAndResponse(SD_SEND_CSD, 0);
uint8 status = sdCRCCommandAndResponse(SD_SEND_CSD, 0);
if(status){goto bad;}
status = sdWaitResp();
if (status != 0xFE) { goto bad; }
@ -389,7 +414,7 @@ int sdInit()
SD_CS_Write(0); // Set CS active (active low)
CyDelayUs(1);
uint8 v = sdCommandAndResponse(SD_GO_IDLE_STATE, 0);
uint8 v = sdCRCCommandAndResponse(SD_GO_IDLE_STATE, 0);
if(v != 1){goto bad;}
if (!sendIfCond()) goto bad; // Sets V1 or V2 flag
@ -398,9 +423,9 @@ int sdInit()
// This command will be ignored if sdDev.ccs is set.
// SDHC and SDXC are always 512bytes.
v = sdCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size
v = sdCRCCommandAndResponse(SD_SET_BLOCKLEN, SCSI_BLOCK_SIZE); //Force sector size
if(v){goto bad;}
v = sdCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
v = sdCRCCommandAndResponse(SD_CRC_ON_OFF, 0); //crc off
if(v){goto bad;}
// now set the sd card up for full speed