diff --git a/CHANGELOG b/CHANGELOG
index ea5ccc8..a7a1ead 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -1,4 +1,4 @@
-20150x0x 4.5
+20151105 4.5
- Fix bug in SCSI MODE SENSE that returned the wrong mode type
- Fixes CDROM emulation
- Added selection delay parameter. This should be set to 1ms for older
diff --git a/readme.txt b/readme.txt
index 3a87917..c6db34c 100644
--- a/readme.txt
+++ b/readme.txt
@@ -111,6 +111,10 @@ Compatibility
1 spare sector per cylinder
2051459 usable sectors on volume
Apollo 400/425s running DOMAIN/OS
+ Motorola System V/68 R3V7 and R3V8.
+ Since the installation have information about limited number of drives(most of them with custom commands) it requires a pre-installed disk image to be dd-ed on it. Works with MVME167 and MVME177
+ Motorola System V/88 R40V4.0 through R40V4.4
+ It requires to describe the disk into a configuration file. The process is described here - http://m88k.com/howto-001.html
Samplers
@@ -134,6 +138,9 @@ Samplers
May require scsi2sd-config --apple flag
Yamaha A5000, A3000, EX5, EX5R
EMU ESI4000
+ Synclavier 9600.
+ Disable Parity. Max size == 9GB.
+
Other
diff --git a/software/SCSI2SD/src/main.c b/software/SCSI2SD/src/main.c
index 992f286..7678394 100755
--- a/software/SCSI2SD/src/main.c
+++ b/software/SCSI2SD/src/main.c
@@ -50,14 +50,20 @@ int main()
// Optional bootup delay
int delaySeconds = 0;
while (delaySeconds < scsiDev.boardCfg.startupDelay) {
- CyDelay(1000);
+ // Keep the USB connection working, otherwise it's very hard to revert
+ // silly extra-long startup delay settings.
+ int i;
+ for (i = 0; i < 200; i++) {
+ CyDelay(5);
+ scsiDev.watchdogTick++;
+ configPoll();
+ }
++delaySeconds;
}
uint32_t lastSDPoll = getTime_ms();
sdCheckPresent();
-
while (1)
{
scsiDev.watchdogTick++;
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index a859ebf..105d7c3 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -391,34 +391,34 @@
#define USBFS_USB__USBIO_CR1 CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B0_UDB07_08_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B0_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B0_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B0_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB07_08_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B0_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B0_UDB07_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B0_UDB07_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B0_UDB07_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B0_UDB07_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB08_09_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB08_09_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB07_08_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB07_08_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB07_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB07_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB07_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -426,9 +426,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB08_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB08_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB08_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB04_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@@ -450,8 +450,8 @@
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@@ -459,9 +459,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B1_UDB07_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B1_UDB07_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB08_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB08_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@@ -1941,15 +1941,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB05_06_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB05_06_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB05_06_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB05_06_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B1_UDB05_06_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B1_UDB05_06_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B1_UDB05_06_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B1_UDB05_06_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB05_06_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1962,37 +1962,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B1_UDB05_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B1_UDB05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B1_UDB05_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B1_UDB05_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B1_UDB05_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B1_UDB05_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B1_UDB05_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB14_15_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB14_15_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB14_15_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB14_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB14_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB14_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB14_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB14_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT6_AG
@@ -2818,8 +2818,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB12_13_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB12_13_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2827,9 +2827,9 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB02_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB02_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB12_MSK
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB12_ACTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2950,8 +2950,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB01_02_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2959,67 +2959,67 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB01_MSK
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB01_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS 0
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS 1
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB11_12_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB11_12_MSK
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB11_12_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB05_06_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB05_06_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB05_06_MSK
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS 2
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB11_ST_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB11_CTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB11_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB05_ST_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB05_CTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB05_ST_CTL
#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK 0x07u
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB11_MSK_ACTL
-#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB11_MSK
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB05_MSK_ACTL
+#define SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB10_11_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB10_11_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB10_11_MSK
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB10_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB10_ST_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB10_CTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB10_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB10_MSK_ACTL
-#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB10_MSK
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB09_10_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB09_10_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB04_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB04_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB09_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB09_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB09_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 815d6a9..721464b 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -122,7 +122,7 @@ static void CyClockStartupError(uint8 errorCode)
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 41u
+#define CY_CFG_BASE_ADDR_COUNT 42u
CYPACKED typedef struct
{
uint8 offset;
@@ -382,43 +382,44 @@ void cyfitter_cfg(void)
0x40004501u, /* Base address: 0x40004500 Count: 1 */
0x40004F02u, /* Base address: 0x40004F00 Count: 2 */
0x4000520Bu, /* Base address: 0x40005200 Count: 11 */
- 0x40006402u, /* Base address: 0x40006400 Count: 2 */
- 0x40010037u, /* Base address: 0x40010000 Count: 55 */
- 0x4001013Cu, /* Base address: 0x40010100 Count: 60 */
- 0x40010245u, /* Base address: 0x40010200 Count: 69 */
+ 0x40006401u, /* Base address: 0x40006400 Count: 1 */
+ 0x40006501u, /* Base address: 0x40006500 Count: 1 */
+ 0x4001003Du, /* Base address: 0x40010000 Count: 61 */
+ 0x40010138u, /* Base address: 0x40010100 Count: 56 */
+ 0x40010248u, /* Base address: 0x40010200 Count: 72 */
0x40010356u, /* Base address: 0x40010300 Count: 86 */
- 0x40010455u, /* Base address: 0x40010400 Count: 85 */
- 0x40010555u, /* Base address: 0x40010500 Count: 85 */
- 0x4001064Bu, /* Base address: 0x40010600 Count: 75 */
- 0x40010756u, /* Base address: 0x40010700 Count: 86 */
- 0x40010922u, /* Base address: 0x40010900 Count: 34 */
- 0x40010A4Eu, /* Base address: 0x40010A00 Count: 78 */
- 0x40010B51u, /* Base address: 0x40010B00 Count: 81 */
- 0x40010C53u, /* Base address: 0x40010C00 Count: 83 */
- 0x40010D59u, /* Base address: 0x40010D00 Count: 89 */
- 0x40010E50u, /* Base address: 0x40010E00 Count: 80 */
- 0x40010F40u, /* Base address: 0x40010F00 Count: 64 */
- 0x40011454u, /* Base address: 0x40011400 Count: 84 */
- 0x40011548u, /* Base address: 0x40011500 Count: 72 */
- 0x4001164Fu, /* Base address: 0x40011600 Count: 79 */
+ 0x40010445u, /* Base address: 0x40010400 Count: 69 */
+ 0x4001054Au, /* Base address: 0x40010500 Count: 74 */
+ 0x4001064Eu, /* Base address: 0x40010600 Count: 78 */
+ 0x4001074Fu, /* Base address: 0x40010700 Count: 79 */
+ 0x40010856u, /* Base address: 0x40010800 Count: 86 */
+ 0x40010954u, /* Base address: 0x40010900 Count: 84 */
+ 0x40010A4Cu, /* Base address: 0x40010A00 Count: 76 */
+ 0x40010B4Bu, /* Base address: 0x40010B00 Count: 75 */
+ 0x40010C51u, /* Base address: 0x40010C00 Count: 81 */
+ 0x40010D56u, /* Base address: 0x40010D00 Count: 86 */
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */
+ 0x40010F42u, /* Base address: 0x40010F00 Count: 66 */
+ 0x4001145Eu, /* Base address: 0x40011400 Count: 94 */
+ 0x4001154Au, /* Base address: 0x40011500 Count: 74 */
+ 0x40011650u, /* Base address: 0x40011600 Count: 80 */
0x4001174Au, /* Base address: 0x40011700 Count: 74 */
- 0x4001184Eu, /* Base address: 0x40011800 Count: 78 */
- 0x40011943u, /* Base address: 0x40011900 Count: 67 */
- 0x40011A04u, /* Base address: 0x40011A00 Count: 4 */
- 0x40011B0Fu, /* Base address: 0x40011B00 Count: 15 */
- 0x40014017u, /* Base address: 0x40014000 Count: 23 */
- 0x4001411Du, /* Base address: 0x40014100 Count: 29 */
- 0x40014215u, /* Base address: 0x40014200 Count: 21 */
- 0x4001430Eu, /* Base address: 0x40014300 Count: 14 */
+ 0x40011804u, /* Base address: 0x40011800 Count: 4 */
+ 0x40011913u, /* Base address: 0x40011900 Count: 19 */
+ 0x40011B0Cu, /* Base address: 0x40011B00 Count: 12 */
+ 0x4001401Bu, /* Base address: 0x40014000 Count: 27 */
+ 0x4001411Au, /* Base address: 0x40014100 Count: 26 */
+ 0x40014213u, /* Base address: 0x40014200 Count: 19 */
+ 0x4001430Au, /* Base address: 0x40014300 Count: 10 */
0x4001440Eu, /* Base address: 0x40014400 Count: 14 */
- 0x40014514u, /* Base address: 0x40014500 Count: 20 */
- 0x40014610u, /* Base address: 0x40014600 Count: 16 */
- 0x40014710u, /* Base address: 0x40014700 Count: 16 */
- 0x40014809u, /* Base address: 0x40014800 Count: 9 */
- 0x4001490Cu, /* Base address: 0x40014900 Count: 12 */
- 0x40014C01u, /* Base address: 0x40014C00 Count: 1 */
- 0x40014D05u, /* Base address: 0x40014D00 Count: 5 */
- 0x40015006u, /* Base address: 0x40015000 Count: 6 */
+ 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */
+ 0x4001460Cu, /* Base address: 0x40014600 Count: 12 */
+ 0x4001470Fu, /* Base address: 0x40014700 Count: 15 */
+ 0x40014807u, /* Base address: 0x40014800 Count: 7 */
+ 0x40014909u, /* Base address: 0x40014900 Count: 9 */
+ 0x40014C03u, /* Base address: 0x40014C00 Count: 3 */
+ 0x40014D03u, /* Base address: 0x40014D00 Count: 3 */
+ 0x40015002u, /* Base address: 0x40015000 Count: 2 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
@@ -426,39 +427,61 @@ void cyfitter_cfg(void)
{0x7Eu, 0x02u},
{0x01u, 0x20u},
{0x0Au, 0x36u},
- {0x00u, 0x13u},
- {0x01u, 0x06u},
+ {0x00u, 0x05u},
+ {0x01u, 0x13u},
{0x18u, 0x08u},
{0x1Cu, 0x71u},
- {0x20u, 0xA0u},
- {0x21u, 0xC8u},
+ {0x20u, 0x50u},
+ {0x21u, 0x90u},
{0x2Cu, 0x0Eu},
- {0x30u, 0x05u},
- {0x31u, 0x03u},
+ {0x30u, 0x0Cu},
+ {0x31u, 0x09u},
{0x34u, 0x80u},
{0x7Cu, 0x40u},
{0x20u, 0x01u},
{0x87u, 0x0Fu},
- {0x06u, 0x07u},
- {0x08u, 0xAAu},
- {0x0Au, 0x55u},
- {0x0Cu, 0x99u},
- {0x0Eu, 0x22u},
- {0x10u, 0x44u},
- {0x12u, 0x88u},
- {0x17u, 0x01u},
- {0x1Au, 0x70u},
- {0x26u, 0x80u},
- {0x2Au, 0x08u},
- {0x31u, 0x01u},
- {0x32u, 0x0Fu},
- {0x34u, 0xF0u},
+ {0x00u, 0x20u},
+ {0x02u, 0x40u},
+ {0x03u, 0x04u},
+ {0x04u, 0x01u},
+ {0x05u, 0x08u},
+ {0x08u, 0x0Au},
+ {0x09u, 0x09u},
+ {0x0Au, 0x35u},
+ {0x0Bu, 0x72u},
+ {0x0Cu, 0x48u},
+ {0x0Eu, 0x36u},
+ {0x10u, 0x07u},
+ {0x11u, 0x01u},
+ {0x12u, 0x18u},
+ {0x13u, 0x66u},
+ {0x14u, 0x4Fu},
+ {0x16u, 0x30u},
+ {0x17u, 0x7Fu},
+ {0x1Bu, 0x01u},
+ {0x1Du, 0x62u},
+ {0x1Eu, 0x02u},
+ {0x21u, 0x20u},
+ {0x22u, 0x20u},
+ {0x23u, 0x40u},
+ {0x24u, 0x05u},
+ {0x25u, 0x74u},
+ {0x27u, 0x09u},
+ {0x29u, 0x20u},
+ {0x2Au, 0x27u},
+ {0x2Bu, 0x40u},
+ {0x30u, 0x1Fu},
+ {0x31u, 0x60u},
+ {0x33u, 0x1Fu},
+ {0x36u, 0x60u},
+ {0x3Au, 0x82u},
+ {0x3Bu, 0x02u},
{0x40u, 0x32u},
{0x41u, 0x04u},
- {0x42u, 0x50u},
- {0x45u, 0xEFu},
- {0x46u, 0xDCu},
- {0x47u, 0x02u},
+ {0x42u, 0x10u},
+ {0x45u, 0x2Du},
+ {0x46u, 0xFCu},
+ {0x47u, 0x0Eu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
@@ -469,7 +492,7 @@ void cyfitter_cfg(void)
{0x59u, 0x04u},
{0x5Au, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x91u},
+ {0x5Cu, 0x11u},
{0x5Du, 0x01u},
{0x5Fu, 0x01u},
{0x60u, 0x08u},
@@ -478,969 +501,1042 @@ void cyfitter_cfg(void)
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
- {0x83u, 0x08u},
+ {0x02u, 0x04u},
+ {0x03u, 0x91u},
+ {0x04u, 0x30u},
+ {0x0Au, 0x80u},
+ {0x0Bu, 0x11u},
+ {0x11u, 0x10u},
+ {0x12u, 0xA8u},
+ {0x1Au, 0x80u},
+ {0x1Bu, 0x80u},
+ {0x20u, 0x30u},
+ {0x23u, 0x90u},
+ {0x28u, 0x48u},
+ {0x2Au, 0x04u},
+ {0x2Bu, 0x10u},
+ {0x32u, 0x88u},
+ {0x33u, 0x11u},
+ {0x38u, 0x10u},
+ {0x3Bu, 0x05u},
+ {0x40u, 0x10u},
+ {0x42u, 0x04u},
+ {0x43u, 0x81u},
+ {0x4Au, 0x20u},
+ {0x4Bu, 0x05u},
+ {0x50u, 0x80u},
+ {0x53u, 0x28u},
+ {0x58u, 0x40u},
+ {0x59u, 0x20u},
+ {0x5Au, 0x02u},
+ {0x5Bu, 0x84u},
+ {0x60u, 0x04u},
+ {0x61u, 0x49u},
+ {0x69u, 0x84u},
+ {0x6Au, 0x20u},
+ {0x6Bu, 0x40u},
+ {0x71u, 0x80u},
+ {0x72u, 0x88u},
+ {0x73u, 0x20u},
+ {0x80u, 0x80u},
+ {0x81u, 0xC0u},
+ {0x85u, 0x04u},
+ {0x8Au, 0x08u},
+ {0x8Eu, 0x10u},
+ {0x8Fu, 0x22u},
+ {0xC0u, 0x0Fu},
+ {0xC2u, 0x0Du},
+ {0xC4u, 0x0Eu},
+ {0xCAu, 0x07u},
+ {0xCCu, 0x0Fu},
+ {0xCEu, 0x07u},
+ {0xD0u, 0x0Fu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE0u, 0x05u},
+ {0xE2u, 0x02u},
+ {0xE4u, 0x03u},
+ {0xE6u, 0x08u},
+ {0x00u, 0x96u},
+ {0x02u, 0x69u},
+ {0x04u, 0x55u},
+ {0x05u, 0x33u},
+ {0x06u, 0xAAu},
+ {0x07u, 0xCCu},
+ {0x0Au, 0xFFu},
+ {0x0Bu, 0xFFu},
+ {0x0Cu, 0x33u},
+ {0x0Du, 0x0Fu},
+ {0x0Eu, 0xCCu},
+ {0x0Fu, 0xF0u},
+ {0x13u, 0xFFu},
+ {0x14u, 0x0Fu},
+ {0x16u, 0xF0u},
+ {0x17u, 0xFFu},
+ {0x18u, 0xFFu},
+ {0x1Du, 0xFFu},
+ {0x1Eu, 0xFFu},
+ {0x25u, 0xFFu},
+ {0x29u, 0x55u},
+ {0x2Au, 0xFFu},
+ {0x2Bu, 0xAAu},
+ {0x2Cu, 0xFFu},
+ {0x2Du, 0x69u},
+ {0x2Fu, 0x96u},
+ {0x32u, 0xFFu},
+ {0x37u, 0xFFu},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x80u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0xE0u},
+ {0x84u, 0x40u},
+ {0x86u, 0x80u},
+ {0x89u, 0x44u},
+ {0x8Au, 0xFFu},
+ {0x8Bu, 0x88u},
+ {0x8Cu, 0x06u},
+ {0x8Eu, 0xF8u},
{0x8Fu, 0x80u},
- {0x93u, 0x70u},
+ {0x91u, 0x99u},
+ {0x93u, 0x22u},
+ {0x94u, 0x01u},
{0x97u, 0x07u},
+ {0x98u, 0xC6u},
+ {0x9Au, 0x19u},
+ {0x9Bu, 0x70u},
+ {0x9Cu, 0x40u},
+ {0x9Eu, 0x80u},
+ {0x9Fu, 0x08u},
+ {0xA0u, 0x14u},
{0xA5u, 0xAAu},
+ {0xA6u, 0x09u},
{0xA7u, 0x55u},
- {0xA9u, 0x44u},
- {0xABu, 0x88u},
- {0xADu, 0x99u},
- {0xAFu, 0x22u},
+ {0xA8u, 0x09u},
+ {0xAAu, 0xF2u},
{0xB3u, 0x0Fu},
- {0xB7u, 0xF0u},
+ {0xB4u, 0x3Fu},
+ {0xB5u, 0xF0u},
+ {0xB6u, 0xC0u},
+ {0xBAu, 0x80u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x10u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x18u},
+ {0x01u, 0x10u},
+ {0x02u, 0x90u},
{0x03u, 0x01u},
- {0x08u, 0x01u},
+ {0x04u, 0x20u},
+ {0x05u, 0x04u},
+ {0x06u, 0x40u},
+ {0x07u, 0x02u},
+ {0x09u, 0x04u},
+ {0x0Au, 0x06u},
+ {0x0Eu, 0x26u},
+ {0x10u, 0x80u},
+ {0x12u, 0x20u},
+ {0x13u, 0x18u},
+ {0x15u, 0x90u},
+ {0x1Au, 0x06u},
+ {0x1Bu, 0x30u},
+ {0x1Eu, 0x20u},
+ {0x21u, 0x20u},
+ {0x22u, 0x04u},
+ {0x24u, 0x02u},
+ {0x25u, 0x40u},
+ {0x2Bu, 0x10u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x21u},
+ {0x31u, 0x20u},
+ {0x32u, 0x04u},
+ {0x33u, 0x41u},
+ {0x36u, 0x89u},
+ {0x37u, 0x01u},
+ {0x38u, 0x20u},
+ {0x3Au, 0x80u},
+ {0x3Du, 0x80u},
+ {0x3Fu, 0x18u},
+ {0x58u, 0x10u},
+ {0x5Bu, 0x80u},
+ {0x5Cu, 0x50u},
+ {0x5Du, 0x09u},
+ {0x60u, 0x08u},
+ {0x62u, 0x40u},
+ {0x63u, 0x08u},
+ {0x65u, 0x80u},
+ {0x81u, 0x08u},
+ {0x82u, 0x40u},
+ {0x83u, 0x80u},
+ {0x85u, 0x20u},
+ {0x87u, 0x08u},
+ {0x89u, 0x20u},
+ {0x8Bu, 0x80u},
+ {0x8Cu, 0x40u},
+ {0x8Eu, 0x04u},
+ {0x90u, 0x20u},
+ {0x91u, 0x10u},
+ {0x93u, 0x10u},
+ {0x94u, 0x04u},
+ {0x96u, 0x06u},
+ {0x98u, 0x04u},
+ {0x9Au, 0x80u},
+ {0x9Bu, 0x42u},
+ {0x9Cu, 0x08u},
+ {0x9Du, 0x61u},
+ {0x9Fu, 0x15u},
+ {0xA0u, 0x80u},
+ {0xA2u, 0x28u},
+ {0xA3u, 0x08u},
+ {0xA5u, 0x08u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x10u},
+ {0xAAu, 0x40u},
+ {0xACu, 0x10u},
+ {0xAEu, 0x04u},
+ {0xB0u, 0x04u},
+ {0xB3u, 0x20u},
+ {0xB6u, 0x28u},
+ {0xC0u, 0xFFu},
+ {0xC2u, 0xE7u},
+ {0xC4u, 0xCEu},
+ {0xCAu, 0x72u},
+ {0xCCu, 0xDFu},
+ {0xCEu, 0x7Cu},
+ {0xD6u, 0xFCu},
+ {0xD8u, 0x1Cu},
+ {0xE0u, 0x08u},
+ {0xE6u, 0x03u},
+ {0xE8u, 0x0Au},
+ {0xEAu, 0x10u},
+ {0xEEu, 0x06u},
+ {0x01u, 0x02u},
+ {0x02u, 0x02u},
+ {0x03u, 0x01u},
+ {0x05u, 0x01u},
+ {0x07u, 0x06u},
+ {0x11u, 0x04u},
+ {0x13u, 0x08u},
+ {0x17u, 0x10u},
+ {0x1Eu, 0x01u},
+ {0x21u, 0x02u},
+ {0x23u, 0x01u},
+ {0x29u, 0x02u},
+ {0x2Bu, 0x01u},
+ {0x2Du, 0x02u},
+ {0x2Fu, 0x29u},
+ {0x30u, 0x01u},
+ {0x31u, 0x20u},
+ {0x33u, 0x03u},
+ {0x34u, 0x02u},
+ {0x35u, 0x10u},
+ {0x37u, 0x0Cu},
+ {0x3Bu, 0x08u},
+ {0x3Fu, 0x40u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x81u, 0x0Du},
+ {0x85u, 0x02u},
+ {0x87u, 0x54u},
+ {0x8Bu, 0x10u},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x02u},
+ {0x8Eu, 0x01u},
+ {0x8Fu, 0x0Du},
+ {0x94u, 0x02u},
+ {0x95u, 0x62u},
+ {0x96u, 0x09u},
+ {0x97u, 0x08u},
+ {0x98u, 0x01u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x02u},
+ {0x9Bu, 0x32u},
+ {0x9Cu, 0x02u},
+ {0x9Eu, 0x05u},
+ {0xA1u, 0x0Du},
+ {0xA5u, 0x0Du},
+ {0xA8u, 0x02u},
+ {0xA9u, 0x0Du},
+ {0xAAu, 0x11u},
+ {0xADu, 0x0Du},
+ {0xB0u, 0x04u},
+ {0xB2u, 0x10u},
+ {0xB4u, 0x03u},
+ {0xB5u, 0x70u},
+ {0xB6u, 0x08u},
+ {0xB7u, 0x0Fu},
+ {0xBAu, 0x20u},
+ {0xBBu, 0x80u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x01u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x06u},
+ {0x03u, 0x20u},
+ {0x04u, 0x40u},
+ {0x0Au, 0x02u},
+ {0x0Eu, 0x1Au},
+ {0x14u, 0x08u},
+ {0x19u, 0x22u},
+ {0x1Cu, 0x40u},
+ {0x1Eu, 0x1Au},
+ {0x20u, 0x01u},
+ {0x21u, 0x45u},
+ {0x22u, 0x91u},
+ {0x25u, 0x50u},
+ {0x28u, 0x02u},
+ {0x29u, 0x22u},
+ {0x2Cu, 0xA8u},
+ {0x2Du, 0x40u},
+ {0x30u, 0x02u},
+ {0x32u, 0x08u},
+ {0x36u, 0x20u},
+ {0x37u, 0x08u},
+ {0x39u, 0x0Au},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0xA0u},
+ {0x3Eu, 0x02u},
+ {0x58u, 0x10u},
+ {0x5Au, 0x84u},
+ {0x5Eu, 0x40u},
+ {0x5Fu, 0x20u},
+ {0x60u, 0x02u},
+ {0x61u, 0x24u},
+ {0x62u, 0x04u},
+ {0x64u, 0x08u},
+ {0x67u, 0x02u},
+ {0x68u, 0x02u},
+ {0x6Du, 0x08u},
+ {0x6Fu, 0x1Au},
+ {0x83u, 0x0Au},
+ {0x84u, 0x10u},
+ {0x85u, 0x08u},
+ {0x86u, 0x04u},
+ {0x8Bu, 0x20u},
+ {0x8Du, 0x10u},
+ {0x90u, 0x22u},
+ {0x92u, 0x80u},
+ {0x94u, 0x14u},
+ {0x95u, 0x89u},
+ {0x97u, 0x02u},
+ {0x98u, 0x04u},
+ {0x9Du, 0x45u},
+ {0x9Eu, 0x30u},
+ {0x9Fu, 0x15u},
+ {0xA2u, 0x10u},
+ {0xA3u, 0x20u},
+ {0xA5u, 0x0Cu},
+ {0xA6u, 0x84u},
+ {0xA7u, 0x80u},
+ {0xABu, 0x18u},
+ {0xACu, 0x10u},
+ {0xAEu, 0x04u},
+ {0xB1u, 0x84u},
+ {0xB3u, 0x01u},
+ {0xC0u, 0x88u},
+ {0xC2u, 0xE1u},
+ {0xC4u, 0x40u},
+ {0xCAu, 0xFDu},
+ {0xCCu, 0x63u},
+ {0xCEu, 0xF3u},
+ {0xD6u, 0x3Eu},
+ {0xD8u, 0x3Eu},
+ {0xE2u, 0x22u},
+ {0xE6u, 0x16u},
+ {0xECu, 0x09u},
+ {0xEEu, 0x06u},
+ {0x00u, 0x02u},
+ {0x02u, 0x01u},
+ {0x05u, 0x34u},
+ {0x07u, 0x08u},
+ {0x09u, 0x01u},
+ {0x0Bu, 0x38u},
+ {0x11u, 0x05u},
+ {0x13u, 0x38u},
+ {0x14u, 0x02u},
+ {0x15u, 0x10u},
+ {0x16u, 0x01u},
+ {0x17u, 0x20u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x01u},
+ {0x1Du, 0x30u},
+ {0x1Eu, 0x02u},
+ {0x1Fu, 0x08u},
+ {0x21u, 0x02u},
+ {0x23u, 0x30u},
+ {0x28u, 0x02u},
+ {0x2Au, 0x01u},
+ {0x2Bu, 0x40u},
+ {0x2Cu, 0x02u},
+ {0x2Du, 0x10u},
+ {0x2Eu, 0x05u},
+ {0x2Fu, 0x20u},
+ {0x32u, 0x04u},
+ {0x33u, 0x40u},
+ {0x35u, 0x30u},
+ {0x36u, 0x03u},
+ {0x37u, 0x0Fu},
+ {0x39u, 0x80u},
+ {0x3Au, 0x80u},
+ {0x3Bu, 0x20u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x81u, 0x01u},
+ {0x82u, 0x3Fu},
+ {0x84u, 0x04u},
+ {0x86u, 0x08u},
+ {0x88u, 0x10u},
+ {0x8Au, 0x20u},
+ {0x8Cu, 0x10u},
+ {0x8Eu, 0x20u},
+ {0x8Fu, 0x01u},
+ {0x90u, 0x04u},
+ {0x92u, 0x08u},
+ {0x95u, 0x01u},
+ {0x98u, 0x01u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x02u},
+ {0x9Cu, 0x01u},
+ {0x9Du, 0x01u},
+ {0x9Eu, 0x02u},
+ {0xA0u, 0x3Fu},
+ {0xA1u, 0x02u},
+ {0xA4u, 0x3Fu},
+ {0xAAu, 0x3Fu},
+ {0xAEu, 0x3Fu},
+ {0xB0u, 0x30u},
+ {0xB1u, 0x01u},
+ {0xB3u, 0x02u},
+ {0xB4u, 0x0Cu},
+ {0xB6u, 0x03u},
+ {0xBAu, 0xA2u},
+ {0xBFu, 0x01u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x91u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x04u},
+ {0x01u, 0x01u},
+ {0x02u, 0x04u},
+ {0x03u, 0x02u},
+ {0x07u, 0x40u},
+ {0x08u, 0x02u},
{0x09u, 0x20u},
- {0x0Au, 0x08u},
- {0x10u, 0x28u},
- {0x18u, 0x20u},
- {0x19u, 0x08u},
- {0x1Au, 0x08u},
- {0x20u, 0x40u},
- {0x26u, 0x88u},
- {0x27u, 0x02u},
- {0x2Du, 0x04u},
+ {0x0Au, 0x01u},
+ {0x0Eu, 0x12u},
+ {0x11u, 0x94u},
+ {0x12u, 0x80u},
+ {0x14u, 0x01u},
+ {0x17u, 0x20u},
+ {0x18u, 0x04u},
+ {0x19u, 0x41u},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0x02u},
+ {0x1Eu, 0x12u},
+ {0x1Fu, 0x84u},
+ {0x21u, 0x01u},
+ {0x22u, 0x04u},
+ {0x25u, 0x40u},
+ {0x27u, 0x25u},
+ {0x2Bu, 0x80u},
+ {0x2Du, 0x01u},
+ {0x2Fu, 0x09u},
+ {0x30u, 0xA8u},
+ {0x36u, 0x80u},
+ {0x37u, 0x15u},
+ {0x38u, 0x20u},
+ {0x39u, 0x50u},
+ {0x3Au, 0x02u},
+ {0x3Du, 0x14u},
+ {0x58u, 0x84u},
+ {0x59u, 0x20u},
+ {0x5Eu, 0x40u},
+ {0x60u, 0x02u},
+ {0x61u, 0x04u},
+ {0x62u, 0x18u},
+ {0x64u, 0x01u},
+ {0x85u, 0x20u},
+ {0x8Bu, 0x01u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x40u},
+ {0x90u, 0x23u},
+ {0x91u, 0x05u},
+ {0x92u, 0x20u},
+ {0x93u, 0x02u},
+ {0x94u, 0x04u},
+ {0x95u, 0x40u},
+ {0x96u, 0x08u},
+ {0x98u, 0x04u},
+ {0x9Au, 0x04u},
+ {0x9Bu, 0x10u},
+ {0x9Du, 0x41u},
+ {0x9Eu, 0x12u},
+ {0x9Fu, 0x0Du},
+ {0xA1u, 0x20u},
+ {0xA2u, 0x90u},
+ {0xA4u, 0xACu},
+ {0xA6u, 0x28u},
+ {0xA7u, 0x80u},
+ {0xAEu, 0x24u},
+ {0xB1u, 0x01u},
+ {0xB4u, 0x11u},
+ {0xB6u, 0x40u},
+ {0xB7u, 0x20u},
+ {0xC0u, 0x1Fu},
+ {0xC2u, 0xABu},
+ {0xC4u, 0xCFu},
+ {0xCAu, 0xB1u},
+ {0xCCu, 0xFEu},
+ {0xCEu, 0x69u},
+ {0xD6u, 0x1Eu},
+ {0xD8u, 0x1Eu},
+ {0xE2u, 0x01u},
+ {0xE6u, 0x03u},
+ {0xEAu, 0x0Bu},
+ {0xEEu, 0x08u},
+ {0x01u, 0x02u},
+ {0x03u, 0x01u},
+ {0x04u, 0x06u},
+ {0x09u, 0x02u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x2Au},
+ {0x0Eu, 0x11u},
+ {0x10u, 0x19u},
+ {0x11u, 0x01u},
+ {0x12u, 0x24u},
+ {0x13u, 0x02u},
+ {0x14u, 0x20u},
+ {0x15u, 0x02u},
+ {0x16u, 0x18u},
+ {0x17u, 0x09u},
+ {0x18u, 0x09u},
+ {0x19u, 0x02u},
+ {0x1Au, 0x32u},
+ {0x1Bu, 0x05u},
+ {0x23u, 0x10u},
+ {0x26u, 0x40u},
+ {0x2Au, 0x80u},
+ {0x2Cu, 0x40u},
{0x2Eu, 0x80u},
- {0x2Fu, 0x28u},
+ {0x31u, 0x08u},
+ {0x32u, 0x38u},
{0x33u, 0x04u},
- {0x35u, 0x04u},
+ {0x34u, 0x07u},
+ {0x35u, 0x10u},
+ {0x36u, 0xC0u},
+ {0x37u, 0x03u},
+ {0x38u, 0x20u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x80u},
+ {0x3Eu, 0x40u},
+ {0x54u, 0x09u},
+ {0x56u, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x10u},
+ {0x5Fu, 0x01u},
+ {0x84u, 0x06u},
+ {0x86u, 0x09u},
+ {0x87u, 0xFFu},
+ {0x88u, 0x05u},
+ {0x89u, 0x50u},
+ {0x8Au, 0x0Au},
+ {0x8Bu, 0xA0u},
+ {0x8Cu, 0x60u},
+ {0x8Eu, 0x90u},
+ {0x90u, 0x0Fu},
+ {0x91u, 0x90u},
+ {0x92u, 0xF0u},
+ {0x93u, 0x60u},
+ {0x94u, 0x50u},
+ {0x95u, 0x30u},
+ {0x96u, 0xA0u},
+ {0x97u, 0xC0u},
+ {0x98u, 0x03u},
+ {0x99u, 0x09u},
+ {0x9Au, 0x0Cu},
+ {0x9Bu, 0x06u},
+ {0x9Du, 0x0Fu},
+ {0x9Fu, 0xF0u},
+ {0xA2u, 0xFFu},
+ {0xA3u, 0xFFu},
+ {0xA4u, 0x30u},
+ {0xA5u, 0x03u},
+ {0xA6u, 0xC0u},
+ {0xA7u, 0x0Cu},
+ {0xA8u, 0xFFu},
+ {0xA9u, 0x05u},
+ {0xABu, 0x0Au},
+ {0xAEu, 0xFFu},
+ {0xAFu, 0xFFu},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0xFFu},
+ {0xBEu, 0x10u},
+ {0xBFu, 0x04u},
+ {0xD4u, 0x01u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDDu, 0x10u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x10u},
+ {0x03u, 0x21u},
+ {0x04u, 0x04u},
+ {0x05u, 0x80u},
+ {0x08u, 0x20u},
+ {0x0Au, 0x80u},
+ {0x0Bu, 0x20u},
+ {0x0Cu, 0x10u},
+ {0x0Eu, 0x20u},
+ {0x0Fu, 0x80u},
+ {0x11u, 0x04u},
+ {0x12u, 0x45u},
+ {0x14u, 0x24u},
+ {0x17u, 0x40u},
+ {0x19u, 0x20u},
+ {0x1Cu, 0x04u},
+ {0x1Eu, 0x22u},
+ {0x1Fu, 0x04u},
+ {0x20u, 0x10u},
+ {0x24u, 0x08u},
+ {0x25u, 0x01u},
+ {0x26u, 0x08u},
+ {0x27u, 0x02u},
+ {0x28u, 0x20u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x41u},
+ {0x2Bu, 0x05u},
+ {0x2Du, 0x02u},
+ {0x30u, 0x04u},
+ {0x32u, 0x44u},
+ {0x33u, 0x61u},
+ {0x35u, 0x10u},
{0x36u, 0x08u},
{0x37u, 0x02u},
- {0x3Du, 0x40u},
- {0x3Eu, 0x02u},
- {0x41u, 0x08u},
- {0x42u, 0x80u},
- {0x43u, 0x29u},
- {0x4Au, 0x50u},
- {0x4Bu, 0x80u},
- {0x50u, 0x80u},
- {0x52u, 0x20u},
- {0x53u, 0x04u},
- {0x5Au, 0x25u},
- {0x5Bu, 0x40u},
- {0x5Du, 0x80u},
- {0x5Eu, 0x0Au},
- {0x5Fu, 0x20u},
- {0x60u, 0x08u},
- {0x61u, 0x40u},
- {0x63u, 0x50u},
- {0x64u, 0x02u},
- {0x69u, 0x61u},
- {0x6Bu, 0x10u},
- {0x70u, 0x28u},
- {0x72u, 0x42u},
- {0x80u, 0x02u},
- {0x81u, 0x02u},
- {0x84u, 0x08u},
- {0x86u, 0x20u},
- {0x8Bu, 0x24u},
- {0x8Eu, 0x10u},
- {0xC0u, 0x07u},
- {0xC2u, 0x0Au},
- {0xC4u, 0x06u},
- {0xCAu, 0x70u},
- {0xCCu, 0xC2u},
- {0xCEu, 0x90u},
- {0xD0u, 0x07u},
- {0xD2u, 0x08u},
- {0xD6u, 0xFFu},
- {0xD8u, 0x1Fu},
- {0xE4u, 0x06u},
- {0xE6u, 0x09u},
- {0x04u, 0x24u},
- {0x05u, 0x01u},
- {0x06u, 0x08u},
- {0x09u, 0x07u},
- {0x0Bu, 0x18u},
- {0x0Cu, 0x01u},
- {0x0Du, 0x2Fu},
- {0x0Eu, 0x02u},
- {0x0Fu, 0x10u},
- {0x13u, 0x07u},
- {0x19u, 0x05u},
- {0x1Au, 0x20u},
- {0x1Eu, 0x1Du},
- {0x23u, 0x20u},
- {0x24u, 0x28u},
- {0x25u, 0x2Au},
- {0x26u, 0x14u},
- {0x27u, 0x15u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x02u},
- {0x2Cu, 0x10u},
- {0x2Du, 0x28u},
- {0x2Eu, 0x20u},
- {0x2Fu, 0x16u},
- {0x31u, 0x20u},
- {0x32u, 0x03u},
- {0x35u, 0x1Fu},
- {0x36u, 0x3Cu},
+ {0x39u, 0x28u},
+ {0x3Au, 0x04u},
{0x3Bu, 0x20u},
+ {0x3Du, 0x02u},
+ {0x3Fu, 0x20u},
+ {0x59u, 0x40u},
+ {0x5Cu, 0x0Au},
+ {0x5Eu, 0x90u},
+ {0x64u, 0x40u},
+ {0x67u, 0x02u},
+ {0x8Bu, 0x04u},
+ {0x8Fu, 0x10u},
+ {0x91u, 0x3Cu},
+ {0x92u, 0x88u},
+ {0x93u, 0x02u},
+ {0x94u, 0x10u},
+ {0x97u, 0x80u},
+ {0x99u, 0x04u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x40u},
+ {0x9Du, 0x20u},
+ {0x9Eu, 0x01u},
+ {0x9Fu, 0x42u},
+ {0xA2u, 0x40u},
+ {0xA3u, 0x25u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0x21u},
+ {0xA7u, 0x40u},
+ {0xAAu, 0x04u},
+ {0xABu, 0x05u},
+ {0xACu, 0x40u},
+ {0xAEu, 0x40u},
+ {0xB2u, 0x01u},
+ {0xB6u, 0x82u},
+ {0xB7u, 0x02u},
+ {0xC0u, 0xA7u},
+ {0xC2u, 0x7Eu},
+ {0xC4u, 0xEFu},
+ {0xCAu, 0x8Fu},
+ {0xCCu, 0xEFu},
+ {0xCEu, 0xA6u},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x90u},
+ {0xE0u, 0x10u},
+ {0xE2u, 0x81u},
+ {0xE6u, 0x43u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0x12u},
+ {0xECu, 0x10u},
+ {0xEEu, 0xC0u},
+ {0x00u, 0x0Fu},
+ {0x02u, 0xF0u},
+ {0x04u, 0x09u},
+ {0x06u, 0x06u},
+ {0x07u, 0xFFu},
+ {0x08u, 0x05u},
+ {0x09u, 0x50u},
+ {0x0Au, 0x0Au},
+ {0x0Bu, 0xA0u},
+ {0x0Cu, 0x90u},
+ {0x0Eu, 0x60u},
+ {0x10u, 0x03u},
+ {0x11u, 0x60u},
+ {0x12u, 0x0Cu},
+ {0x13u, 0x90u},
+ {0x15u, 0x30u},
+ {0x16u, 0xFFu},
+ {0x17u, 0xC0u},
+ {0x18u, 0xFFu},
+ {0x19u, 0x06u},
+ {0x1Bu, 0x09u},
+ {0x1Du, 0x0Fu},
+ {0x1Fu, 0xF0u},
+ {0x23u, 0xFFu},
+ {0x24u, 0x30u},
+ {0x25u, 0x03u},
+ {0x26u, 0xC0u},
+ {0x27u, 0x0Cu},
+ {0x28u, 0x50u},
+ {0x29u, 0x05u},
+ {0x2Au, 0xA0u},
+ {0x2Bu, 0x0Au},
+ {0x2Cu, 0xFFu},
+ {0x2Du, 0xFFu},
+ {0x31u, 0xFFu},
+ {0x32u, 0xFFu},
{0x3Eu, 0x04u},
{0x3Fu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
- {0x5Cu, 0x11u},
{0x5Fu, 0x01u},
- {0x83u, 0x80u},
- {0x86u, 0x04u},
- {0x87u, 0x07u},
- {0x89u, 0xAAu},
- {0x8Au, 0x08u},
- {0x8Bu, 0x55u},
- {0x8Cu, 0x2Au},
- {0x8Eu, 0x54u},
- {0x8Fu, 0x70u},
- {0x95u, 0x99u},
- {0x96u, 0x02u},
- {0x97u, 0x22u},
- {0x9Au, 0x20u},
- {0x9Bu, 0x08u},
- {0x9Eu, 0x10u},
- {0xA6u, 0x01u},
- {0xAAu, 0x40u},
- {0xADu, 0x44u},
- {0xAFu, 0x88u},
- {0xB0u, 0x18u},
- {0xB1u, 0xF0u},
- {0xB2u, 0x01u},
- {0xB3u, 0x0Fu},
- {0xB4u, 0x60u},
- {0xB6u, 0x06u},
- {0xBEu, 0x51u},
+ {0x81u, 0x02u},
+ {0x84u, 0x04u},
+ {0x86u, 0x38u},
+ {0x88u, 0x10u},
+ {0x8Au, 0x20u},
+ {0x8Cu, 0x10u},
+ {0x8Du, 0x05u},
+ {0x8Eu, 0x20u},
+ {0x96u, 0x07u},
+ {0x98u, 0x09u},
+ {0x99u, 0x01u},
+ {0x9Au, 0x32u},
+ {0x9Bu, 0x04u},
+ {0x9Eu, 0x30u},
+ {0xA0u, 0x30u},
+ {0xA1u, 0x01u},
+ {0xA3u, 0x04u},
+ {0xAAu, 0x08u},
+ {0xACu, 0x3Au},
+ {0xAEu, 0x05u},
+ {0xB2u, 0x0Fu},
+ {0xB3u, 0x01u},
+ {0xB4u, 0x30u},
+ {0xB5u, 0x02u},
+ {0xB7u, 0x04u},
+ {0xBAu, 0x20u},
+ {0xBFu, 0x44u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x19u},
+ {0xDCu, 0x91u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x20u},
- {0x01u, 0x40u},
- {0x02u, 0x11u},
- {0x06u, 0x01u},
- {0x07u, 0x20u},
- {0x09u, 0x24u},
- {0x0Bu, 0x02u},
- {0x0Du, 0x10u},
- {0x0Eu, 0x01u},
- {0x11u, 0x02u},
- {0x12u, 0x04u},
- {0x13u, 0x05u},
- {0x14u, 0x05u},
- {0x15u, 0x04u},
- {0x18u, 0x08u},
- {0x19u, 0x0Au},
- {0x1Bu, 0x80u},
- {0x1Eu, 0x11u},
- {0x20u, 0x60u},
- {0x21u, 0x05u},
- {0x25u, 0x11u},
- {0x28u, 0x01u},
- {0x2Cu, 0x80u},
- {0x2Du, 0x04u},
- {0x2Eu, 0x80u},
- {0x2Fu, 0x04u},
- {0x30u, 0x08u},
- {0x33u, 0x10u},
- {0x36u, 0x23u},
- {0x38u, 0x40u},
- {0x39u, 0x19u},
- {0x3Du, 0xA0u},
- {0x3Fu, 0x08u},
- {0x58u, 0x20u},
- {0x5Au, 0x80u},
- {0x5Cu, 0x06u},
- {0x5Eu, 0xA0u},
- {0x61u, 0x10u},
- {0x62u, 0x40u},
- {0x63u, 0x04u},
- {0x67u, 0x01u},
- {0x80u, 0x04u},
- {0x81u, 0x98u},
- {0x84u, 0x20u},
- {0x86u, 0x20u},
- {0x8Au, 0x40u},
- {0x8Bu, 0x40u},
- {0x8Cu, 0x84u},
- {0x8Du, 0x10u},
- {0x8Fu, 0x40u},
- {0x90u, 0x20u},
- {0x91u, 0x35u},
- {0x92u, 0x40u},
- {0x93u, 0x08u},
- {0x96u, 0x04u},
- {0x97u, 0xC0u},
- {0x99u, 0x04u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x01u},
- {0x9Du, 0x82u},
- {0x9Eu, 0x80u},
- {0x9Fu, 0x04u},
- {0xA0u, 0x80u},
- {0xA1u, 0x20u},
- {0xA2u, 0xF0u},
- {0xA5u, 0x08u},
- {0xA6u, 0x05u},
- {0xADu, 0x40u},
- {0xAEu, 0x01u},
- {0xB1u, 0x10u},
- {0xB3u, 0x30u},
- {0xB4u, 0xC0u},
- {0xB7u, 0x40u},
- {0xC0u, 0xA7u},
- {0xC2u, 0xC7u},
- {0xC4u, 0xE6u},
- {0xCAu, 0xF8u},
- {0xCCu, 0xA6u},
- {0xCEu, 0x7Fu},
- {0xD6u, 0xFCu},
- {0xD8u, 0x1Cu},
- {0xE2u, 0x0Cu},
- {0xE4u, 0x04u},
- {0xE6u, 0x2Au},
- {0xEAu, 0x08u},
- {0xEEu, 0x48u},
- {0x00u, 0x40u},
- {0x01u, 0x04u},
- {0x02u, 0x80u},
- {0x05u, 0x30u},
- {0x06u, 0x1Cu},
- {0x07u, 0x05u},
- {0x0Bu, 0x04u},
- {0x0Du, 0x04u},
- {0x0Eu, 0x43u},
+ {0x01u, 0x10u},
+ {0x03u, 0x61u},
+ {0x05u, 0x90u},
+ {0x06u, 0x20u},
+ {0x08u, 0x12u},
+ {0x09u, 0x04u},
+ {0x0Cu, 0x20u},
+ {0x0Eu, 0x21u},
+ {0x10u, 0x09u},
{0x11u, 0x04u},
- {0x12u, 0x20u},
- {0x14u, 0x03u},
- {0x15u, 0x07u},
- {0x16u, 0x40u},
- {0x17u, 0x18u},
- {0x18u, 0x01u},
- {0x19u, 0x04u},
- {0x1Au, 0x02u},
- {0x1Cu, 0x90u},
- {0x1Eu, 0x63u},
- {0x1Fu, 0x08u},
+ {0x14u, 0x10u},
+ {0x15u, 0x08u},
+ {0x16u, 0x8Au},
+ {0x19u, 0x08u},
+ {0x1Du, 0x14u},
+ {0x1Eu, 0x24u},
+ {0x21u, 0x01u},
+ {0x26u, 0x44u},
+ {0x27u, 0x04u},
+ {0x28u, 0x01u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x01u},
+ {0x2Bu, 0x05u},
+ {0x2Fu, 0x40u},
+ {0x32u, 0x44u},
+ {0x33u, 0x21u},
+ {0x36u, 0x20u},
+ {0x39u, 0x28u},
+ {0x3Eu, 0x01u},
+ {0x3Fu, 0x80u},
+ {0x5Cu, 0x80u},
+ {0x66u, 0x40u},
+ {0x68u, 0x88u},
+ {0x69u, 0x24u},
+ {0x6Au, 0x08u},
+ {0x6Bu, 0x01u},
+ {0x71u, 0x60u},
+ {0x72u, 0x50u},
+ {0x79u, 0x10u},
+ {0x7Bu, 0x04u},
+ {0x80u, 0x80u},
+ {0x86u, 0x04u},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x04u},
+ {0x91u, 0x08u},
+ {0x92u, 0x81u},
+ {0x94u, 0x10u},
+ {0x95u, 0x22u},
+ {0x96u, 0x50u},
+ {0x99u, 0x80u},
+ {0x9Au, 0x28u},
+ {0x9Du, 0x68u},
+ {0x9Eu, 0xC2u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x20u},
+ {0xA3u, 0x25u},
+ {0xA4u, 0x80u},
+ {0xA5u, 0x20u},
+ {0xA6u, 0x01u},
+ {0xA8u, 0x81u},
+ {0xAFu, 0x80u},
+ {0xB0u, 0x20u},
+ {0xB1u, 0x08u},
+ {0xC0u, 0xEFu},
+ {0xC2u, 0xEEu},
+ {0xC4u, 0xD7u},
+ {0xCAu, 0x8Fu},
+ {0xCCu, 0x2Fu},
+ {0xCEu, 0x96u},
+ {0xD6u, 0x10u},
+ {0xD8u, 0x10u},
+ {0xE2u, 0x20u},
+ {0xE6u, 0x27u},
+ {0xECu, 0x20u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x03u},
+ {0x04u, 0x10u},
+ {0x06u, 0x23u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x08u},
+ {0x0Cu, 0x2Bu},
+ {0x0Du, 0x0Au},
+ {0x0Eu, 0x14u},
+ {0x0Fu, 0x05u},
+ {0x13u, 0x20u},
+ {0x14u, 0x24u},
+ {0x16u, 0x0Bu},
+ {0x1Au, 0x5Cu},
+ {0x1Bu, 0x17u},
+ {0x1Eu, 0x03u},
{0x20u, 0x01u},
{0x22u, 0x02u},
- {0x23u, 0x02u},
- {0x24u, 0x2Bu},
- {0x26u, 0x54u},
- {0x28u, 0xA4u},
- {0x29u, 0x03u},
- {0x2Au, 0x4Bu},
- {0x2Bu, 0x28u},
- {0x2Du, 0x04u},
- {0x30u, 0xC0u},
- {0x31u, 0x07u},
- {0x32u, 0x3Cu},
- {0x34u, 0x03u},
- {0x35u, 0x07u},
- {0x37u, 0x38u},
- {0x3Au, 0x22u},
- {0x3Bu, 0x33u},
- {0x54u, 0x01u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x01u},
- {0x5Du, 0x10u},
- {0x5Fu, 0x01u},
- {0x81u, 0x05u},
- {0x82u, 0x80u},
- {0x83u, 0x0Au},
- {0x84u, 0x01u},
- {0x86u, 0x12u},
- {0x89u, 0x03u},
- {0x8Bu, 0x0Cu},
- {0x8Cu, 0x04u},
- {0x8Du, 0x0Fu},
- {0x8Eu, 0x28u},
- {0x8Fu, 0xF0u},
- {0x92u, 0x40u},
- {0x93u, 0xFFu},
- {0x9Bu, 0xFFu},
- {0x9Cu, 0x08u},
- {0x9Du, 0x09u},
- {0x9Eu, 0x04u},
- {0x9Fu, 0x06u},
- {0xA0u, 0x02u},
- {0xA2u, 0x01u},
- {0xA3u, 0xFFu},
- {0xA5u, 0x30u},
- {0xA7u, 0xC0u},
- {0xA9u, 0x50u},
- {0xABu, 0xA0u},
- {0xACu, 0x53u},
- {0xADu, 0x90u},
- {0xAEu, 0xACu},
- {0xAFu, 0x60u},
- {0xB0u, 0x0Fu},
- {0xB2u, 0x30u},
- {0xB4u, 0xC0u},
- {0xB5u, 0xFFu},
- {0xBEu, 0x15u},
- {0xBFu, 0x10u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDFu, 0x01u},
- {0x01u, 0x0Au},
- {0x02u, 0x02u},
- {0x05u, 0x04u},
- {0x06u, 0x81u},
- {0x08u, 0x08u},
- {0x09u, 0x40u},
- {0x0Au, 0x44u},
- {0x0Eu, 0x82u},
- {0x11u, 0x04u},
- {0x12u, 0x40u},
- {0x13u, 0x20u},
- {0x15u, 0x42u},
- {0x19u, 0x0Au},
- {0x1Au, 0x04u},
- {0x1Du, 0x19u},
- {0x20u, 0x44u},
- {0x21u, 0x02u},
- {0x22u, 0x50u},
- {0x26u, 0x10u},
- {0x28u, 0x02u},
- {0x29u, 0x20u},
- {0x2Bu, 0x80u},
- {0x2Cu, 0x04u},
- {0x2Eu, 0x82u},
- {0x2Fu, 0x2Au},
- {0x30u, 0x20u},
- {0x32u, 0x44u},
- {0x33u, 0x01u},
- {0x35u, 0x01u},
- {0x36u, 0xE0u},
- {0x38u, 0x84u},
- {0x39u, 0x11u},
- {0x3Cu, 0x20u},
- {0x3Du, 0x40u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x11u},
- {0x5Bu, 0x40u},
- {0x65u, 0x02u},
- {0x67u, 0x80u},
- {0x6Du, 0x40u},
- {0x80u, 0x02u},
- {0x81u, 0x18u},
- {0x84u, 0x08u},
- {0x8Bu, 0x04u},
- {0x8Eu, 0x42u},
- {0x8Fu, 0x04u},
- {0x90u, 0x20u},
- {0x91u, 0x06u},
- {0x92u, 0x41u},
- {0x95u, 0x40u},
- {0x96u, 0x04u},
- {0x97u, 0x80u},
- {0x99u, 0x04u},
- {0x9Au, 0x60u},
- {0x9Bu, 0x60u},
- {0x9Cu, 0x04u},
- {0x9Eu, 0x14u},
- {0x9Fu, 0x04u},
- {0xA0u, 0x10u},
- {0xA1u, 0x60u},
- {0xA2u, 0x80u},
- {0xA6u, 0x06u},
- {0xA7u, 0x24u},
- {0xA8u, 0x02u},
- {0xAAu, 0x30u},
- {0xABu, 0x21u},
- {0xACu, 0x01u},
- {0xADu, 0x48u},
- {0xB3u, 0x80u},
- {0xB4u, 0x18u},
- {0xB5u, 0x04u},
- {0xB6u, 0xC0u},
- {0xB7u, 0x20u},
- {0xC0u, 0xBDu},
- {0xC2u, 0x9Fu},
- {0xC4u, 0x9Eu},
- {0xCAu, 0xFDu},
- {0xCCu, 0xBFu},
- {0xCEu, 0xBFu},
- {0xD6u, 0x08u},
- {0xE2u, 0xD4u},
- {0xE4u, 0x04u},
- {0xE6u, 0x09u},
- {0xE8u, 0x01u},
- {0xEAu, 0x82u},
- {0x00u, 0xFFu},
- {0x07u, 0x02u},
- {0x0Au, 0xFFu},
- {0x0Bu, 0x01u},
- {0x0Du, 0x04u},
- {0x0Eu, 0xFFu},
- {0x10u, 0x60u},
- {0x11u, 0x04u},
- {0x12u, 0x90u},
- {0x14u, 0x03u},
- {0x16u, 0x0Cu},
- {0x19u, 0x04u},
- {0x1Cu, 0x05u},
- {0x1Eu, 0x0Au},
- {0x20u, 0x06u},
- {0x22u, 0x09u},
- {0x24u, 0x50u},
- {0x25u, 0x04u},
- {0x26u, 0xA0u},
- {0x28u, 0x30u},
- {0x2Au, 0xC0u},
- {0x2Cu, 0x0Fu},
- {0x2Eu, 0xF0u},
- {0x33u, 0x01u},
- {0x34u, 0xFFu},
- {0x35u, 0x02u},
- {0x37u, 0x04u},
- {0x39u, 0x80u},
- {0x3Eu, 0x10u},
- {0x3Fu, 0x40u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Cu, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0x04u},
- {0x81u, 0x0Cu},
- {0x84u, 0x09u},
- {0x85u, 0x40u},
- {0x86u, 0x06u},
- {0x87u, 0x30u},
- {0x8Au, 0x06u},
- {0x8Bu, 0x0Cu},
- {0x8Cu, 0x06u},
- {0x8Du, 0x50u},
- {0x8Fu, 0x2Fu},
- {0x90u, 0x02u},
- {0x91u, 0x0Cu},
- {0x94u, 0x01u},
- {0x95u, 0x11u},
- {0x96u, 0x0Eu},
- {0x97u, 0x62u},
- {0x99u, 0x04u},
- {0x9Bu, 0x08u},
- {0x9Cu, 0x06u},
- {0x9Du, 0x0Cu},
- {0xA0u, 0x06u},
- {0xA1u, 0x08u},
- {0xA4u, 0x02u},
- {0xA6u, 0x04u},
- {0xA8u, 0x07u},
- {0xA9u, 0x31u},
- {0xAAu, 0x08u},
- {0xABu, 0x4Eu},
- {0xADu, 0x04u},
- {0xB3u, 0x0Fu},
- {0xB4u, 0x0Fu},
- {0xB5u, 0x70u},
- {0xB8u, 0x20u},
- {0xBBu, 0x20u},
- {0xD6u, 0x02u},
- {0xD7u, 0x24u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x10u},
- {0x03u, 0x81u},
- {0x05u, 0x11u},
- {0x06u, 0x02u},
- {0x08u, 0x02u},
- {0x0Au, 0x21u},
- {0x0Eu, 0x40u},
- {0x0Fu, 0x11u},
- {0x10u, 0xA0u},
- {0x12u, 0x08u},
- {0x14u, 0x18u},
- {0x15u, 0x40u},
- {0x16u, 0x40u},
- {0x18u, 0x04u},
- {0x19u, 0x20u},
- {0x1Au, 0x04u},
- {0x1Fu, 0x10u},
- {0x22u, 0x0Cu},
- {0x23u, 0x04u},
- {0x24u, 0x02u},
- {0x25u, 0x14u},
- {0x27u, 0x04u},
- {0x28u, 0x02u},
- {0x29u, 0x20u},
- {0x2Bu, 0x80u},
- {0x2Eu, 0x40u},
- {0x2Fu, 0x12u},
- {0x30u, 0xA0u},
- {0x32u, 0x04u},
- {0x33u, 0x01u},
- {0x36u, 0x12u},
- {0x38u, 0x40u},
- {0x39u, 0x11u},
- {0x3Bu, 0x04u},
- {0x3Cu, 0x80u},
- {0x3Du, 0x08u},
- {0x3Eu, 0x20u},
- {0x62u, 0xC0u},
- {0x63u, 0x04u},
- {0x68u, 0x21u},
- {0x69u, 0x11u},
- {0x6Au, 0x01u},
- {0x6Bu, 0x01u},
- {0x70u, 0xC0u},
- {0x78u, 0x10u},
- {0x7Bu, 0x08u},
- {0x80u, 0x01u},
- {0x86u, 0x01u},
- {0x88u, 0x20u},
- {0x89u, 0x10u},
- {0x8Cu, 0x80u},
- {0x90u, 0x60u},
- {0x91u, 0x40u},
- {0x92u, 0x20u},
- {0x93u, 0x11u},
- {0x94u, 0x80u},
- {0x95u, 0x11u},
- {0x96u, 0x08u},
- {0x97u, 0x08u},
- {0x98u, 0x02u},
- {0x99u, 0x09u},
- {0x9Au, 0x22u},
- {0x9Du, 0x20u},
- {0x9Eu, 0x15u},
- {0x9Fu, 0x05u},
- {0xA1u, 0x22u},
- {0xA2u, 0x90u},
- {0xA3u, 0x04u},
- {0xA4u, 0x20u},
- {0xA6u, 0x25u},
- {0xA7u, 0xAAu},
- {0xADu, 0x01u},
- {0xB2u, 0x02u},
- {0xB4u, 0x04u},
- {0xC0u, 0xDFu},
- {0xC2u, 0xBDu},
- {0xC4u, 0xFEu},
- {0xCAu, 0x4Du},
- {0xCCu, 0xAFu},
- {0xCEu, 0x7Fu},
- {0xD8u, 0x04u},
- {0xE0u, 0x08u},
- {0xE2u, 0x01u},
- {0xEAu, 0x32u},
- {0xECu, 0x02u},
- {0x81u, 0x40u},
- {0x82u, 0x40u},
- {0x84u, 0x04u},
- {0x85u, 0x01u},
- {0x88u, 0x08u},
- {0x8Au, 0x16u},
- {0x8Eu, 0x01u},
- {0x8Fu, 0x40u},
- {0x90u, 0x20u},
- {0x91u, 0x06u},
- {0x94u, 0x04u},
- {0x95u, 0x01u},
- {0x96u, 0x08u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x40u},
- {0x9Du, 0x08u},
- {0x9Eu, 0x20u},
- {0xA0u, 0x02u},
- {0xA2u, 0x80u},
- {0xA4u, 0x08u},
- {0xA5u, 0x08u},
- {0xA6u, 0x10u},
- {0xA7u, 0x42u},
- {0xABu, 0x04u},
- {0xADu, 0x04u},
- {0xB0u, 0x40u},
- {0xB4u, 0x16u},
- {0xB5u, 0x40u},
- {0xE0u, 0x80u},
- {0xE2u, 0x04u},
- {0xE4u, 0x60u},
- {0xEAu, 0x33u},
- {0xECu, 0x40u},
- {0xEEu, 0x20u},
- {0x00u, 0x08u},
- {0x02u, 0x10u},
- {0x08u, 0x01u},
- {0x0Au, 0x0Au},
- {0x0Cu, 0x02u},
- {0x0Du, 0x01u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x02u},
- {0x14u, 0x02u},
- {0x15u, 0x02u},
- {0x16u, 0x01u},
- {0x17u, 0x01u},
- {0x18u, 0x02u},
- {0x1Au, 0x01u},
- {0x1Du, 0x02u},
- {0x1Fu, 0x01u},
- {0x20u, 0x02u},
- {0x21u, 0x02u},
- {0x22u, 0x11u},
- {0x23u, 0x01u},
- {0x29u, 0x02u},
- {0x2Au, 0x04u},
- {0x2Bu, 0x01u},
- {0x30u, 0x04u},
- {0x31u, 0x03u},
- {0x34u, 0x03u},
- {0x36u, 0x18u},
- {0x3Au, 0x20u},
- {0x3Bu, 0x02u},
- {0x3Eu, 0x40u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x99u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0x10u},
- {0x81u, 0x35u},
- {0x82u, 0x0Cu},
- {0x85u, 0x08u},
- {0x87u, 0x34u},
- {0x89u, 0x0Au},
- {0x8Bu, 0x11u},
- {0x8Cu, 0x10u},
- {0x8Du, 0x35u},
- {0x8Eu, 0x08u},
- {0x91u, 0x02u},
- {0x93u, 0x01u},
- {0x94u, 0x10u},
- {0x95u, 0x05u},
- {0x96u, 0x0Au},
- {0x97u, 0x0Au},
- {0x98u, 0x08u},
- {0x99u, 0x35u},
- {0x9Au, 0x10u},
- {0x9Du, 0x34u},
- {0x9Fu, 0x01u},
- {0xA9u, 0x35u},
- {0xACu, 0x10u},
- {0xADu, 0x0Bu},
- {0xAEu, 0x09u},
- {0xAFu, 0x20u},
- {0xB0u, 0x04u},
- {0xB2u, 0x01u},
- {0xB3u, 0x3Cu},
- {0xB4u, 0x18u},
- {0xB6u, 0x02u},
- {0xB7u, 0x03u},
- {0xBAu, 0x20u},
- {0xBBu, 0x88u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x09u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x00u, 0x02u},
- {0x01u, 0x20u},
- {0x03u, 0x02u},
- {0x04u, 0x41u},
- {0x08u, 0x20u},
- {0x09u, 0x08u},
- {0x0Cu, 0x20u},
- {0x0Eu, 0x14u},
- {0x10u, 0x04u},
- {0x12u, 0x40u},
- {0x14u, 0x01u},
- {0x18u, 0x02u},
- {0x19u, 0xA1u},
- {0x1Bu, 0x80u},
- {0x1Cu, 0x41u},
- {0x1Eu, 0x14u},
- {0x20u, 0x80u},
- {0x21u, 0x01u},
- {0x23u, 0x40u},
- {0x25u, 0x04u},
+ {0x24u, 0x01u},
+ {0x25u, 0x09u},
+ {0x26u, 0x02u},
{0x27u, 0x02u},
- {0x29u, 0x01u},
- {0x2Bu, 0x04u},
- {0x2Cu, 0x0Au},
- {0x30u, 0x04u},
- {0x32u, 0x84u},
- {0x34u, 0x40u},
- {0x35u, 0x08u},
- {0x36u, 0x10u},
- {0x37u, 0x02u},
- {0x3Bu, 0x40u},
- {0x3Du, 0x09u},
- {0x3Eu, 0x20u},
- {0x3Fu, 0x80u},
- {0x58u, 0x10u},
- {0x5Au, 0x40u},
- {0x5Bu, 0x04u},
- {0x5Du, 0x40u},
- {0x60u, 0x02u},
- {0x62u, 0x18u},
- {0x64u, 0x01u},
- {0x68u, 0x01u},
- {0x6Cu, 0x04u},
- {0x6Eu, 0x08u},
- {0x6Fu, 0x01u},
- {0x83u, 0x02u},
- {0x87u, 0x80u},
- {0x88u, 0x10u},
- {0x8Eu, 0x04u},
- {0x92u, 0x40u},
- {0x94u, 0x06u},
- {0x95u, 0x02u},
- {0x97u, 0x40u},
- {0x98u, 0x20u},
- {0x9Au, 0x40u},
- {0x9Cu, 0x02u},
- {0x9Du, 0xA0u},
- {0x9Eu, 0x10u},
- {0x9Fu, 0x01u},
- {0xA2u, 0x80u},
- {0xA3u, 0x04u},
- {0xA4u, 0x60u},
- {0xA6u, 0x0Cu},
- {0xAAu, 0x10u},
- {0xAFu, 0x20u},
- {0xB0u, 0x04u},
- {0xB5u, 0x40u},
- {0xB6u, 0x50u},
- {0xC0u, 0x9Bu},
- {0xC2u, 0x66u},
- {0xC4u, 0x8Au},
- {0xCAu, 0x35u},
- {0xCCu, 0xFAu},
- {0xCEu, 0xF8u},
- {0xD6u, 0x1Eu},
- {0xD8u, 0x1Eu},
- {0xE2u, 0x44u},
- {0xE4u, 0x04u},
- {0xE8u, 0x01u},
- {0xEAu, 0x10u},
- {0xEEu, 0x14u},
- {0x00u, 0xD3u},
- {0x01u, 0x53u},
- {0x02u, 0x20u},
- {0x03u, 0x24u},
- {0x05u, 0x20u},
- {0x08u, 0x01u},
- {0x09u, 0x01u},
- {0x0Au, 0x02u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0xC3u},
- {0x0Eu, 0x20u},
- {0x0Fu, 0x7Fu},
- {0x11u, 0x01u},
- {0x13u, 0x02u},
- {0x14u, 0x04u},
- {0x16u, 0xE3u},
- {0x17u, 0x04u},
- {0x19u, 0x24u},
- {0x1Au, 0x04u},
- {0x1Bu, 0x4Bu},
- {0x1Cu, 0x40u},
- {0x1Eu, 0x80u},
- {0x20u, 0x08u},
- {0x22u, 0xC3u},
- {0x23u, 0x10u},
- {0x24u, 0x40u},
- {0x26u, 0x80u},
- {0x28u, 0x01u},
{0x29u, 0x04u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x1Bu},
- {0x2Cu, 0x14u},
- {0x2Du, 0x0Bu},
- {0x2Eu, 0xE3u},
- {0x32u, 0x3Cu},
- {0x33u, 0x7Cu},
- {0x34u, 0x03u},
- {0x36u, 0xC0u},
- {0x37u, 0x03u},
- {0x38u, 0x08u},
- {0x3Au, 0xA0u},
- {0x3Bu, 0x80u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Cu, 0x11u},
- {0x5Fu, 0x01u},
- {0x83u, 0xFFu},
- {0x85u, 0x69u},
- {0x87u, 0x96u},
- {0x88u, 0x55u},
- {0x8Au, 0xAAu},
- {0x8Cu, 0xFFu},
- {0x90u, 0x33u},
- {0x91u, 0x0Fu},
- {0x92u, 0xCCu},
- {0x93u, 0xF0u},
- {0x96u, 0xFFu},
- {0x97u, 0xFFu},
- {0x98u, 0x0Fu},
- {0x99u, 0x55u},
- {0x9Au, 0xF0u},
- {0x9Bu, 0xAAu},
- {0xA0u, 0xFFu},
- {0xA1u, 0xFFu},
- {0xA4u, 0x96u},
- {0xA5u, 0x33u},
- {0xA6u, 0x69u},
- {0xA7u, 0xCCu},
- {0xAAu, 0xFFu},
- {0xABu, 0xFFu},
- {0xADu, 0xFFu},
- {0xAEu, 0xFFu},
- {0xB1u, 0xFFu},
- {0xB4u, 0xFFu},
- {0xBAu, 0x20u},
- {0xBBu, 0x02u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x01u, 0x90u},
- {0x02u, 0x08u},
- {0x05u, 0x91u},
- {0x08u, 0x02u},
- {0x0Au, 0x14u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x0Au},
- {0x10u, 0x40u},
- {0x13u, 0x64u},
- {0x15u, 0x82u},
- {0x16u, 0x14u},
- {0x17u, 0x10u},
- {0x1Au, 0x04u},
- {0x1Du, 0x10u},
- {0x1Eu, 0x12u},
- {0x1Fu, 0xA8u},
- {0x22u, 0x02u},
- {0x24u, 0x20u},
- {0x25u, 0x0Cu},
- {0x27u, 0x22u},
- {0x28u, 0x40u},
- {0x29u, 0x81u},
- {0x2Au, 0x02u},
- {0x2Bu, 0x18u},
- {0x2Du, 0x82u},
- {0x2Fu, 0x08u},
- {0x31u, 0x08u},
- {0x32u, 0x02u},
- {0x33u, 0x10u},
- {0x36u, 0x04u},
- {0x37u, 0x22u},
- {0x39u, 0x0Au},
- {0x3Cu, 0x80u},
- {0x3Du, 0x10u},
- {0x3Eu, 0x0Au},
- {0x58u, 0x04u},
- {0x5Au, 0x20u},
- {0x5Bu, 0x40u},
- {0x62u, 0x44u},
- {0x63u, 0x04u},
- {0x80u, 0x04u},
- {0x82u, 0x80u},
- {0x83u, 0x40u},
- {0x86u, 0x40u},
- {0x89u, 0x04u},
- {0x8Bu, 0x03u},
- {0x8Du, 0x01u},
- {0x8Fu, 0x04u},
- {0x94u, 0x22u},
- {0x95u, 0x02u},
- {0x96u, 0x14u},
- {0x98u, 0x20u},
- {0x99u, 0x02u},
- {0x9Au, 0x0Au},
- {0x9Cu, 0x02u},
- {0x9Du, 0xA0u},
- {0x9Eu, 0x10u},
- {0xA1u, 0x01u},
- {0xA3u, 0x10u},
- {0xA4u, 0x20u},
- {0xA5u, 0x04u},
- {0xA6u, 0x06u},
- {0xA7u, 0xA0u},
- {0xAAu, 0x40u},
- {0xABu, 0x04u},
- {0xACu, 0x40u},
- {0xADu, 0x20u},
- {0xAEu, 0x04u},
- {0xB2u, 0x02u},
- {0xB3u, 0x0Cu},
- {0xB4u, 0x20u},
- {0xB6u, 0x20u},
- {0xB7u, 0x02u},
- {0xC0u, 0xD3u},
- {0xC2u, 0xEEu},
- {0xC4u, 0xFFu},
- {0xCAu, 0xBFu},
- {0xCCu, 0xE7u},
- {0xCEu, 0xF3u},
- {0xD6u, 0x0Eu},
- {0xD8u, 0x0Eu},
- {0xE0u, 0x40u},
- {0xE2u, 0x30u},
- {0xE4u, 0x80u},
- {0xE6u, 0x2Bu},
- {0xE8u, 0x40u},
- {0xEAu, 0x95u},
- {0xECu, 0x40u},
- {0xEEu, 0x80u},
- {0x01u, 0x3Fu},
- {0x04u, 0x69u},
- {0x05u, 0x3Fu},
- {0x06u, 0x96u},
- {0x08u, 0x0Fu},
- {0x09u, 0x01u},
- {0x0Au, 0xF0u},
- {0x0Bu, 0x02u},
- {0x0Cu, 0xFFu},
- {0x0Fu, 0x3Fu},
- {0x14u, 0x55u},
- {0x16u, 0xAAu},
- {0x17u, 0x3Fu},
- {0x18u, 0xFFu},
- {0x1Bu, 0x3Fu},
- {0x1Cu, 0x33u},
- {0x1Du, 0x10u},
- {0x1Eu, 0xCCu},
- {0x1Fu, 0x20u},
- {0x21u, 0x04u},
- {0x22u, 0xFFu},
- {0x23u, 0x08u},
- {0x25u, 0x10u},
- {0x26u, 0xFFu},
- {0x27u, 0x20u},
- {0x29u, 0x04u},
- {0x2Au, 0xFFu},
+ {0x2Au, 0x80u},
{0x2Bu, 0x08u},
- {0x2Du, 0x01u},
- {0x2Fu, 0x02u},
- {0x32u, 0xFFu},
- {0x33u, 0x0Cu},
- {0x35u, 0x03u},
+ {0x2Cu, 0x40u},
+ {0x2Du, 0x10u},
+ {0x2Eu, 0x80u},
+ {0x2Fu, 0x20u},
+ {0x32u, 0x03u},
+ {0x34u, 0x3Cu},
+ {0x35u, 0x0Fu},
+ {0x36u, 0xC0u},
{0x37u, 0x30u},
{0x3Au, 0x08u},
- {0x3Bu, 0xA8u},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x40u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Fu, 0x01u},
+ {0x81u, 0x10u},
+ {0x84u, 0x06u},
+ {0x85u, 0x01u},
+ {0x86u, 0x09u},
+ {0x87u, 0x02u},
+ {0x89u, 0x10u},
+ {0x8Cu, 0x0Fu},
+ {0x8Du, 0x23u},
+ {0x8Eu, 0xF0u},
+ {0x8Fu, 0x4Cu},
+ {0x90u, 0x30u},
+ {0x92u, 0xC0u},
+ {0x93u, 0x40u},
+ {0x94u, 0x50u},
+ {0x96u, 0xA0u},
+ {0x98u, 0x60u},
+ {0x9Au, 0x90u},
+ {0x9Bu, 0x20u},
+ {0x9Du, 0x08u},
+ {0x9Fu, 0x04u},
+ {0xA1u, 0x02u},
+ {0xA3u, 0x01u},
+ {0xA4u, 0x03u},
+ {0xA5u, 0x10u},
+ {0xA6u, 0x0Cu},
+ {0xA8u, 0x05u},
+ {0xA9u, 0x10u},
+ {0xAAu, 0x0Au},
+ {0xADu, 0x04u},
+ {0xAFu, 0x08u},
+ {0xB0u, 0xFFu},
+ {0xB1u, 0x10u},
+ {0xB3u, 0x0Fu},
+ {0xB5u, 0x60u},
+ {0xB9u, 0x02u},
+ {0xBEu, 0x01u},
+ {0xBFu, 0x15u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x04u},
+ {0x01u, 0x40u},
+ {0x05u, 0x10u},
+ {0x06u, 0xA2u},
+ {0x08u, 0x08u},
+ {0x09u, 0x20u},
+ {0x0Au, 0x50u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x09u},
+ {0x0Fu, 0x08u},
+ {0x12u, 0x18u},
+ {0x13u, 0x08u},
+ {0x14u, 0x10u},
+ {0x15u, 0xA0u},
+ {0x16u, 0x40u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x08u},
+ {0x20u, 0x08u},
+ {0x21u, 0x04u},
+ {0x22u, 0x01u},
+ {0x24u, 0x0Au},
+ {0x26u, 0x20u},
+ {0x28u, 0x01u},
+ {0x29u, 0x68u},
+ {0x2Bu, 0x80u},
+ {0x2Cu, 0x24u},
+ {0x2Du, 0x40u},
+ {0x2Eu, 0x20u},
+ {0x30u, 0x80u},
+ {0x33u, 0x21u},
+ {0x34u, 0x01u},
+ {0x36u, 0x20u},
+ {0x38u, 0x18u},
+ {0x39u, 0xC2u},
+ {0x3Du, 0x80u},
+ {0x3Fu, 0x20u},
+ {0x5Cu, 0x80u},
+ {0x5Du, 0x05u},
+ {0x5Eu, 0x20u},
+ {0x64u, 0x02u},
+ {0x78u, 0x02u},
+ {0x7Au, 0x80u},
+ {0x84u, 0x10u},
+ {0x85u, 0x01u},
+ {0x87u, 0x08u},
+ {0x88u, 0x05u},
+ {0x8Bu, 0x08u},
+ {0x90u, 0x04u},
+ {0x91u, 0x84u},
+ {0x92u, 0x81u},
+ {0x96u, 0x42u},
+ {0x98u, 0x04u},
+ {0x99u, 0x90u},
+ {0x9Au, 0x08u},
+ {0x9Cu, 0x08u},
+ {0x9Eu, 0x10u},
+ {0xA1u, 0x40u},
+ {0xA2u, 0x98u},
+ {0xA3u, 0x30u},
+ {0xA4u, 0xA0u},
+ {0xA5u, 0x28u},
+ {0xA6u, 0x01u},
+ {0xA7u, 0x80u},
+ {0xAAu, 0x01u},
+ {0xABu, 0x01u},
+ {0xACu, 0x04u},
+ {0xADu, 0x41u},
+ {0xAEu, 0x05u},
+ {0xB2u, 0x10u},
+ {0xB4u, 0x80u},
+ {0xB7u, 0x40u},
+ {0xC0u, 0xF5u},
+ {0xC2u, 0xEEu},
+ {0xC4u, 0xF6u},
+ {0xCAu, 0x7Fu},
+ {0xCCu, 0xADu},
+ {0xCEu, 0x3Fu},
+ {0xD6u, 0xF0u},
+ {0xD8u, 0x10u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x21u},
+ {0xE8u, 0x80u},
+ {0xECu, 0x09u},
+ {0xEEu, 0xC0u},
+ {0x00u, 0x80u},
+ {0x02u, 0x40u},
+ {0x06u, 0x1Cu},
+ {0x0Cu, 0x80u},
+ {0x0Du, 0x0Au},
+ {0x0Eu, 0x41u},
+ {0x0Fu, 0x14u},
+ {0x14u, 0x24u},
+ {0x16u, 0x08u},
+ {0x18u, 0x80u},
+ {0x1Au, 0x40u},
+ {0x1Bu, 0x04u},
+ {0x1Cu, 0x40u},
+ {0x1Eu, 0x80u},
+ {0x1Fu, 0x10u},
+ {0x20u, 0x80u},
+ {0x22u, 0x42u},
+ {0x23u, 0x08u},
+ {0x26u, 0x20u},
+ {0x27u, 0x02u},
+ {0x28u, 0x10u},
+ {0x2Au, 0x20u},
+ {0x2Cu, 0x28u},
+ {0x2Eu, 0x14u},
+ {0x2Fu, 0x01u},
+ {0x30u, 0x01u},
+ {0x31u, 0x01u},
+ {0x32u, 0x3Cu},
+ {0x33u, 0x18u},
+ {0x34u, 0x02u},
+ {0x36u, 0xC0u},
+ {0x37u, 0x06u},
+ {0x3Au, 0x80u},
+ {0x3Fu, 0x44u},
{0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
@@ -1448,144 +1544,141 @@ void cyfitter_cfg(void)
{0x5Cu, 0x11u},
{0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x80u, 0xE0u},
- {0x83u, 0x70u},
- {0x84u, 0x14u},
- {0x85u, 0x40u},
- {0x87u, 0x1Fu},
- {0x88u, 0x09u},
- {0x89u, 0x10u},
- {0x8Au, 0xF2u},
- {0x8Bu, 0x2Fu},
- {0x91u, 0x03u},
- {0x92u, 0x09u},
- {0x93u, 0x0Cu},
- {0x94u, 0x06u},
- {0x95u, 0x0Fu},
- {0x96u, 0xF8u},
- {0x98u, 0x40u},
- {0x99u, 0x20u},
- {0x9Au, 0x80u},
- {0x9Bu, 0x4Fu},
- {0x9Cu, 0x40u},
- {0x9Eu, 0x80u},
- {0xA2u, 0xFFu},
- {0xA5u, 0x06u},
- {0xA7u, 0x09u},
- {0xA8u, 0x01u},
- {0xA9u, 0x05u},
- {0xABu, 0x0Au},
- {0xACu, 0xC6u},
- {0xAEu, 0x19u},
- {0xB1u, 0x7Fu},
- {0xB2u, 0x3Fu},
- {0xB4u, 0xC0u},
- {0xBAu, 0x20u},
+ {0x81u, 0x44u},
+ {0x83u, 0x08u},
+ {0x86u, 0x10u},
+ {0x87u, 0x17u},
+ {0x8Bu, 0x40u},
+ {0x8Cu, 0x0Au},
+ {0x8Du, 0x4Au},
+ {0x8Eu, 0x05u},
+ {0x8Fu, 0x05u},
+ {0x91u, 0x10u},
+ {0x92u, 0x20u},
+ {0x93u, 0x20u},
+ {0x94u, 0x09u},
+ {0x96u, 0x02u},
+ {0x97u, 0x20u},
+ {0x9Au, 0x07u},
+ {0xA0u, 0x04u},
+ {0xA2u, 0x08u},
+ {0xA5u, 0x49u},
+ {0xA7u, 0x02u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x08u},
+ {0xACu, 0x10u},
+ {0xAEu, 0x20u},
+ {0xB0u, 0x30u},
+ {0xB1u, 0x30u},
+ {0xB3u, 0x0Fu},
+ {0xB4u, 0x0Fu},
+ {0xB7u, 0x40u},
+ {0xBEu, 0x01u},
+ {0xBFu, 0x41u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
+ {0xDBu, 0x04u},
{0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x01u, 0x80u},
- {0x02u, 0x10u},
- {0x03u, 0x08u},
- {0x04u, 0x22u},
- {0x05u, 0x10u},
- {0x06u, 0x20u},
- {0x08u, 0x08u},
- {0x0Bu, 0x09u},
- {0x0Cu, 0x08u},
- {0x0Du, 0x20u},
- {0x0Eu, 0x90u},
- {0x0Fu, 0x02u},
- {0x10u, 0x08u},
- {0x11u, 0x08u},
- {0x12u, 0x40u},
- {0x14u, 0x04u},
- {0x15u, 0x02u},
- {0x16u, 0x42u},
- {0x1Bu, 0x08u},
- {0x1Du, 0x20u},
- {0x1Eu, 0x20u},
- {0x1Fu, 0x04u},
- {0x21u, 0x10u},
- {0x22u, 0x44u},
- {0x23u, 0x0Au},
- {0x25u, 0x01u},
- {0x28u, 0x4Au},
- {0x2Bu, 0x10u},
- {0x2Eu, 0x04u},
- {0x2Fu, 0x08u},
- {0x30u, 0x08u},
- {0x31u, 0x10u},
- {0x32u, 0x40u},
- {0x34u, 0x04u},
- {0x36u, 0x16u},
- {0x38u, 0x02u},
- {0x39u, 0x20u},
- {0x3Au, 0x40u},
- {0x3Bu, 0x08u},
- {0x3Du, 0x0Au},
- {0x3Eu, 0x10u},
- {0x58u, 0x10u},
- {0x5Au, 0x40u},
- {0x5Bu, 0x04u},
- {0x60u, 0x08u},
- {0x63u, 0x23u},
- {0x81u, 0x20u},
- {0x86u, 0x48u},
- {0x87u, 0x80u},
- {0x88u, 0x30u},
- {0x89u, 0x02u},
- {0x8Fu, 0x20u},
- {0xC0u, 0x77u},
- {0xC2u, 0xF7u},
- {0xC4u, 0xDEu},
- {0xCAu, 0x6Fu},
- {0xCCu, 0xEEu},
- {0xCEu, 0xEFu},
- {0xD6u, 0x0Eu},
- {0xD8u, 0x0Eu},
- {0xE0u, 0x80u},
- {0xE2u, 0x40u},
- {0xE4u, 0x04u},
- {0xE6u, 0x20u},
- {0x02u, 0x02u},
- {0x06u, 0x30u},
- {0x08u, 0x04u},
+ {0x00u, 0x84u},
+ {0x01u, 0x08u},
+ {0x02u, 0x40u},
+ {0x04u, 0x40u},
+ {0x06u, 0x10u},
{0x09u, 0x08u},
- {0x0Au, 0x08u},
- {0x0Bu, 0x22u},
- {0x0Cu, 0x01u},
- {0x0Eu, 0x02u},
- {0x10u, 0x20u},
- {0x11u, 0x14u},
- {0x12u, 0x0Cu},
- {0x13u, 0x08u},
- {0x14u, 0x10u},
- {0x15u, 0x09u},
- {0x16u, 0x0Cu},
- {0x17u, 0x10u},
- {0x19u, 0x37u},
- {0x1Au, 0x01u},
- {0x1Eu, 0x04u},
- {0x27u, 0x07u},
- {0x2Au, 0x48u},
- {0x30u, 0x03u},
- {0x34u, 0x3Cu},
- {0x35u, 0x38u},
- {0x36u, 0x40u},
- {0x37u, 0x07u},
- {0x39u, 0x20u},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
- {0x40u, 0x24u},
+ {0x0Au, 0x05u},
+ {0x0Du, 0x08u},
+ {0x0Eu, 0x48u},
+ {0x10u, 0x54u},
+ {0x11u, 0x80u},
+ {0x15u, 0x85u},
+ {0x16u, 0x24u},
+ {0x19u, 0x0Au},
+ {0x1Au, 0x05u},
+ {0x1Bu, 0x40u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x21u},
+ {0x20u, 0x82u},
+ {0x22u, 0x04u},
+ {0x25u, 0x06u},
+ {0x26u, 0x88u},
+ {0x29u, 0x08u},
+ {0x2Au, 0x40u},
+ {0x2Bu, 0x80u},
+ {0x2Cu, 0x60u},
+ {0x2Du, 0x02u},
+ {0x2Eu, 0x10u},
+ {0x30u, 0x80u},
+ {0x31u, 0x20u},
+ {0x34u, 0x08u},
+ {0x37u, 0x01u},
+ {0x39u, 0x80u},
+ {0x3Cu, 0x40u},
+ {0x3Du, 0x89u},
+ {0x3Eu, 0x20u},
+ {0x58u, 0x80u},
+ {0x5Du, 0x40u},
+ {0x62u, 0x40u},
+ {0x64u, 0x02u},
+ {0x65u, 0x80u},
+ {0x69u, 0x80u},
+ {0x6Au, 0x80u},
+ {0x6Bu, 0x01u},
+ {0x81u, 0x40u},
+ {0x82u, 0x24u},
+ {0x83u, 0x10u},
+ {0x84u, 0x01u},
+ {0x85u, 0x02u},
+ {0x86u, 0x08u},
+ {0x88u, 0x10u},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x10u},
+ {0x8Eu, 0x10u},
+ {0xC0u, 0xADu},
+ {0xC2u, 0x77u},
+ {0xC4u, 0xDFu},
+ {0xCAu, 0x6Bu},
+ {0xCCu, 0xCCu},
+ {0xCEu, 0xF8u},
+ {0xD6u, 0x18u},
+ {0xD8u, 0x18u},
+ {0xE0u, 0x60u},
+ {0xE2u, 0x10u},
+ {0xE4u, 0x10u},
+ {0xE6u, 0x04u},
+ {0x01u, 0x5Cu},
+ {0x05u, 0x11u},
+ {0x07u, 0x22u},
+ {0x09u, 0x50u},
+ {0x0Bu, 0x0Cu},
+ {0x0Du, 0x0Cu},
+ {0x0Fu, 0x50u},
+ {0x15u, 0x30u},
+ {0x17u, 0x0Fu},
+ {0x19u, 0x54u},
+ {0x1Bu, 0x08u},
+ {0x1Du, 0x5Cu},
+ {0x21u, 0x08u},
+ {0x27u, 0x40u},
+ {0x29u, 0x21u},
+ {0x2Bu, 0x1Eu},
+ {0x2Du, 0x24u},
+ {0x2Fu, 0x10u},
+ {0x31u, 0x30u},
+ {0x33u, 0x40u},
+ {0x35u, 0x0Fu},
+ {0x3Bu, 0x02u},
+ {0x3Fu, 0x04u},
+ {0x40u, 0x23u},
{0x41u, 0x06u},
- {0x42u, 0x30u},
+ {0x42u, 0x40u},
{0x44u, 0x01u},
- {0x45u, 0xFEu},
- {0x46u, 0xDCu},
- {0x47u, 0x0Bu},
- {0x48u, 0x1Fu},
+ {0x45u, 0xBDu},
+ {0x46u, 0xF0u},
+ {0x47u, 0xCEu},
+ {0x48u, 0x3Bu},
{0x49u, 0xFFu},
{0x4Au, 0xFFu},
{0x4Bu, 0xFFu},
@@ -1593,9 +1686,11 @@ void cyfitter_cfg(void)
{0x4Eu, 0xF0u},
{0x4Fu, 0x08u},
{0x50u, 0x04u},
- {0x58u, 0x04u},
+ {0x54u, 0x40u},
+ {0x56u, 0x04u},
{0x59u, 0x04u},
{0x5Au, 0x04u},
+ {0x5Bu, 0x04u},
{0x5Fu, 0x01u},
{0x62u, 0xC0u},
{0x64u, 0x40u},
@@ -1609,605 +1704,481 @@ void cyfitter_cfg(void)
{0x6Du, 0x01u},
{0x6Eu, 0x40u},
{0x6Fu, 0x01u},
- {0x81u, 0x02u},
- {0x83u, 0x09u},
- {0x8Du, 0x02u},
- {0x8Fu, 0x01u},
- {0x91u, 0x02u},
- {0x93u, 0x11u},
- {0x95u, 0x02u},
- {0x97u, 0x05u},
- {0x99u, 0x01u},
+ {0x80u, 0x20u},
+ {0x82u, 0x01u},
+ {0x84u, 0x10u},
+ {0x85u, 0x04u},
+ {0x86u, 0x42u},
+ {0x87u, 0x23u},
+ {0x89u, 0x48u},
+ {0x8Bu, 0x03u},
+ {0x8Cu, 0x02u},
+ {0x90u, 0x02u},
+ {0x91u, 0x80u},
+ {0x94u, 0x44u},
+ {0x96u, 0x10u},
+ {0x97u, 0x7Cu},
+ {0x98u, 0x02u},
+ {0x99u, 0x11u},
{0x9Bu, 0x02u},
- {0xA8u, 0x01u},
- {0xB1u, 0x10u},
- {0xB2u, 0x01u},
- {0xB3u, 0x03u},
- {0xB5u, 0x08u},
- {0xB7u, 0x04u},
- {0xBBu, 0x08u},
- {0xD6u, 0x08u},
+ {0x9Cu, 0x02u},
+ {0xA0u, 0x08u},
+ {0xA3u, 0x02u},
+ {0xA5u, 0x80u},
+ {0xA8u, 0x0Eu},
+ {0xA9u, 0x70u},
+ {0xAAu, 0x30u},
+ {0xACu, 0x02u},
+ {0xAFu, 0x01u},
+ {0xB0u, 0x01u},
+ {0xB3u, 0x70u},
+ {0xB4u, 0x7Eu},
+ {0xB5u, 0x0Fu},
+ {0xB7u, 0x80u},
+ {0xB8u, 0x20u},
+ {0xB9u, 0x80u},
+ {0xBEu, 0x10u},
+ {0xBFu, 0x04u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x99u},
- {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x04u},
- {0x01u, 0x40u},
- {0x02u, 0x08u},
- {0x03u, 0x40u},
- {0x08u, 0x28u},
- {0x09u, 0x02u},
- {0x0Au, 0x02u},
- {0x10u, 0x08u},
- {0x17u, 0x20u},
- {0x18u, 0x04u},
- {0x19u, 0x01u},
- {0x1Au, 0x02u},
- {0x1Bu, 0x10u},
- {0x1Fu, 0x04u},
- {0x21u, 0x40u},
- {0x22u, 0x10u},
- {0x24u, 0x40u},
- {0x26u, 0x04u},
- {0x27u, 0x2Au},
- {0x2Bu, 0x10u},
- {0x31u, 0x02u},
- {0x32u, 0x18u},
- {0x37u, 0x2Au},
- {0x39u, 0x20u},
- {0x3Cu, 0x40u},
- {0x3Fu, 0x01u},
- {0x40u, 0x0Au},
- {0x41u, 0x12u},
- {0x42u, 0x14u},
- {0x49u, 0x04u},
- {0x4Au, 0x88u},
- {0x50u, 0x08u},
- {0x53u, 0x90u},
- {0x5Cu, 0x80u},
- {0x67u, 0x01u},
- {0x6Eu, 0x02u},
- {0x6Fu, 0x2Au},
- {0x76u, 0x25u},
- {0x77u, 0x40u},
- {0x84u, 0x88u},
- {0x8Au, 0x80u},
+ {0x04u, 0x04u},
+ {0x05u, 0x02u},
+ {0x06u, 0x02u},
+ {0x0Cu, 0xA1u},
+ {0x0Du, 0x08u},
+ {0x0Fu, 0x40u},
+ {0x15u, 0x60u},
+ {0x17u, 0x02u},
+ {0x1Fu, 0x22u},
+ {0x20u, 0x18u},
+ {0x21u, 0x10u},
+ {0x22u, 0x20u},
+ {0x23u, 0x44u},
+ {0x26u, 0x84u},
+ {0x27u, 0x0Au},
+ {0x28u, 0x01u},
+ {0x29u, 0x04u},
+ {0x2Au, 0x01u},
+ {0x2Bu, 0x04u},
+ {0x2Du, 0x02u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x22u},
+ {0x30u, 0xA0u},
+ {0x31u, 0x08u},
+ {0x36u, 0x21u},
+ {0x37u, 0x08u},
+ {0x39u, 0x50u},
+ {0x3Au, 0x02u},
+ {0x3Bu, 0x04u},
+ {0x3Cu, 0x24u},
+ {0x40u, 0x04u},
+ {0x41u, 0x09u},
+ {0x42u, 0x01u},
+ {0x48u, 0x04u},
+ {0x49u, 0x06u},
+ {0x51u, 0x20u},
+ {0x52u, 0x01u},
+ {0x53u, 0x04u},
+ {0x60u, 0x92u},
+ {0x61u, 0x20u},
+ {0x82u, 0x20u},
+ {0x84u, 0x04u},
+ {0x86u, 0x01u},
{0x8Cu, 0x02u},
- {0x8Du, 0x41u},
- {0x91u, 0x40u},
- {0x92u, 0x14u},
- {0x97u, 0x28u},
- {0x98u, 0x20u},
- {0x9Du, 0x04u},
- {0x9Eu, 0x25u},
- {0x9Fu, 0x40u},
- {0xA1u, 0x02u},
- {0xA2u, 0x08u},
- {0xA6u, 0x05u},
- {0xA7u, 0xAAu},
- {0xAAu, 0x10u},
- {0xABu, 0x80u},
- {0xB2u, 0x04u},
- {0xB5u, 0x08u},
- {0xB6u, 0x01u},
- {0xC0u, 0x0Fu},
- {0xC2u, 0x0Fu},
- {0xC4u, 0x42u},
- {0xCAu, 0x02u},
- {0xCCu, 0xE7u},
- {0xCEu, 0x94u},
+ {0x8Du, 0x04u},
+ {0x8Eu, 0x04u},
+ {0x90u, 0x04u},
+ {0x91u, 0x52u},
+ {0x97u, 0x48u},
+ {0x9Au, 0x02u},
+ {0x9Cu, 0x80u},
+ {0x9Du, 0x02u},
+ {0x9Eu, 0x01u},
+ {0xA0u, 0xB0u},
+ {0xA1u, 0x08u},
+ {0xA2u, 0x01u},
+ {0xA3u, 0x04u},
+ {0xA6u, 0xA0u},
+ {0xABu, 0x01u},
+ {0xB2u, 0x08u},
+ {0xB3u, 0x20u},
+ {0xB4u, 0x04u},
+ {0xC0u, 0xB0u},
+ {0xC2u, 0xF0u},
+ {0xC4u, 0xD0u},
+ {0xCAu, 0xFFu},
+ {0xCCu, 0xEEu},
+ {0xCEu, 0x6Fu},
{0xD0u, 0x0Fu},
{0xD2u, 0x04u},
- {0xD6u, 0x10u},
- {0xD8u, 0x10u},
- {0xE0u, 0x12u},
- {0xE6u, 0x52u},
- {0xEAu, 0x04u},
- {0x00u, 0x0Fu},
- {0x01u, 0x05u},
- {0x02u, 0xF0u},
- {0x03u, 0x0Au},
+ {0xD8u, 0x0Fu},
+ {0xE2u, 0x44u},
+ {0xE4u, 0x02u},
+ {0xE8u, 0x01u},
+ {0x00u, 0x03u},
+ {0x01u, 0xC0u},
+ {0x02u, 0x0Cu},
+ {0x03u, 0x01u},
+ {0x04u, 0x05u},
+ {0x06u, 0x0Au},
{0x07u, 0xFFu},
- {0x08u, 0xFFu},
- {0x09u, 0x03u},
- {0x0Bu, 0x0Cu},
- {0x0Cu, 0x60u},
- {0x0Du, 0x0Fu},
- {0x0Eu, 0x90u},
- {0x0Fu, 0xF0u},
- {0x11u, 0xFFu},
- {0x12u, 0xFFu},
- {0x14u, 0x03u},
- {0x16u, 0x0Cu},
- {0x19u, 0xFFu},
- {0x1Au, 0xFFu},
- {0x1Cu, 0x05u},
- {0x1Du, 0x09u},
- {0x1Eu, 0x0Au},
- {0x1Fu, 0x06u},
- {0x20u, 0x06u},
- {0x22u, 0x09u},
- {0x24u, 0x30u},
- {0x25u, 0x30u},
- {0x26u, 0xC0u},
- {0x27u, 0xC0u},
- {0x28u, 0x50u},
- {0x29u, 0x50u},
- {0x2Au, 0xA0u},
- {0x2Bu, 0xA0u},
+ {0x08u, 0x40u},
+ {0x09u, 0xC0u},
+ {0x0Au, 0x1Fu},
+ {0x0Bu, 0x08u},
+ {0x0Cu, 0x10u},
+ {0x0Du, 0x80u},
+ {0x0Eu, 0x2Fu},
+ {0x13u, 0x9Fu},
+ {0x14u, 0x06u},
+ {0x15u, 0x7Fu},
+ {0x16u, 0x09u},
+ {0x17u, 0x80u},
+ {0x19u, 0x1Fu},
+ {0x1Au, 0x70u},
+ {0x1Bu, 0x20u},
+ {0x1Fu, 0x60u},
+ {0x21u, 0xC0u},
+ {0x23u, 0x02u},
+ {0x24u, 0x20u},
+ {0x25u, 0xC0u},
+ {0x26u, 0x4Fu},
+ {0x27u, 0x04u},
+ {0x28u, 0x0Fu},
{0x2Du, 0x90u},
- {0x2Fu, 0x60u},
- {0x30u, 0xFFu},
+ {0x2Fu, 0x40u},
{0x31u, 0xFFu},
- {0x3Eu, 0x01u},
+ {0x34u, 0x7Fu},
{0x3Fu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Cu, 0x01u},
{0x5Fu, 0x01u},
- {0x82u, 0x0Au},
- {0x85u, 0x60u},
- {0x87u, 0x90u},
- {0x88u, 0x01u},
- {0x89u, 0x05u},
- {0x8Au, 0x04u},
- {0x8Bu, 0x0Au},
- {0x8Du, 0x0Fu},
- {0x8Fu, 0xF0u},
- {0x90u, 0x01u},
- {0x92u, 0x04u},
- {0x96u, 0x02u},
- {0x98u, 0x05u},
- {0x99u, 0x06u},
- {0x9Bu, 0x09u},
- {0x9Cu, 0x0Au},
- {0x9Du, 0x30u},
- {0x9Fu, 0xC0u},
- {0xA0u, 0x0Au},
- {0xA4u, 0x0Au},
- {0xA5u, 0x03u},
- {0xA7u, 0x0Cu},
- {0xA8u, 0x0Au},
- {0xA9u, 0x50u},
- {0xABu, 0xA0u},
- {0xB0u, 0x04u},
- {0xB2u, 0x08u},
- {0xB4u, 0x02u},
- {0xB5u, 0xFFu},
- {0xB6u, 0x01u},
- {0xBEu, 0x55u},
- {0xBFu, 0x10u},
- {0xD4u, 0x09u},
- {0xD6u, 0x04u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDFu, 0x01u},
- {0x00u, 0x02u},
- {0x02u, 0x08u},
- {0x05u, 0x90u},
- {0x06u, 0x80u},
- {0x09u, 0x0Au},
- {0x0Au, 0x05u},
- {0x0Bu, 0x20u},
- {0x0Cu, 0x01u},
- {0x0Fu, 0x19u},
- {0x10u, 0xA0u},
- {0x11u, 0x10u},
- {0x14u, 0x44u},
- {0x15u, 0x04u},
- {0x18u, 0x10u},
- {0x19u, 0x40u},
- {0x1Au, 0x58u},
- {0x1Cu, 0x80u},
- {0x22u, 0x20u},
- {0x26u, 0x02u},
- {0x28u, 0x20u},
- {0x29u, 0x08u},
- {0x2Au, 0x30u},
- {0x2Cu, 0x04u},
- {0x2Du, 0x84u},
- {0x2Fu, 0x2Au},
- {0x31u, 0x20u},
- {0x33u, 0x40u},
- {0x34u, 0x41u},
- {0x35u, 0x11u},
- {0x36u, 0xA0u},
- {0x38u, 0x20u},
- {0x39u, 0x40u},
- {0x3Au, 0x84u},
- {0x3Du, 0x40u},
- {0x3Fu, 0x19u},
- {0x58u, 0x02u},
- {0x59u, 0x04u},
- {0x5Au, 0x60u},
- {0x61u, 0x40u},
- {0x63u, 0x40u},
- {0x80u, 0x12u},
- {0x87u, 0x40u},
- {0x8Du, 0x40u},
- {0x90u, 0x20u},
- {0x91u, 0x50u},
- {0x92u, 0x05u},
- {0x93u, 0x11u},
- {0x97u, 0x08u},
- {0x99u, 0x09u},
- {0x9Du, 0x10u},
- {0x9Eu, 0x15u},
- {0xA0u, 0xA1u},
- {0xA1u, 0x22u},
- {0xA2u, 0x88u},
- {0xA3u, 0x04u},
- {0xA4u, 0x40u},
- {0xA6u, 0x27u},
- {0xA7u, 0xAAu},
- {0xA8u, 0x0Cu},
- {0xABu, 0x20u},
- {0xAEu, 0x04u},
- {0xB0u, 0x01u},
- {0xB5u, 0x14u},
- {0xC0u, 0xDAu},
- {0xC2u, 0xFFu},
- {0xC4u, 0x7Eu},
- {0xCAu, 0x76u},
- {0xCCu, 0xBCu},
- {0xCEu, 0xFEu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x09u},
- {0xE2u, 0x08u},
- {0xE8u, 0x04u},
- {0xECu, 0x08u},
- {0x00u, 0x10u},
- {0x01u, 0xC0u},
- {0x03u, 0x08u},
- {0x04u, 0x07u},
- {0x05u, 0xC0u},
- {0x06u, 0x18u},
- {0x07u, 0x04u},
- {0x08u, 0x22u},
- {0x0Au, 0x08u},
- {0x0Cu, 0x40u},
- {0x0Du, 0xC0u},
- {0x0Fu, 0x01u},
- {0x10u, 0x40u},
- {0x11u, 0x80u},
- {0x14u, 0x04u},
- {0x17u, 0xFFu},
- {0x18u, 0x01u},
- {0x1Bu, 0x60u},
- {0x1Cu, 0x01u},
- {0x1Fu, 0x9Fu},
- {0x20u, 0x01u},
- {0x21u, 0x1Fu},
- {0x23u, 0x20u},
- {0x24u, 0x08u},
- {0x25u, 0x90u},
- {0x26u, 0x21u},
- {0x27u, 0x40u},
- {0x28u, 0x01u},
- {0x29u, 0xC0u},
- {0x2Bu, 0x02u},
- {0x2Cu, 0x01u},
- {0x2Du, 0x7Fu},
- {0x2Fu, 0x80u},
- {0x30u, 0x3Fu},
- {0x32u, 0x40u},
- {0x37u, 0xFFu},
- {0x38u, 0x0Au},
- {0x3Eu, 0x01u},
- {0x3Fu, 0x40u},
- {0x54u, 0x40u},
- {0x56u, 0x04u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Fu, 0x01u},
- {0x80u, 0x10u},
+ {0x80u, 0xFFu},
{0x81u, 0x04u},
- {0x82u, 0x20u},
- {0x84u, 0x01u},
- {0x86u, 0x02u},
- {0x8Cu, 0x02u},
- {0x8Eu, 0x09u},
- {0x90u, 0x02u},
- {0x92u, 0x05u},
- {0x94u, 0x02u},
- {0x96u, 0x01u},
- {0x9Cu, 0x02u},
- {0x9Eu, 0x01u},
- {0x9Fu, 0x01u},
- {0xA2u, 0x20u},
- {0xA6u, 0x10u},
- {0xAFu, 0x02u},
- {0xB0u, 0x04u},
- {0xB1u, 0x02u},
- {0xB2u, 0x08u},
- {0xB3u, 0x01u},
- {0xB4u, 0x03u},
- {0xB6u, 0x30u},
- {0xB7u, 0x04u},
+ {0x83u, 0x20u},
+ {0x84u, 0x33u},
+ {0x85u, 0x39u},
+ {0x86u, 0xCCu},
+ {0x87u, 0x06u},
+ {0x88u, 0x0Fu},
+ {0x8Au, 0xF0u},
+ {0x8Bu, 0x46u},
+ {0x8Du, 0x46u},
+ {0x8Eu, 0xFFu},
+ {0x90u, 0x69u},
+ {0x92u, 0x96u},
+ {0x95u, 0x01u},
+ {0x97u, 0x5Eu},
+ {0x98u, 0x55u},
+ {0x99u, 0x42u},
+ {0x9Au, 0xAAu},
+ {0x9Bu, 0x04u},
+ {0x9Du, 0x46u},
+ {0xA1u, 0x46u},
+ {0xA2u, 0xFFu},
+ {0xA4u, 0xFFu},
+ {0xA5u, 0x77u},
+ {0xA7u, 0x08u},
+ {0xAAu, 0xFFu},
+ {0xADu, 0x42u},
+ {0xB3u, 0x70u},
+ {0xB4u, 0xFFu},
+ {0xB5u, 0x0Fu},
+ {0xB9u, 0x20u},
{0xBAu, 0x20u},
- {0xBEu, 0x40u},
- {0xD6u, 0x08u},
+ {0xBBu, 0x0Cu},
+ {0xD6u, 0x02u},
+ {0xD7u, 0x20u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x99u},
- {0xDDu, 0x90u},
+ {0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x00u, 0x44u},
- {0x01u, 0x02u},
- {0x04u, 0x20u},
- {0x05u, 0x08u},
- {0x07u, 0x81u},
- {0x09u, 0x82u},
- {0x0Au, 0x10u},
- {0x0Eu, 0xA4u},
- {0x0Fu, 0x02u},
- {0x11u, 0x06u},
- {0x14u, 0x04u},
- {0x16u, 0x01u},
- {0x17u, 0x0Au},
- {0x18u, 0x46u},
- {0x1Au, 0x10u},
- {0x1Eu, 0xA0u},
- {0x21u, 0x42u},
- {0x22u, 0x04u},
- {0x27u, 0x01u},
- {0x29u, 0x40u},
- {0x2Cu, 0x06u},
- {0x2Fu, 0xA0u},
- {0x32u, 0x80u},
- {0x36u, 0x10u},
- {0x37u, 0x8Au},
- {0x39u, 0x02u},
- {0x3Eu, 0x06u},
- {0x3Fu, 0x80u},
- {0x5Au, 0x40u},
- {0x61u, 0xC0u},
- {0x64u, 0x20u},
- {0x66u, 0x80u},
- {0x67u, 0x88u},
- {0x87u, 0x40u},
- {0x8Du, 0x02u},
- {0x90u, 0x20u},
- {0x91u, 0x06u},
- {0x92u, 0x44u},
- {0x94u, 0x04u},
- {0x95u, 0x80u},
- {0x96u, 0x08u},
- {0x98u, 0x04u},
- {0x99u, 0x08u},
- {0x9Au, 0x03u},
- {0x9Bu, 0x0Au},
- {0xA0u, 0x02u},
- {0xA2u, 0x80u},
- {0xA3u, 0xE1u},
- {0xAAu, 0x20u},
- {0xABu, 0x08u},
- {0xADu, 0x08u},
- {0xAFu, 0x80u},
- {0xB0u, 0x40u},
- {0xB3u, 0x21u},
- {0xB5u, 0x08u},
- {0xB7u, 0x02u},
- {0xC0u, 0xFDu},
- {0xC2u, 0xFDu},
- {0xC4u, 0xFCu},
- {0xCAu, 0xF8u},
- {0xCCu, 0xF8u},
- {0xCEu, 0xD1u},
- {0xD6u, 0x08u},
- {0xD8u, 0xF8u},
- {0xE0u, 0x40u},
- {0xE8u, 0x80u},
- {0xECu, 0x50u},
- {0xB9u, 0x08u},
- {0xBFu, 0x04u},
- {0xD9u, 0x04u},
- {0xDFu, 0x01u},
- {0x26u, 0x08u},
- {0x87u, 0x80u},
- {0x8Bu, 0x04u},
- {0x97u, 0x08u},
- {0x9Fu, 0x80u},
- {0xA6u, 0x08u},
- {0xAAu, 0x08u},
- {0xB0u, 0x20u},
- {0xB4u, 0x01u},
- {0xB5u, 0x01u},
- {0xB6u, 0x80u},
- {0xE0u, 0x80u},
- {0xE6u, 0x02u},
- {0xE8u, 0x90u},
- {0xECu, 0x10u},
- {0x12u, 0x02u},
- {0x16u, 0x80u},
- {0x17u, 0x20u},
+ {0x00u, 0x01u},
+ {0x01u, 0x20u},
+ {0x02u, 0x10u},
+ {0x03u, 0x01u},
+ {0x04u, 0x2Au},
+ {0x06u, 0x04u},
+ {0x07u, 0x01u},
+ {0x08u, 0x02u},
+ {0x09u, 0x20u},
+ {0x0Eu, 0x28u},
+ {0x11u, 0x05u},
+ {0x12u, 0x04u},
+ {0x15u, 0x04u},
+ {0x17u, 0x10u},
+ {0x18u, 0x08u},
+ {0x19u, 0x20u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x20u},
+ {0x20u, 0x2Cu},
+ {0x21u, 0x08u},
+ {0x22u, 0x08u},
+ {0x26u, 0x01u},
+ {0x28u, 0x10u},
+ {0x2Au, 0x82u},
+ {0x2Cu, 0xA0u},
+ {0x2Du, 0x40u},
+ {0x30u, 0xA0u},
{0x31u, 0x08u},
- {0x34u, 0x18u},
+ {0x34u, 0x10u},
+ {0x35u, 0x02u},
+ {0x36u, 0xA8u},
+ {0x37u, 0x08u},
+ {0x38u, 0x04u},
+ {0x39u, 0x50u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x01u},
+ {0x3Cu, 0x04u},
+ {0x3Eu, 0x92u},
+ {0x3Fu, 0x48u},
+ {0x63u, 0x02u},
+ {0x68u, 0xA8u},
+ {0x69u, 0x50u},
+ {0x6Au, 0x10u},
+ {0x72u, 0x02u},
+ {0x88u, 0x80u},
+ {0x8Bu, 0x04u},
+ {0x90u, 0x23u},
+ {0x91u, 0x07u},
+ {0x95u, 0x40u},
+ {0x98u, 0x02u},
+ {0x9Au, 0x10u},
+ {0x9Bu, 0x11u},
+ {0x9Eu, 0x02u},
+ {0x9Fu, 0x08u},
+ {0xA1u, 0x20u},
+ {0xA2u, 0x10u},
+ {0xA3u, 0x01u},
+ {0xA4u, 0xACu},
+ {0xA6u, 0x20u},
+ {0xABu, 0x58u},
+ {0xB1u, 0x01u},
+ {0xB3u, 0x04u},
+ {0xB4u, 0x80u},
+ {0xB6u, 0x10u},
+ {0xC0u, 0xFFu},
+ {0xC2u, 0x6Au},
+ {0xC4u, 0x6Eu},
+ {0xCAu, 0xDBu},
+ {0xCCu, 0xFEu},
+ {0xCEu, 0xFFu},
+ {0xD8u, 0x08u},
+ {0xE2u, 0x28u},
+ {0xE8u, 0x04u},
+ {0xEEu, 0x01u},
+ {0x39u, 0x20u},
+ {0x3Fu, 0x10u},
+ {0x59u, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x27u, 0x08u},
+ {0x87u, 0x08u},
+ {0x88u, 0x08u},
+ {0x90u, 0x04u},
+ {0x96u, 0x10u},
+ {0x97u, 0x80u},
+ {0x9Cu, 0x18u},
+ {0x9Du, 0xC0u},
+ {0xA6u, 0x20u},
+ {0xA7u, 0x40u},
+ {0xA8u, 0x04u},
+ {0xA9u, 0x04u},
+ {0xAAu, 0x01u},
+ {0xB0u, 0x02u},
+ {0xB1u, 0x02u},
+ {0xB5u, 0x10u},
+ {0xE0u, 0x80u},
+ {0xE8u, 0xE0u},
+ {0xEAu, 0x10u},
+ {0x80u, 0x04u},
+ {0x84u, 0x10u},
+ {0x86u, 0x20u},
+ {0x90u, 0x04u},
+ {0x9Cu, 0x10u},
+ {0xA6u, 0x20u},
+ {0xAAu, 0x10u},
+ {0xB1u, 0xC0u},
+ {0xB3u, 0x40u},
+ {0xB7u, 0x40u},
+ {0xE8u, 0x80u},
+ {0xECu, 0xC0u},
+ {0x12u, 0x08u},
+ {0x16u, 0x80u},
+ {0x17u, 0x80u},
+ {0x33u, 0x04u},
+ {0x35u, 0x08u},
+ {0x36u, 0x80u},
{0x3Au, 0x81u},
- {0x3Eu, 0x01u},
+ {0x3Du, 0x04u},
{0x3Fu, 0x20u},
- {0x42u, 0x08u},
- {0x53u, 0x01u},
- {0x5Bu, 0x08u},
- {0x5Du, 0x02u},
- {0x62u, 0x20u},
- {0x66u, 0x04u},
- {0x77u, 0x10u},
- {0x7Eu, 0x02u},
+ {0x43u, 0x20u},
+ {0x52u, 0x20u},
+ {0x5Bu, 0x01u},
+ {0x60u, 0x20u},
+ {0x64u, 0x08u},
+ {0x65u, 0x40u},
+ {0x82u, 0x01u},
+ {0x85u, 0x40u},
+ {0x87u, 0x01u},
{0xC4u, 0xE0u},
{0xCCu, 0xE0u},
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
- {0xD4u, 0x80u},
+ {0xD4u, 0x20u},
{0xD6u, 0xC0u},
{0xD8u, 0xC0u},
- {0x30u, 0x02u},
- {0x33u, 0x10u},
- {0x34u, 0x02u},
- {0x37u, 0x20u},
- {0x3Bu, 0x20u},
- {0x57u, 0x20u},
- {0x5Au, 0x80u},
- {0x5Eu, 0x10u},
- {0x66u, 0x80u},
- {0x82u, 0x30u},
- {0x84u, 0x02u},
- {0x8Au, 0x80u},
- {0x96u, 0x01u},
- {0x97u, 0x02u},
- {0x9Bu, 0x30u},
- {0x9Cu, 0x18u},
- {0x9Du, 0x02u},
- {0x9Eu, 0x0Cu},
- {0x9Fu, 0x08u},
- {0xA5u, 0x08u},
- {0xA6u, 0x20u},
- {0xA7u, 0x10u},
- {0xB6u, 0x01u},
+ {0xE2u, 0x60u},
+ {0xE6u, 0x10u},
+ {0x33u, 0x18u},
+ {0x35u, 0x04u},
+ {0x37u, 0x80u},
+ {0x39u, 0x80u},
+ {0x54u, 0x02u},
+ {0x57u, 0x10u},
+ {0x5Bu, 0x40u},
+ {0x63u, 0x80u},
+ {0x95u, 0x04u},
+ {0x9Bu, 0xD0u},
+ {0x9Cu, 0x20u},
+ {0x9Du, 0x08u},
+ {0x9Fu, 0x04u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x20u},
+ {0xA8u, 0x08u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x50u},
+ {0xAEu, 0x20u},
+ {0xB7u, 0x10u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
{0xD4u, 0xC0u},
- {0xD6u, 0xA0u},
- {0xE2u, 0x80u},
- {0xE6u, 0xC0u},
- {0x10u, 0x10u},
- {0x30u, 0x20u},
- {0x80u, 0x02u},
- {0x82u, 0x04u},
- {0x88u, 0x08u},
- {0x8Du, 0x80u},
- {0x8Fu, 0x20u},
- {0x96u, 0x81u},
- {0x97u, 0x22u},
- {0x9Cu, 0x18u},
- {0x9Eu, 0x0Cu},
- {0x9Fu, 0x08u},
- {0xA4u, 0x02u},
- {0xA5u, 0x08u},
- {0xA7u, 0x20u},
- {0xABu, 0x10u},
- {0xB1u, 0x02u},
+ {0xD6u, 0x20u},
+ {0xD8u, 0x40u},
+ {0xEEu, 0xE0u},
+ {0x12u, 0x80u},
+ {0x32u, 0x10u},
+ {0x82u, 0x10u},
+ {0x83u, 0x50u},
+ {0x85u, 0x08u},
+ {0x8Bu, 0x08u},
+ {0x8Cu, 0x20u},
+ {0x95u, 0x84u},
+ {0x9Du, 0x0Cu},
+ {0x9Fu, 0x04u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x78u},
+ {0xA8u, 0x22u},
{0xC4u, 0x10u},
{0xCCu, 0x10u},
- {0xE2u, 0xA0u},
- {0xEEu, 0x80u},
- {0x81u, 0x08u},
- {0x83u, 0x01u},
- {0x96u, 0x01u},
- {0x97u, 0x02u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x08u},
- {0xA1u, 0x80u},
- {0xA5u, 0x08u},
- {0xACu, 0x20u},
- {0xB3u, 0x10u},
- {0xB6u, 0x40u},
+ {0xE2u, 0x20u},
+ {0xE6u, 0xB0u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x20u},
+ {0x81u, 0x44u},
+ {0x95u, 0x84u},
+ {0x9Du, 0x04u},
+ {0xA0u, 0x20u},
+ {0xABu, 0x04u},
+ {0xAFu, 0x20u},
{0xE2u, 0x80u},
- {0xE6u, 0x20u},
- {0xEAu, 0x40u},
- {0x08u, 0x28u},
+ {0xE6u, 0x80u},
+ {0xEAu, 0x80u},
+ {0xEEu, 0x10u},
+ {0x08u, 0x04u},
+ {0x09u, 0x80u},
{0x0Fu, 0x20u},
- {0x13u, 0x01u},
- {0x17u, 0x08u},
- {0x53u, 0x21u},
- {0x55u, 0x08u},
- {0x5Cu, 0x40u},
- {0x83u, 0x01u},
- {0x8Bu, 0x10u},
+ {0x12u, 0x20u},
+ {0x17u, 0x01u},
+ {0x50u, 0x04u},
+ {0x57u, 0x20u},
+ {0x58u, 0x20u},
+ {0x5Fu, 0x40u},
+ {0x80u, 0x40u},
{0xC2u, 0x0Eu},
{0xC4u, 0x0Cu},
{0xD4u, 0x07u},
{0xD6u, 0x04u},
- {0xE2u, 0x04u},
- {0x01u, 0x82u},
- {0x06u, 0x08u},
+ {0x00u, 0x40u},
+ {0x02u, 0x10u},
+ {0x05u, 0x20u},
{0x07u, 0x20u},
- {0x08u, 0x80u},
- {0x0Bu, 0x20u},
- {0x0Eu, 0x01u},
- {0x0Fu, 0x80u},
+ {0x08u, 0x02u},
+ {0x09u, 0x20u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x02u},
{0x83u, 0x10u},
- {0x84u, 0x20u},
- {0x85u, 0x01u},
+ {0x8Au, 0x10u},
+ {0x8Bu, 0x60u},
{0x94u, 0x40u},
- {0x97u, 0x20u},
- {0x98u, 0x28u},
- {0x9Bu, 0x08u},
+ {0x97u, 0x40u},
+ {0x9Bu, 0x01u},
+ {0xA2u, 0x20u},
{0xA3u, 0x10u},
- {0xA5u, 0x08u},
- {0xA7u, 0x60u},
- {0xABu, 0x41u},
+ {0xA7u, 0x20u},
+ {0xA8u, 0x04u},
+ {0xACu, 0x20u},
+ {0xB0u, 0x04u},
+ {0xB5u, 0x80u},
{0xC0u, 0x0Fu},
{0xC2u, 0x0Fu},
- {0x82u, 0x40u},
- {0x83u, 0x20u},
- {0x8Au, 0x08u},
- {0x94u, 0x40u},
- {0x95u, 0x02u},
- {0x98u, 0x08u},
- {0x9Au, 0x08u},
- {0x9Bu, 0x28u},
- {0xA7u, 0x20u},
- {0xA9u, 0x0Au},
- {0xB2u, 0x01u},
- {0xB4u, 0x80u},
- {0xB5u, 0x80u},
- {0xE2u, 0x04u},
+ {0xE0u, 0x05u},
+ {0xE6u, 0x04u},
{0xEAu, 0x08u},
- {0xEEu, 0x03u},
- {0x08u, 0x10u},
- {0x0Au, 0x40u},
- {0x0Du, 0x01u},
- {0x0Eu, 0x04u},
- {0x83u, 0x08u},
- {0x94u, 0x40u},
- {0x95u, 0x02u},
- {0x96u, 0x44u},
- {0x9Bu, 0x08u},
- {0x9Cu, 0x10u},
- {0xABu, 0x20u},
- {0xAEu, 0x04u},
- {0xB0u, 0x10u},
- {0xB4u, 0x08u},
+ {0xEEu, 0x01u},
+ {0x82u, 0x05u},
+ {0x84u, 0x02u},
+ {0x8Bu, 0x11u},
+ {0x91u, 0x02u},
+ {0x98u, 0x02u},
+ {0x99u, 0x20u},
+ {0x9Bu, 0x21u},
+ {0xA1u, 0x20u},
+ {0xA2u, 0x01u},
+ {0xAEu, 0x20u},
+ {0xE2u, 0x04u},
+ {0xE6u, 0x04u},
+ {0x0Bu, 0x21u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x20u},
+ {0x83u, 0x11u},
+ {0x85u, 0x01u},
+ {0x8Cu, 0x04u},
+ {0x91u, 0x02u},
+ {0x97u, 0x20u},
+ {0x99u, 0x20u},
+ {0xA6u, 0x04u},
+ {0xAFu, 0x20u},
+ {0xB5u, 0x20u},
{0xC2u, 0x0Fu},
- {0xEAu, 0x06u},
- {0x65u, 0x01u},
- {0x86u, 0x09u},
- {0x96u, 0x01u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x08u},
- {0xA1u, 0x80u},
+ {0xE6u, 0x02u},
+ {0xEEu, 0x02u},
+ {0x67u, 0x80u},
+ {0x87u, 0x40u},
+ {0x89u, 0x04u},
+ {0x95u, 0x04u},
+ {0xA0u, 0x20u},
{0xD8u, 0x80u},
{0xE2u, 0x10u},
- {0xE6u, 0x40u},
- {0x04u, 0x08u},
- {0x51u, 0x80u},
- {0x56u, 0x80u},
- {0x8Cu, 0x04u},
- {0x8Eu, 0x80u},
- {0x8Fu, 0x08u},
- {0x9Fu, 0x08u},
- {0xA1u, 0x80u},
- {0xA9u, 0x01u},
+ {0x06u, 0x40u},
+ {0x50u, 0x20u},
+ {0x57u, 0x80u},
+ {0x86u, 0x40u},
+ {0x8Fu, 0x80u},
+ {0xA0u, 0x20u},
{0xC0u, 0x20u},
{0xD4u, 0x60u},
- {0xEAu, 0x20u},
- {0x94u, 0x40u},
- {0x00u, 0x08u},
- {0x84u, 0x04u},
- {0xB4u, 0x40u},
+ {0xE0u, 0x10u},
+ {0x94u, 0x04u},
+ {0xB5u, 0x20u},
+ {0xEAu, 0x08u},
+ {0x00u, 0x04u},
+ {0x94u, 0x04u},
{0xC0u, 0x08u},
- {0xE8u, 0x02u},
- {0x10u, 0x01u},
- {0x11u, 0x01u},
- {0x1Au, 0x01u},
- {0x1Bu, 0x01u},
- {0x1Cu, 0x01u},
- {0x1Du, 0x01u},
+ {0x10u, 0x03u},
+ {0x1Au, 0x03u},
{0x00u, 0xFDu},
{0x01u, 0xBFu},
{0x02u, 0x2Au},
@@ -2241,7 +2212,7 @@ void cyfitter_cfg(void)
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x01u, 0x01u, 0x02u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 0907392..b6b926e 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -391,34 +391,34 @@
.set USBFS_USB__USBIO_CR1, CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB07_08_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B0_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB07_08_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B0_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B0_UDB07_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B0_UDB07_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B0_UDB07_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B0_UDB07_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB08_09_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB08_09_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB07_08_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB07_08_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB07_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB07_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB07_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -426,9 +426,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB08_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB08_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB08_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB04_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@@ -450,8 +450,8 @@
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@@ -459,9 +459,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB08_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB08_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@@ -1941,15 +1941,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_06_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB05_06_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB05_06_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB05_06_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB05_06_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B1_UDB05_06_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB05_06_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB05_06_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB05_06_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1962,37 +1962,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B1_UDB05_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B1_UDB05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B1_UDB05_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B1_UDB05_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B1_UDB05_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB05_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B1_UDB05_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_15_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB14_15_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB14_15_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB14_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB14_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB14_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB14_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB14_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT6_AG
@@ -2818,8 +2818,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB12_13_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB12_13_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2827,9 +2827,9 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB02_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB02_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB12_MSK
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB12_ACTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2950,8 +2950,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB01_02_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2959,67 +2959,67 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB01_MSK
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB01_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS, 0
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS, 1
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB11_12_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB11_12_MSK
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB11_12_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB05_06_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB05_06_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB05_06_MSK
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS, 2
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB11_ST_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB11_CTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB11_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB05_ST_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB05_CTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB05_ST_CTL
.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK, 0x07
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB11_MSK_ACTL
-.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB11_MSK
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB05_MSK_ACTL
+.set SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_11_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB10_11_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB10_11_MSK
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB10_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB10_ST_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB10_CTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB10_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB10_MSK_ACTL
-.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB10_MSK
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB09_10_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB09_10_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB09_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB09_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB09_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index b5e792b..bfc5642 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -459,9 +459,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@@ -1941,15 +1941,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1962,37 +1962,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2818,8 +2818,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2827,9 +2827,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2950,8 +2950,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2959,67 +2959,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
/* SCSI_Glitch_Ctl */
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index d456caf..b0cda45 100755
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -391,34 +391,34 @@ USBFS_USB__USBIO_CR0 EQU CYREG_USB_USBIO_CR0
USBFS_USB__USBIO_CR1 EQU CYREG_USB_USBIO_CR1
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB07_08_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB07_08_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B0_UDB07_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B0_UDB07_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB07_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B0_UDB07_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B0_UDB07_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_09_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB08_09_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB07_08_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB07_08_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB07_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB07_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB07_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -426,9 +426,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB08_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB08_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB08_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB04_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -450,8 +450,8 @@ SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -459,9 +459,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@@ -1941,15 +1941,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_06_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB05_06_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB05_06_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB05_06_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1962,37 +1962,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB05_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B1_UDB05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B1_UDB05_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B1_UDB05_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B1_UDB05_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB05_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B1_UDB05_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_15_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB14_15_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB14_15_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB14_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB14_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB14_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB14_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB14_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB14_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT6_AG
@@ -2818,8 +2818,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_13_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB12_13_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2827,9 +2827,9 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB02_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB02_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB12_MSK
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB12_ACTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB12_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2950,8 +2950,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB01_02_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2959,67 +2959,67 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB01_MSK
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB01_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_CTL_PHASE_Sync_ctrl_reg__0__POS EQU 0
SCSI_CTL_PHASE_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_CTL_PHASE_Sync_ctrl_reg__1__POS EQU 1
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB11_12_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB11_12_MSK
-SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB11_12_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB05_06_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB05_06_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB05_06_MSK
SCSI_CTL_PHASE_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_CTL_PHASE_Sync_ctrl_reg__2__POS EQU 2
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB11_ST_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB11_CTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB11_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB05_ST_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB05_CTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB05_ST_CTL
SCSI_CTL_PHASE_Sync_ctrl_reg__MASK EQU 0x07
-SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB11_MSK_ACTL
-SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB11_MSK
+SCSI_CTL_PHASE_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB05_MSK_ACTL
+SCSI_CTL_PHASE_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB05_MSK
; SCSI_Glitch_Ctl
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Glitch_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_11_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB10_11_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB10_11_MSK
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB10_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB10_ST_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB10_CTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB10_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB10_MSK_ACTL
-SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB10_MSK
+SCSI_Glitch_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_10_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB09_10_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB09_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB09_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB09_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
index b9e78c0..57ece01 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cycdx
@@ -1,42 +1,12 @@
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
+
-
-
+
+
@@ -95,13 +65,26 @@
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
+
+
+
@@ -128,18 +111,36 @@
-
-
-
-
-
-
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
-
-
-
-
-
@@ -150,7 +151,7 @@
-
+
@@ -158,8 +159,6 @@
-
-
@@ -257,13 +256,6 @@
-
-
-
-
-
-
-
@@ -271,10 +263,16 @@
-
+
+
+
+
+
+
-
+
+
\ No newline at end of file
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit
index 004e661..92a3773 100644
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.cyfit differ
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
index 0a10251..c14defd 100644
--- a/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
+++ b/software/SCSI2SD/v3/SCSI2SD.cydsn/SCSI2SD.svd
@@ -6,161 +6,6 @@
8
32
-
- SCSI_Parity_Error
- No description available
- 0x40006464
-
- 0
- 0x0
- registers
-
-
-
- SCSI_Parity_Error_STATUS_REG
- No description available
- 0x0
- 8
- read-write
- 0
- 0
-
-
- SCSI_Parity_Error_MASK_REG
- No description available
- 0x20
- 8
- read-write
- 0
- 0
-
-
- SCSI_Parity_Error_STATUS_AUX_CTL_REG
- No description available
- 0x30
- 8
- read-write
- 0
- 0
-
-
- FIFO0
- FIFO0 clear
- 5
- 5
- read-write
-
-
- ENABLED
- Enable counter
- 1
-
-
- DISABLED
- Disable counter
- 0
-
-
-
-
- INTRENBL
- Enables or disables the Interrupt
- 4
- 4
- read-write
-
-
- ENABLED
- Interrupt enabled
- 1
-
-
- DISABLED
- Interrupt disabled
- 0
-
-
-
-
- FIFO1LEVEL
- FIFO level
- 3
- 3
- read-write
-
-
- ENABLED
- FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
- 1
-
-
- DISABLED
- FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
- 0
-
-
-
-
- FIFO0LEVEL
- FIFO level
- 2
- 2
- read-write
-
-
- ENABLED
- FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
- 1
-
-
- DISABLED
- FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
- 0
-
-
-
-
- FIFO1CLEAR
- FIFO clear
- 1
- 1
- read-write
-
-
- ENABLED
- Clear FIFO state
- 1
-
-
- DISABLED
- Normal FIFO operation
- 0
-
-
-
-
- FIFO0CLEAR
- FIFO clear
- 0
- 0
- read-write
-
-
- ENABLED
- Clear FIFO state
- 1
-
-
- DISABLED
- Normal FIFO operation
- 0
-
-
-
-
-
-
-
Debug_Timer
No description available
@@ -453,10 +298,52 @@
+
+ SCSI_Out_Ctl
+ No description available
+ 0x4000647E
+
+ 0
+ 0x0
+ registers
+
+
+
+ SCSI_Out_Ctl_CONTROL_REG
+ No description available
+ 0x0
+ 8
+ read-write
+ 0
+ 0
+
+
+
+
+ SCSI_Glitch_Ctl
+ No description available
+ 0x40006474
+
+ 0
+ 0x0
+ registers
+
+
+
+ SCSI_Glitch_Ctl_CONTROL_REG
+ No description available
+ 0x0
+ 8
+ read-write
+ 0
+ 0
+
+
+
SCSI_Filtered
No description available
- 0x40006461
+ 0x40006462
0
0x0
@@ -609,9 +496,9 @@
- SCSI_Glitch_Ctl
+ SCSI_Parity_Error
No description available
- 0x4000647A
+ 0x40006469
0
0x0
@@ -619,7 +506,7 @@
- SCSI_Glitch_Ctl_CONTROL_REG
+ SCSI_Parity_Error_STATUS_REG
No description available
0x0
8
@@ -627,12 +514,146 @@
0
0
+
+ SCSI_Parity_Error_MASK_REG
+ No description available
+ 0x20
+ 8
+ read-write
+ 0
+ 0
+
+
+ SCSI_Parity_Error_STATUS_AUX_CTL_REG
+ No description available
+ 0x30
+ 8
+ read-write
+ 0
+ 0
+
+
+ FIFO0
+ FIFO0 clear
+ 5
+ 5
+ read-write
+
+
+ ENABLED
+ Enable counter
+ 1
+
+
+ DISABLED
+ Disable counter
+ 0
+
+
+
+
+ INTRENBL
+ Enables or disables the Interrupt
+ 4
+ 4
+ read-write
+
+
+ ENABLED
+ Interrupt enabled
+ 1
+
+
+ DISABLED
+ Interrupt disabled
+ 0
+
+
+
+
+ FIFO1LEVEL
+ FIFO level
+ 3
+ 3
+ read-write
+
+
+ ENABLED
+ FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
+ 1
+
+
+ DISABLED
+ FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
+ 0
+
+
+
+
+ FIFO0LEVEL
+ FIFO level
+ 2
+ 2
+ read-write
+
+
+ ENABLED
+ FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
+ 1
+
+
+ DISABLED
+ FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
+ 0
+
+
+
+
+ FIFO1CLEAR
+ FIFO clear
+ 1
+ 1
+ read-write
+
+
+ ENABLED
+ Clear FIFO state
+ 1
+
+
+ DISABLED
+ Normal FIFO operation
+ 0
+
+
+
+
+ FIFO0CLEAR
+ FIFO clear
+ 0
+ 0
+ read-write
+
+
+ ENABLED
+ Clear FIFO state
+ 1
+
+
+ DISABLED
+ Normal FIFO operation
+ 0
+
+
+
+
+
SCSI_CTL_PHASE
No description available
- 0x4000647B
+ 0x40006475
0
0x0
@@ -1134,31 +1155,10 @@
-
- SCSI_Out_Ctl
- No description available
- 0x40006475
-
- 0
- 0x0
- registers
-
-
-
- SCSI_Out_Ctl_CONTROL_REG
- No description available
- 0x0
- 8
- read-write
- 0
- 0
-
-
-
SCSI_Out_Bits
No description available
- 0x40006575
+ 0x4000647A
0
0x0
diff --git a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
index 8583dae..cbbce22 100755
Binary files a/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v3/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
index 69da813..5d43610 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter.h
@@ -426,34 +426,34 @@
#define EXTLED__SLW CYREG_PRT0_SLW
/* SDCard_BSPIM */
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB06_07_CTL
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB06_07_MSK
-#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB06_CTL
-#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB06_07_ACTL
-#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB06_07_ST
-#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB06_MSK
-#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB06_MSK_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB06_ACTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB06_ST_CTL
-#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB06_ST
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
-#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG CYREG_B1_UDB04_05_CTL
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG CYREG_B1_UDB04_05_MSK
+#define SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter__CONTROL_REG CYREG_B1_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__CONTROL_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_REG CYREG_B1_UDB04_CTL
+#define SDCard_BSPIM_BitCounter__COUNT_ST_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter__PERIOD_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB04_05_ACTL
+#define SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG CYREG_B1_UDB04_05_ST
+#define SDCard_BSPIM_BitCounter_ST__MASK_REG CYREG_B1_UDB04_MSK
+#define SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG CYREG_B1_UDB04_ACTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG CYREG_B1_UDB04_ST_CTL
+#define SDCard_BSPIM_BitCounter_ST__STATUS_REG CYREG_B1_UDB04_ST
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B1_UDB07_08_ACTL
+#define SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG CYREG_B1_UDB07_08_ST
#define SDCard_BSPIM_RxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_RxStsReg__4__POS 4
#define SDCard_BSPIM_RxStsReg__5__MASK 0x20u
@@ -461,9 +461,9 @@
#define SDCard_BSPIM_RxStsReg__6__MASK 0x40u
#define SDCard_BSPIM_RxStsReg__6__POS 6
#define SDCard_BSPIM_RxStsReg__MASK 0x70u
-#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B0_UDB07_MSK
-#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
-#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B0_UDB07_ST
+#define SDCard_BSPIM_RxStsReg__MASK_REG CYREG_B1_UDB07_MSK
+#define SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG CYREG_B1_UDB07_ACTL
+#define SDCard_BSPIM_RxStsReg__STATUS_REG CYREG_B1_UDB07_ST
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG CYREG_B1_UDB04_05_A0
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG CYREG_B1_UDB04_05_A1
#define SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG CYREG_B1_UDB04_05_D0
@@ -481,12 +481,14 @@
#define SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG CYREG_B1_UDB04_F0_F1
#define SDCard_BSPIM_sR8_Dp_u0__F0_REG CYREG_B1_UDB04_F0
#define SDCard_BSPIM_sR8_Dp_u0__F1_REG CYREG_B1_UDB04_F1
+#define SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
+#define SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG CYREG_B1_UDB04_MSK_ACTL
#define SDCard_BSPIM_TxStsReg__0__MASK 0x01u
#define SDCard_BSPIM_TxStsReg__0__POS 0
#define SDCard_BSPIM_TxStsReg__1__MASK 0x02u
#define SDCard_BSPIM_TxStsReg__1__POS 1
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
-#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB07_08_ACTL
+#define SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG CYREG_B0_UDB07_08_ST
#define SDCard_BSPIM_TxStsReg__2__MASK 0x04u
#define SDCard_BSPIM_TxStsReg__2__POS 2
#define SDCard_BSPIM_TxStsReg__3__MASK 0x08u
@@ -494,9 +496,9 @@
#define SDCard_BSPIM_TxStsReg__4__MASK 0x10u
#define SDCard_BSPIM_TxStsReg__4__POS 4
#define SDCard_BSPIM_TxStsReg__MASK 0x1Fu
-#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB04_MSK
-#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
-#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB04_ST
+#define SDCard_BSPIM_TxStsReg__MASK_REG CYREG_B0_UDB07_MSK
+#define SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG CYREG_B0_UDB07_ACTL
+#define SDCard_BSPIM_TxStsReg__STATUS_REG CYREG_B0_UDB07_ST
/* SD_SCK */
#define SD_SCK__0__INTTYPE CYREG_PICU3_INTTYPE2
@@ -1906,15 +1908,15 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__0__POS 0
#define SCSI_Out_Bits_Sync_ctrl_reg__1__MASK 0x02u
#define SCSI_Out_Bits_Sync_ctrl_reg__1__POS 1
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB02_03_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB02_03_MSK
-#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB02_03_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB03_04_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB03_04_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB03_04_MSK
#define SCSI_Out_Bits_Sync_ctrl_reg__2__MASK 0x04u
#define SCSI_Out_Bits_Sync_ctrl_reg__2__POS 2
#define SCSI_Out_Bits_Sync_ctrl_reg__3__MASK 0x08u
@@ -1927,37 +1929,37 @@
#define SCSI_Out_Bits_Sync_ctrl_reg__6__POS 6
#define SCSI_Out_Bits_Sync_ctrl_reg__7__MASK 0x80u
#define SCSI_Out_Bits_Sync_ctrl_reg__7__POS 7
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB02_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB02_CTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB02_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB03_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB03_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB03_ST_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB03_CTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB03_ST_CTL
#define SCSI_Out_Bits_Sync_ctrl_reg__MASK 0xFFu
-#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB02_MSK
+#define SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB03_MSK_ACTL
+#define SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK 0x01u
#define SCSI_Out_Ctl_Sync_ctrl_reg__0__POS 0
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB01_02_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB01_02_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB01_02_MSK
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB01_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB01_ST_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB01_CTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB01_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG CYREG_B0_UDB04_05_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG CYREG_B0_UDB04_05_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG CYREG_B0_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG CYREG_B0_UDB04_ST_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG CYREG_B0_UDB04_CTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG CYREG_B0_UDB04_ST_CTL
#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK 0x01u
-#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB01_MSK_ACTL
-#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB01_MSK
+#define SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
#define SCSI_Out_DBx__0__AG CYREG_PRT5_AG
@@ -2785,8 +2787,8 @@
#define scsiTarget_StatusReg__0__POS 0
#define scsiTarget_StatusReg__1__MASK 0x02u
#define scsiTarget_StatusReg__1__POS 1
-#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB03_04_ACTL
-#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB03_04_ST
+#define scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB04_05_ACTL
+#define scsiTarget_StatusReg__16BIT_STATUS_REG CYREG_B0_UDB04_05_ST
#define scsiTarget_StatusReg__2__MASK 0x04u
#define scsiTarget_StatusReg__2__POS 2
#define scsiTarget_StatusReg__3__MASK 0x08u
@@ -2794,9 +2796,13 @@
#define scsiTarget_StatusReg__4__MASK 0x10u
#define scsiTarget_StatusReg__4__POS 4
#define scsiTarget_StatusReg__MASK 0x1Fu
-#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB03_MSK
-#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB03_ACTL
-#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB03_ST
+#define scsiTarget_StatusReg__MASK_REG CYREG_B0_UDB04_MSK
+#define scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_StatusReg__PER_ST_AUX_CTL_REG CYREG_B0_UDB04_MSK_ACTL
+#define scsiTarget_StatusReg__STATUS_AUX_CTL_REG CYREG_B0_UDB04_ACTL
+#define scsiTarget_StatusReg__STATUS_CNT_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_StatusReg__STATUS_CONTROL_REG CYREG_B0_UDB04_ST_CTL
+#define scsiTarget_StatusReg__STATUS_REG CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
#define Debug_Timer_Interrupt__INTC_CLR_EN_REG CYREG_NVIC_CLRENA0
@@ -2917,8 +2923,8 @@
#define SCSI_Filtered_sts_sts_reg__0__POS 0
#define SCSI_Filtered_sts_sts_reg__1__MASK 0x02u
#define SCSI_Filtered_sts_sts_reg__1__POS 1
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB02_03_ACTL
-#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB02_03_ST
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB08_09_ACTL
+#define SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB08_09_ST
#define SCSI_Filtered_sts_sts_reg__2__MASK 0x04u
#define SCSI_Filtered_sts_sts_reg__2__POS 2
#define SCSI_Filtered_sts_sts_reg__3__MASK 0x08u
@@ -2926,13 +2932,9 @@
#define SCSI_Filtered_sts_sts_reg__4__MASK 0x10u
#define SCSI_Filtered_sts_sts_reg__4__POS 4
#define SCSI_Filtered_sts_sts_reg__MASK 0x1Fu
-#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB02_MSK
-#define SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG CYREG_B0_UDB02_MSK_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB02_ACTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG CYREG_B0_UDB02_ST_CTL
-#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB02_ST
+#define SCSI_Filtered_sts_sts_reg__MASK_REG CYREG_B0_UDB08_MSK
+#define SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB08_ACTL
+#define SCSI_Filtered_sts_sts_reg__STATUS_REG CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
#define SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK 0x01u
@@ -2985,12 +2987,12 @@
/* SCSI_Parity_Error */
#define SCSI_Parity_Error_sts_sts_reg__0__MASK 0x01u
#define SCSI_Parity_Error_sts_sts_reg__0__POS 0
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB11_12_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB11_12_ST
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG CYREG_B0_UDB05_06_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG CYREG_B0_UDB05_06_ST
#define SCSI_Parity_Error_sts_sts_reg__MASK 0x01u
-#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB11_MSK
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB11_ACTL
-#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB11_ST
+#define SCSI_Parity_Error_sts_sts_reg__MASK_REG CYREG_B0_UDB05_MSK
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG CYREG_B0_UDB05_ACTL
+#define SCSI_Parity_Error_sts_sts_reg__STATUS_REG CYREG_B0_UDB05_ST
/* Miscellaneous */
#define BCLK__BUS_CLK__HZ 50000000U
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
index 73329e6..78e948b 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitter_cfg.c
@@ -122,7 +122,7 @@ static void CyClockStartupError(uint8 errorCode)
}
#endif
-#define CY_CFG_BASE_ADDR_COUNT 41u
+#define CY_CFG_BASE_ADDR_COUNT 42u
CYPACKED typedef struct
{
uint8 offset;
@@ -384,41 +384,42 @@ void cyfitter_cfg(void)
0x4000520Eu, /* Base address: 0x40005200 Count: 14 */
0x40006401u, /* Base address: 0x40006400 Count: 1 */
0x40006501u, /* Base address: 0x40006500 Count: 1 */
- 0x40010042u, /* Base address: 0x40010000 Count: 66 */
- 0x40010143u, /* Base address: 0x40010100 Count: 67 */
- 0x4001023Fu, /* Base address: 0x40010200 Count: 63 */
- 0x40010351u, /* Base address: 0x40010300 Count: 81 */
- 0x40010448u, /* Base address: 0x40010400 Count: 72 */
- 0x40010550u, /* Base address: 0x40010500 Count: 80 */
- 0x40010653u, /* Base address: 0x40010600 Count: 83 */
- 0x40010751u, /* Base address: 0x40010700 Count: 81 */
- 0x40010911u, /* Base address: 0x40010900 Count: 17 */
- 0x40010A4Du, /* Base address: 0x40010A00 Count: 77 */
- 0x40010B50u, /* Base address: 0x40010B00 Count: 80 */
- 0x40010C4Cu, /* Base address: 0x40010C00 Count: 76 */
- 0x40010D57u, /* Base address: 0x40010D00 Count: 87 */
- 0x40010E50u, /* Base address: 0x40010E00 Count: 80 */
- 0x40010F3Du, /* Base address: 0x40010F00 Count: 61 */
- 0x40011420u, /* Base address: 0x40011400 Count: 32 */
- 0x40011545u, /* Base address: 0x40011500 Count: 69 */
- 0x40011652u, /* Base address: 0x40011600 Count: 82 */
- 0x40011748u, /* Base address: 0x40011700 Count: 72 */
+ 0x4001003Fu, /* Base address: 0x40010000 Count: 63 */
+ 0x4001013Fu, /* Base address: 0x40010100 Count: 63 */
+ 0x40010247u, /* Base address: 0x40010200 Count: 71 */
+ 0x40010358u, /* Base address: 0x40010300 Count: 88 */
+ 0x40010451u, /* Base address: 0x40010400 Count: 81 */
+ 0x40010555u, /* Base address: 0x40010500 Count: 85 */
+ 0x4001064Cu, /* Base address: 0x40010600 Count: 76 */
+ 0x4001074Cu, /* Base address: 0x40010700 Count: 76 */
+ 0x4001084Bu, /* Base address: 0x40010800 Count: 75 */
+ 0x4001094Bu, /* Base address: 0x40010900 Count: 75 */
+ 0x40010A50u, /* Base address: 0x40010A00 Count: 80 */
+ 0x40010B56u, /* Base address: 0x40010B00 Count: 86 */
+ 0x40010C47u, /* Base address: 0x40010C00 Count: 71 */
+ 0x40010D51u, /* Base address: 0x40010D00 Count: 81 */
+ 0x40010E4Fu, /* Base address: 0x40010E00 Count: 79 */
+ 0x40010F45u, /* Base address: 0x40010F00 Count: 69 */
+ 0x4001140Eu, /* Base address: 0x40011400 Count: 14 */
+ 0x40011547u, /* Base address: 0x40011500 Count: 71 */
+ 0x4001164Eu, /* Base address: 0x40011600 Count: 78 */
+ 0x40011743u, /* Base address: 0x40011700 Count: 67 */
0x40011804u, /* Base address: 0x40011800 Count: 4 */
- 0x40011908u, /* Base address: 0x40011900 Count: 8 */
- 0x40011B04u, /* Base address: 0x40011B00 Count: 4 */
- 0x4001401Au, /* Base address: 0x40014000 Count: 26 */
+ 0x40011910u, /* Base address: 0x40011900 Count: 16 */
+ 0x40011B09u, /* Base address: 0x40011B00 Count: 9 */
+ 0x40014018u, /* Base address: 0x40014000 Count: 24 */
0x40014117u, /* Base address: 0x40014100 Count: 23 */
- 0x4001420Eu, /* Base address: 0x40014200 Count: 14 */
- 0x40014307u, /* Base address: 0x40014300 Count: 7 */
+ 0x40014210u, /* Base address: 0x40014200 Count: 16 */
+ 0x4001430Bu, /* Base address: 0x40014300 Count: 11 */
0x4001440Eu, /* Base address: 0x40014400 Count: 14 */
- 0x4001451Bu, /* Base address: 0x40014500 Count: 27 */
+ 0x40014519u, /* Base address: 0x40014500 Count: 25 */
0x40014612u, /* Base address: 0x40014600 Count: 18 */
- 0x4001470Eu, /* Base address: 0x40014700 Count: 14 */
- 0x40014807u, /* Base address: 0x40014800 Count: 7 */
- 0x40014909u, /* Base address: 0x40014900 Count: 9 */
- 0x40014C05u, /* Base address: 0x40014C00 Count: 5 */
- 0x40014D0Eu, /* Base address: 0x40014D00 Count: 14 */
- 0x40015002u, /* Base address: 0x40015000 Count: 2 */
+ 0x40014712u, /* Base address: 0x40014700 Count: 18 */
+ 0x40014805u, /* Base address: 0x40014800 Count: 5 */
+ 0x4001490Du, /* Base address: 0x40014900 Count: 13 */
+ 0x40014C04u, /* Base address: 0x40014C00 Count: 4 */
+ 0x40014D0Bu, /* Base address: 0x40014D00 Count: 11 */
+ 0x40015004u, /* Base address: 0x40015000 Count: 4 */
0x40015104u, /* Base address: 0x40015100 Count: 4 */
};
@@ -426,53 +427,54 @@ void cyfitter_cfg(void)
{0x7Eu, 0x02u},
{0x01u, 0x20u},
{0x0Au, 0x36u},
- {0x00u, 0x04u},
- {0x01u, 0x41u},
+ {0x00u, 0x48u},
+ {0x01u, 0x04u},
{0x04u, 0x31u},
- {0x10u, 0x0Cu},
+ {0x10u, 0xC8u},
{0x11u, 0x44u},
+ {0x18u, 0x08u},
{0x19u, 0x04u},
{0x1Cu, 0x30u},
{0x20u, 0x10u},
{0x24u, 0x44u},
- {0x28u, 0x01u},
- {0x29u, 0x03u},
+ {0x29u, 0x01u},
{0x30u, 0x20u},
{0x31u, 0x30u},
{0x7Cu, 0x40u},
{0x20u, 0x01u},
- {0x86u, 0x0Fu},
- {0x01u, 0x01u},
- {0x03u, 0x02u},
- {0x06u, 0x08u},
- {0x09u, 0x24u},
+ {0x84u, 0x0Fu},
+ {0x03u, 0x70u},
+ {0x06u, 0xFFu},
+ {0x07u, 0x80u},
+ {0x08u, 0xFFu},
{0x0Bu, 0x08u},
- {0x0Cu, 0x99u},
- {0x0Eu, 0x22u},
- {0x0Fu, 0x1Du},
- {0x12u, 0x07u},
- {0x13u, 0x20u},
- {0x14u, 0xAAu},
- {0x15u, 0x10u},
- {0x16u, 0x55u},
- {0x17u, 0x20u},
- {0x1Au, 0x70u},
- {0x1Fu, 0x02u},
- {0x26u, 0x80u},
- {0x28u, 0x44u},
- {0x29u, 0x28u},
- {0x2Au, 0x88u},
- {0x2Bu, 0x14u},
- {0x30u, 0x0Fu},
- {0x31u, 0x3Cu},
- {0x34u, 0xF0u},
- {0x35u, 0x03u},
- {0x3Fu, 0x10u},
- {0x40u, 0x63u},
- {0x41u, 0x05u},
+ {0x0Eu, 0xFFu},
+ {0x10u, 0xFFu},
+ {0x17u, 0x07u},
+ {0x1Au, 0xFFu},
+ {0x1Cu, 0x69u},
+ {0x1Eu, 0x96u},
+ {0x20u, 0x55u},
+ {0x22u, 0xAAu},
+ {0x25u, 0x44u},
+ {0x27u, 0x88u},
+ {0x28u, 0x33u},
+ {0x29u, 0xAAu},
+ {0x2Au, 0xCCu},
+ {0x2Bu, 0x55u},
+ {0x2Cu, 0x0Fu},
+ {0x2Du, 0x99u},
+ {0x2Eu, 0xF0u},
+ {0x2Fu, 0x22u},
+ {0x30u, 0xFFu},
+ {0x31u, 0xF0u},
+ {0x33u, 0x0Fu},
+ {0x3Au, 0x02u},
+ {0x40u, 0x36u},
+ {0x41u, 0x04u},
{0x42u, 0x10u},
- {0x45u, 0xC2u},
- {0x46u, 0xEDu},
+ {0x45u, 0x2Cu},
+ {0x46u, 0xDEu},
{0x47u, 0x0Fu},
{0x48u, 0x1Fu},
{0x49u, 0xFFu},
@@ -493,460 +495,1329 @@ void cyfitter_cfg(void)
{0x68u, 0x40u},
{0x69u, 0x40u},
{0x6Eu, 0x08u},
+ {0x8Du, 0x01u},
+ {0x8Fu, 0x02u},
+ {0x9Fu, 0x01u},
+ {0xA7u, 0x02u},
+ {0xAEu, 0x01u},
+ {0xB2u, 0x01u},
+ {0xB7u, 0x03u},
+ {0xBFu, 0x40u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x28u},
+ {0x03u, 0x02u},
+ {0x04u, 0x80u},
+ {0x06u, 0x01u},
+ {0x08u, 0x02u},
+ {0x09u, 0x50u},
+ {0x10u, 0x08u},
+ {0x12u, 0x41u},
+ {0x15u, 0x80u},
+ {0x18u, 0x80u},
+ {0x1Fu, 0x08u},
+ {0x21u, 0x01u},
+ {0x22u, 0x04u},
+ {0x23u, 0x80u},
+ {0x26u, 0x40u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x12u},
+ {0x2Cu, 0x20u},
+ {0x30u, 0x04u},
+ {0x32u, 0x04u},
+ {0x37u, 0x80u},
+ {0x39u, 0x16u},
+ {0x3Bu, 0x02u},
+ {0x3Du, 0x40u},
+ {0x40u, 0x10u},
+ {0x43u, 0x82u},
+ {0x48u, 0x10u},
+ {0x49u, 0x26u},
+ {0x50u, 0x10u},
+ {0x52u, 0x18u},
+ {0x53u, 0x60u},
+ {0x58u, 0x18u},
+ {0x59u, 0x01u},
+ {0x5Bu, 0x40u},
+ {0x60u, 0x40u},
+ {0x61u, 0x08u},
+ {0x62u, 0xA0u},
+ {0x69u, 0x14u},
+ {0x6Au, 0x82u},
+ {0x70u, 0x01u},
+ {0x72u, 0x20u},
+ {0x73u, 0x06u},
+ {0x80u, 0x40u},
+ {0x81u, 0x01u},
+ {0x82u, 0x20u},
+ {0x84u, 0x18u},
+ {0x85u, 0x40u},
+ {0x88u, 0x08u},
+ {0x8Bu, 0x02u},
+ {0x8Cu, 0x11u},
+ {0xC0u, 0x07u},
+ {0xC2u, 0x0Bu},
+ {0xC4u, 0x8Bu},
+ {0xCAu, 0x4Eu},
+ {0xCCu, 0x12u},
+ {0xCEu, 0x17u},
+ {0xD0u, 0x0Bu},
+ {0xD2u, 0x04u},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x0Fu},
+ {0xE2u, 0x06u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x4Fu},
+ {0x04u, 0x09u},
+ {0x05u, 0x01u},
+ {0x06u, 0x06u},
+ {0x08u, 0x50u},
+ {0x09u, 0x0Fu},
+ {0x0Au, 0xA0u},
+ {0x0Bu, 0x10u},
+ {0x0Cu, 0xFFu},
+ {0x10u, 0x90u},
+ {0x12u, 0x60u},
+ {0x13u, 0x02u},
+ {0x14u, 0x05u},
+ {0x16u, 0x0Au},
+ {0x17u, 0x07u},
+ {0x18u, 0x30u},
+ {0x19u, 0x07u},
+ {0x1Au, 0xC0u},
+ {0x1Bu, 0x18u},
+ {0x20u, 0x03u},
+ {0x22u, 0x0Cu},
+ {0x24u, 0xFFu},
+ {0x25u, 0x05u},
+ {0x29u, 0x0Au},
+ {0x2Au, 0xFFu},
+ {0x2Bu, 0x15u},
+ {0x2Cu, 0x0Fu},
+ {0x2Du, 0x08u},
+ {0x2Eu, 0xF0u},
+ {0x2Fu, 0x16u},
+ {0x33u, 0x1Fu},
+ {0x34u, 0xFFu},
+ {0x3Bu, 0x08u},
+ {0x3Eu, 0x10u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Cu, 0x10u},
+ {0x5Fu, 0x01u},
+ {0x82u, 0x04u},
+ {0x84u, 0x08u},
+ {0x88u, 0x34u},
+ {0x8Au, 0x09u},
+ {0x8Bu, 0x08u},
+ {0x8Eu, 0x20u},
{0x90u, 0x02u},
- {0x92u, 0x01u},
- {0x94u, 0x01u},
- {0x96u, 0x02u},
- {0x99u, 0x01u},
- {0xA0u, 0x02u},
+ {0x96u, 0x1Fu},
+ {0x97u, 0x70u},
+ {0x98u, 0x29u},
+ {0x9Au, 0x12u},
+ {0x9Bu, 0x07u},
+ {0x9Fu, 0x80u},
{0xA2u, 0x01u},
- {0xB2u, 0x03u},
- {0xB3u, 0x01u},
- {0xBAu, 0x08u},
+ {0xA5u, 0x44u},
+ {0xA7u, 0x88u},
+ {0xA8u, 0x21u},
+ {0xA9u, 0xAAu},
+ {0xAAu, 0x06u},
+ {0xABu, 0x55u},
+ {0xADu, 0x99u},
+ {0xAFu, 0x22u},
+ {0xB0u, 0x20u},
+ {0xB2u, 0x1Fu},
+ {0xB3u, 0xF0u},
+ {0xB5u, 0x0Fu},
+ {0xBEu, 0x01u},
+ {0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x99u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x02u, 0x02u},
- {0x03u, 0x10u},
- {0x09u, 0x04u},
- {0x0Au, 0x44u},
- {0x0Cu, 0x01u},
- {0x0Eu, 0x20u},
- {0x10u, 0x08u},
- {0x13u, 0x08u},
- {0x17u, 0x01u},
- {0x19u, 0x22u},
- {0x1Au, 0x44u},
- {0x1Eu, 0x20u},
- {0x1Fu, 0x08u},
- {0x20u, 0x40u},
- {0x21u, 0x20u},
- {0x27u, 0x20u},
- {0x2Au, 0x20u},
- {0x30u, 0x08u},
- {0x32u, 0x01u},
- {0x33u, 0x40u},
- {0x36u, 0x20u},
- {0x38u, 0x42u},
- {0x3Au, 0x50u},
- {0x41u, 0x40u},
- {0x42u, 0x20u},
- {0x44u, 0x10u},
- {0x45u, 0x08u},
- {0x48u, 0x08u},
- {0x49u, 0x04u},
- {0x4Au, 0xC2u},
- {0x4Bu, 0x04u},
- {0x51u, 0x08u},
- {0x53u, 0x50u},
- {0x58u, 0x04u},
- {0x59u, 0x01u},
- {0x5Au, 0x10u},
- {0x5Bu, 0x80u},
- {0x5Du, 0x03u},
- {0x60u, 0x0Au},
- {0x61u, 0x02u},
- {0x63u, 0x20u},
- {0x69u, 0x40u},
- {0x6Au, 0x02u},
- {0x6Bu, 0x18u},
- {0x6Cu, 0x01u},
- {0x70u, 0x20u},
+ {0x01u, 0xA2u},
+ {0x02u, 0x10u},
+ {0x04u, 0x40u},
+ {0x07u, 0x24u},
+ {0x08u, 0x02u},
+ {0x09u, 0x10u},
+ {0x0Au, 0x20u},
+ {0x0Cu, 0x24u},
+ {0x0Eu, 0x40u},
+ {0x13u, 0x12u},
+ {0x15u, 0x42u},
+ {0x16u, 0x08u},
+ {0x17u, 0x08u},
+ {0x18u, 0x10u},
+ {0x1Bu, 0x05u},
+ {0x1Cu, 0x04u},
+ {0x20u, 0x20u},
+ {0x21u, 0x28u},
+ {0x23u, 0x20u},
+ {0x27u, 0x10u},
+ {0x29u, 0x20u},
+ {0x2Bu, 0x12u},
+ {0x2Du, 0x20u},
+ {0x2Fu, 0x22u},
+ {0x31u, 0x28u},
+ {0x32u, 0x40u},
+ {0x35u, 0x0Au},
+ {0x37u, 0x10u},
+ {0x3Au, 0x20u},
+ {0x3Cu, 0x10u},
+ {0x3Du, 0x20u},
+ {0x3Eu, 0x08u},
+ {0x3Fu, 0x20u},
+ {0x49u, 0x10u},
+ {0x4Au, 0x08u},
+ {0x58u, 0x40u},
+ {0x62u, 0x40u},
+ {0x68u, 0x24u},
+ {0x69u, 0x01u},
+ {0x6Au, 0x44u},
+ {0x6Bu, 0x05u},
+ {0x70u, 0x18u},
+ {0x71u, 0x80u},
{0x72u, 0x80u},
- {0x73u, 0x12u},
- {0x80u, 0x08u},
- {0x81u, 0x01u},
- {0x84u, 0x02u},
- {0x86u, 0x12u},
- {0x8Au, 0xC0u},
- {0x8Fu, 0x20u},
- {0xC0u, 0x05u},
- {0xC2u, 0x3Eu},
- {0xC4u, 0x16u},
- {0xCAu, 0x04u},
- {0xCCu, 0x2Bu},
- {0xCEu, 0x0Du},
- {0xD0u, 0x0Au},
- {0xD2u, 0x0Cu},
- {0xD6u, 0x0Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x50u},
- {0xE2u, 0x2Eu},
- {0xE6u, 0x16u},
- {0x00u, 0x0Fu},
- {0x01u, 0x03u},
- {0x02u, 0xF0u},
- {0x03u, 0x0Cu},
- {0x04u, 0xFFu},
- {0x05u, 0xFFu},
- {0x08u, 0x05u},
- {0x09u, 0x06u},
- {0x0Au, 0x0Au},
- {0x0Bu, 0x09u},
- {0x0Cu, 0x90u},
- {0x0Eu, 0x60u},
- {0x10u, 0xFFu},
- {0x11u, 0x0Fu},
- {0x13u, 0xF0u},
- {0x15u, 0x50u},
- {0x17u, 0xA0u},
- {0x18u, 0x09u},
- {0x19u, 0x05u},
- {0x1Au, 0x06u},
- {0x1Bu, 0x0Au},
- {0x1Eu, 0xFFu},
- {0x1Fu, 0xFFu},
- {0x20u, 0x03u},
- {0x21u, 0x60u},
- {0x22u, 0x0Cu},
- {0x23u, 0x90u},
- {0x24u, 0x50u},
- {0x25u, 0x30u},
- {0x26u, 0xA0u},
- {0x27u, 0xC0u},
- {0x28u, 0x30u},
- {0x2Au, 0xC0u},
- {0x2Fu, 0xFFu},
+ {0x81u, 0x08u},
+ {0x82u, 0x10u},
+ {0x89u, 0x81u},
+ {0x8Fu, 0x10u},
+ {0x90u, 0x80u},
+ {0x91u, 0x02u},
+ {0x92u, 0x80u},
+ {0x93u, 0x86u},
+ {0x94u, 0x10u},
+ {0x95u, 0xC0u},
+ {0x98u, 0x04u},
+ {0x99u, 0xA6u},
+ {0x9Au, 0x30u},
+ {0x9Cu, 0x02u},
+ {0x9Du, 0x08u},
+ {0x9Eu, 0x40u},
+ {0x9Fu, 0x40u},
+ {0xA2u, 0x08u},
+ {0xA3u, 0x28u},
+ {0xA4u, 0x20u},
+ {0xA5u, 0x10u},
+ {0xA6u, 0x80u},
+ {0xA7u, 0x92u},
+ {0xA9u, 0x20u},
+ {0xACu, 0x10u},
+ {0xADu, 0x80u},
+ {0xAEu, 0x40u},
+ {0xB2u, 0x01u},
+ {0xB4u, 0x10u},
+ {0xB5u, 0x08u},
+ {0xC0u, 0xEFu},
+ {0xC2u, 0x7Eu},
+ {0xC4u, 0xFAu},
+ {0xCAu, 0x7Eu},
+ {0xCCu, 0xEEu},
+ {0xCEu, 0x64u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x08u},
+ {0xE2u, 0x08u},
+ {0xE6u, 0x64u},
+ {0xE8u, 0x08u},
+ {0xEAu, 0x04u},
+ {0xECu, 0x02u},
+ {0xEEu, 0x01u},
+ {0x00u, 0xFFu},
+ {0x04u, 0x50u},
+ {0x05u, 0x05u},
+ {0x06u, 0xA0u},
+ {0x07u, 0x0Au},
+ {0x08u, 0x06u},
+ {0x09u, 0x0Fu},
+ {0x0Au, 0x09u},
+ {0x0Cu, 0x0Fu},
+ {0x0Du, 0x03u},
+ {0x0Eu, 0xF0u},
+ {0x0Fu, 0x0Cu},
+ {0x13u, 0x70u},
+ {0x14u, 0x05u},
+ {0x16u, 0x0Au},
+ {0x18u, 0x30u},
+ {0x1Au, 0xC0u},
+ {0x1Cu, 0x03u},
+ {0x1Du, 0x10u},
+ {0x1Eu, 0x0Cu},
+ {0x1Fu, 0x2Fu},
+ {0x20u, 0x60u},
+ {0x22u, 0x90u},
+ {0x25u, 0x40u},
+ {0x26u, 0xFFu},
+ {0x27u, 0x1Fu},
+ {0x29u, 0x20u},
+ {0x2Au, 0xFFu},
+ {0x2Bu, 0x4Fu},
+ {0x2Du, 0x06u},
+ {0x2Fu, 0x09u},
{0x30u, 0xFFu},
- {0x31u, 0xFFu},
+ {0x31u, 0x7Fu},
{0x3Eu, 0x01u},
- {0x3Fu, 0x01u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
+ {0x5Cu, 0x10u},
{0x5Fu, 0x01u},
- {0x82u, 0x20u},
- {0x86u, 0x07u},
- {0x88u, 0x07u},
- {0x8Au, 0x18u},
- {0x8Cu, 0x28u},
- {0x8Eu, 0x16u},
- {0x90u, 0x05u},
- {0x94u, 0x2Au},
- {0x96u, 0x15u},
- {0x9Au, 0x02u},
- {0x9Cu, 0x01u},
- {0xA8u, 0x2Fu},
- {0xAAu, 0x10u},
- {0xB0u, 0x20u},
- {0xB2u, 0x1Fu},
- {0xBAu, 0x08u},
- {0xBEu, 0x01u},
+ {0x80u, 0x10u},
+ {0x84u, 0x10u},
+ {0x85u, 0x50u},
+ {0x87u, 0xA0u},
+ {0x88u, 0x0Au},
+ {0x8Au, 0x05u},
+ {0x8Bu, 0xFFu},
+ {0x8Du, 0x0Fu},
+ {0x8Eu, 0x07u},
+ {0x8Fu, 0xF0u},
+ {0x91u, 0x60u},
+ {0x93u, 0x90u},
+ {0x94u, 0x10u},
+ {0x95u, 0x05u},
+ {0x97u, 0x0Au},
+ {0x99u, 0xFFu},
+ {0x9Au, 0x08u},
+ {0x9Fu, 0xFFu},
+ {0xA0u, 0x09u},
+ {0xA2u, 0x02u},
+ {0xA4u, 0x04u},
+ {0xA5u, 0x30u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0xC0u},
+ {0xA8u, 0x10u},
+ {0xA9u, 0x06u},
+ {0xABu, 0x09u},
+ {0xADu, 0x03u},
+ {0xAFu, 0x0Cu},
+ {0xB2u, 0x10u},
+ {0xB5u, 0xFFu},
+ {0xB6u, 0x0Fu},
+ {0xB8u, 0x08u},
+ {0xBEu, 0x04u},
+ {0xBFu, 0x10u},
+ {0xD4u, 0x01u},
{0xD8u, 0x04u},
+ {0xD9u, 0x04u},
{0xDBu, 0x04u},
{0xDCu, 0x01u},
+ {0xDDu, 0x10u},
{0xDFu, 0x01u},
- {0x02u, 0xA2u},
- {0x03u, 0x08u},
- {0x04u, 0x06u},
- {0x05u, 0x21u},
+ {0x00u, 0x28u},
+ {0x01u, 0x40u},
+ {0x02u, 0x80u},
+ {0x04u, 0x04u},
+ {0x05u, 0x61u},
{0x06u, 0x02u},
- {0x07u, 0x01u},
- {0x08u, 0x01u},
- {0x09u, 0x04u},
- {0x0Bu, 0x87u},
- {0x0Du, 0x10u},
- {0x0Eu, 0x80u},
- {0x0Fu, 0x01u},
- {0x10u, 0x08u},
- {0x15u, 0x01u},
- {0x17u, 0x14u},
- {0x1Bu, 0x09u},
- {0x1Du, 0x02u},
- {0x24u, 0x80u},
- {0x2Eu, 0x06u},
+ {0x08u, 0x04u},
+ {0x0Au, 0x44u},
+ {0x0Bu, 0x82u},
+ {0x0Eu, 0x20u},
+ {0x0Fu, 0x04u},
+ {0x11u, 0x12u},
+ {0x13u, 0x08u},
+ {0x14u, 0x20u},
+ {0x16u, 0x40u},
+ {0x17u, 0x20u},
+ {0x19u, 0x01u},
+ {0x1Du, 0x40u},
+ {0x1Fu, 0x04u},
+ {0x21u, 0x02u},
+ {0x23u, 0x40u},
+ {0x26u, 0x10u},
+ {0x28u, 0x22u},
+ {0x29u, 0x20u},
+ {0x2Cu, 0x20u},
+ {0x2Eu, 0x20u},
{0x2Fu, 0x01u},
- {0x35u, 0x21u},
- {0x36u, 0x40u},
- {0x37u, 0x04u},
- {0x3Cu, 0x04u},
- {0x3Du, 0x11u},
- {0x58u, 0x99u},
- {0x5Cu, 0x42u},
- {0x5Du, 0x04u},
- {0x5Eu, 0x20u},
+ {0x30u, 0x80u},
+ {0x31u, 0x02u},
+ {0x34u, 0x04u},
+ {0x36u, 0xA0u},
+ {0x37u, 0x01u},
+ {0x38u, 0x80u},
+ {0x39u, 0x10u},
+ {0x3Au, 0x08u},
+ {0x3Bu, 0x20u},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0x50u},
+ {0x45u, 0x01u},
+ {0x47u, 0x01u},
+ {0x59u, 0x16u},
+ {0x5Au, 0x40u},
+ {0x5Fu, 0x40u},
{0x63u, 0x02u},
- {0x65u, 0x40u},
- {0x6Du, 0x02u},
- {0x6Eu, 0x04u},
- {0x6Fu, 0x55u},
- {0x75u, 0x90u},
- {0x76u, 0xB0u},
- {0x80u, 0x01u},
- {0x82u, 0x80u},
- {0x86u, 0x10u},
- {0x88u, 0x04u},
- {0x8Cu, 0x08u},
- {0x8Du, 0x04u},
- {0x8Eu, 0x90u},
- {0x90u, 0x02u},
- {0x91u, 0x45u},
- {0x93u, 0xB4u},
- {0x95u, 0x80u},
- {0x96u, 0x10u},
- {0x98u, 0x10u},
- {0x99u, 0x24u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x02u},
- {0x9Cu, 0x04u},
- {0x9Fu, 0xC0u},
- {0xA0u, 0x20u},
- {0xA1u, 0x04u},
- {0xA2u, 0x82u},
- {0xA4u, 0x08u},
- {0xA6u, 0x20u},
- {0xA9u, 0x06u},
- {0xAAu, 0x20u},
- {0xABu, 0x10u},
- {0xAFu, 0x41u},
- {0xB0u, 0x01u},
- {0xB1u, 0x24u},
- {0xB3u, 0x08u},
+ {0x69u, 0x40u},
+ {0x83u, 0x40u},
+ {0x84u, 0x80u},
+ {0x86u, 0x40u},
+ {0x87u, 0x12u},
+ {0x8Bu, 0x04u},
+ {0x8Fu, 0x80u},
+ {0x90u, 0xA4u},
+ {0x92u, 0x04u},
+ {0x93u, 0xA6u},
+ {0x95u, 0xC0u},
+ {0x97u, 0x10u},
+ {0x98u, 0x04u},
+ {0x99u, 0x34u},
+ {0x9Au, 0x80u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x40u},
+ {0x9Fu, 0x48u},
+ {0xA0u, 0x3Cu},
+ {0xA1u, 0x20u},
+ {0xA3u, 0x2Du},
+ {0xA7u, 0x82u},
+ {0xA8u, 0x40u},
+ {0xACu, 0x02u},
+ {0xAEu, 0xC0u},
+ {0xB2u, 0x08u},
+ {0xB3u, 0x12u},
+ {0xB5u, 0x40u},
{0xC0u, 0xFFu},
- {0xC2u, 0xDFu},
- {0xC4u, 0x72u},
- {0xCAu, 0xD0u},
- {0xCCu, 0xF0u},
- {0xCEu, 0xE0u},
- {0xD6u, 0xFFu},
- {0xD8u, 0x18u},
- {0xE0u, 0x01u},
- {0xE2u, 0x0Au},
- {0xE4u, 0x04u},
- {0xE6u, 0x0Au},
- {0xE8u, 0x08u},
- {0xEAu, 0x07u},
- {0xEEu, 0x01u},
- {0x03u, 0x70u},
- {0x04u, 0x05u},
- {0x06u, 0x0Au},
- {0x0Bu, 0x80u},
- {0x0Cu, 0x10u},
- {0x0Eu, 0x2Fu},
- {0x0Fu, 0x08u},
- {0x10u, 0x40u},
- {0x11u, 0x99u},
- {0x12u, 0x1Fu},
- {0x13u, 0x22u},
- {0x17u, 0x07u},
- {0x19u, 0xAAu},
- {0x1Au, 0x70u},
- {0x1Bu, 0x55u},
- {0x1Cu, 0x06u},
- {0x1Eu, 0x09u},
- {0x20u, 0x0Fu},
- {0x24u, 0x20u},
- {0x26u, 0x4Fu},
- {0x28u, 0x03u},
- {0x2Au, 0x0Cu},
- {0x2Du, 0x44u},
- {0x2Fu, 0x88u},
- {0x31u, 0xF0u},
- {0x33u, 0x0Fu},
- {0x34u, 0x7Fu},
- {0x54u, 0x09u},
- {0x56u, 0x04u},
+ {0xC2u, 0x67u},
+ {0xC4u, 0x7Eu},
+ {0xCAu, 0x7Eu},
+ {0xCCu, 0xF9u},
+ {0xCEu, 0x7Eu},
+ {0xD6u, 0x1Fu},
+ {0xD8u, 0x08u},
+ {0xE2u, 0x08u},
+ {0xE6u, 0x05u},
+ {0xE8u, 0x0Cu},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x1Eu},
+ {0x05u, 0x50u},
+ {0x07u, 0xA0u},
+ {0x0Au, 0x10u},
+ {0x0Bu, 0xFFu},
+ {0x0Du, 0x0Fu},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0xF0u},
+ {0x11u, 0x90u},
+ {0x13u, 0x60u},
+ {0x15u, 0x05u},
+ {0x17u, 0x0Au},
+ {0x1Au, 0x01u},
+ {0x1Bu, 0xFFu},
+ {0x1Eu, 0x05u},
+ {0x1Fu, 0xFFu},
+ {0x22u, 0x03u},
+ {0x24u, 0x06u},
+ {0x25u, 0x30u},
+ {0x27u, 0xC0u},
+ {0x29u, 0x09u},
+ {0x2Bu, 0x06u},
+ {0x2Cu, 0x08u},
+ {0x2Du, 0x03u},
+ {0x2Eu, 0x10u},
+ {0x2Fu, 0x0Cu},
+ {0x33u, 0xFFu},
+ {0x34u, 0x07u},
+ {0x36u, 0x18u},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x04u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x10u},
+ {0x84u, 0x01u},
+ {0x88u, 0x40u},
+ {0x89u, 0x60u},
+ {0x8Bu, 0x90u},
+ {0x8Cu, 0x87u},
+ {0x8Du, 0x0Fu},
+ {0x8Eu, 0x18u},
+ {0x8Fu, 0xF0u},
+ {0x90u, 0x88u},
+ {0x92u, 0x21u},
+ {0x94u, 0x04u},
+ {0x95u, 0x50u},
+ {0x97u, 0xA0u},
+ {0x98u, 0x40u},
+ {0x99u, 0x05u},
+ {0x9Bu, 0x0Au},
+ {0x9Cu, 0x01u},
+ {0xA0u, 0x01u},
+ {0xA1u, 0x06u},
+ {0xA3u, 0x09u},
+ {0xA4u, 0x01u},
+ {0xA5u, 0x03u},
+ {0xA7u, 0x0Cu},
+ {0xA8u, 0xA2u},
+ {0xAAu, 0x08u},
+ {0xACu, 0x01u},
+ {0xADu, 0x30u},
+ {0xAFu, 0xC0u},
+ {0xB0u, 0x08u},
+ {0xB2u, 0x40u},
+ {0xB4u, 0x3Fu},
+ {0xB5u, 0xFFu},
+ {0xB6u, 0x80u},
+ {0xB8u, 0x28u},
+ {0xBEu, 0x51u},
+ {0xBFu, 0x10u},
+ {0xD4u, 0x09u},
+ {0xD6u, 0x04u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDFu, 0x01u},
+ {0x00u, 0xA0u},
+ {0x01u, 0x04u},
+ {0x02u, 0x40u},
+ {0x04u, 0x20u},
+ {0x06u, 0x02u},
+ {0x0Au, 0xA9u},
+ {0x0Eu, 0x04u},
+ {0x0Fu, 0x02u},
+ {0x10u, 0x02u},
+ {0x11u, 0x01u},
+ {0x12u, 0x08u},
+ {0x13u, 0x04u},
+ {0x15u, 0x4Au},
+ {0x19u, 0x40u},
+ {0x1Au, 0x68u},
+ {0x1Bu, 0x04u},
+ {0x1Eu, 0x04u},
+ {0x1Fu, 0x80u},
+ {0x22u, 0x20u},
+ {0x23u, 0x08u},
+ {0x27u, 0x20u},
+ {0x29u, 0x80u},
+ {0x2Au, 0x8Au},
+ {0x2Cu, 0x20u},
+ {0x2Eu, 0x20u},
+ {0x2Fu, 0x01u},
+ {0x30u, 0x08u},
+ {0x31u, 0x20u},
+ {0x34u, 0x04u},
+ {0x36u, 0xA0u},
+ {0x37u, 0x01u},
+ {0x38u, 0x20u},
+ {0x39u, 0x40u},
+ {0x3Cu, 0x08u},
+ {0x3Du, 0x50u},
+ {0x59u, 0x19u},
+ {0x5Au, 0x40u},
+ {0x61u, 0x42u},
+ {0x81u, 0x02u},
+ {0x87u, 0x81u},
+ {0x89u, 0x20u},
+ {0x90u, 0x20u},
+ {0x91u, 0x50u},
+ {0x93u, 0x02u},
+ {0x95u, 0x80u},
+ {0x98u, 0x04u},
+ {0x9Au, 0xA2u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x40u},
+ {0x9Fu, 0x28u},
+ {0xA0u, 0x2Cu},
+ {0xA1u, 0x20u},
+ {0xA3u, 0x08u},
+ {0xA6u, 0xA0u},
+ {0xA8u, 0x20u},
+ {0xABu, 0x04u},
+ {0xACu, 0x10u},
+ {0xAEu, 0x28u},
+ {0xB1u, 0x02u},
+ {0xB3u, 0x20u},
+ {0xB4u, 0x02u},
+ {0xC0u, 0xCFu},
+ {0xC2u, 0xCFu},
+ {0xC4u, 0xBFu},
+ {0xCAu, 0x7Bu},
+ {0xCCu, 0xF6u},
+ {0xCEu, 0x7Cu},
+ {0xD6u, 0x0Fu},
+ {0xD8u, 0x09u},
+ {0xE0u, 0x02u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x08u},
+ {0xE6u, 0x01u},
+ {0xEAu, 0x01u},
+ {0xECu, 0x04u},
+ {0xEEu, 0x02u},
+ {0x00u, 0x50u},
+ {0x02u, 0xA0u},
+ {0x06u, 0x20u},
+ {0x0Au, 0x08u},
+ {0x0Du, 0x01u},
+ {0x0Eu, 0x40u},
+ {0x0Fu, 0x02u},
+ {0x10u, 0x09u},
+ {0x12u, 0x02u},
+ {0x13u, 0x02u},
+ {0x16u, 0x07u},
+ {0x17u, 0x01u},
+ {0x18u, 0x04u},
+ {0x1Au, 0x08u},
+ {0x1Eu, 0x10u},
+ {0x1Fu, 0x1Cu},
+ {0x21u, 0x24u},
+ {0x22u, 0x80u},
+ {0x23u, 0x08u},
+ {0x25u, 0x10u},
+ {0x27u, 0x20u},
+ {0x28u, 0x0Au},
+ {0x29u, 0x28u},
+ {0x2Au, 0x05u},
+ {0x2Bu, 0x14u},
+ {0x2Fu, 0x20u},
+ {0x31u, 0x3Cu},
+ {0x32u, 0x0Fu},
+ {0x34u, 0xC0u},
+ {0x35u, 0x03u},
+ {0x36u, 0x30u},
+ {0x3Eu, 0x50u},
+ {0x3Fu, 0x10u},
{0x58u, 0x04u},
{0x59u, 0x04u},
{0x5Bu, 0x04u},
{0x5Cu, 0x11u},
{0x5Fu, 0x01u},
- {0x80u, 0x02u},
- {0x83u, 0x10u},
- {0x8Bu, 0x80u},
- {0x8Cu, 0x02u},
- {0x8Fu, 0x40u},
- {0x90u, 0x02u},
- {0x93u, 0x02u},
- {0x94u, 0x02u},
- {0x98u, 0x04u},
- {0x9Au, 0x08u},
- {0x9Bu, 0x08u},
- {0x9Cu, 0x08u},
- {0x9Eu, 0x04u},
- {0xA3u, 0x04u},
- {0xA5u, 0x55u},
- {0xA7u, 0xAAu},
- {0xABu, 0x01u},
- {0xACu, 0x08u},
- {0xAEu, 0x05u},
- {0xAFu, 0x20u},
- {0xB1u, 0x30u},
- {0xB2u, 0x02u},
- {0xB3u, 0xC0u},
- {0xB4u, 0x0Cu},
- {0xB5u, 0x0Cu},
- {0xB6u, 0x01u},
- {0xB7u, 0x03u},
- {0xB8u, 0x08u},
+ {0x80u, 0xFFu},
+ {0x81u, 0x02u},
+ {0x83u, 0x01u},
+ {0x86u, 0xFFu},
+ {0x88u, 0xFFu},
+ {0x8Eu, 0xFFu},
+ {0x90u, 0x96u},
+ {0x92u, 0x69u},
+ {0x94u, 0x0Fu},
+ {0x95u, 0x01u},
+ {0x96u, 0xF0u},
+ {0x97u, 0x02u},
+ {0x99u, 0x02u},
+ {0x9Bu, 0x05u},
+ {0x9Du, 0x02u},
+ {0x9Fu, 0x09u},
+ {0xA0u, 0x33u},
+ {0xA2u, 0xCCu},
+ {0xA8u, 0x55u},
+ {0xAAu, 0xAAu},
+ {0xADu, 0x02u},
+ {0xAEu, 0xFFu},
+ {0xAFu, 0x11u},
+ {0xB1u, 0x08u},
+ {0xB3u, 0x03u},
+ {0xB4u, 0xFFu},
+ {0xB5u, 0x10u},
+ {0xB7u, 0x04u},
{0xBAu, 0x20u},
- {0xBEu, 0x04u},
- {0xBFu, 0x55u},
+ {0xBBu, 0x08u},
{0xD6u, 0x08u},
{0xD8u, 0x04u},
{0xD9u, 0x04u},
{0xDBu, 0x04u},
- {0xDCu, 0x09u},
+ {0xDCu, 0x11u},
{0xDDu, 0x90u},
{0xDFu, 0x01u},
- {0x00u, 0x08u},
- {0x02u, 0x02u},
+ {0x00u, 0x4Au},
+ {0x03u, 0x08u},
{0x04u, 0x80u},
- {0x07u, 0x40u},
- {0x08u, 0x01u},
- {0x09u, 0x80u},
- {0x0Au, 0x04u},
- {0x0Du, 0x02u},
- {0x0Eu, 0x1Au},
- {0x11u, 0x28u},
- {0x12u, 0x20u},
- {0x13u, 0x01u},
- {0x14u, 0x02u},
- {0x1Au, 0x04u},
- {0x1Cu, 0x20u},
- {0x1Eu, 0x0Au},
- {0x20u, 0x80u},
- {0x21u, 0x01u},
- {0x22u, 0x04u},
- {0x23u, 0x20u},
- {0x24u, 0x20u},
- {0x25u, 0x60u},
- {0x27u, 0x80u},
- {0x28u, 0x01u},
- {0x2Du, 0x19u},
- {0x2Fu, 0x09u},
- {0x32u, 0x26u},
- {0x33u, 0x08u},
- {0x37u, 0x11u},
- {0x39u, 0x42u},
- {0x3Au, 0x02u},
- {0x3Bu, 0x10u},
- {0x3Cu, 0x80u},
- {0x3Eu, 0x21u},
- {0x58u, 0x10u},
- {0x59u, 0x04u},
- {0x5Au, 0x42u},
- {0x5Cu, 0x80u},
- {0x60u, 0x04u},
- {0x63u, 0x4Au},
- {0x64u, 0x02u},
+ {0x05u, 0x22u},
+ {0x06u, 0x90u},
+ {0x08u, 0x02u},
+ {0x0Bu, 0x10u},
+ {0x0Cu, 0xA2u},
+ {0x0Eu, 0x28u},
+ {0x10u, 0x02u},
+ {0x12u, 0x84u},
+ {0x14u, 0x04u},
+ {0x16u, 0x40u},
+ {0x1Bu, 0x10u},
+ {0x1Eu, 0x22u},
+ {0x1Fu, 0x10u},
+ {0x21u, 0x09u},
+ {0x22u, 0x50u},
+ {0x24u, 0x88u},
+ {0x27u, 0x40u},
+ {0x29u, 0x40u},
+ {0x2Cu, 0x24u},
+ {0x2Fu, 0x49u},
+ {0x31u, 0x08u},
+ {0x32u, 0x50u},
+ {0x36u, 0x02u},
+ {0x37u, 0x48u},
+ {0x39u, 0x02u},
+ {0x3Eu, 0x80u},
+ {0x4Fu, 0x30u},
+ {0x58u, 0x80u},
+ {0x5Cu, 0x20u},
+ {0x5Eu, 0x44u},
+ {0x5Fu, 0x02u},
+ {0x60u, 0x02u},
+ {0x64u, 0x01u},
{0x81u, 0x20u},
- {0x87u, 0xC0u},
- {0x88u, 0x80u},
- {0x8Au, 0x04u},
- {0x8Cu, 0x10u},
- {0x90u, 0x82u},
- {0x91u, 0x41u},
- {0x93u, 0x11u},
- {0x94u, 0x04u},
- {0x95u, 0x30u},
- {0x99u, 0xB0u},
- {0x9Au, 0xF0u},
- {0x9Bu, 0x17u},
- {0xA0u, 0x20u},
- {0xA1u, 0x07u},
- {0xA2u, 0x02u},
- {0xA6u, 0x44u},
+ {0x82u, 0x40u},
+ {0x86u, 0x10u},
+ {0x88u, 0x04u},
+ {0x8Bu, 0x0Au},
+ {0x8Cu, 0x04u},
+ {0x90u, 0x42u},
+ {0x92u, 0x04u},
+ {0x93u, 0x82u},
+ {0x95u, 0x10u},
+ {0x97u, 0x20u},
+ {0x99u, 0x62u},
+ {0x9Au, 0x04u},
+ {0xA0u, 0x07u},
+ {0xA1u, 0x20u},
+ {0xA2u, 0x84u},
+ {0xA3u, 0x08u},
+ {0xA5u, 0x08u},
+ {0xA6u, 0x10u},
+ {0xA7u, 0x10u},
{0xA8u, 0x40u},
- {0xA9u, 0x40u},
{0xAAu, 0x04u},
- {0xABu, 0x08u},
- {0xACu, 0x02u},
- {0xAEu, 0x20u},
- {0xAFu, 0x80u},
- {0xB0u, 0x88u},
- {0xB1u, 0x40u},
- {0xB3u, 0x10u},
- {0xB7u, 0x01u},
- {0xC0u, 0x95u},
- {0xC2u, 0xFBu},
- {0xC4u, 0x8Eu},
+ {0xACu, 0x44u},
+ {0xAEu, 0x01u},
+ {0xAFu, 0x20u},
+ {0xB5u, 0x84u},
+ {0xB7u, 0x10u},
+ {0xC0u, 0xFFu},
+ {0xC2u, 0xFCu},
+ {0xC4u, 0x5Bu},
{0xCAu, 0xF8u},
- {0xCCu, 0xA7u},
- {0xCEu, 0xBDu},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x19u},
- {0xE0u, 0x06u},
- {0xEAu, 0x03u},
- {0xEEu, 0x12u},
- {0x00u, 0x0Fu},
- {0x01u, 0x03u},
- {0x02u, 0xF0u},
- {0x03u, 0x0Cu},
- {0x04u, 0x30u},
- {0x06u, 0xC0u},
- {0x07u, 0xFFu},
- {0x08u, 0x05u},
- {0x0Au, 0x0Au},
- {0x0Cu, 0x90u},
- {0x0Du, 0x06u},
- {0x0Eu, 0x60u},
- {0x0Fu, 0x09u},
- {0x11u, 0x60u},
+ {0xCCu, 0xDEu},
+ {0xCEu, 0x11u},
+ {0xD6u, 0xF8u},
+ {0xD8u, 0x18u},
+ {0xE2u, 0x08u},
+ {0xE4u, 0x88u},
+ {0xE6u, 0x01u},
+ {0xEAu, 0x19u},
+ {0x00u, 0xFFu},
+ {0x06u, 0xFFu},
+ {0x08u, 0xFFu},
+ {0x09u, 0x02u},
+ {0x0Bu, 0x09u},
+ {0x0Eu, 0xFFu},
{0x12u, 0xFFu},
- {0x13u, 0x90u},
- {0x15u, 0x50u},
- {0x17u, 0xA0u},
- {0x19u, 0x30u},
- {0x1Au, 0xFFu},
- {0x1Bu, 0xC0u},
- {0x1Du, 0xFFu},
- {0x1Eu, 0xFFu},
- {0x20u, 0x03u},
- {0x22u, 0x0Cu},
- {0x23u, 0xFFu},
- {0x24u, 0x50u},
- {0x25u, 0x0Fu},
- {0x26u, 0xA0u},
- {0x27u, 0xF0u},
- {0x28u, 0x09u},
- {0x29u, 0x05u},
- {0x2Au, 0x06u},
- {0x2Bu, 0x0Au},
- {0x31u, 0xFFu},
- {0x32u, 0xFFu},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x01u},
+ {0x14u, 0x33u},
+ {0x15u, 0x02u},
+ {0x16u, 0xCCu},
+ {0x17u, 0x01u},
+ {0x19u, 0x01u},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x0Fu},
+ {0x1Du, 0x02u},
+ {0x1Eu, 0xF0u},
+ {0x1Fu, 0x05u},
+ {0x24u, 0x69u},
+ {0x26u, 0x96u},
+ {0x28u, 0x55u},
+ {0x2Au, 0xAAu},
+ {0x2Du, 0x02u},
+ {0x2Fu, 0x01u},
+ {0x33u, 0x04u},
+ {0x35u, 0x03u},
+ {0x36u, 0xFFu},
+ {0x37u, 0x08u},
+ {0x3Au, 0x80u},
+ {0x3Bu, 0x20u},
+ {0x56u, 0x08u},
{0x58u, 0x04u},
{0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
{0x5Fu, 0x01u},
- {0x81u, 0x31u},
- {0x82u, 0x07u},
+ {0x81u, 0x0Fu},
+ {0x84u, 0x40u},
+ {0x86u, 0x80u},
+ {0x87u, 0x0Fu},
+ {0x88u, 0x40u},
+ {0x89u, 0x04u},
+ {0x8Au, 0x80u},
+ {0x8Bu, 0x08u},
+ {0x8Cu, 0x06u},
+ {0x8Eu, 0xE1u},
+ {0x8Fu, 0x0Fu},
+ {0x93u, 0x0Fu},
+ {0x94u, 0xD0u},
+ {0x95u, 0x01u},
+ {0x96u, 0x21u},
+ {0x97u, 0x02u},
+ {0x99u, 0x04u},
+ {0x9Bu, 0x08u},
+ {0x9Cu, 0x16u},
+ {0x9Eu, 0xE1u},
+ {0xA0u, 0x01u},
+ {0xA2u, 0x02u},
+ {0xA3u, 0x10u},
+ {0xA4u, 0x08u},
+ {0xA6u, 0xC1u},
+ {0xA9u, 0x0Fu},
+ {0xAAu, 0x04u},
+ {0xACu, 0xC0u},
+ {0xADu, 0x01u},
+ {0xAEu, 0x21u},
+ {0xAFu, 0x02u},
+ {0xB2u, 0xC0u},
+ {0xB3u, 0x03u},
+ {0xB4u, 0x03u},
+ {0xB5u, 0x0Cu},
+ {0xB6u, 0x3Cu},
+ {0xB7u, 0x10u},
+ {0xB8u, 0x80u},
+ {0xBAu, 0x28u},
+ {0xBBu, 0x28u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x4Au},
+ {0x03u, 0x08u},
+ {0x04u, 0x50u},
+ {0x05u, 0x04u},
+ {0x08u, 0x08u},
+ {0x0Au, 0x02u},
+ {0x0Bu, 0x80u},
+ {0x0Du, 0x04u},
+ {0x0Eu, 0x02u},
+ {0x12u, 0x28u},
+ {0x14u, 0x40u},
+ {0x15u, 0x84u},
+ {0x17u, 0x10u},
+ {0x1Au, 0x02u},
+ {0x1Du, 0x04u},
+ {0x1Eu, 0x02u},
+ {0x1Fu, 0x64u},
+ {0x21u, 0x20u},
+ {0x22u, 0x44u},
+ {0x24u, 0x08u},
+ {0x25u, 0x14u},
+ {0x27u, 0x01u},
+ {0x2Au, 0x40u},
+ {0x2Du, 0x80u},
+ {0x2Eu, 0x01u},
+ {0x2Fu, 0x08u},
+ {0x31u, 0x20u},
+ {0x32u, 0x44u},
+ {0x34u, 0x08u},
+ {0x35u, 0x10u},
+ {0x36u, 0x01u},
+ {0x39u, 0x20u},
+ {0x3Cu, 0x4Au},
+ {0x3Du, 0x24u},
+ {0x41u, 0x04u},
+ {0x43u, 0x08u},
+ {0x58u, 0x94u},
+ {0x60u, 0x18u},
+ {0x61u, 0x40u},
+ {0x62u, 0x08u},
+ {0x80u, 0x04u},
+ {0x84u, 0x02u},
+ {0x87u, 0x50u},
+ {0x88u, 0x10u},
+ {0x8Fu, 0x20u},
+ {0x90u, 0x02u},
+ {0x91u, 0xA0u},
+ {0x92u, 0x05u},
+ {0x93u, 0x02u},
+ {0x95u, 0x10u},
+ {0x97u, 0x08u},
+ {0x98u, 0x80u},
+ {0x99u, 0x32u},
+ {0x9Au, 0x44u},
+ {0x9Bu, 0x10u},
+ {0x9Du, 0x40u},
+ {0x9Fu, 0x01u},
+ {0xA0u, 0x05u},
+ {0xA2u, 0xA0u},
+ {0xA3u, 0x08u},
+ {0xA5u, 0x0Cu},
+ {0xA6u, 0x11u},
+ {0xA8u, 0x81u},
+ {0xA9u, 0x80u},
+ {0xAFu, 0x0Eu},
+ {0xB0u, 0x04u},
+ {0xB1u, 0x04u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0x02u},
+ {0xB6u, 0x40u},
+ {0xB7u, 0x80u},
+ {0xC0u, 0xEFu},
+ {0xC2u, 0xADu},
+ {0xC4u, 0xF6u},
+ {0xCAu, 0xB8u},
+ {0xCCu, 0xEEu},
+ {0xCEu, 0xF4u},
+ {0xD6u, 0x0Eu},
+ {0xD8u, 0x0Eu},
+ {0xE0u, 0x80u},
+ {0xE2u, 0x40u},
+ {0xE4u, 0x02u},
+ {0xE6u, 0x04u},
+ {0xE8u, 0x40u},
+ {0xEAu, 0x20u},
+ {0xEEu, 0x11u},
+ {0x00u, 0x08u},
+ {0x02u, 0x10u},
+ {0x04u, 0x02u},
+ {0x05u, 0x01u},
+ {0x06u, 0x01u},
+ {0x0Du, 0x06u},
+ {0x0Fu, 0x18u},
+ {0x12u, 0x10u},
+ {0x15u, 0x20u},
+ {0x16u, 0x08u},
+ {0x18u, 0x01u},
+ {0x19u, 0x04u},
+ {0x1Au, 0x02u},
+ {0x1Bu, 0x02u},
+ {0x1Cu, 0x02u},
+ {0x1Du, 0x02u},
+ {0x1Eu, 0x01u},
+ {0x1Fu, 0x04u},
+ {0x20u, 0x02u},
+ {0x22u, 0x05u},
+ {0x25u, 0x08u},
+ {0x27u, 0x10u},
+ {0x28u, 0x02u},
+ {0x2Au, 0x21u},
+ {0x2Du, 0x10u},
+ {0x2Fu, 0x08u},
+ {0x30u, 0x18u},
+ {0x31u, 0x20u},
+ {0x32u, 0x04u},
+ {0x33u, 0x01u},
+ {0x34u, 0x03u},
+ {0x36u, 0x20u},
+ {0x37u, 0x1Eu},
+ {0x3Au, 0x20u},
+ {0x3Eu, 0x01u},
+ {0x3Fu, 0x40u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x91u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x84u, 0x04u},
+ {0x86u, 0x02u},
+ {0x8Du, 0x02u},
+ {0x8Fu, 0x04u},
+ {0x90u, 0x04u},
+ {0x92u, 0x03u},
+ {0x94u, 0x04u},
+ {0x96u, 0x02u},
+ {0x97u, 0x02u},
+ {0x98u, 0x02u},
+ {0x9Au, 0x04u},
+ {0x9Cu, 0x04u},
+ {0x9Eu, 0x02u},
+ {0x9Fu, 0x04u},
+ {0xAFu, 0x01u},
+ {0xB2u, 0x01u},
+ {0xB4u, 0x06u},
+ {0xB5u, 0x01u},
+ {0xB7u, 0x06u},
+ {0xBAu, 0x20u},
+ {0xBFu, 0x40u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x01u, 0x08u},
+ {0x05u, 0x06u},
+ {0x08u, 0x02u},
+ {0x0Au, 0x26u},
+ {0x0Cu, 0x02u},
+ {0x0Eu, 0x29u},
+ {0x14u, 0x08u},
+ {0x17u, 0x01u},
+ {0x1Au, 0x24u},
+ {0x1Cu, 0x08u},
+ {0x1Du, 0x05u},
+ {0x1Eu, 0x09u},
+ {0x20u, 0x02u},
+ {0x21u, 0x50u},
+ {0x23u, 0x03u},
+ {0x24u, 0x02u},
+ {0x26u, 0x08u},
+ {0x27u, 0x80u},
+ {0x2Au, 0x40u},
+ {0x2Cu, 0x02u},
+ {0x2Fu, 0x10u},
+ {0x31u, 0x48u},
+ {0x36u, 0x14u},
+ {0x37u, 0x44u},
+ {0x39u, 0x40u},
+ {0x3Cu, 0x40u},
+ {0x3Eu, 0x04u},
+ {0x58u, 0x14u},
+ {0x5Au, 0x40u},
+ {0x5Du, 0x80u},
+ {0x5Fu, 0x10u},
+ {0x62u, 0xA4u},
+ {0x64u, 0x0Au},
+ {0x69u, 0x40u},
+ {0x6Cu, 0x28u},
+ {0x6Du, 0x04u},
+ {0x6Fu, 0x12u},
+ {0x81u, 0x01u},
+ {0x82u, 0x04u},
+ {0x84u, 0x10u},
+ {0x87u, 0x02u},
+ {0x88u, 0x0Au},
+ {0x8Bu, 0x10u},
+ {0x92u, 0x02u},
+ {0x93u, 0x12u},
+ {0x95u, 0x90u},
+ {0x96u, 0x20u},
+ {0x97u, 0x21u},
+ {0x99u, 0x38u},
+ {0x9Au, 0x40u},
+ {0x9Bu, 0x40u},
+ {0x9Du, 0x02u},
+ {0x9Eu, 0x04u},
+ {0x9Fu, 0x0Cu},
+ {0xA3u, 0x08u},
+ {0xA4u, 0x20u},
+ {0xA5u, 0x04u},
+ {0xA6u, 0xA9u},
+ {0xA8u, 0x40u},
+ {0xAAu, 0x08u},
+ {0xABu, 0x08u},
+ {0xACu, 0x04u},
+ {0xADu, 0x08u},
+ {0xB1u, 0x20u},
+ {0xB4u, 0x40u},
+ {0xB5u, 0x01u},
+ {0xB6u, 0x08u},
+ {0xC0u, 0x34u},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x50u},
+ {0xCAu, 0x58u},
+ {0xCCu, 0x7Au},
+ {0xCEu, 0x58u},
+ {0xD6u, 0x3Eu},
+ {0xD8u, 0x3Eu},
+ {0xE0u, 0x24u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x22u},
+ {0xE8u, 0x32u},
+ {0xECu, 0x02u},
+ {0xEEu, 0x14u},
+ {0x02u, 0x6Fu},
+ {0x04u, 0x04u},
+ {0x06u, 0x08u},
+ {0x08u, 0x6Fu},
+ {0x0Cu, 0x20u},
+ {0x0Eu, 0x40u},
+ {0x12u, 0x6Fu},
+ {0x16u, 0x10u},
+ {0x1Au, 0x6Fu},
+ {0x1Cu, 0x6Fu},
+ {0x20u, 0x01u},
+ {0x22u, 0x02u},
+ {0x24u, 0x04u},
+ {0x26u, 0x08u},
+ {0x27u, 0x01u},
+ {0x28u, 0x20u},
+ {0x2Au, 0x40u},
+ {0x2Cu, 0x01u},
+ {0x2Eu, 0x02u},
+ {0x30u, 0x03u},
+ {0x31u, 0x01u},
+ {0x32u, 0x10u},
+ {0x34u, 0x0Cu},
+ {0x36u, 0x60u},
+ {0x3Au, 0xA2u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x11u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x80u, 0x06u},
+ {0x81u, 0xC0u},
+ {0x82u, 0xF8u},
+ {0x84u, 0xC6u},
+ {0x85u, 0x10u},
+ {0x86u, 0x19u},
+ {0x87u, 0xE0u},
+ {0x88u, 0x40u},
+ {0x8Au, 0x80u},
+ {0x8Fu, 0x20u},
+ {0x91u, 0x24u},
+ {0x92u, 0x09u},
+ {0x93u, 0xC8u},
+ {0x94u, 0x14u},
+ {0x97u, 0xC0u},
+ {0x98u, 0x01u},
+ {0x99u, 0x40u},
+ {0x9Bu, 0x80u},
+ {0x9Cu, 0xE0u},
+ {0x9Fu, 0x1Du},
+ {0xA0u, 0x40u},
+ {0xA1u, 0x01u},
+ {0xA2u, 0x80u},
+ {0xA3u, 0x02u},
+ {0xA6u, 0xFFu},
+ {0xA7u, 0x02u},
+ {0xA8u, 0x09u},
+ {0xA9u, 0xE8u},
+ {0xAAu, 0xF2u},
+ {0xABu, 0x14u},
+ {0xADu, 0x40u},
+ {0xAFu, 0x80u},
+ {0xB1u, 0x3Cu},
+ {0xB2u, 0x3Fu},
+ {0xB3u, 0x03u},
+ {0xB4u, 0xC0u},
+ {0xB5u, 0xC0u},
+ {0xBAu, 0x20u},
+ {0xBBu, 0x20u},
+ {0xBFu, 0x04u},
+ {0xD6u, 0x08u},
+ {0xD8u, 0x04u},
+ {0xD9u, 0x04u},
+ {0xDBu, 0x04u},
+ {0xDCu, 0x11u},
+ {0xDDu, 0x90u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x06u},
+ {0x01u, 0x80u},
+ {0x03u, 0x08u},
+ {0x05u, 0x05u},
+ {0x07u, 0x08u},
+ {0x08u, 0x10u},
+ {0x09u, 0x01u},
+ {0x0Au, 0x20u},
+ {0x0Bu, 0x01u},
+ {0x0Cu, 0x24u},
+ {0x0Du, 0x40u},
+ {0x0Eu, 0x40u},
+ {0x11u, 0x40u},
+ {0x12u, 0xA4u},
+ {0x14u, 0x10u},
+ {0x15u, 0x02u},
+ {0x16u, 0x08u},
+ {0x17u, 0x04u},
+ {0x18u, 0x86u},
+ {0x19u, 0x88u},
+ {0x1Bu, 0x10u},
+ {0x1Cu, 0x08u},
+ {0x1Du, 0x04u},
+ {0x1Fu, 0x08u},
+ {0x22u, 0x01u},
+ {0x25u, 0x08u},
+ {0x26u, 0x10u},
+ {0x27u, 0x40u},
+ {0x29u, 0x08u},
+ {0x2Du, 0x02u},
+ {0x2Eu, 0x80u},
+ {0x2Fu, 0x18u},
+ {0x35u, 0x01u},
+ {0x36u, 0x11u},
+ {0x37u, 0x44u},
+ {0x38u, 0x80u},
+ {0x39u, 0x40u},
+ {0x3Eu, 0x08u},
+ {0x3Fu, 0x41u},
+ {0x48u, 0x01u},
+ {0x4Au, 0x01u},
+ {0x58u, 0x40u},
+ {0x5Cu, 0x40u},
+ {0x5Du, 0x10u},
+ {0x62u, 0x40u},
+ {0x65u, 0x10u},
+ {0x66u, 0x90u},
+ {0x80u, 0x01u},
+ {0x81u, 0x04u},
+ {0x83u, 0x10u},
+ {0x84u, 0x04u},
+ {0x85u, 0x01u},
+ {0x86u, 0x90u},
+ {0x88u, 0x40u},
+ {0x8Au, 0x10u},
+ {0x8Bu, 0x50u},
+ {0x8Eu, 0x40u},
+ {0x8Fu, 0x01u},
+ {0xC0u, 0x7Fu},
+ {0xC2u, 0xFFu},
+ {0xC4u, 0x7Fu},
+ {0xCAu, 0xF2u},
+ {0xCCu, 0xF0u},
+ {0xCEu, 0xD0u},
+ {0xD6u, 0x38u},
+ {0xD8u, 0x38u},
+ {0xE0u, 0x60u},
+ {0xE4u, 0xC0u},
+ {0xE6u, 0x20u},
+ {0x8Eu, 0x38u},
+ {0x90u, 0x3Eu},
+ {0x94u, 0x01u},
+ {0x96u, 0x14u},
+ {0xA0u, 0x09u},
+ {0xA2u, 0x02u},
+ {0xA4u, 0x22u},
+ {0xA6u, 0x01u},
+ {0xB0u, 0x07u},
+ {0xB6u, 0x38u},
+ {0xB8u, 0x02u},
+ {0xBEu, 0x40u},
+ {0xD8u, 0x04u},
+ {0xDFu, 0x01u},
+ {0x00u, 0x40u},
+ {0x01u, 0x05u},
+ {0x02u, 0x08u},
+ {0x07u, 0x01u},
+ {0x0Au, 0x19u},
+ {0x0Eu, 0x90u},
+ {0x10u, 0x08u},
+ {0x12u, 0x01u},
+ {0x13u, 0x06u},
+ {0x15u, 0x0Au},
+ {0x1Au, 0x98u},
+ {0x1Bu, 0x01u},
+ {0x1Cu, 0x02u},
+ {0x1Eu, 0x80u},
+ {0x20u, 0xC0u},
+ {0x21u, 0x15u},
+ {0x22u, 0x0Au},
+ {0x23u, 0x04u},
+ {0x2Au, 0x02u},
+ {0x2Bu, 0x01u},
+ {0x30u, 0x22u},
+ {0x32u, 0x08u},
+ {0x33u, 0x40u},
+ {0x38u, 0x40u},
+ {0x39u, 0x10u},
+ {0x3Au, 0x01u},
+ {0x3Bu, 0x04u},
+ {0x42u, 0x58u},
+ {0x49u, 0x08u},
+ {0x4Au, 0x8Au},
+ {0x51u, 0x40u},
+ {0x52u, 0x51u},
+ {0x53u, 0x81u},
+ {0x60u, 0x04u},
+ {0x68u, 0x2Au},
+ {0x69u, 0x15u},
+ {0x6Au, 0x22u},
+ {0x6Bu, 0x42u},
+ {0x72u, 0x03u},
+ {0x73u, 0x01u},
+ {0x82u, 0x08u},
+ {0x84u, 0x01u},
+ {0x86u, 0x04u},
+ {0x88u, 0x40u},
+ {0x8Du, 0x10u},
+ {0x8Fu, 0x01u},
+ {0x90u, 0x04u},
+ {0x92u, 0x44u},
+ {0x94u, 0x40u},
+ {0x95u, 0xAFu},
+ {0x96u, 0xA3u},
+ {0x97u, 0x05u},
+ {0x9Bu, 0x01u},
+ {0x9Cu, 0x40u},
+ {0x9Du, 0x18u},
+ {0x9Eu, 0x52u},
+ {0xA4u, 0x42u},
+ {0xA6u, 0x88u},
+ {0xA7u, 0x81u},
+ {0xA9u, 0x80u},
+ {0xC0u, 0x8Fu},
+ {0xC2u, 0x37u},
+ {0xC4u, 0x3Fu},
+ {0xCAu, 0x09u},
+ {0xCCu, 0x0Fu},
+ {0xCEu, 0x0Fu},
+ {0xD0u, 0x07u},
+ {0xD2u, 0x0Cu},
+ {0xD8u, 0x04u},
+ {0xEAu, 0x04u},
+ {0xEEu, 0x02u},
+ {0x01u, 0x34u},
+ {0x03u, 0x43u},
+ {0x04u, 0x02u},
+ {0x05u, 0x40u},
+ {0x06u, 0x01u},
+ {0x07u, 0x30u},
+ {0x0Cu, 0x02u},
+ {0x0Du, 0x11u},
+ {0x0Eu, 0x01u},
+ {0x0Fu, 0x62u},
+ {0x13u, 0x0Cu},
+ {0x14u, 0x02u},
+ {0x15u, 0x58u},
+ {0x16u, 0x05u},
+ {0x17u, 0x23u},
+ {0x18u, 0x01u},
+ {0x1Au, 0x02u},
+ {0x23u, 0x02u},
+ {0x2Bu, 0x01u},
+ {0x2Cu, 0x02u},
+ {0x2Eu, 0x09u},
+ {0x32u, 0x04u},
+ {0x34u, 0x03u},
+ {0x35u, 0x70u},
+ {0x36u, 0x08u},
+ {0x37u, 0x0Fu},
+ {0x3Au, 0x20u},
+ {0x3Bu, 0x20u},
+ {0x56u, 0x08u},
+ {0x58u, 0x04u},
+ {0x59u, 0x04u},
+ {0x5Bu, 0x04u},
+ {0x5Cu, 0x01u},
+ {0x5Du, 0x90u},
+ {0x5Fu, 0x01u},
+ {0x81u, 0xC0u},
+ {0x82u, 0x01u},
{0x83u, 0x02u},
{0x85u, 0xC0u},
- {0x87u, 0x2Cu},
- {0x89u, 0xE4u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x99u},
- {0x8Du, 0x24u},
- {0x8Eu, 0x22u},
- {0x91u, 0x2Cu},
- {0x93u, 0xC0u},
- {0x94u, 0xAAu},
- {0x95u, 0x11u},
- {0x96u, 0x55u},
- {0x97u, 0x0Eu},
- {0x98u, 0x44u},
- {0x9Au, 0x88u},
- {0x9Bu, 0x2Fu},
- {0x9Du, 0xECu},
- {0x9Eu, 0x70u},
- {0xA2u, 0x08u},
- {0xA3u, 0x80u},
- {0xA5u, 0x08u},
- {0xA6u, 0x80u},
- {0xA7u, 0x10u},
- {0xADu, 0xECu},
- {0xB0u, 0x0Fu},
- {0xB1u, 0x40u},
- {0xB3u, 0x80u},
- {0xB5u, 0x31u},
- {0xB6u, 0xF0u},
- {0xB7u, 0x0Fu},
- {0xBBu, 0x30u},
- {0xBFu, 0x05u},
+ {0x86u, 0x04u},
+ {0x87u, 0x04u},
+ {0x89u, 0x80u},
+ {0x8Cu, 0x02u},
+ {0x8Du, 0x1Fu},
+ {0x8Eu, 0x04u},
+ {0x8Fu, 0x20u},
+ {0x91u, 0x90u},
+ {0x92u, 0x10u},
+ {0x93u, 0x40u},
+ {0x94u, 0x09u},
+ {0x95u, 0x7Fu},
+ {0x97u, 0x80u},
+ {0x99u, 0xC0u},
+ {0x9Bu, 0x08u},
+ {0x9Cu, 0x09u},
+ {0x9Fu, 0xFFu},
+ {0xA0u, 0x09u},
+ {0xA1u, 0xC0u},
+ {0xA3u, 0x01u},
+ {0xA4u, 0x09u},
+ {0xAAu, 0x02u},
+ {0xABu, 0x60u},
+ {0xAEu, 0x09u},
+ {0xAFu, 0x9Fu},
+ {0xB0u, 0x08u},
+ {0xB2u, 0x01u},
+ {0xB3u, 0xFFu},
+ {0xB4u, 0x10u},
+ {0xB6u, 0x06u},
+ {0xBEu, 0x45u},
+ {0xBFu, 0x04u},
{0xD4u, 0x40u},
{0xD6u, 0x04u},
{0xD8u, 0x04u},
@@ -954,854 +1825,119 @@ void cyfitter_cfg(void)
{0xDBu, 0x04u},
{0xDCu, 0x01u},
{0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x02u, 0x02u},
- {0x04u, 0x02u},
- {0x05u, 0x20u},
- {0x07u, 0x11u},
- {0x09u, 0x04u},
- {0x0Au, 0x05u},
- {0x0Cu, 0x40u},
- {0x0Eu, 0x80u},
- {0x0Fu, 0x09u},
- {0x10u, 0x20u},
- {0x13u, 0x02u},
- {0x15u, 0x05u},
- {0x17u, 0x24u},
- {0x19u, 0x02u},
- {0x1Au, 0x01u},
- {0x1Eu, 0x10u},
- {0x20u, 0x05u},
- {0x21u, 0x09u},
- {0x22u, 0x91u},
- {0x27u, 0x40u},
- {0x28u, 0x10u},
- {0x29u, 0x40u},
- {0x2Au, 0x05u},
- {0x2Cu, 0x40u},
- {0x2Du, 0x28u},
- {0x32u, 0x18u},
- {0x33u, 0x82u},
- {0x36u, 0x40u},
- {0x37u, 0x15u},
- {0x38u, 0x69u},
- {0x3Cu, 0x80u},
- {0x3Du, 0x01u},
- {0x3Fu, 0x08u},
- {0x45u, 0x80u},
- {0x46u, 0x01u},
- {0x61u, 0x88u},
- {0x62u, 0x20u},
- {0x63u, 0x40u},
- {0x64u, 0x80u},
- {0x65u, 0x02u},
- {0x86u, 0x04u},
- {0x89u, 0x50u},
- {0x8Au, 0x80u},
- {0x8Bu, 0x40u},
- {0x90u, 0x02u},
- {0x91u, 0x01u},
- {0x93u, 0x01u},
- {0x96u, 0x53u},
- {0x99u, 0xB8u},
- {0x9Au, 0xD2u},
- {0x9Bu, 0x37u},
- {0x9Cu, 0x10u},
- {0x9Du, 0x04u},
- {0x9Fu, 0x40u},
- {0xA0u, 0x20u},
- {0xA1u, 0x45u},
- {0xA2u, 0x02u},
- {0xA6u, 0x40u},
- {0xA7u, 0x24u},
- {0xA8u, 0x01u},
- {0xA9u, 0x18u},
- {0xACu, 0x14u},
- {0xADu, 0x10u},
- {0xAFu, 0x20u},
- {0xB0u, 0x01u},
- {0xB1u, 0x80u},
- {0xB3u, 0x21u},
- {0xB5u, 0x10u},
- {0xB7u, 0x01u},
- {0xC0u, 0xF9u},
- {0xC2u, 0xD7u},
- {0xC4u, 0x7Cu},
- {0xCAu, 0xEBu},
- {0xCCu, 0xFFu},
- {0xCEu, 0xDFu},
- {0xD8u, 0x0Fu},
- {0xE2u, 0x23u},
- {0xE8u, 0x08u},
- {0xEAu, 0x01u},
- {0xEEu, 0x02u},
- {0x80u, 0x02u},
- {0x85u, 0x40u},
- {0x9Cu, 0x02u},
- {0x9Du, 0x08u},
- {0xA1u, 0x40u},
- {0xA2u, 0x04u},
- {0xA9u, 0x40u},
- {0xAEu, 0x01u},
- {0xB1u, 0x01u},
- {0xB3u, 0x31u},
- {0xB5u, 0x20u},
- {0xE2u, 0x01u},
- {0xE4u, 0x20u},
- {0xE6u, 0x01u},
- {0xE8u, 0x08u},
- {0xEAu, 0x20u},
- {0xEEu, 0x20u},
- {0x00u, 0x33u},
- {0x02u, 0xCCu},
- {0x09u, 0xFFu},
- {0x0Au, 0xFFu},
- {0x0Cu, 0xFFu},
- {0x0Du, 0x0Fu},
- {0x0Fu, 0xF0u},
- {0x13u, 0xFFu},
- {0x14u, 0x69u},
- {0x16u, 0x96u},
- {0x17u, 0xFFu},
- {0x1Au, 0xFFu},
- {0x1Bu, 0xFFu},
- {0x1Cu, 0x0Fu},
- {0x1Eu, 0xF0u},
- {0x21u, 0x55u},
- {0x23u, 0xAAu},
- {0x24u, 0xFFu},
- {0x25u, 0x33u},
- {0x27u, 0xCCu},
- {0x28u, 0x55u},
- {0x29u, 0x69u},
- {0x2Au, 0xAAu},
- {0x2Bu, 0x96u},
- {0x2Du, 0xFFu},
- {0x2Eu, 0xFFu},
- {0x36u, 0xFFu},
- {0x37u, 0xFFu},
- {0x3Au, 0x80u},
- {0x3Bu, 0x80u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x11u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0xFFu},
- {0x83u, 0x04u},
- {0x86u, 0xFFu},
- {0x87u, 0x7Fu},
- {0x8Cu, 0x96u},
- {0x8Du, 0x20u},
- {0x8Eu, 0x69u},
- {0x8Fu, 0x40u},
- {0x90u, 0x0Fu},
- {0x91u, 0x09u},
- {0x92u, 0xF0u},
- {0x93u, 0x72u},
- {0x96u, 0xFFu},
- {0x99u, 0x74u},
- {0x9Au, 0xFFu},
- {0x9Bu, 0x09u},
- {0x9Du, 0x20u},
- {0x9Fu, 0x40u},
- {0xA0u, 0x33u},
- {0xA1u, 0x08u},
- {0xA2u, 0xCCu},
- {0xA4u, 0x55u},
- {0xA6u, 0xAAu},
- {0xA7u, 0x01u},
- {0xA8u, 0xFFu},
- {0xA9u, 0x01u},
- {0xABu, 0x66u},
- {0xADu, 0x62u},
- {0xB1u, 0x60u},
- {0xB4u, 0xFFu},
- {0xB7u, 0x1Fu},
- {0xBAu, 0x20u},
- {0xBBu, 0x02u},
- {0xD4u, 0x01u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x10u},
- {0xDFu, 0x01u},
- {0x01u, 0x80u},
- {0x02u, 0x40u},
- {0x03u, 0x08u},
- {0x04u, 0x02u},
- {0x05u, 0x40u},
- {0x07u, 0x20u},
- {0x08u, 0x08u},
- {0x0Au, 0x06u},
- {0x0Du, 0x09u},
- {0x0Eu, 0x04u},
- {0x10u, 0x10u},
- {0x11u, 0x80u},
- {0x12u, 0x04u},
- {0x15u, 0x10u},
- {0x16u, 0xA0u},
- {0x17u, 0x10u},
- {0x1Au, 0x02u},
- {0x1Fu, 0x10u},
- {0x21u, 0x40u},
- {0x24u, 0x80u},
- {0x25u, 0x40u},
- {0x27u, 0x41u},
- {0x28u, 0x20u},
- {0x29u, 0x80u},
- {0x2Bu, 0x44u},
- {0x2Cu, 0x20u},
- {0x2Du, 0x81u},
- {0x2Fu, 0x08u},
- {0x31u, 0x28u},
- {0x33u, 0x09u},
- {0x34u, 0x10u},
- {0x37u, 0x51u},
- {0x39u, 0x90u},
- {0x3Du, 0x02u},
- {0x3Eu, 0x04u},
- {0x3Fu, 0x80u},
- {0x58u, 0x82u},
- {0x59u, 0x28u},
- {0x5Fu, 0x80u},
- {0x60u, 0x20u},
- {0x61u, 0x40u},
- {0x62u, 0x08u},
- {0x63u, 0x88u},
- {0x80u, 0x80u},
- {0x8Bu, 0x80u},
- {0x90u, 0x02u},
- {0x91u, 0x01u},
- {0x92u, 0x04u},
- {0x94u, 0x80u},
- {0x98u, 0x08u},
- {0x99u, 0x80u},
- {0x9Au, 0xE4u},
- {0x9Bu, 0x10u},
- {0xA0u, 0x20u},
- {0xA1u, 0x29u},
- {0xA2u, 0x04u},
- {0xA5u, 0x40u},
- {0xA6u, 0x08u},
- {0xA7u, 0x04u},
- {0xABu, 0x20u},
- {0xAFu, 0x11u},
- {0xB0u, 0x80u},
- {0xB1u, 0x60u},
- {0xB2u, 0x10u},
- {0xB3u, 0x60u},
- {0xB4u, 0x20u},
- {0xC0u, 0xBBu},
- {0xC2u, 0x77u},
- {0xC4u, 0x77u},
- {0xCAu, 0xFFu},
- {0xCCu, 0xB7u},
- {0xCEu, 0xDCu},
- {0xD6u, 0x1Fu},
- {0xD8u, 0x0Fu},
- {0xE0u, 0x06u},
- {0xE2u, 0x20u},
- {0xE4u, 0x60u},
- {0xE6u, 0x01u},
- {0xEAu, 0x80u},
- {0xEEu, 0x30u},
- {0x01u, 0x10u},
- {0x03u, 0x20u},
- {0x04u, 0x20u},
- {0x05u, 0x10u},
- {0x06u, 0x10u},
- {0x07u, 0x20u},
- {0x08u, 0x04u},
- {0x09u, 0x02u},
- {0x0Au, 0x08u},
- {0x0Bu, 0x3Du},
- {0x0Cu, 0x20u},
- {0x0Du, 0x3Cu},
- {0x0Eu, 0x11u},
- {0x0Fu, 0x01u},
+ {0x00u, 0x08u},
+ {0x01u, 0x40u},
+ {0x02u, 0x80u},
+ {0x05u, 0x44u},
+ {0x0Au, 0x22u},
+ {0x0Bu, 0x80u},
+ {0x0Eu, 0x08u},
+ {0x0Fu, 0x20u},
+ {0x10u, 0x06u},
{0x11u, 0x04u},
- {0x13u, 0x08u},
- {0x15u, 0x04u},
- {0x17u, 0x08u},
+ {0x13u, 0x01u},
+ {0x14u, 0x02u},
{0x18u, 0x10u},
{0x19u, 0x01u},
- {0x1Au, 0x20u},
- {0x1Bu, 0x02u},
- {0x20u, 0x02u},
- {0x21u, 0x02u},
- {0x23u, 0x3Du},
- {0x26u, 0x08u},
- {0x27u, 0x3Du},
- {0x2Au, 0x04u},
- {0x2Du, 0x3Cu},
- {0x2Fu, 0x01u},
- {0x30u, 0x0Cu},
- {0x32u, 0x01u},
- {0x33u, 0x03u},
- {0x34u, 0x30u},
- {0x35u, 0x30u},
- {0x36u, 0x02u},
- {0x37u, 0x0Cu},
- {0x3Au, 0x20u},
- {0x3Bu, 0xA8u},
- {0x3Eu, 0x01u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x19u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0x08u},
- {0x82u, 0x04u},
- {0x84u, 0x04u},
- {0x85u, 0x02u},
- {0x86u, 0x09u},
- {0x87u, 0x05u},
- {0x90u, 0x08u},
- {0x92u, 0x16u},
- {0x99u, 0x02u},
- {0x9Bu, 0x01u},
- {0x9Du, 0x01u},
- {0x9Fu, 0x02u},
- {0xACu, 0x01u},
- {0xAEu, 0x02u},
- {0xB0u, 0x10u},
- {0xB4u, 0x0Cu},
- {0xB5u, 0x04u},
- {0xB6u, 0x03u},
- {0xB7u, 0x03u},
- {0xBAu, 0x20u},
- {0xBBu, 0x80u},
- {0xBEu, 0x40u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x99u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x01u, 0x02u},
- {0x03u, 0x20u},
- {0x05u, 0x54u},
- {0x08u, 0x02u},
- {0x0Eu, 0x04u},
- {0x10u, 0x02u},
- {0x15u, 0x12u},
- {0x17u, 0x04u},
- {0x18u, 0x02u},
- {0x19u, 0x82u},
- {0x1Bu, 0x60u},
- {0x1Cu, 0x80u},
- {0x1Du, 0x24u},
- {0x1Eu, 0x04u},
- {0x1Fu, 0x50u},
- {0x22u, 0xA0u},
- {0x27u, 0x29u},
- {0x2Du, 0x80u},
- {0x2Eu, 0x02u},
- {0x2Fu, 0x10u},
- {0x32u, 0xA0u},
- {0x36u, 0x08u},
- {0x37u, 0x21u},
- {0x38u, 0x04u},
- {0x3Cu, 0x20u},
- {0x3Eu, 0x41u},
- {0x3Fu, 0x08u},
- {0x45u, 0x40u},
- {0x46u, 0x02u},
- {0x5Au, 0xA8u},
- {0x5Du, 0x20u},
- {0x5Fu, 0x40u},
- {0x60u, 0x0Au},
- {0x62u, 0x04u},
- {0x66u, 0xA0u},
- {0x68u, 0x02u},
- {0x6Cu, 0x20u},
- {0x6Fu, 0x0Au},
- {0x79u, 0x10u},
- {0x7Au, 0x04u},
- {0x81u, 0x10u},
- {0x83u, 0x04u},
- {0x86u, 0x80u},
- {0x87u, 0x0Au},
- {0x88u, 0x40u},
- {0x89u, 0x20u},
- {0x8Au, 0x01u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x40u},
- {0x8Du, 0x01u},
- {0x8Eu, 0x10u},
- {0x90u, 0x04u},
- {0x91u, 0x03u},
- {0x92u, 0xC8u},
- {0x94u, 0x02u},
- {0x97u, 0xA0u},
- {0x99u, 0x40u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x10u},
- {0x9Cu, 0x08u},
- {0x9Eu, 0xB4u},
- {0xA0u, 0x10u},
- {0xA1u, 0x08u},
- {0xA2u, 0x04u},
- {0xA4u, 0xA0u},
- {0xA7u, 0x40u},
- {0xAAu, 0x78u},
- {0xADu, 0x01u},
- {0xAFu, 0x04u},
- {0xB1u, 0x01u},
- {0xB2u, 0x04u},
- {0xB5u, 0x80u},
- {0xB6u, 0x50u},
- {0xC0u, 0xECu},
- {0xC2u, 0x48u},
- {0xC4u, 0x71u},
- {0xCAu, 0xD0u},
- {0xCCu, 0xECu},
- {0xCEu, 0xF2u},
- {0xD6u, 0x3Eu},
- {0xD8u, 0x3Eu},
- {0xE0u, 0x10u},
- {0xE2u, 0x02u},
- {0xE6u, 0x90u},
- {0xE8u, 0x20u},
- {0xECu, 0x80u},
- {0xEEu, 0x20u},
- {0x01u, 0x40u},
- {0x03u, 0x80u},
- {0x05u, 0xD3u},
- {0x07u, 0x20u},
- {0x09u, 0x08u},
- {0x0Bu, 0xC3u},
- {0x0Du, 0x01u},
- {0x0Fu, 0x02u},
- {0x15u, 0x14u},
- {0x17u, 0xE3u},
- {0x1Bu, 0x04u},
- {0x21u, 0xC3u},
- {0x23u, 0x20u},
- {0x25u, 0x01u},
- {0x26u, 0x01u},
- {0x27u, 0x02u},
- {0x29u, 0x04u},
- {0x2Bu, 0xE3u},
- {0x2Du, 0x40u},
- {0x2Fu, 0x80u},
- {0x33u, 0x3Cu},
- {0x34u, 0x01u},
- {0x35u, 0xC0u},
- {0x37u, 0x03u},
- {0x39u, 0x08u},
- {0x3Bu, 0xA0u},
- {0x56u, 0x08u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Cu, 0x19u},
- {0x5Du, 0x90u},
- {0x5Fu, 0x01u},
- {0x80u, 0xF0u},
- {0x83u, 0x09u},
- {0x84u, 0x04u},
- {0x86u, 0xF8u},
- {0x88u, 0xFAu},
- {0x89u, 0x40u},
- {0x8Au, 0x05u},
- {0x8Bu, 0x80u},
- {0x8Du, 0xE0u},
- {0x91u, 0x06u},
- {0x92u, 0x08u},
- {0x93u, 0xF8u},
- {0x94u, 0x40u},
- {0x95u, 0xC6u},
- {0x96u, 0x80u},
- {0x97u, 0x19u},
- {0x99u, 0x09u},
- {0x9Au, 0x07u},
- {0x9Bu, 0xF2u},
- {0x9Eu, 0xF0u},
- {0xA0u, 0x09u},
- {0xA2u, 0xF2u},
- {0xA3u, 0xFFu},
- {0xA4u, 0x40u},
- {0xA5u, 0x01u},
- {0xA6u, 0x80u},
- {0xA8u, 0x10u},
- {0xA9u, 0x14u},
- {0xAAu, 0x20u},
- {0xACu, 0x10u},
- {0xADu, 0x40u},
- {0xAEu, 0x20u},
- {0xAFu, 0x80u},
- {0xB2u, 0xC0u},
- {0xB3u, 0x3Fu},
- {0xB4u, 0x0Fu},
- {0xB5u, 0xC0u},
- {0xB6u, 0x30u},
- {0xBAu, 0x88u},
- {0xBBu, 0x20u},
- {0xD6u, 0x08u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDBu, 0x04u},
- {0xDCu, 0x11u},
- {0xDDu, 0x90u},
- {0xDFu, 0x01u},
- {0x04u, 0x02u},
- {0x06u, 0x18u},
- {0x0Cu, 0x81u},
- {0x0Eu, 0x18u},
- {0x13u, 0x04u},
- {0x14u, 0x08u},
- {0x15u, 0x40u},
- {0x16u, 0x20u},
- {0x17u, 0x01u},
- {0x1Au, 0x04u},
- {0x1Eu, 0x18u},
- {0x1Fu, 0x80u},
+ {0x1Au, 0x40u},
+ {0x1Bu, 0x50u},
+ {0x1Du, 0x44u},
+ {0x1Eu, 0x08u},
+ {0x1Fu, 0x40u},
{0x20u, 0x20u},
- {0x21u, 0x48u},
- {0x23u, 0x2Au},
- {0x25u, 0x10u},
- {0x26u, 0x28u},
- {0x27u, 0x10u},
- {0x29u, 0x10u},
- {0x2Au, 0x54u},
- {0x2Bu, 0x40u},
- {0x2Cu, 0xA0u},
- {0x2Eu, 0x80u},
- {0x2Fu, 0x08u},
- {0x30u, 0x20u},
- {0x31u, 0x08u},
- {0x35u, 0x10u},
+ {0x24u, 0x04u},
+ {0x27u, 0x01u},
+ {0x2Au, 0x42u},
+ {0x2Bu, 0x04u},
+ {0x2Fu, 0x88u},
+ {0x30u, 0x02u},
+ {0x32u, 0x58u},
{0x36u, 0x08u},
{0x37u, 0x01u},
- {0x39u, 0x80u},
- {0x3Au, 0x09u},
- {0x3Bu, 0x20u},
- {0x3Du, 0x21u},
- {0x3Fu, 0x80u},
- {0x42u, 0x08u},
- {0x43u, 0x10u},
- {0x59u, 0x80u},
- {0x5Au, 0x20u},
- {0x5Cu, 0x50u},
- {0x60u, 0x04u},
- {0x62u, 0x40u},
- {0x65u, 0x40u},
- {0x67u, 0x04u},
- {0x81u, 0x40u},
- {0x82u, 0x01u},
- {0x83u, 0x88u},
- {0x87u, 0x63u},
- {0x88u, 0x01u},
- {0x8Au, 0x04u},
- {0x8Bu, 0x08u},
- {0x8Cu, 0x50u},
- {0xC0u, 0x70u},
- {0xC2u, 0xF0u},
- {0xC4u, 0xF4u},
- {0xCAu, 0xFFu},
- {0xCCu, 0xE6u},
- {0xCEu, 0xBFu},
- {0xD6u, 0x3Cu},
- {0xD8u, 0x3Cu},
- {0xE0u, 0x70u},
- {0xE4u, 0x20u},
- {0x80u, 0x09u},
- {0x81u, 0x01u},
- {0x82u, 0x02u},
- {0x83u, 0x32u},
- {0x84u, 0x22u},
- {0x85u, 0x62u},
- {0x86u, 0x01u},
- {0x87u, 0x08u},
- {0x89u, 0x0Du},
- {0x8Du, 0x0Du},
- {0x90u, 0x3Eu},
- {0x94u, 0x01u},
- {0x95u, 0x02u},
- {0x96u, 0x14u},
- {0x97u, 0x54u},
- {0x9Bu, 0x10u},
- {0x9Du, 0x02u},
- {0x9Fu, 0x0Du},
- {0xA1u, 0x0Du},
- {0xA5u, 0x0Du},
- {0xAAu, 0x38u},
- {0xADu, 0x0Du},
- {0xB0u, 0x07u},
- {0xB3u, 0x70u},
- {0xB4u, 0x38u},
- {0xB7u, 0x0Fu},
- {0xB8u, 0x02u},
- {0xBBu, 0x80u},
- {0xBEu, 0x10u},
- {0xD8u, 0x04u},
- {0xD9u, 0x04u},
- {0xDFu, 0x01u},
- {0x01u, 0xA0u},
- {0x02u, 0x40u},
- {0x04u, 0x05u},
- {0x08u, 0x80u},
- {0x09u, 0x01u},
- {0x0Du, 0x08u},
- {0x0Eu, 0x80u},
- {0x11u, 0x04u},
- {0x13u, 0x40u},
- {0x17u, 0x10u},
- {0x1Au, 0x04u},
- {0x1Bu, 0x05u},
- {0x1Eu, 0x80u},
- {0x1Fu, 0x20u},
- {0x21u, 0x02u},
- {0x26u, 0x80u},
- {0x27u, 0x20u},
- {0x29u, 0x40u},
- {0x2Au, 0x20u},
- {0x2Bu, 0x80u},
- {0x2Cu, 0x20u},
- {0x2Fu, 0x82u},
- {0x31u, 0x88u},
- {0x32u, 0x10u},
- {0x33u, 0x02u},
- {0x36u, 0x88u},
- {0x37u, 0x20u},
- {0x38u, 0x69u},
- {0x3Cu, 0x85u},
- {0x3Eu, 0x10u},
- {0x40u, 0x05u},
- {0x41u, 0x09u},
- {0x49u, 0x06u},
- {0x4Au, 0x04u},
- {0x52u, 0x25u},
- {0x53u, 0x40u},
- {0x83u, 0x20u},
- {0x86u, 0x24u},
- {0x87u, 0x40u},
- {0x8Bu, 0x20u},
- {0x8Eu, 0x04u},
- {0x90u, 0x6Du},
- {0x91u, 0x06u},
- {0x92u, 0x30u},
- {0x93u, 0x40u},
- {0x98u, 0x80u},
- {0x99u, 0xE0u},
- {0x9Au, 0x40u},
- {0x9Bu, 0x10u},
- {0x9Du, 0x06u},
- {0x9Eu, 0x05u},
- {0xA0u, 0x60u},
- {0xA1u, 0x89u},
- {0xA2u, 0x08u},
- {0xA3u, 0x82u},
- {0xA5u, 0x02u},
- {0xA6u, 0x20u},
- {0xA7u, 0x05u},
- {0xB3u, 0x01u},
- {0xC0u, 0x3Bu},
- {0xC2u, 0x39u},
- {0xC4u, 0x45u},
- {0xCAu, 0xDDu},
- {0xCCu, 0x7Fu},
- {0xCEu, 0xFFu},
- {0xD0u, 0x0Fu},
- {0xD2u, 0x04u},
- {0xE0u, 0x42u},
- {0xE2u, 0x80u},
- {0x00u, 0x0Fu},
- {0x01u, 0x11u},
- {0x02u, 0xF0u},
- {0x03u, 0x62u},
- {0x04u, 0x03u},
- {0x05u, 0x58u},
- {0x06u, 0x0Cu},
- {0x07u, 0x23u},
- {0x08u, 0x60u},
- {0x09u, 0x40u},
- {0x0Au, 0x90u},
- {0x0Bu, 0x30u},
- {0x0Cu, 0x05u},
- {0x0Eu, 0x0Au},
- {0x13u, 0x01u},
- {0x15u, 0x34u},
- {0x17u, 0x43u},
- {0x1Bu, 0x0Cu},
- {0x1Cu, 0x06u},
- {0x1Eu, 0x09u},
- {0x20u, 0x30u},
- {0x22u, 0xC0u},
- {0x23u, 0x82u},
- {0x24u, 0x50u},
- {0x26u, 0xA0u},
- {0x30u, 0xFFu},
- {0x33u, 0x0Fu},
- {0x35u, 0x70u},
- {0x37u, 0x80u},
- {0x3Bu, 0x20u},
- {0x3Eu, 0x01u},
- {0x56u, 0x02u},
- {0x57u, 0x28u},
- {0x58u, 0x04u},
- {0x59u, 0x04u},
- {0x5Bu, 0x04u},
- {0x5Fu, 0x01u},
- {0x80u, 0x10u},
- {0x81u, 0x16u},
- {0x85u, 0x10u},
- {0x87u, 0x06u},
- {0x88u, 0x47u},
- {0x89u, 0x12u},
- {0x8Au, 0x18u},
- {0x8Bu, 0x04u},
- {0x8Cu, 0x01u},
- {0x8Du, 0x22u},
- {0x8Fu, 0x10u},
- {0x90u, 0x04u},
+ {0x38u, 0x40u},
+ {0x39u, 0x25u},
+ {0x3Cu, 0x84u},
+ {0x3Fu, 0x02u},
+ {0x5Du, 0x80u},
+ {0x60u, 0x10u},
+ {0x62u, 0x92u},
+ {0x64u, 0x02u},
+ {0x82u, 0x06u},
+ {0x8Fu, 0x40u},
{0x91u, 0x40u},
- {0x94u, 0x62u},
- {0x95u, 0x29u},
- {0x96u, 0x08u},
- {0x97u, 0x16u},
- {0x99u, 0x31u},
- {0x9Bu, 0x0Eu},
- {0x9Cu, 0x01u},
- {0x9Du, 0x17u},
- {0x9Fu, 0x28u},
- {0xA0u, 0x01u},
- {0xA1u, 0x16u},
- {0xA4u, 0x01u},
- {0xA5u, 0x04u},
- {0xA8u, 0x48u},
- {0xA9u, 0x40u},
- {0xAAu, 0x21u},
- {0xACu, 0x01u},
- {0xADu, 0x06u},
- {0xAFu, 0x10u},
- {0xB0u, 0x08u},
- {0xB1u, 0x30u},
- {0xB2u, 0x3Fu},
- {0xB3u, 0x0Fu},
- {0xB4u, 0x40u},
- {0xB7u, 0x40u},
+ {0x92u, 0x04u},
+ {0x95u, 0x8Fu},
+ {0x96u, 0x81u},
+ {0x97u, 0x04u},
+ {0x98u, 0x04u},
+ {0x9Cu, 0x40u},
+ {0x9Du, 0x19u},
+ {0x9Eu, 0x40u},
+ {0xA0u, 0x04u},
+ {0xA3u, 0x0Cu},
+ {0xA4u, 0x52u},
+ {0xA6u, 0x08u},
+ {0xA7u, 0x01u},
+ {0xAAu, 0x80u},
+ {0xB1u, 0x80u},
+ {0xB4u, 0x08u},
+ {0xB6u, 0x28u},
+ {0xC0u, 0xADu},
+ {0xC2u, 0x6Du},
+ {0xC4u, 0x8Fu},
+ {0xCAu, 0xADu},
+ {0xCCu, 0xCFu},
+ {0xCEu, 0xDFu},
+ {0xD6u, 0x10u},
+ {0xD8u, 0x1Fu},
+ {0xE4u, 0x04u},
+ {0xEEu, 0x04u},
{0xB8u, 0x08u},
- {0xB9u, 0x88u},
- {0xBBu, 0x02u},
- {0xBEu, 0x15u},
+ {0xBEu, 0x04u},
{0xD8u, 0x04u},
- {0xD9u, 0x04u},
{0xDFu, 0x01u},
- {0x00u, 0x80u},
- {0x01u, 0x12u},
- {0x04u, 0x02u},
- {0x05u, 0x18u},
- {0x06u, 0x02u},
- {0x09u, 0x40u},
- {0x0Au, 0xA0u},
- {0x0Eu, 0x01u},
- {0x10u, 0x20u},
- {0x11u, 0x01u},
- {0x12u, 0x0Au},
- {0x16u, 0x90u},
- {0x1Au, 0x40u},
- {0x1Bu, 0x28u},
- {0x1Eu, 0x80u},
- {0x20u, 0x40u},
- {0x21u, 0x88u},
- {0x22u, 0x4Au},
- {0x25u, 0x10u},
- {0x27u, 0x12u},
- {0x28u, 0x40u},
- {0x2Au, 0x04u},
- {0x2Bu, 0x0Au},
- {0x2Du, 0x02u},
- {0x31u, 0x0Au},
- {0x32u, 0x90u},
- {0x36u, 0x08u},
- {0x37u, 0x12u},
- {0x38u, 0x68u},
- {0x39u, 0x01u},
- {0x3Cu, 0x05u},
- {0x3Du, 0x20u},
- {0x45u, 0x10u},
- {0x46u, 0x08u},
- {0x4Cu, 0x01u},
- {0x4Fu, 0x40u},
- {0x58u, 0x40u},
- {0x59u, 0x40u},
- {0x66u, 0x08u},
- {0x6Cu, 0x34u},
- {0x6Du, 0x81u},
- {0x6Eu, 0x10u},
- {0x6Fu, 0x82u},
- {0x74u, 0x40u},
- {0x75u, 0x40u},
- {0x8Du, 0x08u},
- {0x90u, 0x07u},
- {0x91u, 0x16u},
- {0x92u, 0x21u},
- {0x94u, 0x68u},
- {0x96u, 0x40u},
- {0x98u, 0x80u},
- {0x99u, 0xB0u},
- {0x9Au, 0xD2u},
- {0x9Du, 0x44u},
- {0x9Eu, 0x05u},
- {0xA1u, 0x01u},
- {0xA2u, 0x80u},
- {0xA6u, 0x68u},
- {0xA7u, 0xA6u},
- {0xB0u, 0x40u},
- {0xB3u, 0x20u},
- {0xC0u, 0xFBu},
- {0xC2u, 0x8Du},
- {0xC4u, 0x3Fu},
- {0xCAu, 0x8Fu},
- {0xCCu, 0xEFu},
- {0xCEu, 0xEFu},
- {0xD8u, 0x40u},
- {0xE2u, 0x08u},
- {0xEAu, 0x02u},
- {0xEEu, 0x08u},
- {0x38u, 0x80u},
- {0x3Eu, 0x40u},
- {0x58u, 0x04u},
- {0x5Fu, 0x01u},
- {0x1Fu, 0x40u},
- {0x87u, 0x40u},
- {0x8Eu, 0x04u},
- {0x9Du, 0x08u},
- {0xA2u, 0x04u},
- {0xE2u, 0x40u},
- {0xEAu, 0x02u},
- {0xEEu, 0x08u},
- {0x8Du, 0x08u},
- {0x9Du, 0x08u},
- {0xE0u, 0x02u},
- {0xE8u, 0x80u},
- {0x04u, 0x10u},
- {0x0Eu, 0x08u},
- {0x12u, 0x08u},
+ {0x1Bu, 0x08u},
+ {0x80u, 0x20u},
+ {0x95u, 0x10u},
+ {0x9Cu, 0x20u},
+ {0xA2u, 0x01u},
+ {0xA8u, 0x81u},
+ {0xB0u, 0x01u},
+ {0xB1u, 0x08u},
+ {0xB2u, 0x40u},
+ {0xB4u, 0x80u},
+ {0xB6u, 0x02u},
+ {0xB7u, 0x40u},
+ {0xE4u, 0x40u},
+ {0xEAu, 0x10u},
+ {0xECu, 0xD0u},
+ {0xEEu, 0x01u},
+ {0x82u, 0x01u},
+ {0x85u, 0x10u},
+ {0x95u, 0x10u},
+ {0xA2u, 0x01u},
+ {0xAFu, 0x08u},
+ {0xE2u, 0x80u},
+ {0xE4u, 0x01u},
+ {0xE6u, 0x08u},
+ {0xEAu, 0x04u},
+ {0x05u, 0x80u},
+ {0x0Cu, 0x80u},
+ {0x13u, 0x20u},
{0x16u, 0x80u},
{0x17u, 0x80u},
{0x32u, 0x02u},
+ {0x35u, 0x01u},
{0x36u, 0x80u},
- {0x37u, 0x08u},
- {0x39u, 0x04u},
+ {0x39u, 0x01u},
{0x3Au, 0x80u},
- {0x3Cu, 0x08u},
- {0x3Fu, 0x10u},
- {0x42u, 0x08u},
+ {0x3Eu, 0x40u},
+ {0x3Fu, 0x01u},
+ {0x41u, 0x40u},
{0x66u, 0x40u},
- {0x87u, 0x08u},
- {0x89u, 0x04u},
- {0x8Cu, 0x10u},
- {0x8Eu, 0x06u},
+ {0x77u, 0x60u},
+ {0x88u, 0x80u},
+ {0x8Eu, 0x40u},
{0xC0u, 0x80u},
{0xC2u, 0x80u},
{0xC4u, 0xE0u},
@@ -1809,161 +1945,168 @@ void cyfitter_cfg(void)
{0xCEu, 0xF0u},
{0xD0u, 0x10u},
{0xD6u, 0x80u},
- {0xE2u, 0x10u},
- {0x33u, 0x11u},
- {0x36u, 0x02u},
- {0x37u, 0x80u},
- {0x39u, 0x80u},
- {0x50u, 0x04u},
- {0x54u, 0x20u},
- {0x63u, 0x40u},
- {0x86u, 0x42u},
- {0x87u, 0x40u},
- {0x9Bu, 0x90u},
- {0x9Eu, 0x48u},
- {0xA4u, 0x04u},
- {0xA6u, 0x80u},
- {0xAAu, 0x08u},
- {0xABu, 0x10u},
- {0xAFu, 0x10u},
+ {0x33u, 0x42u},
+ {0x37u, 0x84u},
+ {0x38u, 0x10u},
+ {0x56u, 0x20u},
+ {0x58u, 0x10u},
+ {0x66u, 0x80u},
+ {0x86u, 0x40u},
+ {0x8Au, 0x80u},
+ {0x8Eu, 0x20u},
+ {0x95u, 0x80u},
+ {0x97u, 0x01u},
+ {0x99u, 0x80u},
+ {0x9Bu, 0xC0u},
+ {0x9Eu, 0x40u},
+ {0xA6u, 0x82u},
+ {0xA9u, 0x01u},
+ {0xADu, 0x01u},
{0xCCu, 0xF0u},
{0xCEu, 0x10u},
- {0xD4u, 0x60u},
- {0xD8u, 0x40u},
- {0xE2u, 0x50u},
- {0xE6u, 0x40u},
- {0xEAu, 0x10u},
+ {0xD4u, 0xC0u},
+ {0xD6u, 0x80u},
+ {0xE2u, 0x10u},
+ {0xEAu, 0x30u},
{0x12u, 0x80u},
- {0x33u, 0x80u},
- {0x86u, 0x08u},
+ {0x32u, 0x10u},
+ {0x82u, 0x10u},
+ {0x94u, 0x10u},
{0x95u, 0x80u},
- {0x9Eu, 0x08u},
- {0x9Fu, 0x01u},
- {0xA4u, 0x04u},
+ {0x97u, 0x01u},
+ {0x9Fu, 0x04u},
{0xA6u, 0x80u},
- {0xA8u, 0x04u},
- {0xB4u, 0x20u},
+ {0xA7u, 0x02u},
+ {0xA9u, 0x80u},
+ {0xB0u, 0x10u},
+ {0xB6u, 0x02u},
{0xC4u, 0x10u},
{0xCCu, 0x10u},
- {0xE6u, 0x40u},
- {0xEEu, 0x80u},
+ {0xE6u, 0x20u},
+ {0xE8u, 0x20u},
+ {0x80u, 0x10u},
{0x81u, 0x40u},
- {0x88u, 0x04u},
+ {0x87u, 0x02u},
+ {0x94u, 0x10u},
{0x95u, 0x80u},
- {0x9Fu, 0x01u},
- {0xA4u, 0x04u},
- {0xA7u, 0x80u},
- {0xE2u, 0x80u},
+ {0x97u, 0x01u},
+ {0xA7u, 0x02u},
+ {0xABu, 0x04u},
+ {0xE2u, 0x90u},
+ {0xE6u, 0x80u},
+ {0xEAu, 0x80u},
{0x00u, 0x10u},
- {0x04u, 0x40u},
- {0x09u, 0x20u},
- {0x0Eu, 0x02u},
- {0x12u, 0x80u},
- {0x14u, 0x20u},
- {0x62u, 0x08u},
- {0x65u, 0x01u},
- {0x88u, 0x20u},
+ {0x05u, 0x80u},
+ {0x08u, 0x80u},
+ {0x0Fu, 0x08u},
+ {0x13u, 0x02u},
+ {0x15u, 0x08u},
+ {0x63u, 0x80u},
+ {0x65u, 0x20u},
+ {0x8Bu, 0x80u},
{0xC0u, 0x03u},
{0xC2u, 0x03u},
{0xC4u, 0x0Cu},
{0xD8u, 0x03u},
{0xE2u, 0x01u},
- {0x00u, 0x08u},
+ {0x03u, 0x80u},
{0x07u, 0x40u},
- {0x08u, 0x02u},
- {0x0Du, 0x01u},
- {0x56u, 0x20u},
- {0x5Au, 0x08u},
- {0x5Fu, 0x80u},
- {0x62u, 0x10u},
- {0x84u, 0x08u},
- {0x88u, 0x02u},
- {0x8Bu, 0x80u},
- {0x8Eu, 0x80u},
- {0x9Du, 0x01u},
- {0xA2u, 0x81u},
- {0xB2u, 0x08u},
- {0xB4u, 0x50u},
- {0xB5u, 0x20u},
+ {0x0Bu, 0x80u},
+ {0x0Cu, 0x02u},
+ {0x57u, 0x08u},
+ {0x58u, 0x10u},
+ {0x64u, 0x20u},
+ {0x66u, 0x80u},
+ {0x83u, 0x40u},
+ {0x87u, 0x02u},
+ {0x90u, 0x10u},
+ {0x91u, 0x08u},
+ {0x98u, 0x80u},
+ {0x99u, 0x80u},
+ {0x9Au, 0x80u},
+ {0x9Bu, 0x02u},
+ {0xA7u, 0xC0u},
+ {0xABu, 0x04u},
+ {0xADu, 0x20u},
+ {0xAEu, 0x80u},
{0xC0u, 0x0Cu},
{0xC2u, 0x0Cu},
- {0xD4u, 0x02u},
- {0xD6u, 0x06u},
- {0xD8u, 0x02u},
- {0xE2u, 0x06u},
- {0xE4u, 0x04u},
- {0xEAu, 0x0Au},
- {0xECu, 0x01u},
- {0xEEu, 0x02u},
- {0x53u, 0x40u},
- {0x81u, 0x01u},
- {0x83u, 0x40u},
- {0x86u, 0x10u},
- {0x88u, 0x04u},
- {0x8Eu, 0x20u},
- {0x96u, 0x08u},
- {0x9Bu, 0x40u},
- {0x9Du, 0x01u},
- {0x9Eu, 0x30u},
- {0xA0u, 0x04u},
- {0xA2u, 0x01u},
- {0xA4u, 0x08u},
- {0xB1u, 0x01u},
- {0xD4u, 0x04u},
- {0xE2u, 0x04u},
- {0xE4u, 0x02u},
- {0xEAu, 0x04u},
- {0x09u, 0x08u},
- {0x0Bu, 0x01u},
- {0x0Cu, 0x08u},
- {0x0Fu, 0x02u},
- {0x81u, 0x20u},
- {0x83u, 0x01u},
+ {0xD4u, 0x03u},
+ {0xD6u, 0x01u},
+ {0xD8u, 0x01u},
+ {0x53u, 0x80u},
+ {0x82u, 0x04u},
+ {0x84u, 0x10u},
+ {0x88u, 0x80u},
{0x8Bu, 0x80u},
- {0x96u, 0x08u},
- {0xA4u, 0x08u},
- {0xAFu, 0x40u},
- {0xB6u, 0x01u},
- {0xC2u, 0x0Fu},
- {0xE4u, 0x04u},
- {0xEAu, 0x08u},
- {0x67u, 0x80u},
+ {0x91u, 0x08u},
+ {0x98u, 0x80u},
+ {0x99u, 0x80u},
+ {0x9Bu, 0x40u},
+ {0x9Cu, 0x30u},
+ {0xA7u, 0x08u},
+ {0xA8u, 0x10u},
+ {0xB3u, 0x40u},
+ {0xB4u, 0x02u},
+ {0xD4u, 0x04u},
+ {0xE0u, 0x01u},
+ {0xE2u, 0x04u},
+ {0xEEu, 0x03u},
+ {0x08u, 0x80u},
+ {0x0Bu, 0x80u},
+ {0x0Du, 0x02u},
+ {0x0Eu, 0x08u},
+ {0x80u, 0x80u},
+ {0x84u, 0x20u},
{0x87u, 0x40u},
- {0xAFu, 0x81u},
+ {0x8Fu, 0x08u},
+ {0x99u, 0x80u},
+ {0x9Bu, 0x40u},
+ {0x9Cu, 0x20u},
+ {0xA5u, 0x02u},
+ {0xA6u, 0x04u},
+ {0xA7u, 0x08u},
+ {0xA9u, 0x02u},
+ {0xADu, 0x04u},
+ {0xC2u, 0x0Fu},
+ {0xE0u, 0x08u},
+ {0x67u, 0x40u},
+ {0x83u, 0x01u},
+ {0x97u, 0x01u},
{0xD8u, 0x80u},
- {0xE2u, 0x10u},
- {0xEAu, 0x40u},
- {0xEEu, 0x10u},
- {0x04u, 0x02u},
- {0x52u, 0x02u},
- {0x53u, 0x04u},
- {0x82u, 0x02u},
- {0x8Bu, 0x04u},
- {0x8Cu, 0x01u},
- {0xC0u, 0x20u},
- {0xD4u, 0xA0u},
{0xE2u, 0x80u},
- {0x96u, 0x08u},
- {0x9Bu, 0x80u},
- {0x9Du, 0x20u},
- {0xADu, 0x08u},
- {0xAFu, 0x01u},
- {0x01u, 0x20u},
- {0x04u, 0x40u},
- {0x5Bu, 0x80u},
- {0x5Fu, 0x20u},
+ {0x05u, 0x04u},
+ {0x52u, 0x02u},
+ {0x57u, 0x20u},
+ {0x81u, 0x04u},
+ {0x86u, 0x02u},
{0x87u, 0x20u},
- {0x8Cu, 0x40u},
- {0x9Bu, 0x80u},
- {0x9Du, 0x20u},
- {0xB2u, 0x04u},
+ {0xAFu, 0x40u},
+ {0xC0u, 0x20u},
+ {0xD4u, 0xC0u},
+ {0xE2u, 0x40u},
+ {0xE4u, 0x80u},
+ {0xE6u, 0x10u},
+ {0xEEu, 0x40u},
+ {0x8Cu, 0x02u},
+ {0x99u, 0x80u},
+ {0xABu, 0x40u},
+ {0xE4u, 0x02u},
+ {0x01u, 0x10u},
+ {0x06u, 0x02u},
+ {0x50u, 0x06u},
+ {0x80u, 0x04u},
+ {0x86u, 0x02u},
+ {0x89u, 0x10u},
+ {0xA0u, 0x02u},
+ {0xA9u, 0x80u},
{0xC0u, 0x03u},
- {0xD4u, 0x01u},
- {0xD6u, 0x04u},
- {0xE2u, 0x02u},
- {0xE8u, 0x01u},
- {0x10u, 0x01u},
- {0x1Au, 0x01u},
+ {0xD4u, 0x05u},
+ {0xE2u, 0x01u},
+ {0x10u, 0x03u},
+ {0x11u, 0x01u},
+ {0x1Au, 0x03u},
+ {0x1Bu, 0x01u},
{0x00u, 0xFDu},
{0x01u, 0xBFu},
{0x02u, 0x2Au},
@@ -1997,18 +2140,18 @@ void cyfitter_cfg(void)
/* UDB_1_0_0_CONFIG Address: CYDEV_UCFG_B1_P2_U0_BASE Size (bytes): 128 */
static const uint8 CYCODE BS_UDB_1_0_0_CONFIG_VAL[] = {
- 0x02u, 0x1Fu, 0x01u, 0x20u, 0x00u, 0xC0u, 0x00u, 0x08u, 0x00u, 0xC0u, 0x10u, 0x04u, 0x04u, 0x80u, 0x88u, 0x00u,
- 0x08u, 0x90u, 0x04u, 0x40u, 0x00u, 0x00u, 0x00u, 0xFFu, 0x00u, 0x7Fu, 0x00u, 0x80u, 0x01u, 0x00u, 0x42u, 0x60u,
- 0x00u, 0xC0u, 0x00u, 0x02u, 0x00u, 0x00u, 0x20u, 0x00u, 0x00u, 0x00u, 0x00u, 0x9Fu, 0x53u, 0xC0u, 0xACu, 0x01u,
- 0xC0u, 0xFFu, 0x0Fu, 0x00u, 0x30u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x15u, 0x01u,
- 0x32u, 0x01u, 0x40u, 0x00u, 0x06u, 0xBEu, 0xFBu, 0xDCu, 0x3Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
- 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x01u,
+ 0xD6u, 0x20u, 0x00u, 0x40u, 0xD2u, 0x92u, 0x04u, 0x01u, 0x21u, 0x01u, 0x8Eu, 0xB0u, 0x17u, 0xC5u, 0x28u, 0x0Au,
+ 0x00u, 0xB0u, 0x00u, 0x01u, 0x29u, 0x03u, 0x46u, 0xBCu, 0x20u, 0x91u, 0xD0u, 0x20u, 0xD6u, 0xB1u, 0x00u, 0x00u,
+ 0xD6u, 0xB1u, 0x00u, 0x00u, 0x02u, 0x00u, 0x00u, 0x00u, 0xD0u, 0x00u, 0x06u, 0x00u, 0x04u, 0x46u, 0x00u, 0x39u,
+ 0x0Fu, 0x3Cu, 0x0Fu, 0xC4u, 0xF0u, 0x03u, 0x00u, 0x00u, 0x0Au, 0x00u, 0x20u, 0x2Cu, 0x00u, 0x00u, 0x00u, 0x00u,
+ 0x36u, 0x05u, 0x40u, 0x00u, 0x02u, 0xDEu, 0xFBu, 0xC0u, 0x2Fu, 0xFFu, 0xFFu, 0xFFu, 0x22u, 0x00u, 0xF0u, 0x08u,
+ 0x04u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x24u, 0x04u, 0x04u, 0x04u, 0x04u, 0x00u, 0x00u, 0x00u, 0x01u,
0x00u, 0x00u, 0xC0u, 0x00u, 0x40u, 0x01u, 0x10u, 0x11u, 0xC0u, 0x01u, 0x00u, 0x11u, 0x40u, 0x01u, 0x40u, 0x01u,
0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u};
/* UCFG_BCTL0 Address: CYREG_BCTL0_MDCLK_EN Size (bytes): 16 */
static const uint8 CYCODE BS_UCFG_BCTL0_VAL[] = {
- 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x02u, 0x01u, 0x03u, 0x01u, 0x02u, 0x01u, 0x02u, 0x01u};
+ 0x03u, 0x01u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x00u, 0x03u, 0x01u, 0x03u, 0x00u, 0x02u, 0x01u, 0x02u, 0x01u};
static const cfg_memcpy_t CYCODE cfg_memcpy_list [] = {
/* dest, src, size */
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
index 0b9318f..01ee8a3 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfittergnu.inc
@@ -426,34 +426,34 @@
.set EXTLED__SLW, CYREG_PRT0_SLW
/* SDCard_BSPIM */
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB06_07_CTL
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB06_07_MSK
-.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB06_CTL
-.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB06_07_ACTL
-.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB06_07_ST
-.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB06_MSK
-.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB06_MSK_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB06_ACTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB06_ST_CTL
-.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB06_ST
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
-.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG, CYREG_B1_UDB04_05_CTL
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG, CYREG_B1_UDB04_05_MSK
+.set SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter__CONTROL_REG, CYREG_B1_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__CONTROL_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_REG, CYREG_B1_UDB04_CTL
+.set SDCard_BSPIM_BitCounter__COUNT_ST_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter__PERIOD_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB04_05_ACTL
+.set SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG, CYREG_B1_UDB04_05_ST
+.set SDCard_BSPIM_BitCounter_ST__MASK_REG, CYREG_B1_UDB04_MSK
+.set SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG, CYREG_B1_UDB04_ACTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG, CYREG_B1_UDB04_ST_CTL
+.set SDCard_BSPIM_BitCounter_ST__STATUS_REG, CYREG_B1_UDB04_ST
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B1_UDB07_08_ACTL
+.set SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG, CYREG_B1_UDB07_08_ST
.set SDCard_BSPIM_RxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_RxStsReg__4__POS, 4
.set SDCard_BSPIM_RxStsReg__5__MASK, 0x20
@@ -461,9 +461,9 @@
.set SDCard_BSPIM_RxStsReg__6__MASK, 0x40
.set SDCard_BSPIM_RxStsReg__6__POS, 6
.set SDCard_BSPIM_RxStsReg__MASK, 0x70
-.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
-.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
-.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
+.set SDCard_BSPIM_RxStsReg__MASK_REG, CYREG_B1_UDB07_MSK
+.set SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG, CYREG_B1_UDB07_ACTL
+.set SDCard_BSPIM_RxStsReg__STATUS_REG, CYREG_B1_UDB07_ST
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG, CYREG_B1_UDB04_05_A0
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG, CYREG_B1_UDB04_05_A1
.set SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG, CYREG_B1_UDB04_05_D0
@@ -481,12 +481,14 @@
.set SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG, CYREG_B1_UDB04_F0_F1
.set SDCard_BSPIM_sR8_Dp_u0__F0_REG, CYREG_B1_UDB04_F0
.set SDCard_BSPIM_sR8_Dp_u0__F1_REG, CYREG_B1_UDB04_F1
+.set SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
+.set SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG, CYREG_B1_UDB04_MSK_ACTL
.set SDCard_BSPIM_TxStsReg__0__MASK, 0x01
.set SDCard_BSPIM_TxStsReg__0__POS, 0
.set SDCard_BSPIM_TxStsReg__1__MASK, 0x02
.set SDCard_BSPIM_TxStsReg__1__POS, 1
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
-.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB07_08_ACTL
+.set SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG, CYREG_B0_UDB07_08_ST
.set SDCard_BSPIM_TxStsReg__2__MASK, 0x04
.set SDCard_BSPIM_TxStsReg__2__POS, 2
.set SDCard_BSPIM_TxStsReg__3__MASK, 0x08
@@ -494,9 +496,9 @@
.set SDCard_BSPIM_TxStsReg__4__MASK, 0x10
.set SDCard_BSPIM_TxStsReg__4__POS, 4
.set SDCard_BSPIM_TxStsReg__MASK, 0x1F
-.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB04_MSK
-.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
-.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB04_ST
+.set SDCard_BSPIM_TxStsReg__MASK_REG, CYREG_B0_UDB07_MSK
+.set SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB07_ACTL
+.set SDCard_BSPIM_TxStsReg__STATUS_REG, CYREG_B0_UDB07_ST
/* SD_SCK */
.set SD_SCK__0__INTTYPE, CYREG_PICU3_INTTYPE2
@@ -1906,15 +1908,15 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__0__POS, 0
.set SCSI_Out_Bits_Sync_ctrl_reg__1__MASK, 0x02
.set SCSI_Out_Bits_Sync_ctrl_reg__1__POS, 1
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB02_03_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB02_03_MSK
-.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB02_03_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB03_04_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB03_04_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB03_04_MSK
.set SCSI_Out_Bits_Sync_ctrl_reg__2__MASK, 0x04
.set SCSI_Out_Bits_Sync_ctrl_reg__2__POS, 2
.set SCSI_Out_Bits_Sync_ctrl_reg__3__MASK, 0x08
@@ -1927,37 +1929,37 @@
.set SCSI_Out_Bits_Sync_ctrl_reg__6__POS, 6
.set SCSI_Out_Bits_Sync_ctrl_reg__7__MASK, 0x80
.set SCSI_Out_Bits_Sync_ctrl_reg__7__POS, 7
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB02_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB02_CTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB02_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB03_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB03_ST_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB03_CTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB03_ST_CTL
.set SCSI_Out_Bits_Sync_ctrl_reg__MASK, 0xFF
-.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB02_MSK
+.set SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB03_MSK_ACTL
+.set SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK, 0x01
.set SCSI_Out_Ctl_Sync_ctrl_reg__0__POS, 0
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_02_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB01_02_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB01_02_MSK
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB01_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB01_ST_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB01_CTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB01_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG, CYREG_B0_UDB04_05_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG, CYREG_B0_UDB04_05_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG, CYREG_B0_UDB04_ST_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG, CYREG_B0_UDB04_CTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG, CYREG_B0_UDB04_ST_CTL
.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK, 0x01
-.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB01_MSK_ACTL
-.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB01_MSK
+.set SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG, CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
.set SCSI_Out_DBx__0__AG, CYREG_PRT5_AG
@@ -2785,8 +2787,8 @@
.set scsiTarget_StatusReg__0__POS, 0
.set scsiTarget_StatusReg__1__MASK, 0x02
.set scsiTarget_StatusReg__1__POS, 1
-.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB03_04_ACTL
-.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB03_04_ST
+.set scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB04_05_ACTL
+.set scsiTarget_StatusReg__16BIT_STATUS_REG, CYREG_B0_UDB04_05_ST
.set scsiTarget_StatusReg__2__MASK, 0x04
.set scsiTarget_StatusReg__2__POS, 2
.set scsiTarget_StatusReg__3__MASK, 0x08
@@ -2794,9 +2796,13 @@
.set scsiTarget_StatusReg__4__MASK, 0x10
.set scsiTarget_StatusReg__4__POS, 4
.set scsiTarget_StatusReg__MASK, 0x1F
-.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB03_MSK
-.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB03_ACTL
-.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB03_ST
+.set scsiTarget_StatusReg__MASK_REG, CYREG_B0_UDB04_MSK
+.set scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_StatusReg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB04_MSK_ACTL
+.set scsiTarget_StatusReg__STATUS_AUX_CTL_REG, CYREG_B0_UDB04_ACTL
+.set scsiTarget_StatusReg__STATUS_CNT_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_StatusReg__STATUS_CONTROL_REG, CYREG_B0_UDB04_ST_CTL
+.set scsiTarget_StatusReg__STATUS_REG, CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
.set Debug_Timer_Interrupt__INTC_CLR_EN_REG, CYREG_NVIC_CLRENA0
@@ -2917,8 +2923,8 @@
.set SCSI_Filtered_sts_sts_reg__0__POS, 0
.set SCSI_Filtered_sts_sts_reg__1__MASK, 0x02
.set SCSI_Filtered_sts_sts_reg__1__POS, 1
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB02_03_ACTL
-.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB02_03_ST
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB08_09_ACTL
+.set SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB08_09_ST
.set SCSI_Filtered_sts_sts_reg__2__MASK, 0x04
.set SCSI_Filtered_sts_sts_reg__2__POS, 2
.set SCSI_Filtered_sts_sts_reg__3__MASK, 0x08
@@ -2926,13 +2932,9 @@
.set SCSI_Filtered_sts_sts_reg__4__MASK, 0x10
.set SCSI_Filtered_sts_sts_reg__4__POS, 4
.set SCSI_Filtered_sts_sts_reg__MASK, 0x1F
-.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB02_MSK
-.set SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG, CYREG_B0_UDB02_MSK_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB02_ACTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG, CYREG_B0_UDB02_ST_CTL
-.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB02_ST
+.set SCSI_Filtered_sts_sts_reg__MASK_REG, CYREG_B0_UDB08_MSK
+.set SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB08_ACTL
+.set SCSI_Filtered_sts_sts_reg__STATUS_REG, CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
.set SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK, 0x01
@@ -2985,12 +2987,12 @@
/* SCSI_Parity_Error */
.set SCSI_Parity_Error_sts_sts_reg__0__MASK, 0x01
.set SCSI_Parity_Error_sts_sts_reg__0__POS, 0
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB11_12_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB11_12_ST
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG, CYREG_B0_UDB05_06_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG, CYREG_B0_UDB05_06_ST
.set SCSI_Parity_Error_sts_sts_reg__MASK, 0x01
-.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB11_MSK
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB11_ACTL
-.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB11_ST
+.set SCSI_Parity_Error_sts_sts_reg__MASK_REG, CYREG_B0_UDB05_MSK
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG, CYREG_B0_UDB05_ACTL
+.set SCSI_Parity_Error_sts_sts_reg__STATUS_REG, CYREG_B0_UDB05_ST
/* Miscellaneous */
.set BCLK__BUS_CLK__HZ, 50000000
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
index 789a9f8..c02aeab 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitteriar.inc
@@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
/* SDCard_BSPIM */
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -481,12 +481,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -494,9 +496,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
/* SD_SCK */
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@@ -1906,15 +1908,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1927,37 +1929,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
/* SCSI_Out_Ctl */
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
/* SCSI_Out_DBx */
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2785,8 +2787,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2794,9 +2796,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
/* Debug_Timer_Interrupt */
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2917,8 +2923,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2926,13 +2932,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
/* SCSI_CTL_PHASE */
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@@ -2985,12 +2987,12 @@ SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
/* SCSI_Parity_Error */
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
/* Miscellaneous */
BCLK__BUS_CLK__HZ EQU 50000000
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
index 98aa696..c639021 100755
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/Generated_Source/PSoC5/cyfitterrv.inc
@@ -426,34 +426,34 @@ EXTLED__SHIFT EQU 0
EXTLED__SLW EQU CYREG_PRT0_SLW
; SDCard_BSPIM
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB06_07_CTL
-SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB06_07_MSK
-SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB06_CTL
-SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_07_ACTL
-SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB06_07_ST
-SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB06_MSK
-SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB06_MSK_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB06_ACTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB06_ST_CTL
-SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB06_ST
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
-SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_CONTROL_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_CONTROL_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_COUNT_COUNT_REG EQU CYREG_B1_UDB04_05_CTL
+SDCard_BSPIM_BitCounter__16BIT_MASK_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_MASK_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_MASK_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__16BIT_PERIOD_PERIOD_REG EQU CYREG_B1_UDB04_05_MSK
+SDCard_BSPIM_BitCounter__CONTROL_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter__CONTROL_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__CONTROL_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__COUNT_REG EQU CYREG_B1_UDB04_CTL
+SDCard_BSPIM_BitCounter__COUNT_ST_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter__MASK_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PER_CTL_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter__PERIOD_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_05_ACTL
+SDCard_BSPIM_BitCounter_ST__16BIT_STATUS_REG EQU CYREG_B1_UDB04_05_ST
+SDCard_BSPIM_BitCounter_ST__MASK_REG EQU CYREG_B1_UDB04_MSK
+SDCard_BSPIM_BitCounter_ST__MASK_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__PER_ST_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CNT_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_CONTROL_REG EQU CYREG_B1_UDB04_ST_CTL
+SDCard_BSPIM_BitCounter_ST__STATUS_REG EQU CYREG_B1_UDB04_ST
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_08_ACTL
+SDCard_BSPIM_RxStsReg__16BIT_STATUS_REG EQU CYREG_B1_UDB07_08_ST
SDCard_BSPIM_RxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_RxStsReg__4__POS EQU 4
SDCard_BSPIM_RxStsReg__5__MASK EQU 0x20
@@ -461,9 +461,9 @@ SDCard_BSPIM_RxStsReg__5__POS EQU 5
SDCard_BSPIM_RxStsReg__6__MASK EQU 0x40
SDCard_BSPIM_RxStsReg__6__POS EQU 6
SDCard_BSPIM_RxStsReg__MASK EQU 0x70
-SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
-SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
-SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
+SDCard_BSPIM_RxStsReg__MASK_REG EQU CYREG_B1_UDB07_MSK
+SDCard_BSPIM_RxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B1_UDB07_ACTL
+SDCard_BSPIM_RxStsReg__STATUS_REG EQU CYREG_B1_UDB07_ST
SDCard_BSPIM_sR8_Dp_u0__16BIT_A0_REG EQU CYREG_B1_UDB04_05_A0
SDCard_BSPIM_sR8_Dp_u0__16BIT_A1_REG EQU CYREG_B1_UDB04_05_A1
SDCard_BSPIM_sR8_Dp_u0__16BIT_D0_REG EQU CYREG_B1_UDB04_05_D0
@@ -481,12 +481,14 @@ SDCard_BSPIM_sR8_Dp_u0__DP_AUX_CTL_REG EQU CYREG_B1_UDB04_ACTL
SDCard_BSPIM_sR8_Dp_u0__F0_F1_REG EQU CYREG_B1_UDB04_F0_F1
SDCard_BSPIM_sR8_Dp_u0__F0_REG EQU CYREG_B1_UDB04_F0
SDCard_BSPIM_sR8_Dp_u0__F1_REG EQU CYREG_B1_UDB04_F1
+SDCard_BSPIM_sR8_Dp_u0__MSK_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
+SDCard_BSPIM_sR8_Dp_u0__PER_DP_AUX_CTL_REG EQU CYREG_B1_UDB04_MSK_ACTL
SDCard_BSPIM_TxStsReg__0__MASK EQU 0x01
SDCard_BSPIM_TxStsReg__0__POS EQU 0
SDCard_BSPIM_TxStsReg__1__MASK EQU 0x02
SDCard_BSPIM_TxStsReg__1__POS EQU 1
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
-SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_08_ACTL
+SDCard_BSPIM_TxStsReg__16BIT_STATUS_REG EQU CYREG_B0_UDB07_08_ST
SDCard_BSPIM_TxStsReg__2__MASK EQU 0x04
SDCard_BSPIM_TxStsReg__2__POS EQU 2
SDCard_BSPIM_TxStsReg__3__MASK EQU 0x08
@@ -494,9 +496,9 @@ SDCard_BSPIM_TxStsReg__3__POS EQU 3
SDCard_BSPIM_TxStsReg__4__MASK EQU 0x10
SDCard_BSPIM_TxStsReg__4__POS EQU 4
SDCard_BSPIM_TxStsReg__MASK EQU 0x1F
-SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB04_MSK
-SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
-SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB04_ST
+SDCard_BSPIM_TxStsReg__MASK_REG EQU CYREG_B0_UDB07_MSK
+SDCard_BSPIM_TxStsReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB07_ACTL
+SDCard_BSPIM_TxStsReg__STATUS_REG EQU CYREG_B0_UDB07_ST
; SD_SCK
SD_SCK__0__INTTYPE EQU CYREG_PICU3_INTTYPE2
@@ -1906,15 +1908,15 @@ SCSI_Out_Bits_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Bits_Sync_ctrl_reg__0__POS EQU 0
SCSI_Out_Bits_Sync_ctrl_reg__1__MASK EQU 0x02
SCSI_Out_Bits_Sync_ctrl_reg__1__POS EQU 1
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB02_03_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB02_03_MSK
-SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB02_03_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB03_04_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB03_04_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB03_04_MSK
SCSI_Out_Bits_Sync_ctrl_reg__2__MASK EQU 0x04
SCSI_Out_Bits_Sync_ctrl_reg__2__POS EQU 2
SCSI_Out_Bits_Sync_ctrl_reg__3__MASK EQU 0x08
@@ -1927,37 +1929,37 @@ SCSI_Out_Bits_Sync_ctrl_reg__6__MASK EQU 0x40
SCSI_Out_Bits_Sync_ctrl_reg__6__POS EQU 6
SCSI_Out_Bits_Sync_ctrl_reg__7__MASK EQU 0x80
SCSI_Out_Bits_Sync_ctrl_reg__7__POS EQU 7
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB02_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB02_CTL
-SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB02_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB03_ST_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB03_CTL
+SCSI_Out_Bits_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB03_ST_CTL
SCSI_Out_Bits_Sync_ctrl_reg__MASK EQU 0xFF
-SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB02_MSK
+SCSI_Out_Bits_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB03_MSK_ACTL
+SCSI_Out_Bits_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB03_MSK
; SCSI_Out_Ctl
SCSI_Out_Ctl_Sync_ctrl_reg__0__MASK EQU 0x01
SCSI_Out_Ctl_Sync_ctrl_reg__0__POS EQU 0
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_02_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB01_02_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB01_02_MSK
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB01_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB01_ST_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB01_CTL
-SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB01_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_CONTROL_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_CONTROL_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_COUNT_COUNT_REG EQU CYREG_B0_UDB04_05_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_MASK_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_MASK_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__16BIT_PERIOD_PERIOD_REG EQU CYREG_B0_UDB04_05_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__CONTROL_ST_REG EQU CYREG_B0_UDB04_ST_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_REG EQU CYREG_B0_UDB04_CTL
+SCSI_Out_Ctl_Sync_ctrl_reg__COUNT_ST_REG EQU CYREG_B0_UDB04_ST_CTL
SCSI_Out_Ctl_Sync_ctrl_reg__MASK EQU 0x01
-SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB01_MSK_ACTL
-SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB01_MSK
+SCSI_Out_Ctl_Sync_ctrl_reg__MASK_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PER_CTL_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+SCSI_Out_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB04_MSK
; SCSI_Out_DBx
SCSI_Out_DBx__0__AG EQU CYREG_PRT5_AG
@@ -2785,8 +2787,8 @@ scsiTarget_StatusReg__0__MASK EQU 0x01
scsiTarget_StatusReg__0__POS EQU 0
scsiTarget_StatusReg__1__MASK EQU 0x02
scsiTarget_StatusReg__1__POS EQU 1
-scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_04_ACTL
-scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB03_04_ST
+scsiTarget_StatusReg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_05_ACTL
+scsiTarget_StatusReg__16BIT_STATUS_REG EQU CYREG_B0_UDB04_05_ST
scsiTarget_StatusReg__2__MASK EQU 0x04
scsiTarget_StatusReg__2__POS EQU 2
scsiTarget_StatusReg__3__MASK EQU 0x08
@@ -2794,9 +2796,13 @@ scsiTarget_StatusReg__3__POS EQU 3
scsiTarget_StatusReg__4__MASK EQU 0x10
scsiTarget_StatusReg__4__POS EQU 4
scsiTarget_StatusReg__MASK EQU 0x1F
-scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB03_MSK
-scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB03_ACTL
-scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB03_ST
+scsiTarget_StatusReg__MASK_REG EQU CYREG_B0_UDB04_MSK
+scsiTarget_StatusReg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_StatusReg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB04_MSK_ACTL
+scsiTarget_StatusReg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB04_ACTL
+scsiTarget_StatusReg__STATUS_CNT_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_StatusReg__STATUS_CONTROL_REG EQU CYREG_B0_UDB04_ST_CTL
+scsiTarget_StatusReg__STATUS_REG EQU CYREG_B0_UDB04_ST
; Debug_Timer_Interrupt
Debug_Timer_Interrupt__INTC_CLR_EN_REG EQU CYREG_NVIC_CLRENA0
@@ -2917,8 +2923,8 @@ SCSI_Filtered_sts_sts_reg__0__MASK EQU 0x01
SCSI_Filtered_sts_sts_reg__0__POS EQU 0
SCSI_Filtered_sts_sts_reg__1__MASK EQU 0x02
SCSI_Filtered_sts_sts_reg__1__POS EQU 1
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_03_ACTL
-SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB02_03_ST
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_09_ACTL
+SCSI_Filtered_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB08_09_ST
SCSI_Filtered_sts_sts_reg__2__MASK EQU 0x04
SCSI_Filtered_sts_sts_reg__2__POS EQU 2
SCSI_Filtered_sts_sts_reg__3__MASK EQU 0x08
@@ -2926,13 +2932,9 @@ SCSI_Filtered_sts_sts_reg__3__POS EQU 3
SCSI_Filtered_sts_sts_reg__4__MASK EQU 0x10
SCSI_Filtered_sts_sts_reg__4__POS EQU 4
SCSI_Filtered_sts_sts_reg__MASK EQU 0x1F
-SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB02_MSK
-SCSI_Filtered_sts_sts_reg__MASK_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__PER_ST_AUX_CTL_REG EQU CYREG_B0_UDB02_MSK_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB02_ACTL
-SCSI_Filtered_sts_sts_reg__STATUS_CNT_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_CONTROL_REG EQU CYREG_B0_UDB02_ST_CTL
-SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB02_ST
+SCSI_Filtered_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB08_MSK
+SCSI_Filtered_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB08_ACTL
+SCSI_Filtered_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB08_ST
; SCSI_CTL_PHASE
SCSI_CTL_PHASE_Sync_ctrl_reg__0__MASK EQU 0x01
@@ -2985,12 +2987,12 @@ SCSI_Glitch_Ctl_Sync_ctrl_reg__PERIOD_REG EQU CYREG_B0_UDB13_MSK
; SCSI_Parity_Error
SCSI_Parity_Error_sts_sts_reg__0__MASK EQU 0x01
SCSI_Parity_Error_sts_sts_reg__0__POS EQU 0
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_12_ACTL
-SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB11_12_ST
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_06_ACTL
+SCSI_Parity_Error_sts_sts_reg__16BIT_STATUS_REG EQU CYREG_B0_UDB05_06_ST
SCSI_Parity_Error_sts_sts_reg__MASK EQU 0x01
-SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB11_MSK
-SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB11_ACTL
-SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB11_ST
+SCSI_Parity_Error_sts_sts_reg__MASK_REG EQU CYREG_B0_UDB05_MSK
+SCSI_Parity_Error_sts_sts_reg__STATUS_AUX_CTL_REG EQU CYREG_B0_UDB05_ACTL
+SCSI_Parity_Error_sts_sts_reg__STATUS_REG EQU CYREG_B0_UDB05_ST
; Miscellaneous
BCLK__BUS_CLK__HZ EQU 50000000
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
index 1828394..0c75e97 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cycdx
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+
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit
index e6b8bee..f8c4c93 100644
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit and b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.cyfit differ
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
index a5792d5..13e987c 100644
--- a/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
+++ b/software/SCSI2SD/v4/SCSI2SD.cydsn/SCSI2SD.svd
@@ -6,165 +6,10 @@
8
32
-
- SCSI_Filtered
- No description available
- 0x40006462
-
- 0
- 0x0
- registers
-
-
-
- SCSI_Filtered_STATUS_REG
- No description available
- 0x0
- 8
- read-write
- 0
- 0
-
-
- SCSI_Filtered_MASK_REG
- No description available
- 0x20
- 8
- read-write
- 0
- 0
-
-
- SCSI_Filtered_STATUS_AUX_CTL_REG
- No description available
- 0x30
- 8
- read-write
- 0
- 0
-
-
- FIFO0
- FIFO0 clear
- 5
- 5
- read-write
-
-
- ENABLED
- Enable counter
- 1
-
-
- DISABLED
- Disable counter
- 0
-
-
-
-
- INTRENBL
- Enables or disables the Interrupt
- 4
- 4
- read-write
-
-
- ENABLED
- Interrupt enabled
- 1
-
-
- DISABLED
- Interrupt disabled
- 0
-
-
-
-
- FIFO1LEVEL
- FIFO level
- 3
- 3
- read-write
-
-
- ENABLED
- FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
- 1
-
-
- DISABLED
- FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
- 0
-
-
-
-
- FIFO0LEVEL
- FIFO level
- 2
- 2
- read-write
-
-
- ENABLED
- FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
- 1
-
-
- DISABLED
- FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
- 0
-
-
-
-
- FIFO1CLEAR
- FIFO clear
- 1
- 1
- read-write
-
-
- ENABLED
- Clear FIFO state
- 1
-
-
- DISABLED
- Normal FIFO operation
- 0
-
-
-
-
- FIFO0CLEAR
- FIFO clear
- 0
- 0
- read-write
-
-
- ENABLED
- Clear FIFO state
- 1
-
-
- DISABLED
- Normal FIFO operation
- 0
-
-
-
-
-
-
-
SCSI_Parity_Error
No description available
- 0x4000646B
+ 0x40006465
0
0x0
@@ -316,6 +161,161 @@
+
+ SCSI_Filtered
+ No description available
+ 0x40006468
+
+ 0
+ 0x0
+ registers
+
+
+
+ SCSI_Filtered_STATUS_REG
+ No description available
+ 0x0
+ 8
+ read-write
+ 0
+ 0
+
+
+ SCSI_Filtered_MASK_REG
+ No description available
+ 0x20
+ 8
+ read-write
+ 0
+ 0
+
+
+ SCSI_Filtered_STATUS_AUX_CTL_REG
+ No description available
+ 0x30
+ 8
+ read-write
+ 0
+ 0
+
+
+ FIFO0
+ FIFO0 clear
+ 5
+ 5
+ read-write
+
+
+ ENABLED
+ Enable counter
+ 1
+
+
+ DISABLED
+ Disable counter
+ 0
+
+
+
+
+ INTRENBL
+ Enables or disables the Interrupt
+ 4
+ 4
+ read-write
+
+
+ ENABLED
+ Interrupt enabled
+ 1
+
+
+ DISABLED
+ Interrupt disabled
+ 0
+
+
+
+
+ FIFO1LEVEL
+ FIFO level
+ 3
+ 3
+ read-write
+
+
+ ENABLED
+ FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
+ 1
+
+
+ DISABLED
+ FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
+ 0
+
+
+
+
+ FIFO0LEVEL
+ FIFO level
+ 2
+ 2
+ read-write
+
+
+ ENABLED
+ FIFO LVL: input mode: FIFO at least 1/2 empty; output mode: FIFO at least 1/2 full
+ 1
+
+
+ DISABLED
+ FIFO LVL: input mode: FIFO not full; output mode: FIFO not empty
+ 0
+
+
+
+
+ FIFO1CLEAR
+ FIFO clear
+ 1
+ 1
+ read-write
+
+
+ ENABLED
+ Clear FIFO state
+ 1
+
+
+ DISABLED
+ Normal FIFO operation
+ 0
+
+
+
+
+ FIFO0CLEAR
+ FIFO clear
+ 0
+ 0
+ read-write
+
+
+ ENABLED
+ Clear FIFO state
+ 1
+
+
+ DISABLED
+ Normal FIFO operation
+ 0
+
+
+
+
+
+
+
SCSI_Glitch_Ctl
No description available
@@ -337,6 +337,298 @@
+
+ Debug_Timer
+ No description available
+ 0x0
+
+ 0
+ 0x0
+ registers
+
+
+
+ Debug_Timer_GLOBAL_ENABLE
+ PM.ACT.CFG
+ 0x400043A3
+ 8
+ read-write
+ 0
+ 0
+
+
+ en_timer
+ Enable timer/counters.
+ 0
+ 3
+ read-write
+
+
+
+
+ Debug_Timer_CONTROL
+ TMRx.CFG0
+ 0x40004F00
+ 8
+ read-write
+ 0
+ 0
+
+
+ EN
+ Enables timer/comparator.
+ 0
+ 0
+ read-write
+
+
+ MODE
+ Mode. (0 = Timer; 1 = Comparator)
+ 1
+ 1
+ read-write
+
+
+ Timer
+ Timer mode. CNT/CMP register holds timer count value.
+ 0
+
+
+ Comparator
+ Comparator mode. CNT/CMP register holds comparator threshold value.
+ 1
+
+
+
+
+ ONESHOT
+ Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.
+ 2
+ 2
+ read-write
+
+
+ CMP_BUFF
+ Buffer compare register. Compare register updates only on timer terminal count.
+ 3
+ 3
+ read-write
+
+
+ INV
+ Invert sense of TIMEREN signal
+ 4
+ 4
+ read-write
+
+
+ DB
+ Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.
+ 5
+ 5
+ read-write
+
+
+ Timer
+ CMP and TC are output.
+ 0
+
+
+ Deadband
+ PHI1 (instead of CMP) and PHI2 (instead of TC) are output.
+ 1
+
+
+
+
+ DEADBAND_PERIOD
+ Deadband Period
+ 6
+ 7
+ read-write
+
+
+
+
+ Debug_Timer_CONTROL2
+ TMRx.CFG1
+ 0x40004F01
+ 8
+ read-write
+ 0
+ 0
+
+
+ IRQ_SEL
+ Irq selection. (0 = raw interrupts; 1 = status register interrupts)
+ 0
+ 0
+ read-write
+
+
+ FTC
+ First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.
+ 1
+ 1
+ read-write
+
+
+ Disable_FTC
+ Disable the single cycle pulse, which signifies the timer is starting.
+ 0
+
+
+ Enable_FTC
+ Enable the single cycle pulse, which signifies the timer is starting.
+ 1
+
+
+
+
+ DCOR
+ Disable Clear on Read (DCOR) of Status Register SR0.
+ 2
+ 2
+ read-write
+
+
+ DBMODE
+ Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).
+ 3
+ 3
+ read-write
+
+
+ CLK_BUS_EN_SEL
+ Digital Global Clock selection.
+ 4
+ 6
+ read-write
+
+
+ BUS_CLK_SEL
+ Bus Clock selection.
+ 7
+ 7
+ read-write
+
+
+
+
+ Debug_Timer_CONTROL3_
+ TMRx.CFG2
+ 0x40004F02
+ 8
+ read-write
+ 0
+ 0
+
+
+ TMR_CFG
+ Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ
+ 0
+ 1
+ read-write
+
+
+ Continuous
+ Timer runs while EN bit of CFG0 register is set to '1'.
+ 0
+
+
+ Pulsewidth
+ Timer runs from positive to negative edge of TIMEREN.
+ 1
+
+
+ Period
+ Timer runs from positive to positive edge of TIMEREN.
+ 2
+
+
+ Irq
+ Timer runs until IRQ.
+ 3
+
+
+
+
+ COD
+ Clear On Disable (COD). Clears or gates outputs to zero.
+ 2
+ 2
+ read-write
+
+
+ ROD
+ Reset On Disable (ROD). Resets internal state of output logic
+ 3
+ 3
+ read-write
+
+
+ CMP_CFG
+ Comparator configurations
+ 4
+ 6
+ read-write
+
+
+ Equal
+ Compare Equal
+ 0
+
+
+ Less_than
+ Compare Less Than
+ 1
+
+
+ Less_than_or_equal
+ Compare Less Than or Equal .
+ 2
+
+
+ Greater
+ Compare Greater Than .
+ 3
+
+
+ Greater_than_or_equal
+ Compare Greater Than or Equal
+ 4
+
+
+
+
+ HW_EN
+ When set Timer Enable controls counting.
+ 7
+ 7
+ read-write
+
+
+
+
+ Debug_Timer_PERIOD
+ TMRx.PER0 - Assigned Period
+ 0x40004F04
+ 16
+ read-write
+ 0
+ 0
+
+
+ Debug_Timer_COUNTER
+ TMRx.CNT_CMP0 - Current Down Counter Value
+ 0x40004F06
+ 16
+ read-write
+ 0
+ 0
+
+
+
SCSI_CTL_PHASE
No description available
@@ -842,302 +1134,10 @@
-
- Debug_Timer
- No description available
- 0x0
-
- 0
- 0x0
- registers
-
-
-
- Debug_Timer_GLOBAL_ENABLE
- PM.ACT.CFG
- 0x400043A3
- 8
- read-write
- 0
- 0
-
-
- en_timer
- Enable timer/counters.
- 0
- 3
- read-write
-
-
-
-
- Debug_Timer_CONTROL
- TMRx.CFG0
- 0x40004F00
- 8
- read-write
- 0
- 0
-
-
- EN
- Enables timer/comparator.
- 0
- 0
- read-write
-
-
- MODE
- Mode. (0 = Timer; 1 = Comparator)
- 1
- 1
- read-write
-
-
- Timer
- Timer mode. CNT/CMP register holds timer count value.
- 0
-
-
- Comparator
- Comparator mode. CNT/CMP register holds comparator threshold value.
- 1
-
-
-
-
- ONESHOT
- Timer stops upon reaching stop condition defined by TMR_CFG bits. Can be restarted by asserting TIMER RESET or disabling and re-enabling block.
- 2
- 2
- read-write
-
-
- CMP_BUFF
- Buffer compare register. Compare register updates only on timer terminal count.
- 3
- 3
- read-write
-
-
- INV
- Invert sense of TIMEREN signal
- 4
- 4
- read-write
-
-
- DB
- Deadband mode--Deadband phases phi1 and phi2 are outputted on CMP and TC output pins respectively.
- 5
- 5
- read-write
-
-
- Timer
- CMP and TC are output.
- 0
-
-
- Deadband
- PHI1 (instead of CMP) and PHI2 (instead of TC) are output.
- 1
-
-
-
-
- DEADBAND_PERIOD
- Deadband Period
- 6
- 7
- read-write
-
-
-
-
- Debug_Timer_CONTROL2
- TMRx.CFG1
- 0x40004F01
- 8
- read-write
- 0
- 0
-
-
- IRQ_SEL
- Irq selection. (0 = raw interrupts; 1 = status register interrupts)
- 0
- 0
- read-write
-
-
- FTC
- First Terminal Count (FTC). Setting this bit forces a single pulse on the TC pin when first enabled.
- 1
- 1
- read-write
-
-
- Disable_FTC
- Disable the single cycle pulse, which signifies the timer is starting.
- 0
-
-
- Enable_FTC
- Enable the single cycle pulse, which signifies the timer is starting.
- 1
-
-
-
-
- DCOR
- Disable Clear on Read (DCOR) of Status Register SR0.
- 2
- 2
- read-write
-
-
- DBMODE
- Deadband mode (asynchronous/synchronous). CMP output pin is also affected when not in deadband mode (CFG0.DEADBAND).
- 3
- 3
- read-write
-
-
- CLK_BUS_EN_SEL
- Digital Global Clock selection.
- 4
- 6
- read-write
-
-
- BUS_CLK_SEL
- Bus Clock selection.
- 7
- 7
- read-write
-
-
-
-
- Debug_Timer_CONTROL3_
- TMRx.CFG2
- 0x40004F02
- 8
- read-write
- 0
- 0
-
-
- TMR_CFG
- Timer configuration (MODE = 0): 000 = Continuous; 001 = Pulsewidth; 010 = Period; 011 = Stop on IRQ
- 0
- 1
- read-write
-
-
- Continuous
- Timer runs while EN bit of CFG0 register is set to '1'.
- 0
-
-
- Pulsewidth
- Timer runs from positive to negative edge of TIMEREN.
- 1
-
-
- Period
- Timer runs from positive to positive edge of TIMEREN.
- 2
-
-
- Irq
- Timer runs until IRQ.
- 3
-
-
-
-
- COD
- Clear On Disable (COD). Clears or gates outputs to zero.
- 2
- 2
- read-write
-
-
- ROD
- Reset On Disable (ROD). Resets internal state of output logic
- 3
- 3
- read-write
-
-
- CMP_CFG
- Comparator configurations
- 4
- 6
- read-write
-
-
- Equal
- Compare Equal
- 0
-
-
- Less_than
- Compare Less Than
- 1
-
-
- Less_than_or_equal
- Compare Less Than or Equal .
- 2
-
-
- Greater
- Compare Greater Than .
- 3
-
-
- Greater_than_or_equal
- Compare Greater Than or Equal
- 4
-
-
-
-
- HW_EN
- When set Timer Enable controls counting.
- 7
- 7
- read-write
-
-
-
-
- Debug_Timer_PERIOD
- TMRx.PER0 - Assigned Period
- 0x40004F04
- 16
- read-write
- 0
- 0
-
-
- Debug_Timer_COUNTER
- TMRx.CNT_CMP0 - Current Down Counter Value
- 0x40004F06
- 16
- read-write
- 0
- 0
-
-
-
SCSI_Out_Ctl
No description available
- 0x40006471
+ 0x40006474
0
0x0
@@ -1158,7 +1158,7 @@
SCSI_Out_Bits
No description available
- 0x40006472
+ 0x40006473
0
0x0
diff --git a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch
index fdaa05f..54f0773 100755
Binary files a/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch and b/software/SCSI2SD/v4/SCSI2SD.cydsn/TopDesign/TopDesign.cysch differ
diff --git a/software/scsi2sd-util/BoardPanel.cc b/software/scsi2sd-util/BoardPanel.cc
index fc69ae6..fb9218a 100644
--- a/software/scsi2sd-util/BoardPanel.cc
+++ b/software/scsi2sd-util/BoardPanel.cc
@@ -46,26 +46,41 @@ namespace
return std::make_pair(value, static_cast(conv));
}
- void CtrlGetFixedString(wxTextEntry* ctrl, char* dest, size_t len)
- {
- memset(dest, ' ', len);
- std::string str(ctrl->GetValue().ToAscii());
- // Don't use strncpy - we need to avoid NULL's
- memcpy(dest, str.c_str(), std::min(len, str.size()));
- }
-
- bool CtrlIsAscii(wxTextEntry* ctrl)
- {
- return ctrl->GetValue().IsAscii();
- }
-
}
BoardPanel::BoardPanel(wxWindow* parent, const BoardConfig& initialConfig) :
wxPanel(parent),
- myParent(parent)
+ myParent(parent),
+ myDelayValidator(new wxIntegerValidator)
{
- wxFlexGridSizer *fgs = new wxFlexGridSizer(6, 2, 9, 25);
+ wxFlexGridSizer *fgs = new wxFlexGridSizer(8, 2, 9, 25);
+
+ fgs->Add(new wxStaticText(this, wxID_ANY, _("Startup Delay (seconds)")));
+ myStartDelayCtrl =
+ new wxTextCtrl(
+ this,
+ ID_startDelayCtrl,
+ "0",
+ wxDefaultPosition,
+ wxDefaultSize,
+ 0,
+ *myDelayValidator);
+ myStartDelayCtrl->SetToolTip(_("Extra delay on power on, normally set to 0"));
+ fgs->Add(myStartDelayCtrl);
+
+
+ fgs->Add(new wxStaticText(this, wxID_ANY, _("SCSI Selection Delay (ms, 255 = auto)")));
+ mySelDelayCtrl =
+ new wxTextCtrl(
+ this,
+ ID_selDelayCtrl,
+ "255",
+ wxDefaultPosition,
+ wxDefaultSize,
+ 0,
+ *myDelayValidator);
+ mySelDelayCtrl->SetToolTip(_("Delay before responding to SCSI selection. SCSI1 hosts usually require 1ms delay, however some require no delay"));
+ fgs->Add(mySelDelayCtrl);
fgs->Add(new wxStaticText(this, wxID_ANY, wxT("")));
myParityCtrl =
@@ -147,6 +162,8 @@ BoardPanel::getConfig() const
(myCacheCtrl->IsChecked() ? CONFIG_ENABLE_CACHE: 0) |
(myDisconnectCtrl->IsChecked() ? CONFIG_ENABLE_DISCONNECT: 0);
+ config.startupDelay = CtrlGetValue(myStartDelayCtrl).first;
+ config.selectionDelay = CtrlGetValue(mySelDelayCtrl).first;
return config;
}
@@ -161,6 +178,17 @@ BoardPanel::setConfig(const BoardConfig& config)
myGlitchCtrl->SetValue(config.flags & CONFIG_DISABLE_GLITCH);
myCacheCtrl->SetValue(config.flags & CONFIG_ENABLE_CACHE);
myDisconnectCtrl->SetValue(config.flags & CONFIG_ENABLE_DISCONNECT);
+
+ {
+ std::stringstream conv;
+ conv << static_cast(config.startupDelay);
+ myStartDelayCtrl->ChangeValue(conv.str());
+ }
+ {
+ std::stringstream conv;
+ conv << static_cast(config.selectionDelay);
+ mySelDelayCtrl->ChangeValue(conv.str());
+ }
}
diff --git a/software/scsi2sd-util/BoardPanel.hh b/software/scsi2sd-util/BoardPanel.hh
index 210c2a8..4ecc886 100644
--- a/software/scsi2sd-util/BoardPanel.hh
+++ b/software/scsi2sd-util/BoardPanel.hh
@@ -57,7 +57,9 @@ private:
ID_scsi2Ctrl,
ID_glitchCtrl,
ID_cacheCtrl,
- ID_disconnectCtrl
+ ID_disconnectCtrl,
+ ID_startDelayCtrl,
+ ID_selDelayCtrl
};
wxWindow* myParent;
@@ -70,6 +72,10 @@ private:
wxCheckBox* myGlitchCtrl;
wxCheckBox* myCacheCtrl;
wxCheckBox* myDisconnectCtrl;
+
+ wxIntegerValidator* myDelayValidator;
+ wxTextCtrl* myStartDelayCtrl;
+ wxTextCtrl* mySelDelayCtrl;
};
} // namespace SCSI2SD
diff --git a/software/scsi2sd-util/scsi2sd-util.cc b/software/scsi2sd-util/scsi2sd-util.cc
index b111d8e..e78e11e 100644
--- a/software/scsi2sd-util/scsi2sd-util.cc
+++ b/software/scsi2sd-util/scsi2sd-util.cc
@@ -378,6 +378,7 @@ private:
void OnID_ConfigDefaults(wxCommandEvent& event)
{
+ myBoardPanel->setConfig(ConfigUtil::DefaultBoardConfig());
for (size_t i = 0; i < myTargets.size(); ++i)
{
myTargets[i]->setConfig(ConfigUtil::Default(i));