mirror of
https://github.com/fhgwright/SCSI2SD.git
synced 2025-03-23 05:30:25 +00:00
1127 lines
19 KiB
Plaintext
1127 lines
19 KiB
Plaintext
v 20060113 1
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T 17100 450 9 8 1 1 90 0 1
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pinlabel=P3[5]
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T 17100 450 5 8 0 1 90 2 1
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pintype=io
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P 17800 100 17800 400 1 0 0
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{
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T 17750 300 5 8 1 1 90 6 1
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T 17850 300 5 8 0 1 90 8 1
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T 17800 450 9 8 1 1 90 0 1
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pinlabel=VDDIO3
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T 17800 450 5 8 0 1 90 2 1
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P 18700 17900 18400 17900 1 0 0
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{
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T 18500 17950 5 8 1 1 0 0 1
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T 18500 17850 5 8 0 1 0 2 1
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T 18350 17900 9 8 1 1 0 6 1
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pinlabel=VDDIO0
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T 18350 17900 5 8 0 1 0 8 1
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P 18700 17200 18400 17200 1 0 0
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{
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T 18500 17250 5 8 1 1 0 0 1
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T 18500 17150 5 8 0 1 0 2 1
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T 18350 17200 9 8 1 1 0 6 1
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pinlabel=P0[3]
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T 18350 17200 5 8 0 1 0 8 1
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P 18700 16500 18400 16500 1 0 0
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{
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T 18500 16550 5 8 1 1 0 0 1
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T 18500 16450 5 8 0 1 0 2 1
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T 18350 16500 9 8 1 1 0 6 1
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pinlabel=P0[2]
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T 18350 16500 5 8 0 1 0 8 1
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pintype=io
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P 18700 15800 18400 15800 1 0 0
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{
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T 18500 15850 5 8 1 1 0 0 1
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T 18500 15750 5 8 0 1 0 2 1
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T 18350 15800 9 8 1 1 0 6 1
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pinlabel=P0[1]
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T 18350 15800 5 8 0 1 0 8 1
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P 18700 15100 18400 15100 1 0 0
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{
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T 18500 15150 5 8 1 1 0 0 1
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T 18500 15050 5 8 0 1 0 2 1
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T 18350 15100 9 8 1 1 0 6 1
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pinlabel=P0[0]
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T 18350 15100 5 8 0 1 0 8 1
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P 18700 14400 18400 14400 1 0 0
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{
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T 18500 14350 5 8 0 1 0 2 1
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T 18350 14400 9 8 1 1 0 6 1
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pinlabel=P4[1]
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T 18350 14400 5 8 0 1 0 8 1
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P 18700 13700 18400 13700 1 0 0
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{
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T 18500 13650 5 8 0 1 0 2 1
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T 18350 13700 9 8 1 1 0 6 1
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pinlabel=P4[0]
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T 18350 13700 5 8 0 1 0 8 1
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P 18700 13000 18400 13000 1 0 0
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{
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T 18500 12950 5 8 0 1 0 2 1
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pinseq=58
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T 18350 13000 9 8 1 1 0 6 1
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pinlabel=P12[3]
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T 18350 13000 5 8 0 1 0 8 1
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pintype=io
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P 18700 12300 18400 12300 1 0 0
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{
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T 18500 12350 5 8 1 1 0 0 1
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T 18500 12250 5 8 0 1 0 2 1
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pinseq=59
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T 18350 12300 9 8 1 1 0 6 1
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pinlabel=P12[2]
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T 18350 12300 5 8 0 1 0 8 1
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pintype=io
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P 18700 11600 18400 11600 1 0 0
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{
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T 18500 11650 5 8 1 1 0 0 1
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pinnumber=66
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T 18500 11550 5 8 0 1 0 2 1
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pinseq=60
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T 18350 11600 9 8 1 1 0 6 1
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pinlabel=VSSD
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T 18350 11600 5 8 0 1 0 8 1
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P 18700 10900 18400 10900 1 0 0
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{
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T 18500 10950 5 8 1 1 0 0 1
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pinnumber=65
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T 18500 10850 5 8 0 1 0 2 1
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pinseq=61
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T 18350 10900 9 8 1 1 0 6 1
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pinlabel=VDDA
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T 18350 10900 5 8 0 1 0 8 1
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pintype=pwr
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P 18700 10200 18400 10200 1 0 0
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{
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T 18500 10250 5 8 1 1 0 0 1
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T 18500 10150 5 8 0 1 0 2 1
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pinseq=62
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T 18350 10200 9 8 1 1 0 6 1
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pinlabel=VSSA
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T 18350 10200 5 8 0 1 0 8 1
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pintype=pwr
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P 18700 9500 18400 9500 1 0 0
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{
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T 18500 9550 5 8 1 1 0 0 1
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T 18500 9450 5 8 0 1 0 2 1
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pinseq=63
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T 18350 9500 9 8 1 1 0 6 1
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pinlabel=VCCA
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T 18350 9500 5 8 0 1 0 8 1
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pintype=pwr
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P 18700 8800 18400 8800 1 0 0
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{
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T 18500 8850 5 8 1 1 0 0 1
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T 18500 8750 5 8 0 1 0 2 1
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pinseq=64
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T 18350 8800 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 8800 5 8 0 1 0 8 1
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pintype=io
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P 18700 8100 18400 8100 1 0 0
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{
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T 18500 8150 5 8 1 1 0 0 1
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T 18500 8050 5 8 0 1 0 2 1
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pinseq=65
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T 18350 8100 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 8100 5 8 0 1 0 8 1
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pintype=io
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P 18700 7400 18400 7400 1 0 0
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{
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T 18500 7450 5 8 1 1 0 0 1
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pinnumber=60
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T 18500 7350 5 8 0 1 0 2 1
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pinseq=66
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T 18350 7400 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 7400 5 8 0 1 0 8 1
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pintype=io
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P 18700 6700 18400 6700 1 0 0
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{
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T 18500 6750 5 8 1 1 0 0 1
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pinnumber=59
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T 18500 6650 5 8 0 1 0 2 1
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pinseq=67
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T 18350 6700 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 6700 5 8 0 1 0 8 1
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pintype=io
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P 18700 6000 18400 6000 1 0 0
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{
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T 18500 6050 5 8 1 1 0 0 1
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pinnumber=58
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T 18500 5950 5 8 0 1 0 2 1
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pinseq=68
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T 18350 6000 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 6000 5 8 0 1 0 8 1
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pintype=io
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P 18700 5300 18400 5300 1 0 0
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{
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T 18500 5350 5 8 1 1 0 0 1
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pinnumber=57
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T 18500 5250 5 8 0 1 0 2 1
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pinseq=69
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T 18350 5300 9 8 1 1 0 6 1
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pinlabel=NC
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T 18350 5300 5 8 0 1 0 8 1
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pintype=io
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P 18700 4600 18400 4600 1 0 0
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{
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T 18500 4650 5 8 1 1 0 0 1
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pinnumber=56
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T 18500 4550 5 8 0 1 0 2 1
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pinseq=70
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T 18350 4600 9 8 1 1 0 6 1
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pinlabel=XI XTAL P15[3],KHZ
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T 18350 4600 5 8 0 1 0 8 1
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pintype=io
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P 18700 3900 18400 3900 1 0 0
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{
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T 18500 3950 5 8 1 1 0 0 1
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pinnumber=55
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T 18500 3850 5 8 0 1 0 2 1
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pinseq=71
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T 18350 3900 9 8 1 1 0 6 1
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pinlabel=XO XTAL P15[2],KHZ
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T 18350 3900 5 8 0 1 0 8 1
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pintype=io
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P 18700 3200 18400 3200 1 0 0
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{
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T 18500 3250 5 8 1 1 0 0 1
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pinnumber=54
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T 18500 3150 5 8 0 1 0 2 1
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pinseq=72
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T 18350 3200 9 8 1 1 0 6 1
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pinlabel=P12[1]
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T 18350 3200 5 8 0 1 0 8 1
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pintype=io
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P 18700 2500 18400 2500 1 0 0
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{
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T 18500 2550 5 8 1 1 0 0 1
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pinnumber=53
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T 18500 2450 5 8 0 1 0 2 1
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pinseq=73
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T 18350 2500 9 8 1 1 0 6 1
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pinlabel=P12[0]
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T 18350 2500 5 8 0 1 0 8 1
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pintype=io
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P 18700 1800 18400 1800 1 0 0
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{
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T 18500 1850 5 8 1 1 0 0 1
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pinnumber=52
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T 18500 1750 5 8 0 1 0 2 1
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pinseq=74
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T 18350 1800 9 8 1 1 0 6 1
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pinlabel=P3[7]
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T 18350 1800 5 8 0 1 0 8 1
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pintype=io
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P 18700 1100 18400 1100 1 0 0
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{
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T 18500 1150 5 8 1 1 0 0 1
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pinnumber=51
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T 18500 1050 5 8 0 1 0 2 1
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pinseq=75
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T 18350 1100 9 8 1 1 0 6 1
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pinlabel=P3[6]
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T 18350 1100 5 8 0 1 0 8 1
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pintype=io
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P 1000 18900 1000 18600 1 0 0
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{
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T 950 18700 5 8 1 1 90 0 1
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pinnumber=100
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T 1050 18700 5 8 0 1 90 2 1
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pinseq=76
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T 1000 18550 9 8 1 1 90 6 1
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pinlabel=VDDIO2
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T 1000 18550 5 8 0 1 90 8 1
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{
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T 1650 18700 5 8 1 1 90 0 1
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pinnumber=99
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T 1750 18700 5 8 0 1 90 2 1
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pinseq=77
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T 1700 18550 9 8 1 1 90 6 1
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pinlabel=P2[4]
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T 1700 18550 5 8 0 1 90 8 1
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P 2400 18900 2400 18600 1 0 0
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{
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T 2350 18700 5 8 1 1 90 0 1
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pinnumber=98
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T 2450 18700 5 8 0 1 90 2 1
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pinseq=78
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T 2400 18550 9 8 1 1 90 6 1
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pinlabel=P2[3]
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T 2400 18550 5 8 0 1 90 8 1
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pintype=io
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P 3100 18900 3100 18600 1 0 0
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{
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T 3050 18700 5 8 1 1 90 0 1
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pinnumber=97
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T 3150 18700 5 8 0 1 90 2 1
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pinseq=79
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T 3100 18550 9 8 1 1 90 6 1
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pinlabel=P2[2]
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T 3100 18550 5 8 0 1 90 8 1
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pintype=io
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P 3800 18900 3800 18600 1 0 0
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{
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T 3750 18700 5 8 1 1 90 0 1
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pinnumber=96
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T 3850 18700 5 8 0 1 90 2 1
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pinseq=80
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T 3800 18550 9 8 1 1 90 6 1
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pinlabel=P2[1]
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T 3800 18550 5 8 0 1 90 8 1
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pintype=io
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P 4500 18900 4500 18600 1 0 0
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{
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T 4450 18700 5 8 1 1 90 0 1
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pinnumber=95
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T 4550 18700 5 8 0 1 90 2 1
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pinseq=81
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T 4500 18550 9 8 1 1 90 6 1
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pinlabel=P2[0]
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T 4500 18550 5 8 0 1 90 8 1
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pintype=io
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P 5200 18900 5200 18600 1 0 0
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{
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T 5150 18700 5 8 1 1 90 0 1
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pinnumber=94
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T 5250 18700 5 8 0 1 90 2 1
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pinseq=82
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T 5200 18550 9 8 1 1 90 6 1
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pinlabel=P15[5]
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T 5200 18550 5 8 0 1 90 8 1
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pintype=io
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P 5900 18900 5900 18600 1 0 0
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{
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T 5850 18700 5 8 1 1 90 0 1
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pinnumber=93
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T 5950 18700 5 8 0 1 90 2 1
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pinseq=83
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T 5900 18550 9 8 1 1 90 6 1
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pinlabel=P15[4]
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T 5900 18550 5 8 0 1 90 8 1
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pintype=io
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P 6600 18900 6600 18600 1 0 0
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{
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T 6550 18700 5 8 1 1 90 0 1
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pinnumber=92
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T 6650 18700 5 8 0 1 90 2 1
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pinseq=84
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T 6600 18550 9 8 1 1 90 6 1
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pinlabel=P6[3]
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T 6600 18550 5 8 0 1 90 8 1
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pintype=io
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P 7300 18900 7300 18600 1 0 0
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{
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T 7250 18700 5 8 1 1 90 0 1
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pinnumber=91
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T 7350 18700 5 8 0 1 90 2 1
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pinseq=85
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T 7300 18550 9 8 1 1 90 6 1
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pinlabel=P6[2]
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T 7300 18550 5 8 0 1 90 8 1
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pintype=io
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P 8000 18900 8000 18600 1 0 0
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{
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T 7950 18700 5 8 1 1 90 0 1
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pinnumber=90
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T 8050 18700 5 8 0 1 90 2 1
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pinseq=86
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T 8000 18550 9 8 1 1 90 6 1
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pinlabel=P6[1]
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T 8000 18550 5 8 0 1 90 8 1
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pintype=io
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P 8700 18900 8700 18600 1 0 0
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{
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T 8650 18700 5 8 1 1 90 0 1
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pinnumber=89
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T 8750 18700 5 8 0 1 90 2 1
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pinseq=87
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T 8700 18550 9 8 1 1 90 6 1
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pinlabel=P6[0]
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T 8700 18550 5 8 0 1 90 8 1
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pintype=io
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P 9400 18900 9400 18600 1 0 0
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{
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T 9350 18700 5 8 1 1 90 0 1
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pinnumber=88
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T 9450 18700 5 8 0 1 90 2 1
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pinseq=88
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T 9400 18550 9 8 1 1 90 6 1
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pinlabel=VDDD
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T 9400 18550 5 8 0 1 90 8 1
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pintype=pwr
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P 10100 18900 10100 18600 1 0 0
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{
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T 10050 18700 5 8 1 1 90 0 1
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pinnumber=87
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T 10150 18700 5 8 0 1 90 2 1
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pinseq=89
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T 10100 18550 9 8 1 1 90 6 1
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pinlabel=VSSD
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T 10100 18550 5 8 0 1 90 8 1
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pintype=pwr
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P 10800 18900 10800 18600 1 0 0
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{
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T 10750 18700 5 8 1 1 90 0 1
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pinnumber=86
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T 10850 18700 5 8 0 1 90 2 1
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pinseq=90
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T 10800 18550 9 8 1 1 90 6 1
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pinlabel=VCCD
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T 10800 18550 5 8 0 1 90 8 1
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pintype=pwr
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P 11500 18900 11500 18600 1 0 0
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{
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T 11450 18700 5 8 1 1 90 0 1
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pinnumber=85
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T 11550 18700 5 8 0 1 90 2 1
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pinseq=91
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T 11500 18550 9 8 1 1 90 6 1
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pinlabel=P4[7]
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T 11500 18550 5 8 0 1 90 8 1
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pintype=io
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P 12200 18900 12200 18600 1 0 0
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{
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T 12150 18700 5 8 1 1 90 0 1
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pinnumber=84
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T 12250 18700 5 8 0 1 90 2 1
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pinseq=92
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T 12200 18550 9 8 1 1 90 6 1
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pinlabel=P4[6]
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T 12200 18550 5 8 0 1 90 8 1
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pintype=io
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P 12900 18900 12900 18600 1 0 0
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{
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T 12850 18700 5 8 1 1 90 0 1
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pinnumber=83
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T 12950 18700 5 8 0 1 90 2 1
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pinseq=93
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T 12900 18550 9 8 1 1 90 6 1
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pinlabel=P4[5]
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T 12900 18550 5 8 0 1 90 8 1
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pintype=io
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P 13600 18900 13600 18600 1 0 0
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{
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T 13550 18700 5 8 1 1 90 0 1
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pinnumber=82
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T 13650 18700 5 8 0 1 90 2 1
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pinseq=94
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T 13600 18550 9 8 1 1 90 6 1
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pinlabel=P4[4]
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T 13600 18550 5 8 0 1 90 8 1
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pintype=io
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P 14300 18900 14300 18600 1 0 0
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{
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T 14250 18700 5 8 1 1 90 0 1
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pinnumber=81
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T 14350 18700 5 8 0 1 90 2 1
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pinseq=95
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T 14300 18550 9 8 1 1 90 6 1
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pinlabel=P4[3]
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T 14300 18550 5 8 0 1 90 8 1
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pintype=io
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P 15000 18900 15000 18600 1 0 0
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{
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T 14950 18700 5 8 1 1 90 0 1
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pinnumber=80
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T 15050 18700 5 8 0 1 90 2 1
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pinseq=96
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T 15000 18550 9 8 1 1 90 6 1
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pinlabel=P4[2]
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T 15000 18550 5 8 0 1 90 8 1
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pintype=io
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P 15700 18900 15700 18600 1 0 0
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{
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T 15650 18700 5 8 1 1 90 0 1
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pinnumber=79
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|
T 15750 18700 5 8 0 1 90 2 1
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pinseq=97
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T 15700 18550 9 8 1 1 90 6 1
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pinlabel=P0[7]
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T 15700 18550 5 8 0 1 90 8 1
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pintype=io
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}
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P 16400 18900 16400 18600 1 0 0
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{
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T 16350 18700 5 8 1 1 90 0 1
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pinnumber=78
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T 16450 18700 5 8 0 1 90 2 1
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pinseq=98
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T 16400 18550 9 8 1 1 90 6 1
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pinlabel=P0[6]
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T 16400 18550 5 8 0 1 90 8 1
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pintype=io
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}
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P 17100 18900 17100 18600 1 0 0
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{
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T 17050 18700 5 8 1 1 90 0 1
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pinnumber=77
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T 17150 18700 5 8 0 1 90 2 1
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pinseq=99
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T 17100 18550 9 8 1 1 90 6 1
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pinlabel=P0[5]
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T 17100 18550 5 8 0 1 90 8 1
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pintype=io
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}
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P 17800 18900 17800 18600 1 0 0
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{
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T 17750 18700 5 8 1 1 90 0 1
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pinnumber=76
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T 17850 18700 5 8 0 1 90 2 1
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pinseq=100
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T 17800 18550 9 8 1 1 90 6 1
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pinlabel=P0[4]
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T 17800 18550 5 8 0 1 90 8 1
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pintype=io
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}
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B 400 400 18000 18200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
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|
T 18400 18700 8 10 1 1 0 6 1
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refdes=U?
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T 9200 9400 9 10 1 0 0 0 1
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CY8C53
|
|
T 9200 9700 5 10 0 0 0 0 1
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device=CY8C53
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|
T 9200 9900 5 10 0 0 0 0 1
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footprint=TQFP100_14
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T 9200 10100 5 10 0 0 0 0 1
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author=Michael McMaster <michael@codesrc.com>
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T 9200 10300 5 10 0 0 0 0 1
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documentation=http://www.cypress.com/?id=2233
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T 9200 10500 5 10 0 0 0 0 1
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description=Cypress PSoC5 CY8C53
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T 9200 10700 5 10 0 0 0 0 1
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numslots=0
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T 9200 10900 5 10 0 0 0 0 1
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dist-license=gpl3+
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T 9200 11100 5 10 0 0 0 0 1
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use-license=gpl3+
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