466 lines
13 KiB
C
466 lines
13 KiB
C
// Copyright (C) 2013 Michael McMaster <michael@codesrc.com>
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//
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// This file is part of SCSI2SD.
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//
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// SCSI2SD is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// SCSI2SD is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with SCSI2SD. If not, see <http://www.gnu.org/licenses/>.
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#include "device.h"
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#include "flash.h"
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#include "config.h"
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#include "led.h"
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#include "time.h"
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typedef struct
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{
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S2S_Device dev;
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S2S_Target targets[MAX_SCSI_TARGETS];
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uint32_t capacity; // in 512 byte blocks
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// CFI info
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uint8_t manufacturerID;
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uint8_t deviceID[2];
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} SpiFlash;
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static void spiFlash_earlyInit(S2S_Device* dev);
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static void spiFlash_init(S2S_Device* dev);
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static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count);
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static uint32_t spiFlash_getCapacity(S2S_Device* dev);
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static int spiFlash_pollMediaChange(S2S_Device* dev);
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static void spiFlash_pollMediaBusy(S2S_Device* dev);
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static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count);
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static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
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static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer);
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static int spiFlash_readAsyncPoll(S2S_Device* dev);
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static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, const uint8_t* buffer);
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SpiFlash spiFlash = {
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{
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spiFlash_earlyInit,
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spiFlash_init,
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spiFlash_getTargets,
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spiFlash_getCapacity,
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spiFlash_pollMediaChange,
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spiFlash_pollMediaBusy,
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spiFlash_erase,
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spiFlash_read,
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spiFlash_readAsync,
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spiFlash_readAsyncPoll,
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spiFlash_write,
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0, // initial mediaState
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CONFIG_STOREDEVICE_FLASH
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}
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};
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S2S_Device* spiFlashDevice = &(spiFlash.dev);
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// Private DMA variables.
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static uint8 spiFlashDMARxChan = CY_DMA_INVALID_CHANNEL;
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static uint8 spiFlashDMATxChan = CY_DMA_INVALID_CHANNEL;
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static uint8_t spiFlashDmaRxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
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static uint8_t spiFlashDmaTxTd[2] = { CY_DMA_INVALID_TD, CY_DMA_INVALID_TD };
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// Source of dummy SPI bytes for DMA
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static uint8_t dummyBuffer[2] __attribute__((aligned(4))) = {0xFF, 0xFF};
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// Dummy location for DMA to sink usless data to
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static uint8 discardBuffer[2] __attribute__((aligned(4)));
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volatile uint8_t spiFlashRxDMAComplete = 1;
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volatile uint8_t spiFlashTxDMAComplete = 1;
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CY_ISR_PROTO(spiFlashRxISR);
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CY_ISR(spiFlashRxISR)
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{
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spiFlashRxDMAComplete = 1;
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}
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CY_ISR_PROTO(spiFlashTxISR);
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CY_ISR(spiFlashTxISR)
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{
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spiFlashTxDMAComplete = 1;
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}
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// Read and write 1 byte.
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static uint8_t spiFlashByte(uint8_t value)
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{
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NOR_SPI_WriteTxData(value);
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while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
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return NOR_SPI_ReadRxData();
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}
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static void spiFlash_earlyInit(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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for (int i = 0; i < MAX_SCSI_TARGETS; ++i)
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{
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spiFlash->targets[i].device = dev;
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const S2S_TargetCfg* cfg = getConfigByIndex(i);
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if (cfg->storageDevice == CONFIG_STOREDEVICE_FLASH)
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{
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spiFlash->targets[i].cfg = (S2S_TargetCfg*)cfg;
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}
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else
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{
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spiFlash->targets[i].cfg = NULL;
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}
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}
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// Don't require the host to send us a START STOP UNIT command
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spiFlash->dev.mediaState = MEDIA_STARTED | MEDIA_WP;
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// DMA stuff
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spiFlashDMATxChan =
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NOR_TX_DMA_DmaInitialize(
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2, // Bytes per burst
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1, // request per burst
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HI16(CYDEV_SRAM_BASE),
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HI16(CYDEV_PERIPH_BASE)
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);
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spiFlashDMARxChan =
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NOR_RX_DMA_DmaInitialize(
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1, // Bytes per burst
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1, // request per burst
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HI16(CYDEV_PERIPH_BASE),
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HI16(CYDEV_SRAM_BASE)
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);
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CyDmaChDisable(spiFlashDMATxChan);
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CyDmaChDisable(spiFlashDMARxChan);
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NOR_RX_DMA_COMPLETE_StartEx(spiFlashRxISR);
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NOR_TX_DMA_COMPLETE_StartEx(spiFlashTxISR);
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spiFlashDmaRxTd[0] = CyDmaTdAllocate();
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spiFlashDmaRxTd[1] = CyDmaTdAllocate();
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spiFlashDmaTxTd[0] = CyDmaTdAllocate();
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spiFlashDmaTxTd[1] = CyDmaTdAllocate();
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}
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static void spiFlash_init(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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spiFlash->capacity = 0;
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nNOR_WP_Write(1); // We don't need write Protect
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nNOR_CS_Write(1); // Deselect
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NOR_SPI_Start();
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CyDelayUs(50); // tRPH is 35 uS. Wait a bit longer
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// Mode-bit-reset (go back to normal from high performance mode)
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nNOR_CS_Write(0); // Select
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CyDelayCycles(4); // Tiny delay
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spiFlashByte(0xFF);
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nNOR_CS_Write(1); // Deselect
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CyDelayCycles(4); // Tiny delay
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// Software-reset
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nNOR_CS_Write(0); // Select
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CyDelayCycles(4); // Tiny delay
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spiFlashByte(0xF0);
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nNOR_CS_Write(1); // Deselect - reset is triggered on the deselect
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CyDelayUs(50); // tRPH is 35 uS. Wait a bit longer
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nNOR_CS_Write(0); // Select
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// JEDEC standard "Read Identification" command
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// returns CFI information
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spiFlashByte(0x9F);
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// 1 byte manufacturer ID
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spiFlash->manufacturerID = spiFlashByte(0xFF);
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// 2 bytes device ID
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spiFlash->deviceID[0] = spiFlashByte(0xFF);
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spiFlash->deviceID[1] = spiFlashByte(0xFF);
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uint8_t bytesFollowing = spiFlashByte(0xFF);
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// Chances are this says 0, which means up to 512 bytes.
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// But ignore it for now and just get the capacity.
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for (int i = 0; i < 0x23; ++i)
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{
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spiFlashByte(0xFF);
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}
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// Capacity is 2^n at offset 0x27
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//spiFlash->capacity = (1 << spiFlashByte(0xFF)) / 512;
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// Record value in 512-byte sectors.
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spiFlash->capacity = 1 << (spiFlashByte(0xFF) - 9);
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if (spiFlash->capacity > 0)
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{
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spiFlash->dev.mediaState |= MEDIA_PRESENT | MEDIA_INITIALISED;
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}
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// Don't bother reading the rest. Deselecting will cancel the command.
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nNOR_CS_Write(1); // Deselect
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}
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static S2S_Target* spiFlash_getTargets(S2S_Device* dev, int* count)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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*count = MAX_SCSI_TARGETS;
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return spiFlash->targets;
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}
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static uint32_t spiFlash_getCapacity(S2S_Device* dev)
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{
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SpiFlash* spiFlash = (SpiFlash*)dev;
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return spiFlash->capacity;
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}
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static int spiFlash_pollMediaChange(S2S_Device* dev)
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{
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// Non-removable
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return 0;
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}
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static void spiFlash_pollMediaBusy(S2S_Device* dev)
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{
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// Non-removable
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}
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static void spiFlash_WaitForWIP()
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{
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int inProgress = 1;
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while (inProgress)
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{
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nNOR_CS_Write(0);
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uint8_t status = spiFlashByte(0x05); // Read Status Register 1;
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inProgress = status & 1;
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nNOR_CS_Write(1);
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}
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}
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static void spiFlash_erase(S2S_Device* dev, uint32_t sectorNumber, uint32_t count)
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{
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// SpiFlash* spiFlash = (SpiFlash*)dev;
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nNOR_CS_Write(0); // Select
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// Send the WREN - Write Enable command
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spiFlashByte(0x06);
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// We NEED to deselect the device now for writes to work
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nNOR_CS_Write(1);
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// For now we assume 256kb sectors. This needs to be expanded to cater for
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// different sector sizes. We safely assume it will always be >= 512 bytes.
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const uint32_t flashSectorSize = 256*1024;
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// We don't have enough memory to do a read-modify-write cycle, so the caller
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// had better line these up on sector boundaries.
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for (uint32_t linearAddress = sectorNumber * 512;
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linearAddress < (sectorNumber + count) * 512;
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linearAddress += flashSectorSize)
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{
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nNOR_CS_Write(0);
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spiFlashByte(0xDC);
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// 4-byte address
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spiFlashByte(linearAddress >> 24);
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spiFlashByte(linearAddress >> 16);
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spiFlashByte(linearAddress >> 8);
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spiFlashByte(linearAddress);
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// Initiate erase
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nNOR_CS_Write(1);
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spiFlash_WaitForWIP();
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}
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nNOR_CS_Write(0);
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// Send the WREN - Write Disable command
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spiFlashByte(0x04);
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nNOR_CS_Write(1); // Deselect
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}
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static void spiFlash_write(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, const uint8_t* buffer)
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{
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// SpiFlash* spiFlash = (SpiFlash*)dev;
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nNOR_CS_Write(0); // Select
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// Send the WREN - Write Enable command
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spiFlashByte(0x06);
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// We NEED to deselect the device now for writes to work
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nNOR_CS_Write(1);
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// We're assuming here that the page size is 512 bytes or more.
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for (unsigned int i = 0; i < count; ++i)
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{
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nNOR_CS_Write(0);
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spiFlashByte(0x12);
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uint32_t linearAddress = (sectorNumber + i) * 512;
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spiFlashByte(linearAddress >> 24);
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spiFlashByte(linearAddress >> 16);
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spiFlashByte(linearAddress >> 8);
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spiFlashByte(linearAddress);
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for (int off = 0; off < 512; ++off)
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{
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spiFlashByte(buffer[i * 512 + off]);
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}
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// Initiate write
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nNOR_CS_Write(1);
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spiFlash_WaitForWIP();
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}
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nNOR_CS_Write(0);
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// Send the WREN - Write Disable command
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spiFlashByte(0x04);
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nNOR_CS_Write(1); // Deselect
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}
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static void spiFlash_read(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
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{
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// SpiFlash* spiFlash = (SpiFlash*)dev;
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nNOR_CS_Write(0); // Select
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spiFlashByte(0x13);
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uint32_t linearAddress = sectorNumber * 512;
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spiFlashByte(linearAddress >> 24);
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spiFlashByte(linearAddress >> 16);
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spiFlashByte(linearAddress >> 8);
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spiFlashByte(linearAddress);
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// There's no harm in reading -extra- data, so keep the FIFO
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// one step ahead.
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NOR_SPI_WriteTxData(0xFF);
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NOR_SPI_WriteTxData(0xFF);
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NOR_SPI_WriteTxData(0xFF);
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for (int off = 0; off < count * 512; ++off)
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{
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NOR_SPI_WriteTxData(0xFF);
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while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
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buffer[off] = NOR_SPI_ReadRxData();
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}
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// Read and discard the extra bytes of data. It was only used to improve
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// performance with a full FIFO.
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for (int i = 0; i < 3; ++i)
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{
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while (!(NOR_SPI_ReadRxStatus() & NOR_SPI_STS_RX_FIFO_NOT_EMPTY)) {}
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NOR_SPI_ReadRxData();
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}
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nNOR_CS_Write(1); // Deselect
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}
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static void spiFlash_readAsync(S2S_Device* dev, uint32_t sectorNumber, uint32_t count, uint8_t* buffer)
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{
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// SpiFlash* spiFlash = (SpiFlash*)dev;
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nNOR_CS_Write(0); // Select
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spiFlashByte(0x13);
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uint32_t linearAddress = sectorNumber * 512;
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// DMA implementation
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// send is static as the address must remain consistent for the static
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// DMA descriptors to work.
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// Size must be divisible by 2 to suit 2-byte-burst TX DMA channel.
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static uint8_t send[4] __attribute__((aligned(4)));
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send[0] = linearAddress >> 24;
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send[1] = linearAddress >> 16;
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send[2] = linearAddress >> 8;
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send[3] = linearAddress;
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// Prepare DMA transfer
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CyDmaTdSetConfiguration(spiFlashDmaTxTd[0], sizeof(send), spiFlashDmaTxTd[1], TD_INC_SRC_ADR);
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CyDmaTdSetAddress(spiFlashDmaTxTd[0], LO16((uint32)&send), LO16((uint32)NOR_SPI_TXDATA_PTR));
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CyDmaTdSetConfiguration(
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spiFlashDmaTxTd[1],
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count * 512,
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CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
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NOR_TX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
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);
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CyDmaTdSetAddress(
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spiFlashDmaTxTd[1],
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LO16((uint32)&dummyBuffer),
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LO16((uint32)NOR_SPI_TXDATA_PTR));
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CyDmaTdSetConfiguration(spiFlashDmaRxTd[0], sizeof(send), spiFlashDmaRxTd[1], 0);
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CyDmaTdSetAddress(spiFlashDmaRxTd[0], LO16((uint32)NOR_SPI_RXDATA_PTR), LO16((uint32)&discardBuffer));
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CyDmaTdSetConfiguration(
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spiFlashDmaRxTd[1],
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count * 512,
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CY_DMA_DISABLE_TD, // Disable the DMA channel when TD completes count bytes
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TD_INC_DST_ADR |
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NOR_RX_DMA__TD_TERMOUT_EN // Trigger interrupt when complete
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);
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CyDmaTdSetAddress(
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spiFlashDmaRxTd[1],
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LO16((uint32)NOR_SPI_RXDATA_PTR),
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LO16((uint32)buffer)
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);
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CyDmaChSetInitialTd(spiFlashDMATxChan, spiFlashDmaTxTd[0]);
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CyDmaChSetInitialTd(spiFlashDMARxChan, spiFlashDmaRxTd[0]);
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// The DMA controller is a bit trigger-happy. It will retain
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// a drq request that was triggered while the channel was
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// disabled.
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CyDmaChSetRequest(spiFlashDMATxChan, CY_DMA_CPU_REQ);
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CyDmaClearPendingDrq(spiFlashDMARxChan);
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spiFlashTxDMAComplete = 0;
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spiFlashRxDMAComplete = 0;
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CyDmaChEnable(spiFlashDMARxChan, 1);
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CyDmaChEnable(spiFlashDMATxChan, 1);
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}
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static int spiFlash_readAsyncPoll(S2S_Device* dev)
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{
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// SpiFlash* spiFlash = (SpiFlash*)dev;
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int allComplete = 0;
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uint8_t intr = CyEnterCriticalSection();
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allComplete = spiFlashTxDMAComplete && spiFlashRxDMAComplete;
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CyExitCriticalSection(intr);
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if (allComplete)
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{
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nNOR_CS_Write(1); // Deselect
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}
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return allComplete;
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}
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